{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 6.0 Build 178 04/27/2006 SJ Web Edition " "Info: Version 6.0 Build 178 04/27/2006 SJ Web Edition" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Thu Oct 06 16:00:33 2011 " "Info: Processing started: Thu Oct 06 16:00:33 2011" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off standard -c standard " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off standard -c standard" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Warning" "WSGN_FILE_IS_MISSING" "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/altera_europa_support.vhd " "Warning: Can't analyze file -- file D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/altera_europa_support.vhd is missing" {  } {  } 0 0 "Can't analyze file -- file %1!s! is missing" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "addroundkey.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file addroundkey.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 addroundkey-comp " "Info: Found design unit 1: addroundkey-comp" {  } { { "addroundkey.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/addroundkey.vhd" 29 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 addroundkey " "Info: Found entity 1: addroundkey" {  } { { "addroundkey.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/addroundkey.vhd" 16 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "mixcolumn.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file mixcolumn.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 mixcolumn-comp " "Info: Found design unit 1: mixcolumn-comp" {  } { { "mixcolumn.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/mixcolumn.vhd" 28 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 mixcolumn " "Info: Found entity 1: mixcolumn" {  } { { "mixcolumn.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/mixcolumn.vhd" 16 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "xor32.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file xor32.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 xor32-comp " "Info: Found design unit 1: xor32-comp" {  } { { "xor32.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/xor32.vhd" 29 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 xor32 " "Info: Found entity 1: xor32" {  } { { "xor32.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/xor32.vhd" 16 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "subbytes.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file subbytes.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 subbytes-comp " "Info: Found design unit 1: subbytes-comp" {  } { { "subbytes.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/subbytes.vhd" 31 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 subbytes " "Info: Found entity 1: subbytes" {  } { { "subbytes.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/subbytes.vhd" 18 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Warning" "WSGN_SEARCH_FILE" "standard.bdf 1 1 " "Warning: Using design file standard.bdf, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project" { { "Info" "ISGN_ENTITY_NAME" "1 standard " "Info: Found entity 1: standard" {  } { { "standard.bdf" "" { Schematic "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/standard.bdf" { } } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!d! design units and %3!d! entities in project" 0 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "standard " "Info: Elaborating entity \"standard\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0}
{ "Warning" "WSGN_SEARCH_FILE" "std_1c20.vhd 82 41 " "Warning: Using design file std_1c20.vhd, which is not specified as a design file for the current project, but contains definitions for 82 design units and 41 entities in project" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 button_pio_s1_arbitrator-europa " "Info: Found design unit 1: button_pio_s1_arbitrator-europa" {  } { { "std_1c20.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/std_1c20.vhd" 63 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_DESIGN_UNIT_NAME" "2 clock_0_in_arbitrator-europa " "Info: Found design unit 2: clock_0_in_arbitrator-europa" {  } { { "std_1c20.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/std_1c20.vhd" 274 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_DESIGN_UNIT_NAME" "3 clock_0_out_arbitrator-europa " "Info: Found design unit 3: clock_0_out_arbitrator-europa" {  } { { "std_1c20.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/std_1c20.vhd" 488 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_DESIGN_UNIT_NAME" "4 clock_1_in_arbitrator-europa " "Info: Found design unit 4: clock_1_in_arbitrator-europa" {  } { { "std_1c20.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/std_1c20.vhd" 698 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_DESIGN_UNIT_NAME" "5 clock_1_out_arbitrator-europa " "Info: Found design unit 5: clock_1_out_arbitrator-europa" {  } { { "std_1c20.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/std_1c20.vhd" 912 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_DESIGN_UNIT_NAME" "6 connector_pll_s1_arbitrator-europa " "Info: Found design unit 6: connector_pll_s1_arbitrator-europa" {  } { { "std_1c20.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/std_1c20.vhd" 1118 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_DESIGN_UNIT_NAME" "7 cpu_jtag_debug_module_arbitrator-europa " "Info: Found design unit 7: cpu_jtag_debug_module_arbitrator-europa" {  } { { "std_1c20.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/std_1c20.vhd" 1341 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_DESIGN_UNIT_NAME" "8 cpu_custom_instruction_master_arbitrator-europa " "Info: Found design unit 8: cpu_custom_instruction_master_arbitrator-europa" {  } { { "std_1c20.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/std_1c20.vhd" 1677 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_DESIGN_UNIT_NAME" "9 cpu_data_master_arbitrator-europa " "Info: Found design unit 9: cpu_data_master_arbitrator-europa" {  } { { "std_1c20.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/std_1c20.vhd" 1868 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_DESIGN_UNIT_NAME" "10 cpu_instruction_master_arbitrator-europa " "Info: Found design unit 10: cpu_instruction_master_arbitrator-europa" {  } { { "std_1c20.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/std_1c20.vhd" 2111 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_DESIGN_UNIT_NAME" "11 custominstruction1_cpu_s1_arbitrator-europa " "Info: Found design unit 11: custominstruction1_cpu_s1_arbitrator-europa" {  } { { "std_1c20.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/std_1c20.vhd" 2402 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_DESIGN_UNIT_NAME" "12 custominstruction2_cpu_s1_arbitrator-europa " "Info: Found design unit 12: custominstruction2_cpu_s1_arbitrator-europa" {  } { { "std_1c20.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/std_1c20.vhd" 2447 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_DESIGN_UNIT_NAME" "13 custominstruction3_cpu_s1_arbitrator-europa " "Info: Found design unit 13: custominstruction3_cpu_s1_arbitrator-europa" {  } { { "std_1c20.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/std_1c20.vhd" 2490 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_DESIGN_UNIT_NAME" "14 custominstruction_cpu_s1_arbitrator-europa " "Info: Found design unit 14: custominstruction_cpu_s1_arbitrator-europa" {  } { { "std_1c20.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/std_1c20.vhd" 2534 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_DESIGN_UNIT_NAME" "15 epcs_controller_epcs_control_port_arbitrator-europa " "Info: Found design unit 15: epcs_controller_epcs_control_port_arbitrator-europa" {  } { { "std_1c20.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/std_1c20.vhd" 2608 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_DESIGN_UNIT_NAME" "16 ext_ram_bus_avalon_slave_arbitrator-europa " "Info: Found design unit 16: ext_ram_bus_avalon_slave_arbitrator-europa" {  } { { "std_1c20.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/std_1c20.vhd" 3003 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_DESIGN_UNIT_NAME" "17 ext_ram_bus_bridge_arbitrator-europa " "Info: Found design unit 17: ext_ram_bus_bridge_arbitrator-europa" {  } { { "std_1c20.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/std_1c20.vhd" 4006 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_DESIGN_UNIT_NAME" "18 high_res_timer_s1_arbitrator-europa " "Info: Found design unit 18: high_res_timer_s1_arbitrator-europa" {  } { { "std_1c20.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/std_1c20.vhd" 4059 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_DESIGN_UNIT_NAME" "19 jtag_uart_avalon_jtag_slave_arbitrator-europa " "Info: Found design unit 19: jtag_uart_avalon_jtag_slave_arbitrator-europa" {  } { { "std_1c20.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/std_1c20.vhd" 4272 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_DESIGN_UNIT_NAME" "20 lcd_display_control_slave_arbitrator-europa " "Info: Found design unit 20: lcd_display_control_slave_arbitrator-europa" {  } { { "std_1c20.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/std_1c20.vhd" 4489 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_DESIGN_UNIT_NAME" "21 led_pio_s1_arbitrator-europa " "Info: Found design unit 21: led_pio_s1_arbitrator-europa" {  } { { "std_1c20.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/std_1c20.vhd" 4714 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_DESIGN_UNIT_NAME" "22 reconfig_request_pio_s1_arbitrator-europa " "Info: Found design unit 22: reconfig_request_pio_s1_arbitrator-europa" {  } { { "std_1c20.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/std_1c20.vhd" 4917 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_DESIGN_UNIT_NAME" "23 rdv_fifo_for_cpu_data_master_to_sdram_s1_module-europa " "Info: Found design unit 23: rdv_fifo_for_cpu_data_master_to_sdram_s1_module-europa" {  } { { "std_1c20.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/std_1c20.vhd" 5109 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_DESIGN_UNIT_NAME" "24 rdv_fifo_for_cpu_instruction_master_to_sdram_s1_module-europa " "Info: Found design unit 24: rdv_fifo_for_cpu_instruction_master_to_sdram_s1_module-europa" {  } { { "std_1c20.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/std_1c20.vhd" 5469 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_DESIGN_UNIT_NAME" "25 sdram_s1_arbitrator-europa " "Info: Found design unit 25: sdram_s1_arbitrator-europa" {  } { { "std_1c20.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/std_1c20.vhd" 5857 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_DESIGN_UNIT_NAME" "26 sdram_pll_s1_arbitrator-europa " "Info: Found design unit 26: sdram_pll_s1_arbitrator-europa" {  } { { "std_1c20.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/std_1c20.vhd" 6305 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_DESIGN_UNIT_NAME" "27 seven_seg_pio_s1_arbitrator-europa " "Info: Found design unit 27: seven_seg_pio_s1_arbitrator-europa" {  } { { "std_1c20.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/std_1c20.vhd" 6509 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_DESIGN_UNIT_NAME" "28 sys_clk_timer_s1_arbitrator-europa " "Info: Found design unit 28: sys_clk_timer_s1_arbitrator-europa" {  } { { "std_1c20.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/std_1c20.vhd" 6711 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_DESIGN_UNIT_NAME" "29 sysid_control_slave_arbitrator-europa " "Info: Found design unit 29: sysid_control_slave_arbitrator-europa" {  } { { "std_1c20.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/std_1c20.vhd" 6909 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_DESIGN_UNIT_NAME" "30 uart1_s1_arbitrator-europa " "Info: Found design unit 30: uart1_s1_arbitrator-europa" {  } { { "std_1c20.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/std_1c20.vhd" 7111 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_DESIGN_UNIT_NAME" "31 std_1c20_reset_sysclk2_domain_synch_module-europa " "Info: Found design unit 31: std_1c20_reset_sysclk2_domain_synch_module-europa" {  } { { "std_1c20.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/std_1c20.vhd" 7305 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_DESIGN_UNIT_NAME" "32 std_1c20_reset_PLD_CLOCKINPUT_domain_synch_module-europa " "Info: Found design unit 32: std_1c20_reset_PLD_CLOCKINPUT_domain_synch_module-europa" {  } { { "std_1c20.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/std_1c20.vhd" 7367 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_DESIGN_UNIT_NAME" "33 std_1c20_reset_PLD_CLKFB_domain_synch_module-europa " "Info: Found design unit 33: std_1c20_reset_PLD_CLKFB_domain_synch_module-europa" {  } { { "std_1c20.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/std_1c20.vhd" 7429 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_DESIGN_UNIT_NAME" "34 std_1c20-europa " "Info: Found design unit 34: std_1c20-europa" {  } { { "std_1c20.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/std_1c20.vhd" 7541 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_DESIGN_UNIT_NAME" "35 ext_flash_lane0_module-europa " "Info: Found design unit 35: ext_flash_lane0_module-europa" {  } { { "std_1c20.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/std_1c20.vhd" 10976 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_DESIGN_UNIT_NAME" "36 ext_flash-europa " "Info: Found design unit 36: ext_flash-europa" {  } { { "std_1c20.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/std_1c20.vhd" 11075 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_DESIGN_UNIT_NAME" "37 ext_ram_lane0_module-europa " "Info: Found design unit 37: ext_ram_lane0_module-europa" {  } { { "std_1c20.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/std_1c20.vhd" 11375 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_DESIGN_UNIT_NAME" "38 ext_ram_lane1_module-europa " "Info: Found design unit 38: ext_ram_lane1_module-europa" {  } { { "std_1c20.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/std_1c20.vhd" 11696 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_DESIGN_UNIT_NAME" "39 ext_ram_lane2_module-europa " "Info: Found design unit 39: ext_ram_lane2_module-europa" {  } { { "std_1c20.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/std_1c20.vhd" 12017 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_DESIGN_UNIT_NAME" "40 ext_ram_lane3_module-europa " "Info: Found design unit 40: ext_ram_lane3_module-europa" {  } { { "std_1c20.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/std_1c20.vhd" 12338 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_DESIGN_UNIT_NAME" "41 ext_ram-europa " "Info: Found design unit 41: ext_ram-europa" {  } { { "std_1c20.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/std_1c20.vhd" 12438 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 button_pio_s1_arbitrator " "Info: Found entity 1: button_pio_s1_arbitrator" {  } { { "std_1c20.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/std_1c20.vhd" 31 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "2 clock_0_in_arbitrator " "Info: Found entity 2: clock_0_in_arbitrator" {  } { { "std_1c20.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/std_1c20.vhd" 237 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "3 clock_0_out_arbitrator " "Info: Found entity 3: clock_0_out_arbitrator" {  } { { "std_1c20.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/std_1c20.vhd" 461 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "4 clock_1_in_arbitrator " "Info: Found entity 4: clock_1_in_arbitrator" {  } { { "std_1c20.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/std_1c20.vhd" 661 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "5 clock_1_out_arbitrator " "Info: Found entity 5: clock_1_out_arbitrator" {  } { { "std_1c20.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/std_1c20.vhd" 885 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "6 connector_pll_s1_arbitrator " "Info: Found entity 6: connector_pll_s1_arbitrator" {  } { { "std_1c20.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/std_1c20.vhd" 1085 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "7 cpu_jtag_debug_module_arbitrator " "Info: Found entity 7: cpu_jtag_debug_module_arbitrator" {  } { { "std_1c20.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/std_1c20.vhd" 1297 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "8 cpu_custom_instruction_master_arbitrator " "Info: Found entity 8: cpu_custom_instruction_master_arbitrator" {  } { { "std_1c20.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/std_1c20.vhd" 1653 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "9 cpu_data_master_arbitrator " "Info: Found entity 9: cpu_data_master_arbitrator" {  } { { "std_1c20.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/std_1c20.vhd" 1718 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "10 cpu_instruction_master_arbitrator " "Info: Found entity 10: cpu_instruction_master_arbitrator" {  } { { "std_1c20.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/std_1c20.vhd" 2052 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "11 custominstruction1_cpu_s1_arbitrator " "Info: Found entity 11: custominstruction1_cpu_s1_arbitrator" {  } { { "std_1c20.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/std_1c20.vhd" 2382 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "12 custominstruction2_cpu_s1_arbitrator " "Info: Found entity 12: custominstruction2_cpu_s1_arbitrator" {  } { { "std_1c20.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/std_1c20.vhd" 2427 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "13 custominstruction3_cpu_s1_arbitrator " "Info: Found entity 13: custominstruction3_cpu_s1_arbitrator" {  } { { "std_1c20.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/std_1c20.vhd" 2472 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "14 custominstruction_cpu_s1_arbitrator " "Info: Found entity 14: custominstruction_cpu_s1_arbitrator" {  } { { "std_1c20.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/std_1c20.vhd" 2514 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "15 epcs_controller_epcs_control_port_arbitrator " "Info: Found entity 15: epcs_controller_epcs_control_port_arbitrator" {  } { { "std_1c20.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/std_1c20.vhd" 2562 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "16 ext_ram_bus_avalon_slave_arbitrator " "Info: Found entity 16: ext_ram_bus_avalon_slave_arbitrator" {  } { { "std_1c20.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/std_1c20.vhd" 2926 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "17 ext_ram_bus_bridge_arbitrator " "Info: Found entity 17: ext_ram_bus_bridge_arbitrator" {  } { { "std_1c20.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/std_1c20.vhd" 4002 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "18 high_res_timer_s1_arbitrator " "Info: Found entity 18: high_res_timer_s1_arbitrator" {  } { { "std_1c20.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/std_1c20.vhd" 4027 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "19 jtag_uart_avalon_jtag_slave_arbitrator " "Info: Found entity 19: jtag_uart_avalon_jtag_slave_arbitrator" {  } { { "std_1c20.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/std_1c20.vhd" 4233 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "20 lcd_display_control_slave_arbitrator " "Info: Found entity 20: lcd_display_control_slave_arbitrator" {  } { { "std_1c20.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/std_1c20.vhd" 4457 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "21 led_pio_s1_arbitrator " "Info: Found entity 21: led_pio_s1_arbitrator" {  } { { "std_1c20.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/std_1c20.vhd" 4685 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "22 reconfig_request_pio_s1_arbitrator " "Info: Found entity 22: reconfig_request_pio_s1_arbitrator" {  } { { "std_1c20.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/std_1c20.vhd" 4887 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "23 rdv_fifo_for_cpu_data_master_to_sdram_s1_module " "Info: Found entity 23: rdv_fifo_for_cpu_data_master_to_sdram_s1_module" {  } { { "std_1c20.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/std_1c20.vhd" 5089 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "24 rdv_fifo_for_cpu_instruction_master_to_sdram_s1_module " "Info: Found entity 24: rdv_fifo_for_cpu_instruction_master_to_sdram_s1_module" {  } { { "std_1c20.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/std_1c20.vhd" 5449 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "25 sdram_s1_arbitrator " "Info: Found entity 25: sdram_s1_arbitrator" {  } { { "std_1c20.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/std_1c20.vhd" 5812 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "26 sdram_pll_s1_arbitrator " "Info: Found entity 26: sdram_pll_s1_arbitrator" {  } { { "std_1c20.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/std_1c20.vhd" 6272 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "27 seven_seg_pio_s1_arbitrator " "Info: Found entity 27: seven_seg_pio_s1_arbitrator" {  } { { "std_1c20.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/std_1c20.vhd" 6481 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "28 sys_clk_timer_s1_arbitrator " "Info: Found entity 28: sys_clk_timer_s1_arbitrator" {  } { { "std_1c20.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/std_1c20.vhd" 6679 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "29 sysid_control_slave_arbitrator " "Info: Found entity 29: sysid_control_slave_arbitrator" {  } { { "std_1c20.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/std_1c20.vhd" 6885 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "30 uart1_s1_arbitrator " "Info: Found entity 30: uart1_s1_arbitrator" {  } { { "std_1c20.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/std_1c20.vhd" 7074 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "31 std_1c20_reset_sysclk2_domain_synch_module " "Info: Found entity 31: std_1c20_reset_sysclk2_domain_synch_module" {  } { { "std_1c20.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/std_1c20.vhd" 7292 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "32 std_1c20_reset_PLD_CLOCKINPUT_domain_synch_module " "Info: Found entity 32: std_1c20_reset_PLD_CLOCKINPUT_domain_synch_module" {  } { { "std_1c20.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/std_1c20.vhd" 7354 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "33 std_1c20_reset_PLD_CLKFB_domain_synch_module " "Info: Found entity 33: std_1c20_reset_PLD_CLKFB_domain_synch_module" {  } { { "std_1c20.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/std_1c20.vhd" 7416 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "34 std_1c20 " "Info: Found entity 34: std_1c20" {  } { { "std_1c20.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/std_1c20.vhd" 7478 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "35 ext_flash_lane0_module " "Info: Found entity 35: ext_flash_lane0_module" {  } { { "std_1c20.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/std_1c20.vhd" 10960 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "36 ext_flash " "Info: Found entity 36: ext_flash" {  } { { "std_1c20.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/std_1c20.vhd" 11061 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "37 ext_ram_lane0_module " "Info: Found entity 37: ext_ram_lane0_module" {  } { { "std_1c20.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/std_1c20.vhd" 11359 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "38 ext_ram_lane1_module " "Info: Found entity 38: ext_ram_lane1_module" {  } { { "std_1c20.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/std_1c20.vhd" 11680 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "39 ext_ram_lane2_module " "Info: Found entity 39: ext_ram_lane2_module" {  } { { "std_1c20.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/std_1c20.vhd" 12001 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "40 ext_ram_lane3_module " "Info: Found entity 40: ext_ram_lane3_module" {  } { { "std_1c20.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/std_1c20.vhd" 12322 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "41 ext_ram " "Info: Found entity 41: ext_ram" {  } { { "std_1c20.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/std_1c20.vhd" 12423 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!d! design units and %3!d! entities in project" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "std_1c20 std_1c20:inst " "Info: Elaborating entity \"std_1c20\" for hierarchy \"std_1c20:inst\"" {  } { { "standard.bdf" "inst" { Schematic "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/standard.bdf" { { 560 808 1272 1296 "inst" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "button_pio_s1_arbitrator std_1c20:inst\|button_pio_s1_arbitrator:the_button_pio_s1 " "Info: Elaborating entity \"button_pio_s1_arbitrator\" for hierarchy \"std_1c20:inst\|button_pio_s1_arbitrator:the_button_pio_s1\"" {  } { { "std_1c20.vhd" "the_button_pio_s1" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/std_1c20.vhd" 9365 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Warning" "WSGN_SEARCH_FILE" "button_pio.vhd 2 1 " "Warning: Using design file button_pio.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 button_pio-europa " "Info: Found design unit 1: button_pio-europa" {  } { { "button_pio.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/button_pio.vhd" 44 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 button_pio " "Info: Found entity 1: button_pio" {  } { { "button_pio.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/button_pio.vhd" 26 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!d! design units and %3!d! entities in project" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "button_pio std_1c20:inst\|button_pio:the_button_pio " "Info: Elaborating entity \"button_pio\" for hierarchy \"std_1c20:inst\|button_pio:the_button_pio\"" {  } { { "std_1c20.vhd" "the_button_pio" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/std_1c20.vhd" 9392 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "clock_0_in_arbitrator std_1c20:inst\|clock_0_in_arbitrator:the_clock_0_in " "Info: Elaborating entity \"clock_0_in_arbitrator\" for hierarchy \"std_1c20:inst\|clock_0_in_arbitrator:the_clock_0_in\"" {  } { { "std_1c20.vhd" "the_clock_0_in" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/std_1c20.vhd" 9407 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "clock_0_out_arbitrator std_1c20:inst\|clock_0_out_arbitrator:the_clock_0_out " "Info: Elaborating entity \"clock_0_out_arbitrator\" for hierarchy \"std_1c20:inst\|clock_0_out_arbitrator:the_clock_0_out\"" {  } { { "std_1c20.vhd" "the_clock_0_out" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/std_1c20.vhd" 9439 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Warning" "WSGN_SEARCH_FILE" "clock_0.vhd 18 9 " "Warning: Using design file clock_0.vhd, which is not specified as a design file for the current project, but contains definitions for 18 design units and 9 entities in project" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 clock_0_master_read_done_sync_module-europa " "Info: Found design unit 1: clock_0_master_read_done_sync_module-europa" {  } { { "clock_0.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/clock_0.vhd" 39 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_DESIGN_UNIT_NAME" "2 clock_0_master_write_done_sync_module-europa " "Info: Found design unit 2: clock_0_master_write_done_sync_module-europa" {  } { { "clock_0.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/clock_0.vhd" 101 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_DESIGN_UNIT_NAME" "3 clock_0_edge_to_pulse-europa " "Info: Found design unit 3: clock_0_edge_to_pulse-europa" {  } { { "clock_0.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/clock_0.vhd" 163 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_DESIGN_UNIT_NAME" "4 clock_0_slave_FSM-europa " "Info: Found design unit 4: clock_0_slave_FSM-europa" {  } { { "clock_0.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/clock_0.vhd" 216 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_DESIGN_UNIT_NAME" "5 clock_0_slave_read_request_sync_module-europa " "Info: Found design unit 5: clock_0_slave_read_request_sync_module-europa" {  } { { "clock_0.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/clock_0.vhd" 356 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_DESIGN_UNIT_NAME" "6 clock_0_slave_write_request_sync_module-europa " "Info: Found design unit 6: clock_0_slave_write_request_sync_module-europa" {  } { { "clock_0.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/clock_0.vhd" 418 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_DESIGN_UNIT_NAME" "7 clock_0_master_FSM-europa " "Info: Found design unit 7: clock_0_master_FSM-europa" {  } { { "clock_0.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/clock_0.vhd" 485 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_DESIGN_UNIT_NAME" "8 clock_0_bit_pipe-europa " "Info: Found design unit 8: clock_0_bit_pipe-europa" {  } { { "clock_0.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/clock_0.vhd" 663 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_DESIGN_UNIT_NAME" "9 clock_0-europa " "Info: Found design unit 9: clock_0-europa" {  } { { "clock_0.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/clock_0.vhd" 746 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 clock_0_master_read_done_sync_module " "Info: Found entity 1: clock_0_master_read_done_sync_module" {  } { { "clock_0.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/clock_0.vhd" 26 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "2 clock_0_master_write_done_sync_module " "Info: Found entity 2: clock_0_master_write_done_sync_module" {  } { { "clock_0.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/clock_0.vhd" 88 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "3 clock_0_edge_to_pulse " "Info: Found entity 3: clock_0_edge_to_pulse" {  } { { "clock_0.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/clock_0.vhd" 150 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "4 clock_0_slave_FSM " "Info: Found entity 4: clock_0_slave_FSM" {  } { { "clock_0.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/clock_0.vhd" 198 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "5 clock_0_slave_read_request_sync_module " "Info: Found entity 5: clock_0_slave_read_request_sync_module" {  } { { "clock_0.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/clock_0.vhd" 343 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "6 clock_0_slave_write_request_sync_module " "Info: Found entity 6: clock_0_slave_write_request_sync_module" {  } { { "clock_0.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/clock_0.vhd" 405 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "7 clock_0_master_FSM " "Info: Found entity 7: clock_0_master_FSM" {  } { { "clock_0.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/clock_0.vhd" 467 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "8 clock_0_bit_pipe " "Info: Found entity 8: clock_0_bit_pipe" {  } { { "clock_0.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/clock_0.vhd" 648 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "9 clock_0 " "Info: Found entity 9: clock_0" {  } { { "clock_0.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/clock_0.vhd" 715 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!d! design units and %3!d! entities in project" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "clock_0 std_1c20:inst\|clock_0:the_clock_0 " "Info: Elaborating entity \"clock_0\" for hierarchy \"std_1c20:inst\|clock_0:the_clock_0\"" {  } { { "std_1c20.vhd" "the_clock_0" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/std_1c20.vhd" 9461 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "clock_0_master_read_done_sync_module std_1c20:inst\|clock_0:the_clock_0\|clock_0_master_read_done_sync_module:clock_0_master_read_done_sync " "Info: Elaborating entity \"clock_0_master_read_done_sync_module\" for hierarchy \"std_1c20:inst\|clock_0:the_clock_0\|clock_0_master_read_done_sync_module:clock_0_master_read_done_sync\"" {  } { { "clock_0.vhd" "clock_0_master_read_done_sync" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/clock_0.vhd" 892 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "clock_0_master_write_done_sync_module std_1c20:inst\|clock_0:the_clock_0\|clock_0_master_write_done_sync_module:clock_0_master_write_done_sync " "Info: Elaborating entity \"clock_0_master_write_done_sync_module\" for hierarchy \"std_1c20:inst\|clock_0:the_clock_0\|clock_0_master_write_done_sync_module:clock_0_master_write_done_sync\"" {  } { { "clock_0.vhd" "clock_0_master_write_done_sync" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/clock_0.vhd" 902 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "clock_0_edge_to_pulse std_1c20:inst\|clock_0:the_clock_0\|clock_0_edge_to_pulse:read_done_edge_to_pulse " "Info: Elaborating entity \"clock_0_edge_to_pulse\" for hierarchy \"std_1c20:inst\|clock_0:the_clock_0\|clock_0_edge_to_pulse:read_done_edge_to_pulse\"" {  } { { "clock_0.vhd" "read_done_edge_to_pulse" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/clock_0.vhd" 912 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "clock_0_slave_FSM std_1c20:inst\|clock_0:the_clock_0\|clock_0_slave_FSM:slave_FSM " "Info: Elaborating entity \"clock_0_slave_FSM\" for hierarchy \"std_1c20:inst\|clock_0:the_clock_0\|clock_0_slave_FSM:slave_FSM\"" {  } { { "clock_0.vhd" "slave_FSM" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/clock_0.vhd" 932 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "clock_0_slave_read_request_sync_module std_1c20:inst\|clock_0:the_clock_0\|clock_0_slave_read_request_sync_module:clock_0_slave_read_request_sync " "Info: Elaborating entity \"clock_0_slave_read_request_sync_module\" for hierarchy \"std_1c20:inst\|clock_0:the_clock_0\|clock_0_slave_read_request_sync_module:clock_0_slave_read_request_sync\"" {  } { { "clock_0.vhd" "clock_0_slave_read_request_sync" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/clock_0.vhd" 947 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "clock_0_slave_write_request_sync_module std_1c20:inst\|clock_0:the_clock_0\|clock_0_slave_write_request_sync_module:clock_0_slave_write_request_sync " "Info: Elaborating entity \"clock_0_slave_write_request_sync_module\" for hierarchy \"std_1c20:inst\|clock_0:the_clock_0\|clock_0_slave_write_request_sync_module:clock_0_slave_write_request_sync\"" {  } { { "clock_0.vhd" "clock_0_slave_write_request_sync" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/clock_0.vhd" 957 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "clock_0_master_FSM std_1c20:inst\|clock_0:the_clock_0\|clock_0_master_FSM:master_FSM " "Info: Elaborating entity \"clock_0_master_FSM\" for hierarchy \"std_1c20:inst\|clock_0:the_clock_0\|clock_0_master_FSM:master_FSM\"" {  } { { "clock_0.vhd" "master_FSM" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/clock_0.vhd" 987 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "clock_0_bit_pipe std_1c20:inst\|clock_0:the_clock_0\|clock_0_bit_pipe:endofpacket_bit_pipe " "Info: Elaborating entity \"clock_0_bit_pipe\" for hierarchy \"std_1c20:inst\|clock_0:the_clock_0\|clock_0_bit_pipe:endofpacket_bit_pipe\"" {  } { { "clock_0.vhd" "endofpacket_bit_pipe" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/clock_0.vhd" 1002 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "clock_1_in_arbitrator std_1c20:inst\|clock_1_in_arbitrator:the_clock_1_in " "Info: Elaborating entity \"clock_1_in_arbitrator\" for hierarchy \"std_1c20:inst\|clock_1_in_arbitrator:the_clock_1_in\"" {  } { { "std_1c20.vhd" "the_clock_1_in" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/std_1c20.vhd" 9489 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "clock_1_out_arbitrator std_1c20:inst\|clock_1_out_arbitrator:the_clock_1_out " "Info: Elaborating entity \"clock_1_out_arbitrator\" for hierarchy \"std_1c20:inst\|clock_1_out_arbitrator:the_clock_1_out\"" {  } { { "std_1c20.vhd" "the_clock_1_out" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/std_1c20.vhd" 9521 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Warning" "WSGN_SEARCH_FILE" "clock_1.vhd 18 9 " "Warning: Using design file clock_1.vhd, which is not specified as a design file for the current project, but contains definitions for 18 design units and 9 entities in project" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 clock_1_master_read_done_sync_module-europa " "Info: Found design unit 1: clock_1_master_read_done_sync_module-europa" {  } { { "clock_1.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/clock_1.vhd" 39 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_DESIGN_UNIT_NAME" "2 clock_1_master_write_done_sync_module-europa " "Info: Found design unit 2: clock_1_master_write_done_sync_module-europa" {  } { { "clock_1.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/clock_1.vhd" 101 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_DESIGN_UNIT_NAME" "3 clock_1_edge_to_pulse-europa " "Info: Found design unit 3: clock_1_edge_to_pulse-europa" {  } { { "clock_1.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/clock_1.vhd" 163 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_DESIGN_UNIT_NAME" "4 clock_1_slave_FSM-europa " "Info: Found design unit 4: clock_1_slave_FSM-europa" {  } { { "clock_1.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/clock_1.vhd" 216 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_DESIGN_UNIT_NAME" "5 clock_1_slave_read_request_sync_module-europa " "Info: Found design unit 5: clock_1_slave_read_request_sync_module-europa" {  } { { "clock_1.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/clock_1.vhd" 356 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_DESIGN_UNIT_NAME" "6 clock_1_slave_write_request_sync_module-europa " "Info: Found design unit 6: clock_1_slave_write_request_sync_module-europa" {  } { { "clock_1.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/clock_1.vhd" 418 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_DESIGN_UNIT_NAME" "7 clock_1_master_FSM-europa " "Info: Found design unit 7: clock_1_master_FSM-europa" {  } { { "clock_1.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/clock_1.vhd" 485 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_DESIGN_UNIT_NAME" "8 clock_1_bit_pipe-europa " "Info: Found design unit 8: clock_1_bit_pipe-europa" {  } { { "clock_1.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/clock_1.vhd" 663 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_DESIGN_UNIT_NAME" "9 clock_1-europa " "Info: Found design unit 9: clock_1-europa" {  } { { "clock_1.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/clock_1.vhd" 746 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 clock_1_master_read_done_sync_module " "Info: Found entity 1: clock_1_master_read_done_sync_module" {  } { { "clock_1.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/clock_1.vhd" 26 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "2 clock_1_master_write_done_sync_module " "Info: Found entity 2: clock_1_master_write_done_sync_module" {  } { { "clock_1.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/clock_1.vhd" 88 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "3 clock_1_edge_to_pulse " "Info: Found entity 3: clock_1_edge_to_pulse" {  } { { "clock_1.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/clock_1.vhd" 150 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "4 clock_1_slave_FSM " "Info: Found entity 4: clock_1_slave_FSM" {  } { { "clock_1.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/clock_1.vhd" 198 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "5 clock_1_slave_read_request_sync_module " "Info: Found entity 5: clock_1_slave_read_request_sync_module" {  } { { "clock_1.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/clock_1.vhd" 343 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "6 clock_1_slave_write_request_sync_module " "Info: Found entity 6: clock_1_slave_write_request_sync_module" {  } { { "clock_1.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/clock_1.vhd" 405 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "7 clock_1_master_FSM " "Info: Found entity 7: clock_1_master_FSM" {  } { { "clock_1.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/clock_1.vhd" 467 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "8 clock_1_bit_pipe " "Info: Found entity 8: clock_1_bit_pipe" {  } { { "clock_1.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/clock_1.vhd" 648 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "9 clock_1 " "Info: Found entity 9: clock_1" {  } { { "clock_1.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/clock_1.vhd" 715 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!d! design units and %3!d! entities in project" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "clock_1 std_1c20:inst\|clock_1:the_clock_1 " "Info: Elaborating entity \"clock_1\" for hierarchy \"std_1c20:inst\|clock_1:the_clock_1\"" {  } { { "std_1c20.vhd" "the_clock_1" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/std_1c20.vhd" 9543 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "clock_1_master_read_done_sync_module std_1c20:inst\|clock_1:the_clock_1\|clock_1_master_read_done_sync_module:clock_1_master_read_done_sync " "Info: Elaborating entity \"clock_1_master_read_done_sync_module\" for hierarchy \"std_1c20:inst\|clock_1:the_clock_1\|clock_1_master_read_done_sync_module:clock_1_master_read_done_sync\"" {  } { { "clock_1.vhd" "clock_1_master_read_done_sync" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/clock_1.vhd" 892 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "clock_1_master_write_done_sync_module std_1c20:inst\|clock_1:the_clock_1\|clock_1_master_write_done_sync_module:clock_1_master_write_done_sync " "Info: Elaborating entity \"clock_1_master_write_done_sync_module\" for hierarchy \"std_1c20:inst\|clock_1:the_clock_1\|clock_1_master_write_done_sync_module:clock_1_master_write_done_sync\"" {  } { { "clock_1.vhd" "clock_1_master_write_done_sync" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/clock_1.vhd" 902 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "clock_1_edge_to_pulse std_1c20:inst\|clock_1:the_clock_1\|clock_1_edge_to_pulse:read_done_edge_to_pulse " "Info: Elaborating entity \"clock_1_edge_to_pulse\" for hierarchy \"std_1c20:inst\|clock_1:the_clock_1\|clock_1_edge_to_pulse:read_done_edge_to_pulse\"" {  } { { "clock_1.vhd" "read_done_edge_to_pulse" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/clock_1.vhd" 912 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "clock_1_slave_FSM std_1c20:inst\|clock_1:the_clock_1\|clock_1_slave_FSM:slave_FSM " "Info: Elaborating entity \"clock_1_slave_FSM\" for hierarchy \"std_1c20:inst\|clock_1:the_clock_1\|clock_1_slave_FSM:slave_FSM\"" {  } { { "clock_1.vhd" "slave_FSM" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/clock_1.vhd" 932 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "clock_1_slave_read_request_sync_module std_1c20:inst\|clock_1:the_clock_1\|clock_1_slave_read_request_sync_module:clock_1_slave_read_request_sync " "Info: Elaborating entity \"clock_1_slave_read_request_sync_module\" for hierarchy \"std_1c20:inst\|clock_1:the_clock_1\|clock_1_slave_read_request_sync_module:clock_1_slave_read_request_sync\"" {  } { { "clock_1.vhd" "clock_1_slave_read_request_sync" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/clock_1.vhd" 947 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "clock_1_slave_write_request_sync_module std_1c20:inst\|clock_1:the_clock_1\|clock_1_slave_write_request_sync_module:clock_1_slave_write_request_sync " "Info: Elaborating entity \"clock_1_slave_write_request_sync_module\" for hierarchy \"std_1c20:inst\|clock_1:the_clock_1\|clock_1_slave_write_request_sync_module:clock_1_slave_write_request_sync\"" {  } { { "clock_1.vhd" "clock_1_slave_write_request_sync" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/clock_1.vhd" 957 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "clock_1_master_FSM std_1c20:inst\|clock_1:the_clock_1\|clock_1_master_FSM:master_FSM " "Info: Elaborating entity \"clock_1_master_FSM\" for hierarchy \"std_1c20:inst\|clock_1:the_clock_1\|clock_1_master_FSM:master_FSM\"" {  } { { "clock_1.vhd" "master_FSM" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/clock_1.vhd" 987 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "clock_1_bit_pipe std_1c20:inst\|clock_1:the_clock_1\|clock_1_bit_pipe:endofpacket_bit_pipe " "Info: Elaborating entity \"clock_1_bit_pipe\" for hierarchy \"std_1c20:inst\|clock_1:the_clock_1\|clock_1_bit_pipe:endofpacket_bit_pipe\"" {  } { { "clock_1.vhd" "endofpacket_bit_pipe" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/clock_1.vhd" 1002 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "connector_pll_s1_arbitrator std_1c20:inst\|connector_pll_s1_arbitrator:the_connector_pll_s1 " "Info: Elaborating entity \"connector_pll_s1_arbitrator\" for hierarchy \"std_1c20:inst\|connector_pll_s1_arbitrator:the_connector_pll_s1\"" {  } { { "std_1c20.vhd" "the_connector_pll_s1" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/std_1c20.vhd" 9571 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Warning" "WSGN_SEARCH_FILE" "connector_pll.vhd 2 1 " "Warning: Using design file connector_pll.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 connector_pll-europa " "Info: Found design unit 1: connector_pll-europa" {  } { { "connector_pll.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/connector_pll.vhd" 52 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 connector_pll " "Info: Found entity 1: connector_pll" {  } { { "connector_pll.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/connector_pll.vhd" 32 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!d! design units and %3!d! entities in project" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "connector_pll std_1c20:inst\|connector_pll:the_connector_pll " "Info: Elaborating entity \"connector_pll\" for hierarchy \"std_1c20:inst\|connector_pll:the_connector_pll\"" {  } { { "std_1c20.vhd" "the_connector_pll" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/std_1c20.vhd" 9599 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "reset_input1 connector_pll.vhd(176) " "Warning (10492): VHDL Process Statement warning at connector_pll.vhd(176): signal \"reset_input1\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "connector_pll.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/connector_pll.vhd" 176 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" 0 0}
{ "Warning" "WSGN_SEARCH_FILE" "altpllconnector_pll.vhd 2 1 " "Warning: Using design file altpllconnector_pll.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 altpllconnector_pll-SYN " "Info: Found design unit 1: altpllconnector_pll-SYN" {  } { { "altpllconnector_pll.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/altpllconnector_pll.vhd" 49 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 altpllconnector_pll " "Info: Found entity 1: altpllconnector_pll" {  } { { "altpllconnector_pll.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/altpllconnector_pll.vhd" 39 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!d! design units and %3!d! entities in project" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altpllconnector_pll std_1c20:inst\|connector_pll:the_connector_pll\|altpllconnector_pll:the_pll " "Info: Elaborating entity \"altpllconnector_pll\" for hierarchy \"std_1c20:inst\|connector_pll:the_connector_pll\|altpllconnector_pll:the_pll\"" {  } { { "connector_pll.vhd" "the_pll" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/connector_pll.vhd" 145 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "../../../../quartus60/libraries/megafunctions/altpll.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file ../../../../quartus60/libraries/megafunctions/altpll.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altpll " "Info: Found entity 1: altpll" {  } { { "altpll.tdf" "" { Text "d:/altera/quartus60/libraries/megafunctions/altpll.tdf" 365 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altpll std_1c20:inst\|connector_pll:the_connector_pll\|altpllconnector_pll:the_pll\|altpll:altpll_component " "Info: Elaborating entity \"altpll\" for hierarchy \"std_1c20:inst\|connector_pll:the_connector_pll\|altpllconnector_pll:the_pll\|altpll:altpll_component\"" {  } { { "altpllconnector_pll.vhd" "altpll_component" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/altpllconnector_pll.vhd" 137 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_ELABORATION_HEADER" "std_1c20:inst\|connector_pll:the_connector_pll\|altpllconnector_pll:the_pll\|altpll:altpll_component " "Info: Elaborated megafunction instantiation \"std_1c20:inst\|connector_pll:the_connector_pll\|altpllconnector_pll:the_pll\|altpll:altpll_component\"" {  } { { "altpllconnector_pll.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/altpllconnector_pll.vhd" 137 -1 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "cpu_jtag_debug_module_arbitrator std_1c20:inst\|cpu_jtag_debug_module_arbitrator:the_cpu_jtag_debug_module " "Info: Elaborating entity \"cpu_jtag_debug_module_arbitrator\" for hierarchy \"std_1c20:inst\|cpu_jtag_debug_module_arbitrator:the_cpu_jtag_debug_module\"" {  } { { "std_1c20.vhd" "the_cpu_jtag_debug_module" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/std_1c20.vhd" 9616 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "cpu_custom_instruction_master_arbitrator std_1c20:inst\|cpu_custom_instruction_master_arbitrator:the_cpu_custom_instruction_master " "Info: Elaborating entity \"cpu_custom_instruction_master_arbitrator\" for hierarchy \"std_1c20:inst\|cpu_custom_instruction_master_arbitrator:the_cpu_custom_instruction_master\"" {  } { { "std_1c20.vhd" "the_cpu_custom_instruction_master" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/std_1c20.vhd" 9655 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "cpu_data_master_arbitrator std_1c20:inst\|cpu_data_master_arbitrator:the_cpu_data_master " "Info: Elaborating entity \"cpu_data_master_arbitrator\" for hierarchy \"std_1c20:inst\|cpu_data_master_arbitrator:the_cpu_data_master\"" {  } { { "std_1c20.vhd" "the_cpu_data_master" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/std_1c20.vhd" 9674 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "cpu_instruction_master_arbitrator std_1c20:inst\|cpu_instruction_master_arbitrator:the_cpu_instruction_master " "Info: Elaborating entity \"cpu_instruction_master_arbitrator\" for hierarchy \"std_1c20:inst\|cpu_instruction_master_arbitrator:the_cpu_instruction_master\"" {  } { { "std_1c20.vhd" "the_cpu_instruction_master" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/std_1c20.vhd" 9819 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Warning" "WSGN_SEARCH_FILE" "cpu.vhd 52 26 " "Warning: Using design file cpu.vhd, which is not specified as a design file for the current project, but contains definitions for 52 design units and 26 entities in project" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 cpu_ic_data_module-europa " "Info: Found design unit 1: cpu_ic_data_module-europa" {  } { { "cpu.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/cpu.vhd" 52 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_DESIGN_UNIT_NAME" "2 cpu_ic_tag_module-europa " "Info: Found design unit 2: cpu_ic_tag_module-europa" {  } { { "cpu.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/cpu.vhd" 219 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_DESIGN_UNIT_NAME" "3 cpu_register_bank_a_module-europa " "Info: Found design unit 3: cpu_register_bank_a_module-europa" {  } { { "cpu.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/cpu.vhd" 390 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_DESIGN_UNIT_NAME" "4 cpu_register_bank_b_module-europa " "Info: Found design unit 4: cpu_register_bank_b_module-europa" {  } { { "cpu.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/cpu.vhd" 561 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_DESIGN_UNIT_NAME" "5 cpu_nios2_oci_debug-europa " "Info: Found design unit 5: cpu_nios2_oci_debug-europa" {  } { { "cpu.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/cpu.vhd" 735 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_DESIGN_UNIT_NAME" "6 cpu_ociram_lpm_dram_bdp_component_module-europa " "Info: Found design unit 6: cpu_ociram_lpm_dram_bdp_component_module-europa" {  } { { "cpu.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/cpu.vhd" 845 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_DESIGN_UNIT_NAME" "7 cpu_nios2_ocimem-europa " "Info: Found design unit 7: cpu_nios2_ocimem-europa" {  } { { "cpu.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/cpu.vhd" 983 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_DESIGN_UNIT_NAME" "8 cpu_nios2_avalon_reg-europa " "Info: Found design unit 8: cpu_nios2_avalon_reg-europa" {  } { { "cpu.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/cpu.vhd" 1142 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_DESIGN_UNIT_NAME" "9 cpu_nios2_oci_break-europa " "Info: Found design unit 9: cpu_nios2_oci_break-europa" {  } { { "cpu.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/cpu.vhd" 1258 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_DESIGN_UNIT_NAME" "10 cpu_nios2_oci_xbrk-europa " "Info: Found design unit 10: cpu_nios2_oci_xbrk-europa" {  } { { "cpu.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/cpu.vhd" 1711 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_DESIGN_UNIT_NAME" "11 cpu_nios2_oci_match_paired-europa " "Info: Found design unit 11: cpu_nios2_oci_match_paired-europa" {  } { { "cpu.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/cpu.vhd" 1908 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_DESIGN_UNIT_NAME" "12 cpu_nios2_oci_match_single-europa " "Info: Found design unit 12: cpu_nios2_oci_match_single-europa" {  } { { "cpu.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/cpu.vhd" 1947 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_DESIGN_UNIT_NAME" "13 cpu_nios2_oci_dbrk-europa " "Info: Found design unit 13: cpu_nios2_oci_dbrk-europa" {  } { { "cpu.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/cpu.vhd" 2013 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_DESIGN_UNIT_NAME" "14 cpu_nios2_oci_itrace-europa " "Info: Found design unit 14: cpu_nios2_oci_itrace-europa" {  } { { "cpu.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/cpu.vhd" 2266 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_DESIGN_UNIT_NAME" "15 cpu_nios2_oci_td_mode-europa " "Info: Found design unit 15: cpu_nios2_oci_td_mode-europa" {  } { { "cpu.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/cpu.vhd" 2468 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_DESIGN_UNIT_NAME" "16 cpu_nios2_oci_dtrace-europa " "Info: Found design unit 16: cpu_nios2_oci_dtrace-europa" {  } { { "cpu.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/cpu.vhd" 2553 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_DESIGN_UNIT_NAME" "17 cpu_nios2_oci_compute_tm_count-europa " "Info: Found design unit 17: cpu_nios2_oci_compute_tm_count-europa" {  } { { "cpu.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/cpu.vhd" 2648 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_DESIGN_UNIT_NAME" "18 cpu_nios2_oci_fifowp_inc-europa " "Info: Found design unit 18: cpu_nios2_oci_fifowp_inc-europa" {  } { { "cpu.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/cpu.vhd" 2726 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_DESIGN_UNIT_NAME" "19 cpu_nios2_oci_fifocount_inc-europa " "Info: Found design unit 19: cpu_nios2_oci_fifocount_inc-europa" {  } { { "cpu.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/cpu.vhd" 2775 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_DESIGN_UNIT_NAME" "20 cpu_nios2_oci_fifo-europa " "Info: Found design unit 20: cpu_nios2_oci_fifo-europa" {  } { { "cpu.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/cpu.vhd" 2832 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_DESIGN_UNIT_NAME" "21 cpu_nios2_oci_pib-europa " "Info: Found design unit 21: cpu_nios2_oci_pib-europa" {  } { { "cpu.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/cpu.vhd" 3272 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_DESIGN_UNIT_NAME" "22 cpu_traceram_lpm_dram_bdp_component_module-europa " "Info: Found design unit 22: cpu_traceram_lpm_dram_bdp_component_module-europa" {  } { { "cpu.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/cpu.vhd" 3355 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_DESIGN_UNIT_NAME" "23 cpu_nios2_oci_im-europa " "Info: Found design unit 23: cpu_nios2_oci_im-europa" {  } { { "cpu.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/cpu.vhd" 3490 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_DESIGN_UNIT_NAME" "24 cpu_nios2_performance_monitors-europa " "Info: Found design unit 24: cpu_nios2_performance_monitors-europa" {  } { { "cpu.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/cpu.vhd" 3629 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_DESIGN_UNIT_NAME" "25 cpu_nios2_oci-europa " "Info: Found design unit 25: cpu_nios2_oci-europa" {  } { { "cpu.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/cpu.vhd" 3703 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_DESIGN_UNIT_NAME" "26 cpu-europa " "Info: Found design unit 26: cpu-europa" {  } { { "cpu.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/cpu.vhd" 4574 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 cpu_ic_data_module " "Info: Found entity 1: cpu_ic_data_module" {  } { { "cpu.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/cpu.vhd" 32 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "2 cpu_ic_tag_module " "Info: Found entity 2: cpu_ic_tag_module" {  } { { "cpu.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/cpu.vhd" 199 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "3 cpu_register_bank_a_module " "Info: Found entity 3: cpu_register_bank_a_module" {  } { { "cpu.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/cpu.vhd" 370 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "4 cpu_register_bank_b_module " "Info: Found entity 4: cpu_register_bank_b_module" {  } { { "cpu.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/cpu.vhd" 541 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "5 cpu_nios2_oci_debug " "Info: Found entity 5: cpu_nios2_oci_debug" {  } { { "cpu.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/cpu.vhd" 706 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "6 cpu_ociram_lpm_dram_bdp_component_module " "Info: Found entity 6: cpu_ociram_lpm_dram_bdp_component_module" {  } { { "cpu.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/cpu.vhd" 820 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "7 cpu_nios2_ocimem " "Info: Found entity 7: cpu_nios2_ocimem" {  } { { "cpu.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/cpu.vhd" 958 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "8 cpu_nios2_avalon_reg " "Info: Found entity 8: cpu_nios2_avalon_reg" {  } { { "cpu.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/cpu.vhd" 1117 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "9 cpu_nios2_oci_break " "Info: Found entity 9: cpu_nios2_oci_break" {  } { { "cpu.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/cpu.vhd" 1210 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "10 cpu_nios2_oci_xbrk " "Info: Found entity 10: cpu_nios2_oci_xbrk" {  } { { "cpu.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/cpu.vhd" 1680 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "11 cpu_nios2_oci_match_paired " "Info: Found entity 11: cpu_nios2_oci_match_paired" {  } { { "cpu.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/cpu.vhd" 1892 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "12 cpu_nios2_oci_match_single " "Info: Found entity 12: cpu_nios2_oci_match_single" {  } { { "cpu.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/cpu.vhd" 1932 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "13 cpu_nios2_oci_dbrk " "Info: Found entity 13: cpu_nios2_oci_dbrk" {  } { { "cpu.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/cpu.vhd" 1971 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "14 cpu_nios2_oci_itrace " "Info: Found entity 14: cpu_nios2_oci_itrace" {  } { { "cpu.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/cpu.vhd" 2223 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "15 cpu_nios2_oci_td_mode " "Info: Found entity 15: cpu_nios2_oci_td_mode" {  } { { "cpu.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/cpu.vhd" 2457 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "16 cpu_nios2_oci_dtrace " "Info: Found entity 16: cpu_nios2_oci_dtrace" {  } { { "cpu.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/cpu.vhd" 2533 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "17 cpu_nios2_oci_compute_tm_count " "Info: Found entity 17: cpu_nios2_oci_compute_tm_count" {  } { { "cpu.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/cpu.vhd" 2635 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "18 cpu_nios2_oci_fifowp_inc " "Info: Found entity 18: cpu_nios2_oci_fifowp_inc" {  } { { "cpu.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/cpu.vhd" 2713 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "19 cpu_nios2_oci_fifocount_inc " "Info: Found entity 19: cpu_nios2_oci_fifocount_inc" {  } { { "cpu.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/cpu.vhd" 2761 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "20 cpu_nios2_oci_fifo " "Info: Found entity 20: cpu_nios2_oci_fifo" {  } { { "cpu.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/cpu.vhd" 2812 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "21 cpu_nios2_oci_pib " "Info: Found entity 21: cpu_nios2_oci_pib" {  } { { "cpu.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/cpu.vhd" 3257 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "22 cpu_traceram_lpm_dram_bdp_component_module " "Info: Found entity 22: cpu_traceram_lpm_dram_bdp_component_module" {  } { { "cpu.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/cpu.vhd" 3331 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "23 cpu_nios2_oci_im " "Info: Found entity 23: cpu_nios2_oci_im" {  } { { "cpu.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/cpu.vhd" 3464 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "24 cpu_nios2_performance_monitors " "Info: Found entity 24: cpu_nios2_performance_monitors" {  } { { "cpu.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/cpu.vhd" 3625 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "25 cpu_nios2_oci " "Info: Found entity 25: cpu_nios2_oci" {  } { { "cpu.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/cpu.vhd" 3650 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "26 cpu " "Info: Found entity 26: cpu" {  } { { "cpu.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/cpu.vhd" 4525 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!d! design units and %3!d! entities in project" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "cpu std_1c20:inst\|cpu:the_cpu " "Info: Elaborating entity \"cpu\" for hierarchy \"std_1c20:inst\|cpu:the_cpu\"" {  } { { "std_1c20.vhd" "the_cpu" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/std_1c20.vhd" 9873 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Warning" "WSGN_SEARCH_FILE" "cpu_test_bench.vhd 2 1 " "Warning: Using design file cpu_test_bench.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 cpu_test_bench-europa " "Info: Found design unit 1: cpu_test_bench-europa" {  } { { "cpu_test_bench.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/cpu_test_bench.vhd" 80 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 cpu_test_bench " "Info: Found entity 1: cpu_test_bench" {  } { { "cpu_test_bench.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/cpu_test_bench.vhd" 29 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!d! design units and %3!d! entities in project" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "cpu_test_bench std_1c20:inst\|cpu:the_cpu\|cpu_test_bench:the_cpu_test_bench " "Info: Elaborating entity \"cpu_test_bench\" for hierarchy \"std_1c20:inst\|cpu:the_cpu\|cpu_test_bench:the_cpu_test_bench\"" {  } { { "cpu.vhd" "the_cpu_test_bench" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/cpu.vhd" 5902 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "cpu_ic_data_module std_1c20:inst\|cpu:the_cpu\|cpu_ic_data_module:cpu_ic_data " "Info: Elaborating entity \"cpu_ic_data_module\" for hierarchy \"std_1c20:inst\|cpu:the_cpu\|cpu_ic_data_module:cpu_ic_data\"" {  } { { "cpu.vhd" "cpu_ic_data" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/cpu.vhd" 6804 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "../../../../quartus60/libraries/megafunctions/altsyncram.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file ../../../../quartus60/libraries/megafunctions/altsyncram.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram " "Info: Found entity 1: altsyncram" {  } { { "altsyncram.tdf" "" { Text "d:/altera/quartus60/libraries/megafunctions/altsyncram.tdf" 426 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram std_1c20:inst\|cpu:the_cpu\|cpu_ic_data_module:cpu_ic_data\|altsyncram:the_altsyncram " "Info: Elaborating entity \"altsyncram\" for hierarchy \"std_1c20:inst\|cpu:the_cpu\|cpu_ic_data_module:cpu_ic_data\|altsyncram:the_altsyncram\"" {  } { { "cpu.vhd" "the_altsyncram" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/cpu.vhd" 148 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_ELABORATION_HEADER" "std_1c20:inst\|cpu:the_cpu\|cpu_ic_data_module:cpu_ic_data\|altsyncram:the_altsyncram " "Info: Elaborated megafunction instantiation \"std_1c20:inst\|cpu:the_cpu\|cpu_ic_data_module:cpu_ic_data\|altsyncram:the_altsyncram\"" {  } { { "cpu.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/cpu.vhd" 148 -1 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_qmb1.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/altsyncram_qmb1.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_qmb1 " "Info: Found entity 1: altsyncram_qmb1" {  } { { "db/altsyncram_qmb1.tdf" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/db/altsyncram_qmb1.tdf" 36 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram_qmb1 std_1c20:inst\|cpu:the_cpu\|cpu_ic_data_module:cpu_ic_data\|altsyncram:the_altsyncram\|altsyncram_qmb1:auto_generated " "Info: Elaborating entity \"altsyncram_qmb1\" for hierarchy \"std_1c20:inst\|cpu:the_cpu\|cpu_ic_data_module:cpu_ic_data\|altsyncram:the_altsyncram\|altsyncram_qmb1:auto_generated\"" {  } { { "altsyncram.tdf" "auto_generated" { Text "d:/altera/quartus60/libraries/megafunctions/altsyncram.tdf" 905 4 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "cpu_ic_tag_module std_1c20:inst\|cpu:the_cpu\|cpu_ic_tag_module:cpu_ic_tag " "Info: Elaborating entity \"cpu_ic_tag_module\" for hierarchy \"std_1c20:inst\|cpu:the_cpu\|cpu_ic_tag_module:cpu_ic_tag\"" {  } { { "cpu.vhd" "cpu_ic_tag" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/cpu.vhd" 6877 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram std_1c20:inst\|cpu:the_cpu\|cpu_ic_tag_module:cpu_ic_tag\|altsyncram:the_altsyncram " "Info: Elaborating entity \"altsyncram\" for hierarchy \"std_1c20:inst\|cpu:the_cpu\|cpu_ic_tag_module:cpu_ic_tag\|altsyncram:the_altsyncram\"" {  } { { "cpu.vhd" "the_altsyncram" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/cpu.vhd" 318 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_ELABORATION_HEADER" "std_1c20:inst\|cpu:the_cpu\|cpu_ic_tag_module:cpu_ic_tag\|altsyncram:the_altsyncram " "Info: Elaborated megafunction instantiation \"std_1c20:inst\|cpu:the_cpu\|cpu_ic_tag_module:cpu_ic_tag\|altsyncram:the_altsyncram\"" {  } { { "cpu.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/cpu.vhd" 318 -1 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_09e1.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/altsyncram_09e1.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_09e1 " "Info: Found entity 1: altsyncram_09e1" {  } { { "db/altsyncram_09e1.tdf" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/db/altsyncram_09e1.tdf" 36 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram_09e1 std_1c20:inst\|cpu:the_cpu\|cpu_ic_tag_module:cpu_ic_tag\|altsyncram:the_altsyncram\|altsyncram_09e1:auto_generated " "Info: Elaborating entity \"altsyncram_09e1\" for hierarchy \"std_1c20:inst\|cpu:the_cpu\|cpu_ic_tag_module:cpu_ic_tag\|altsyncram:the_altsyncram\|altsyncram_09e1:auto_generated\"" {  } { { "altsyncram.tdf" "auto_generated" { Text "d:/altera/quartus60/libraries/megafunctions/altsyncram.tdf" 905 4 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "cpu_register_bank_a_module std_1c20:inst\|cpu:the_cpu\|cpu_register_bank_a_module:cpu_register_bank_a " "Info: Elaborating entity \"cpu_register_bank_a_module\" for hierarchy \"std_1c20:inst\|cpu:the_cpu\|cpu_register_bank_a_module:cpu_register_bank_a\"" {  } { { "cpu.vhd" "cpu_register_bank_a" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/cpu.vhd" 7488 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram std_1c20:inst\|cpu:the_cpu\|cpu_register_bank_a_module:cpu_register_bank_a\|altsyncram:the_altsyncram " "Info: Elaborating entity \"altsyncram\" for hierarchy \"std_1c20:inst\|cpu:the_cpu\|cpu_register_bank_a_module:cpu_register_bank_a\|altsyncram:the_altsyncram\"" {  } { { "cpu.vhd" "the_altsyncram" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/cpu.vhd" 489 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_ELABORATION_HEADER" "std_1c20:inst\|cpu:the_cpu\|cpu_register_bank_a_module:cpu_register_bank_a\|altsyncram:the_altsyncram " "Info: Elaborated megafunction instantiation \"std_1c20:inst\|cpu:the_cpu\|cpu_register_bank_a_module:cpu_register_bank_a\|altsyncram:the_altsyncram\"" {  } { { "cpu.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/cpu.vhd" 489 -1 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_3vd1.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/altsyncram_3vd1.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_3vd1 " "Info: Found entity 1: altsyncram_3vd1" {  } { { "db/altsyncram_3vd1.tdf" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/db/altsyncram_3vd1.tdf" 36 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram_3vd1 std_1c20:inst\|cpu:the_cpu\|cpu_register_bank_a_module:cpu_register_bank_a\|altsyncram:the_altsyncram\|altsyncram_3vd1:auto_generated " "Info: Elaborating entity \"altsyncram_3vd1\" for hierarchy \"std_1c20:inst\|cpu:the_cpu\|cpu_register_bank_a_module:cpu_register_bank_a\|altsyncram:the_altsyncram\|altsyncram_3vd1:auto_generated\"" {  } { { "altsyncram.tdf" "auto_generated" { Text "d:/altera/quartus60/libraries/megafunctions/altsyncram.tdf" 905 4 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "cpu_register_bank_b_module std_1c20:inst\|cpu:the_cpu\|cpu_register_bank_b_module:cpu_register_bank_b " "Info: Elaborating entity \"cpu_register_bank_b_module\" for hierarchy \"std_1c20:inst\|cpu:the_cpu\|cpu_register_bank_b_module:cpu_register_bank_b\"" {  } { { "cpu.vhd" "cpu_register_bank_b" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/cpu.vhd" 7505 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram std_1c20:inst\|cpu:the_cpu\|cpu_register_bank_b_module:cpu_register_bank_b\|altsyncram:the_altsyncram " "Info: Elaborating entity \"altsyncram\" for hierarchy \"std_1c20:inst\|cpu:the_cpu\|cpu_register_bank_b_module:cpu_register_bank_b\|altsyncram:the_altsyncram\"" {  } { { "cpu.vhd" "the_altsyncram" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/cpu.vhd" 660 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_ELABORATION_HEADER" "std_1c20:inst\|cpu:the_cpu\|cpu_register_bank_b_module:cpu_register_bank_b\|altsyncram:the_altsyncram " "Info: Elaborated megafunction instantiation \"std_1c20:inst\|cpu:the_cpu\|cpu_register_bank_b_module:cpu_register_bank_b\|altsyncram:the_altsyncram\"" {  } { { "cpu.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/cpu.vhd" 660 -1 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_4vd1.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/altsyncram_4vd1.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_4vd1 " "Info: Found entity 1: altsyncram_4vd1" {  } { { "db/altsyncram_4vd1.tdf" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/db/altsyncram_4vd1.tdf" 36 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram_4vd1 std_1c20:inst\|cpu:the_cpu\|cpu_register_bank_b_module:cpu_register_bank_b\|altsyncram:the_altsyncram\|altsyncram_4vd1:auto_generated " "Info: Elaborating entity \"altsyncram_4vd1\" for hierarchy \"std_1c20:inst\|cpu:the_cpu\|cpu_register_bank_b_module:cpu_register_bank_b\|altsyncram:the_altsyncram\|altsyncram_4vd1:auto_generated\"" {  } { { "altsyncram.tdf" "auto_generated" { Text "d:/altera/quartus60/libraries/megafunctions/altsyncram.tdf" 905 4 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "cpu_nios2_oci std_1c20:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci " "Info: Elaborating entity \"cpu_nios2_oci\" for hierarchy \"std_1c20:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\"" {  } { { "cpu.vhd" "the_cpu_nios2_oci" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/cpu.vhd" 7884 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "cpu_nios2_oci_debug std_1c20:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_oci_debug:the_cpu_nios2_oci_debug " "Info: Elaborating entity \"cpu_nios2_oci_debug\" for hierarchy \"std_1c20:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_oci_debug:the_cpu_nios2_oci_debug\"" {  } { { "cpu.vhd" "the_cpu_nios2_oci_debug" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/cpu.vhd" 4161 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "cpu_nios2_ocimem std_1c20:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_ocimem:the_cpu_nios2_ocimem " "Info: Elaborating entity \"cpu_nios2_ocimem\" for hierarchy \"std_1c20:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_ocimem:the_cpu_nios2_ocimem\"" {  } { { "cpu.vhd" "the_cpu_nios2_ocimem" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/cpu.vhd" 4187 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "cpu_ociram_lpm_dram_bdp_component_module std_1c20:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_ocimem:the_cpu_nios2_ocimem\|cpu_ociram_lpm_dram_bdp_component_module:cpu_ociram_lpm_dram_bdp_component " "Info: Elaborating entity \"cpu_ociram_lpm_dram_bdp_component_module\" for hierarchy \"std_1c20:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_ocimem:the_cpu_nios2_ocimem\|cpu_ociram_lpm_dram_bdp_component_module:cpu_ociram_lpm_dram_bdp_component\"" {  } { { "cpu.vhd" "cpu_ociram_lpm_dram_bdp_component" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/cpu.vhd" 1068 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram std_1c20:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_ocimem:the_cpu_nios2_ocimem\|cpu_ociram_lpm_dram_bdp_component_module:cpu_ociram_lpm_dram_bdp_component\|altsyncram:the_altsyncram " "Info: Elaborating entity \"altsyncram\" for hierarchy \"std_1c20:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_ocimem:the_cpu_nios2_ocimem\|cpu_ociram_lpm_dram_bdp_component_module:cpu_ociram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\"" {  } { { "cpu.vhd" "the_altsyncram" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/cpu.vhd" 894 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_ELABORATION_HEADER" "std_1c20:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_ocimem:the_cpu_nios2_ocimem\|cpu_ociram_lpm_dram_bdp_component_module:cpu_ociram_lpm_dram_bdp_component\|altsyncram:the_altsyncram " "Info: Elaborated megafunction instantiation \"std_1c20:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_ocimem:the_cpu_nios2_ocimem\|cpu_ociram_lpm_dram_bdp_component_module:cpu_ociram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\"" {  } { { "cpu.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/cpu.vhd" 894 -1 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_bp62.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/altsyncram_bp62.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_bp62 " "Info: Found entity 1: altsyncram_bp62" {  } { { "db/altsyncram_bp62.tdf" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/db/altsyncram_bp62.tdf" 36 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram_bp62 std_1c20:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_ocimem:the_cpu_nios2_ocimem\|cpu_ociram_lpm_dram_bdp_component_module:cpu_ociram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_bp62:auto_generated " "Info: Elaborating entity \"altsyncram_bp62\" for hierarchy \"std_1c20:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_ocimem:the_cpu_nios2_ocimem\|cpu_ociram_lpm_dram_bdp_component_module:cpu_ociram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_bp62:auto_generated\"" {  } { { "altsyncram.tdf" "auto_generated" { Text "d:/altera/quartus60/libraries/megafunctions/altsyncram.tdf" 905 4 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "cpu_nios2_avalon_reg std_1c20:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_avalon_reg:the_cpu_nios2_avalon_reg " "Info: Elaborating entity \"cpu_nios2_avalon_reg\" for hierarchy \"std_1c20:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_avalon_reg:the_cpu_nios2_avalon_reg\"" {  } { { "cpu.vhd" "the_cpu_nios2_avalon_reg" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/cpu.vhd" 4209 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "cpu_nios2_oci_break std_1c20:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_oci_break:the_cpu_nios2_oci_break " "Info: Elaborating entity \"cpu_nios2_oci_break\" for hierarchy \"std_1c20:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_oci_break:the_cpu_nios2_oci_break\"" {  } { { "cpu.vhd" "the_cpu_nios2_oci_break" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/cpu.vhd" 4231 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "cpu_nios2_oci_xbrk std_1c20:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_oci_xbrk:the_cpu_nios2_oci_xbrk " "Info: Elaborating entity \"cpu_nios2_oci_xbrk\" for hierarchy \"std_1c20:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_oci_xbrk:the_cpu_nios2_oci_xbrk\"" {  } { { "cpu.vhd" "the_cpu_nios2_oci_xbrk" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/cpu.vhd" 4276 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "cpu_nios2_oci_dbrk std_1c20:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_oci_dbrk:the_cpu_nios2_oci_dbrk " "Info: Elaborating entity \"cpu_nios2_oci_dbrk\" for hierarchy \"std_1c20:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_oci_dbrk:the_cpu_nios2_oci_dbrk\"" {  } { { "cpu.vhd" "the_cpu_nios2_oci_dbrk" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/cpu.vhd" 4304 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "cpu_nios2_oci_match_paired std_1c20:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_oci_dbrk:the_cpu_nios2_oci_dbrk\|cpu_nios2_oci_match_paired:cpu_nios2_oci_dbrk_hit0_match_paired " "Info: Elaborating entity \"cpu_nios2_oci_match_paired\" for hierarchy \"std_1c20:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_oci_dbrk:the_cpu_nios2_oci_dbrk\|cpu_nios2_oci_match_paired:cpu_nios2_oci_dbrk_hit0_match_paired\"" {  } { { "cpu.vhd" "cpu_nios2_oci_dbrk_hit0_match_paired" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/cpu.vhd" 2079 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "cpu_nios2_oci_match_single std_1c20:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_oci_dbrk:the_cpu_nios2_oci_dbrk\|cpu_nios2_oci_match_single:cpu_nios2_oci_dbrk_hit0_match_single " "Info: Elaborating entity \"cpu_nios2_oci_match_single\" for hierarchy \"std_1c20:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_oci_dbrk:the_cpu_nios2_oci_dbrk\|cpu_nios2_oci_match_single:cpu_nios2_oci_dbrk_hit0_match_single\"" {  } { { "cpu.vhd" "cpu_nios2_oci_dbrk_hit0_match_single" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/cpu.vhd" 2092 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "cpu_nios2_oci_itrace std_1c20:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_oci_itrace:the_cpu_nios2_oci_itrace " "Info: Elaborating entity \"cpu_nios2_oci_itrace\" for hierarchy \"std_1c20:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_oci_itrace:the_cpu_nios2_oci_itrace\"" {  } { { "cpu.vhd" "the_cpu_nios2_oci_itrace" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/cpu.vhd" 4343 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "cpu_nios2_oci_dtrace std_1c20:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_oci_dtrace:the_cpu_nios2_oci_dtrace " "Info: Elaborating entity \"cpu_nios2_oci_dtrace\" for hierarchy \"std_1c20:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_oci_dtrace:the_cpu_nios2_oci_dtrace\"" {  } { { "cpu.vhd" "the_cpu_nios2_oci_dtrace" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/cpu.vhd" 4383 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "cpu_nios2_oci_td_mode std_1c20:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_oci_dtrace:the_cpu_nios2_oci_dtrace\|cpu_nios2_oci_td_mode:cpu_nios2_oci_trc_ctrl_td_mode " "Info: Elaborating entity \"cpu_nios2_oci_td_mode\" for hierarchy \"std_1c20:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_oci_dtrace:the_cpu_nios2_oci_dtrace\|cpu_nios2_oci_td_mode:cpu_nios2_oci_trc_ctrl_td_mode\"" {  } { { "cpu.vhd" "cpu_nios2_oci_trc_ctrl_td_mode" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/cpu.vhd" 2580 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "cpu_nios2_oci_fifo std_1c20:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_oci_fifo:the_cpu_nios2_oci_fifo " "Info: Elaborating entity \"cpu_nios2_oci_fifo\" for hierarchy \"std_1c20:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_oci_fifo:the_cpu_nios2_oci_fifo\"" {  } { { "cpu.vhd" "the_cpu_nios2_oci_fifo" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/cpu.vhd" 4400 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "cpu_nios2_oci_compute_tm_count std_1c20:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_oci_fifo:the_cpu_nios2_oci_fifo\|cpu_nios2_oci_compute_tm_count:cpu_nios2_oci_compute_tm_count_tm_count " "Info: Elaborating entity \"cpu_nios2_oci_compute_tm_count\" for hierarchy \"std_1c20:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_oci_fifo:the_cpu_nios2_oci_fifo\|cpu_nios2_oci_compute_tm_count:cpu_nios2_oci_compute_tm_count_tm_count\"" {  } { { "cpu.vhd" "cpu_nios2_oci_compute_tm_count_tm_count" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/cpu.vhd" 2955 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "cpu_nios2_oci_fifowp_inc std_1c20:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_oci_fifo:the_cpu_nios2_oci_fifo\|cpu_nios2_oci_fifowp_inc:cpu_nios2_oci_fifowp_inc_fifowp " "Info: Elaborating entity \"cpu_nios2_oci_fifowp_inc\" for hierarchy \"std_1c20:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_oci_fifo:the_cpu_nios2_oci_fifo\|cpu_nios2_oci_fifowp_inc:cpu_nios2_oci_fifowp_inc_fifowp\"" {  } { { "cpu.vhd" "cpu_nios2_oci_fifowp_inc_fifowp" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/cpu.vhd" 2966 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "cpu_nios2_oci_fifocount_inc std_1c20:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_oci_fifo:the_cpu_nios2_oci_fifo\|cpu_nios2_oci_fifocount_inc:cpu_nios2_oci_fifocount_inc_fifocount " "Info: Elaborating entity \"cpu_nios2_oci_fifocount_inc\" for hierarchy \"std_1c20:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_oci_fifo:the_cpu_nios2_oci_fifo\|cpu_nios2_oci_fifocount_inc:cpu_nios2_oci_fifocount_inc_fifocount\"" {  } { { "cpu.vhd" "cpu_nios2_oci_fifocount_inc_fifocount" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/cpu.vhd" 2976 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "cpu_nios2_oci_pib std_1c20:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_oci_pib:the_cpu_nios2_oci_pib " "Info: Elaborating entity \"cpu_nios2_oci_pib\" for hierarchy \"std_1c20:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_oci_pib:the_cpu_nios2_oci_pib\"" {  } { { "cpu.vhd" "the_cpu_nios2_oci_pib" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/cpu.vhd" 4417 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "cpu_nios2_oci_im std_1c20:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_oci_im:the_cpu_nios2_oci_im " "Info: Elaborating entity \"cpu_nios2_oci_im\" for hierarchy \"std_1c20:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_oci_im:the_cpu_nios2_oci_im\"" {  } { { "cpu.vhd" "the_cpu_nios2_oci_im" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/cpu.vhd" 4429 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "cpu_traceram_lpm_dram_bdp_component_module std_1c20:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_oci_im:the_cpu_nios2_oci_im\|cpu_traceram_lpm_dram_bdp_component_module:cpu_traceram_lpm_dram_bdp_component " "Info: Elaborating entity \"cpu_traceram_lpm_dram_bdp_component_module\" for hierarchy \"std_1c20:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_oci_im:the_cpu_nios2_oci_im\|cpu_traceram_lpm_dram_bdp_component_module:cpu_traceram_lpm_dram_bdp_component\"" {  } { { "cpu.vhd" "cpu_traceram_lpm_dram_bdp_component" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/cpu.vhd" 3563 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram std_1c20:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_oci_im:the_cpu_nios2_oci_im\|cpu_traceram_lpm_dram_bdp_component_module:cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram " "Info: Elaborating entity \"altsyncram\" for hierarchy \"std_1c20:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_oci_im:the_cpu_nios2_oci_im\|cpu_traceram_lpm_dram_bdp_component_module:cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\"" {  } { { "cpu.vhd" "the_altsyncram" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/cpu.vhd" 3402 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_ELABORATION_HEADER" "std_1c20:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_oci_im:the_cpu_nios2_oci_im\|cpu_traceram_lpm_dram_bdp_component_module:cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram " "Info: Elaborated megafunction instantiation \"std_1c20:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_oci_im:the_cpu_nios2_oci_im\|cpu_traceram_lpm_dram_bdp_component_module:cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\"" {  } { { "cpu.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/cpu.vhd" 3402 -1 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_stv1.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/altsyncram_stv1.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_stv1 " "Info: Found entity 1: altsyncram_stv1" {  } { { "db/altsyncram_stv1.tdf" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/db/altsyncram_stv1.tdf" 36 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram_stv1 std_1c20:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_oci_im:the_cpu_nios2_oci_im\|cpu_traceram_lpm_dram_bdp_component_module:cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_stv1:auto_generated " "Info: Elaborating entity \"altsyncram_stv1\" for hierarchy \"std_1c20:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_oci_im:the_cpu_nios2_oci_im\|cpu_traceram_lpm_dram_bdp_component_module:cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_stv1:auto_generated\"" {  } { { "altsyncram.tdf" "auto_generated" { Text "d:/altera/quartus60/libraries/megafunctions/altsyncram.tdf" 905 4 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Warning" "WSGN_SEARCH_FILE" "cpu_jtag_debug_module_wrapper.vhd 2 1 " "Warning: Using design file cpu_jtag_debug_module_wrapper.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 cpu_jtag_debug_module_wrapper-europa " "Info: Found design unit 1: cpu_jtag_debug_module_wrapper-europa" {  } { { "cpu_jtag_debug_module_wrapper.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/cpu_jtag_debug_module_wrapper.vhd" 71 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 cpu_jtag_debug_module_wrapper " "Info: Found entity 1: cpu_jtag_debug_module_wrapper" {  } { { "cpu_jtag_debug_module_wrapper.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/cpu_jtag_debug_module_wrapper.vhd" 26 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!d! design units and %3!d! entities in project" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "cpu_jtag_debug_module_wrapper std_1c20:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper " "Info: Elaborating entity \"cpu_jtag_debug_module_wrapper\" for hierarchy \"std_1c20:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper\"" {  } { { "cpu.vhd" "the_cpu_jtag_debug_module_wrapper" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/cpu.vhd" 4455 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Warning" "WSGN_SEARCH_FILE" "cpu_jtag_debug_module.vhd 2 1 " "Warning: Using design file cpu_jtag_debug_module.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 cpu_jtag_debug_module-europa " "Info: Found design unit 1: cpu_jtag_debug_module-europa" {  } { { "cpu_jtag_debug_module.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/cpu_jtag_debug_module.vhd" 87 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 cpu_jtag_debug_module " "Info: Found entity 1: cpu_jtag_debug_module" {  } { { "cpu_jtag_debug_module.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/cpu_jtag_debug_module.vhd" 26 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!d! design units and %3!d! entities in project" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "cpu_jtag_debug_module std_1c20:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper\|cpu_jtag_debug_module:the_cpu_jtag_debug_module1 " "Info: Elaborating entity \"cpu_jtag_debug_module\" for hierarchy \"std_1c20:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper\|cpu_jtag_debug_module:the_cpu_jtag_debug_module1\"" {  } { { "cpu_jtag_debug_module_wrapper.vhd" "the_cpu_jtag_debug_module1" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/cpu_jtag_debug_module_wrapper.vhd" 305 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "usr1 cpu_jtag_debug_module.vhd(254) " "Warning (10492): VHDL Process Statement warning at cpu_jtag_debug_module.vhd(254): signal \"usr1\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "cpu_jtag_debug_module.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/cpu_jtag_debug_module.vhd" 254 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "ena cpu_jtag_debug_module.vhd(254) " "Warning (10492): VHDL Process Statement warning at cpu_jtag_debug_module.vhd(254): signal \"ena\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "cpu_jtag_debug_module.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/cpu_jtag_debug_module.vhd" 254 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "usr1 cpu_jtag_debug_module.vhd(257) " "Warning (10492): VHDL Process Statement warning at cpu_jtag_debug_module.vhd(257): signal \"usr1\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "cpu_jtag_debug_module.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/cpu_jtag_debug_module.vhd" 257 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "ena cpu_jtag_debug_module.vhd(257) " "Warning (10492): VHDL Process Statement warning at cpu_jtag_debug_module.vhd(257): signal \"ena\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "cpu_jtag_debug_module.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/cpu_jtag_debug_module.vhd" 257 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "custominstruction1_cpu_s1_arbitrator std_1c20:inst\|custominstruction1_cpu_s1_arbitrator:the_custominstruction1_cpu_s1 " "Info: Elaborating entity \"custominstruction1_cpu_s1_arbitrator\" for hierarchy \"std_1c20:inst\|custominstruction1_cpu_s1_arbitrator:the_custominstruction1_cpu_s1\"" {  } { { "std_1c20.vhd" "the_custominstruction1_cpu_s1" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/std_1c20.vhd" 9919 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Warning" "WSGN_SEARCH_FILE" "custominstruction1_cpu.vhd 2 1 " "Warning: Using design file custominstruction1_cpu.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 custominstruction1_cpu-europa " "Info: Found design unit 1: custominstruction1_cpu-europa" {  } { { "custominstruction1_cpu.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/custominstruction1_cpu.vhd" 38 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 custominstruction1_cpu " "Info: Found entity 1: custominstruction1_cpu" {  } { { "custominstruction1_cpu.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/custominstruction1_cpu.vhd" 26 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!d! design units and %3!d! entities in project" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "custominstruction1_cpu std_1c20:inst\|custominstruction1_cpu:the_custominstruction1_cpu " "Info: Elaborating entity \"custominstruction1_cpu\" for hierarchy \"std_1c20:inst\|custominstruction1_cpu:the_custominstruction1_cpu\"" {  } { { "std_1c20.vhd" "the_custominstruction1_cpu" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/std_1c20.vhd" 9934 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "subbytes std_1c20:inst\|custominstruction1_cpu:the_custominstruction1_cpu\|subbytes:the_subbytes " "Info: Elaborating entity \"subbytes\" for hierarchy \"std_1c20:inst\|custominstruction1_cpu:the_custominstruction1_cpu\|subbytes:the_subbytes\"" {  } { { "custominstruction1_cpu.vhd" "the_subbytes" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/custominstruction1_cpu.vhd" 56 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Warning" "WVRFX_VHDL_USED_EXPLICIT_DEFAULT_VALUE" "sbox subbytes.vhd(35) " "Warning (10540): VHDL Signal Declaration warning at subbytes.vhd(35): used explicit default value for signal \"sbox\" because signal was never assigned a value" {  } { { "subbytes.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/subbytes.vhd" 35 0 0 } }  } 0 10540 "VHDL Signal Declaration warning at %2!s!: used explicit default value for signal \"%1!s!\" because signal was never assigned a value" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "custominstruction2_cpu_s1_arbitrator std_1c20:inst\|custominstruction2_cpu_s1_arbitrator:the_custominstruction2_cpu_s1 " "Info: Elaborating entity \"custominstruction2_cpu_s1_arbitrator\" for hierarchy \"std_1c20:inst\|custominstruction2_cpu_s1_arbitrator:the_custominstruction2_cpu_s1\"" {  } { { "std_1c20.vhd" "the_custominstruction2_cpu_s1" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/std_1c20.vhd" 9943 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Warning" "WSGN_SEARCH_FILE" "custominstruction2_cpu.vhd 2 1 " "Warning: Using design file custominstruction2_cpu.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 custominstruction2_cpu-europa " "Info: Found design unit 1: custominstruction2_cpu-europa" {  } { { "custominstruction2_cpu.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/custominstruction2_cpu.vhd" 38 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 custominstruction2_cpu " "Info: Found entity 1: custominstruction2_cpu" {  } { { "custominstruction2_cpu.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/custominstruction2_cpu.vhd" 26 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!d! design units and %3!d! entities in project" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "custominstruction2_cpu std_1c20:inst\|custominstruction2_cpu:the_custominstruction2_cpu " "Info: Elaborating entity \"custominstruction2_cpu\" for hierarchy \"std_1c20:inst\|custominstruction2_cpu:the_custominstruction2_cpu\"" {  } { { "std_1c20.vhd" "the_custominstruction2_cpu" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/std_1c20.vhd" 9958 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "addroundkey std_1c20:inst\|custominstruction2_cpu:the_custominstruction2_cpu\|addroundkey:the_addroundkey " "Info: Elaborating entity \"addroundkey\" for hierarchy \"std_1c20:inst\|custominstruction2_cpu:the_custominstruction2_cpu\|addroundkey:the_addroundkey\"" {  } { { "custominstruction2_cpu.vhd" "the_addroundkey" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/custominstruction2_cpu.vhd" 56 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "custominstruction3_cpu_s1_arbitrator std_1c20:inst\|custominstruction3_cpu_s1_arbitrator:the_custominstruction3_cpu_s1 " "Info: Elaborating entity \"custominstruction3_cpu_s1_arbitrator\" for hierarchy \"std_1c20:inst\|custominstruction3_cpu_s1_arbitrator:the_custominstruction3_cpu_s1\"" {  } { { "std_1c20.vhd" "the_custominstruction3_cpu_s1" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/std_1c20.vhd" 9967 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Warning" "WSGN_SEARCH_FILE" "custominstruction3_cpu.vhd 2 1 " "Warning: Using design file custominstruction3_cpu.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 custominstruction3_cpu-europa " "Info: Found design unit 1: custominstruction3_cpu-europa" {  } { { "custominstruction3_cpu.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/custominstruction3_cpu.vhd" 37 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 custominstruction3_cpu " "Info: Found entity 1: custominstruction3_cpu" {  } { { "custominstruction3_cpu.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/custominstruction3_cpu.vhd" 26 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!d! design units and %3!d! entities in project" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "custominstruction3_cpu std_1c20:inst\|custominstruction3_cpu:the_custominstruction3_cpu " "Info: Elaborating entity \"custominstruction3_cpu\" for hierarchy \"std_1c20:inst\|custominstruction3_cpu:the_custominstruction3_cpu\"" {  } { { "std_1c20.vhd" "the_custominstruction3_cpu" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/std_1c20.vhd" 9980 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "mixcolumn std_1c20:inst\|custominstruction3_cpu:the_custominstruction3_cpu\|mixcolumn:the_mixcolumn " "Info: Elaborating entity \"mixcolumn\" for hierarchy \"std_1c20:inst\|custominstruction3_cpu:the_custominstruction3_cpu\|mixcolumn:the_mixcolumn\"" {  } { { "custominstruction3_cpu.vhd" "the_mixcolumn" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/custominstruction3_cpu.vhd" 54 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "custominstruction_cpu_s1_arbitrator std_1c20:inst\|custominstruction_cpu_s1_arbitrator:the_custominstruction_cpu_s1 " "Info: Elaborating entity \"custominstruction_cpu_s1_arbitrator\" for hierarchy \"std_1c20:inst\|custominstruction_cpu_s1_arbitrator:the_custominstruction_cpu_s1\"" {  } { { "std_1c20.vhd" "the_custominstruction_cpu_s1" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/std_1c20.vhd" 9988 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Warning" "WSGN_SEARCH_FILE" "custominstruction_cpu.vhd 2 1 " "Warning: Using design file custominstruction_cpu.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 custominstruction_cpu-europa " "Info: Found design unit 1: custominstruction_cpu-europa" {  } { { "custominstruction_cpu.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/custominstruction_cpu.vhd" 38 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 custominstruction_cpu " "Info: Found entity 1: custominstruction_cpu" {  } { { "custominstruction_cpu.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/custominstruction_cpu.vhd" 26 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!d! design units and %3!d! entities in project" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "custominstruction_cpu std_1c20:inst\|custominstruction_cpu:the_custominstruction_cpu " "Info: Elaborating entity \"custominstruction_cpu\" for hierarchy \"std_1c20:inst\|custominstruction_cpu:the_custominstruction_cpu\"" {  } { { "std_1c20.vhd" "the_custominstruction_cpu" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/std_1c20.vhd" 10003 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "xor32 std_1c20:inst\|custominstruction_cpu:the_custominstruction_cpu\|xor32:the_xor32 " "Info: Elaborating entity \"xor32\" for hierarchy \"std_1c20:inst\|custominstruction_cpu:the_custominstruction_cpu\|xor32:the_xor32\"" {  } { { "custominstruction_cpu.vhd" "the_xor32" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/custominstruction_cpu.vhd" 56 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "epcs_controller_epcs_control_port_arbitrator std_1c20:inst\|epcs_controller_epcs_control_port_arbitrator:the_epcs_controller_epcs_control_port " "Info: Elaborating entity \"epcs_controller_epcs_control_port_arbitrator\" for hierarchy \"std_1c20:inst\|epcs_controller_epcs_control_port_arbitrator:the_epcs_controller_epcs_control_port\"" {  } { { "std_1c20.vhd" "the_epcs_controller_epcs_control_port" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/std_1c20.vhd" 10012 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Warning" "WSGN_SEARCH_FILE" "epcs_controller.vhd 6 3 " "Warning: Using design file epcs_controller.vhd, which is not specified as a design file for the current project, but contains definitions for 6 design units and 3 entities in project" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 epcs_controller_sub-europa " "Info: Found design unit 1: epcs_controller_sub-europa" {  } { { "epcs_controller.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/epcs_controller.vhd" 71 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_DESIGN_UNIT_NAME" "2 tornado_epcs_controller_atom-europa " "Info: Found design unit 2: tornado_epcs_controller_atom-europa" {  } { { "epcs_controller.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/epcs_controller.vhd" 466 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_DESIGN_UNIT_NAME" "3 epcs_controller-europa " "Info: Found design unit 3: epcs_controller-europa" {  } { { "epcs_controller.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/epcs_controller.vhd" 541 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 epcs_controller_sub " "Info: Found entity 1: epcs_controller_sub" {  } { { "epcs_controller.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/epcs_controller.vhd" 46 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "2 tornado_epcs_controller_atom " "Info: Found entity 2: tornado_epcs_controller_atom" {  } { { "epcs_controller.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/epcs_controller.vhd" 452 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "3 epcs_controller " "Info: Found entity 3: epcs_controller" {  } { { "epcs_controller.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/epcs_controller.vhd" 520 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!d! design units and %3!d! entities in project" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "epcs_controller std_1c20:inst\|epcs_controller:the_epcs_controller " "Info: Elaborating entity \"epcs_controller\" for hierarchy \"std_1c20:inst\|epcs_controller:the_epcs_controller\"" {  } { { "std_1c20.vhd" "the_epcs_controller" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/std_1c20.vhd" 10053 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "epcs_controller_sub std_1c20:inst\|epcs_controller:the_epcs_controller\|epcs_controller_sub:the_epcs_controller_sub " "Info: Elaborating entity \"epcs_controller_sub\" for hierarchy \"std_1c20:inst\|epcs_controller:the_epcs_controller\|epcs_controller_sub:the_epcs_controller_sub\"" {  } { { "epcs_controller.vhd" "the_epcs_controller_sub" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/epcs_controller.vhd" 637 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "tornado_epcs_controller_atom std_1c20:inst\|epcs_controller:the_epcs_controller\|tornado_epcs_controller_atom:the_tornado_epcs_controller_atom " "Info: Elaborating entity \"tornado_epcs_controller_atom\" for hierarchy \"std_1c20:inst\|epcs_controller:the_epcs_controller\|tornado_epcs_controller_atom:the_tornado_epcs_controller_atom\"" {  } { { "epcs_controller.vhd" "the_tornado_epcs_controller_atom" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/epcs_controller.vhd" 660 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram std_1c20:inst\|epcs_controller:the_epcs_controller\|altsyncram:the_boot_copier_rom " "Info: Elaborating entity \"altsyncram\" for hierarchy \"std_1c20:inst\|epcs_controller:the_epcs_controller\|altsyncram:the_boot_copier_rom\"" {  } { { "epcs_controller.vhd" "the_boot_copier_rom" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/epcs_controller.vhd" 704 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_ELABORATION_HEADER" "std_1c20:inst\|epcs_controller:the_epcs_controller\|altsyncram:the_boot_copier_rom " "Info: Elaborated megafunction instantiation \"std_1c20:inst\|epcs_controller:the_epcs_controller\|altsyncram:the_boot_copier_rom\"" {  } { { "epcs_controller.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/epcs_controller.vhd" 704 -1 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_3h31.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/altsyncram_3h31.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_3h31 " "Info: Found entity 1: altsyncram_3h31" {  } { { "db/altsyncram_3h31.tdf" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/db/altsyncram_3h31.tdf" 36 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram_3h31 std_1c20:inst\|epcs_controller:the_epcs_controller\|altsyncram:the_boot_copier_rom\|altsyncram_3h31:auto_generated " "Info: Elaborating entity \"altsyncram_3h31\" for hierarchy \"std_1c20:inst\|epcs_controller:the_epcs_controller\|altsyncram:the_boot_copier_rom\|altsyncram_3h31:auto_generated\"" {  } { { "altsyncram.tdf" "auto_generated" { Text "d:/altera/quartus60/libraries/megafunctions/altsyncram.tdf" 905 4 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "ext_ram_bus_avalon_slave_arbitrator std_1c20:inst\|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave " "Info: Elaborating entity \"ext_ram_bus_avalon_slave_arbitrator\" for hierarchy \"std_1c20:inst\|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave\"" {  } { { "std_1c20.vhd" "the_ext_ram_bus_avalon_slave" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/std_1c20.vhd" 10071 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "high_res_timer_s1_arbitrator std_1c20:inst\|high_res_timer_s1_arbitrator:the_high_res_timer_s1 " "Info: Elaborating entity \"high_res_timer_s1_arbitrator\" for hierarchy \"std_1c20:inst\|high_res_timer_s1_arbitrator:the_high_res_timer_s1\"" {  } { { "std_1c20.vhd" "the_high_res_timer_s1" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/std_1c20.vhd" 10143 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Warning" "WSGN_SEARCH_FILE" "high_res_timer.vhd 2 1 " "Warning: Using design file high_res_timer.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 high_res_timer-europa " "Info: Found design unit 1: high_res_timer-europa" {  } { { "high_res_timer.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/high_res_timer.vhd" 43 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 high_res_timer " "Info: Found entity 1: high_res_timer" {  } { { "high_res_timer.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/high_res_timer.vhd" 26 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!d! design units and %3!d! entities in project" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "high_res_timer std_1c20:inst\|high_res_timer:the_high_res_timer " "Info: Elaborating entity \"high_res_timer\" for hierarchy \"std_1c20:inst\|high_res_timer:the_high_res_timer\"" {  } { { "std_1c20.vhd" "the_high_res_timer" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/std_1c20.vhd" 10170 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "jtag_uart_avalon_jtag_slave_arbitrator std_1c20:inst\|jtag_uart_avalon_jtag_slave_arbitrator:the_jtag_uart_avalon_jtag_slave " "Info: Elaborating entity \"jtag_uart_avalon_jtag_slave_arbitrator\" for hierarchy \"std_1c20:inst\|jtag_uart_avalon_jtag_slave_arbitrator:the_jtag_uart_avalon_jtag_slave\"" {  } { { "std_1c20.vhd" "the_jtag_uart_avalon_jtag_slave" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/std_1c20.vhd" 10184 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Warning" "WSGN_SEARCH_FILE" "jtag_uart.vhd 14 7 " "Warning: Using design file jtag_uart.vhd, which is not specified as a design file for the current project, but contains definitions for 14 design units and 7 entities in project" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 jtag_uart_log_module-europa " "Info: Found design unit 1: jtag_uart_log_module-europa" {  } { { "jtag_uart.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/jtag_uart.vhd" 40 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_DESIGN_UNIT_NAME" "2 jtag_uart_sim_scfifo_w-europa " "Info: Found design unit 2: jtag_uart_sim_scfifo_w-europa" {  } { { "jtag_uart.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/jtag_uart.vhd" 237 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_DESIGN_UNIT_NAME" "3 jtag_uart_scfifo_w-europa " "Info: Found design unit 3: jtag_uart_scfifo_w-europa" {  } { { "jtag_uart.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/jtag_uart.vhd" 310 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_DESIGN_UNIT_NAME" "4 jtag_uart_drom_module-europa " "Info: Found design unit 4: jtag_uart_drom_module-europa" {  } { { "jtag_uart.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/jtag_uart.vhd" 449 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_DESIGN_UNIT_NAME" "5 jtag_uart_sim_scfifo_r-europa " "Info: Found design unit 5: jtag_uart_sim_scfifo_r-europa" {  } { { "jtag_uart.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/jtag_uart.vhd" 835 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_DESIGN_UNIT_NAME" "6 jtag_uart_scfifo_r-europa " "Info: Found design unit 6: jtag_uart_scfifo_r-europa" {  } { { "jtag_uart.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/jtag_uart.vhd" 952 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_DESIGN_UNIT_NAME" "7 jtag_uart-europa " "Info: Found design unit 7: jtag_uart-europa" {  } { { "jtag_uart.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/jtag_uart.vhd" 1096 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 jtag_uart_log_module " "Info: Found entity 1: jtag_uart_log_module" {  } { { "jtag_uart.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/jtag_uart.vhd" 29 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "2 jtag_uart_sim_scfifo_w " "Info: Found entity 2: jtag_uart_sim_scfifo_w" {  } { { "jtag_uart.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/jtag_uart.vhd" 221 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "3 jtag_uart_scfifo_w " "Info: Found entity 3: jtag_uart_scfifo_w" {  } { { "jtag_uart.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/jtag_uart.vhd" 292 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "4 jtag_uart_drom_module " "Info: Found entity 4: jtag_uart_drom_module" {  } { { "jtag_uart.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/jtag_uart.vhd" 430 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "5 jtag_uart_sim_scfifo_r " "Info: Found entity 5: jtag_uart_sim_scfifo_r" {  } { { "jtag_uart.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/jtag_uart.vhd" 819 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "6 jtag_uart_scfifo_r " "Info: Found entity 6: jtag_uart_scfifo_r" {  } { { "jtag_uart.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/jtag_uart.vhd" 933 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "7 jtag_uart " "Info: Found entity 7: jtag_uart" {  } { { "jtag_uart.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/jtag_uart.vhd" 1075 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!d! design units and %3!d! entities in project" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "jtag_uart std_1c20:inst\|jtag_uart:the_jtag_uart " "Info: Elaborating entity \"jtag_uart\" for hierarchy \"std_1c20:inst\|jtag_uart:the_jtag_uart\"" {  } { { "std_1c20.vhd" "the_jtag_uart" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/std_1c20.vhd" 10218 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "jtag_uart_scfifo_w std_1c20:inst\|jtag_uart:the_jtag_uart\|jtag_uart_scfifo_w:the_jtag_uart_scfifo_w " "Info: Elaborating entity \"jtag_uart_scfifo_w\" for hierarchy \"std_1c20:inst\|jtag_uart:the_jtag_uart\|jtag_uart_scfifo_w:the_jtag_uart_scfifo_w\"" {  } { { "jtag_uart.vhd" "the_jtag_uart_scfifo_w" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/jtag_uart.vhd" 1197 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "../../../../quartus60/libraries/megafunctions/scfifo.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file ../../../../quartus60/libraries/megafunctions/scfifo.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 scfifo " "Info: Found entity 1: scfifo" {  } { { "scfifo.tdf" "" { Text "d:/altera/quartus60/libraries/megafunctions/scfifo.tdf" 234 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "scfifo std_1c20:inst\|jtag_uart:the_jtag_uart\|jtag_uart_scfifo_w:the_jtag_uart_scfifo_w\|scfifo:wfifo " "Info: Elaborating entity \"scfifo\" for hierarchy \"std_1c20:inst\|jtag_uart:the_jtag_uart\|jtag_uart_scfifo_w:the_jtag_uart_scfifo_w\|scfifo:wfifo\"" {  } { { "jtag_uart.vhd" "wfifo" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/jtag_uart.vhd" 385 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_ELABORATION_HEADER" "std_1c20:inst\|jtag_uart:the_jtag_uart\|jtag_uart_scfifo_w:the_jtag_uart_scfifo_w\|scfifo:wfifo " "Info: Elaborated megafunction instantiation \"std_1c20:inst\|jtag_uart:the_jtag_uart\|jtag_uart_scfifo_w:the_jtag_uart_scfifo_w\|scfifo:wfifo\"" {  } { { "jtag_uart.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/jtag_uart.vhd" 385 -1 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/scfifo_jf21.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/scfifo_jf21.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 scfifo_jf21 " "Info: Found entity 1: scfifo_jf21" {  } { { "db/scfifo_jf21.tdf" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/db/scfifo_jf21.tdf" 24 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "scfifo_jf21 std_1c20:inst\|jtag_uart:the_jtag_uart\|jtag_uart_scfifo_w:the_jtag_uart_scfifo_w\|scfifo:wfifo\|scfifo_jf21:auto_generated " "Info: Elaborating entity \"scfifo_jf21\" for hierarchy \"std_1c20:inst\|jtag_uart:the_jtag_uart\|jtag_uart_scfifo_w:the_jtag_uart_scfifo_w\|scfifo:wfifo\|scfifo_jf21:auto_generated\"" {  } { { "scfifo.tdf" "auto_generated" { Text "d:/altera/quartus60/libraries/megafunctions/scfifo.tdf" 294 3 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/a_dpfifo_ml21.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/a_dpfifo_ml21.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 a_dpfifo_ml21 " "Info: Found entity 1: a_dpfifo_ml21" {  } { { "db/a_dpfifo_ml21.tdf" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/db/a_dpfifo_ml21.tdf" 28 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "a_dpfifo_ml21 std_1c20:inst\|jtag_uart:the_jtag_uart\|jtag_uart_scfifo_w:the_jtag_uart_scfifo_w\|scfifo:wfifo\|scfifo_jf21:auto_generated\|a_dpfifo_ml21:dpfifo " "Info: Elaborating entity \"a_dpfifo_ml21\" for hierarchy \"std_1c20:inst\|jtag_uart:the_jtag_uart\|jtag_uart_scfifo_w:the_jtag_uart_scfifo_w\|scfifo:wfifo\|scfifo_jf21:auto_generated\|a_dpfifo_ml21:dpfifo\"" {  } { { "db/scfifo_jf21.tdf" "dpfifo" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/db/scfifo_jf21.tdf" 37 2 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/a_fefifo_7cf.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/a_fefifo_7cf.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 a_fefifo_7cf " "Info: Found entity 1: a_fefifo_7cf" {  } { { "db/a_fefifo_7cf.tdf" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/db/a_fefifo_7cf.tdf" 24 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "a_fefifo_7cf std_1c20:inst\|jtag_uart:the_jtag_uart\|jtag_uart_scfifo_w:the_jtag_uart_scfifo_w\|scfifo:wfifo\|scfifo_jf21:auto_generated\|a_dpfifo_ml21:dpfifo\|a_fefifo_7cf:fifo_state " "Info: Elaborating entity \"a_fefifo_7cf\" for hierarchy \"std_1c20:inst\|jtag_uart:the_jtag_uart\|jtag_uart_scfifo_w:the_jtag_uart_scfifo_w\|scfifo:wfifo\|scfifo_jf21:auto_generated\|a_dpfifo_ml21:dpfifo\|a_fefifo_7cf:fifo_state\"" {  } { { "db/a_dpfifo_ml21.tdf" "fifo_state" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/db/a_dpfifo_ml21.tdf" 42 2 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/cntr_9c7.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/cntr_9c7.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 cntr_9c7 " "Info: Found entity 1: cntr_9c7" {  } { { "db/cntr_9c7.tdf" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/db/cntr_9c7.tdf" 25 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "cntr_9c7 std_1c20:inst\|jtag_uart:the_jtag_uart\|jtag_uart_scfifo_w:the_jtag_uart_scfifo_w\|scfifo:wfifo\|scfifo_jf21:auto_generated\|a_dpfifo_ml21:dpfifo\|a_fefifo_7cf:fifo_state\|cntr_9c7:count_usedw " "Info: Elaborating entity \"cntr_9c7\" for hierarchy \"std_1c20:inst\|jtag_uart:the_jtag_uart\|jtag_uart_scfifo_w:the_jtag_uart_scfifo_w\|scfifo:wfifo\|scfifo_jf21:auto_generated\|a_dpfifo_ml21:dpfifo\|a_fefifo_7cf:fifo_state\|cntr_9c7:count_usedw\"" {  } { { "db/a_fefifo_7cf.tdf" "count_usedw" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/db/a_fefifo_7cf.tdf" 38 2 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/dpram_j921.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/dpram_j921.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 dpram_j921 " "Info: Found entity 1: dpram_j921" {  } { { "db/dpram_j921.tdf" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/db/dpram_j921.tdf" 24 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "dpram_j921 std_1c20:inst\|jtag_uart:the_jtag_uart\|jtag_uart_scfifo_w:the_jtag_uart_scfifo_w\|scfifo:wfifo\|scfifo_jf21:auto_generated\|a_dpfifo_ml21:dpfifo\|dpram_j921:FIFOram " "Info: Elaborating entity \"dpram_j921\" for hierarchy \"std_1c20:inst\|jtag_uart:the_jtag_uart\|jtag_uart_scfifo_w:the_jtag_uart_scfifo_w\|scfifo:wfifo\|scfifo_jf21:auto_generated\|a_dpfifo_ml21:dpfifo\|dpram_j921:FIFOram\"" {  } { { "db/a_dpfifo_ml21.tdf" "FIFOram" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/db/a_dpfifo_ml21.tdf" 43 2 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_nll1.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/altsyncram_nll1.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_nll1 " "Info: Found entity 1: altsyncram_nll1" {  } { { "db/altsyncram_nll1.tdf" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/db/altsyncram_nll1.tdf" 36 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram_nll1 std_1c20:inst\|jtag_uart:the_jtag_uart\|jtag_uart_scfifo_w:the_jtag_uart_scfifo_w\|scfifo:wfifo\|scfifo_jf21:auto_generated\|a_dpfifo_ml21:dpfifo\|dpram_j921:FIFOram\|altsyncram_nll1:altsyncram1 " "Info: Elaborating entity \"altsyncram_nll1\" for hierarchy \"std_1c20:inst\|jtag_uart:the_jtag_uart\|jtag_uart_scfifo_w:the_jtag_uart_scfifo_w\|scfifo:wfifo\|scfifo_jf21:auto_generated\|a_dpfifo_ml21:dpfifo\|dpram_j921:FIFOram\|altsyncram_nll1:altsyncram1\"" {  } { { "db/dpram_j921.tdf" "altsyncram1" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/db/dpram_j921.tdf" 36 2 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/cntr_rd8.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/cntr_rd8.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 cntr_rd8 " "Info: Found entity 1: cntr_rd8" {  } { { "db/cntr_rd8.tdf" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/db/cntr_rd8.tdf" 25 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "cntr_rd8 std_1c20:inst\|jtag_uart:the_jtag_uart\|jtag_uart_scfifo_w:the_jtag_uart_scfifo_w\|scfifo:wfifo\|scfifo_jf21:auto_generated\|a_dpfifo_ml21:dpfifo\|cntr_rd8:rd_ptr_count " "Info: Elaborating entity \"cntr_rd8\" for hierarchy \"std_1c20:inst\|jtag_uart:the_jtag_uart\|jtag_uart_scfifo_w:the_jtag_uart_scfifo_w\|scfifo:wfifo\|scfifo_jf21:auto_generated\|a_dpfifo_ml21:dpfifo\|cntr_rd8:rd_ptr_count\"" {  } { { "db/a_dpfifo_ml21.tdf" "rd_ptr_count" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/db/a_dpfifo_ml21.tdf" 44 2 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "jtag_uart_scfifo_r std_1c20:inst\|jtag_uart:the_jtag_uart\|jtag_uart_scfifo_r:the_jtag_uart_scfifo_r " "Info: Elaborating entity \"jtag_uart_scfifo_r\" for hierarchy \"std_1c20:inst\|jtag_uart:the_jtag_uart\|jtag_uart_scfifo_r:the_jtag_uart_scfifo_r\"" {  } { { "jtag_uart.vhd" "the_jtag_uart_scfifo_r" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/jtag_uart.vhd" 1212 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "../../../../quartus60/libraries/megafunctions/alt_jtag_atlantic.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file ../../../../quartus60/libraries/megafunctions/alt_jtag_atlantic.v" { { "Info" "ISGN_ENTITY_NAME" "1 alt_jtag_atlantic " "Info: Found entity 1: alt_jtag_atlantic" {  } { { "../../../../quartus60/libraries/megafunctions/alt_jtag_atlantic.v" "" { Text "D:/ALTERA/quartus60/libraries/megafunctions/alt_jtag_atlantic.v" 116 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "alt_jtag_atlantic std_1c20:inst\|jtag_uart:the_jtag_uart\|alt_jtag_atlantic:jtag_uart_alt_jtag_atlantic " "Info: Elaborating entity \"alt_jtag_atlantic\" for hierarchy \"std_1c20:inst\|jtag_uart:the_jtag_uart\|alt_jtag_atlantic:jtag_uart_alt_jtag_atlantic\"" {  } { { "jtag_uart.vhd" "jtag_uart_alt_jtag_atlantic" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/jtag_uart.vhd" 1350 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_ELABORATION_HEADER" "std_1c20:inst\|jtag_uart:the_jtag_uart\|alt_jtag_atlantic:jtag_uart_alt_jtag_atlantic " "Info: Elaborated megafunction instantiation \"std_1c20:inst\|jtag_uart:the_jtag_uart\|alt_jtag_atlantic:jtag_uart_alt_jtag_atlantic\"" {  } { { "jtag_uart.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/jtag_uart.vhd" 1350 -1 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "lcd_display_control_slave_arbitrator std_1c20:inst\|lcd_display_control_slave_arbitrator:the_lcd_display_control_slave " "Info: Elaborating entity \"lcd_display_control_slave_arbitrator\" for hierarchy \"std_1c20:inst\|lcd_display_control_slave_arbitrator:the_lcd_display_control_slave\"" {  } { { "std_1c20.vhd" "the_lcd_display_control_slave" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/std_1c20.vhd" 10236 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Warning" "WSGN_SEARCH_FILE" "lcd_display.vhd 2 1 " "Warning: Using design file lcd_display.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 lcd_display-europa " "Info: Found design unit 1: lcd_display-europa" {  } { { "lcd_display.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/lcd_display.vhd" 46 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 lcd_display " "Info: Found entity 1: lcd_display" {  } { { "lcd_display.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/lcd_display.vhd" 26 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!d! design units and %3!d! entities in project" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "lcd_display std_1c20:inst\|lcd_display:the_lcd_display " "Info: Elaborating entity \"lcd_display\" for hierarchy \"std_1c20:inst\|lcd_display:the_lcd_display\"" {  } { { "std_1c20.vhd" "the_lcd_display" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/std_1c20.vhd" 10263 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "led_pio_s1_arbitrator std_1c20:inst\|led_pio_s1_arbitrator:the_led_pio_s1 " "Info: Elaborating entity \"led_pio_s1_arbitrator\" for hierarchy \"std_1c20:inst\|led_pio_s1_arbitrator:the_led_pio_s1\"" {  } { { "std_1c20.vhd" "the_led_pio_s1" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/std_1c20.vhd" 10280 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Warning" "WSGN_SEARCH_FILE" "led_pio.vhd 2 1 " "Warning: Using design file led_pio.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 led_pio-europa " "Info: Found design unit 1: led_pio-europa" {  } { { "led_pio.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/led_pio.vhd" 42 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 led_pio " "Info: Found entity 1: led_pio" {  } { { "led_pio.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/led_pio.vhd" 26 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!d! design units and %3!d! entities in project" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "led_pio std_1c20:inst\|led_pio:the_led_pio " "Info: Elaborating entity \"led_pio\" for hierarchy \"std_1c20:inst\|led_pio:the_led_pio\"" {  } { { "std_1c20.vhd" "the_led_pio" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/std_1c20.vhd" 10304 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "reconfig_request_pio_s1_arbitrator std_1c20:inst\|reconfig_request_pio_s1_arbitrator:the_reconfig_request_pio_s1 " "Info: Elaborating entity \"reconfig_request_pio_s1_arbitrator\" for hierarchy \"std_1c20:inst\|reconfig_request_pio_s1_arbitrator:the_reconfig_request_pio_s1\"" {  } { { "std_1c20.vhd" "the_reconfig_request_pio_s1" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/std_1c20.vhd" 10317 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Warning" "WSGN_SEARCH_FILE" "reconfig_request_pio.vhd 2 1 " "Warning: Using design file reconfig_request_pio.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 reconfig_request_pio-europa " "Info: Found design unit 1: reconfig_request_pio-europa" {  } { { "reconfig_request_pio.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/reconfig_request_pio.vhd" 43 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 reconfig_request_pio " "Info: Found entity 1: reconfig_request_pio" {  } { { "reconfig_request_pio.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/reconfig_request_pio.vhd" 26 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!d! design units and %3!d! entities in project" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "reconfig_request_pio std_1c20:inst\|reconfig_request_pio:the_reconfig_request_pio " "Info: Elaborating entity \"reconfig_request_pio\" for hierarchy \"std_1c20:inst\|reconfig_request_pio:the_reconfig_request_pio\"" {  } { { "std_1c20.vhd" "the_reconfig_request_pio" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/std_1c20.vhd" 10342 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "sdram_s1_arbitrator std_1c20:inst\|sdram_s1_arbitrator:the_sdram_s1 " "Info: Elaborating entity \"sdram_s1_arbitrator\" for hierarchy \"std_1c20:inst\|sdram_s1_arbitrator:the_sdram_s1\"" {  } { { "std_1c20.vhd" "the_sdram_s1" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/std_1c20.vhd" 10356 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "rdv_fifo_for_cpu_data_master_to_sdram_s1_module std_1c20:inst\|sdram_s1_arbitrator:the_sdram_s1\|rdv_fifo_for_cpu_data_master_to_sdram_s1_module:rdv_fifo_for_cpu_data_master_to_sdram_s1 " "Info: Elaborating entity \"rdv_fifo_for_cpu_data_master_to_sdram_s1_module\" for hierarchy \"std_1c20:inst\|sdram_s1_arbitrator:the_sdram_s1\|rdv_fifo_for_cpu_data_master_to_sdram_s1_module:rdv_fifo_for_cpu_data_master_to_sdram_s1\"" {  } { { "std_1c20.vhd" "rdv_fifo_for_cpu_data_master_to_sdram_s1" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/std_1c20.vhd" 6048 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "rdv_fifo_for_cpu_instruction_master_to_sdram_s1_module std_1c20:inst\|sdram_s1_arbitrator:the_sdram_s1\|rdv_fifo_for_cpu_instruction_master_to_sdram_s1_module:rdv_fifo_for_cpu_instruction_master_to_sdram_s1 " "Info: Elaborating entity \"rdv_fifo_for_cpu_instruction_master_to_sdram_s1_module\" for hierarchy \"std_1c20:inst\|sdram_s1_arbitrator:the_sdram_s1\|rdv_fifo_for_cpu_instruction_master_to_sdram_s1_module:rdv_fifo_for_cpu_instruction_master_to_sdram_s1\"" {  } { { "std_1c20.vhd" "rdv_fifo_for_cpu_instruction_master_to_sdram_s1" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/std_1c20.vhd" 6090 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Warning" "WSGN_SEARCH_FILE" "sdram.vhd 4 2 " "Warning: Using design file sdram.vhd, which is not specified as a design file for the current project, but contains definitions for 4 design units and 2 entities in project" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 sdram_input_efifo_module-europa " "Info: Found design unit 1: sdram_input_efifo_module-europa" {  } { { "sdram.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/sdram.vhd" 45 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_DESIGN_UNIT_NAME" "2 sdram-europa " "Info: Found design unit 2: sdram-europa" {  } { { "sdram.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/sdram.vhd" 190 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 sdram_input_efifo_module " "Info: Found entity 1: sdram_input_efifo_module" {  } { { "sdram.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/sdram.vhd" 26 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "2 sdram " "Info: Found entity 2: sdram" {  } { { "sdram.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/sdram.vhd" 161 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!d! design units and %3!d! entities in project" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "sdram std_1c20:inst\|sdram:the_sdram " "Info: Elaborating entity \"sdram\" for hierarchy \"std_1c20:inst\|sdram:the_sdram\"" {  } { { "std_1c20.vhd" "the_sdram" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/std_1c20.vhd" 10396 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "sdram_input_efifo_module std_1c20:inst\|sdram:the_sdram\|sdram_input_efifo_module:the_sdram_input_efifo_module " "Info: Elaborating entity \"sdram_input_efifo_module\" for hierarchy \"std_1c20:inst\|sdram:the_sdram\|sdram_input_efifo_module:the_sdram_input_efifo_module\"" {  } { { "sdram.vhd" "the_sdram_input_efifo_module" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/sdram.vhd" 289 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "sdram_pll_s1_arbitrator std_1c20:inst\|sdram_pll_s1_arbitrator:the_sdram_pll_s1 " "Info: Elaborating entity \"sdram_pll_s1_arbitrator\" for hierarchy \"std_1c20:inst\|sdram_pll_s1_arbitrator:the_sdram_pll_s1\"" {  } { { "std_1c20.vhd" "the_sdram_pll_s1" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/std_1c20.vhd" 10422 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Warning" "WSGN_SEARCH_FILE" "sdram_pll.vhd 2 1 " "Warning: Using design file sdram_pll.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 sdram_pll-europa " "Info: Found design unit 1: sdram_pll-europa" {  } { { "sdram_pll.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/sdram_pll.vhd" 52 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 sdram_pll " "Info: Found entity 1: sdram_pll" {  } { { "sdram_pll.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/sdram_pll.vhd" 32 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!d! design units and %3!d! entities in project" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "sdram_pll std_1c20:inst\|sdram_pll:the_sdram_pll " "Info: Elaborating entity \"sdram_pll\" for hierarchy \"std_1c20:inst\|sdram_pll:the_sdram_pll\"" {  } { { "std_1c20.vhd" "the_sdram_pll" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/std_1c20.vhd" 10450 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "reset_input1 sdram_pll.vhd(176) " "Warning (10492): VHDL Process Statement warning at sdram_pll.vhd(176): signal \"reset_input1\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "sdram_pll.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/sdram_pll.vhd" 176 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" 0 0}
{ "Warning" "WSGN_SEARCH_FILE" "altpllsdram_pll.vhd 2 1 " "Warning: Using design file altpllsdram_pll.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 altpllsdram_pll-SYN " "Info: Found design unit 1: altpllsdram_pll-SYN" {  } { { "altpllsdram_pll.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/altpllsdram_pll.vhd" 49 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 altpllsdram_pll " "Info: Found entity 1: altpllsdram_pll" {  } { { "altpllsdram_pll.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/altpllsdram_pll.vhd" 39 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!d! design units and %3!d! entities in project" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altpllsdram_pll std_1c20:inst\|sdram_pll:the_sdram_pll\|altpllsdram_pll:the_pll " "Info: Elaborating entity \"altpllsdram_pll\" for hierarchy \"std_1c20:inst\|sdram_pll:the_sdram_pll\|altpllsdram_pll:the_pll\"" {  } { { "sdram_pll.vhd" "the_pll" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/sdram_pll.vhd" 145 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altpll std_1c20:inst\|sdram_pll:the_sdram_pll\|altpllsdram_pll:the_pll\|altpll:altpll_component " "Info: Elaborating entity \"altpll\" for hierarchy \"std_1c20:inst\|sdram_pll:the_sdram_pll\|altpllsdram_pll:the_pll\|altpll:altpll_component\"" {  } { { "altpllsdram_pll.vhd" "altpll_component" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/altpllsdram_pll.vhd" 137 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_ELABORATION_HEADER" "std_1c20:inst\|sdram_pll:the_sdram_pll\|altpllsdram_pll:the_pll\|altpll:altpll_component " "Info: Elaborated megafunction instantiation \"std_1c20:inst\|sdram_pll:the_sdram_pll\|altpllsdram_pll:the_pll\|altpll:altpll_component\"" {  } { { "altpllsdram_pll.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/altpllsdram_pll.vhd" 137 -1 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "seven_seg_pio_s1_arbitrator std_1c20:inst\|seven_seg_pio_s1_arbitrator:the_seven_seg_pio_s1 " "Info: Elaborating entity \"seven_seg_pio_s1_arbitrator\" for hierarchy \"std_1c20:inst\|seven_seg_pio_s1_arbitrator:the_seven_seg_pio_s1\"" {  } { { "std_1c20.vhd" "the_seven_seg_pio_s1" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/std_1c20.vhd" 10467 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Warning" "WSGN_SEARCH_FILE" "seven_seg_pio.vhd 2 1 " "Warning: Using design file seven_seg_pio.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 seven_seg_pio-europa " "Info: Found design unit 1: seven_seg_pio-europa" {  } { { "seven_seg_pio.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/seven_seg_pio.vhd" 42 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 seven_seg_pio " "Info: Found entity 1: seven_seg_pio" {  } { { "seven_seg_pio.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/seven_seg_pio.vhd" 26 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!d! design units and %3!d! entities in project" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "seven_seg_pio std_1c20:inst\|seven_seg_pio:the_seven_seg_pio " "Info: Elaborating entity \"seven_seg_pio\" for hierarchy \"std_1c20:inst\|seven_seg_pio:the_seven_seg_pio\"" {  } { { "std_1c20.vhd" "the_seven_seg_pio" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/std_1c20.vhd" 10490 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "sys_clk_timer_s1_arbitrator std_1c20:inst\|sys_clk_timer_s1_arbitrator:the_sys_clk_timer_s1 " "Info: Elaborating entity \"sys_clk_timer_s1_arbitrator\" for hierarchy \"std_1c20:inst\|sys_clk_timer_s1_arbitrator:the_sys_clk_timer_s1\"" {  } { { "std_1c20.vhd" "the_sys_clk_timer_s1" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/std_1c20.vhd" 10503 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Warning" "WSGN_SEARCH_FILE" "sys_clk_timer.vhd 2 1 " "Warning: Using design file sys_clk_timer.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 sys_clk_timer-europa " "Info: Found design unit 1: sys_clk_timer-europa" {  } { { "sys_clk_timer.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/sys_clk_timer.vhd" 43 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 sys_clk_timer " "Info: Found entity 1: sys_clk_timer" {  } { { "sys_clk_timer.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/sys_clk_timer.vhd" 26 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!d! design units and %3!d! entities in project" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "sys_clk_timer std_1c20:inst\|sys_clk_timer:the_sys_clk_timer " "Info: Elaborating entity \"sys_clk_timer\" for hierarchy \"std_1c20:inst\|sys_clk_timer:the_sys_clk_timer\"" {  } { { "std_1c20.vhd" "the_sys_clk_timer" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/std_1c20.vhd" 10530 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "sysid_control_slave_arbitrator std_1c20:inst\|sysid_control_slave_arbitrator:the_sysid_control_slave " "Info: Elaborating entity \"sysid_control_slave_arbitrator\" for hierarchy \"std_1c20:inst\|sysid_control_slave_arbitrator:the_sysid_control_slave\"" {  } { { "std_1c20.vhd" "the_sysid_control_slave" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/std_1c20.vhd" 10544 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Warning" "WSGN_SEARCH_FILE" "sysid.vhd 2 1 " "Warning: Using design file sysid.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 sysid-europa " "Info: Found design unit 1: sysid-europa" {  } { { "sysid.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/sysid.vhd" 37 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 sysid " "Info: Found entity 1: sysid" {  } { { "sysid.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/sysid.vhd" 26 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!d! design units and %3!d! entities in project" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "sysid std_1c20:inst\|sysid:the_sysid " "Info: Elaborating entity \"sysid\" for hierarchy \"std_1c20:inst\|sysid:the_sysid\"" {  } { { "std_1c20.vhd" "the_sysid" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/std_1c20.vhd" 10563 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "uart1_s1_arbitrator std_1c20:inst\|uart1_s1_arbitrator:the_uart1_s1 " "Info: Elaborating entity \"uart1_s1_arbitrator\" for hierarchy \"std_1c20:inst\|uart1_s1_arbitrator:the_uart1_s1\"" {  } { { "std_1c20.vhd" "the_uart1_s1" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/std_1c20.vhd" 10571 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Warning" "WSGN_SEARCH_FILE" "uart1.vhd 14 7 " "Warning: Using design file uart1.vhd, which is not specified as a design file for the current project, but contains definitions for 14 design units and 7 entities in project" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 uart1_log_module-europa " "Info: Found design unit 1: uart1_log_module-europa" {  } { { "uart1.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/uart1.vhd" 40 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_DESIGN_UNIT_NAME" "2 uart1_tx-europa " "Info: Found design unit 2: uart1_tx-europa" {  } { { "uart1.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/uart1.vhd" 237 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_DESIGN_UNIT_NAME" "3 uart1_rx_stimulus_source_character_source_rom_module-europa " "Info: Found design unit 3: uart1_rx_stimulus_source_character_source_rom_module-europa" {  } { { "uart1.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/uart1.vhd" 424 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_DESIGN_UNIT_NAME" "4 uart1_rx_stimulus_source-europa " "Info: Found design unit 4: uart1_rx_stimulus_source-europa" {  } { { "uart1.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/uart1.vhd" 771 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_DESIGN_UNIT_NAME" "5 uart1_rx-europa " "Info: Found design unit 5: uart1_rx-europa" {  } { { "uart1.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/uart1.vhd" 941 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_DESIGN_UNIT_NAME" "6 uart1_regs-europa " "Info: Found design unit 6: uart1_regs-europa" {  } { { "uart1.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/uart1.vhd" 1265 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_DESIGN_UNIT_NAME" "7 uart1-europa " "Info: Found design unit 7: uart1-europa" {  } { { "uart1.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/uart1.vhd" 1459 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 uart1_log_module " "Info: Found entity 1: uart1_log_module" {  } { { "uart1.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/uart1.vhd" 29 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "2 uart1_tx " "Info: Found entity 2: uart1_tx" {  } { { "uart1.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/uart1.vhd" 215 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "3 uart1_rx_stimulus_source_character_source_rom_module " "Info: Found entity 3: uart1_rx_stimulus_source_character_source_rom_module" {  } { { "uart1.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/uart1.vhd" 406 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "4 uart1_rx_stimulus_source " "Info: Found entity 4: uart1_rx_stimulus_source" {  } { { "uart1.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/uart1.vhd" 755 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "5 uart1_rx " "Info: Found entity 5: uart1_rx" {  } { { "uart1.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/uart1.vhd" 918 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "6 uart1_regs " "Info: Found entity 6: uart1_regs" {  } { { "uart1.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/uart1.vhd" 1229 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "7 uart1 " "Info: Found entity 7: uart1" {  } { { "uart1.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/uart1.vhd" 1436 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!d! design units and %3!d! entities in project" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "uart1 std_1c20:inst\|uart1:the_uart1 " "Info: Elaborating entity \"uart1\" for hierarchy \"std_1c20:inst\|uart1:the_uart1\"" {  } { { "std_1c20.vhd" "the_uart1" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/std_1c20.vhd" 10603 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "uart1_tx std_1c20:inst\|uart1:the_uart1\|uart1_tx:the_uart1_tx " "Info: Elaborating entity \"uart1_tx\" for hierarchy \"std_1c20:inst\|uart1:the_uart1\|uart1_tx:the_uart1_tx\"" {  } { { "uart1.vhd" "the_uart1_tx" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/uart1.vhd" 1577 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "uart1_rx std_1c20:inst\|uart1:the_uart1\|uart1_rx:the_uart1_rx " "Info: Elaborating entity \"uart1_rx\" for hierarchy \"std_1c20:inst\|uart1:the_uart1\|uart1_rx:the_uart1_rx\"" {  } { { "uart1.vhd" "the_uart1_rx" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/uart1.vhd" 1596 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "uart1_rx_stimulus_source std_1c20:inst\|uart1:the_uart1\|uart1_rx:the_uart1_rx\|uart1_rx_stimulus_source:the_uart1_rx_stimulus_source " "Info: Elaborating entity \"uart1_rx_stimulus_source\" for hierarchy \"std_1c20:inst\|uart1:the_uart1\|uart1_rx:the_uart1_rx\|uart1_rx_stimulus_source:the_uart1_rx_stimulus_source\"" {  } { { "uart1.vhd" "the_uart1_rx_stimulus_source" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/uart1.vhd" 989 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "uart1_regs std_1c20:inst\|uart1:the_uart1\|uart1_regs:the_uart1_regs " "Info: Elaborating entity \"uart1_regs\" for hierarchy \"std_1c20:inst\|uart1:the_uart1\|uart1_regs:the_uart1_regs\"" {  } { { "uart1.vhd" "the_uart1_regs" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/uart1.vhd" 1616 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "std_1c20_reset_sysclk2_domain_synch_module std_1c20:inst\|std_1c20_reset_sysclk2_domain_synch_module:std_1c20_reset_sysclk2_domain_synch " "Info: Elaborating entity \"std_1c20_reset_sysclk2_domain_synch_module\" for hierarchy \"std_1c20:inst\|std_1c20_reset_sysclk2_domain_synch_module:std_1c20_reset_sysclk2_domain_synch\"" {  } { { "std_1c20.vhd" "std_1c20_reset_sysclk2_domain_synch" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/std_1c20.vhd" 10623 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "std_1c20_reset_PLD_CLOCKINPUT_domain_synch_module std_1c20:inst\|std_1c20_reset_PLD_CLOCKINPUT_domain_synch_module:std_1c20_reset_PLD_CLOCKINPUT_domain_synch " "Info: Elaborating entity \"std_1c20_reset_PLD_CLOCKINPUT_domain_synch_module\" for hierarchy \"std_1c20:inst\|std_1c20_reset_PLD_CLOCKINPUT_domain_synch_module:std_1c20_reset_PLD_CLOCKINPUT_domain_synch\"" {  } { { "std_1c20.vhd" "std_1c20_reset_PLD_CLOCKINPUT_domain_synch" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/std_1c20.vhd" 10636 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "std_1c20_reset_PLD_CLKFB_domain_synch_module std_1c20:inst\|std_1c20_reset_PLD_CLKFB_domain_synch_module:std_1c20_reset_PLD_CLKFB_domain_synch " "Info: Elaborating entity \"std_1c20_reset_PLD_CLKFB_domain_synch_module\" for hierarchy \"std_1c20:inst\|std_1c20_reset_PLD_CLKFB_domain_synch_module:std_1c20_reset_PLD_CLKFB_domain_synch\"" {  } { { "std_1c20.vhd" "std_1c20_reset_PLD_CLKFB_domain_synch" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/std_1c20.vhd" 10651 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "../../../../quartus60/libraries/megafunctions/sld_hub.vhd 6 2 " "Info: Found 6 design units, including 2 entities, in source file ../../../../quartus60/libraries/megafunctions/sld_hub.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 HUB_PACK " "Info: Found design unit 1: HUB_PACK" {  } { { "../../../../quartus60/libraries/megafunctions/sld_hub.vhd" "" { Text "D:/ALTERA/quartus60/libraries/megafunctions/sld_hub.vhd" 49 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_DESIGN_UNIT_NAME" "2 JTAG_PACK " "Info: Found design unit 2: JTAG_PACK" {  } { { "../../../../quartus60/libraries/megafunctions/sld_hub.vhd" "" { Text "D:/ALTERA/quartus60/libraries/megafunctions/sld_hub.vhd" 63 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_DESIGN_UNIT_NAME" "3 sld_hub-rtl " "Info: Found design unit 3: sld_hub-rtl" {  } { { "../../../../quartus60/libraries/megafunctions/sld_hub.vhd" "" { Text "D:/ALTERA/quartus60/libraries/megafunctions/sld_hub.vhd" 167 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_DESIGN_UNIT_NAME" "4 sld_jtag_state_machine-rtl " "Info: Found design unit 4: sld_jtag_state_machine-rtl" {  } { { "../../../../quartus60/libraries/megafunctions/sld_hub.vhd" "" { Text "D:/ALTERA/quartus60/libraries/megafunctions/sld_hub.vhd" 1133 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 sld_hub " "Info: Found entity 1: sld_hub" {  } { { "../../../../quartus60/libraries/megafunctions/sld_hub.vhd" "" { Text "D:/ALTERA/quartus60/libraries/megafunctions/sld_hub.vhd" 99 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "2 sld_jtag_state_machine " "Info: Found entity 2: sld_jtag_state_machine" {  } { { "../../../../quartus60/libraries/megafunctions/sld_hub.vhd" "" { Text "D:/ALTERA/quartus60/libraries/megafunctions/sld_hub.vhd" 1118 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_ELABORATION_HEADER" "sld_hub:sld_hub_inst " "Info: Elaborated megafunction instantiation \"sld_hub:sld_hub_inst\"" {  } {  } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0}
{ "Info" "ISGN_MEGAFN_DESCENDANT" "sld_hub:sld_hub_inst\|sld_jtag_state_machine:jtag_state_machine sld_hub:sld_hub_inst " "Info: Elaborated megafunction instantiation \"sld_hub:sld_hub_inst\|sld_jtag_state_machine:jtag_state_machine\", which is child of megafunction instantiation \"sld_hub:sld_hub_inst\"" {  } { { "../../../../quartus60/libraries/megafunctions/sld_hub.vhd" "" { Text "D:/ALTERA/quartus60/libraries/megafunctions/sld_hub.vhd" 564 -1 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0}
{ "Info" "ISGN_MEGAFN_PARAM_TOP" "sld_hub:sld_hub_inst " "Info: Instantiated megafunction \"sld_hub:sld_hub_inst\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "SLD_HUB_IP_VERSION 1 " "Info: Parameter \"SLD_HUB_IP_VERSION\" = \"1\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "SLD_HUB_IP_MINOR_VERSION 3 " "Info: Parameter \"SLD_HUB_IP_MINOR_VERSION\" = \"3\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "SLD_COMMON_IP_VERSION 0 " "Info: Parameter \"SLD_COMMON_IP_VERSION\" = \"0\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "N_NODES 2 " "Info: Parameter \"N_NODES\" = \"2\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "N_SEL_BITS 2 " "Info: Parameter \"N_SEL_BITS\" = \"2\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "N_NODE_IR_BITS 5 " "Info: Parameter \"N_NODE_IR_BITS\" = \"5\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "NODE_INFO 0000110000000000011011100000000000010001000100000100011000000000 " "Info: Parameter \"NODE_INFO\" = \"0000110000000000011011100000000000010001000100000100011000000000\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "COMPILATION_MODE 0 " "Info: Parameter \"COMPILATION_MODE\" = \"0\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "DEVICE_FAMILY Cyclone " "Info: Parameter \"DEVICE_FAMILY\" = \"Cyclone\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0}  } {  } 0 0 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "../../../../quartus60/libraries/megafunctions/lpm_shiftreg.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file ../../../../quartus60/libraries/megafunctions/lpm_shiftreg.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_shiftreg " "Info: Found entity 1: lpm_shiftreg" {  } { { "lpm_shiftreg.tdf" "" { Text "d:/altera/quartus60/libraries/megafunctions/lpm_shiftreg.tdf" 37 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_MEGAFN_DESCENDANT" "sld_hub:sld_hub_inst\|lpm_shiftreg:jtag_ir_register sld_hub:sld_hub_inst " "Info: Elaborated megafunction instantiation \"sld_hub:sld_hub_inst\|lpm_shiftreg:jtag_ir_register\", which is child of megafunction instantiation \"sld_hub:sld_hub_inst\"" {  } { { "../../../../quartus60/libraries/megafunctions/sld_hub.vhd" "" { Text "D:/ALTERA/quartus60/libraries/megafunctions/sld_hub.vhd" 595 -1 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0}
{ "Info" "ISGN_MEGAFN_PARAM_TOP" "sld_hub:sld_hub_inst " "Info: Instantiated megafunction \"sld_hub:sld_hub_inst\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "SLD_HUB_IP_VERSION 1 " "Info: Parameter \"SLD_HUB_IP_VERSION\" = \"1\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "SLD_HUB_IP_MINOR_VERSION 3 " "Info: Parameter \"SLD_HUB_IP_MINOR_VERSION\" = \"3\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "SLD_COMMON_IP_VERSION 0 " "Info: Parameter \"SLD_COMMON_IP_VERSION\" = \"0\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "N_NODES 2 " "Info: Parameter \"N_NODES\" = \"2\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "N_SEL_BITS 2 " "Info: Parameter \"N_SEL_BITS\" = \"2\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "N_NODE_IR_BITS 5 " "Info: Parameter \"N_NODE_IR_BITS\" = \"5\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "NODE_INFO 0000110000000000011011100000000000010001000100000100011000000000 " "Info: Parameter \"NODE_INFO\" = \"0000110000000000011011100000000000010001000100000100011000000000\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "COMPILATION_MODE 0 " "Info: Parameter \"COMPILATION_MODE\" = \"0\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "DEVICE_FAMILY Cyclone " "Info: Parameter \"DEVICE_FAMILY\" = \"Cyclone\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0}  } {  } 0 0 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "../../../../quartus60/libraries/megafunctions/lpm_decode.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file ../../../../quartus60/libraries/megafunctions/lpm_decode.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_decode " "Info: Found entity 1: lpm_decode" {  } { { "lpm_decode.tdf" "" { Text "d:/altera/quartus60/libraries/megafunctions/lpm_decode.tdf" 62 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_MEGAFN_DESCENDANT" "sld_hub:sld_hub_inst\|lpm_decode:instruction_decoder sld_hub:sld_hub_inst " "Info: Elaborated megafunction instantiation \"sld_hub:sld_hub_inst\|lpm_decode:instruction_decoder\", which is child of megafunction instantiation \"sld_hub:sld_hub_inst\"" {  } { { "../../../../quartus60/libraries/megafunctions/sld_hub.vhd" "" { Text "D:/ALTERA/quartus60/libraries/megafunctions/sld_hub.vhd" 684 -1 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0}
{ "Info" "ISGN_MEGAFN_PARAM_TOP" "sld_hub:sld_hub_inst " "Info: Instantiated megafunction \"sld_hub:sld_hub_inst\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "SLD_HUB_IP_VERSION 1 " "Info: Parameter \"SLD_HUB_IP_VERSION\" = \"1\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "SLD_HUB_IP_MINOR_VERSION 3 " "Info: Parameter \"SLD_HUB_IP_MINOR_VERSION\" = \"3\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "SLD_COMMON_IP_VERSION 0 " "Info: Parameter \"SLD_COMMON_IP_VERSION\" = \"0\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "N_NODES 2 " "Info: Parameter \"N_NODES\" = \"2\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "N_SEL_BITS 2 " "Info: Parameter \"N_SEL_BITS\" = \"2\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "N_NODE_IR_BITS 5 " "Info: Parameter \"N_NODE_IR_BITS\" = \"5\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "NODE_INFO 0000110000000000011011100000000000010001000100000100011000000000 " "Info: Parameter \"NODE_INFO\" = \"0000110000000000011011100000000000010001000100000100011000000000\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "COMPILATION_MODE 0 " "Info: Parameter \"COMPILATION_MODE\" = \"0\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "DEVICE_FAMILY Cyclone " "Info: Parameter \"DEVICE_FAMILY\" = \"Cyclone\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0}  } {  } 0 0 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/decode_ogi.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/decode_ogi.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 decode_ogi " "Info: Found entity 1: decode_ogi" {  } { { "db/decode_ogi.tdf" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/db/decode_ogi.tdf" 22 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "../../../../quartus60/libraries/megafunctions/sld_dffex.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file ../../../../quartus60/libraries/megafunctions/sld_dffex.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 sld_dffex-DFFEX " "Info: Found design unit 1: sld_dffex-DFFEX" {  } { { "../../../../quartus60/libraries/megafunctions/sld_dffex.vhd" "" { Text "D:/ALTERA/quartus60/libraries/megafunctions/sld_dffex.vhd" 11 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 sld_dffex " "Info: Found entity 1: sld_dffex" {  } { { "../../../../quartus60/libraries/megafunctions/sld_dffex.vhd" "" { Text "D:/ALTERA/quartus60/libraries/megafunctions/sld_dffex.vhd" 4 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_MEGAFN_DESCENDANT" "sld_hub:sld_hub_inst\|sld_dffex:RESET sld_hub:sld_hub_inst " "Info: Elaborated megafunction instantiation \"sld_hub:sld_hub_inst\|sld_dffex:RESET\", which is child of megafunction instantiation \"sld_hub:sld_hub_inst\"" {  } { { "../../../../quartus60/libraries/megafunctions/sld_hub.vhd" "" { Text "D:/ALTERA/quartus60/libraries/megafunctions/sld_hub.vhd" 763 -1 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0}
{ "Info" "ISGN_MEGAFN_PARAM_TOP" "sld_hub:sld_hub_inst " "Info: Instantiated megafunction \"sld_hub:sld_hub_inst\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "SLD_HUB_IP_VERSION 1 " "Info: Parameter \"SLD_HUB_IP_VERSION\" = \"1\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "SLD_HUB_IP_MINOR_VERSION 3 " "Info: Parameter \"SLD_HUB_IP_MINOR_VERSION\" = \"3\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "SLD_COMMON_IP_VERSION 0 " "Info: Parameter \"SLD_COMMON_IP_VERSION\" = \"0\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "N_NODES 2 " "Info: Parameter \"N_NODES\" = \"2\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "N_SEL_BITS 2 " "Info: Parameter \"N_SEL_BITS\" = \"2\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "N_NODE_IR_BITS 5 " "Info: Parameter \"N_NODE_IR_BITS\" = \"5\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "NODE_INFO 0000110000000000011011100000000000010001000100000100011000000000 " "Info: Parameter \"NODE_INFO\" = \"0000110000000000011011100000000000010001000100000100011000000000\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "COMPILATION_MODE 0 " "Info: Parameter \"COMPILATION_MODE\" = \"0\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "DEVICE_FAMILY Cyclone " "Info: Parameter \"DEVICE_FAMILY\" = \"Cyclone\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0}  } {  } 0 0 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0}
{ "Info" "ISGN_MEGAFN_DESCENDANT" "sld_hub:sld_hub_inst\|sld_dffex:IRSR sld_hub:sld_hub_inst " "Info: Elaborated megafunction instantiation \"sld_hub:sld_hub_inst\|sld_dffex:IRSR\", which is child of megafunction instantiation \"sld_hub:sld_hub_inst\"" {  } { { "../../../../quartus60/libraries/megafunctions/sld_hub.vhd" "" { Text "D:/ALTERA/quartus60/libraries/megafunctions/sld_hub.vhd" 842 -1 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0}
{ "Info" "ISGN_MEGAFN_PARAM_TOP" "sld_hub:sld_hub_inst " "Info: Instantiated megafunction \"sld_hub:sld_hub_inst\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "SLD_HUB_IP_VERSION 1 " "Info: Parameter \"SLD_HUB_IP_VERSION\" = \"1\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "SLD_HUB_IP_MINOR_VERSION 3 " "Info: Parameter \"SLD_HUB_IP_MINOR_VERSION\" = \"3\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "SLD_COMMON_IP_VERSION 0 " "Info: Parameter \"SLD_COMMON_IP_VERSION\" = \"0\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "N_NODES 2 " "Info: Parameter \"N_NODES\" = \"2\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "N_SEL_BITS 2 " "Info: Parameter \"N_SEL_BITS\" = \"2\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "N_NODE_IR_BITS 5 " "Info: Parameter \"N_NODE_IR_BITS\" = \"5\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "NODE_INFO 0000110000000000011011100000000000010001000100000100011000000000 " "Info: Parameter \"NODE_INFO\" = \"0000110000000000011011100000000000010001000100000100011000000000\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "COMPILATION_MODE 0 " "Info: Parameter \"COMPILATION_MODE\" = \"0\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "DEVICE_FAMILY Cyclone " "Info: Parameter \"DEVICE_FAMILY\" = \"Cyclone\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0}  } {  } 0 0 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0}
{ "Info" "ISGN_MEGAFN_DESCENDANT" "sld_hub:sld_hub_inst\|sld_dffex:\\GEN_IRF:2:IRF sld_hub:sld_hub_inst " "Info: Elaborated megafunction instantiation \"sld_hub:sld_hub_inst\|sld_dffex:\\GEN_IRF:2:IRF\", which is child of megafunction instantiation \"sld_hub:sld_hub_inst\"" {  } { { "../../../../quartus60/libraries/megafunctions/sld_hub.vhd" "" { Text "D:/ALTERA/quartus60/libraries/megafunctions/sld_hub.vhd" 910 -1 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0}
{ "Info" "ISGN_MEGAFN_PARAM_TOP" "sld_hub:sld_hub_inst " "Info: Instantiated megafunction \"sld_hub:sld_hub_inst\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "SLD_HUB_IP_VERSION 1 " "Info: Parameter \"SLD_HUB_IP_VERSION\" = \"1\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "SLD_HUB_IP_MINOR_VERSION 3 " "Info: Parameter \"SLD_HUB_IP_MINOR_VERSION\" = \"3\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "SLD_COMMON_IP_VERSION 0 " "Info: Parameter \"SLD_COMMON_IP_VERSION\" = \"0\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "N_NODES 2 " "Info: Parameter \"N_NODES\" = \"2\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "N_SEL_BITS 2 " "Info: Parameter \"N_SEL_BITS\" = \"2\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "N_NODE_IR_BITS 5 " "Info: Parameter \"N_NODE_IR_BITS\" = \"5\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "NODE_INFO 0000110000000000011011100000000000010001000100000100011000000000 " "Info: Parameter \"NODE_INFO\" = \"0000110000000000011011100000000000010001000100000100011000000000\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "COMPILATION_MODE 0 " "Info: Parameter \"COMPILATION_MODE\" = \"0\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "DEVICE_FAMILY Cyclone " "Info: Parameter \"DEVICE_FAMILY\" = \"Cyclone\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0}  } {  } 0 0 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0}
{ "Info" "ISGN_MEGAFN_DESCENDANT" "sld_hub:sld_hub_inst\|sld_dffex:IRF_ENA sld_hub:sld_hub_inst " "Info: Elaborated megafunction instantiation \"sld_hub:sld_hub_inst\|sld_dffex:IRF_ENA\", which is child of megafunction instantiation \"sld_hub:sld_hub_inst\"" {  } { { "../../../../quartus60/libraries/megafunctions/sld_hub.vhd" "" { Text "D:/ALTERA/quartus60/libraries/megafunctions/sld_hub.vhd" 953 -1 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0}
{ "Info" "ISGN_MEGAFN_PARAM_TOP" "sld_hub:sld_hub_inst " "Info: Instantiated megafunction \"sld_hub:sld_hub_inst\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "SLD_HUB_IP_VERSION 1 " "Info: Parameter \"SLD_HUB_IP_VERSION\" = \"1\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "SLD_HUB_IP_MINOR_VERSION 3 " "Info: Parameter \"SLD_HUB_IP_MINOR_VERSION\" = \"3\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "SLD_COMMON_IP_VERSION 0 " "Info: Parameter \"SLD_COMMON_IP_VERSION\" = \"0\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "N_NODES 2 " "Info: Parameter \"N_NODES\" = \"2\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "N_SEL_BITS 2 " "Info: Parameter \"N_SEL_BITS\" = \"2\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "N_NODE_IR_BITS 5 " "Info: Parameter \"N_NODE_IR_BITS\" = \"5\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "NODE_INFO 0000110000000000011011100000000000010001000100000100011000000000 " "Info: Parameter \"NODE_INFO\" = \"0000110000000000011011100000000000010001000100000100011000000000\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "COMPILATION_MODE 0 " "Info: Parameter \"COMPILATION_MODE\" = \"0\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "DEVICE_FAMILY Cyclone " "Info: Parameter \"DEVICE_FAMILY\" = \"Cyclone\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0}  } {  } 0 0 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "../../../../quartus60/libraries/megafunctions/sld_rom_sr.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file ../../../../quartus60/libraries/megafunctions/sld_rom_sr.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 sld_rom_sr-INFO_REG " "Info: Found design unit 1: sld_rom_sr-INFO_REG" {  } { { "../../../../quartus60/libraries/megafunctions/sld_rom_sr.vhd" "" { Text "D:/ALTERA/quartus60/libraries/megafunctions/sld_rom_sr.vhd" 27 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 sld_rom_sr " "Info: Found entity 1: sld_rom_sr" {  } { { "../../../../quartus60/libraries/megafunctions/sld_rom_sr.vhd" "" { Text "D:/ALTERA/quartus60/libraries/megafunctions/sld_rom_sr.vhd" 5 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_MEGAFN_DESCENDANT" "sld_hub:sld_hub_inst\|sld_rom_sr:HUB_INFO_REG sld_hub:sld_hub_inst " "Info: Elaborated megafunction instantiation \"sld_hub:sld_hub_inst\|sld_rom_sr:HUB_INFO_REG\", which is child of megafunction instantiation \"sld_hub:sld_hub_inst\"" {  } { { "../../../../quartus60/libraries/megafunctions/sld_hub.vhd" "" { Text "D:/ALTERA/quartus60/libraries/megafunctions/sld_hub.vhd" 1018 -1 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0}
{ "Info" "ISGN_MEGAFN_PARAM_TOP" "sld_hub:sld_hub_inst " "Info: Instantiated megafunction \"sld_hub:sld_hub_inst\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "SLD_HUB_IP_VERSION 1 " "Info: Parameter \"SLD_HUB_IP_VERSION\" = \"1\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "SLD_HUB_IP_MINOR_VERSION 3 " "Info: Parameter \"SLD_HUB_IP_MINOR_VERSION\" = \"3\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "SLD_COMMON_IP_VERSION 0 " "Info: Parameter \"SLD_COMMON_IP_VERSION\" = \"0\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "N_NODES 2 " "Info: Parameter \"N_NODES\" = \"2\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "N_SEL_BITS 2 " "Info: Parameter \"N_SEL_BITS\" = \"2\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "N_NODE_IR_BITS 5 " "Info: Parameter \"N_NODE_IR_BITS\" = \"5\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "NODE_INFO 0000110000000000011011100000000000010001000100000100011000000000 " "Info: Parameter \"NODE_INFO\" = \"0000110000000000011011100000000000010001000100000100011000000000\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "COMPILATION_MODE 0 " "Info: Parameter \"COMPILATION_MODE\" = \"0\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "DEVICE_FAMILY Cyclone " "Info: Parameter \"DEVICE_FAMILY\" = \"Cyclone\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0}  } {  } 0 0 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "std_1c20:inst\|uart1:the_uart1\|uart1_regs:the_uart1_regs\|readdata\[10\] data_in GND " "Warning: Reduced register \"std_1c20:inst\|uart1:the_uart1\|uart1_regs:the_uart1_regs\|readdata\[10\]\" with stuck data_in port to stuck value GND" {  } { { "uart1.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/uart1.vhd" 1296 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "std_1c20:inst\|uart1:the_uart1\|uart1_regs:the_uart1_regs\|readdata\[11\] data_in GND " "Warning: Reduced register \"std_1c20:inst\|uart1:the_uart1\|uart1_regs:the_uart1_regs\|readdata\[11\]\" with stuck data_in port to stuck value GND" {  } { { "uart1.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/uart1.vhd" 1296 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "std_1c20:inst\|uart1:the_uart1\|uart1_regs:the_uart1_regs\|readdata\[12\] data_in GND " "Warning: Reduced register \"std_1c20:inst\|uart1:the_uart1\|uart1_regs:the_uart1_regs\|readdata\[12\]\" with stuck data_in port to stuck value GND" {  } { { "uart1.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/uart1.vhd" 1296 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "std_1c20:inst\|uart1:the_uart1\|uart1_regs:the_uart1_regs\|readdata\[13\] data_in GND " "Warning: Reduced register \"std_1c20:inst\|uart1:the_uart1\|uart1_regs:the_uart1_regs\|readdata\[13\]\" with stuck data_in port to stuck value GND" {  } { { "uart1.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/uart1.vhd" 1296 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "std_1c20:inst\|uart1:the_uart1\|uart1_regs:the_uart1_regs\|readdata\[14\] data_in GND " "Warning: Reduced register \"std_1c20:inst\|uart1:the_uart1\|uart1_regs:the_uart1_regs\|readdata\[14\]\" with stuck data_in port to stuck value GND" {  } { { "uart1.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/uart1.vhd" 1296 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "std_1c20:inst\|uart1:the_uart1\|uart1_regs:the_uart1_regs\|readdata\[15\] data_in GND " "Warning: Reduced register \"std_1c20:inst\|uart1:the_uart1\|uart1_regs:the_uart1_regs\|readdata\[15\]\" with stuck data_in port to stuck value GND" {  } { { "uart1.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/uart1.vhd" 1296 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "std_1c20:inst\|sdram_pll:the_sdram_pll\|status_reg_out\[0\] data_in GND " "Warning: Reduced register \"std_1c20:inst\|sdram_pll:the_sdram_pll\|status_reg_out\[0\]\" with stuck data_in port to stuck value GND" {  } { { "sdram_pll.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/sdram_pll.vhd" 119 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "std_1c20:inst\|sdram_pll:the_sdram_pll\|status_reg_out\[1\] data_in GND " "Warning: Reduced register \"std_1c20:inst\|sdram_pll:the_sdram_pll\|status_reg_out\[1\]\" with stuck data_in port to stuck value GND" {  } { { "sdram_pll.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/sdram_pll.vhd" 119 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "std_1c20:inst\|sdram_pll:the_sdram_pll\|status_reg_out\[2\] data_in GND " "Warning: Reduced register \"std_1c20:inst\|sdram_pll:the_sdram_pll\|status_reg_out\[2\]\" with stuck data_in port to stuck value GND" {  } { { "sdram_pll.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/sdram_pll.vhd" 119 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "std_1c20:inst\|sdram_pll:the_sdram_pll\|status_reg_out\[3\] data_in GND " "Warning: Reduced register \"std_1c20:inst\|sdram_pll:the_sdram_pll\|status_reg_out\[3\]\" with stuck data_in port to stuck value GND" {  } { { "sdram_pll.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/sdram_pll.vhd" 119 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "std_1c20:inst\|sdram_pll:the_sdram_pll\|status_reg_out\[4\] data_in GND " "Warning: Reduced register \"std_1c20:inst\|sdram_pll:the_sdram_pll\|status_reg_out\[4\]\" with stuck data_in port to stuck value GND" {  } { { "sdram_pll.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/sdram_pll.vhd" 119 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "std_1c20:inst\|sdram_pll:the_sdram_pll\|status_reg_out\[5\] data_in GND " "Warning: Reduced register \"std_1c20:inst\|sdram_pll:the_sdram_pll\|status_reg_out\[5\]\" with stuck data_in port to stuck value GND" {  } { { "sdram_pll.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/sdram_pll.vhd" 119 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "std_1c20:inst\|sdram_pll:the_sdram_pll\|status_reg_out\[6\] data_in GND " "Warning: Reduced register \"std_1c20:inst\|sdram_pll:the_sdram_pll\|status_reg_out\[6\]\" with stuck data_in port to stuck value GND" {  } { { "sdram_pll.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/sdram_pll.vhd" 119 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "std_1c20:inst\|sdram_pll:the_sdram_pll\|status_reg_out\[7\] data_in GND " "Warning: Reduced register \"std_1c20:inst\|sdram_pll:the_sdram_pll\|status_reg_out\[7\]\" with stuck data_in port to stuck value GND" {  } { { "sdram_pll.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/sdram_pll.vhd" 119 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "std_1c20:inst\|sdram_pll:the_sdram_pll\|status_reg_out\[8\] data_in GND " "Warning: Reduced register \"std_1c20:inst\|sdram_pll:the_sdram_pll\|status_reg_out\[8\]\" with stuck data_in port to stuck value GND" {  } { { "sdram_pll.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/sdram_pll.vhd" 119 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "std_1c20:inst\|sdram_pll:the_sdram_pll\|status_reg_out\[9\] data_in GND " "Warning: Reduced register \"std_1c20:inst\|sdram_pll:the_sdram_pll\|status_reg_out\[9\]\" with stuck data_in port to stuck value GND" {  } { { "sdram_pll.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/sdram_pll.vhd" 119 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "std_1c20:inst\|sdram_pll:the_sdram_pll\|status_reg_out\[10\] data_in GND " "Warning: Reduced register \"std_1c20:inst\|sdram_pll:the_sdram_pll\|status_reg_out\[10\]\" with stuck data_in port to stuck value GND" {  } { { "sdram_pll.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/sdram_pll.vhd" 119 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "std_1c20:inst\|sdram_pll:the_sdram_pll\|status_reg_out\[11\] data_in GND " "Warning: Reduced register \"std_1c20:inst\|sdram_pll:the_sdram_pll\|status_reg_out\[11\]\" with stuck data_in port to stuck value GND" {  } { { "sdram_pll.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/sdram_pll.vhd" 119 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "std_1c20:inst\|sdram_pll:the_sdram_pll\|status_reg_out\[12\] data_in GND " "Warning: Reduced register \"std_1c20:inst\|sdram_pll:the_sdram_pll\|status_reg_out\[12\]\" with stuck data_in port to stuck value GND" {  } { { "sdram_pll.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/sdram_pll.vhd" 119 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "std_1c20:inst\|sdram_pll:the_sdram_pll\|status_reg_out\[13\] data_in GND " "Warning: Reduced register \"std_1c20:inst\|sdram_pll:the_sdram_pll\|status_reg_out\[13\]\" with stuck data_in port to stuck value GND" {  } { { "sdram_pll.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/sdram_pll.vhd" 119 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "std_1c20:inst\|sdram_pll:the_sdram_pll\|status_reg_out\[14\] data_in GND " "Warning: Reduced register \"std_1c20:inst\|sdram_pll:the_sdram_pll\|status_reg_out\[14\]\" with stuck data_in port to stuck value GND" {  } { { "sdram_pll.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/sdram_pll.vhd" 119 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "std_1c20:inst\|sdram_pll:the_sdram_pll\|status_reg_out\[15\] data_in GND " "Warning: Reduced register \"std_1c20:inst\|sdram_pll:the_sdram_pll\|status_reg_out\[15\]\" with stuck data_in port to stuck value GND" {  } { { "sdram_pll.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/sdram_pll.vhd" 119 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Info" "ICDB_SGATE_CDB_INFO_USING_PWRUP_DC" "std_1c20:inst\|sdram:the_sdram\|i_addr\[4\] High " "Info: Power-up level of register \"std_1c20:inst\|sdram:the_sdram\|i_addr\[4\]\" is not specified -- using power-up level of High to minimize register" {  } { { "sdram.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/sdram.vhd" 364 -1 0 } }  } 0 0 "Power-up level of register \"%1!s!\" is not specified -- using power-up level of %2!s! to minimize register" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "std_1c20:inst\|sdram:the_sdram\|i_addr\[4\] data_in VCC " "Warning: Reduced register \"std_1c20:inst\|sdram:the_sdram\|i_addr\[4\]\" with stuck data_in port to stuck value VCC" {  } { { "sdram.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/sdram.vhd" 364 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Info" "ICDB_SGATE_CDB_INFO_USING_PWRUP_DC" "std_1c20:inst\|sdram:the_sdram\|i_addr\[5\] High " "Info: Power-up level of register \"std_1c20:inst\|sdram:the_sdram\|i_addr\[5\]\" is not specified -- using power-up level of High to minimize register" {  } { { "sdram.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/sdram.vhd" 364 -1 0 } }  } 0 0 "Power-up level of register \"%1!s!\" is not specified -- using power-up level of %2!s! to minimize register" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "std_1c20:inst\|sdram:the_sdram\|i_addr\[5\] data_in VCC " "Warning: Reduced register \"std_1c20:inst\|sdram:the_sdram\|i_addr\[5\]\" with stuck data_in port to stuck value VCC" {  } { { "sdram.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/sdram.vhd" 364 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "std_1c20:inst\|cpu:the_cpu\|M_ipending_reg\[31\] data_in GND " "Warning: Reduced register \"std_1c20:inst\|cpu:the_cpu\|M_ipending_reg\[31\]\" with stuck data_in port to stuck value GND" {  } { { "cpu.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/cpu.vhd" 7721 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "std_1c20:inst\|cpu:the_cpu\|M_ipending_reg\[30\] data_in GND " "Warning: Reduced register \"std_1c20:inst\|cpu:the_cpu\|M_ipending_reg\[30\]\" with stuck data_in port to stuck value GND" {  } { { "cpu.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/cpu.vhd" 7721 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "std_1c20:inst\|cpu:the_cpu\|M_ipending_reg\[29\] data_in GND " "Warning: Reduced register \"std_1c20:inst\|cpu:the_cpu\|M_ipending_reg\[29\]\" with stuck data_in port to stuck value GND" {  } { { "cpu.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/cpu.vhd" 7721 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "std_1c20:inst\|cpu:the_cpu\|M_ipending_reg\[28\] data_in GND " "Warning: Reduced register \"std_1c20:inst\|cpu:the_cpu\|M_ipending_reg\[28\]\" with stuck data_in port to stuck value GND" {  } { { "cpu.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/cpu.vhd" 7721 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "std_1c20:inst\|cpu:the_cpu\|M_ipending_reg\[27\] data_in GND " "Warning: Reduced register \"std_1c20:inst\|cpu:the_cpu\|M_ipending_reg\[27\]\" with stuck data_in port to stuck value GND" {  } { { "cpu.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/cpu.vhd" 7721 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "std_1c20:inst\|cpu:the_cpu\|M_ipending_reg\[26\] data_in GND " "Warning: Reduced register \"std_1c20:inst\|cpu:the_cpu\|M_ipending_reg\[26\]\" with stuck data_in port to stuck value GND" {  } { { "cpu.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/cpu.vhd" 7721 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "std_1c20:inst\|cpu:the_cpu\|M_ipending_reg\[25\] data_in GND " "Warning: Reduced register \"std_1c20:inst\|cpu:the_cpu\|M_ipending_reg\[25\]\" with stuck data_in port to stuck value GND" {  } { { "cpu.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/cpu.vhd" 7721 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "std_1c20:inst\|cpu:the_cpu\|M_ipending_reg\[24\] data_in GND " "Warning: Reduced register \"std_1c20:inst\|cpu:the_cpu\|M_ipending_reg\[24\]\" with stuck data_in port to stuck value GND" {  } { { "cpu.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/cpu.vhd" 7721 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "std_1c20:inst\|cpu:the_cpu\|M_ipending_reg\[23\] data_in GND " "Warning: Reduced register \"std_1c20:inst\|cpu:the_cpu\|M_ipending_reg\[23\]\" with stuck data_in port to stuck value GND" {  } { { "cpu.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/cpu.vhd" 7721 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "std_1c20:inst\|cpu:the_cpu\|M_ipending_reg\[22\] data_in GND " "Warning: Reduced register \"std_1c20:inst\|cpu:the_cpu\|M_ipending_reg\[22\]\" with stuck data_in port to stuck value GND" {  } { { "cpu.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/cpu.vhd" 7721 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "std_1c20:inst\|cpu:the_cpu\|M_ipending_reg\[21\] data_in GND " "Warning: Reduced register \"std_1c20:inst\|cpu:the_cpu\|M_ipending_reg\[21\]\" with stuck data_in port to stuck value GND" {  } { { "cpu.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/cpu.vhd" 7721 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "std_1c20:inst\|cpu:the_cpu\|M_ipending_reg\[20\] data_in GND " "Warning: Reduced register \"std_1c20:inst\|cpu:the_cpu\|M_ipending_reg\[20\]\" with stuck data_in port to stuck value GND" {  } { { "cpu.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/cpu.vhd" 7721 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "std_1c20:inst\|cpu:the_cpu\|M_ipending_reg\[19\] data_in GND " "Warning: Reduced register \"std_1c20:inst\|cpu:the_cpu\|M_ipending_reg\[19\]\" with stuck data_in port to stuck value GND" {  } { { "cpu.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/cpu.vhd" 7721 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "std_1c20:inst\|cpu:the_cpu\|M_ipending_reg\[18\] data_in GND " "Warning: Reduced register \"std_1c20:inst\|cpu:the_cpu\|M_ipending_reg\[18\]\" with stuck data_in port to stuck value GND" {  } { { "cpu.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/cpu.vhd" 7721 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "std_1c20:inst\|cpu:the_cpu\|M_ipending_reg\[17\] data_in GND " "Warning: Reduced register \"std_1c20:inst\|cpu:the_cpu\|M_ipending_reg\[17\]\" with stuck data_in port to stuck value GND" {  } { { "cpu.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/cpu.vhd" 7721 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "std_1c20:inst\|cpu:the_cpu\|M_ipending_reg\[16\] data_in GND " "Warning: Reduced register \"std_1c20:inst\|cpu:the_cpu\|M_ipending_reg\[16\]\" with stuck data_in port to stuck value GND" {  } { { "cpu.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/cpu.vhd" 7721 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "std_1c20:inst\|cpu:the_cpu\|M_ipending_reg\[15\] data_in GND " "Warning: Reduced register \"std_1c20:inst\|cpu:the_cpu\|M_ipending_reg\[15\]\" with stuck data_in port to stuck value GND" {  } { { "cpu.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/cpu.vhd" 7721 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "std_1c20:inst\|cpu:the_cpu\|M_ipending_reg\[14\] data_in GND " "Warning: Reduced register \"std_1c20:inst\|cpu:the_cpu\|M_ipending_reg\[14\]\" with stuck data_in port to stuck value GND" {  } { { "cpu.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/cpu.vhd" 7721 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "std_1c20:inst\|cpu:the_cpu\|M_ipending_reg\[13\] data_in GND " "Warning: Reduced register \"std_1c20:inst\|cpu:the_cpu\|M_ipending_reg\[13\]\" with stuck data_in port to stuck value GND" {  } { { "cpu.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/cpu.vhd" 7721 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "std_1c20:inst\|cpu:the_cpu\|M_ipending_reg\[12\] data_in GND " "Warning: Reduced register \"std_1c20:inst\|cpu:the_cpu\|M_ipending_reg\[12\]\" with stuck data_in port to stuck value GND" {  } { { "cpu.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/cpu.vhd" 7721 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "std_1c20:inst\|cpu:the_cpu\|M_ipending_reg\[11\] data_in GND " "Warning: Reduced register \"std_1c20:inst\|cpu:the_cpu\|M_ipending_reg\[11\]\" with stuck data_in port to stuck value GND" {  } { { "cpu.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/cpu.vhd" 7721 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "std_1c20:inst\|cpu:the_cpu\|M_ipending_reg\[10\] data_in GND " "Warning: Reduced register \"std_1c20:inst\|cpu:the_cpu\|M_ipending_reg\[10\]\" with stuck data_in port to stuck value GND" {  } { { "cpu.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/cpu.vhd" 7721 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "std_1c20:inst\|cpu:the_cpu\|M_ipending_reg\[9\] data_in GND " "Warning: Reduced register \"std_1c20:inst\|cpu:the_cpu\|M_ipending_reg\[9\]\" with stuck data_in port to stuck value GND" {  } { { "cpu.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/cpu.vhd" 7721 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "std_1c20:inst\|cpu:the_cpu\|M_ipending_reg\[8\] data_in GND " "Warning: Reduced register \"std_1c20:inst\|cpu:the_cpu\|M_ipending_reg\[8\]\" with stuck data_in port to stuck value GND" {  } { { "cpu.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/cpu.vhd" 7721 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "std_1c20:inst\|cpu:the_cpu\|M_ipending_reg\[7\] data_in GND " "Warning: Reduced register \"std_1c20:inst\|cpu:the_cpu\|M_ipending_reg\[7\]\" with stuck data_in port to stuck value GND" {  } { { "cpu.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/cpu.vhd" 7721 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "std_1c20:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_oci_im:the_cpu_nios2_oci_im\|internal_trc_wrap data_in GND " "Warning: Reduced register \"std_1c20:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_oci_im:the_cpu_nios2_oci_im\|internal_trc_wrap\" with stuck data_in port to stuck value GND" {  } { { "cpu.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/cpu.vhd" 3538 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "std_1c20:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_oci_im:the_cpu_nios2_oci_im\|internal_trc_im_addr\[0\] data_in GND " "Warning: Reduced register \"std_1c20:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_oci_im:the_cpu_nios2_oci_im\|internal_trc_im_addr\[0\]\" with stuck data_in port to stuck value GND" {  } { { "cpu.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/cpu.vhd" 3538 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "std_1c20:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_oci_im:the_cpu_nios2_oci_im\|internal_trc_im_addr\[1\] data_in GND " "Warning: Reduced register \"std_1c20:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_oci_im:the_cpu_nios2_oci_im\|internal_trc_im_addr\[1\]\" with stuck data_in port to stuck value GND" {  } { { "cpu.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/cpu.vhd" 3538 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "std_1c20:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_oci_im:the_cpu_nios2_oci_im\|internal_trc_im_addr\[2\] data_in GND " "Warning: Reduced register \"std_1c20:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_oci_im:the_cpu_nios2_oci_im\|internal_trc_im_addr\[2\]\" with stuck data_in port to stuck value GND" {  } { { "cpu.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/cpu.vhd" 3538 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "std_1c20:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_oci_im:the_cpu_nios2_oci_im\|internal_trc_im_addr\[3\] data_in GND " "Warning: Reduced register \"std_1c20:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_oci_im:the_cpu_nios2_oci_im\|internal_trc_im_addr\[3\]\" with stuck data_in port to stuck value GND" {  } { { "cpu.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/cpu.vhd" 3538 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "std_1c20:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_oci_im:the_cpu_nios2_oci_im\|internal_trc_im_addr\[4\] data_in GND " "Warning: Reduced register \"std_1c20:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_oci_im:the_cpu_nios2_oci_im\|internal_trc_im_addr\[4\]\" with stuck data_in port to stuck value GND" {  } { { "cpu.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/cpu.vhd" 3538 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "std_1c20:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_oci_im:the_cpu_nios2_oci_im\|internal_trc_im_addr\[5\] data_in GND " "Warning: Reduced register \"std_1c20:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_oci_im:the_cpu_nios2_oci_im\|internal_trc_im_addr\[5\]\" with stuck data_in port to stuck value GND" {  } { { "cpu.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/cpu.vhd" 3538 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "std_1c20:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_oci_im:the_cpu_nios2_oci_im\|internal_trc_im_addr\[6\] data_in GND " "Warning: Reduced register \"std_1c20:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_oci_im:the_cpu_nios2_oci_im\|internal_trc_im_addr\[6\]\" with stuck data_in port to stuck value GND" {  } { { "cpu.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/cpu.vhd" 3538 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "std_1c20:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_oci_dbrk:the_cpu_nios2_oci_dbrk\|dbrk_break_pulse data_in GND " "Warning: Reduced register \"std_1c20:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_oci_dbrk:the_cpu_nios2_oci_dbrk\|dbrk_break_pulse\" with stuck data_in port to stuck value GND" {  } { { "cpu.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/cpu.vhd" 2048 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "std_1c20:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_oci_dbrk:the_cpu_nios2_oci_dbrk\|dbrk_goto0 data_in GND " "Warning: Reduced register \"std_1c20:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_oci_dbrk:the_cpu_nios2_oci_dbrk\|dbrk_goto0\" with stuck data_in port to stuck value GND" {  } { { "cpu.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/cpu.vhd" 1999 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "std_1c20:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_oci_dbrk:the_cpu_nios2_oci_dbrk\|dbrk_goto1 data_in GND " "Warning: Reduced register \"std_1c20:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_oci_dbrk:the_cpu_nios2_oci_dbrk\|dbrk_goto1\" with stuck data_in port to stuck value GND" {  } { { "cpu.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/cpu.vhd" 2000 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "std_1c20:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_oci_xbrk:the_cpu_nios2_oci_xbrk\|xbrk_hit0 data_in GND " "Warning: Reduced register \"std_1c20:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_oci_xbrk:the_cpu_nios2_oci_xbrk\|xbrk_hit0\" with stuck data_in port to stuck value GND" {  } { { "cpu.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/cpu.vhd" 1727 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "std_1c20:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_oci_xbrk:the_cpu_nios2_oci_xbrk\|xbrk_hit1 data_in GND " "Warning: Reduced register \"std_1c20:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_oci_xbrk:the_cpu_nios2_oci_xbrk\|xbrk_hit1\" with stuck data_in port to stuck value GND" {  } { { "cpu.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/cpu.vhd" 1728 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "std_1c20:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_oci_xbrk:the_cpu_nios2_oci_xbrk\|xbrk_hit2 data_in GND " "Warning: Reduced register \"std_1c20:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_oci_xbrk:the_cpu_nios2_oci_xbrk\|xbrk_hit2\" with stuck data_in port to stuck value GND" {  } { { "cpu.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/cpu.vhd" 1729 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "std_1c20:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_oci_xbrk:the_cpu_nios2_oci_xbrk\|xbrk_hit3 data_in GND " "Warning: Reduced register \"std_1c20:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_oci_xbrk:the_cpu_nios2_oci_xbrk\|xbrk_hit3\" with stuck data_in port to stuck value GND" {  } { { "cpu.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/cpu.vhd" 1730 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Info" "ICDB_SGATE_CDB_INFO_USING_PWRUP_DC" "std_1c20:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_avalon_reg:the_cpu_nios2_avalon_reg\|internal_oci_ienable1\[7\] High " "Info: Power-up level of register \"std_1c20:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_avalon_reg:the_cpu_nios2_avalon_reg\|internal_oci_ienable1\[7\]\" is not specified -- using power-up level of High to minimize register" {  } { { "cpu.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/cpu.vhd" 1177 -1 0 } }  } 0 0 "Power-up level of register \"%1!s!\" is not specified -- using power-up level of %2!s! to minimize register" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "std_1c20:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_avalon_reg:the_cpu_nios2_avalon_reg\|internal_oci_ienable1\[7\] data_in VCC " "Warning: Reduced register \"std_1c20:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_avalon_reg:the_cpu_nios2_avalon_reg\|internal_oci_ienable1\[7\]\" with stuck data_in port to stuck value VCC" {  } { { "cpu.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/cpu.vhd" 1177 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Info" "ICDB_SGATE_CDB_INFO_USING_PWRUP_DC" "std_1c20:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_avalon_reg:the_cpu_nios2_avalon_reg\|internal_oci_ienable1\[8\] High " "Info: Power-up level of register \"std_1c20:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_avalon_reg:the_cpu_nios2_avalon_reg\|internal_oci_ienable1\[8\]\" is not specified -- using power-up level of High to minimize register" {  } { { "cpu.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/cpu.vhd" 1177 -1 0 } }  } 0 0 "Power-up level of register \"%1!s!\" is not specified -- using power-up level of %2!s! to minimize register" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "std_1c20:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_avalon_reg:the_cpu_nios2_avalon_reg\|internal_oci_ienable1\[8\] data_in VCC " "Warning: Reduced register \"std_1c20:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_avalon_reg:the_cpu_nios2_avalon_reg\|internal_oci_ienable1\[8\]\" with stuck data_in port to stuck value VCC" {  } { { "cpu.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/cpu.vhd" 1177 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Info" "ICDB_SGATE_CDB_INFO_USING_PWRUP_DC" "std_1c20:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_avalon_reg:the_cpu_nios2_avalon_reg\|internal_oci_ienable1\[9\] High " "Info: Power-up level of register \"std_1c20:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_avalon_reg:the_cpu_nios2_avalon_reg\|internal_oci_ienable1\[9\]\" is not specified -- using power-up level of High to minimize register" {  } { { "cpu.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/cpu.vhd" 1177 -1 0 } }  } 0 0 "Power-up level of register \"%1!s!\" is not specified -- using power-up level of %2!s! to minimize register" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "std_1c20:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_avalon_reg:the_cpu_nios2_avalon_reg\|internal_oci_ienable1\[9\] data_in VCC " "Warning: Reduced register \"std_1c20:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_avalon_reg:the_cpu_nios2_avalon_reg\|internal_oci_ienable1\[9\]\" with stuck data_in port to stuck value VCC" {  } { { "cpu.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/cpu.vhd" 1177 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Info" "ICDB_SGATE_CDB_INFO_USING_PWRUP_DC" "std_1c20:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_avalon_reg:the_cpu_nios2_avalon_reg\|internal_oci_ienable1\[10\] High " "Info: Power-up level of register \"std_1c20:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_avalon_reg:the_cpu_nios2_avalon_reg\|internal_oci_ienable1\[10\]\" is not specified -- using power-up level of High to minimize register" {  } { { "cpu.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/cpu.vhd" 1177 -1 0 } }  } 0 0 "Power-up level of register \"%1!s!\" is not specified -- using power-up level of %2!s! to minimize register" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "std_1c20:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_avalon_reg:the_cpu_nios2_avalon_reg\|internal_oci_ienable1\[10\] data_in VCC " "Warning: Reduced register \"std_1c20:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_avalon_reg:the_cpu_nios2_avalon_reg\|internal_oci_ienable1\[10\]\" with stuck data_in port to stuck value VCC" {  } { { "cpu.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/cpu.vhd" 1177 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Info" "ICDB_SGATE_CDB_INFO_USING_PWRUP_DC" "std_1c20:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_avalon_reg:the_cpu_nios2_avalon_reg\|internal_oci_ienable1\[11\] High " "Info: Power-up level of register \"std_1c20:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_avalon_reg:the_cpu_nios2_avalon_reg\|internal_oci_ienable1\[11\]\" is not specified -- using power-up level of High to minimize register" {  } { { "cpu.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/cpu.vhd" 1177 -1 0 } }  } 0 0 "Power-up level of register \"%1!s!\" is not specified -- using power-up level of %2!s! to minimize register" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "std_1c20:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_avalon_reg:the_cpu_nios2_avalon_reg\|internal_oci_ienable1\[11\] data_in VCC " "Warning: Reduced register \"std_1c20:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_avalon_reg:the_cpu_nios2_avalon_reg\|internal_oci_ienable1\[11\]\" with stuck data_in port to stuck value VCC" {  } { { "cpu.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/cpu.vhd" 1177 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Info" "ICDB_SGATE_CDB_INFO_USING_PWRUP_DC" "std_1c20:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_avalon_reg:the_cpu_nios2_avalon_reg\|internal_oci_ienable1\[12\] High " "Info: Power-up level of register \"std_1c20:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_avalon_reg:the_cpu_nios2_avalon_reg\|internal_oci_ienable1\[12\]\" is not specified -- using power-up level of High to minimize register" {  } { { "cpu.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/cpu.vhd" 1177 -1 0 } }  } 0 0 "Power-up level of register \"%1!s!\" is not specified -- using power-up level of %2!s! to minimize register" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "std_1c20:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_avalon_reg:the_cpu_nios2_avalon_reg\|internal_oci_ienable1\[12\] data_in VCC " "Warning: Reduced register \"std_1c20:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_avalon_reg:the_cpu_nios2_avalon_reg\|internal_oci_ienable1\[12\]\" with stuck data_in port to stuck value VCC" {  } { { "cpu.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/cpu.vhd" 1177 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Info" "ICDB_SGATE_CDB_INFO_USING_PWRUP_DC" "std_1c20:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_avalon_reg:the_cpu_nios2_avalon_reg\|internal_oci_ienable1\[13\] High " "Info: Power-up level of register \"std_1c20:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_avalon_reg:the_cpu_nios2_avalon_reg\|internal_oci_ienable1\[13\]\" is not specified -- using power-up level of High to minimize register" {  } { { "cpu.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/cpu.vhd" 1177 -1 0 } }  } 0 0 "Power-up level of register \"%1!s!\" is not specified -- using power-up level of %2!s! to minimize register" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "std_1c20:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_avalon_reg:the_cpu_nios2_avalon_reg\|internal_oci_ienable1\[13\] data_in VCC " "Warning: Reduced register \"std_1c20:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_avalon_reg:the_cpu_nios2_avalon_reg\|internal_oci_ienable1\[13\]\" with stuck data_in port to stuck value VCC" {  } { { "cpu.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/cpu.vhd" 1177 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Info" "ICDB_SGATE_CDB_INFO_USING_PWRUP_DC" "std_1c20:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_avalon_reg:the_cpu_nios2_avalon_reg\|internal_oci_ienable1\[14\] High " "Info: Power-up level of register \"std_1c20:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_avalon_reg:the_cpu_nios2_avalon_reg\|internal_oci_ienable1\[14\]\" is not specified -- using power-up level of High to minimize register" {  } { { "cpu.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/cpu.vhd" 1177 -1 0 } }  } 0 0 "Power-up level of register \"%1!s!\" is not specified -- using power-up level of %2!s! to minimize register" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "std_1c20:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_avalon_reg:the_cpu_nios2_avalon_reg\|internal_oci_ienable1\[14\] data_in VCC " "Warning: Reduced register \"std_1c20:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_avalon_reg:the_cpu_nios2_avalon_reg\|internal_oci_ienable1\[14\]\" with stuck data_in port to stuck value VCC" {  } { { "cpu.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/cpu.vhd" 1177 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Info" "ICDB_SGATE_CDB_INFO_USING_PWRUP_DC" "std_1c20:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_avalon_reg:the_cpu_nios2_avalon_reg\|internal_oci_ienable1\[15\] High " "Info: Power-up level of register \"std_1c20:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_avalon_reg:the_cpu_nios2_avalon_reg\|internal_oci_ienable1\[15\]\" is not specified -- using power-up level of High to minimize register" {  } { { "cpu.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/cpu.vhd" 1177 -1 0 } }  } 0 0 "Power-up level of register \"%1!s!\" is not specified -- using power-up level of %2!s! to minimize register" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "std_1c20:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_avalon_reg:the_cpu_nios2_avalon_reg\|internal_oci_ienable1\[15\] data_in VCC " "Warning: Reduced register \"std_1c20:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_avalon_reg:the_cpu_nios2_avalon_reg\|internal_oci_ienable1\[15\]\" with stuck data_in port to stuck value VCC" {  } { { "cpu.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/cpu.vhd" 1177 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Info" "ICDB_SGATE_CDB_INFO_USING_PWRUP_DC" "std_1c20:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_avalon_reg:the_cpu_nios2_avalon_reg\|internal_oci_ienable1\[16\] High " "Info: Power-up level of register \"std_1c20:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_avalon_reg:the_cpu_nios2_avalon_reg\|internal_oci_ienable1\[16\]\" is not specified -- using power-up level of High to minimize register" {  } { { "cpu.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/cpu.vhd" 1177 -1 0 } }  } 0 0 "Power-up level of register \"%1!s!\" is not specified -- using power-up level of %2!s! to minimize register" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "std_1c20:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_avalon_reg:the_cpu_nios2_avalon_reg\|internal_oci_ienable1\[16\] data_in VCC " "Warning: Reduced register \"std_1c20:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_avalon_reg:the_cpu_nios2_avalon_reg\|internal_oci_ienable1\[16\]\" with stuck data_in port to stuck value VCC" {  } { { "cpu.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/cpu.vhd" 1177 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Info" "ICDB_SGATE_CDB_INFO_USING_PWRUP_DC" "std_1c20:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_avalon_reg:the_cpu_nios2_avalon_reg\|internal_oci_ienable1\[17\] High " "Info: Power-up level of register \"std_1c20:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_avalon_reg:the_cpu_nios2_avalon_reg\|internal_oci_ienable1\[17\]\" is not specified -- using power-up level of High to minimize register" {  } { { "cpu.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/cpu.vhd" 1177 -1 0 } }  } 0 0 "Power-up level of register \"%1!s!\" is not specified -- using power-up level of %2!s! to minimize register" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "std_1c20:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_avalon_reg:the_cpu_nios2_avalon_reg\|internal_oci_ienable1\[17\] data_in VCC " "Warning: Reduced register \"std_1c20:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_avalon_reg:the_cpu_nios2_avalon_reg\|internal_oci_ienable1\[17\]\" with stuck data_in port to stuck value VCC" {  } { { "cpu.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/cpu.vhd" 1177 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Info" "ICDB_SGATE_CDB_INFO_USING_PWRUP_DC" "std_1c20:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_avalon_reg:the_cpu_nios2_avalon_reg\|internal_oci_ienable1\[18\] High " "Info: Power-up level of register \"std_1c20:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_avalon_reg:the_cpu_nios2_avalon_reg\|internal_oci_ienable1\[18\]\" is not specified -- using power-up level of High to minimize register" {  } { { "cpu.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/cpu.vhd" 1177 -1 0 } }  } 0 0 "Power-up level of register \"%1!s!\" is not specified -- using power-up level of %2!s! to minimize register" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "std_1c20:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_avalon_reg:the_cpu_nios2_avalon_reg\|internal_oci_ienable1\[18\] data_in VCC " "Warning: Reduced register \"std_1c20:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_avalon_reg:the_cpu_nios2_avalon_reg\|internal_oci_ienable1\[18\]\" with stuck data_in port to stuck value VCC" {  } { { "cpu.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/cpu.vhd" 1177 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Info" "ICDB_SGATE_CDB_INFO_USING_PWRUP_DC" "std_1c20:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_avalon_reg:the_cpu_nios2_avalon_reg\|internal_oci_ienable1\[19\] High " "Info: Power-up level of register \"std_1c20:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_avalon_reg:the_cpu_nios2_avalon_reg\|internal_oci_ienable1\[19\]\" is not specified -- using power-up level of High to minimize register" {  } { { "cpu.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/cpu.vhd" 1177 -1 0 } }  } 0 0 "Power-up level of register \"%1!s!\" is not specified -- using power-up level of %2!s! to minimize register" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "std_1c20:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_avalon_reg:the_cpu_nios2_avalon_reg\|internal_oci_ienable1\[19\] data_in VCC " "Warning: Reduced register \"std_1c20:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_avalon_reg:the_cpu_nios2_avalon_reg\|internal_oci_ienable1\[19\]\" with stuck data_in port to stuck value VCC" {  } { { "cpu.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/cpu.vhd" 1177 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Info" "ICDB_SGATE_CDB_INFO_USING_PWRUP_DC" "std_1c20:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_avalon_reg:the_cpu_nios2_avalon_reg\|internal_oci_ienable1\[20\] High " "Info: Power-up level of register \"std_1c20:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_avalon_reg:the_cpu_nios2_avalon_reg\|internal_oci_ienable1\[20\]\" is not specified -- using power-up level of High to minimize register" {  } { { "cpu.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/cpu.vhd" 1177 -1 0 } }  } 0 0 "Power-up level of register \"%1!s!\" is not specified -- using power-up level of %2!s! to minimize register" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "std_1c20:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_avalon_reg:the_cpu_nios2_avalon_reg\|internal_oci_ienable1\[20\] data_in VCC " "Warning: Reduced register \"std_1c20:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_avalon_reg:the_cpu_nios2_avalon_reg\|internal_oci_ienable1\[20\]\" with stuck data_in port to stuck value VCC" {  } { { "cpu.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/cpu.vhd" 1177 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Info" "ICDB_SGATE_CDB_INFO_USING_PWRUP_DC" "std_1c20:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_avalon_reg:the_cpu_nios2_avalon_reg\|internal_oci_ienable1\[21\] High " "Info: Power-up level of register \"std_1c20:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_avalon_reg:the_cpu_nios2_avalon_reg\|internal_oci_ienable1\[21\]\" is not specified -- using power-up level of High to minimize register" {  } { { "cpu.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/cpu.vhd" 1177 -1 0 } }  } 0 0 "Power-up level of register \"%1!s!\" is not specified -- using power-up level of %2!s! to minimize register" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "std_1c20:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_avalon_reg:the_cpu_nios2_avalon_reg\|internal_oci_ienable1\[21\] data_in VCC " "Warning: Reduced register \"std_1c20:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_avalon_reg:the_cpu_nios2_avalon_reg\|internal_oci_ienable1\[21\]\" with stuck data_in port to stuck value VCC" {  } { { "cpu.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/cpu.vhd" 1177 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Info" "ICDB_SGATE_CDB_INFO_USING_PWRUP_DC" "std_1c20:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_avalon_reg:the_cpu_nios2_avalon_reg\|internal_oci_ienable1\[22\] High " "Info: Power-up level of register \"std_1c20:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_avalon_reg:the_cpu_nios2_avalon_reg\|internal_oci_ienable1\[22\]\" is not specified -- using power-up level of High to minimize register" {  } { { "cpu.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/cpu.vhd" 1177 -1 0 } }  } 0 0 "Power-up level of register \"%1!s!\" is not specified -- using power-up level of %2!s! to minimize register" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "std_1c20:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_avalon_reg:the_cpu_nios2_avalon_reg\|internal_oci_ienable1\[22\] data_in VCC " "Warning: Reduced register \"std_1c20:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_avalon_reg:the_cpu_nios2_avalon_reg\|internal_oci_ienable1\[22\]\" with stuck data_in port to stuck value VCC" {  } { { "cpu.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/cpu.vhd" 1177 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Info" "ICDB_SGATE_CDB_INFO_USING_PWRUP_DC" "std_1c20:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_avalon_reg:the_cpu_nios2_avalon_reg\|internal_oci_ienable1\[23\] High " "Info: Power-up level of register \"std_1c20:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_avalon_reg:the_cpu_nios2_avalon_reg\|internal_oci_ienable1\[23\]\" is not specified -- using power-up level of High to minimize register" {  } { { "cpu.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/cpu.vhd" 1177 -1 0 } }  } 0 0 "Power-up level of register \"%1!s!\" is not specified -- using power-up level of %2!s! to minimize register" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "std_1c20:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_avalon_reg:the_cpu_nios2_avalon_reg\|internal_oci_ienable1\[23\] data_in VCC " "Warning: Reduced register \"std_1c20:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_avalon_reg:the_cpu_nios2_avalon_reg\|internal_oci_ienable1\[23\]\" with stuck data_in port to stuck value VCC" {  } { { "cpu.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/cpu.vhd" 1177 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Info" "ICDB_SGATE_CDB_INFO_USING_PWRUP_DC" "std_1c20:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_avalon_reg:the_cpu_nios2_avalon_reg\|internal_oci_ienable1\[24\] High " "Info: Power-up level of register \"std_1c20:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_avalon_reg:the_cpu_nios2_avalon_reg\|internal_oci_ienable1\[24\]\" is not specified -- using power-up level of High to minimize register" {  } { { "cpu.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/cpu.vhd" 1177 -1 0 } }  } 0 0 "Power-up level of register \"%1!s!\" is not specified -- using power-up level of %2!s! to minimize register" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "std_1c20:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_avalon_reg:the_cpu_nios2_avalon_reg\|internal_oci_ienable1\[24\] data_in VCC " "Warning: Reduced register \"std_1c20:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_avalon_reg:the_cpu_nios2_avalon_reg\|internal_oci_ienable1\[24\]\" with stuck data_in port to stuck value VCC" {  } { { "cpu.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/cpu.vhd" 1177 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Info" "ICDB_SGATE_CDB_INFO_USING_PWRUP_DC" "std_1c20:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_avalon_reg:the_cpu_nios2_avalon_reg\|internal_oci_ienable1\[25\] High " "Info: Power-up level of register \"std_1c20:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_avalon_reg:the_cpu_nios2_avalon_reg\|internal_oci_ienable1\[25\]\" is not specified -- using power-up level of High to minimize register" {  } { { "cpu.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/cpu.vhd" 1177 -1 0 } }  } 0 0 "Power-up level of register \"%1!s!\" is not specified -- using power-up level of %2!s! to minimize register" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "std_1c20:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_avalon_reg:the_cpu_nios2_avalon_reg\|internal_oci_ienable1\[25\] data_in VCC " "Warning: Reduced register \"std_1c20:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_avalon_reg:the_cpu_nios2_avalon_reg\|internal_oci_ienable1\[25\]\" with stuck data_in port to stuck value VCC" {  } { { "cpu.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/cpu.vhd" 1177 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Info" "ICDB_SGATE_CDB_INFO_USING_PWRUP_DC" "std_1c20:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_avalon_reg:the_cpu_nios2_avalon_reg\|internal_oci_ienable1\[26\] High " "Info: Power-up level of register \"std_1c20:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_avalon_reg:the_cpu_nios2_avalon_reg\|internal_oci_ienable1\[26\]\" is not specified -- using power-up level of High to minimize register" {  } { { "cpu.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/cpu.vhd" 1177 -1 0 } }  } 0 0 "Power-up level of register \"%1!s!\" is not specified -- using power-up level of %2!s! to minimize register" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "std_1c20:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_avalon_reg:the_cpu_nios2_avalon_reg\|internal_oci_ienable1\[26\] data_in VCC " "Warning: Reduced register \"std_1c20:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_avalon_reg:the_cpu_nios2_avalon_reg\|internal_oci_ienable1\[26\]\" with stuck data_in port to stuck value VCC" {  } { { "cpu.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/cpu.vhd" 1177 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Info" "ICDB_SGATE_CDB_INFO_USING_PWRUP_DC" "std_1c20:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_avalon_reg:the_cpu_nios2_avalon_reg\|internal_oci_ienable1\[27\] High " "Info: Power-up level of register \"std_1c20:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_avalon_reg:the_cpu_nios2_avalon_reg\|internal_oci_ienable1\[27\]\" is not specified -- using power-up level of High to minimize register" {  } { { "cpu.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/cpu.vhd" 1177 -1 0 } }  } 0 0 "Power-up level of register \"%1!s!\" is not specified -- using power-up level of %2!s! to minimize register" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "std_1c20:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_avalon_reg:the_cpu_nios2_avalon_reg\|internal_oci_ienable1\[27\] data_in VCC " "Warning: Reduced register \"std_1c20:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_avalon_reg:the_cpu_nios2_avalon_reg\|internal_oci_ienable1\[27\]\" with stuck data_in port to stuck value VCC" {  } { { "cpu.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/cpu.vhd" 1177 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Info" "ICDB_SGATE_CDB_INFO_USING_PWRUP_DC" "std_1c20:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_avalon_reg:the_cpu_nios2_avalon_reg\|internal_oci_ienable1\[28\] High " "Info: Power-up level of register \"std_1c20:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_avalon_reg:the_cpu_nios2_avalon_reg\|internal_oci_ienable1\[28\]\" is not specified -- using power-up level of High to minimize register" {  } { { "cpu.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/cpu.vhd" 1177 -1 0 } }  } 0 0 "Power-up level of register \"%1!s!\" is not specified -- using power-up level of %2!s! to minimize register" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "std_1c20:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_avalon_reg:the_cpu_nios2_avalon_reg\|internal_oci_ienable1\[28\] data_in VCC " "Warning: Reduced register \"std_1c20:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_avalon_reg:the_cpu_nios2_avalon_reg\|internal_oci_ienable1\[28\]\" with stuck data_in port to stuck value VCC" {  } { { "cpu.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/cpu.vhd" 1177 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Info" "ICDB_SGATE_CDB_INFO_USING_PWRUP_DC" "std_1c20:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_avalon_reg:the_cpu_nios2_avalon_reg\|internal_oci_ienable1\[29\] High " "Info: Power-up level of register \"std_1c20:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_avalon_reg:the_cpu_nios2_avalon_reg\|internal_oci_ienable1\[29\]\" is not specified -- using power-up level of High to minimize register" {  } { { "cpu.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/cpu.vhd" 1177 -1 0 } }  } 0 0 "Power-up level of register \"%1!s!\" is not specified -- using power-up level of %2!s! to minimize register" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "std_1c20:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_avalon_reg:the_cpu_nios2_avalon_reg\|internal_oci_ienable1\[29\] data_in VCC " "Warning: Reduced register \"std_1c20:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_avalon_reg:the_cpu_nios2_avalon_reg\|internal_oci_ienable1\[29\]\" with stuck data_in port to stuck value VCC" {  } { { "cpu.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/cpu.vhd" 1177 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Info" "ICDB_SGATE_CDB_INFO_USING_PWRUP_DC" "std_1c20:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_avalon_reg:the_cpu_nios2_avalon_reg\|internal_oci_ienable1\[30\] High " "Info: Power-up level of register \"std_1c20:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_avalon_reg:the_cpu_nios2_avalon_reg\|internal_oci_ienable1\[30\]\" is not specified -- using power-up level of High to minimize register" {  } { { "cpu.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/cpu.vhd" 1177 -1 0 } }  } 0 0 "Power-up level of register \"%1!s!\" is not specified -- using power-up level of %2!s! to minimize register" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "std_1c20:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_avalon_reg:the_cpu_nios2_avalon_reg\|internal_oci_ienable1\[30\] data_in VCC " "Warning: Reduced register \"std_1c20:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_avalon_reg:the_cpu_nios2_avalon_reg\|internal_oci_ienable1\[30\]\" with stuck data_in port to stuck value VCC" {  } { { "cpu.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/cpu.vhd" 1177 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Info" "ICDB_SGATE_CDB_INFO_USING_PWRUP_DC" "std_1c20:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_avalon_reg:the_cpu_nios2_avalon_reg\|internal_oci_ienable1\[31\] High " "Info: Power-up level of register \"std_1c20:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_avalon_reg:the_cpu_nios2_avalon_reg\|internal_oci_ienable1\[31\]\" is not specified -- using power-up level of High to minimize register" {  } { { "cpu.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/cpu.vhd" 1177 -1 0 } }  } 0 0 "Power-up level of register \"%1!s!\" is not specified -- using power-up level of %2!s! to minimize register" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "std_1c20:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_avalon_reg:the_cpu_nios2_avalon_reg\|internal_oci_ienable1\[31\] data_in VCC " "Warning: Reduced register \"std_1c20:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_avalon_reg:the_cpu_nios2_avalon_reg\|internal_oci_ienable1\[31\]\" with stuck data_in port to stuck value VCC" {  } { { "cpu.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/cpu.vhd" 1177 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "std_1c20:inst\|connector_pll:the_connector_pll\|status_reg_out\[0\] data_in GND " "Warning: Reduced register \"std_1c20:inst\|connector_pll:the_connector_pll\|status_reg_out\[0\]\" with stuck data_in port to stuck value GND" {  } { { "connector_pll.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/connector_pll.vhd" 119 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "std_1c20:inst\|connector_pll:the_connector_pll\|status_reg_out\[1\] data_in GND " "Warning: Reduced register \"std_1c20:inst\|connector_pll:the_connector_pll\|status_reg_out\[1\]\" with stuck data_in port to stuck value GND" {  } { { "connector_pll.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/connector_pll.vhd" 119 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "std_1c20:inst\|connector_pll:the_connector_pll\|status_reg_out\[2\] data_in GND " "Warning: Reduced register \"std_1c20:inst\|connector_pll:the_connector_pll\|status_reg_out\[2\]\" with stuck data_in port to stuck value GND" {  } { { "connector_pll.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/connector_pll.vhd" 119 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "std_1c20:inst\|connector_pll:the_connector_pll\|status_reg_out\[3\] data_in GND " "Warning: Reduced register \"std_1c20:inst\|connector_pll:the_connector_pll\|status_reg_out\[3\]\" with stuck data_in port to stuck value GND" {  } { { "connector_pll.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/connector_pll.vhd" 119 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "std_1c20:inst\|connector_pll:the_connector_pll\|status_reg_out\[4\] data_in GND " "Warning: Reduced register \"std_1c20:inst\|connector_pll:the_connector_pll\|status_reg_out\[4\]\" with stuck data_in port to stuck value GND" {  } { { "connector_pll.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/connector_pll.vhd" 119 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "std_1c20:inst\|connector_pll:the_connector_pll\|status_reg_out\[5\] data_in GND " "Warning: Reduced register \"std_1c20:inst\|connector_pll:the_connector_pll\|status_reg_out\[5\]\" with stuck data_in port to stuck value GND" {  } { { "connector_pll.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/connector_pll.vhd" 119 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "std_1c20:inst\|connector_pll:the_connector_pll\|status_reg_out\[6\] data_in GND " "Warning: Reduced register \"std_1c20:inst\|connector_pll:the_connector_pll\|status_reg_out\[6\]\" with stuck data_in port to stuck value GND" {  } { { "connector_pll.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/connector_pll.vhd" 119 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "std_1c20:inst\|connector_pll:the_connector_pll\|status_reg_out\[7\] data_in GND " "Warning: Reduced register \"std_1c20:inst\|connector_pll:the_connector_pll\|status_reg_out\[7\]\" with stuck data_in port to stuck value GND" {  } { { "connector_pll.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/connector_pll.vhd" 119 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "std_1c20:inst\|connector_pll:the_connector_pll\|status_reg_out\[8\] data_in GND " "Warning: Reduced register \"std_1c20:inst\|connector_pll:the_connector_pll\|status_reg_out\[8\]\" with stuck data_in port to stuck value GND" {  } { { "connector_pll.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/connector_pll.vhd" 119 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "std_1c20:inst\|connector_pll:the_connector_pll\|status_reg_out\[9\] data_in GND " "Warning: Reduced register \"std_1c20:inst\|connector_pll:the_connector_pll\|status_reg_out\[9\]\" with stuck data_in port to stuck value GND" {  } { { "connector_pll.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/connector_pll.vhd" 119 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "std_1c20:inst\|connector_pll:the_connector_pll\|status_reg_out\[10\] data_in GND " "Warning: Reduced register \"std_1c20:inst\|connector_pll:the_connector_pll\|status_reg_out\[10\]\" with stuck data_in port to stuck value GND" {  } { { "connector_pll.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/connector_pll.vhd" 119 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "std_1c20:inst\|connector_pll:the_connector_pll\|status_reg_out\[11\] data_in GND " "Warning: Reduced register \"std_1c20:inst\|connector_pll:the_connector_pll\|status_reg_out\[11\]\" with stuck data_in port to stuck value GND" {  } { { "connector_pll.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/connector_pll.vhd" 119 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "std_1c20:inst\|connector_pll:the_connector_pll\|status_reg_out\[12\] data_in GND " "Warning: Reduced register \"std_1c20:inst\|connector_pll:the_connector_pll\|status_reg_out\[12\]\" with stuck data_in port to stuck value GND" {  } { { "connector_pll.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/connector_pll.vhd" 119 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "std_1c20:inst\|connector_pll:the_connector_pll\|status_reg_out\[13\] data_in GND " "Warning: Reduced register \"std_1c20:inst\|connector_pll:the_connector_pll\|status_reg_out\[13\]\" with stuck data_in port to stuck value GND" {  } { { "connector_pll.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/connector_pll.vhd" 119 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "std_1c20:inst\|connector_pll:the_connector_pll\|status_reg_out\[14\] data_in GND " "Warning: Reduced register \"std_1c20:inst\|connector_pll:the_connector_pll\|status_reg_out\[14\]\" with stuck data_in port to stuck value GND" {  } { { "connector_pll.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/connector_pll.vhd" 119 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "std_1c20:inst\|connector_pll:the_connector_pll\|status_reg_out\[15\] data_in GND " "Warning: Reduced register \"std_1c20:inst\|connector_pll:the_connector_pll\|status_reg_out\[15\]\" with stuck data_in port to stuck value GND" {  } { { "connector_pll.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/connector_pll.vhd" 119 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "std_1c20:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_oci_xbrk:the_cpu_nios2_oci_xbrk\|xbrk_break data_in GND " "Warning: Reduced register \"std_1c20:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_oci_xbrk:the_cpu_nios2_oci_xbrk\|xbrk_break\" with stuck data_in port to stuck value GND" {  } { { "cpu.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/cpu.vhd" 1701 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "std_1c20:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_oci_xbrk:the_cpu_nios2_oci_xbrk\|E_xbrk_goto0 data_in GND " "Warning: Reduced register \"std_1c20:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_oci_xbrk:the_cpu_nios2_oci_xbrk\|E_xbrk_goto0\" with stuck data_in port to stuck value GND" {  } { { "cpu.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/cpu.vhd" 1714 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "std_1c20:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_oci_xbrk:the_cpu_nios2_oci_xbrk\|E_xbrk_goto1 data_in GND " "Warning: Reduced register \"std_1c20:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_oci_xbrk:the_cpu_nios2_oci_xbrk\|E_xbrk_goto1\" with stuck data_in port to stuck value GND" {  } { { "cpu.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/cpu.vhd" 1715 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_HDR" "" "Warning: Synthesized away the following node(s):" { { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_SUB_HDR" "RAM " "Warning: Synthesized away the following RAM node(s):" { { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "std_1c20:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_oci_im:the_cpu_nios2_oci_im\|cpu_traceram_lpm_dram_bdp_component_module:cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_stv1:auto_generated\|q_a\[0\] " "Warning: Synthesized away node \"std_1c20:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_oci_im:the_cpu_nios2_oci_im\|cpu_traceram_lpm_dram_bdp_component_module:cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_stv1:auto_generated\|q_a\[0\]\"" {  } { { "db/altsyncram_stv1.tdf" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/db/altsyncram_stv1.tdf" 52 2 0 } } { "altsyncram.tdf" "" { Text "d:/altera/quartus60/libraries/megafunctions/altsyncram.tdf" 905 4 0 } } { "cpu.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/cpu.vhd" 3402 -1 0 } } { "cpu.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/cpu.vhd" 3563 -1 0 } } { "cpu.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/cpu.vhd" 4429 -1 0 } } { "cpu.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/cpu.vhd" 7884 -1 0 } } { "std_1c20.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/std_1c20.vhd" 9873 -1 0 } } { "standard.bdf" "" { Schematic "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/standard.bdf" { { 560 808 1272 1296 "inst" "" } } } }  } 0 0 "Synthesized away node \"%1!s!\"" 0 0} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "std_1c20:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_oci_im:the_cpu_nios2_oci_im\|cpu_traceram_lpm_dram_bdp_component_module:cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_stv1:auto_generated\|q_a\[1\] " "Warning: Synthesized away node \"std_1c20:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_oci_im:the_cpu_nios2_oci_im\|cpu_traceram_lpm_dram_bdp_component_module:cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_stv1:auto_generated\|q_a\[1\]\"" {  } { { "db/altsyncram_stv1.tdf" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/db/altsyncram_stv1.tdf" 83 2 0 } } { "altsyncram.tdf" "" { Text "d:/altera/quartus60/libraries/megafunctions/altsyncram.tdf" 905 4 0 } } { "cpu.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/cpu.vhd" 3402 -1 0 } } { "cpu.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/cpu.vhd" 3563 -1 0 } } { "cpu.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/cpu.vhd" 4429 -1 0 } } { "cpu.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/cpu.vhd" 7884 -1 0 } } { "std_1c20.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/std_1c20.vhd" 9873 -1 0 } } { "standard.bdf" "" { Schematic "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/standard.bdf" { { 560 808 1272 1296 "inst" "" } } } }  } 0 0 "Synthesized away node \"%1!s!\"" 0 0} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "std_1c20:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_oci_im:the_cpu_nios2_oci_im\|cpu_traceram_lpm_dram_bdp_component_module:cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_stv1:auto_generated\|q_a\[2\] " "Warning: Synthesized away node \"std_1c20:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_oci_im:the_cpu_nios2_oci_im\|cpu_traceram_lpm_dram_bdp_component_module:cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_stv1:auto_generated\|q_a\[2\]\"" {  } { { "db/altsyncram_stv1.tdf" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/db/altsyncram_stv1.tdf" 114 2 0 } } { "altsyncram.tdf" "" { Text "d:/altera/quartus60/libraries/megafunctions/altsyncram.tdf" 905 4 0 } } { "cpu.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/cpu.vhd" 3402 -1 0 } } { "cpu.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/cpu.vhd" 3563 -1 0 } } { "cpu.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/cpu.vhd" 4429 -1 0 } } { "cpu.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/cpu.vhd" 7884 -1 0 } } { "std_1c20.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/std_1c20.vhd" 9873 -1 0 } } { "standard.bdf" "" { Schematic "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/standard.bdf" { { 560 808 1272 1296 "inst" "" } } } }  } 0 0 "Synthesized away node \"%1!s!\"" 0 0} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "std_1c20:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_oci_im:the_cpu_nios2_oci_im\|cpu_traceram_lpm_dram_bdp_component_module:cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_stv1:auto_generated\|q_a\[3\] " "Warning: Synthesized away node \"std_1c20:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_oci_im:the_cpu_nios2_oci_im\|cpu_traceram_lpm_dram_bdp_component_module:cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_stv1:auto_generated\|q_a\[3\]\"" {  } { { "db/altsyncram_stv1.tdf" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/db/altsyncram_stv1.tdf" 145 2 0 } } { "altsyncram.tdf" "" { Text "d:/altera/quartus60/libraries/megafunctions/altsyncram.tdf" 905 4 0 } } { "cpu.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/cpu.vhd" 3402 -1 0 } } { "cpu.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/cpu.vhd" 3563 -1 0 } } { "cpu.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/cpu.vhd" 4429 -1 0 } } { "cpu.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/cpu.vhd" 7884 -1 0 } } { "std_1c20.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/std_1c20.vhd" 9873 -1 0 } } { "standard.bdf" "" { Schematic "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/standard.bdf" { { 560 808 1272 1296 "inst" "" } } } }  } 0 0 "Synthesized away node \"%1!s!\"" 0 0} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "std_1c20:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_oci_im:the_cpu_nios2_oci_im\|cpu_traceram_lpm_dram_bdp_component_module:cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_stv1:auto_generated\|q_a\[4\] " "Warning: Synthesized away node \"std_1c20:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_oci_im:the_cpu_nios2_oci_im\|cpu_traceram_lpm_dram_bdp_component_module:cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_stv1:auto_generated\|q_a\[4\]\"" {  } { { "db/altsyncram_stv1.tdf" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/db/altsyncram_stv1.tdf" 176 2 0 } } { "altsyncram.tdf" "" { Text "d:/altera/quartus60/libraries/megafunctions/altsyncram.tdf" 905 4 0 } } { "cpu.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/cpu.vhd" 3402 -1 0 } } { "cpu.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/cpu.vhd" 3563 -1 0 } } { "cpu.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/cpu.vhd" 4429 -1 0 } } { "cpu.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/cpu.vhd" 7884 -1 0 } } { "std_1c20.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/std_1c20.vhd" 9873 -1 0 } } { "standard.bdf" "" { Schematic "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/standard.bdf" { { 560 808 1272 1296 "inst" "" } } } }  } 0 0 "Synthesized away node \"%1!s!\"" 0 0} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "std_1c20:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_oci_im:the_cpu_nios2_oci_im\|cpu_traceram_lpm_dram_bdp_component_module:cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_stv1:auto_generated\|q_a\[5\] " "Warning: Synthesized away node \"std_1c20:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_oci_im:the_cpu_nios2_oci_im\|cpu_traceram_lpm_dram_bdp_component_module:cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_stv1:auto_generated\|q_a\[5\]\"" {  } { { "db/altsyncram_stv1.tdf" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/db/altsyncram_stv1.tdf" 207 2 0 } } { "altsyncram.tdf" "" { Text "d:/altera/quartus60/libraries/megafunctions/altsyncram.tdf" 905 4 0 } } { "cpu.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/cpu.vhd" 3402 -1 0 } } { "cpu.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/cpu.vhd" 3563 -1 0 } } { "cpu.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/cpu.vhd" 4429 -1 0 } } { "cpu.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/cpu.vhd" 7884 -1 0 } } { "std_1c20.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/std_1c20.vhd" 9873 -1 0 } } { "standard.bdf" "" { Schematic "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/standard.bdf" { { 560 808 1272 1296 "inst" "" } } } }  } 0 0 "Synthesized away node \"%1!s!\"" 0 0} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "std_1c20:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_oci_im:the_cpu_nios2_oci_im\|cpu_traceram_lpm_dram_bdp_component_module:cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_stv1:auto_generated\|q_a\[6\] " "Warning: Synthesized away node \"std_1c20:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_oci_im:the_cpu_nios2_oci_im\|cpu_traceram_lpm_dram_bdp_component_module:cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_stv1:auto_generated\|q_a\[6\]\"" {  } { { "db/altsyncram_stv1.tdf" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/db/altsyncram_stv1.tdf" 238 2 0 } } { "altsyncram.tdf" "" { Text "d:/altera/quartus60/libraries/megafunctions/altsyncram.tdf" 905 4 0 } } { "cpu.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/cpu.vhd" 3402 -1 0 } } { "cpu.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/cpu.vhd" 3563 -1 0 } } { "cpu.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/cpu.vhd" 4429 -1 0 } } { "cpu.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/cpu.vhd" 7884 -1 0 } } { "std_1c20.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/std_1c20.vhd" 9873 -1 0 } } { "standard.bdf" "" { Schematic "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/standard.bdf" { { 560 808 1272 1296 "inst" "" } } } }  } 0 0 "Synthesized away node \"%1!s!\"" 0 0} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "std_1c20:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_oci_im:the_cpu_nios2_oci_im\|cpu_traceram_lpm_dram_bdp_component_module:cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_stv1:auto_generated\|q_a\[7\] " "Warning: Synthesized away node \"std_1c20:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_oci_im:the_cpu_nios2_oci_im\|cpu_traceram_lpm_dram_bdp_component_module:cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_stv1:auto_generated\|q_a\[7\]\"" {  } { { "db/altsyncram_stv1.tdf" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/db/altsyncram_stv1.tdf" 269 2 0 } } { "altsyncram.tdf" "" { Text "d:/altera/quartus60/libraries/megafunctions/altsyncram.tdf" 905 4 0 } } { "cpu.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/cpu.vhd" 3402 -1 0 } } { "cpu.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/cpu.vhd" 3563 -1 0 } } { "cpu.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/cpu.vhd" 4429 -1 0 } } { "cpu.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/cpu.vhd" 7884 -1 0 } } { "std_1c20.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/std_1c20.vhd" 9873 -1 0 } } { "standard.bdf" "" { Schematic "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/standard.bdf" { { 560 808 1272 1296 "inst" "" } } } }  } 0 0 "Synthesized away node \"%1!s!\"" 0 0} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "std_1c20:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_oci_im:the_cpu_nios2_oci_im\|cpu_traceram_lpm_dram_bdp_component_module:cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_stv1:auto_generated\|q_a\[8\] " "Warning: Synthesized away node \"std_1c20:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_oci_im:the_cpu_nios2_oci_im\|cpu_traceram_lpm_dram_bdp_component_module:cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_stv1:auto_generated\|q_a\[8\]\"" {  } { { "db/altsyncram_stv1.tdf" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/db/altsyncram_stv1.tdf" 300 2 0 } } { "altsyncram.tdf" "" { Text "d:/altera/quartus60/libraries/megafunctions/altsyncram.tdf" 905 4 0 } } { "cpu.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/cpu.vhd" 3402 -1 0 } } { "cpu.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/cpu.vhd" 3563 -1 0 } } { "cpu.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/cpu.vhd" 4429 -1 0 } } { "cpu.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/cpu.vhd" 7884 -1 0 } } { "std_1c20.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/std_1c20.vhd" 9873 -1 0 } } { "standard.bdf" "" { Schematic "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/standard.bdf" { { 560 808 1272 1296 "inst" "" } } } }  } 0 0 "Synthesized away node \"%1!s!\"" 0 0} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "std_1c20:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_oci_im:the_cpu_nios2_oci_im\|cpu_traceram_lpm_dram_bdp_component_module:cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_stv1:auto_generated\|q_a\[9\] " "Warning: Synthesized away node \"std_1c20:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_oci_im:the_cpu_nios2_oci_im\|cpu_traceram_lpm_dram_bdp_component_module:cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_stv1:auto_generated\|q_a\[9\]\"" {  } { { "db/altsyncram_stv1.tdf" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/db/altsyncram_stv1.tdf" 331 2 0 } } { "altsyncram.tdf" "" { Text "d:/altera/quartus60/libraries/megafunctions/altsyncram.tdf" 905 4 0 } } { "cpu.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/cpu.vhd" 3402 -1 0 } } { "cpu.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/cpu.vhd" 3563 -1 0 } } { "cpu.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/cpu.vhd" 4429 -1 0 } } { "cpu.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/cpu.vhd" 7884 -1 0 } } { "std_1c20.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/std_1c20.vhd" 9873 -1 0 } } { "standard.bdf" "" { Schematic "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/standard.bdf" { { 560 808 1272 1296 "inst" "" } } } }  } 0 0 "Synthesized away node \"%1!s!\"" 0 0} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "std_1c20:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_oci_im:the_cpu_nios2_oci_im\|cpu_traceram_lpm_dram_bdp_component_module:cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_stv1:auto_generated\|q_a\[10\] " "Warning: Synthesized away node \"std_1c20:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_oci_im:the_cpu_nios2_oci_im\|cpu_traceram_lpm_dram_bdp_component_module:cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_stv1:auto_generated\|q_a\[10\]\"" {  } { { "db/altsyncram_stv1.tdf" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/db/altsyncram_stv1.tdf" 362 2 0 } } { "altsyncram.tdf" "" { Text "d:/altera/quartus60/libraries/megafunctions/altsyncram.tdf" 905 4 0 } } { "cpu.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/cpu.vhd" 3402 -1 0 } } { "cpu.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/cpu.vhd" 3563 -1 0 } } { "cpu.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/cpu.vhd" 4429 -1 0 } } { "cpu.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/cpu.vhd" 7884 -1 0 } } { "std_1c20.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/std_1c20.vhd" 9873 -1 0 } } { "standard.bdf" "" { Schematic "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/standard.bdf" { { 560 808 1272 1296 "inst" "" } } } }  } 0 0 "Synthesized away node \"%1!s!\"" 0 0} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "std_1c20:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_oci_im:the_cpu_nios2_oci_im\|cpu_traceram_lpm_dram_bdp_component_module:cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_stv1:auto_generated\|q_a\[11\] " "Warning: Synthesized away node \"std_1c20:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_oci_im:the_cpu_nios2_oci_im\|cpu_traceram_lpm_dram_bdp_component_module:cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_stv1:auto_generated\|q_a\[11\]\"" {  } { { "db/altsyncram_stv1.tdf" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/db/altsyncram_stv1.tdf" 393 2 0 } } { "altsyncram.tdf" "" { Text "d:/altera/quartus60/libraries/megafunctions/altsyncram.tdf" 905 4 0 } } { "cpu.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/cpu.vhd" 3402 -1 0 } } { "cpu.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/cpu.vhd" 3563 -1 0 } } { "cpu.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/cpu.vhd" 4429 -1 0 } } { "cpu.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/cpu.vhd" 7884 -1 0 } } { "std_1c20.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/std_1c20.vhd" 9873 -1 0 } } { "standard.bdf" "" { Schematic "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/standard.bdf" { { 560 808 1272 1296 "inst" "" } } } }  } 0 0 "Synthesized away node \"%1!s!\"" 0 0} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "std_1c20:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_oci_im:the_cpu_nios2_oci_im\|cpu_traceram_lpm_dram_bdp_component_module:cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_stv1:auto_generated\|q_a\[12\] " "Warning: Synthesized away node \"std_1c20:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_oci_im:the_cpu_nios2_oci_im\|cpu_traceram_lpm_dram_bdp_component_module:cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_stv1:auto_generated\|q_a\[12\]\"" {  } { { "db/altsyncram_stv1.tdf" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/db/altsyncram_stv1.tdf" 424 2 0 } } { "altsyncram.tdf" "" { Text "d:/altera/quartus60/libraries/megafunctions/altsyncram.tdf" 905 4 0 } } { "cpu.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/cpu.vhd" 3402 -1 0 } } { "cpu.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/cpu.vhd" 3563 -1 0 } } { "cpu.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/cpu.vhd" 4429 -1 0 } } { "cpu.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/cpu.vhd" 7884 -1 0 } } { "std_1c20.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/std_1c20.vhd" 9873 -1 0 } } { "standard.bdf" "" { Schematic "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/standard.bdf" { { 560 808 1272 1296 "inst" "" } } } }  } 0 0 "Synthesized away node \"%1!s!\"" 0 0} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "std_1c20:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_oci_im:the_cpu_nios2_oci_im\|cpu_traceram_lpm_dram_bdp_component_module:cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_stv1:auto_generated\|q_a\[13\] " "Warning: Synthesized away node \"std_1c20:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_oci_im:the_cpu_nios2_oci_im\|cpu_traceram_lpm_dram_bdp_component_module:cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_stv1:auto_generated\|q_a\[13\]\"" {  } { { "db/altsyncram_stv1.tdf" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/db/altsyncram_stv1.tdf" 455 2 0 } } { "altsyncram.tdf" "" { Text "d:/altera/quartus60/libraries/megafunctions/altsyncram.tdf" 905 4 0 } } { "cpu.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/cpu.vhd" 3402 -1 0 } } { "cpu.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/cpu.vhd" 3563 -1 0 } } { "cpu.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/cpu.vhd" 4429 -1 0 } } { "cpu.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/cpu.vhd" 7884 -1 0 } } { "std_1c20.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/std_1c20.vhd" 9873 -1 0 } } { "standard.bdf" "" { Schematic "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/standard.bdf" { { 560 808 1272 1296 "inst" "" } } } }  } 0 0 "Synthesized away node \"%1!s!\"" 0 0} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "std_1c20:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_oci_im:the_cpu_nios2_oci_im\|cpu_traceram_lpm_dram_bdp_component_module:cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_stv1:auto_generated\|q_a\[14\] " "Warning: Synthesized away node \"std_1c20:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_oci_im:the_cpu_nios2_oci_im\|cpu_traceram_lpm_dram_bdp_component_module:cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_stv1:auto_generated\|q_a\[14\]\"" {  } { { "db/altsyncram_stv1.tdf" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/db/altsyncram_stv1.tdf" 486 2 0 } } { "altsyncram.tdf" "" { Text "d:/altera/quartus60/libraries/megafunctions/altsyncram.tdf" 905 4 0 } } { "cpu.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/cpu.vhd" 3402 -1 0 } } { "cpu.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/cpu.vhd" 3563 -1 0 } } { "cpu.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/cpu.vhd" 4429 -1 0 } } { "cpu.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/cpu.vhd" 7884 -1 0 } } { "std_1c20.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/std_1c20.vhd" 9873 -1 0 } } { "standard.bdf" "" { Schematic "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/standard.bdf" { { 560 808 1272 1296 "inst" "" } } } }  } 0 0 "Synthesized away node \"%1!s!\"" 0 0} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "std_1c20:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_oci_im:the_cpu_nios2_oci_im\|cpu_traceram_lpm_dram_bdp_component_module:cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_stv1:auto_generated\|q_a\[15\] " "Warning: Synthesized away node \"std_1c20:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_oci_im:the_cpu_nios2_oci_im\|cpu_traceram_lpm_dram_bdp_component_module:cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_stv1:auto_generated\|q_a\[15\]\"" {  } { { "db/altsyncram_stv1.tdf" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/db/altsyncram_stv1.tdf" 517 2 0 } } { "altsyncram.tdf" "" { Text "d:/altera/quartus60/libraries/megafunctions/altsyncram.tdf" 905 4 0 } } { "cpu.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/cpu.vhd" 3402 -1 0 } } { "cpu.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/cpu.vhd" 3563 -1 0 } } { "cpu.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/cpu.vhd" 4429 -1 0 } } { "cpu.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/cpu.vhd" 7884 -1 0 } } { "std_1c20.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/std_1c20.vhd" 9873 -1 0 } } { "standard.bdf" "" { Schematic "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/standard.bdf" { { 560 808 1272 1296 "inst" "" } } } }  } 0 0 "Synthesized away node \"%1!s!\"" 0 0} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "std_1c20:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_oci_im:the_cpu_nios2_oci_im\|cpu_traceram_lpm_dram_bdp_component_module:cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_stv1:auto_generated\|q_a\[16\] " "Warning: Synthesized away node \"std_1c20:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_oci_im:the_cpu_nios2_oci_im\|cpu_traceram_lpm_dram_bdp_component_module:cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_stv1:auto_generated\|q_a\[16\]\"" {  } { { "db/altsyncram_stv1.tdf" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/db/altsyncram_stv1.tdf" 548 2 0 } } { "altsyncram.tdf" "" { Text "d:/altera/quartus60/libraries/megafunctions/altsyncram.tdf" 905 4 0 } } { "cpu.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/cpu.vhd" 3402 -1 0 } } { "cpu.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/cpu.vhd" 3563 -1 0 } } { "cpu.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/cpu.vhd" 4429 -1 0 } } { "cpu.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/cpu.vhd" 7884 -1 0 } } { "std_1c20.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/std_1c20.vhd" 9873 -1 0 } } { "standard.bdf" "" { Schematic "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/standard.bdf" { { 560 808 1272 1296 "inst" "" } } } }  } 0 0 "Synthesized away node \"%1!s!\"" 0 0} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "std_1c20:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_oci_im:the_cpu_nios2_oci_im\|cpu_traceram_lpm_dram_bdp_component_module:cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_stv1:auto_generated\|q_a\[17\] " "Warning: Synthesized away node \"std_1c20:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_oci_im:the_cpu_nios2_oci_im\|cpu_traceram_lpm_dram_bdp_component_module:cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_stv1:auto_generated\|q_a\[17\]\"" {  } { { "db/altsyncram_stv1.tdf" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/db/altsyncram_stv1.tdf" 579 2 0 } } { "altsyncram.tdf" "" { Text "d:/altera/quartus60/libraries/megafunctions/altsyncram.tdf" 905 4 0 } } { "cpu.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/cpu.vhd" 3402 -1 0 } } { "cpu.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/cpu.vhd" 3563 -1 0 } } { "cpu.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/cpu.vhd" 4429 -1 0 } } { "cpu.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/cpu.vhd" 7884 -1 0 } } { "std_1c20.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/std_1c20.vhd" 9873 -1 0 } } { "standard.bdf" "" { Schematic "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/standard.bdf" { { 560 808 1272 1296 "inst" "" } } } }  } 0 0 "Synthesized away node \"%1!s!\"" 0 0} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "std_1c20:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_oci_im:the_cpu_nios2_oci_im\|cpu_traceram_lpm_dram_bdp_component_module:cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_stv1:auto_generated\|q_a\[18\] " "Warning: Synthesized away node \"std_1c20:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_oci_im:the_cpu_nios2_oci_im\|cpu_traceram_lpm_dram_bdp_component_module:cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_stv1:auto_generated\|q_a\[18\]\"" {  } { { "db/altsyncram_stv1.tdf" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/db/altsyncram_stv1.tdf" 610 2 0 } } { "altsyncram.tdf" "" { Text "d:/altera/quartus60/libraries/megafunctions/altsyncram.tdf" 905 4 0 } } { "cpu.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/cpu.vhd" 3402 -1 0 } } { "cpu.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/cpu.vhd" 3563 -1 0 } } { "cpu.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/cpu.vhd" 4429 -1 0 } } { "cpu.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/cpu.vhd" 7884 -1 0 } } { "std_1c20.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/std_1c20.vhd" 9873 -1 0 } } { "standard.bdf" "" { Schematic "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/standard.bdf" { { 560 808 1272 1296 "inst" "" } } } }  } 0 0 "Synthesized away node \"%1!s!\"" 0 0} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "std_1c20:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_oci_im:the_cpu_nios2_oci_im\|cpu_traceram_lpm_dram_bdp_component_module:cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_stv1:auto_generated\|q_a\[19\] " "Warning: Synthesized away node \"std_1c20:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_oci_im:the_cpu_nios2_oci_im\|cpu_traceram_lpm_dram_bdp_component_module:cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_stv1:auto_generated\|q_a\[19\]\"" {  } { { "db/altsyncram_stv1.tdf" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/db/altsyncram_stv1.tdf" 641 2 0 } } { "altsyncram.tdf" "" { Text "d:/altera/quartus60/libraries/megafunctions/altsyncram.tdf" 905 4 0 } } { "cpu.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/cpu.vhd" 3402 -1 0 } } { "cpu.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/cpu.vhd" 3563 -1 0 } } { "cpu.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/cpu.vhd" 4429 -1 0 } } { "cpu.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/cpu.vhd" 7884 -1 0 } } { "std_1c20.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/std_1c20.vhd" 9873 -1 0 } } { "standard.bdf" "" { Schematic "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/standard.bdf" { { 560 808 1272 1296 "inst" "" } } } }  } 0 0 "Synthesized away node \"%1!s!\"" 0 0} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "std_1c20:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_oci_im:the_cpu_nios2_oci_im\|cpu_traceram_lpm_dram_bdp_component_module:cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_stv1:auto_generated\|q_a\[20\] " "Warning: Synthesized away node \"std_1c20:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_oci_im:the_cpu_nios2_oci_im\|cpu_traceram_lpm_dram_bdp_component_module:cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_stv1:auto_generated\|q_a\[20\]\"" {  } { { "db/altsyncram_stv1.tdf" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/db/altsyncram_stv1.tdf" 672 2 0 } } { "altsyncram.tdf" "" { Text "d:/altera/quartus60/libraries/megafunctions/altsyncram.tdf" 905 4 0 } } { "cpu.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/cpu.vhd" 3402 -1 0 } } { "cpu.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/cpu.vhd" 3563 -1 0 } } { "cpu.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/cpu.vhd" 4429 -1 0 } } { "cpu.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/cpu.vhd" 7884 -1 0 } } { "std_1c20.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/std_1c20.vhd" 9873 -1 0 } } { "standard.bdf" "" { Schematic "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/standard.bdf" { { 560 808 1272 1296 "inst" "" } } } }  } 0 0 "Synthesized away node \"%1!s!\"" 0 0} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "std_1c20:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_oci_im:the_cpu_nios2_oci_im\|cpu_traceram_lpm_dram_bdp_component_module:cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_stv1:auto_generated\|q_a\[21\] " "Warning: Synthesized away node \"std_1c20:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_oci_im:the_cpu_nios2_oci_im\|cpu_traceram_lpm_dram_bdp_component_module:cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_stv1:auto_generated\|q_a\[21\]\"" {  } { { "db/altsyncram_stv1.tdf" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/db/altsyncram_stv1.tdf" 703 2 0 } } { "altsyncram.tdf" "" { Text "d:/altera/quartus60/libraries/megafunctions/altsyncram.tdf" 905 4 0 } } { "cpu.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/cpu.vhd" 3402 -1 0 } } { "cpu.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/cpu.vhd" 3563 -1 0 } } { "cpu.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/cpu.vhd" 4429 -1 0 } } { "cpu.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/cpu.vhd" 7884 -1 0 } } { "std_1c20.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/std_1c20.vhd" 9873 -1 0 } } { "standard.bdf" "" { Schematic "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/standard.bdf" { { 560 808 1272 1296 "inst" "" } } } }  } 0 0 "Synthesized away node \"%1!s!\"" 0 0} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "std_1c20:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_oci_im:the_cpu_nios2_oci_im\|cpu_traceram_lpm_dram_bdp_component_module:cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_stv1:auto_generated\|q_a\[22\] " "Warning: Synthesized away node \"std_1c20:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_oci_im:the_cpu_nios2_oci_im\|cpu_traceram_lpm_dram_bdp_component_module:cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_stv1:auto_generated\|q_a\[22\]\"" {  } { { "db/altsyncram_stv1.tdf" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/db/altsyncram_stv1.tdf" 734 2 0 } } { "altsyncram.tdf" "" { Text "d:/altera/quartus60/libraries/megafunctions/altsyncram.tdf" 905 4 0 } } { "cpu.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/cpu.vhd" 3402 -1 0 } } { "cpu.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/cpu.vhd" 3563 -1 0 } } { "cpu.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/cpu.vhd" 4429 -1 0 } } { "cpu.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/cpu.vhd" 7884 -1 0 } } { "std_1c20.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/std_1c20.vhd" 9873 -1 0 } } { "standard.bdf" "" { Schematic "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/standard.bdf" { { 560 808 1272 1296 "inst" "" } } } }  } 0 0 "Synthesized away node \"%1!s!\"" 0 0} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "std_1c20:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_oci_im:the_cpu_nios2_oci_im\|cpu_traceram_lpm_dram_bdp_component_module:cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_stv1:auto_generated\|q_a\[23\] " "Warning: Synthesized away node \"std_1c20:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_oci_im:the_cpu_nios2_oci_im\|cpu_traceram_lpm_dram_bdp_component_module:cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_stv1:auto_generated\|q_a\[23\]\"" {  } { { "db/altsyncram_stv1.tdf" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/db/altsyncram_stv1.tdf" 765 2 0 } } { "altsyncram.tdf" "" { Text "d:/altera/quartus60/libraries/megafunctions/altsyncram.tdf" 905 4 0 } } { "cpu.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/cpu.vhd" 3402 -1 0 } } { "cpu.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/cpu.vhd" 3563 -1 0 } } { "cpu.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/cpu.vhd" 4429 -1 0 } } { "cpu.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/cpu.vhd" 7884 -1 0 } } { "std_1c20.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/std_1c20.vhd" 9873 -1 0 } } { "standard.bdf" "" { Schematic "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/standard.bdf" { { 560 808 1272 1296 "inst" "" } } } }  } 0 0 "Synthesized away node \"%1!s!\"" 0 0} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "std_1c20:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_oci_im:the_cpu_nios2_oci_im\|cpu_traceram_lpm_dram_bdp_component_module:cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_stv1:auto_generated\|q_a\[24\] " "Warning: Synthesized away node \"std_1c20:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_oci_im:the_cpu_nios2_oci_im\|cpu_traceram_lpm_dram_bdp_component_module:cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_stv1:auto_generated\|q_a\[24\]\"" {  } { { "db/altsyncram_stv1.tdf" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/db/altsyncram_stv1.tdf" 796 2 0 } } { "altsyncram.tdf" "" { Text "d:/altera/quartus60/libraries/megafunctions/altsyncram.tdf" 905 4 0 } } { "cpu.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/cpu.vhd" 3402 -1 0 } } { "cpu.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/cpu.vhd" 3563 -1 0 } } { "cpu.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/cpu.vhd" 4429 -1 0 } } { "cpu.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/cpu.vhd" 7884 -1 0 } } { "std_1c20.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/std_1c20.vhd" 9873 -1 0 } } { "standard.bdf" "" { Schematic "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/standard.bdf" { { 560 808 1272 1296 "inst" "" } } } }  } 0 0 "Synthesized away node \"%1!s!\"" 0 0} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "std_1c20:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_oci_im:the_cpu_nios2_oci_im\|cpu_traceram_lpm_dram_bdp_component_module:cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_stv1:auto_generated\|q_a\[25\] " "Warning: Synthesized away node \"std_1c20:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_oci_im:the_cpu_nios2_oci_im\|cpu_traceram_lpm_dram_bdp_component_module:cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_stv1:auto_generated\|q_a\[25\]\"" {  } { { "db/altsyncram_stv1.tdf" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/db/altsyncram_stv1.tdf" 827 2 0 } } { "altsyncram.tdf" "" { Text "d:/altera/quartus60/libraries/megafunctions/altsyncram.tdf" 905 4 0 } } { "cpu.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/cpu.vhd" 3402 -1 0 } } { "cpu.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/cpu.vhd" 3563 -1 0 } } { "cpu.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/cpu.vhd" 4429 -1 0 } } { "cpu.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/cpu.vhd" 7884 -1 0 } } { "std_1c20.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/std_1c20.vhd" 9873 -1 0 } } { "standard.bdf" "" { Schematic "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/standard.bdf" { { 560 808 1272 1296 "inst" "" } } } }  } 0 0 "Synthesized away node \"%1!s!\"" 0 0} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "std_1c20:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_oci_im:the_cpu_nios2_oci_im\|cpu_traceram_lpm_dram_bdp_component_module:cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_stv1:auto_generated\|q_a\[26\] " "Warning: Synthesized away node \"std_1c20:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_oci_im:the_cpu_nios2_oci_im\|cpu_traceram_lpm_dram_bdp_component_module:cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_stv1:auto_generated\|q_a\[26\]\"" {  } { { "db/altsyncram_stv1.tdf" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/db/altsyncram_stv1.tdf" 858 2 0 } } { "altsyncram.tdf" "" { Text "d:/altera/quartus60/libraries/megafunctions/altsyncram.tdf" 905 4 0 } } { "cpu.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/cpu.vhd" 3402 -1 0 } } { "cpu.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/cpu.vhd" 3563 -1 0 } } { "cpu.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/cpu.vhd" 4429 -1 0 } } { "cpu.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/cpu.vhd" 7884 -1 0 } } { "std_1c20.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/std_1c20.vhd" 9873 -1 0 } } { "standard.bdf" "" { Schematic "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/standard.bdf" { { 560 808 1272 1296 "inst" "" } } } }  } 0 0 "Synthesized away node \"%1!s!\"" 0 0} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "std_1c20:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_oci_im:the_cpu_nios2_oci_im\|cpu_traceram_lpm_dram_bdp_component_module:cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_stv1:auto_generated\|q_a\[27\] " "Warning: Synthesized away node \"std_1c20:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_oci_im:the_cpu_nios2_oci_im\|cpu_traceram_lpm_dram_bdp_component_module:cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_stv1:auto_generated\|q_a\[27\]\"" {  } { { "db/altsyncram_stv1.tdf" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/db/altsyncram_stv1.tdf" 889 2 0 } } { "altsyncram.tdf" "" { Text "d:/altera/quartus60/libraries/megafunctions/altsyncram.tdf" 905 4 0 } } { "cpu.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/cpu.vhd" 3402 -1 0 } } { "cpu.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/cpu.vhd" 3563 -1 0 } } { "cpu.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/cpu.vhd" 4429 -1 0 } } { "cpu.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/cpu.vhd" 7884 -1 0 } } { "std_1c20.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/std_1c20.vhd" 9873 -1 0 } } { "standard.bdf" "" { Schematic "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/standard.bdf" { { 560 808 1272 1296 "inst" "" } } } }  } 0 0 "Synthesized away node \"%1!s!\"" 0 0} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "std_1c20:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_oci_im:the_cpu_nios2_oci_im\|cpu_traceram_lpm_dram_bdp_component_module:cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_stv1:auto_generated\|q_a\[28\] " "Warning: Synthesized away node \"std_1c20:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_oci_im:the_cpu_nios2_oci_im\|cpu_traceram_lpm_dram_bdp_component_module:cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_stv1:auto_generated\|q_a\[28\]\"" {  } { { "db/altsyncram_stv1.tdf" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/db/altsyncram_stv1.tdf" 920 2 0 } } { "altsyncram.tdf" "" { Text "d:/altera/quartus60/libraries/megafunctions/altsyncram.tdf" 905 4 0 } } { "cpu.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/cpu.vhd" 3402 -1 0 } } { "cpu.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/cpu.vhd" 3563 -1 0 } } { "cpu.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/cpu.vhd" 4429 -1 0 } } { "cpu.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/cpu.vhd" 7884 -1 0 } } { "std_1c20.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/std_1c20.vhd" 9873 -1 0 } } { "standard.bdf" "" { Schematic "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/standard.bdf" { { 560 808 1272 1296 "inst" "" } } } }  } 0 0 "Synthesized away node \"%1!s!\"" 0 0} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "std_1c20:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_oci_im:the_cpu_nios2_oci_im\|cpu_traceram_lpm_dram_bdp_component_module:cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_stv1:auto_generated\|q_a\[29\] " "Warning: Synthesized away node \"std_1c20:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_oci_im:the_cpu_nios2_oci_im\|cpu_traceram_lpm_dram_bdp_component_module:cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_stv1:auto_generated\|q_a\[29\]\"" {  } { { "db/altsyncram_stv1.tdf" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/db/altsyncram_stv1.tdf" 951 2 0 } } { "altsyncram.tdf" "" { Text "d:/altera/quartus60/libraries/megafunctions/altsyncram.tdf" 905 4 0 } } { "cpu.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/cpu.vhd" 3402 -1 0 } } { "cpu.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/cpu.vhd" 3563 -1 0 } } { "cpu.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/cpu.vhd" 4429 -1 0 } } { "cpu.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/cpu.vhd" 7884 -1 0 } } { "std_1c20.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/std_1c20.vhd" 9873 -1 0 } } { "standard.bdf" "" { Schematic "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/standard.bdf" { { 560 808 1272 1296 "inst" "" } } } }  } 0 0 "Synthesized away node \"%1!s!\"" 0 0} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "std_1c20:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_oci_im:the_cpu_nios2_oci_im\|cpu_traceram_lpm_dram_bdp_component_module:cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_stv1:auto_generated\|q_a\[30\] " "Warning: Synthesized away node \"std_1c20:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_oci_im:the_cpu_nios2_oci_im\|cpu_traceram_lpm_dram_bdp_component_module:cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_stv1:auto_generated\|q_a\[30\]\"" {  } { { "db/altsyncram_stv1.tdf" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/db/altsyncram_stv1.tdf" 982 2 0 } } { "altsyncram.tdf" "" { Text "d:/altera/quartus60/libraries/megafunctions/altsyncram.tdf" 905 4 0 } } { "cpu.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/cpu.vhd" 3402 -1 0 } } { "cpu.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/cpu.vhd" 3563 -1 0 } } { "cpu.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/cpu.vhd" 4429 -1 0 } } { "cpu.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/cpu.vhd" 7884 -1 0 } } { "std_1c20.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/std_1c20.vhd" 9873 -1 0 } } { "standard.bdf" "" { Schematic "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/standard.bdf" { { 560 808 1272 1296 "inst" "" } } } }  } 0 0 "Synthesized away node \"%1!s!\"" 0 0} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "std_1c20:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_oci_im:the_cpu_nios2_oci_im\|cpu_traceram_lpm_dram_bdp_component_module:cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_stv1:auto_generated\|q_a\[31\] " "Warning: Synthesized away node \"std_1c20:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_oci_im:the_cpu_nios2_oci_im\|cpu_traceram_lpm_dram_bdp_component_module:cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_stv1:auto_generated\|q_a\[31\]\"" {  } { { "db/altsyncram_stv1.tdf" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/db/altsyncram_stv1.tdf" 1013 2 0 } } { "altsyncram.tdf" "" { Text "d:/altera/quartus60/libraries/megafunctions/altsyncram.tdf" 905 4 0 } } { "cpu.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/cpu.vhd" 3402 -1 0 } } { "cpu.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/cpu.vhd" 3563 -1 0 } } { "cpu.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/cpu.vhd" 4429 -1 0 } } { "cpu.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/cpu.vhd" 7884 -1 0 } } { "std_1c20.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/std_1c20.vhd" 9873 -1 0 } } { "standard.bdf" "" { Schematic "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/standard.bdf" { { 560 808 1272 1296 "inst" "" } } } }  } 0 0 "Synthesized away node \"%1!s!\"" 0 0} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "std_1c20:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_oci_im:the_cpu_nios2_oci_im\|cpu_traceram_lpm_dram_bdp_component_module:cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_stv1:auto_generated\|q_a\[32\] " "Warning: Synthesized away node \"std_1c20:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_oci_im:the_cpu_nios2_oci_im\|cpu_traceram_lpm_dram_bdp_component_module:cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_stv1:auto_generated\|q_a\[32\]\"" {  } { { "db/altsyncram_stv1.tdf" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/db/altsyncram_stv1.tdf" 1044 2 0 } } { "altsyncram.tdf" "" { Text "d:/altera/quartus60/libraries/megafunctions/altsyncram.tdf" 905 4 0 } } { "cpu.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/cpu.vhd" 3402 -1 0 } } { "cpu.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/cpu.vhd" 3563 -1 0 } } { "cpu.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/cpu.vhd" 4429 -1 0 } } { "cpu.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/cpu.vhd" 7884 -1 0 } } { "std_1c20.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/std_1c20.vhd" 9873 -1 0 } } { "standard.bdf" "" { Schematic "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/standard.bdf" { { 560 808 1272 1296 "inst" "" } } } }  } 0 0 "Synthesized away node \"%1!s!\"" 0 0} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "std_1c20:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_oci_im:the_cpu_nios2_oci_im\|cpu_traceram_lpm_dram_bdp_component_module:cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_stv1:auto_generated\|q_a\[33\] " "Warning: Synthesized away node \"std_1c20:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_oci_im:the_cpu_nios2_oci_im\|cpu_traceram_lpm_dram_bdp_component_module:cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_stv1:auto_generated\|q_a\[33\]\"" {  } { { "db/altsyncram_stv1.tdf" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/db/altsyncram_stv1.tdf" 1075 2 0 } } { "altsyncram.tdf" "" { Text "d:/altera/quartus60/libraries/megafunctions/altsyncram.tdf" 905 4 0 } } { "cpu.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/cpu.vhd" 3402 -1 0 } } { "cpu.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/cpu.vhd" 3563 -1 0 } } { "cpu.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/cpu.vhd" 4429 -1 0 } } { "cpu.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/cpu.vhd" 7884 -1 0 } } { "std_1c20.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/std_1c20.vhd" 9873 -1 0 } } { "standard.bdf" "" { Schematic "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/standard.bdf" { { 560 808 1272 1296 "inst" "" } } } }  } 0 0 "Synthesized away node \"%1!s!\"" 0 0} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "std_1c20:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_oci_im:the_cpu_nios2_oci_im\|cpu_traceram_lpm_dram_bdp_component_module:cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_stv1:auto_generated\|q_a\[34\] " "Warning: Synthesized away node \"std_1c20:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_oci_im:the_cpu_nios2_oci_im\|cpu_traceram_lpm_dram_bdp_component_module:cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_stv1:auto_generated\|q_a\[34\]\"" {  } { { "db/altsyncram_stv1.tdf" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/db/altsyncram_stv1.tdf" 1106 2 0 } } { "altsyncram.tdf" "" { Text "d:/altera/quartus60/libraries/megafunctions/altsyncram.tdf" 905 4 0 } } { "cpu.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/cpu.vhd" 3402 -1 0 } } { "cpu.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/cpu.vhd" 3563 -1 0 } } { "cpu.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/cpu.vhd" 4429 -1 0 } } { "cpu.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/cpu.vhd" 7884 -1 0 } } { "std_1c20.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/std_1c20.vhd" 9873 -1 0 } } { "standard.bdf" "" { Schematic "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/standard.bdf" { { 560 808 1272 1296 "inst" "" } } } }  } 0 0 "Synthesized away node \"%1!s!\"" 0 0} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "std_1c20:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_oci_im:the_cpu_nios2_oci_im\|cpu_traceram_lpm_dram_bdp_component_module:cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_stv1:auto_generated\|q_a\[35\] " "Warning: Synthesized away node \"std_1c20:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_oci_im:the_cpu_nios2_oci_im\|cpu_traceram_lpm_dram_bdp_component_module:cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_stv1:auto_generated\|q_a\[35\]\"" {  } { { "db/altsyncram_stv1.tdf" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/db/altsyncram_stv1.tdf" 1137 2 0 } } { "altsyncram.tdf" "" { Text "d:/altera/quartus60/libraries/megafunctions/altsyncram.tdf" 905 4 0 } } { "cpu.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/cpu.vhd" 3402 -1 0 } } { "cpu.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/cpu.vhd" 3563 -1 0 } } { "cpu.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/cpu.vhd" 4429 -1 0 } } { "cpu.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/cpu.vhd" 7884 -1 0 } } { "std_1c20.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/std_1c20.vhd" 9873 -1 0 } } { "standard.bdf" "" { Schematic "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/standard.bdf" { { 560 808 1272 1296 "inst" "" } } } }  } 0 0 "Synthesized away node \"%1!s!\"" 0 0}  } {  } 0 0 "Synthesized away the following %1!s! node(s):" 0 0}  } {  } 0 0 "Synthesized away the following node(s):" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "std_1c20:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_oci_break:the_cpu_nios2_oci_break\|dbrk_hit3_latch data_in GND " "Warning: Reduced register \"std_1c20:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_oci_break:the_cpu_nios2_oci_break\|dbrk_hit3_latch\" with stuck data_in port to stuck value GND" {  } { { "cpu.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/cpu.vhd" 1242 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "std_1c20:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_oci_break:the_cpu_nios2_oci_break\|dbrk_hit2_latch data_in GND " "Warning: Reduced register \"std_1c20:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_oci_break:the_cpu_nios2_oci_break\|dbrk_hit2_latch\" with stuck data_in port to stuck value GND" {  } { { "cpu.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/cpu.vhd" 1241 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "std_1c20:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_oci_break:the_cpu_nios2_oci_break\|dbrk_hit1_latch data_in GND " "Warning: Reduced register \"std_1c20:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_oci_break:the_cpu_nios2_oci_break\|dbrk_hit1_latch\" with stuck data_in port to stuck value GND" {  } { { "cpu.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/cpu.vhd" 1240 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "std_1c20:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_oci_break:the_cpu_nios2_oci_break\|dbrk_hit0_latch data_in GND " "Warning: Reduced register \"std_1c20:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_oci_break:the_cpu_nios2_oci_break\|dbrk_hit0_latch\" with stuck data_in port to stuck value GND" {  } { { "cpu.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/cpu.vhd" 1239 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Info" "IOPT_MLS_DUP_REG_INFO_HDR" "" "Info: Duplicate registers merged to single register" { { "Info" "IOPT_MLS_DUP_REG_INFO" "std_1c20:inst\|uart1:the_uart1\|uart1_rx:the_uart1_rx\|delayed_unxsync_rxdxx1 std_1c20:inst\|uart1:the_uart1\|uart1_rx:the_uart1_rx\|delayed_unxsync_rxdxx2 " "Info: Duplicate register \"std_1c20:inst\|uart1:the_uart1\|uart1_rx:the_uart1_rx\|delayed_unxsync_rxdxx1\" merged to single register \"std_1c20:inst\|uart1:the_uart1\|uart1_rx:the_uart1_rx\|delayed_unxsync_rxdxx2\"" {  } { { "uart1.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/uart1.vhd" 963 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO_POWER_UP_CHANGE" "std_1c20:inst\|sdram_pll_s1_arbitrator:the_sdram_pll_s1\|d1_sdram_pll_s1_end_xfer std_1c20:inst\|sdram_pll_s1_arbitrator:the_sdram_pll_s1\|d1_reasons_to_wait " "Info: Duplicate register \"std_1c20:inst\|sdram_pll_s1_arbitrator:the_sdram_pll_s1\|d1_sdram_pll_s1_end_xfer\" merged to single register \"std_1c20:inst\|sdram_pll_s1_arbitrator:the_sdram_pll_s1\|d1_reasons_to_wait\", power-up level changed" {  } { { "std_1c20.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/std_1c20.vhd" 6290 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\", power-up level changed" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "std_1c20:inst\|sdram:the_sdram\|i_addr\[1\] std_1c20:inst\|sdram:the_sdram\|i_addr\[0\] " "Info: Duplicate register \"std_1c20:inst\|sdram:the_sdram\|i_addr\[1\]\" merged to single register \"std_1c20:inst\|sdram:the_sdram\|i_addr\[0\]\"" {  } { { "sdram.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/sdram.vhd" 364 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "std_1c20:inst\|sdram:the_sdram\|i_addr\[2\] std_1c20:inst\|sdram:the_sdram\|i_addr\[0\] " "Info: Duplicate register \"std_1c20:inst\|sdram:the_sdram\|i_addr\[2\]\" merged to single register \"std_1c20:inst\|sdram:the_sdram\|i_addr\[0\]\"" {  } { { "sdram.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/sdram.vhd" 364 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "std_1c20:inst\|sdram:the_sdram\|i_addr\[3\] std_1c20:inst\|sdram:the_sdram\|i_addr\[0\] " "Info: Duplicate register \"std_1c20:inst\|sdram:the_sdram\|i_addr\[3\]\" merged to single register \"std_1c20:inst\|sdram:the_sdram\|i_addr\[0\]\"" {  } { { "sdram.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/sdram.vhd" 364 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "std_1c20:inst\|sdram:the_sdram\|i_addr\[6\] std_1c20:inst\|sdram:the_sdram\|i_addr\[0\] " "Info: Duplicate register \"std_1c20:inst\|sdram:the_sdram\|i_addr\[6\]\" merged to single register \"std_1c20:inst\|sdram:the_sdram\|i_addr\[0\]\"" {  } { { "sdram.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/sdram.vhd" 364 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "std_1c20:inst\|sdram:the_sdram\|i_addr\[7\] std_1c20:inst\|sdram:the_sdram\|i_addr\[0\] " "Info: Duplicate register \"std_1c20:inst\|sdram:the_sdram\|i_addr\[7\]\" merged to single register \"std_1c20:inst\|sdram:the_sdram\|i_addr\[0\]\"" {  } { { "sdram.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/sdram.vhd" 364 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "std_1c20:inst\|sdram:the_sdram\|i_addr\[8\] std_1c20:inst\|sdram:the_sdram\|i_addr\[0\] " "Info: Duplicate register \"std_1c20:inst\|sdram:the_sdram\|i_addr\[8\]\" merged to single register \"std_1c20:inst\|sdram:the_sdram\|i_addr\[0\]\"" {  } { { "sdram.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/sdram.vhd" 364 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "std_1c20:inst\|sdram:the_sdram\|i_addr\[9\] std_1c20:inst\|sdram:the_sdram\|i_addr\[0\] " "Info: Duplicate register \"std_1c20:inst\|sdram:the_sdram\|i_addr\[9\]\" merged to single register \"std_1c20:inst\|sdram:the_sdram\|i_addr\[0\]\"" {  } { { "sdram.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/sdram.vhd" 364 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "std_1c20:inst\|sdram:the_sdram\|i_addr\[10\] std_1c20:inst\|sdram:the_sdram\|i_addr\[0\] " "Info: Duplicate register \"std_1c20:inst\|sdram:the_sdram\|i_addr\[10\]\" merged to single register \"std_1c20:inst\|sdram:the_sdram\|i_addr\[0\]\"" {  } { { "sdram.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/sdram.vhd" 364 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "std_1c20:inst\|sdram:the_sdram\|i_addr\[11\] std_1c20:inst\|sdram:the_sdram\|i_addr\[0\] " "Info: Duplicate register \"std_1c20:inst\|sdram:the_sdram\|i_addr\[11\]\" merged to single register \"std_1c20:inst\|sdram:the_sdram\|i_addr\[0\]\"" {  } { { "sdram.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/sdram.vhd" 364 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO_POWER_UP_CHANGE" "std_1c20:inst\|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave\|wrote_half_cycle_ext_ram_s1_last_time std_1c20:inst\|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave\|write_n_to_the_ext_ram_local " "Info: Duplicate register \"std_1c20:inst\|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave\|wrote_half_cycle_ext_ram_s1_last_time\" merged to single register \"std_1c20:inst\|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave\|write_n_to_the_ext_ram_local\", power-up level changed" {  } { { "std_1c20.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/std_1c20.vhd" 3142 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\", power-up level changed" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO_POWER_UP_CHANGE" "std_1c20:inst\|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave\|d1_reasons_to_wait std_1c20:inst\|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave\|d1_ext_ram_bus_avalon_slave_end_xfer " "Info: Duplicate register \"std_1c20:inst\|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave\|d1_reasons_to_wait\" merged to single register \"std_1c20:inst\|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave\|d1_ext_ram_bus_avalon_slave_end_xfer\", power-up level changed" {  } { { "std_1c20.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/std_1c20.vhd" 3034 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\", power-up level changed" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO_POWER_UP_CHANGE" "std_1c20:inst\|epcs_controller_epcs_control_port_arbitrator:the_epcs_controller_epcs_control_port\|d1_epcs_controller_epcs_control_port_end_xfer std_1c20:inst\|epcs_controller_epcs_control_port_arbitrator:the_epcs_controller_epcs_control_port\|d1_reasons_to_wait " "Info: Duplicate register \"std_1c20:inst\|epcs_controller_epcs_control_port_arbitrator:the_epcs_controller_epcs_control_port\|d1_epcs_controller_epcs_control_port_end_xfer\" merged to single register \"std_1c20:inst\|epcs_controller_epcs_control_port_arbitrator:the_epcs_controller_epcs_control_port\|d1_reasons_to_wait\", power-up level changed" {  } { { "std_1c20.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/std_1c20.vhd" 2590 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\", power-up level changed" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO_POWER_UP_CHANGE" "std_1c20:inst\|cpu_jtag_debug_module_arbitrator:the_cpu_jtag_debug_module\|d1_cpu_jtag_debug_module_end_xfer std_1c20:inst\|cpu_jtag_debug_module_arbitrator:the_cpu_jtag_debug_module\|d1_reasons_to_wait " "Info: Duplicate register \"std_1c20:inst\|cpu_jtag_debug_module_arbitrator:the_cpu_jtag_debug_module\|d1_cpu_jtag_debug_module_end_xfer\" merged to single register \"std_1c20:inst\|cpu_jtag_debug_module_arbitrator:the_cpu_jtag_debug_module\|d1_reasons_to_wait\", power-up level changed" {  } { { "std_1c20.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/std_1c20.vhd" 1334 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\", power-up level changed" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO_POWER_UP_CHANGE" "std_1c20:inst\|connector_pll_s1_arbitrator:the_connector_pll_s1\|d1_connector_pll_s1_end_xfer std_1c20:inst\|connector_pll_s1_arbitrator:the_connector_pll_s1\|d1_reasons_to_wait " "Info: Duplicate register \"std_1c20:inst\|connector_pll_s1_arbitrator:the_connector_pll_s1\|d1_connector_pll_s1_end_xfer\" merged to single register \"std_1c20:inst\|connector_pll_s1_arbitrator:the_connector_pll_s1\|d1_reasons_to_wait\", power-up level changed" {  } { { "std_1c20.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/std_1c20.vhd" 1111 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\", power-up level changed" 0 0}  } {  } 0 0 "Duplicate registers merged to single register" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "std_1c20:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_oci_break:the_cpu_nios2_oci_break\|trigger_state data_in GND " "Warning: Reduced register \"std_1c20:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_oci_break:the_cpu_nios2_oci_break\|trigger_state\" with stuck data_in port to stuck value GND" {  } { { "cpu.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/cpu.vhd" 1627 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Info" "IOPT_MLS_DUP_REG_INFO_HDR" "" "Info: Duplicate registers merged to single register" { { "Info" "IOPT_MLS_DUP_REG_INFO" "std_1c20:inst\|sdram_s1_arbitrator:the_sdram_s1\|rdv_fifo_for_cpu_data_master_to_sdram_s1_module:rdv_fifo_for_cpu_data_master_to_sdram_s1\|full_0 std_1c20:inst\|sdram_s1_arbitrator:the_sdram_s1\|rdv_fifo_for_cpu_instruction_master_to_sdram_s1_module:rdv_fifo_for_cpu_instruction_master_to_sdram_s1\|full_0 " "Info: Duplicate register \"std_1c20:inst\|sdram_s1_arbitrator:the_sdram_s1\|rdv_fifo_for_cpu_data_master_to_sdram_s1_module:rdv_fifo_for_cpu_data_master_to_sdram_s1\|full_0\" merged to single register \"std_1c20:inst\|sdram_s1_arbitrator:the_sdram_s1\|rdv_fifo_for_cpu_instruction_master_to_sdram_s1_module:rdv_fifo_for_cpu_instruction_master_to_sdram_s1\|full_0\"" {  } { { "std_1c20.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/std_1c20.vhd" 5110 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "std_1c20:inst\|sdram_s1_arbitrator:the_sdram_s1\|rdv_fifo_for_cpu_data_master_to_sdram_s1_module:rdv_fifo_for_cpu_data_master_to_sdram_s1\|full_1 std_1c20:inst\|sdram_s1_arbitrator:the_sdram_s1\|rdv_fifo_for_cpu_instruction_master_to_sdram_s1_module:rdv_fifo_for_cpu_instruction_master_to_sdram_s1\|full_1 " "Info: Duplicate register \"std_1c20:inst\|sdram_s1_arbitrator:the_sdram_s1\|rdv_fifo_for_cpu_data_master_to_sdram_s1_module:rdv_fifo_for_cpu_data_master_to_sdram_s1\|full_1\" merged to single register \"std_1c20:inst\|sdram_s1_arbitrator:the_sdram_s1\|rdv_fifo_for_cpu_instruction_master_to_sdram_s1_module:rdv_fifo_for_cpu_instruction_master_to_sdram_s1\|full_1\"" {  } { { "std_1c20.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/std_1c20.vhd" 5111 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "std_1c20:inst\|sdram_s1_arbitrator:the_sdram_s1\|rdv_fifo_for_cpu_data_master_to_sdram_s1_module:rdv_fifo_for_cpu_data_master_to_sdram_s1\|full_2 std_1c20:inst\|sdram_s1_arbitrator:the_sdram_s1\|rdv_fifo_for_cpu_instruction_master_to_sdram_s1_module:rdv_fifo_for_cpu_instruction_master_to_sdram_s1\|full_2 " "Info: Duplicate register \"std_1c20:inst\|sdram_s1_arbitrator:the_sdram_s1\|rdv_fifo_for_cpu_data_master_to_sdram_s1_module:rdv_fifo_for_cpu_data_master_to_sdram_s1\|full_2\" merged to single register \"std_1c20:inst\|sdram_s1_arbitrator:the_sdram_s1\|rdv_fifo_for_cpu_instruction_master_to_sdram_s1_module:rdv_fifo_for_cpu_instruction_master_to_sdram_s1\|full_2\"" {  } { { "std_1c20.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/std_1c20.vhd" 5112 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "std_1c20:inst\|sdram_s1_arbitrator:the_sdram_s1\|rdv_fifo_for_cpu_data_master_to_sdram_s1_module:rdv_fifo_for_cpu_data_master_to_sdram_s1\|full_3 std_1c20:inst\|sdram_s1_arbitrator:the_sdram_s1\|rdv_fifo_for_cpu_instruction_master_to_sdram_s1_module:rdv_fifo_for_cpu_instruction_master_to_sdram_s1\|full_3 " "Info: Duplicate register \"std_1c20:inst\|sdram_s1_arbitrator:the_sdram_s1\|rdv_fifo_for_cpu_data_master_to_sdram_s1_module:rdv_fifo_for_cpu_data_master_to_sdram_s1\|full_3\" merged to single register \"std_1c20:inst\|sdram_s1_arbitrator:the_sdram_s1\|rdv_fifo_for_cpu_instruction_master_to_sdram_s1_module:rdv_fifo_for_cpu_instruction_master_to_sdram_s1\|full_3\"" {  } { { "std_1c20.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/std_1c20.vhd" 5113 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "std_1c20:inst\|sdram_s1_arbitrator:the_sdram_s1\|rdv_fifo_for_cpu_data_master_to_sdram_s1_module:rdv_fifo_for_cpu_data_master_to_sdram_s1\|full_4 std_1c20:inst\|sdram_s1_arbitrator:the_sdram_s1\|rdv_fifo_for_cpu_instruction_master_to_sdram_s1_module:rdv_fifo_for_cpu_instruction_master_to_sdram_s1\|full_4 " "Info: Duplicate register \"std_1c20:inst\|sdram_s1_arbitrator:the_sdram_s1\|rdv_fifo_for_cpu_data_master_to_sdram_s1_module:rdv_fifo_for_cpu_data_master_to_sdram_s1\|full_4\" merged to single register \"std_1c20:inst\|sdram_s1_arbitrator:the_sdram_s1\|rdv_fifo_for_cpu_instruction_master_to_sdram_s1_module:rdv_fifo_for_cpu_instruction_master_to_sdram_s1\|full_4\"" {  } { { "std_1c20.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/std_1c20.vhd" 5114 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "std_1c20:inst\|sdram_s1_arbitrator:the_sdram_s1\|rdv_fifo_for_cpu_data_master_to_sdram_s1_module:rdv_fifo_for_cpu_data_master_to_sdram_s1\|full_5 std_1c20:inst\|sdram_s1_arbitrator:the_sdram_s1\|rdv_fifo_for_cpu_instruction_master_to_sdram_s1_module:rdv_fifo_for_cpu_instruction_master_to_sdram_s1\|full_5 " "Info: Duplicate register \"std_1c20:inst\|sdram_s1_arbitrator:the_sdram_s1\|rdv_fifo_for_cpu_data_master_to_sdram_s1_module:rdv_fifo_for_cpu_data_master_to_sdram_s1\|full_5\" merged to single register \"std_1c20:inst\|sdram_s1_arbitrator:the_sdram_s1\|rdv_fifo_for_cpu_instruction_master_to_sdram_s1_module:rdv_fifo_for_cpu_instruction_master_to_sdram_s1\|full_5\"" {  } { { "std_1c20.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/std_1c20.vhd" 5115 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "std_1c20:inst\|sdram_s1_arbitrator:the_sdram_s1\|rdv_fifo_for_cpu_data_master_to_sdram_s1_module:rdv_fifo_for_cpu_data_master_to_sdram_s1\|full_6 std_1c20:inst\|sdram_s1_arbitrator:the_sdram_s1\|rdv_fifo_for_cpu_instruction_master_to_sdram_s1_module:rdv_fifo_for_cpu_instruction_master_to_sdram_s1\|full_6 " "Info: Duplicate register \"std_1c20:inst\|sdram_s1_arbitrator:the_sdram_s1\|rdv_fifo_for_cpu_data_master_to_sdram_s1_module:rdv_fifo_for_cpu_data_master_to_sdram_s1\|full_6\" merged to single register \"std_1c20:inst\|sdram_s1_arbitrator:the_sdram_s1\|rdv_fifo_for_cpu_instruction_master_to_sdram_s1_module:rdv_fifo_for_cpu_instruction_master_to_sdram_s1\|full_6\"" {  } { { "std_1c20.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/std_1c20.vhd" 5172 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0}  } {  } 0 0 "Duplicate registers merged to single register" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "std_1c20:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_oci_dbrk:the_cpu_nios2_oci_dbrk\|internal_dbrk_break data_in GND " "Warning: Reduced register \"std_1c20:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_oci_dbrk:the_cpu_nios2_oci_dbrk\|internal_dbrk_break\" with stuck data_in port to stuck value GND" {  } { { "cpu.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/cpu.vhd" 2158 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "std_1c20:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_oci_break:the_cpu_nios2_oci_break\|trigbrktype data_in GND " "Warning: Reduced register \"std_1c20:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_oci_break:the_cpu_nios2_oci_break\|trigbrktype\" with stuck data_in port to stuck value GND" {  } { { "cpu.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/cpu.vhd" 1243 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Info" "IOPT_MLS_DUP_REG_INFO_HDR" "" "Info: Duplicate registers merged to single register" { { "Info" "IOPT_MLS_DUP_REG_INFO" "std_1c20:inst\|sdram:the_sdram\|m_next\[2\] std_1c20:inst\|sdram:the_sdram\|m_next\[1\] " "Info: Duplicate register \"std_1c20:inst\|sdram:the_sdram\|m_next\[2\]\" merged to single register \"std_1c20:inst\|sdram:the_sdram\|m_next\[1\]\"" {  } { { "sdram.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/sdram.vhd" 443 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "std_1c20:inst\|sdram:the_sdram\|m_next\[5\] std_1c20:inst\|sdram:the_sdram\|m_next\[1\] " "Info: Duplicate register \"std_1c20:inst\|sdram:the_sdram\|m_next\[5\]\" merged to single register \"std_1c20:inst\|sdram:the_sdram\|m_next\[1\]\"" {  } { { "sdram.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/sdram.vhd" 443 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "std_1c20:inst\|sdram:the_sdram\|m_next\[6\] std_1c20:inst\|sdram:the_sdram\|m_next\[1\] " "Info: Duplicate register \"std_1c20:inst\|sdram:the_sdram\|m_next\[6\]\" merged to single register \"std_1c20:inst\|sdram:the_sdram\|m_next\[1\]\"" {  } { { "sdram.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/sdram.vhd" 443 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "std_1c20:inst\|sdram:the_sdram\|m_next\[8\] std_1c20:inst\|sdram:the_sdram\|m_next\[1\] " "Info: Duplicate register \"std_1c20:inst\|sdram:the_sdram\|m_next\[8\]\" merged to single register \"std_1c20:inst\|sdram:the_sdram\|m_next\[1\]\"" {  } { { "sdram.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/sdram.vhd" 443 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "std_1c20:inst\|sdram:the_sdram\|i_next\[2\] std_1c20:inst\|sdram:the_sdram\|i_next\[0\] " "Info: Duplicate register \"std_1c20:inst\|sdram:the_sdram\|i_next\[2\]\" merged to single register \"std_1c20:inst\|sdram:the_sdram\|i_next\[0\]\"" {  } { { "sdram.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/sdram.vhd" 364 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "std_1c20:inst\|cpu:the_cpu\|E_compare_op\[1\] std_1c20:inst\|cpu:the_cpu\|E_logic_op\[1\] " "Info: Duplicate register \"std_1c20:inst\|cpu:the_cpu\|E_compare_op\[1\]\" merged to single register \"std_1c20:inst\|cpu:the_cpu\|E_logic_op\[1\]\"" {  } { { "cpu.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/cpu.vhd" 7621 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "std_1c20:inst\|cpu:the_cpu\|E_compare_op\[0\] std_1c20:inst\|cpu:the_cpu\|E_logic_op\[0\] " "Info: Duplicate register \"std_1c20:inst\|cpu:the_cpu\|E_compare_op\[0\]\" merged to single register \"std_1c20:inst\|cpu:the_cpu\|E_logic_op\[0\]\"" {  } { { "cpu.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/cpu.vhd" 7621 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0}  } {  } 0 0 "Duplicate registers merged to single register" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "std_1c20:inst\|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave\|ext_ram_bus_avalon_slave_arb_share_counter\[2\] data_in GND " "Warning: Reduced register \"std_1c20:inst\|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave\|ext_ram_bus_avalon_slave_arb_share_counter\[2\]\" with stuck data_in port to stuck value GND" {  } { { "std_1c20.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/std_1c20.vhd" 3221 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "std_1c20:inst\|cpu_jtag_debug_module_arbitrator:the_cpu_jtag_debug_module\|cpu_jtag_debug_module_arb_share_counter\[2\] data_in GND " "Warning: Reduced register \"std_1c20:inst\|cpu_jtag_debug_module_arbitrator:the_cpu_jtag_debug_module\|cpu_jtag_debug_module_arb_share_counter\[2\]\" with stuck data_in port to stuck value GND" {  } { { "std_1c20.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/std_1c20.vhd" 1422 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "std_1c20:inst\|epcs_controller_epcs_control_port_arbitrator:the_epcs_controller_epcs_control_port\|epcs_controller_epcs_control_port_arb_share_counter\[2\] data_in GND " "Warning: Reduced register \"std_1c20:inst\|epcs_controller_epcs_control_port_arbitrator:the_epcs_controller_epcs_control_port\|epcs_controller_epcs_control_port_arb_share_counter\[2\]\" with stuck data_in port to stuck value GND" {  } { { "std_1c20.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/std_1c20.vhd" 2693 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "std_1c20:inst\|epcs_controller:the_epcs_controller\|epcs_controller_sub:the_epcs_controller_sub\|slowcount\[1\] data_in GND " "Warning: Reduced register \"std_1c20:inst\|epcs_controller:the_epcs_controller\|epcs_controller_sub:the_epcs_controller_sub\|slowcount\[1\]\" with stuck data_in port to stuck value GND" {  } { { "epcs_controller.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/epcs_controller.vhd" 265 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "std_1c20:inst\|cpu_jtag_debug_module_arbitrator:the_cpu_jtag_debug_module\|cpu_jtag_debug_module_slavearbiterlockenable data_in GND " "Warning: Reduced register \"std_1c20:inst\|cpu_jtag_debug_module_arbitrator:the_cpu_jtag_debug_module\|cpu_jtag_debug_module_slavearbiterlockenable\" with stuck data_in port to stuck value GND" {  } { { "std_1c20.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/std_1c20.vhd" 1372 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "std_1c20:inst\|epcs_controller_epcs_control_port_arbitrator:the_epcs_controller_epcs_control_port\|epcs_controller_epcs_control_port_slavearbiterlockenable data_in GND " "Warning: Reduced register \"std_1c20:inst\|epcs_controller_epcs_control_port_arbitrator:the_epcs_controller_epcs_control_port\|epcs_controller_epcs_control_port_slavearbiterlockenable\" with stuck data_in port to stuck value GND" {  } { { "std_1c20.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/std_1c20.vhd" 2640 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "../../../../quartus60/libraries/megafunctions/lpm_add_sub.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file ../../../../quartus60/libraries/megafunctions/lpm_add_sub.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_add_sub " "Info: Found entity 1: lpm_add_sub" {  } { { "lpm_add_sub.tdf" "" { Text "d:/altera/quartus60/libraries/megafunctions/lpm_add_sub.tdf" 100 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_ELABORATION_HEADER" "std_1c20:inst\|cpu:the_cpu\|lpm_add_sub:Add8 " "Info: Elaborated megafunction instantiation \"std_1c20:inst\|cpu:the_cpu\|lpm_add_sub:Add8\"" {  } { { "d:/altera/quartus60/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "d:/altera/quartus60/libraries/vhdl/synopsys/syn_arit.vhd" 836 -1 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "../../../../quartus60/libraries/megafunctions/alt_stratix_add_sub.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file ../../../../quartus60/libraries/megafunctions/alt_stratix_add_sub.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 alt_stratix_add_sub " "Info: Found entity 1: alt_stratix_add_sub" {  } { { "alt_stratix_add_sub.tdf" "" { Text "d:/altera/quartus60/libraries/megafunctions/alt_stratix_add_sub.tdf" 92 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_MEGAFN_DESCENDANT" "std_1c20:inst\|cpu:the_cpu\|lpm_add_sub:Add8\|alt_stratix_add_sub:stratix_adder std_1c20:inst\|cpu:the_cpu\|lpm_add_sub:Add8 " "Info: Elaborated megafunction instantiation \"std_1c20:inst\|cpu:the_cpu\|lpm_add_sub:Add8\|alt_stratix_add_sub:stratix_adder\", which is child of megafunction instantiation \"std_1c20:inst\|cpu:the_cpu\|lpm_add_sub:Add8\"" {  } { { "lpm_add_sub.tdf" "" { Text "d:/altera/quartus60/libraries/megafunctions/lpm_add_sub.tdf" 138 5 0 } } { "d:/altera/quartus60/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "d:/altera/quartus60/libraries/vhdl/synopsys/syn_arit.vhd" 836 -1 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0}
{ "Info" "ISGN_MEGAFN_PARAM_TOP" "std_1c20:inst\|cpu:the_cpu\|lpm_add_sub:Add8 " "Info: Instantiated megafunction \"std_1c20:inst\|cpu:the_cpu\|lpm_add_sub:Add8\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTH 33 " "Info: Parameter \"LPM_WIDTH\" = \"33\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_REPRESENTATION UNSIGNED " "Info: Parameter \"LPM_REPRESENTATION\" = \"UNSIGNED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "ONE_INPUT_IS_CONSTANT NO " "Info: Parameter \"ONE_INPUT_IS_CONSTANT\" = \"NO\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0}  } { { "d:/altera/quartus60/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "d:/altera/quartus60/libraries/vhdl/synopsys/syn_arit.vhd" 836 -1 0 } }  } 0 0 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0}
{ "Info" "ISCL_SCL_WYSIWYG_RESYNTHESIS" "0 speed 36 " "Info: Resynthesizing 0 WYSIWYG logic cells and I/Os using \"speed\" technology mapper which leaves 36 WYSIWYG logic cells and I/Os untouched" {  } {  } 0 0 "Resynthesizing %1!d! WYSIWYG logic cells and I/Os using \"%2!s!\" technology mapper which leaves %3!d! WYSIWYG logic cells and I/Os untouched" 0 0}
{ "Info" "IOPT_MLS_DUP_REG_INFO_HDR" "" "Info: Duplicate registers merged to single register" { { "Info" "IOPT_MLS_DUP_REG_INFO" "std_1c20:inst\|clock_1:the_clock_1\|clock_1_master_FSM:master_FSM\|internal_master_read1 std_1c20:inst\|clock_1:the_clock_1\|clock_1_master_FSM:master_FSM\|master_state\[1\] " "Info: Duplicate register \"std_1c20:inst\|clock_1:the_clock_1\|clock_1_master_FSM:master_FSM\|internal_master_read1\" merged to single register \"std_1c20:inst\|clock_1:the_clock_1\|clock_1_master_FSM:master_FSM\|master_state\[1\]\"" {  } { { "clock_1.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/clock_1.vhd" 525 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "std_1c20:inst\|clock_0:the_clock_0\|clock_0_master_FSM:master_FSM\|internal_master_read1 std_1c20:inst\|clock_0:the_clock_0\|clock_0_master_FSM:master_FSM\|master_state\[1\] " "Info: Duplicate register \"std_1c20:inst\|clock_0:the_clock_0\|clock_0_master_FSM:master_FSM\|internal_master_read1\" merged to single register \"std_1c20:inst\|clock_0:the_clock_0\|clock_0_master_FSM:master_FSM\|master_state\[1\]\"" {  } { { "clock_0.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/clock_0.vhd" 525 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0}  } {  } 0 0 "Duplicate registers merged to single register" 0 0}
{ "Info" "IOPT_MLS_DUP_REG_INFO_HDR" "" "Info: Duplicate registers merged to single register" { { "Info" "IOPT_MLS_DUP_REG_INFO" "std_1c20:inst\|clock_1:the_clock_1\|clock_1_master_FSM:master_FSM\|internal_master_write1 std_1c20:inst\|clock_1:the_clock_1\|clock_1_master_FSM:master_FSM\|master_state\[2\] " "Info: Duplicate register \"std_1c20:inst\|clock_1:the_clock_1\|clock_1_master_FSM:master_FSM\|internal_master_write1\" merged to single register \"std_1c20:inst\|clock_1:the_clock_1\|clock_1_master_FSM:master_FSM\|master_state\[2\]\"" {  } { { "clock_1.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/clock_1.vhd" 537 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "std_1c20:inst\|clock_0:the_clock_0\|clock_0_master_FSM:master_FSM\|internal_master_write1 std_1c20:inst\|clock_0:the_clock_0\|clock_0_master_FSM:master_FSM\|master_state\[2\] " "Info: Duplicate register \"std_1c20:inst\|clock_0:the_clock_0\|clock_0_master_FSM:master_FSM\|internal_master_write1\" merged to single register \"std_1c20:inst\|clock_0:the_clock_0\|clock_0_master_FSM:master_FSM\|master_state\[2\]\"" {  } { { "clock_0.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/clock_0.vhd" 537 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0}  } {  } 0 0 "Duplicate registers merged to single register" 0 0}
{ "Info" "IOPT_MLS_GATE_LEVEL_RETIMING_STARTED_INFO" "" "Info: Performing gate-level register retiming" {  } {  } 0 0 "Performing gate-level register retiming" 0 0}
{ "Info" "IOPT_MLS_RETIMING_DONT_TOUCH_REGISTERS_HDR" "545 " "Info: Not allowed to move 545 registers" { { "Info" "IOPT_MLS_RETIMING_DONT_TOUCH_REGISTERS_INPUT_DETAILS" "7 " "Info: Not allowed to move 7 registers because they are directly fed by input pins" {  } {  } 0 0 "Not allowed to move %1!d! registers because they are directly fed by input pins" 0 0} { "Info" "IOPT_MLS_RETIMING_DONT_TOUCH_REGISTERS_OUTPUT_DETAILS" "163 " "Info: Not allowed to move 163 registers because they feed output pins directly" {  } {  } 0 0 "Not allowed to move %1!d! registers because they feed output pins directly" 0 0} { "Info" "IOPT_MLS_RETIMING_DONT_TOUCH_REGISTERS_FED_BY_OTHER_CLOCK_DETAILS" "168 " "Info: Not allowed to move 168 registers because they are fed by registers in a different clock domain" {  } {  } 0 0 "Not allowed to move %1!d! registers because they are fed by registers in a different clock domain" 0 0} { "Info" "IOPT_MLS_RETIMING_DONT_TOUCH_REGISTERS_FEEDING_OTHER_CLOCK_DETAILS" "97 " "Info: Not allowed to move 97 registers because they feed registers in a different clock domain" {  } {  } 0 0 "Not allowed to move %1!d! registers because they feed registers in a different clock domain" 0 0} { "Info" "IOPT_MLS_RETIMING_DONT_TOUCH_REGISTERS_FEEDING_SECONDARIES_DETAILS" "10 " "Info: Not allowed to move 10 registers because they feed clock or asynchronous control signals of other registers" {  } {  } 0 0 "Not allowed to move %1!d! registers because they feed clock or asynchronous control signals of other registers" 0 0} { "Info" "IOPT_MLS_RETIMING_USER_DONT_TOUCH_DETAILS" "100 " "Info: Not allowed to move 100 registers due to user assignments" {  } {  } 0 0 "Not allowed to move %1!d! registers due to user assignments" 0 0}  } {  } 0 0 "Not allowed to move %1!d! registers" 0 0}
{ "Info" "IOPT_MLS_GATE_LEVEL_RETIMING_RESULTS_HDR" "3 " "Info: Quartus II software applied gate-level register retiming to 3 clock domains" { { "Info" "IOPT_MLS_GATE_LEVEL_RETIMING_RESULTS_DETAILS" "std_1c20:inst\|sdram_pll:the_sdram_pll\|altpllsdram_pll:the_pll\|altpll:altpll_component\|_clk0 36 18 1688 " "Info: Quartus II software applied gate-level register retiming to clock \"std_1c20:inst\|sdram_pll:the_sdram_pll\|altpllsdram_pll:the_pll\|altpll:altpll_component\|_clk0\": created 36 new registers, removed 18 registers, left 1688 registers untouched" {  } {  } 0 0 "Quartus II software applied gate-level register retiming to clock \"%1!s!\": created %2!d! new registers, removed %3!d! registers, left %4!d! registers untouched" 0 0} { "Info" "IOPT_MLS_GATE_LEVEL_RETIMING_RESULTS_DETAILS" "!altera_internal_jtag~TCKUTAP 6 1 1 " "Info: Quartus II software applied gate-level register retiming to clock \"!altera_internal_jtag~TCKUTAP\": created 6 new registers, removed 1 registers, left 1 registers untouched" {  } {  } 0 0 "Quartus II software applied gate-level register retiming to clock \"%1!s!\": created %2!d! new registers, removed %3!d! registers, left %4!d! registers untouched" 0 0} { "Info" "IOPT_MLS_GATE_LEVEL_RETIMING_RESULTS_DETAILS" "altera_internal_jtag~TCKUTAP 1 0 167 " "Info: Quartus II software applied gate-level register retiming to clock \"altera_internal_jtag~TCKUTAP\": created 1 new registers, removed 0 registers, left 167 registers untouched" {  } {  } 0 0 "Quartus II software applied gate-level register retiming to clock \"%1!s!\": created %2!d! new registers, removed %3!d! registers, left %4!d! registers untouched" 0 0}  } {  } 0 0 "Quartus II software applied gate-level register retiming to %1!d! clock domains" 0 0}
{ "Warning" "WOPT_MLS_STUCK_PIN_HDR" "" "Warning: Output pins are stuck at VCC or GND" { { "Warning" "WOPT_MLS_STUCK_PIN" "ENET_ADS_N GND " "Warning: Pin \"ENET_ADS_N\" stuck at GND" {  } { { "standard.bdf" "" { Schematic "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/standard.bdf" { { 504 1392 1568 520 "ENET_ADS_N" "" } } } }  } 0 0 "Pin \"%1!s!\" stuck at %2!s!" 0 0} { "Warning" "WOPT_MLS_STUCK_PIN" "ENET_AEN GND " "Warning: Pin \"ENET_AEN\" stuck at GND" {  } { { "standard.bdf" "" { Schematic "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/standard.bdf" { { 520 1392 1568 536 "ENET_AEN" "" } } } }  } 0 0 "Pin \"%1!s!\" stuck at %2!s!" 0 0} { "Warning" "WOPT_MLS_STUCK_PIN" "zs_cke_from_the_sdram VCC " "Warning: Pin \"zs_cke_from_the_sdram\" stuck at VCC" {  } { { "standard.bdf" "" { Schematic "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/standard.bdf" { { 1112 1312 1488 1128 "zs_cke_from_the_sdram" "" } } } }  } 0 0 "Pin \"%1!s!\" stuck at %2!s!" 0 0}  } {  } 0 0 "Output pins are stuck at VCC or GND" 0 0}
{ "Info" "IFTM_FTM_PRESET_POWER_UP" "" "Info: Registers with preset signals will power-up high" {  } { { "std_1c20.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/std_1c20.vhd" 2983 -1 0 } } { "std_1c20.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/std_1c20.vhd" 2995 -1 0 } } { "std_1c20.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/std_1c20.vhd" 2984 -1 0 } } { "std_1c20.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/std_1c20.vhd" 2987 -1 0 } } { "std_1c20.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/std_1c20.vhd" 2988 -1 0 } } { "std_1c20.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/std_1c20.vhd" 2993 -1 0 } } { "std_1c20.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/std_1c20.vhd" 2994 -1 0 } } { "std_1c20.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/std_1c20.vhd" 3140 -1 0 } } { "std_1c20.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/std_1c20.vhd" 3141 -1 0 } } { "sdram.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/sdram.vhd" 443 -1 0 } } { "sdram.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/sdram.vhd" 443 -1 0 } } { "sdram.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/sdram.vhd" 443 -1 0 } } { "sdram.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/sdram.vhd" 443 -1 0 } } { "uart1.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/uart1.vhd" 232 -1 0 } } { "std_1c20.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/std_1c20.vhd" 3833 -1 0 } } { "std_1c20.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/std_1c20.vhd" 3833 -1 0 } } { "std_1c20.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/std_1c20.vhd" 3833 -1 0 } } { "std_1c20.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/std_1c20.vhd" 3833 -1 0 } } { "std_1c20.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/std_1c20.vhd" 3683 -1 0 } } { "std_1c20.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/std_1c20.vhd" 3683 -1 0 } } { "std_1c20.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/std_1c20.vhd" 3683 -1 0 } } { "std_1c20.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/std_1c20.vhd" 3683 -1 0 } } { "std_1c20.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/std_1c20.vhd" 5463 -1 0 } } { "std_1c20.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/std_1c20.vhd" 5463 -1 0 } } { "std_1c20.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/std_1c20.vhd" 2975 -1 0 } } { "std_1c20.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/std_1c20.vhd" 1912 -1 0 } } { "sdram.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/sdram.vhd" 443 -1 0 } } { "sdram.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/sdram.vhd" 364 -1 0 } } { "sdram.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/sdram.vhd" 364 -1 0 } } { "sdram.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/sdram.vhd" 443 -1 0 } } { "sdram.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/sdram.vhd" 364 -1 0 } } { "sdram.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/sdram.vhd" 364 -1 0 } } { "uart1.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/uart1.vhd" 244 -1 0 } } { "cpu.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/cpu.vhd" 5615 -1 0 } } { "cpu.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/cpu.vhd" 5819 -1 0 } } { "sdram.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/sdram.vhd" 364 -1 0 } } { "../../../../quartus60/libraries/megafunctions/sld_hub.vhd" "" { Text "D:/ALTERA/quartus60/libraries/megafunctions/sld_hub.vhd" 135 -1 0 } } { "../../../../quartus60/libraries/megafunctions/sld_hub.vhd" "" { Text "D:/ALTERA/quartus60/libraries/megafunctions/sld_hub.vhd" 135 -1 0 } } { "../../../../quartus60/libraries/megafunctions/sld_hub.vhd" "" { Text "D:/ALTERA/quartus60/libraries/megafunctions/sld_hub.vhd" 135 -1 0 } } { "../../../../quartus60/libraries/megafunctions/sld_hub.vhd" "" { Text "D:/ALTERA/quartus60/libraries/megafunctions/sld_hub.vhd" 135 -1 0 } } { "../../../../quartus60/libraries/megafunctions/sld_hub.vhd" "" { Text "D:/ALTERA/quartus60/libraries/megafunctions/sld_hub.vhd" 135 -1 0 } } { "../../../../quartus60/libraries/megafunctions/sld_hub.vhd" "" { Text "D:/ALTERA/quartus60/libraries/megafunctions/sld_hub.vhd" 135 -1 0 } } { "std_1c20.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/std_1c20.vhd" 3621 -1 0 } } { "std_1c20.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/std_1c20.vhd" 3621 -1 0 } } { "std_1c20.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/std_1c20.vhd" 3621 -1 0 } } { "std_1c20.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/std_1c20.vhd" 1534 -1 0 } } { "std_1c20.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/std_1c20.vhd" 5103 -1 0 } } { "std_1c20.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/std_1c20.vhd" 5103 -1 0 } } { "std_1c20.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/std_1c20.vhd" 6150 -1 0 } } { "std_1c20.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/std_1c20.vhd" 2805 -1 0 } } { "jtag_uart.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/jtag_uart.vhd" 1260 -1 0 } } { "clock_0.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/clock_0.vhd" 252 -1 0 } } { "clock_1.vhd" "" { Text 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"D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/high_res_timer.vhd" 173 -1 0 } } { "epcs_controller.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/epcs_controller.vhd" 236 -1 0 } } { "high_res_timer.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/high_res_timer.vhd" 173 -1 0 } } { "sys_clk_timer.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/sys_clk_timer.vhd" 185 -1 0 } } { "sys_clk_timer.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/sys_clk_timer.vhd" 173 -1 0 } } { "high_res_timer.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/high_res_timer.vhd" 173 -1 0 } } { "sys_clk_timer.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/sys_clk_timer.vhd" 173 -1 0 } } { "high_res_timer.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/high_res_timer.vhd" 173 -1 0 } } { "sys_clk_timer.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/sys_clk_timer.vhd" 173 -1 0 } } { "high_res_timer.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/high_res_timer.vhd" 173 -1 0 } } { "high_res_timer.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/high_res_timer.vhd" 173 -1 0 } } { "sys_clk_timer.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/sys_clk_timer.vhd" 173 -1 0 } } { "clock_0.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/clock_0.vhd" 549 -1 0 } } { "clock_1.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/clock_1.vhd" 549 -1 0 } } { "epcs_controller.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/epcs_controller.vhd" 249 -1 0 } } { "epcs_controller.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/epcs_controller.vhd" 113 -1 0 } }  } 0 0 "Registers with preset signals will power-up high" 0 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "6197 " "Info: Implemented 6197 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "12 " "Info: Implemented 12 input pins" {  } {  } 0 0 "Implemented %1!d! input pins" 0 0} { "Info" "ISCL_SCL_TM_OPINS" "95 " "Info: Implemented 95 output pins" {  } {  } 0 0 "Implemented %1!d! output pins" 0 0} { "Info" "ISCL_SCL_TM_BIDIRS" "73 " "Info: Implemented 73 bidirectional pins" {  } {  } 0 0 "Implemented %1!d! bidirectional pins" 0 0} { "Info" "ISCL_SCL_TM_LCELLS" "5843 " "Info: Implemented 5843 logic cells" {  } {  } 0 0 "Implemented %1!d! logic cells" 0 0} { "Info" "ISCL_SCL_TM_RAMS" "170 " "Info: Implemented 170 RAM segments" {  } {  } 0 0 "Implemented %1!d! RAM segments" 0 0} { "Info" "ISCL_SCL_TM_PLLS" "2 " "Info: Implemented 2 ClockLock PLLs" {  } {  } 0 0 "Implemented %1!d! ClockLock PLLs" 0 0}  } {  } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 199 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 199 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Thu Oct 06 16:03:12 2011 " "Info: Processing ended: Thu Oct 06 16:03:12 2011" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:02:40 " "Info: Elapsed time: 00:02:40" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}
