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--output files any of the foregoing (including device programming or
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-- turn off superfluous VHDL processor warnings 
-- altera message_level Level1 
-- altera message_off 10034 10035 10036 10037 10230 10240 10030 

library altera;
use altera.altera_europa_support_lib.all;

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity custominstruction_cpu is 
        port (
              -- inputs:
                 signal dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
                 signal datab : IN STD_LOGIC_VECTOR (31 DOWNTO 0);

              -- outputs:
                 signal result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
              );
end entity custominstruction_cpu;


architecture europa of custominstruction_cpu is
component xor32 is 
           port (
                 -- inputs:
                    signal dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
                    signal datab : IN STD_LOGIC_VECTOR (31 DOWNTO 0);

                 -- outputs:
                    signal result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
                 );
end component xor32;

                signal internal_result :  STD_LOGIC_VECTOR (31 DOWNTO 0);

begin

  --s1, which is an e_custom_instruction_slave
  --the_xor32, which is an e_instance
  the_xor32 : xor32
    port map(
      result => internal_result,
      dataa => dataa,
      datab => datab
    );


  --vhdl renameroo for output signals
  result <= internal_result;

end europa;

