SYSTEM std_1c20
{
   System_Wizard_Version = "5.10";
   System_Wizard_Build = "148";
   WIZARD_SCRIPT_ARGUMENTS 
   {
      device_family = "CYCLONE";
      clock_freq = "50000000";
      generate_hdl = "1";
      generate_sdk = "0";
      do_build_sim = "0";
      hardcopy_compatible = "0";
      board_class = "altera_nios_dev_board_cyclone_1c20";
      CLOCKS 
      {
         CLOCK sysclk2
         {
            frequency = "50000000";
            source = "sdram_pll_c0";
            display_name = "sysclk2";
            Is_Clock_Source = "0";
            BOARD_COMPONENT altera_nios_dev_board_cyclone_1c20
            {
               component_pin = "use_quartus_pin_assignment";
               pin_assignment = "";
            }
         }
         CLOCK PLD_CLKFB
         {
            frequency = "50000000";
            source = "External";
            Is_Clock_Source = "0";
            display_name = "PLD_CLKFB";
            pipeline = "0";
            BOARD_COMPONENT altera_nios_dev_board_cyclone_1c20
            {
               component_pin = "use_quartus_pin_assignment";
               pin_assignment = "";
            }
         }
         CLOCK sdram_pll_e0
         {
            frequency = "50000000";
            source = "";
            Is_Clock_Source = "1";
            display_name = "e0 from sdram_pll";
            pipeline = "0";
         }
         CLOCK sdram_pll_c0
         {
            frequency = "50000000";
            source = "";
            Is_Clock_Source = "1";
            display_name = "c0 from sdram_pll";
            pipeline = "0";
         }
         CLOCK connector_pll_e0
         {
            frequency = "50000000";
            source = "";
            Is_Clock_Source = "1";
            display_name = "e0 from connector_pll";
            pipeline = "0";
         }
         CLOCK connector_pll_c0
         {
            frequency = "90000000";
            source = "";
            Is_Clock_Source = "1";
            display_name = "c0 from connector_pll";
            pipeline = "0";
         }
         CLOCK PLD_CLOCKINPUT
         {
            frequency = "50000000";
            source = "External";
            Is_Clock_Source = "0";
            display_name = "PLD_CLOCKINPUT";
            pipeline = "0";
            BOARD_COMPONENT altera_nios_dev_board_cyclone_1c20
            {
               component_pin = "use_quartus_pin_assignment";
               pin_assignment = "";
            }
         }
         CLOCK sysclk
         {
            frequency = "90000000";
            source = "connector_pll_c0";
            Is_Clock_Source = "0";
            display_name = "sysclk";
            pipeline = "0";
            BOARD_COMPONENT altera_nios_dev_board_cyclone_1c20
            {
               component_pin = "use_quartus_pin_assignment";
               pin_assignment = "";
            }
         }
         CLOCK SDRAM_CLK
         {
            frequency = "50000000";
            source = "sdram_pll_e0";
            Is_Clock_Source = "0";
            display_name = "SDRAM_CLK";
            pipeline = "0";
            BOARD_COMPONENT altera_nios_dev_board_cyclone_1c20
            {
               component_pin = "use_quartus_pin_assignment";
               pin_assignment = "";
            }
         }
         CLOCK PLD_CLKOUT
         {
            frequency = "50000000";
            source = "connector_pll_e0";
            Is_Clock_Source = "0";
            display_name = "PLD_CLKOUT";
            pipeline = "0";
            BOARD_COMPONENT altera_nios_dev_board_cyclone_1c20
            {
               component_pin = "use_quartus_pin_assignment";
               pin_assignment = "";
            }
         }
      }
      hdl_language = "vhdl";
      device_family_id = "CYCLONE";
      view_master_columns = "1";
      view_master_priorities = "0";
      name_column_width = "75";
      desc_column_width = "75";
      bustype_column_width = "0";
      base_column_width = "75";
      clock_column_width = "120";
      end_column_width = "75";
      BOARD_INFO 
      {
         CONFIGURATION epcs
         {
            length = "";
            menu_position = "2";
            offset = "0x0";
            reference_designator = "U59";
         }
         CONFIGURATION factory
         {
            length = "";
            menu_position = "3";
            offset = "0x700000";
            reference_designator = "U5";
         }
         CONFIGURATION user
         {
            length = "";
            menu_position = "1";
            offset = "0x600000";
            reference_designator = "U5";
         }
         JTAG_device_index = "1";
         REFDES U5
         {
            base = "0x00800000";
         }
         REFDES U59
         {
            base = "0x00060000";
         }
         altera_avalon_cfi_flash 
         {
            reference_designators = "U5";
         }
         altera_avalon_epcs_flash_controller 
         {
            reference_designators = "U59";
         }
         class = "altera_nios_dev_board_cyclone_1c20";
         class_version = "5.0";
         device_family = "CYCLONE";
         quartus_pgm_file = "system/altera_nios_dev_board_cyclone_1c20.sof";
         quartus_project_file = "system/altera_nios_dev_board_cyclone_1c20.qpf";
         reference_designators = "U59,U5";
         sopc_system_file = "system/altera_nios_dev_board_cyclone_1c20.ptf";
      }
      RESETS 
      {
         RESET reset
         {
            BOARD_COMPONENT altera_nios_dev_board_cyclone_1c20
            {
               component_pin = "use_quartus_pin_assignment";
               pin_assignment = "";
            }
         }
      }
      view_frame_window = "maximized";
      do_log_history = "0";
   }
   MODULE cpu
   {
      class = "altera_nios2";
      class_version = "5.0";
      iss_model_name = "altera_nios2";
      HDL_INFO 
      {
         PLI_Files = "";
         Precompiled_Simulation_Library_Files = "";
         Simulation_HDL_Files = "";
         Synthesis_HDL_Files = "__PROJECT_DIRECTORY__/cpu_test_bench.v, __PROJECT_DIRECTORY__/cpu_jtag_debug_module.v, __PROJECT_DIRECTORY__/cpu_jtag_debug_module_wrapper.v, __PROJECT_DIRECTORY__/cpu.v";
         Synthesis_Only_Files = "";
      }
      MASTER instruction_master
      {
         PORT_WIRING 
         {
            PORT i_address
            {
               Is_Enabled = "1";
               direction = "output";
               type = "address";
               width = "26";
            }
            PORT i_read
            {
               Is_Enabled = "1";
               direction = "output";
               type = "read";
               width = "1";
            }
            PORT i_readdata
            {
               Is_Enabled = "1";
               direction = "input";
               type = "readdata";
               width = "32";
            }
            PORT i_readdatavalid
            {
               Is_Enabled = "1";
               direction = "input";
               type = "readdatavalid";
               width = "1";
            }
            PORT i_waitrequest
            {
               Is_Enabled = "1";
               direction = "input";
               type = "waitrequest";
               width = "1";
            }
         }
         SYSTEM_BUILDER_INFO 
         {
            Bus_Type = "avalon";
            Data_Width = "32";
            Max_Address_Width = "31";
            Address_Width = "8";
            Is_Instruction_Master = "1";
            Is_Readable = "1";
            Is_Writeable = "0";
            Address_Group = "0";
            Has_IRQ = "0";
            Irq_Scheme = "individual_requests";
            Interrupt_Range = "0-0";
            Is_Enabled = "1";
            Maximum_Burst_Size = "1";
            Burst_On_Burst_Boundaries_Only = "";
            Linewrap_Bursts = "";
            Interleave_Bursts = "";
         }
      }
      MASTER tightly_coupled_instruction_master_0
      {
         PORT_WIRING 
         {
         }
         SYSTEM_BUILDER_INFO 
         {
            Register_Incoming_Signals = "0";
            Bus_Type = "avalon";
            Data_Width = "32";
            Max_Address_Width = "31";
            Address_Width = "8";
            Is_Instruction_Master = "1";
            Has_IRQ = "0";
            Is_Enabled = "0";
            Connection_Limit = "1";
            Is_Channel = "1";
         }
      }
      MASTER tightly_coupled_instruction_master_1
      {
         PORT_WIRING 
         {
         }
         SYSTEM_BUILDER_INFO 
         {
            Register_Incoming_Signals = "0";
            Bus_Type = "avalon";
            Data_Width = "32";
            Max_Address_Width = "31";
            Address_Width = "8";
            Address_Group = "0";
            Is_Instruction_Master = "1";
            Is_Readable = "1";
            Is_Writeable = "0";
            Has_IRQ = "0";
            Is_Enabled = "0";
            Connection_Limit = "1";
            Is_Channel = "1";
         }
      }
      MASTER tightly_coupled_instruction_master_2
      {
         PORT_WIRING 
         {
         }
         SYSTEM_BUILDER_INFO 
         {
            Register_Incoming_Signals = "0";
            Bus_Type = "avalon";
            Data_Width = "32";
            Max_Address_Width = "31";
            Address_Width = "8";
            Address_Group = "0";
            Is_Instruction_Master = "1";
            Is_Readable = "1";
            Is_Writeable = "0";
            Has_IRQ = "0";
            Is_Enabled = "0";
            Connection_Limit = "1";
            Is_Channel = "1";
         }
      }
      MASTER tightly_coupled_instruction_master_3
      {
         PORT_WIRING 
         {
         }
         SYSTEM_BUILDER_INFO 
         {
            Register_Incoming_Signals = "0";
            Bus_Type = "avalon";
            Data_Width = "32";
            Max_Address_Width = "31";
            Address_Width = "8";
            Address_Group = "0";
            Is_Instruction_Master = "1";
            Is_Readable = "1";
            Is_Writeable = "0";
            Has_IRQ = "0";
            Is_Enabled = "0";
            Connection_Limit = "1";
            Is_Channel = "1";
         }
      }
      MASTER data_master
      {
         PORT_WIRING 
         {
            PORT clk
            {
               Is_Enabled = "1";
               direction = "input";
               type = "clk";
               width = "1";
            }
            PORT d_address
            {
               Is_Enabled = "1";
               direction = "output";
               type = "address";
               width = "26";
            }
            PORT d_byteenable
            {
               Is_Enabled = "1";
               direction = "output";
               type = "byteenable";
               width = "4";
            }
            PORT d_irq
            {
               Is_Enabled = "1";
               direction = "input";
               type = "irq";
               width = "32";
            }
            PORT d_read
            {
               Is_Enabled = "1";
               direction = "output";
               type = "read";
               width = "1";
            }
            PORT d_readdata
            {
               Is_Enabled = "1";
               direction = "input";
               type = "readdata";
               width = "32";
            }
            PORT d_waitrequest
            {
               Is_Enabled = "1";
               direction = "input";
               type = "waitrequest";
               width = "1";
            }
            PORT d_write
            {
               Is_Enabled = "1";
               direction = "output";
               type = "write";
               width = "1";
            }
            PORT d_writedata
            {
               Is_Enabled = "1";
               direction = "output";
               type = "writedata";
               width = "32";
            }
            PORT jtag_debug_module_debugaccess_to_roms
            {
               Is_Enabled = "1";
               direction = "output";
               type = "debugaccess";
               width = "1";
            }
         }
         SYSTEM_BUILDER_INFO 
         {
            Register_Incoming_Signals = "1";
            Bus_Type = "avalon";
            Data_Width = "32";
            Max_Address_Width = "31";
            Address_Width = "8";
            Address_Group = "0";
            Is_Data_Master = "1";
            Is_Readable = "1";
            Is_Writeable = "1";
            Has_IRQ = "1";
            Irq_Scheme = "individual_requests";
            Interrupt_Range = "0-31";
            Is_Enabled = "1";
            Maximum_Burst_Size = "1";
            Burst_On_Burst_Boundaries_Only = "";
            Adapts_To = "";
         }
      }
      MASTER data_master2
      {
         PORT_WIRING 
         {
         }
         SYSTEM_BUILDER_INFO 
         {
            Register_Incoming_Signals = "1";
            Bus_Type = "avalon";
            Data_Width = "32";
            Max_Address_Width = "31";
            Address_Width = "8";
            Address_Group = "0";
            Is_Data_Master = "1";
            Is_Readable = "1";
            Is_Writeable = "1";
            Has_IRQ = "0";
            Is_Enabled = "0";
         }
      }
      MASTER tightly_coupled_data_master_0
      {
         PORT_WIRING 
         {
         }
         SYSTEM_BUILDER_INFO 
         {
            Register_Incoming_Signals = "0";
            Bus_Type = "avalon";
            Data_Width = "32";
            Max_Address_Width = "31";
            Address_Width = "8";
            Address_Group = "0";
            Is_Data_Master = "1";
            Is_Readable = "1";
            Is_Writeable = "1";
            Has_IRQ = "0";
            Is_Enabled = "0";
            Connection_Limit = "1";
            Is_Channel = "1";
         }
      }
      MASTER tightly_coupled_data_master_1
      {
         PORT_WIRING 
         {
         }
         SYSTEM_BUILDER_INFO 
         {
            Register_Incoming_Signals = "0";
            Bus_Type = "avalon";
            Data_Width = "32";
            Max_Address_Width = "31";
            Address_Width = "8";
            Address_Group = "0";
            Is_Data_Master = "1";
            Is_Readable = "1";
            Is_Writeable = "1";
            Has_IRQ = "0";
            Is_Enabled = "0";
            Connection_Limit = "1";
            Is_Channel = "1";
         }
      }
      MASTER tightly_coupled_data_master_2
      {
         PORT_WIRING 
         {
         }
         SYSTEM_BUILDER_INFO 
         {
            Register_Incoming_Signals = "0";
            Bus_Type = "avalon";
            Data_Width = "32";
            Max_Address_Width = "31";
            Address_Width = "8";
            Address_Group = "0";
            Is_Data_Master = "1";
            Is_Readable = "1";
            Is_Writeable = "1";
            Has_IRQ = "0";
            Is_Enabled = "0";
            Connection_Limit = "1";
            Is_Channel = "1";
         }
      }
      MASTER tightly_coupled_data_master_3
      {
         PORT_WIRING 
         {
         }
         SYSTEM_BUILDER_INFO 
         {
            Register_Incoming_Signals = "0";
            Bus_Type = "avalon";
            Data_Width = "32";
            Max_Address_Width = "31";
            Address_Width = "8";
            Address_Group = "0";
            Is_Data_Master = "1";
            Is_Readable = "1";
            Is_Writeable = "1";
            Has_IRQ = "0";
            Is_Enabled = "0";
            Connection_Limit = "1";
            Is_Channel = "1";
         }
      }
      MASTER custom_instruction_master
      {
         PORT_WIRING 
         {
         }
         SYSTEM_BUILDER_INFO 
         {
            Bus_Type = "nios_custom_instruction";
            Data_Width = "32";
            Address_Width = "8";
            Max_Address_Width = "8";
            Base_Address = "N/A";
            Is_Visible = "0";
            Is_Custom_Instruction = "0";
            Is_Enabled = "0";
         }
      }
      SLAVE jtag_debug_module
      {
         PORT_WIRING 
         {
            PORT jtag_debug_module_address
            {
               Is_Enabled = "1";
               direction = "input";
               type = "address";
               width = "9";
            }
            PORT jtag_debug_module_begintransfer
            {
               Is_Enabled = "1";
               direction = "input";
               type = "begintransfer";
               width = "1";
            }
            PORT jtag_debug_module_byteenable
            {
               Is_Enabled = "1";
               direction = "input";
               type = "byteenable";
               width = "4";
            }
            PORT jtag_debug_module_clk
            {
               Is_Enabled = "1";
               direction = "input";
               type = "clk";
               width = "1";
            }
            PORT jtag_debug_module_debugaccess
            {
               Is_Enabled = "1";
               direction = "input";
               type = "debugaccess";
               width = "1";
            }
            PORT jtag_debug_module_readdata
            {
               Is_Enabled = "1";
               direction = "output";
               type = "readdata";
               width = "32";
            }
            PORT jtag_debug_module_reset
            {
               Is_Enabled = "1";
               direction = "input";
               type = "reset";
               width = "1";
            }
            PORT jtag_debug_module_resetrequest
            {
               Is_Enabled = "1";
               direction = "output";
               type = "resetrequest";
               width = "1";
            }
            PORT jtag_debug_module_select
            {
               Is_Enabled = "1";
               direction = "input";
               type = "chipselect";
               width = "1";
            }
            PORT jtag_debug_module_write
            {
               Is_Enabled = "1";
               direction = "input";
               type = "write";
               width = "1";
            }
            PORT jtag_debug_module_writedata
            {
               Is_Enabled = "1";
               direction = "input";
               type = "writedata";
               width = "32";
            }
            PORT reset_n
            {
               Is_Enabled = "1";
               direction = "input";
               type = "reset_n";
               width = "1";
            }
         }
         SYSTEM_BUILDER_INFO 
         {
            Read_Wait_States = "1";
            Write_Wait_States = "1";
            Register_Incoming_Signals = "1";
            Bus_Type = "avalon";
            Data_Width = "32";
            Address_Width = "9";
            Accepts_Internal_Connections = "1";
            Requires_Internal_Connections = "instruction_master,data_master";
            Accepts_External_Connections = "0";
            Is_Enabled = "1";
            Address_Alignment = "dynamic";
            Base_Address = "0x02120000";
            Is_Memory_Device = "1";
            Is_Readable = "1";
            Is_Writeable = "1";
            Is_Printable_Device = "0";
            Uses_Tri_State_Data_Bus = "0";
            Has_IRQ = "0";
            JTAG_Hub_Base_Id = "1118278";
            JTAG_Hub_Instance_Id = "0";
            MASTERED_BY cpu/instruction_master
            {
               priority = "1";
            }
            MASTERED_BY cpu/data_master
            {
               priority = "1";
            }
            IRQ_MASTER cpu/data_master
            {
               IRQ_Number = "NC";
            }
         }
      }
      PORT_WIRING 
      {
         PORT jtag_debug_trigout
         {
            width = "1";
            direction = "output";
            Is_Enabled = "0";
         }
         PORT jtag_debug_offchip_trace_clk
         {
            width = "1";
            direction = "output";
            Is_Enabled = "0";
         }
         PORT jtag_debug_offchip_trace_data
         {
            width = "18";
            direction = "output";
            Is_Enabled = "0";
         }
         PORT clkx2
         {
            width = "1";
            direction = "input";
            Is_Enabled = "0";
            visible = "0";
         }
      }
      WIZARD_SCRIPT_ARGUMENTS 
      {
         asp_debug = "0";
         asp_core_debug = "0";
         CPU_Architecture = "nios2";
         do_generate = "1";
         cpu_selection = "s";
         CPU_Implementation = "small";
         gui_include_tightly_coupled_instruction_masters = "0";
         gui_num_tightly_coupled_instruction_masters = "1";
         gui_omit_avalon_data_master = "0";
         gui_include_tightly_coupled_data_masters = "0";
         gui_num_tightly_coupled_data_masters = "1";
         num_tightly_coupled_instruction_masters = "0";
         num_tightly_coupled_data_masters = "0";
         cache_has_dcache = "0";
         cache_has_icache = "1";
         cache_dcache_size = "2048";
         cache_icache_size = "4096";
         cache_dcache_line_size = "4";
         cache_icache_line_size = "32";
         cache_dcache_bursts = "0";
         cache_icache_burst_type = "none";
         cache_dcache_ram_block_type = "AUTO";
         cache_icache_ram_block_type = "AUTO";
         include_debug = "0";
         include_trace = "0";
         include_oci = "1";
         include_third_party_debug_port = "0";
         debug_level = "2";
         oci_offchip_trace = "0";
         oci_onchip_trace = "0";
         oci_data_trace = "0";
         oci_trace_addr_width = "7";
         oci_num_xbrk = "0";
         oci_num_dbrk = "0";
         oci_dbrk_trace = "0";
         oci_dbrk_pairs = "0";
         oci_num_pm = "0";
         oci_pm_width = "40";
         oci_debugreq_signals = "0";
         oci_trigger_arming = "1";
         oci_embedded_pll = "1";
         hardware_multiply_present = "0";
         hardware_divide_present = "0";
         gui_hardware_multiply_setting = "no_mul_small_le_shift";
         hardware_multiply_uses_les = "0";
         hardware_multiply_omits_msw = "1";
         hardware_multiply_impl = "no_mul";
         gui_hardware_divide_setting = "0";
         reset_slave = "ext_flash/s1";
         reset_offset = "0x00000000";
         exc_slave = "sdram/s1";
         exc_offset = "0x00000020";
         break_slave = "cpu/jtag_debug_module";
         break_offset = "0x00000020";
         break_slave_override = "";
         break_offset_override = "0x20";
         legacy_sdk_support = "0";
         altera_show_unreleased_features = "0";
         full_waveform_signals = "0";
         illegal_instructions_trap = "0";
         gui_branch_prediction_type = "Automatic";
         branch_prediction_type = "Static";
         bht_ptr_sz = "8";
         bht_index_pc_only = "0";
         shift_rot_impl = "small_le_shift";
         mmu_present = "0";
         process_id_num_bits = "10";
         dtlb_ptr_sz = "7";
         dtlb_num_ways = "4";
         udtlb_num_entries = "6";
         itlb_ptr_sz = "7";
         itlb_num_ways = "4";
         uitlb_num_entries = "4";
         fast_tlb_miss_exc_slave = "";
         fast_tlb_miss_exc_offset = "0x0";
         cache_omit_dcache = "0";
         cache_omit_icache = "0";
         omit_instruction_master = "0";
         omit_data_master = "0";
         altera_internal_test = "0";
         performance_counters_present = "0";
         performance_counters_width = "32";
         ras_ptr_sz = "4";
         jtb_ptr_sz = "5";
         ibuf_ptr_sz = "4";
         always_encrypt = "1";
         activate_model_checker = "0";
         activate_monitors = "1";
         activate_test_end_checker = "0";
         activate_trace = "1";
         clear_x_bits_ld_non_bypass = "1";
         bit_31_bypass_dcache = "1";
         always_bypass_dcache = "0";
         hdl_sim_caches_cleared = "1";
         consistent_synthesis = "0";
         hbreak_test = "0";
         allow_full_address_range = "0";
         iss_trace_on = "0";
         iss_trace_warning = "1";
         iss_trace_info = "1";
         iss_trace_disassembly = "0";
         iss_trace_registers = "0";
         iss_trace_instr_count = "0";
         iss_software_debug = "0";
         iss_software_debug_port = "9996";
         iss_memory_dump_start = "";
         iss_memory_dump_end = "";
         Boot_Copier = "boot_loader_cfi.srec";
         Boot_Copier_EPCS = "boot_loader_epcs.srec";
         CONSTANTS 
         {
            CONSTANT __nios_catch_irqs__
            {
               value = "1";
               comment = "Include panic handler for all irqs (needs uart)";
            }
            CONSTANT __nios_use_constructors__
            {
               value = "1";
               comment = "Call c++ static constructors";
            }
            CONSTANT __nios_use_small_printf__
            {
               value = "1";
               comment = "Smaller non-ANSI printf, with no floating point";
            }
            CONSTANT nasys_has_icache
            {
               value = "1";
               comment = "True if instruction cache present";
            }
            CONSTANT nasys_icache_size
            {
               value = "4096";
               comment = "Size in bytes of instruction cache";
            }
            CONSTANT nasys_icache_line_size
            {
               value = "32";
               comment = "Size in bytes of each icache line";
            }
            CONSTANT nasys_icache_line_size_log2
            {
               value = "5";
               comment = "Log2 size in bytes of each icache line";
            }
            CONSTANT nasys_has_dcache
            {
               value = "0";
               comment = "True if instruction cache present";
            }
            CONSTANT nasys_dcache_size
            {
               value = "2048";
               comment = "Size in bytes of data cache";
            }
            CONSTANT nasys_dcache_line_size
            {
               value = "4";
               comment = "Size in bytes of each dcache line";
            }
            CONSTANT nasys_dcache_line_size_log2
            {
               value = "2";
               comment = "Log2 size in bytes of each dcache line";
            }
         }
         license_status = "ocp";
         germs_monitor_id = "";
         cpuid_sz = "1";
         cpuid_value = "0";
         gui_illegal_instructions_trap = "0";
         gui_illegal_memory_access_detection = "0";
         illegal_memory_access_detection = "0";
         gui_mmu_present = "0";
      }
      SYSTEM_BUILDER_INFO 
      {
         Parameters_Signature = "";
         Is_CPU = "1";
         Is_Enabled = "1";
         Instantiate_In_System_Module = "1";
         Required_Device_Family = "STRATIX,STRATIXGX,STRATIXII,STRATIXIIGX,CYCLONE,CYCLONEII";
         Default_Module_Name = "cpu";
         Top_Level_Ports_Are_Enumerated = "1";
         Clock_Source = "sysclk2";
         View 
         {
            MESSAGES 
            {
            }
            Is_Collapsed = "1";
            Settings_Summary = "Nios II/s
            <br>&nbsp;&nbsp;4-Kbyte Instruction Cache
            
            <br>&nbsp;&nbsp;JTAG Debug Module
            ";
         }
      }
      SOFTWARE_COMPONENT altera_plugs_library
      {
         class = "altera_plugs_library";
         class_version = "2.1";
         WIZARD_SCRIPT_ARGUMENTS 
         {
            CONSTANTS 
            {
               CONSTANT PLUGS_PLUG_COUNT
               {
                  value = "5";
                  comment = "Maximum number of plugs";
               }
               CONSTANT PLUGS_ADAPTER_COUNT
               {
                  value = "2";
                  comment = "Maximum number of adapters";
               }
               CONSTANT PLUGS_DNS
               {
                  value = "1";
                  comment = "Have routines for DNS lookups";
               }
               CONSTANT PLUGS_PING
               {
                  value = "1";
                  comment = "Respond to icmp echo (ping) messages";
               }
               CONSTANT PLUGS_TCP
               {
                  value = "1";
                  comment = "Support tcp in/out connections";
               }
               CONSTANT PLUGS_IRQ
               {
                  value = "1";
                  comment = "Run at interrupte level";
               }
               CONSTANT PLUGS_DEBUG
               {
                  value = "1";
                  comment = "Support debug routines";
               }
            }
         }
         SYSTEM_BUILDER_INFO 
         {
            Is_Enabled = "1";
         }
      }
      SIMULATION 
      {
         DISPLAY 
         {
            SIGNAL aaa
            {
               format = "Logic";
               name = "i_readdata";
               radix = "hexadecimal";
            }
            SIGNAL aab
            {
               format = "Logic";
               name = "i_readdatavalid";
               radix = "hexadecimal";
            }
            SIGNAL aac
            {
               format = "Logic";
               name = "i_waitrequest";
               radix = "hexadecimal";
            }
            SIGNAL aad
            {
               format = "Logic";
               name = "i_address";
               radix = "hexadecimal";
            }
            SIGNAL aae
            {
               format = "Logic";
               name = "i_read";
               radix = "hexadecimal";
            }
            SIGNAL aaf
            {
               format = "Logic";
               name = "clk";
               radix = "hexadecimal";
            }
            SIGNAL aag
            {
               format = "Logic";
               name = "reset_n";
               radix = "hexadecimal";
            }
            SIGNAL aah
            {
               format = "Logic";
               name = "d_readdata";
               radix = "hexadecimal";
            }
            SIGNAL aai
            {
               format = "Logic";
               name = "d_waitrequest";
               radix = "hexadecimal";
            }
            SIGNAL aaj
            {
               format = "Logic";
               name = "d_irq";
               radix = "hexadecimal";
            }
            SIGNAL aak
            {
               format = "Logic";
               name = "d_address";
               radix = "hexadecimal";
            }
            SIGNAL aal
            {
               format = "Logic";
               name = "d_byteenable";
               radix = "hexadecimal";
            }
            SIGNAL aam
            {
               format = "Logic";
               name = "d_read";
               radix = "hexadecimal";
            }
            SIGNAL aan
            {
               format = "Logic";
               name = "d_write";
               radix = "hexadecimal";
            }
            SIGNAL aao
            {
               format = "Logic";
               name = "d_writedata";
               radix = "hexadecimal";
            }
            SIGNAL aap
            {
               format = "Divider";
               name = "base pipeline";
               radix = "";
            }
            SIGNAL aaq
            {
               format = "Logic";
               name = "clk";
               radix = "hexadecimal";
            }
            SIGNAL aar
            {
               format = "Logic";
               name = "reset_n";
               radix = "hexadecimal";
            }
            SIGNAL aas
            {
               format = "Logic";
               name = "M_stall";
               radix = "hexadecimal";
            }
            SIGNAL aat
            {
               format = "Logic";
               name = "F_pcb_nxt";
               radix = "hexadecimal";
            }
            SIGNAL aau
            {
               format = "Logic";
               name = "F_pcb";
               radix = "hexadecimal";
            }
            SIGNAL aav
            {
               format = "Logic";
               name = "D_pcb";
               radix = "hexadecimal";
            }
            SIGNAL aaw
            {
               format = "Logic";
               name = "E_pcb";
               radix = "hexadecimal";
            }
            SIGNAL aax
            {
               format = "Logic";
               name = "M_pcb";
               radix = "hexadecimal";
            }
            SIGNAL aay
            {
               format = "Logic";
               name = "W_pcb";
               radix = "hexadecimal";
            }
            SIGNAL aaz
            {
               format = "Logic";
               name = "F_vinst";
               radix = "ascii";
            }
            SIGNAL aba
            {
               format = "Logic";
               name = "D_vinst";
               radix = "ascii";
            }
            SIGNAL abb
            {
               format = "Logic";
               name = "E_vinst";
               radix = "ascii";
            }
            SIGNAL abc
            {
               format = "Logic";
               name = "M_vinst";
               radix = "ascii";
            }
            SIGNAL abd
            {
               format = "Logic";
               name = "W_vinst";
               radix = "ascii";
            }
            SIGNAL abe
            {
               format = "Logic";
               name = "F_inst_ram_hit";
               radix = "hexadecimal";
            }
            SIGNAL abf
            {
               format = "Logic";
               name = "F_issue";
               radix = "hexadecimal";
            }
            SIGNAL abg
            {
               format = "Logic";
               name = "F_kill";
               radix = "hexadecimal";
            }
            SIGNAL abh
            {
               format = "Logic";
               name = "D_kill";
               radix = "hexadecimal";
            }
            SIGNAL abi
            {
               format = "Logic";
               name = "D_refetch";
               radix = "hexadecimal";
            }
            SIGNAL abj
            {
               format = "Logic";
               name = "D_issue";
               radix = "hexadecimal";
            }
            SIGNAL abk
            {
               format = "Logic";
               name = "D_valid";
               radix = "hexadecimal";
            }
            SIGNAL abl
            {
               format = "Logic";
               name = "E_valid";
               radix = "hexadecimal";
            }
            SIGNAL abm
            {
               format = "Logic";
               name = "M_valid";
               radix = "hexadecimal";
            }
            SIGNAL abn
            {
               format = "Logic";
               name = "W_valid";
               radix = "hexadecimal";
            }
            SIGNAL abo
            {
               format = "Logic";
               name = "W_wr_dst_reg";
               radix = "hexadecimal";
            }
            SIGNAL abp
            {
               format = "Logic";
               name = "W_dst_regnum";
               radix = "hexadecimal";
            }
            SIGNAL abq
            {
               format = "Logic";
               name = "W_wr_data";
               radix = "hexadecimal";
            }
            SIGNAL abr
            {
               format = "Logic";
               name = "F_en";
               radix = "hexadecimal";
            }
            SIGNAL abs
            {
               format = "Logic";
               name = "D_en";
               radix = "hexadecimal";
            }
            SIGNAL abt
            {
               format = "Logic";
               name = "E_en";
               radix = "hexadecimal";
            }
            SIGNAL abu
            {
               format = "Logic";
               name = "M_en";
               radix = "hexadecimal";
            }
            SIGNAL abv
            {
               format = "Logic";
               name = "F_iw";
               radix = "hexadecimal";
            }
            SIGNAL abw
            {
               format = "Logic";
               name = "D_iw";
               radix = "hexadecimal";
            }
            SIGNAL abx
            {
               format = "Logic";
               name = "E_iw";
               radix = "hexadecimal";
            }
            SIGNAL aby
            {
               format = "Logic";
               name = "E_valid_prior_to_hbreak";
               radix = "hexadecimal";
            }
            SIGNAL abz
            {
               format = "Logic";
               name = "M_pipe_flush_nxt";
               radix = "hexadecimal";
            }
            SIGNAL aca
            {
               format = "Logic";
               name = "M_pipe_flush_baddr_nxt";
               radix = "hexadecimal";
            }
            SIGNAL acb
            {
               format = "Logic";
               name = "M_status_reg_pie";
               radix = "hexadecimal";
            }
            SIGNAL acc
            {
               format = "Logic";
               name = "M_ienable_reg";
               radix = "hexadecimal";
            }
            SIGNAL acd
            {
               format = "Logic";
               name = "intr_req";
               radix = "hexadecimal";
            }
         }
      }
   }
   MODULE ext_ram_bus
   {
      class = "altera_avalon_tri_state_bridge";
      class_version = "2.0";
      SLAVE avalon_slave
      {
         SYSTEM_BUILDER_INFO 
         {
            Bus_Type = "avalon";
            Bridges_To = "tristate_master";
            Base_Address = "N/A";
            Has_IRQ = "0";
            IRQ = "N/A";
            Register_Outgoing_Signals = "1";
            Register_Incoming_Signals = "1";
            MASTERED_BY cpu/instruction_master
            {
               priority = "1";
            }
            MASTERED_BY cpu/data_master
            {
               priority = "1";
            }
            IRQ_MASTER cpu/data_master
            {
               IRQ_Number = "NC";
            }
         }
      }
      MASTER tristate_master
      {
         SYSTEM_BUILDER_INFO 
         {
            Bus_Type = "avalon_tristate";
            Bridges_To = "avalon_slave";
         }
      }
      SYSTEM_BUILDER_INFO 
      {
         Instantiate_In_System_Module = "1";
         Is_Enabled = "1";
         Is_Bridge = "1";
         Top_Level_Ports_Are_Enumerated = "1";
         Clock_Source = "sysclk2";
         View 
         {
            MESSAGES 
            {
            }
            Is_Collapsed = "1";
         }
      }
   }
   MODULE ext_flash
   {
      class = "altera_avalon_cfi_flash";
      class_version = "1.1";
      iss_model_name = "altera_avalon_flash";
      HDL_INFO 
      {
      }
      SLAVE s1
      {
         PORT_WIRING 
         {
            PORT data
            {
               width = "8";
               is_shared = "1";
               direction = "inout";
               type = "data";
               originally_shared = "1";
               BOARD_COMPONENT altera_nios_dev_board_cyclone_1c20
               {
                  component_pin = "U5.31,U5.32,U5.33,U5.34,U5.38,U5.39,U5.40,U5.41";
                  pin_assignment = "C6,E6,B6,A6,F7,E7,B7,A7";
               }
            }
            PORT address
            {
               width = "23";
               is_shared = "1";
               direction = "input";
               type = "address";
               originally_shared = "1";
               BOARD_COMPONENT altera_nios_dev_board_cyclone_1c20
               {
                  component_pin = "U5.27,U5.22,U5.21,U5.20,U5.19,U5.18,U5.17,U5.16,U5.10,U5.9,U5.42,U5.8,U5.7,U5.6,U5.5,U5.4,U5.3,U5.46,U5.15,U5.43,U5.44,U5.35,U5.2";
                  pin_assignment = "B4,A4,D5,D6,C5,B5,C2,D2,D4,D1,E4,E5,F3,E3,E2,F4,F5,F2,F1,F6,G5,G1,G2";
               }
            }
            PORT read_n
            {
               width = "1";
               is_shared = "0";
               direction = "input";
               type = "read_n";
               originally_shared = "1";
               BOARD_COMPONENT altera_nios_dev_board_cyclone_1c20
               {
                  component_pin = "U5.30";
                  pin_assignment = "B12";
               }
            }
            PORT write_n
            {
               width = "1";
               is_shared = "0";
               direction = "input";
               type = "write_n";
               originally_shared = "0";
               BOARD_COMPONENT altera_nios_dev_board_cyclone_1c20
               {
                  component_pin = "U5.11";
                  pin_assignment = "D12";
               }
            }
            PORT select_n
            {
               width = "1";
               is_shared = "0";
               direction = "input";
               type = "chipselect_n";
               originally_shared = "0";
               BOARD_COMPONENT altera_nios_dev_board_cyclone_1c20
               {
                  component_pin = "U5.28";
                  pin_assignment = "A12";
               }
            }
         }
         WIZARD_SCRIPT_ARGUMENTS 
         {
            class = "altera_avalon_cfi_flash";
            Supports_Flash_File_System = "1";
            flash_reference_designator = "U5";
         }
         SYSTEM_BUILDER_INFO 
         {
            Bus_Type = "avalon_tristate";
            Is_Nonvolatile_Storage = "1";
            Is_Memory_Device = "1";
            Address_Alignment = "dynamic";
            Has_IRQ = "0";
            Base_Address = "0x00000000";
            Data_Width = "8";
            Address_Width = "23";
            Simulation_Num_Lanes = "1";
            Convert_Xs_To_0 = "1";
            Write_Wait_States = "160ns";
            Read_Wait_States = "160ns";
            Setup_Time = "40ns";
            Hold_Time = "40ns";
            Address_Span = "8388608";
            MASTERED_BY ext_ram_bus/tristate_master
            {
               priority = "1";
            }
            IRQ_MASTER cpu/data_master
            {
               IRQ_Number = "NC";
            }
            Is_Base_Locked = "1";
         }
      }
      SYSTEM_BUILDER_INFO 
      {
         Make_Memory_Model = "1";
         Is_Enabled = "1";
         Instantiate_In_System_Module = "0";
         Top_Level_Ports_Are_Enumerated = "1";
         Clock_Source = "sysclk2";
         View 
         {
            MESSAGES 
            {
            }
            Is_Collapsed = "1";
         }
      }
      WIZARD_SCRIPT_ARGUMENTS 
      {
         Setup_Value = "40";
         Wait_Value = "160";
         Hold_Value = "40";
         Timing_Units = "ns";
         Unit_Multiplier = "1";
         Size = "8388608";
         MAKE 
         {
            MACRO 
            {
               EXT_FLASH_FLASHTARGET_ALT_SIM_PREFIX = "$(EXT_FLASH_FLASHTARGET_TMP1:0=)";
               EXT_FLASH_FLASHTARGET_TMP1 = "$(ALT_SIM_OPTIMIZE:1=RUN_ON_HDL_SIMULATOR_ONLY_)";
            }
            MASTER cpu
            {
               MACRO 
               {
                  BOOT_COPIER = "boot_loader_cfi.srec";
                  CPU_CLASS = "altera_nios2";
                  CPU_RESET_ADDRESS = "0x0";
               }
            }
            TARGET delete_placeholder_warning
            {
               ext_flash 
               {
                  Command1 = "rm -f $(SIMDIR)/contents_file_warning.txt";
                  Is_Phony = "1";
                  Target_File = "do_delete_placeholder_warning";
               }
            }
            TARGET factory
            {
               ext_flash 
               {
                  All_Depends_On = "0";
                  Command1 = "sof2flash --flash=U5 --offset=0x700000 --output=factory.flash $(SOF) ";
                  Command2 = "nios2-flash-programmer --input=factory.flash --sof=$(shell $(QUARTUS_ROOTDIR)/sopc_builder/bin/find_sopc_component_dir altera_nios_dev_board_cyclone_1c20 $(QUARTUS_PROJECT_DIR))/system/altera_nios_dev_board_cyclone_1c20.sof --device=1 $(JTAG_CABLE) --base=0x00800000 ";
                  Dependency = "";
                  Is_Phony = "1";
                  Target_File = "ext_flash_factory_configuration";
               }
            }
            TARGET flashfiles
            {
               ext_flash 
               {
                  Command1 = "@echo Post-processing to create $(notdir $@)";
                  Command2 = "elf2flash --input=$(ELF) --flash=U5 --boot=$(shell $(QUARTUS_ROOTDIR)/sopc_builder/bin/find_sopc_component_dir $(CPU_CLASS) $(QUARTUS_PROJECT_DIR))/$(BOOT_COPIER) --outfile=$(EXT_FLASH_FLASHTARGET_ALT_SIM_PREFIX)ext_flash.flash --sim_optimize=$(ALT_SIM_OPTIMIZE) --base=0x0 --end=0x7FFFFF --reset=$(CPU_RESET_ADDRESS) ";
                  Dependency = "$(ELF)";
                  Target_File = "$(EXT_FLASH_FLASHTARGET_ALT_SIM_PREFIX)ext_flash.flash";
               }
            }
            TARGET programflash
            {
               ext_flash 
               {
                  All_Depends_On = "0";
                  Command1 = "nios2-flash-programmer --input=$(EXT_FLASH_FLASHTARGET_ALT_SIM_PREFIX)ext_flash.flash --sof=$(shell $(QUARTUS_ROOTDIR)/sopc_builder/bin/find_sopc_component_dir altera_nios_dev_board_cyclone_1c20 $(QUARTUS_PROJECT_DIR))/system/altera_nios_dev_board_cyclone_1c20.sof --device=1 $(JTAG_CABLE) --base=0x00800000 ";
                  Dependency = "$(EXT_FLASH_FLASHTARGET_ALT_SIM_PREFIX)ext_flash.flash";
                  Is_Phony = "1";
                  Target_File = "ext_flash_programflash";
               }
            }
            TARGET programflashnoelfdependency
            {
               ext_flash 
               {
                  All_Depends_On = "0";
                  Command1 = "nios2-flash-programmer --input=$(EXT_FLASH_FLASHTARGET_ALT_SIM_PREFIX)ext_flash.flash --sof=$(shell $(QUARTUS_ROOTDIR)/sopc_builder/bin/find_sopc_component_dir altera_nios_dev_board_cyclone_1c20 $(QUARTUS_PROJECT_DIR))/system/altera_nios_dev_board_cyclone_1c20.sof --device=1 $(JTAG_CABLE) --base=0x00800000 ";
                  Is_Phony = "1";
                  Target_File = "ext_flash_programflashnoelf";
               }
            }
            TARGET user
            {
               ext_flash 
               {
                  All_Depends_On = "0";
                  Command1 = "sof2flash --flash=U5 --offset=0x600000 --output=user.flash $(SOF) ";
                  Command2 = "nios2-flash-programmer --input=user.flash --sof=$(shell $(QUARTUS_ROOTDIR)/sopc_builder/bin/find_sopc_component_dir altera_nios_dev_board_cyclone_1c20 $(QUARTUS_PROJECT_DIR))/system/altera_nios_dev_board_cyclone_1c20.sof --device=1 $(JTAG_CABLE) --base=0x00800000 ";
                  Dependency = "";
                  Is_Phony = "1";
                  Target_File = "ext_flash_user_configuration";
               }
            }
            TARGET sim
            {
               ext_flash 
               {
                  Command1 = "if [ ! -d $(SIMDIR) ]; then mkdir $(SIMDIR) ; fi";
                  Command2 = "@echo Hardware simulation is not enabled for the target SOPC Builder system. Skipping creation of hardware simulation model contents and simulation symbol files. \\(Note: This does not affect the instruction set simulator.\\)";
                  Command3 = "touch $(SIMDIR)/dummy_file";
                  Dependency = "$(ELF)";
                  Target_File = "$(SIMDIR)/dummy_file";
               }
            }
         }
         contents_info = "SIMDIR/ext_flash.dat 1124853268 ";
      }
   }
   MODULE ext_ram
   {
      class = "altera_nios_dev_kit_stratix_edition_sram2";
      class_version = "1.0";
      iss_model_name = "altera_memory";
      HDL_INFO 
      {
      }
      WIZARD_SCRIPT_ARGUMENTS 
      {
         sram_memory_size = "1024";
         sram_memory_units = "1024";
         sram_data_width = "32";
         MAKE 
         {
            TARGET delete_placeholder_warning
            {
               ext_ram 
               {
                  Command1 = "rm -f $(SIMDIR)/contents_file_warning.txt";
                  Is_Phony = "1";
                  Target_File = "do_delete_placeholder_warning";
               }
            }
            TARGET sim
            {
               ext_ram 
               {
                  Command1 = "if [ ! -d $(SIMDIR) ]; then mkdir $(SIMDIR) ; fi";
                  Command2 = "@echo Hardware simulation is not enabled for the target SOPC Builder system. Skipping creation of hardware simulation model contents and simulation symbol files. \\(Note: This does not affect the instruction set simulator.\\)";
                  Command3 = "touch $(SIMDIR)/dummy_file";
                  Dependency = "$(ELF)";
                  Target_File = "$(SIMDIR)/dummy_file";
               }
            }
         }
         contents_info = "SIMDIR/ext_ram_lane0.dat 1124853270 SIMDIR/ext_ram_lane3.dat 1124853270 SIMDIR/ext_ram_lane2.dat 1124853270 SIMDIR/ext_ram.dat 1124853270 SIMDIR/ext_ram_lane1.dat 1124853270 ";
      }
      SLAVE s1
      {
         PORT_WIRING 
         {
            PORT data
            {
               width = "32";
               is_shared = "1";
               direction = "inout";
               type = "data";
               originally_shared = "1";
               BOARD_COMPONENT altera_nios_dev_board_cyclone_1c20
               {
                  pin_assignment = "C6,E6,B6,A6,F7,E7,B7,A7,D7,C7,F8,E8,B8,A8,D8,C8,B9,A9,D9,C9,E9,E10,B10,A10,F10,C10,D10,C11,D11,B11,A11,E11";
                  component_pin = "U35-U36.D0,U35-U36.D1,U35-U36.D2,U35-U36.D3,U35-U36.D4,U35-U36.D5,U35-U36.D6,U35-U36.D7,U35-U36.D8,U35-U36.D9,U35-U36.D10,U35-U36.D11,U35-U36.D12,U35-U36.D13,U35-U36.D14,U35-U36.D15,U35-U36.D16,U35-U36.D17,U35-U36.D18,U35-U36.D19,U35-U36.D20,U35-U36.D21,U35-U36.D22,U35-U36.D23,U35-U36.D24,U35-U36.D25,U35-U36.D26,U35-U36.D27,U35-U36.D28,U35-U36.D29,U35-U36.D30,U35-U36.D31";
               }
            }
            PORT address
            {
               width = "18";
               is_shared = "1";
               direction = "input";
               type = "address";
               originally_shared = "1";
               lsb = "2";
               BOARD_COMPONENT altera_nios_dev_board_cyclone_1c20
               {
                  pin_assignment = "D5,D6,C5,B5,C2,D2,D4,D1,E4,E5,F3,E3,E2,F4,F5,F2,F1,F6";
                  component_pin = "U35-U36.A0,U35-U36.A1,U35-U36.A2,U35-U36.A3,U35-U36.A4,U35-U36.A5,U35-U36.A6,U35-U36.A7,U35-U36.A8,U35-U36.A9,U35-U36.A10,U35-U36.A11,U35-U36.A12,U35-U36.A13,U35-U36.A14,U35-U36.A15,U35-U36.A16,U35-U36.A17";
               }
            }
            PORT read_n
            {
               width = "1";
               is_shared = "0";
               direction = "input";
               type = "read_n";
               originally_shared = "0";
               BOARD_COMPONENT altera_nios_dev_board_cyclone_1c20
               {
                  component_pin = "U35-U36.OE_n";
                  pin_assignment = "Y17";
               }
            }
            PORT write_n
            {
               width = "1";
               is_shared = "0";
               direction = "input";
               type = "write_n";
               originally_shared = "0";
               BOARD_COMPONENT altera_nios_dev_board_cyclone_1c20
               {
                  pin_assignment = "U16";
                  component_pin = "U35-U36.WE_n";
               }
            }
            PORT be_n
            {
               width = "4";
               is_shared = "0";
               direction = "input";
               type = "byteenable_n";
               originally_shared = "0";
               BOARD_COMPONENT altera_nios_dev_board_cyclone_1c20
               {
                  pin_assignment = "V17,V16,W16,T16";
                  component_pin = "U35-U36.BE_n0,U35-U36.BE_n1,U35-U36.BE_n2,U35-U36.BE_n3";
               }
            }
            PORT select_n
            {
               width = "1";
               is_shared = "0";
               direction = "input";
               type = "chipselect_n";
               originally_shared = "0";
               BOARD_COMPONENT altera_nios_dev_board_cyclone_1c20
               {
                  pin_assignment = "W17";
                  component_pin = "U35-U36.CS_n";
               }
            }
         }
         SYSTEM_BUILDER_INFO 
         {
            Bus_Type = "avalon_tristate";
            Is_Memory_Device = "1";
            Address_Alignment = "dynamic";
            Data_Width = "32";
            Address_Width = "18";
            Has_IRQ = "0";
            Read_Wait_States = "0ns";
            Write_Wait_States = "0ns";
            Hold_Time = "half";
            Base_Address = "0x02000000";
            Address_Span = "1048576";
            MASTERED_BY ext_ram_bus/tristate_master
            {
               priority = "1";
            }
            IRQ_MASTER cpu/data_master
            {
               IRQ_Number = "NC";
            }
            Is_Base_Locked = "1";
            Setup_Time = "0";
         }
      }
      SYSTEM_BUILDER_INFO 
      {
         Is_Enabled = "1";
         Instantiate_In_System_Module = "0";
         Make_Memory_Model = "1";
         Default_Module_Name = "sram";
         Top_Level_Ports_Are_Enumerated = "1";
         View 
         {
            MESSAGES 
            {
            }
            Is_Collapsed = "1";
         }
         Clock_Source = "sysclk2";
      }
   }
   MODULE epcs_controller
   {
      class = "altera_avalon_epcs_flash_controller";
      class_version = "2.1";
      SLAVE epcs_control_port
      {
         SYSTEM_BUILDER_INFO 
         {
            Bus_Type = "avalon";
            Is_Nonvolatile_Storage = "1";
            Is_Printable_Device = "0";
            Address_Alignment = "dynamic";
            Is_Memory_Device = "1";
            Address_Width = "9";
            Data_Width = "32";
            Has_IRQ = "1";
            Read_Wait_States = "1";
            Write_Wait_States = "1";
            MASTERED_BY cpu/instruction_master
            {
               priority = "1";
            }
            MASTERED_BY cpu/data_master
            {
               priority = "1";
            }
            IRQ_MASTER cpu/data_master
            {
               IRQ_Number = "5";
            }
            Base_Address = "0x02100000";
         }
         WIZARD_SCRIPT_ARGUMENTS 
         {
            class = "altera_avalon_epcs_flash_controller";
            flash_reference_designator = "U59";
         }
         PORT_WIRING 
         {
            PORT address
            {
               Is_Enabled = "1";
               direction = "input";
               type = "address";
               width = "9";
            }
            PORT chipselect
            {
               Is_Enabled = "1";
               direction = "input";
               type = "chipselect";
               width = "1";
            }
            PORT clk
            {
               Is_Enabled = "1";
               direction = "input";
               type = "clk";
               width = "1";
            }
            PORT data_from_cpu
            {
               Is_Enabled = "0";
               direction = "input";
               type = "writedata";
               width = "16";
            }
            PORT data_to_cpu
            {
               Is_Enabled = "0";
               direction = "output";
               type = "readdata";
               width = "16";
            }
            PORT dataavailable
            {
               Is_Enabled = "1";
               direction = "output";
               type = "dataavailable";
               width = "1";
            }
            PORT endofpacket
            {
               Is_Enabled = "1";
               direction = "output";
               type = "endofpacket";
               width = "1";
            }
            PORT epcs_select
            {
               Is_Enabled = "0";
               direction = "input";
               type = "chipselect";
               width = "1";
            }
            PORT irq
            {
               Is_Enabled = "1";
               direction = "output";
               type = "irq";
               width = "1";
            }
            PORT mem_addr
            {
               Is_Enabled = "0";
               direction = "input";
               type = "address";
               width = "3";
            }
            PORT read_n
            {
               Is_Enabled = "1";
               direction = "input";
               type = "read_n";
               width = "1";
            }
            PORT readdata
            {
               Is_Enabled = "1";
               direction = "output";
               type = "readdata";
               width = "32";
            }
            PORT readyfordata
            {
               Is_Enabled = "1";
               direction = "output";
               type = "readyfordata";
               width = "1";
            }
            PORT reset_n
            {
               Is_Enabled = "1";
               direction = "input";
               type = "reset_n";
               width = "1";
            }
            PORT write_n
            {
               Is_Enabled = "1";
               direction = "input";
               type = "write_n";
               width = "1";
            }
            PORT writedata
            {
               Is_Enabled = "1";
               direction = "input";
               type = "writedata";
               width = "32";
            }
         }
      }
      SYSTEM_BUILDER_INFO 
      {
         Is_Enabled = "1";
         Instantiate_In_System_Module = "1";
         Required_Device_Family = "CYCLONE,CYCLONEII,STRATIXII,STRATIXIIGX";
         Fixed_Module_Name = "epcs_controller";
         Top_Level_Ports_Are_Enumerated = "1";
         Clock_Source = "sysclk2";
         View 
         {
            MESSAGES 
            {
            }
            Is_Collapsed = "1";
         }
      }
      WIZARD_SCRIPT_ARGUMENTS 
      {
         databits = "8";
         targetclock = "20";
         clockunits = "MHz";
         clockmult = "1000000";
         numslaves = "1";
         ismaster = "1";
         clockpolarity = "0";
         clockphase = "0";
         lsbfirst = "0";
         extradelay = "0";
         targetssdelay = "100";
         delayunits = "us";
         delaymult = "1e-006";
         prefix = "epcs_";
         register_offset = "0x200";
         MAKE 
         {
            MACRO 
            {
               EPCS_CONTROLLER_BOOT_ROM_FLASHTARGET_ALT_SIM_PREFIX = "$(EPCS_CONTROLLER_BOOT_ROM_FLASHTARGET_TMP1:0=)";
               EPCS_CONTROLLER_BOOT_ROM_FLASHTARGET_TMP1 = "$(ALT_SIM_OPTIMIZE:1=RUN_ON_HDL_SIMULATOR_ONLY_)";
               EPCS_RELOCATE = "$(EPCS_RELOCATE_TMP:1=--relocate)";
               EPCS_RELOCATE_TMP = "$(BOOTS_FROM_EPCS:0=)";
            }
            MASTER cpu
            {
               MACRO 
               {
                  BOOTS_FROM_EPCS = "0";
                  BOOT_COPIER_EPCS = "boot_loader_epcs.srec";
                  CPU_CLASS = "altera_nios2";
                  CPU_RESET_ADDRESS = "0x0";
               }
            }
            TARGET delete_placeholder_warning
            {
               epcs_controller 
               {
                  Command1 = "rm -f $(SIMDIR)/contents_file_warning.txt";
                  Is_Phony = "1";
                  Target_File = "do_delete_placeholder_warning";
               }
            }
            TARGET epcs
            {
               epcs_controller 
               {
                  All_Depends_On = "0";
                  Command1 = "sof2flash --flash=U59 --offset=0x0 --output=epcs.flash $(SOF) --epcs ";
                  Command2 = "nios2-flash-programmer --input=epcs.flash --sof=$(shell $(QUARTUS_ROOTDIR)/sopc_builder/bin/find_sopc_component_dir altera_nios_dev_board_cyclone_1c20 $(QUARTUS_PROJECT_DIR))/system/altera_nios_dev_board_cyclone_1c20.sof --device=1 $(JTAG_CABLE) --epcs $(EPCS_RELOCATE) ";
                  Dependency = "";
                  Is_Phony = "1";
                  Target_File = "epcs_controller_boot_rom_epcs_configuration";
               }
            }
            TARGET flashfiles
            {
               epcs_controller 
               {
                  Command1 = "@if [ $(BOOTS_FROM_EPCS) -eq 1 ]; then echo Post-processing to create $(notdir $@) ; elf2flash --input=$(ELF) --flash=U59 --boot=$(shell $(QUARTUS_ROOTDIR)/sopc_builder/bin/find_sopc_component_dir $(CPU_CLASS) $(QUARTUS_PROJECT_DIR))/$(BOOT_COPIER_EPCS) --outfile=$(EPCS_CONTROLLER_BOOT_ROM_FLASHTARGET_ALT_SIM_PREFIX)epcs_controller_boot_rom.flash --sim_optimize=$(ALT_SIM_OPTIMIZE) --epcs --base=0x0 --end=0x7FFFFFFF  ; fi";
                  Dependency = "$(ELF)";
                  Target_File = "$(EPCS_CONTROLLER_BOOT_ROM_FLASHTARGET_ALT_SIM_PREFIX)epcs_controller_boot_rom.flash";
               }
            }
            TARGET programflash
            {
               epcs_controller 
               {
                  All_Depends_On = "0";
                  Command1 = "@if [ $(BOOTS_FROM_EPCS) -eq 1 ]; then nios2-flash-programmer --input=$(EPCS_CONTROLLER_BOOT_ROM_FLASHTARGET_ALT_SIM_PREFIX)epcs_controller_boot_rom.flash --sof=$(shell $(QUARTUS_ROOTDIR)/sopc_builder/bin/find_sopc_component_dir altera_nios_dev_board_cyclone_1c20 $(QUARTUS_PROJECT_DIR))/system/altera_nios_dev_board_cyclone_1c20.sof --device=1 $(JTAG_CABLE) --epcs  ; fi";
                  Dependency = "$(EPCS_CONTROLLER_BOOT_ROM_FLASHTARGET_ALT_SIM_PREFIX)epcs_controller_boot_rom.flash";
                  Is_Phony = "1";
                  Target_File = "epcs_controller_boot_rom_programflash";
               }
            }
            TARGET programflashnoelfdependency
            {
               epcs_controller 
               {
                  All_Depends_On = "0";
                  Command1 = "@if [ $(BOOTS_FROM_EPCS) -eq 1 ]; then nios2-flash-programmer --input=$(EPCS_CONTROLLER_BOOT_ROM_FLASHTARGET_ALT_SIM_PREFIX)epcs_controller_boot_rom.flash --sof=$(shell $(QUARTUS_ROOTDIR)/sopc_builder/bin/find_sopc_component_dir altera_nios_dev_board_cyclone_1c20 $(QUARTUS_PROJECT_DIR))/system/altera_nios_dev_board_cyclone_1c20.sof --device=1 $(JTAG_CABLE) --epcs  ; fi";
                  Is_Phony = "1";
                  Target_File = "epcs_controller_boot_rom_programflashnoelf";
               }
            }
            TARGET sim
            {
               epcs_controller 
               {
                  Command1 = "if [ ! -d $(SIMDIR) ]; then mkdir $(SIMDIR) ; fi";
                  Command2 = "@echo Hardware simulation is not enabled for the target SOPC Builder system. Skipping creation of hardware simulation model contents and simulation symbol files. \\(Note: This does not affect the instruction set simulator.\\)";
                  Command3 = "touch $(SIMDIR)/dummy_file";
                  Dependency = "$(ELF)";
                  Target_File = "$(SIMDIR)/dummy_file";
               }
            }
         }
         clockunit = "kHz";
         contents_info = "SIMDIR/epcs_controller_boot_rom.hex 1124853272 SIMDIR/epcs_controller_boot_rom.dat 1124853272 ";
         delayunit = "us";
      }
      HDL_INFO 
      {
         Precompiled_Simulation_Library_Files = "";
         Simulation_HDL_Files = "";
         Synthesis_HDL_Files = "__PROJECT_DIRECTORY__/epcs_controller.v";
         Synthesis_Only_Files = "";
      }
      PORT_WIRING 
      {
      }
   }
   MODULE lan91c111
   {
      class = "altera_avalon_lan91c111";
      class_version = "2.3";
      WIZARD_SCRIPT_ARGUMENTS 
      {
         Is_Ethernet_Mac = "1";
         CONSTANTS 
         {
            CONSTANT LAN91C111_REGISTERS_OFFSET
            {
               value = "0x0300";
               comment = "offset 0 or 0x300, depending on address bus wiring";
            }
            CONSTANT LAN91C111_DATA_BUS_WIDTH
            {
               value = "32";
               comment = "width 16 or 32, depending on data bus wiring";
            }
         }
      }
      SYSTEM_BUILDER_INFO 
      {
         Instantiate_In_System_Module = "0";
         Wire_Test_Bench_Values = "1";
         Is_Enabled = "1";
         Top_Level_Ports_Are_Enumerated = "1";
         View 
         {
            MESSAGES 
            {
            }
            Is_Collapsed = "1";
         }
         Clock_Source = "sysclk2";
      }
      SLAVE s1
      {
         SYSTEM_BUILDER_INFO 
         {
            Instantiate_In_System_Module = "0";
            Is_Enabled = "1";
            Is_Bus_Master = "0";
            Bus_Type = "avalon_tristate";
            Uses_Tri_State_Data_Bus = "1";
            Address_Alignment = "native";
            Address_Width = "14";
            Data_Width = "32";
            Has_IRQ = "1";
            Read_Wait_States = "175ns";
            Write_Wait_States = "175ns";
            Setup_Time = "10ns";
            Hold_Time = "5ns";
            Is_Memory_Device = "0";
            Date_Modified = "2002.03.19.10:51:51";
            Base_Address = "0x02110000";
            Tri_State_Data_Bus = "--unknown--";
            MASTERED_BY ext_ram_bus/tristate_master
            {
               priority = "1";
            }
            IRQ_MASTER cpu/data_master
            {
               IRQ_Number = "6";
            }
         }
         PORT_WIRING 
         {
            PORT irq
            {
               direction = "output";
               width = "1";
               type = "irq";
               test_bench_value = "0";
               originally_shared = "0";
               is_shared = "0";
               BOARD_COMPONENT altera_nios_dev_board_cyclone_1c20
               {
                  component_pin = "U4.29";
                  pin_assignment = "D15";
               }
            }
            PORT byteenablen
            {
               is_shared = "0";
               direction = "input";
               width = "4";
               type = "byteenable_n";
               originally_shared = "1";
               BOARD_COMPONENT altera_nios_dev_board_cyclone_1c20
               {
                  component_pin = "U4.94,U4.95,U4.96,U4.97";
                  pin_assignment = "C16,B16,D16,E16";
               }
            }
            PORT address
            {
               is_shared = "1";
               direction = "input";
               width = "14";
               type = "address";
               originally_shared = "1";
               lsb = "2";
               BOARD_COMPONENT altera_nios_dev_board_cyclone_1c20
               {
                  component_pin = "U4.79,U4.80,U4.81,U4.82,U4.83,U4.84,U4.85,U4.86,U4.87,U4.88,U4.89,U4.90,U4.91,U4.92";
                  pin_assignment = "D5,D6,C5,B5,C2,D2,D4,D1,E4,E5,F3,E3,E2,F4";
               }
            }
            PORT data
            {
               is_shared = "1";
               direction = "inout";
               width = "32";
               type = "data";
               originally_shared = "1";
               BOARD_COMPONENT altera_nios_dev_board_cyclone_1c20
               {
                  component_pin = "U4.107,U4.106,U4.105,U4.104,U4.102,U4.101,U4.100,U4.99,U4.76,U4.75,U4.74,U4.73,U4.71,U4.70,U4.69,U4.68,U4.66,U4.65,U4.64,U4.63,U4.61,U4.60,U4.59,U4.58,U4.56,U4.55,U4.54,U4.53,U4.51,U4.50,U4.49,U4.48";
                  pin_assignment = "C6,E6,B6,A6,F7,E7,B7,A7,D7,C7,F8,E8,B8,A8,D8,C8,B9,A9,D9,C9,E9,E10,B10,A10,F10,C10,D10,C11,D11,B11,A11,E11";
               }
            }
            PORT iow_n
            {
               direction = "input";
               width = "1";
               type = "write_n";
               originally_shared = "0";
               is_shared = "0";
               BOARD_COMPONENT altera_nios_dev_board_cyclone_1c20
               {
                  component_pin = "U4.32";
                  pin_assignment = "E15";
               }
            }
            PORT ior_n
            {
               direction = "input";
               width = "1";
               type = "read_n";
               originally_shared = "0";
               is_shared = "0";
               BOARD_COMPONENT altera_nios_dev_board_cyclone_1c20
               {
                  component_pin = "U4.31";
                  pin_assignment = "A15";
               }
            }
            PORT reset
            {
               direction = "input";
               width = "1";
               type = "reset";
               originally_shared = "0";
               is_shared = "0";
               BOARD_COMPONENT altera_nios_dev_board_cyclone_1c20
               {
                  component_pin = "use_quartus_pin_assignment";
                  pin_assignment = "";
               }
            }
            PORT reset_n
            {
               direction = "input";
               width = "1";
               type = "reset_n";
               Is_Enabled = "0";
            }
            PORT ardy
            {
               direction = "output";
               width = "1";
               type = "inhibitrequest_n";
               Is_Enabled = "0";
            }
         }
      }
   }
   MODULE sys_clk_timer
   {
      class = "altera_avalon_timer";
      class_version = "2.1";
      iss_model_name = "altera_avalon_timer";
      SLAVE s1
      {
         SYSTEM_BUILDER_INFO 
         {
            Bus_Type = "avalon";
            Is_Printable_Device = "0";
            Address_Alignment = "native";
            Address_Width = "3";
            Data_Width = "16";
            Has_IRQ = "1";
            Read_Wait_States = "1";
            Write_Wait_States = "0";
            MASTERED_BY cpu/data_master
            {
               priority = "1";
            }
            IRQ_MASTER cpu/data_master
            {
               IRQ_Number = "0";
            }
            Base_Address = "0x02120800";
         }
         PORT_WIRING 
         {
            PORT address
            {
               Is_Enabled = "1";
               direction = "input";
               type = "address";
               width = "3";
            }
            PORT chipselect
            {
               Is_Enabled = "1";
               direction = "input";
               type = "chipselect";
               width = "1";
            }
            PORT clk
            {
               Is_Enabled = "1";
               direction = "input";
               type = "clk";
               width = "1";
            }
            PORT irq
            {
               Is_Enabled = "1";
               direction = "output";
               type = "irq";
               width = "1";
            }
            PORT readdata
            {
               Is_Enabled = "1";
               direction = "output";
               type = "readdata";
               width = "16";
            }
            PORT reset_n
            {
               Is_Enabled = "1";
               direction = "input";
               type = "reset_n";
               width = "1";
            }
            PORT write_n
            {
               Is_Enabled = "1";
               direction = "input";
               type = "write_n";
               width = "1";
            }
            PORT writedata
            {
               Is_Enabled = "1";
               direction = "input";
               type = "writedata";
               width = "16";
            }
         }
      }
      SYSTEM_BUILDER_INFO 
      {
         Instantiate_In_System_Module = "1";
         Is_Enabled = "1";
         Top_Level_Ports_Are_Enumerated = "1";
         Clock_Source = "sysclk2";
         View 
         {
            Settings_Summary = "Timer with 10 ms timeout period.";
            MESSAGES 
            {
            }
            Is_Collapsed = "1";
         }
      }
      WIZARD_SCRIPT_ARGUMENTS 
      {
         always_run = "0";
         fixed_period = "0";
         snapshot = "1";
         period = "10";
         period_units = "ms";
         reset_output = "0";
         timeout_pulse_output = "0";
         mult = "0.001";
      }
      HDL_INFO 
      {
         Precompiled_Simulation_Library_Files = "";
         Simulation_HDL_Files = "";
         Synthesis_HDL_Files = "__PROJECT_DIRECTORY__/sys_clk_timer.v";
         Synthesis_Only_Files = "";
      }
      PORT_WIRING 
      {
      }
   }
   MODULE jtag_uart
   {
      class = "altera_avalon_jtag_uart";
      class_version = "1.0";
      iss_model_name = "altera_avalon_jtag_uart";
      SLAVE avalon_jtag_slave
      {
         SYSTEM_BUILDER_INFO 
         {
            Bus_Type = "avalon";
            Is_Printable_Device = "1";
            Address_Alignment = "native";
            Address_Width = "1";
            Data_Width = "32";
            Has_IRQ = "1";
            Read_Wait_States = "peripheral_controlled";
            Write_Wait_States = "peripheral_controlled";
            JTAG_Hub_Base_Id = "0x04006E";
            JTAG_Hub_Instance_Id = "0";
            Connection_Limit = "1";
            MASTERED_BY cpu/data_master
            {
               priority = "1";
            }
            IRQ_MASTER cpu/data_master
            {
               IRQ_Number = "1";
            }
            Base_Address = "0x021208B0";
         }
         PORT_WIRING 
         {
            PORT clk
            {
               type = "clk";
               direction = "input";
               width = "1";
               Is_Enabled = "1";
            }
            PORT rst_n
            {
               type = "reset_n";
               direction = "input";
               width = "1";
               Is_Enabled = "1";
            }
            PORT av_chipselect
            {
               type = "chipselect";
               direction = "input";
               width = "1";
               Is_Enabled = "1";
            }
            PORT av_address
            {
               type = "address";
               direction = "input";
               width = "1";
               Is_Enabled = "1";
            }
            PORT av_read_n
            {
               type = "read_n";
               direction = "input";
               width = "1";
               Is_Enabled = "1";
            }
            PORT av_readdata
            {
               type = "readdata";
               direction = "output";
               width = "32";
               Is_Enabled = "1";
            }
            PORT av_write_n
            {
               type = "write_n";
               direction = "input";
               width = "1";
               Is_Enabled = "1";
            }
            PORT av_writedata
            {
               type = "writedata";
               direction = "input";
               width = "32";
               Is_Enabled = "1";
            }
            PORT av_waitrequest
            {
               type = "waitrequest";
               direction = "output";
               width = "1";
               Is_Enabled = "1";
            }
            PORT av_irq
            {
               type = "irq";
               direction = "output";
               width = "1";
               Is_Enabled = "1";
            }
            PORT dataavailable
            {
               Is_Enabled = "1";
               direction = "output";
               type = "dataavailable";
               width = "1";
            }
            PORT readyfordata
            {
               Is_Enabled = "1";
               direction = "output";
               type = "readyfordata";
               width = "1";
            }
         }
      }
      SYSTEM_BUILDER_INFO 
      {
         Instantiate_In_System_Module = "1";
         Is_Enabled = "1";
         Iss_Launch_Telnet = "0";
         Top_Level_Ports_Are_Enumerated = "1";
         Clock_Source = "sysclk2";
         View 
         {
            Settings_Summary = "<br>Write Depth: 64; Write IRQ Threshold: 8
                <br>Read  Depth: 64; Read  IRQ Threshold: 8";
            MESSAGES 
            {
            }
            Is_Collapsed = "1";
         }
      }
      WIZARD_SCRIPT_ARGUMENTS 
      {
         write_depth = "64";
         read_depth = "64";
         write_threshold = "8";
         read_threshold = "8";
         read_char_stream = "";
         showascii = "1";
         read_le = "0";
         write_le = "0";
         altera_show_unreleased_jtag_uart_features = "0";
      }
      SIMULATION 
      {
         Fix_Me_Up = "";
         DISPLAY 
         {
            SIGNAL av_chipselect
            {
               name = "av_chipselect";
            }
            SIGNAL av_address
            {
               name = "av_address";
               radix = "hexadecimal";
            }
            SIGNAL av_read_n
            {
               name = "av_read_n";
            }
            SIGNAL av_readdata
            {
               name = "av_readdata";
               radix = "hexadecimal";
            }
            SIGNAL av_write_n
            {
               name = "av_write_n";
            }
            SIGNAL av_writedata
            {
               name = "av_writedata";
               radix = "hexadecimal";
            }
            SIGNAL av_waitrequest
            {
               name = "av_waitrequest";
            }
            SIGNAL av_irq
            {
               name = "av_irq";
            }
            SIGNAL dataavailable
            {
               name = "dataavailable";
            }
            SIGNAL readyfordata
            {
               name = "readyfordata";
            }
         }
         INTERACTIVE_IN drive
         {
            enable = "0";
            file = "_input_data_stream.dat";
            mutex = "_input_data_mutex.dat";
            log = "_in.log";
            rate = "100";
            signals = "temp,list";
            exe = "nios2-terminal";
         }
         INTERACTIVE_OUT log
         {
            enable = "1";
            exe = "perl -- atail-f.pl";
            file = "_output_stream.dat";
            radix = "ascii";
            signals = "temp,list";
         }
      }
      HDL_INFO 
      {
         Precompiled_Simulation_Library_Files = "";
         Simulation_HDL_Files = "";
         Synthesis_HDL_Files = "__PROJECT_DIRECTORY__/jtag_uart.v";
         Synthesis_Only_Files = "";
      }
      PORT_WIRING 
      {
      }
   }
   MODULE button_pio
   {
      class = "altera_avalon_pio";
      class_version = "2.2";
      HDL_INFO 
      {
         Precompiled_Simulation_Library_Files = "";
         Simulation_HDL_Files = "";
         Synthesis_HDL_Files = "__PROJECT_DIRECTORY__/button_pio.v";
         Synthesis_Only_Files = "";
      }
      PORT_WIRING 
      {
         PORT in_port
         {
            direction = "input";
            Is_Enabled = "1";
            width = "4";
            originally_shared = "0";
            is_shared = "0";
            BOARD_COMPONENT altera_nios_dev_board_cyclone_1c20
            {
               pin_assignment = "W3,Y4,V4,W4";
               component_pin = "SW0-SW3.SW0,SW0-SW3.SW1,SW0-SW3.SW2,SW0-SW3.SW3";
            }
            test_bench_value = "15";
         }
         PORT out_port
         {
            direction = "output";
            Is_Enabled = "0";
            width = "4";
         }
         PORT bidir_port
         {
            direction = "inout";
            Is_Enabled = "0";
            width = "4";
         }
      }
      SLAVE s1
      {
         PORT_WIRING 
         {
            PORT address
            {
               Is_Enabled = "1";
               direction = "input";
               type = "address";
               width = "2";
            }
            PORT chipselect
            {
               Is_Enabled = "1";
               direction = "input";
               type = "chipselect";
               width = "1";
            }
            PORT clk
            {
               Is_Enabled = "1";
               direction = "input";
               type = "clk";
               width = "1";
            }
            PORT irq
            {
               Is_Enabled = "1";
               direction = "output";
               type = "irq";
               width = "1";
            }
            PORT readdata
            {
               Is_Enabled = "1";
               direction = "output";
               type = "readdata";
               width = "4";
            }
            PORT reset_n
            {
               Is_Enabled = "1";
               direction = "input";
               type = "reset_n";
               width = "1";
            }
            PORT write_n
            {
               Is_Enabled = "1";
               direction = "input";
               type = "write_n";
               width = "1";
            }
            PORT writedata
            {
               Is_Enabled = "1";
               direction = "input";
               type = "writedata";
               width = "4";
            }
         }
         SYSTEM_BUILDER_INFO 
         {
            Bus_Type = "avalon";
            Has_IRQ = "1";
            Address_Width = "2";
            Data_Width = "4";
            Base_Address = "0x02120860";
            Address_Alignment = "native";
            Read_Wait_States = "1";
            Write_Wait_States = "0";
            MASTERED_BY cpu/data_master
            {
               priority = "1";
            }
            IRQ_MASTER cpu/data_master
            {
               IRQ_Number = "2";
            }
         }
      }
      SYSTEM_BUILDER_INFO 
      {
         Date_Modified = "";
         Is_Enabled = "1";
         Instantiate_In_System_Module = "1";
         Wire_Test_Bench_Values = "1";
         Top_Level_Ports_Are_Enumerated = "1";
         Clock_Source = "sysclk2";
         View 
         {
            Settings_Summary = " 4-bit PIO using <br>
					
					 input pins with edge type ANY and interrupt source EDGE
					";
            MESSAGES 
            {
            }
            Is_Collapsed = "1";
         }
      }
      WIZARD_SCRIPT_ARGUMENTS 
      {
         Do_Test_Bench_Wiring = "1";
         Driven_Sim_Value = "0x000F";
         has_tri = "0";
         has_out = "0";
         has_in = "1";
         capture = "1";
         edge_type = "ANY";
         irq_type = "EDGE";
      }
   }
   MODULE led_pio
   {
      class = "altera_avalon_pio";
      class_version = "2.2";
      HDL_INFO 
      {
         Precompiled_Simulation_Library_Files = "";
         Simulation_HDL_Files = "";
         Synthesis_HDL_Files = "__PROJECT_DIRECTORY__/led_pio.v";
         Synthesis_Only_Files = "";
      }
      PORT_WIRING 
      {
         PORT in_port
         {
            direction = "input";
            Is_Enabled = "0";
            width = "8";
         }
         PORT out_port
         {
            direction = "output";
            Is_Enabled = "1";
            width = "8";
            originally_shared = "0";
            is_shared = "0";
            BOARD_COMPONENT altera_nios_dev_board_cyclone_1c20
            {
               pin_assignment = "E14,E13,C14,D14,E12,F12,B3,B14";
               component_pin = "D0-D7.D0,D0-D7.D1,D0-D7.D2,D0-D7.D3,D0-D7.D4,D0-D7.D5,D0-D7.D6,D0-D7.D7";
            }
         }
         PORT bidir_port
         {
            direction = "inout";
            Is_Enabled = "0";
            width = "8";
         }
      }
      SLAVE s1
      {
         PORT_WIRING 
         {
            PORT address
            {
               Is_Enabled = "1";
               direction = "input";
               type = "address";
               width = "2";
            }
            PORT chipselect
            {
               Is_Enabled = "1";
               direction = "input";
               type = "chipselect";
               width = "1";
            }
            PORT clk
            {
               Is_Enabled = "1";
               direction = "input";
               type = "clk";
               width = "1";
            }
            PORT reset_n
            {
               Is_Enabled = "1";
               direction = "input";
               type = "reset_n";
               width = "1";
            }
            PORT write_n
            {
               Is_Enabled = "1";
               direction = "input";
               type = "write_n";
               width = "1";
            }
            PORT writedata
            {
               Is_Enabled = "1";
               direction = "input";
               type = "writedata";
               width = "8";
            }
         }
         SYSTEM_BUILDER_INFO 
         {
            Bus_Type = "avalon";
            Has_IRQ = "0";
            Address_Width = "2";
            Data_Width = "8";
            Base_Address = "0x02120870";
            Address_Alignment = "native";
            Read_Wait_States = "1";
            Write_Wait_States = "0";
            MASTERED_BY cpu/data_master
            {
               priority = "1";
            }
            IRQ_MASTER cpu/data_master
            {
               IRQ_Number = "NC";
            }
         }
      }
      SYSTEM_BUILDER_INFO 
      {
         Date_Modified = "";
         Is_Enabled = "1";
         Instantiate_In_System_Module = "1";
         Wire_Test_Bench_Values = "1";
         Top_Level_Ports_Are_Enumerated = "1";
         Clock_Source = "sysclk2";
         View 
         {
            Settings_Summary = " 8-bit PIO using <br>
					
					
					 output pins";
            MESSAGES 
            {
            }
            Is_Collapsed = "1";
         }
      }
      WIZARD_SCRIPT_ARGUMENTS 
      {
         Do_Test_Bench_Wiring = "0";
         Driven_Sim_Value = "0x0000";
         has_tri = "0";
         has_out = "1";
         has_in = "0";
         capture = "0";
         edge_type = "NONE";
         irq_type = "NONE";
      }
   }
   MODULE lcd_display
   {
      class = "altera_avalon_lcd_16207";
      class_version = "4.0";
      HDL_INFO 
      {
         Precompiled_Simulation_Library_Files = "";
         Simulation_HDL_Files = "";
         Synthesis_HDL_Files = "__PROJECT_DIRECTORY__/lcd_display.v";
         Synthesis_Only_Files = "";
      }
      PORT_WIRING 
      {
         PORT LCD_data
         {
            direction = "inout";
            width = "8";
            Is_Enabled = "1";
            originally_shared = "0";
            is_shared = "0";
            BOARD_COMPONENT altera_nios_dev_board_cyclone_1c20
            {
               component_pin = "J12.7,J12.8,J12.9,J12.10,J12.11,J12.12,J12.13,J12.14";
               pin_assignment = "H14,J14,J17,J18,K15,W18,V18,V19";
            }
         }
         PORT LCD_E
         {
            direction = "output";
            width = "1";
            Is_Enabled = "1";
            originally_shared = "0";
            is_shared = "0";
            BOARD_COMPONENT altera_nios_dev_board_cyclone_1c20
            {
               component_pin = "J12.6";
               pin_assignment = "J20";
            }
         }
         PORT LCD_RS
         {
            direction = "output";
            width = "1";
            Is_Enabled = "1";
            originally_shared = "0";
            is_shared = "0";
            BOARD_COMPONENT altera_nios_dev_board_cyclone_1c20
            {
               component_pin = "J12.4";
               pin_assignment = "J15";
            }
         }
         PORT LCD_RW
         {
            direction = "output";
            width = "1";
            Is_Enabled = "1";
            originally_shared = "0";
            is_shared = "0";
            BOARD_COMPONENT altera_nios_dev_board_cyclone_1c20
            {
               component_pin = "J12.5";
               pin_assignment = "J19";
            }
         }
      }
      SLAVE control_slave
      {
         PORT_WIRING 
         {
            PORT address
            {
               Is_Enabled = "1";
               direction = "input";
               type = "address";
               width = "2";
            }
            PORT begintransfer
            {
               Is_Enabled = "1";
               direction = "input";
               type = "begintransfer";
               width = "1";
            }
            PORT irq
            {
               Is_Enabled = "1";
               direction = "output";
               type = "irq";
               width = "1";
            }
            PORT read
            {
               Is_Enabled = "1";
               direction = "input";
               type = "read";
               width = "1";
            }
            PORT readdata
            {
               Is_Enabled = "1";
               direction = "output";
               type = "readdata";
               width = "8";
            }
            PORT write
            {
               Is_Enabled = "1";
               direction = "input";
               type = "write";
               width = "1";
            }
            PORT writedata
            {
               Is_Enabled = "1";
               direction = "input";
               type = "writedata";
               width = "8";
            }
         }
         SYSTEM_BUILDER_INFO 
         {
            Bus_Type = "avalon";
            Has_IRQ = "0";
            Is_Printable_Device = "1";
            Address_Width = "2";
            Data_Width = "8";
            Base_Address = "0x02120880";
            Address_Alignment = "native";
            Read_Wait_States = "250ns";
            Write_Wait_States = "250ns";
            Setup_Time = "250ns";
            Hold_Time = "250ns";
            Read_Latency = "0";
            MASTERED_BY cpu/data_master
            {
               priority = "1";
            }
            IRQ_MASTER cpu/data_master
            {
               IRQ_Number = "NC";
            }
         }
      }
      SYSTEM_BUILDER_INFO 
      {
         Date_Modified = "";
         Is_Enabled = "1";
         Instantiate_In_System_Module = "1";
         Top_Level_Ports_Are_Enumerated = "1";
         View 
         {
            Is_Collapsed = "1";
            MESSAGES 
            {
            }
         }
         Clock_Source = "sysclk2";
      }
      WIZARD_SCRIPT_ARGUMENTS 
      {
      }
   }
   MODULE high_res_timer
   {
      class = "altera_avalon_timer";
      class_version = "2.1";
      iss_model_name = "altera_avalon_timer";
      SLAVE s1
      {
         SYSTEM_BUILDER_INFO 
         {
            Bus_Type = "avalon";
            Is_Printable_Device = "0";
            Address_Alignment = "native";
            Address_Width = "3";
            Data_Width = "16";
            Has_IRQ = "1";
            Read_Wait_States = "1";
            Write_Wait_States = "0";
            MASTERED_BY cpu/data_master
            {
               priority = "1";
            }
            IRQ_MASTER cpu/data_master
            {
               IRQ_Number = "3";
            }
            Base_Address = "0x02120820";
         }
         PORT_WIRING 
         {
            PORT address
            {
               Is_Enabled = "1";
               direction = "input";
               type = "address";
               width = "3";
            }
            PORT chipselect
            {
               Is_Enabled = "1";
               direction = "input";
               type = "chipselect";
               width = "1";
            }
            PORT clk
            {
               Is_Enabled = "1";
               direction = "input";
               type = "clk";
               width = "1";
            }
            PORT irq
            {
               Is_Enabled = "1";
               direction = "output";
               type = "irq";
               width = "1";
            }
            PORT readdata
            {
               Is_Enabled = "1";
               direction = "output";
               type = "readdata";
               width = "16";
            }
            PORT reset_n
            {
               Is_Enabled = "1";
               direction = "input";
               type = "reset_n";
               width = "1";
            }
            PORT write_n
            {
               Is_Enabled = "1";
               direction = "input";
               type = "write_n";
               width = "1";
            }
            PORT writedata
            {
               Is_Enabled = "1";
               direction = "input";
               type = "writedata";
               width = "16";
            }
         }
      }
      SYSTEM_BUILDER_INFO 
      {
         Instantiate_In_System_Module = "1";
         Is_Enabled = "1";
         Top_Level_Ports_Are_Enumerated = "1";
         Clock_Source = "sysclk2";
         View 
         {
            Settings_Summary = "Timer with 1 ms timeout period.";
            MESSAGES 
            {
            }
            Is_Collapsed = "1";
         }
      }
      WIZARD_SCRIPT_ARGUMENTS 
      {
         always_run = "0";
         fixed_period = "0";
         snapshot = "1";
         period = "1";
         period_units = "ms";
         reset_output = "0";
         timeout_pulse_output = "0";
         mult = "0.001";
      }
      HDL_INFO 
      {
         Precompiled_Simulation_Library_Files = "";
         Simulation_HDL_Files = "";
         Synthesis_HDL_Files = "__PROJECT_DIRECTORY__/high_res_timer.v";
         Synthesis_Only_Files = "";
      }
      PORT_WIRING 
      {
      }
   }
   MODULE seven_seg_pio
   {
      class = "altera_avalon_pio";
      class_version = "2.2";
      HDL_INFO 
      {
         Precompiled_Simulation_Library_Files = "";
         Simulation_HDL_Files = "";
         Synthesis_HDL_Files = "__PROJECT_DIRECTORY__/seven_seg_pio.v";
         Synthesis_Only_Files = "";
      }
      PORT_WIRING 
      {
         PORT in_port
         {
            direction = "input";
            Is_Enabled = "0";
            width = "16";
         }
         PORT out_port
         {
            direction = "output";
            Is_Enabled = "1";
            width = "16";
            originally_shared = "0";
            is_shared = "0";
            BOARD_COMPONENT altera_nios_dev_board_cyclone_1c20
            {
               component_pin = "U8-U9.G0,U8-U9.F0,U8-U9.E0,U8-U9.D0,U8-U9.C0,U8-U9.B0,U8-U9.A0,U8-U9.DP0,U8-U9.G1,U8-U9.F1,U8-U9.E1,U8-U9.D1,U8-U9.C1,U8-U9.B1,U8-U9.A1,U8-U9.DP1";
               pin_assignment = "V7,T8,R7,Y7,W7,V6,U6,U7,W6,T7,T6,W5,V5,U5,T5,Y6";
            }
         }
         PORT bidir_port
         {
            direction = "inout";
            Is_Enabled = "0";
            width = "16";
         }
      }
      SLAVE s1
      {
         PORT_WIRING 
         {
            PORT address
            {
               Is_Enabled = "1";
               direction = "input";
               type = "address";
               width = "2";
            }
            PORT chipselect
            {
               Is_Enabled = "1";
               direction = "input";
               type = "chipselect";
               width = "1";
            }
            PORT clk
            {
               Is_Enabled = "1";
               direction = "input";
               type = "clk";
               width = "1";
            }
            PORT reset_n
            {
               Is_Enabled = "1";
               direction = "input";
               type = "reset_n";
               width = "1";
            }
            PORT write_n
            {
               Is_Enabled = "1";
               direction = "input";
               type = "write_n";
               width = "1";
            }
            PORT writedata
            {
               Is_Enabled = "1";
               direction = "input";
               type = "writedata";
               width = "16";
            }
         }
         SYSTEM_BUILDER_INFO 
         {
            Bus_Type = "avalon";
            Has_IRQ = "0";
            Address_Width = "2";
            Data_Width = "16";
            Base_Address = "0x02120890";
            Address_Alignment = "native";
            Read_Wait_States = "1";
            Write_Wait_States = "0";
            MASTERED_BY cpu/data_master
            {
               priority = "1";
            }
            IRQ_MASTER cpu/data_master
            {
               IRQ_Number = "NC";
            }
         }
      }
      SYSTEM_BUILDER_INFO 
      {
         Date_Modified = "";
         Is_Enabled = "1";
         Instantiate_In_System_Module = "1";
         Wire_Test_Bench_Values = "1";
         Top_Level_Ports_Are_Enumerated = "1";
         Clock_Source = "sysclk2";
         View 
         {
            Settings_Summary = " 16-bit PIO using <br>
					
					
					 output pins";
            MESSAGES 
            {
            }
            Is_Collapsed = "1";
         }
      }
      WIZARD_SCRIPT_ARGUMENTS 
      {
         Do_Test_Bench_Wiring = "0";
         Driven_Sim_Value = "0x0000";
         has_tri = "0";
         has_out = "1";
         has_in = "0";
         capture = "0";
         edge_type = "NONE";
         irq_type = "NONE";
      }
   }
   MODULE reconfig_request_pio
   {
      class = "altera_avalon_pio";
      class_version = "2.2";
      HDL_INFO 
      {
         Precompiled_Simulation_Library_Files = "";
         Simulation_HDL_Files = "";
         Synthesis_HDL_Files = "__PROJECT_DIRECTORY__/reconfig_request_pio.v";
         Synthesis_Only_Files = "";
      }
      PORT_WIRING 
      {
         PORT in_port
         {
            direction = "input";
            Is_Enabled = "0";
            width = "1";
         }
         PORT out_port
         {
            direction = "output";
            Is_Enabled = "0";
            width = "1";
         }
         PORT bidir_port
         {
            direction = "inout";
            Is_Enabled = "1";
            width = "1";
            originally_shared = "0";
            is_shared = "0";
            BOARD_COMPONENT altera_nios_dev_board_cyclone_1c20
            {
               component_pin = "U3.94";
               pin_assignment = "V8";
            }
         }
      }
      SLAVE s1
      {
         PORT_WIRING 
         {
            PORT address
            {
               Is_Enabled = "1";
               direction = "input";
               type = "address";
               width = "2";
            }
            PORT chipselect
            {
               Is_Enabled = "1";
               direction = "input";
               type = "chipselect";
               width = "1";
            }
            PORT clk
            {
               Is_Enabled = "1";
               direction = "input";
               type = "clk";
               width = "1";
            }
            PORT readdata
            {
               Is_Enabled = "1";
               direction = "output";
               type = "readdata";
               width = "1";
            }
            PORT reset_n
            {
               Is_Enabled = "1";
               direction = "input";
               type = "reset_n";
               width = "1";
            }
            PORT write_n
            {
               Is_Enabled = "1";
               direction = "input";
               type = "write_n";
               width = "1";
            }
            PORT writedata
            {
               Is_Enabled = "1";
               direction = "input";
               type = "writedata";
               width = "1";
            }
         }
         SYSTEM_BUILDER_INFO 
         {
            Bus_Type = "avalon";
            Has_IRQ = "0";
            Address_Width = "2";
            Data_Width = "1";
            Base_Address = "0x021208A0";
            Address_Alignment = "native";
            Read_Wait_States = "1";
            Write_Wait_States = "0";
            MASTERED_BY cpu/data_master
            {
               priority = "1";
            }
            IRQ_MASTER cpu/data_master
            {
               IRQ_Number = "NC";
            }
         }
      }
      SYSTEM_BUILDER_INFO 
      {
         Date_Modified = "";
         Is_Enabled = "1";
         Instantiate_In_System_Module = "1";
         Wire_Test_Bench_Values = "1";
         Top_Level_Ports_Are_Enumerated = "1";
         Clock_Source = "sysclk2";
         View 
         {
            Settings_Summary = " 1-bit PIO using <br>
					 tri-state pins with edge type NONE and interrupt source NONE
					
					";
            MESSAGES 
            {
            }
            Is_Collapsed = "1";
         }
      }
      WIZARD_SCRIPT_ARGUMENTS 
      {
         Do_Test_Bench_Wiring = "0";
         Driven_Sim_Value = "0x0000";
         has_tri = "1";
         has_out = "0";
         has_in = "0";
         capture = "0";
         edge_type = "NONE";
         irq_type = "NONE";
      }
   }
   MODULE uart1
   {
      class = "altera_avalon_uart";
      class_version = "4.2";
      iss_model_name = "altera_avalon_uart";
      PORT_WIRING 
      {
         PORT rxd
         {
            direction = "input";
            width = "1";
            Is_Enabled = "1";
            originally_shared = "0";
            is_shared = "0";
            BOARD_COMPONENT altera_nios_dev_board_cyclone_1c20
            {
               component_pin = "J19.3";
               pin_assignment = "K16";
            }
         }
         PORT txd
         {
            direction = "output";
            width = "1";
            Is_Enabled = "1";
            originally_shared = "0";
            is_shared = "0";
            BOARD_COMPONENT altera_nios_dev_board_cyclone_1c20
            {
               component_pin = "J19.2";
               pin_assignment = "M14";
            }
         }
         PORT cts_n
         {
            direction = "input";
            width = "1";
            Is_Enabled = "0";
         }
         PORT rts_n
         {
            direction = "output";
            width = "1";
            Is_Enabled = "0";
         }
      }
      SLAVE s1
      {
         SYSTEM_BUILDER_INFO 
         {
            Bus_Type = "avalon";
            Is_Printable_Device = "1";
            Address_Alignment = "native";
            Address_Width = "3";
            Data_Width = "16";
            Has_IRQ = "1";
            Read_Wait_States = "1";
            Write_Wait_States = "1";
            MASTERED_BY cpu/data_master
            {
               priority = "1";
            }
            IRQ_MASTER cpu/data_master
            {
               IRQ_Number = "4";
            }
            Base_Address = "0x02120840";
         }
         PORT_WIRING 
         {
            PORT address
            {
               Is_Enabled = "1";
               direction = "input";
               type = "address";
               width = "3";
            }
            PORT begintransfer
            {
               Is_Enabled = "1";
               direction = "input";
               type = "begintransfer";
               width = "1";
            }
            PORT chipselect
            {
               Is_Enabled = "1";
               direction = "input";
               type = "chipselect";
               width = "1";
            }
            PORT clk
            {
               Is_Enabled = "1";
               direction = "input";
               type = "clk";
               width = "1";
            }
            PORT dataavailable
            {
               Is_Enabled = "1";
               direction = "output";
               type = "dataavailable";
               width = "1";
            }
            PORT irq
            {
               Is_Enabled = "1";
               direction = "output";
               type = "irq";
               width = "1";
            }
            PORT read_n
            {
               Is_Enabled = "1";
               direction = "input";
               type = "read_n";
               width = "1";
            }
            PORT readdata
            {
               Is_Enabled = "1";
               direction = "output";
               type = "readdata";
               width = "16";
            }
            PORT readyfordata
            {
               Is_Enabled = "1";
               direction = "output";
               type = "readyfordata";
               width = "1";
            }
            PORT reset_n
            {
               Is_Enabled = "1";
               direction = "input";
               type = "reset_n";
               width = "1";
            }
            PORT write_n
            {
               Is_Enabled = "1";
               direction = "input";
               type = "write_n";
               width = "1";
            }
            PORT writedata
            {
               Is_Enabled = "1";
               direction = "input";
               type = "writedata";
               width = "16";
            }
         }
      }
      SYSTEM_BUILDER_INFO 
      {
         Instantiate_In_System_Module = "1";
         Is_Enabled = "1";
         Iss_Launch_Telnet = "0";
         Top_Level_Ports_Are_Enumerated = "1";
         Clock_Source = "sysclk2";
         View 
         {
            Settings_Summary = "8-bit UART with 115200 baud, <br>
                    1 stop bits and N parity";
            MESSAGES 
            {
            }
            Is_Collapsed = "1";
         }
      }
      SIMULATION 
      {
         DISPLAY 
         {
            SIGNAL a
            {
               name = "  Bus Interface";
               format = "Divider";
            }
            SIGNAL b
            {
               name = "chipselect";
            }
            SIGNAL c
            {
               name = "address";
               radix = "hexadecimal";
            }
            SIGNAL d
            {
               name = "writedata";
               radix = "hexadecimal";
            }
            SIGNAL e
            {
               name = "readdata";
               radix = "hexadecimal";
            }
            SIGNAL f
            {
               name = "  Internals";
               format = "Divider";
            }
            SIGNAL g
            {
               name = "tx_ready";
            }
            SIGNAL h
            {
               name = "tx_data";
               radix = "ascii";
            }
            SIGNAL i
            {
               name = "rx_char_ready";
            }
            SIGNAL j
            {
               name = "rx_data";
               radix = "ascii";
            }
         }
         INTERACTIVE_OUT log
         {
            enable = "0";
            file = "_log_module.txt";
            radix = "ascii";
            signals = "temp,list";
            exe = "perl -- tail-f.pl";
         }
         INTERACTIVE_IN drive
         {
            enable = "0";
            file = "_input_data_stream.dat";
            mutex = "_input_data_mutex.dat";
            log = "_in.log";
            rate = "100";
            signals = "temp,list";
            exe = "perl -- uart.pl";
         }
      }
      WIZARD_SCRIPT_ARGUMENTS 
      {
         baud = "115200";
         data_bits = "8";
         fixed_baud = "1";
         parity = "N";
         stop_bits = "1";
         use_cts_rts = "0";
         use_eop_register = "0";
         sim_true_baud = "0";
         sim_char_stream = "";
      }
      HDL_INFO 
      {
         Precompiled_Simulation_Library_Files = "";
         Simulation_HDL_Files = "";
         Synthesis_HDL_Files = "__PROJECT_DIRECTORY__/uart1.v";
         Synthesis_Only_Files = "";
      }
   }
   MODULE sysid
   {
      class = "altera_avalon_sysid";
      class_version = "4.0";
      HDL_INFO 
      {
         Precompiled_Simulation_Library_Files = "";
         Simulation_HDL_Files = "";
         Synthesis_HDL_Files = "__PROJECT_DIRECTORY__/sysid.v";
         Synthesis_Only_Files = "";
      }
      PORT_WIRING 
      {
      }
      SLAVE control_slave
      {
         PORT_WIRING 
         {
            PORT address
            {
               Is_Enabled = "1";
               direction = "input";
               type = "address";
               width = "1";
            }
            PORT readdata
            {
               Is_Enabled = "1";
               direction = "output";
               type = "readdata";
               width = "32";
            }
         }
         SYSTEM_BUILDER_INFO 
         {
            Bus_Type = "avalon";
            Has_IRQ = "0";
            Address_Width = "1";
            Data_Width = "32";
            Base_Address = "0x021208B8";
            Address_Alignment = "native";
            Read_Wait_States = "1";
            Write_Wait_States = "0";
            Read_Latency = "0";
            MASTERED_BY cpu/data_master
            {
               priority = "1";
            }
            IRQ_MASTER cpu/data_master
            {
               IRQ_Number = "NC";
            }
         }
      }
      SYSTEM_BUILDER_INFO 
      {
         Date_Modified = "";
         Is_Enabled = "1";
         Instantiate_In_System_Module = "1";
         Fixed_Module_Name = "sysid";
         Top_Level_Ports_Are_Enumerated = "1";
         View 
         {
            Settings_Summary = "System ID (at last Generate):<br> <b>6D0BC731</b>    (unique ID tag) <br> <b>431E7E82</b> (timestamp: Wed Sep 7, 2005 @1:45 PM)";
            Is_Collapsed = "1";
            MESSAGES 
            {
            }
         }
         Clock_Source = "sysclk2";
      }
      WIZARD_SCRIPT_ARGUMENTS 
      {
         id = "1829488433u";
         timestamp = "1126071938u";
         MAKE 
         {
            TARGET verifysysid
            {
               verifysysid 
               {
                  All_Depends_On = "0";
                  Command = "nios2-download $(JTAG_CABLE)                                --sidp=0x021208B8 --id=1829488433 --timestamp=1126071938";
                  Is_Phony = "1";
                  Target_File = "dummy_verifysysid_file";
               }
            }
         }
      }
   }
   MODULE sdram
   {
      class = "altera_avalon_new_sdram_controller";
      class_version = "4.2";
      iss_model_name = "altera_memory";
      SLAVE s1
      {
         SYSTEM_BUILDER_INFO 
         {
            Bus_Type = "avalon";
            Address_Alignment = "dynamic";
            Has_IRQ = "0";
            Maximum_Pending_Read_Transactions = "7";
            Read_Wait_States = "peripheral_controlled";
            Write_Wait_States = "peripheral_controlled";
            Is_Memory_Device = "1";
            Address_Width = "22";
            Data_Width = "32";
            Simulation_Num_Lanes = "1";
            MASTERED_BY cpu/instruction_master
            {
               priority = "8";
            }
            MASTERED_BY cpu/data_master
            {
               priority = "1";
            }
            Base_Address = "0x01000000";
            Is_Base_Locked = "1";
            IRQ_MASTER cpu/data_master
            {
               IRQ_Number = "NC";
            }
         }
         PORT_WIRING 
         {
            PORT zs_addr
            {
               direction = "output";
               width = "12";
               Is_Enabled = "1";
               originally_shared = "0";
               is_shared = "0";
               BOARD_COMPONENT altera_nios_dev_board_cyclone_1c20
               {
                  component_pin = "U57.25,U57.26,U57.27,U57.60,U57.61,U57.62,U57.63,U57.64,U57.65,U57.66,U57.24,U57.21";
                  pin_assignment = "M2,M1,M6,M4,J8,J7,J6,J5,J4,J3,H6,H5";
               }
            }
            PORT zs_ba
            {
               direction = "output";
               width = "2";
               Is_Enabled = "1";
               originally_shared = "0";
               is_shared = "0";
               BOARD_COMPONENT altera_nios_dev_board_cyclone_1c20
               {
                  component_pin = "U57.22,U57.23";
                  pin_assignment = "H7,H1";
               }
            }
            PORT zs_cas_n
            {
               direction = "output";
               width = "1";
               Is_Enabled = "1";
               originally_shared = "0";
               is_shared = "0";
               BOARD_COMPONENT altera_nios_dev_board_cyclone_1c20
               {
                  component_pin = "U57.18";
                  pin_assignment = "G3";
               }
            }
            PORT zs_cke
            {
               direction = "output";
               width = "1";
               Is_Enabled = "1";
               originally_shared = "0";
               is_shared = "0";
               BOARD_COMPONENT altera_nios_dev_board_cyclone_1c20
               {
                  component_pin = "U57.67";
                  pin_assignment = "G7";
               }
            }
            PORT zs_cs_n
            {
               direction = "output";
               width = "1";
               Is_Enabled = "1";
               originally_shared = "0";
               is_shared = "0";
               BOARD_COMPONENT altera_nios_dev_board_cyclone_1c20
               {
                  component_pin = "U57.20";
                  pin_assignment = "G6";
               }
            }
            PORT zs_dq
            {
               direction = "inout";
               width = "32";
               Is_Enabled = "1";
               originally_shared = "0";
               is_shared = "0";
               BOARD_COMPONENT altera_nios_dev_board_cyclone_1c20
               {
                  component_pin = "U57.2,U57.4,U57.5,U57.7,U57.8,U57.10,U57.11,U57.13,U57.74,U57.76,U57.77,U57.79,U57.80,U57.82,U57.83,U57.85,U57.31,U57.33,U57.34,U57.36,U57.37,U57.39,U57.40,U57.42,U57.45,U57.47,U57.48,U57.50,U57.51,U57.53,U57.54,U57.56";
                  pin_assignment = "M5,M3,M7,N6,N1,N2,N4,N3,N5,N7,P7,P2,P1,P6,P5,P3,P4,R1,R2,R6,R5,R3,R4,T4,T2,T3,U1,U4,U2,U3,V3,V2";
               }
            }
            PORT zs_dqm
            {
               direction = "output";
               width = "4";
               Is_Enabled = "1";
               originally_shared = "0";
               is_shared = "0";
               BOARD_COMPONENT altera_nios_dev_board_cyclone_1c20
               {
                  component_pin = "U57.16,U57.71,U57.28,U57.59";
                  pin_assignment = "J2,J1,H4,H3";
               }
            }
            PORT zs_ras_n
            {
               direction = "output";
               width = "1";
               Is_Enabled = "1";
               originally_shared = "0";
               is_shared = "0";
               BOARD_COMPONENT altera_nios_dev_board_cyclone_1c20
               {
                  component_pin = "U57.19";
                  pin_assignment = "H2";
               }
            }
            PORT zs_we_n
            {
               direction = "output";
               width = "1";
               Is_Enabled = "1";
               originally_shared = "0";
               is_shared = "0";
               BOARD_COMPONENT altera_nios_dev_board_cyclone_1c20
               {
                  component_pin = "U57.17";
                  pin_assignment = "G4";
               }
            }
            PORT az_addr
            {
               Is_Enabled = "1";
               direction = "input";
               type = "address";
               width = "22";
            }
            PORT az_be_n
            {
               Is_Enabled = "1";
               direction = "input";
               type = "byteenable_n";
               width = "4";
            }
            PORT az_cs
            {
               Is_Enabled = "1";
               direction = "input";
               type = "chipselect";
               width = "1";
            }
            PORT az_data
            {
               Is_Enabled = "1";
               direction = "input";
               type = "writedata";
               width = "32";
            }
            PORT az_rd_n
            {
               Is_Enabled = "1";
               direction = "input";
               type = "read_n";
               width = "1";
            }
            PORT az_wr_n
            {
               Is_Enabled = "1";
               direction = "input";
               type = "write_n";
               width = "1";
            }
            PORT clk
            {
               Is_Enabled = "1";
               direction = "input";
               type = "clk";
               width = "1";
            }
            PORT reset_n
            {
               Is_Enabled = "1";
               direction = "input";
               type = "reset_n";
               width = "1";
            }
            PORT za_data
            {
               Is_Enabled = "1";
               direction = "output";
               type = "readdata";
               width = "32";
            }
            PORT za_valid
            {
               Is_Enabled = "1";
               direction = "output";
               type = "readdatavalid";
               width = "1";
            }
            PORT za_waitrequest
            {
               Is_Enabled = "1";
               direction = "output";
               type = "waitrequest";
               width = "1";
            }
         }
      }
      SYSTEM_BUILDER_INFO 
      {
         Instantiate_In_System_Module = "1";
         Is_Enabled = "1";
         Default_Module_Name = "sdram";
         Disable_Simulation_Port_Wiring = "0";
         Top_Level_Ports_Are_Enumerated = "1";
         Clock_Source = "sysclk2";
         View 
         {
            Settings_Summary = "4194304 x 32<br>
                Memory size: 16 MBytes<br>
                128 MBits
                ";
            MESSAGES 
            {
            }
            Is_Collapsed = "1";
         }
      }
      WIZARD_SCRIPT_ARGUMENTS 
      {
         register_data_in = "1";
         sim_model_base = "1";
         sdram_data_width = "32";
         sdram_addr_width = "12";
         sdram_row_width = "12";
         sdram_col_width = "8";
         sdram_num_chipselects = "1";
         sdram_num_banks = "4";
         refresh_period = "15.625";
         powerup_delay = "100";
         cas_latency = "3";
         t_rfc = "70";
         t_rp = "20";
         t_mrd = "3";
         t_rcd = "20";
         t_ac = "5.5";
         t_wr = "14";
         init_refresh_commands = "2";
         init_nop_delay = "0";
         shared_data = "0";
         starvation_indicator = "0";
         tristate_bridge_slave = "";
         is_initialized = "1";
         sdram_bank_width = "2";
         MAKE 
         {
            TARGET delete_placeholder_warning
            {
               sdram 
               {
                  Command1 = "rm -f $(SIMDIR)/contents_file_warning.txt";
                  Is_Phony = "1";
                  Target_File = "do_delete_placeholder_warning";
               }
            }
            TARGET sim
            {
               sdram 
               {
                  Command1 = "if [ ! -d $(SIMDIR) ]; then mkdir $(SIMDIR) ; fi";
                  Command2 = "@echo Hardware simulation is not enabled for the target SOPC Builder system. Skipping creation of hardware simulation model contents and simulation symbol files. \\(Note: This does not affect the instruction set simulator.\\)";
                  Command3 = "touch $(SIMDIR)/dummy_file";
                  Dependency = "$(ELF)";
                  Target_File = "$(SIMDIR)/dummy_file";
               }
            }
         }
         contents_info = "SIMDIR/sdram.dat 1124853293 ";
      }
      SIMULATION 
      {
         Fix_Me_Up = "";
         DISPLAY 
         {
            SIGNAL a
            {
               name = "az_addr";
               radix = "hexadecimal";
            }
            SIGNAL b
            {
               name = "az_be_n";
               radix = "hexadecimal";
            }
            SIGNAL c
            {
               name = "az_cs";
            }
            SIGNAL d
            {
               name = "az_data";
               radix = "hexadecimal";
            }
            SIGNAL e
            {
               name = "az_rd_n";
            }
            SIGNAL f
            {
               name = "az_wr_n";
            }
            SIGNAL g
            {
               name = "clk";
            }
            SIGNAL h
            {
               name = "za_data";
               radix = "hexadecimal";
            }
            SIGNAL i
            {
               name = "za_valid";
            }
            SIGNAL j
            {
               name = "za_waitrequest";
            }
            SIGNAL k
            {
               name = "za_cannotrefresh";
               suppress = "1";
            }
            SIGNAL l
            {
               name = "CODE";
               radix = "ascii";
            }
            SIGNAL m
            {
               name = "zs_addr";
               radix = "hexadecimal";
               suppress = "0";
            }
            SIGNAL n
            {
               name = "zs_ba";
               radix = "hexadecimal";
               suppress = "0";
            }
            SIGNAL o
            {
               name = "zs_cs_n";
               radix = "hexadecimal";
               suppress = "0";
            }
            SIGNAL p
            {
               name = "zs_ras_n";
               suppress = "0";
            }
            SIGNAL q
            {
               name = "zs_cas_n";
               suppress = "0";
            }
            SIGNAL r
            {
               name = "zs_we_n";
               suppress = "0";
            }
            SIGNAL s
            {
               name = "zs_dq";
               radix = "hexadecimal";
               suppress = "0";
            }
            SIGNAL t
            {
               name = "zs_dqm";
               radix = "hexadecimal";
               suppress = "0";
            }
            SIGNAL u
            {
               name = "zt_addr";
               radix = "hexadecimal";
               suppress = "1";
            }
            SIGNAL v
            {
               name = "zt_ba";
               radix = "hexadecimal";
               suppress = "1";
            }
            SIGNAL w
            {
               name = "zt_oe";
               suppress = "1";
            }
            SIGNAL x
            {
               name = "zt_cke";
               suppress = "1";
            }
            SIGNAL y
            {
               name = "zt_chipselect";
               suppress = "1";
            }
            SIGNAL z0
            {
               name = "zt_lock_n";
               suppress = "1";
            }
            SIGNAL z1
            {
               name = "zt_ras_n";
               suppress = "1";
            }
            SIGNAL z2
            {
               name = "zt_cas_n";
               suppress = "1";
            }
            SIGNAL z3
            {
               name = "zt_we_n";
               suppress = "1";
            }
            SIGNAL z4
            {
               name = "zt_cs_n";
               radix = "hexadecimal";
               suppress = "1";
            }
            SIGNAL z5
            {
               name = "zt_dqm";
               radix = "hexadecimal";
               suppress = "1";
            }
            SIGNAL z6
            {
               name = "zt_data";
               radix = "hexadecimal";
               suppress = "1";
            }
            SIGNAL z7
            {
               name = "tz_data";
               radix = "hexadecimal";
               suppress = "1";
            }
            SIGNAL z8
            {
               name = "tz_waitrequest";
               suppress = "1";
            }
         }
         PORT_WIRING 
         {
            PORT clk
            {
               Is_Enabled = "1";
               direction = "input";
               width = "1";
            }
            PORT zs_addr
            {
               Is_Enabled = "1";
               direction = "input";
               width = "12";
            }
            PORT zs_ba
            {
               Is_Enabled = "1";
               direction = "input";
               width = "2";
            }
            PORT zs_cas_n
            {
               Is_Enabled = "1";
               direction = "input";
               width = "1";
            }
            PORT zs_cke
            {
               Is_Enabled = "1";
               direction = "input";
               width = "1";
            }
            PORT zs_cs_n
            {
               Is_Enabled = "1";
               direction = "input";
               width = "1";
            }
            PORT zs_dq
            {
               Is_Enabled = "1";
               direction = "inout";
               width = "32";
            }
            PORT zs_dqm
            {
               Is_Enabled = "1";
               direction = "input";
               width = "4";
            }
            PORT zs_ras_n
            {
               Is_Enabled = "1";
               direction = "input";
               width = "1";
            }
            PORT zs_we_n
            {
               Is_Enabled = "1";
               direction = "input";
               width = "1";
            }
         }
      }
      HDL_INFO 
      {
         Precompiled_Simulation_Library_Files = "";
         Simulation_HDL_Files = "";
         Synthesis_HDL_Files = "__PROJECT_DIRECTORY__/sdram.v, __PROJECT_DIRECTORY__/sdram_test_component.v";
         Synthesis_Only_Files = "";
      }
      PORT_WIRING 
      {
      }
   }
   MODULE sdram_pll
   {
      class = "altera_avalon_pll";
      class_version = "1.0";
      HDL_INFO 
      {
         Precompiled_Simulation_Library_Files = "";
         Simulation_HDL_Files = "";
         Synthesis_HDL_Files = "__PROJECT_DIRECTORY__/sdram_pll.v";
         Synthesis_Only_Files = "";
      }
      SYSTEM_BUILDER_INFO 
      {
         Is_Enabled = "1";
         Instantiate_In_System_Module = "1";
         Default_Module_Name = "pll";
         Clock_Source = "PLD_CLKFB";
         Required_Device_Family = "STRATIX,STRATIXGX,STRATIXII,STRATIXIIGX,CYCLONE,CYCLONEII";
         Top_Level_Ports_Are_Enumerated = "1";
         View 
         {
            Settings_Summary = " Avalon PLL: <br>
         input clock configured: <b>PLD_CLKFB</b>
        ";
            MESSAGES 
            {
            }
            Is_Collapsed = "1";
         }
      }
      SLAVE s1
      {
         SYSTEM_BUILDER_INFO 
         {
            Bus_Type = "avalon";
            Is_Printable_Device = "0";
            Address_Alignment = "native";
            Address_Width = "3";
            Data_Width = "16";
            Has_IRQ = "0";
            Read_Wait_States = "1";
            Write_Wait_States = "0";
            Date_Modified = "";
            Is_Enabled = "1";
            Instantiate_In_System_Module = "1";
            Requires_Internal_Clock_Promotion = "Yes";
            Is_Clock_Source = "1";
            Base_Address = "0x00800000";
            MASTERED_BY cpu/data_master
            {
               priority = "1";
               ADAPTER_MASTER clock_0/out
               {
                  priority = "1";
               }
            }
            IRQ_MASTER cpu/data_master
            {
               IRQ_Number = "NC";
            }
         }
         PORT_WIRING 
         {
            PORT address
            {
               direction = "input";
               type = "address";
               width = "3";
               Is_Enabled = "1";
            }
            PORT clk
            {
               direction = "input";
               type = "clk";
               width = "1";
               Is_Enabled = "1";
            }
            PORT reset_n
            {
               direction = "input";
               type = "reset_n";
               width = "1";
               Is_Enabled = "1";
            }
            PORT c0
            {
               Is_Enabled = "1";
               direction = "output";
               type = "out_clk";
               width = "1";
            }
            PORT e0
            {
               Is_Enabled = "1";
               direction = "output";
               type = "out_clk";
               width = "1";
            }
            PORT chipselect
            {
               Is_Enabled = "1";
               direction = "input";
               type = "chipselect";
               width = "1";
            }
            PORT read
            {
               Is_Enabled = "1";
               direction = "input";
               type = "read";
               width = "1";
            }
            PORT readdata
            {
               Is_Enabled = "1";
               direction = "output";
               type = "readdata";
               width = "16";
            }
            PORT resetrequest
            {
               Is_Enabled = "1";
               direction = "output";
               type = "resetrequest";
               width = "1";
            }
            PORT write
            {
               Is_Enabled = "1";
               direction = "input";
               type = "write";
               width = "1";
            }
            PORT writedata
            {
               Is_Enabled = "1";
               direction = "input";
               type = "writedata";
               width = "16";
            }
         }
      }
      WIZARD_SCRIPT_ARGUMENTS 
      {
         locked = "None";
         areset = "None";
         pllena = "None";
         pfdena = "None";
         Config_Done = "1";
         UI_CONTROL 
         {
            areset_port_exist = "0";
            pllena_port_exist = "0";
            pfdena_port_exist = "0";
            locked_port_exist = "0";
         }
         ALTPLL_PORTS 
         {
            PORT c0
            {
               Is_Enabled = "1";
               direction = "output";
               type = "out_clk";
               width = "1";
            }
            PORT e0
            {
               Is_Enabled = "1";
               direction = "output";
               type = "out_clk";
               width = "1";
            }
            PORT inclk0
            {
               Is_Enabled = "1";
               direction = "input";
               type = "in_clk";
               width = "1";
            }
         }
         CLOCK_INFO 
         {
            CLOCK inclk0
            {
               clock_freq = "50000000";
               clock_unit = "MHz";
               type = "in_clk";
            }
            NUMBER_OF_INPUT_CLOCKS = "1";
            NUMBER_OF_OUTPUT_CLOCKS = "2";
            RECONFIG_ENABLED = "0";
            USED_OUTPUT_CLOCKS 
            {
               INDEX_0 = "0";
               INDEX_6 = "6";
            }
         }
         CLOCK_SOURCES 
         {
            CLOCK c0
            {
               DIVIDE_BY = "1";
               DUTY_CYCLE = "50";
               MULTIPLY_BY = "1";
               PHASE_SHIFT = "0";
               clk_index = "0";
               clock_freq = "50000000";
               clock_unit = "MHz";
               type = "out_clk";
            }
            CLOCK e0
            {
               DIVIDE_BY = "1";
               DUTY_CYCLE = "50";
               MULTIPLY_BY = "1";
               PHASE_SHIFT = "-3500";
               clk_index = "6";
               clock_freq = "50000000";
               clock_unit = "MHz";
               type = "out_clk";
            }
         }
         CNX_INFO 
         {
            CONSTANT 
            {
               NUMERIC 
               {
                  CLK0_DIVIDE_BY = "1";
                  CLK0_DUTY_CYCLE = "50";
                  CLK0_MULTIPLY_BY = "1";
                  EXTCLK0_DIVIDE_BY = "1";
                  EXTCLK0_DUTY_CYCLE = "50";
                  EXTCLK0_MULTIPLY_BY = "1";
                  INCLK0_INPUT_FREQUENCY = "20000";
               }
               STRING 
               {
                  CLK0_PHASE_SHIFT = "0";
                  COMPENSATE_CLOCK = "CLK0";
                  EXTCLK0_PHASE_SHIFT = "-3500";
                  INTENDED_DEVICE_FAMILY = "Cyclone";
                  LPM_TYPE = "altpll";
                  OPERATION_MODE = "NORMAL";
                  PLL_TYPE = "AUTO";
               }
            }
            GEN_FILE 
            {
               TYPE_NORMAL 
               {
                  FALSE 
                  {
                     name1 = ".inc";
                     name2 = ".cmp";
                     name3 = ".bsf";
                     name4 = "_inst.v";
                     name5 = "_bb.v";
                     name6 = "_waveforms.html";
                     name7 = "_wave*.jpg";
                  }
                  TRUE 
                  {
                     name0 = ".v";
                  }
               }
            }
            LIBRARY = "altera_mf altera_mf.altera_mf_components.all";
            PRIVATE 
            {
               NUMERIC 
               {
                  DEVICE_FAMILY = "11";
                  DIV_FACTOR0 = "1";
                  DIV_FACTOR6 = "1";
                  GLOCK_COUNTER_EDIT = "1048575";
                  LVDS_MODE_DATA_RATE_DIRTY = "0";
                  MULT_FACTOR0 = "1";
                  MULT_FACTOR6 = "1";
                  PLL_AUTOPLL_CHECK = "1";
                  PLL_ENHPLL_CHECK = "0";
                  PLL_FASTPLL_CHECK = "0";
                  PLL_LVDS_PLL_CHECK = "0";
                  SWITCHOVER_COUNT_EDIT = "1";
               }
               STRING 
               {
                  ACTIVECLK_CHECK = "0";
                  BANDWIDTH = "1.000";
                  BANDWIDTH_FEATURE_ENABLED = "0";
                  BANDWIDTH_FREQ_UNIT = "MHz";
                  BANDWIDTH_PRESET = "Low";
                  BANDWIDTH_USE_AUTO = "1";
                  BANDWIDTH_USE_CUSTOM = "0";
                  BANDWIDTH_USE_PRESET = "0";
                  CLKBAD_SWITCHOVER_CHECK = "0";
                  CLKLOSS_CHECK = "0";
                  CLKSWITCH_CHECK = "0";
                  CNX_NO_COMPENSATE_RADIO = "0";
                  CREATE_CLKBAD_CHECK = "0";
                  CREATE_INCLK1_CHECK = "0";
                  CUR_DEDICATED_CLK = "c0";
                  CUR_FBIN_CLK = "e0";
                  DEVICE_SPEED_GRADE = "Any";
                  DEV_FAMILY = "Cyclone";
                  DUTY_CYCLE0 = "50.00000000";
                  DUTY_CYCLE6 = "50.00000000";
                  EXT_FEEDBACK_RADIO = "0";
                  GLOCKED_COUNTER_EDIT_CHANGED = "1";
                  GLOCKED_FEATURE_ENABLED = "0";
                  GLOCKED_MODE_CHECK = "0";
                  HAS_MANUAL_SWITCHOVER = "1";
                  INCLK0_FREQ_EDIT = "50.000";
                  INCLK0_FREQ_UNIT_COMBO = "MHz";
                  INCLK1_FREQ_EDIT = "100.000";
                  INCLK1_FREQ_EDIT_CHANGED = "1";
                  INCLK1_FREQ_UNIT_CHANGED = "1";
                  INCLK1_FREQ_UNIT_COMBO = "MHz";
                  INT_FEEDBACK__MODE_RADIO = "1";
                  LOCKED_OUTPUT_CHECK = "0";
                  LOCK_LOSS_SWITCHOVER_CHECK = "0";
                  LONG_SCAN_RADIO = "1";
                  LVDS_MODE_DATA_RATE = "500.000";
                  LVDS_PHASE_SHIFT_UNIT0 = "deg";
                  LVDS_PHASE_SHIFT_UNIT6 = "ps";
                  MIRROR_CLK0 = "0";
                  MIRROR_CLK6 = "0";
                  NORMAL_MODE_RADIO = "1";
                  OUTPUT_FREQ0 = "100.000";
                  OUTPUT_FREQ6 = "100.000";
                  OUTPUT_FREQ_MODE0 = "0";
                  OUTPUT_FREQ_MODE6 = "0";
                  OUTPUT_FREQ_UNIT0 = "MHz";
                  OUTPUT_FREQ_UNIT6 = "MHz";
                  PHASE_SHIFT0 = "0.00000000";
                  PHASE_SHIFT6 = "0.00000000";
                  PHASE_SHIFT_UNIT0 = "deg";
                  PHASE_SHIFT_UNIT6 = "ps";
                  PLL_ADVANCED_PARAM_CHECK = "0";
                  PLL_ARESET_CHECK = "0";
                  PLL_ENA_CHECK = "0";
                  PLL_PFDENA_CHECK = "0";
                  PRIMARY_CLK_COMBO = "inclk0";
                  SACN_INPUTS_CHECK = "0";
                  SCAN_FEATURE_ENABLED = "0";
                  SHORT_SCAN_RADIO = "0";
                  SPREAD_FEATURE_ENABLED = "0";
                  SPREAD_FREQ = "50.000";
                  SPREAD_FREQ_UNIT = "KHz";
                  SPREAD_PERCENT = "0.500";
                  SPREAD_USE = "0";
                  SRC_SYNCH_COMP_RADIO = "0";
                  STICKY_CLK0 = "1";
                  STICKY_CLK6 = "0";
                  SWITCHOVER_FEATURE_ENABLED = "0";
                  USE_CLK0 = "1";
                  USE_CLK6 = "0";
                  USE_CLKENA0 = "0";
                  USE_CLKENA6 = "0";
                  ZERO_DELAY_RADIO = "0";
               }
            }
            USED_PORT 
            {
               c0 
               {
                  VALUE_0 = "0";
                  VALUE_1 = "0";
                  VALUE_2 = "0";
                  VALUE_3 = "0";
                  VALUE_4 = "OUTPUT";
                  VALUE_5 = "VCC";
               }
               e0 
               {
                  VALUE_0 = "0";
                  VALUE_1 = "0";
                  VALUE_2 = "0";
                  VALUE_3 = "0";
                  VALUE_4 = "OUTPUT";
                  VALUE_5 = "VCC";
               }
            }
         }
      }
      PORT_WIRING 
      {
      }
   }
   MODULE connector_pll
   {
      class = "altera_avalon_pll";
      class_version = "1.0";
      HDL_INFO 
      {
         Precompiled_Simulation_Library_Files = "";
         Simulation_HDL_Files = "";
         Synthesis_HDL_Files = "__PROJECT_DIRECTORY__/connector_pll.v";
         Synthesis_Only_Files = "";
      }
      SYSTEM_BUILDER_INFO 
      {
         Is_Enabled = "1";
         Instantiate_In_System_Module = "1";
         Default_Module_Name = "pll";
         Clock_Source = "PLD_CLOCKINPUT";
         Required_Device_Family = "STRATIX,STRATIXGX,STRATIXII,STRATIXIIGX,CYCLONE,CYCLONEII";
         Top_Level_Ports_Are_Enumerated = "1";
         View 
         {
            Settings_Summary = " Avalon PLL: <br>
         input clock configured: <b>PLD_CLOCKINPUT</b>
        ";
            MESSAGES 
            {
            }
            Is_Collapsed = "1";
         }
      }
      SLAVE s1
      {
         SYSTEM_BUILDER_INFO 
         {
            Bus_Type = "avalon";
            Is_Printable_Device = "0";
            Address_Alignment = "native";
            Address_Width = "3";
            Data_Width = "16";
            Has_IRQ = "0";
            Read_Wait_States = "1";
            Write_Wait_States = "0";
            Date_Modified = "";
            Is_Enabled = "1";
            Instantiate_In_System_Module = "1";
            Requires_Internal_Clock_Promotion = "Yes";
            Is_Clock_Source = "1";
            Base_Address = "0x00800020";
            MASTERED_BY cpu/data_master
            {
               priority = "1";
               ADAPTER_MASTER clock_1/out
               {
                  priority = "1";
               }
            }
            IRQ_MASTER cpu/data_master
            {
               IRQ_Number = "NC";
            }
         }
         PORT_WIRING 
         {
            PORT address
            {
               direction = "input";
               type = "address";
               width = "3";
               Is_Enabled = "1";
            }
            PORT clk
            {
               direction = "input";
               type = "clk";
               width = "1";
               Is_Enabled = "1";
            }
            PORT reset_n
            {
               direction = "input";
               type = "reset_n";
               width = "1";
               Is_Enabled = "1";
            }
            PORT c0
            {
               Is_Enabled = "1";
               direction = "output";
               type = "out_clk";
               width = "1";
            }
            PORT e0
            {
               Is_Enabled = "1";
               direction = "output";
               type = "out_clk";
               width = "1";
            }
            PORT chipselect
            {
               Is_Enabled = "1";
               direction = "input";
               type = "chipselect";
               width = "1";
            }
            PORT read
            {
               Is_Enabled = "1";
               direction = "input";
               type = "read";
               width = "1";
            }
            PORT readdata
            {
               Is_Enabled = "1";
               direction = "output";
               type = "readdata";
               width = "16";
            }
            PORT resetrequest
            {
               Is_Enabled = "1";
               direction = "output";
               type = "resetrequest";
               width = "1";
            }
            PORT write
            {
               Is_Enabled = "1";
               direction = "input";
               type = "write";
               width = "1";
            }
            PORT writedata
            {
               Is_Enabled = "1";
               direction = "input";
               type = "writedata";
               width = "16";
            }
         }
      }
      WIZARD_SCRIPT_ARGUMENTS 
      {
         locked = "None";
         areset = "None";
         pllena = "None";
         pfdena = "None";
         Config_Done = "1";
         UI_CONTROL 
         {
            areset_port_exist = "0";
            pllena_port_exist = "0";
            pfdena_port_exist = "0";
            locked_port_exist = "0";
         }
         ALTPLL_PORTS 
         {
            PORT c0
            {
               Is_Enabled = "1";
               direction = "output";
               type = "out_clk";
               width = "1";
            }
            PORT e0
            {
               Is_Enabled = "1";
               direction = "output";
               type = "out_clk";
               width = "1";
            }
            PORT inclk0
            {
               Is_Enabled = "1";
               direction = "input";
               type = "in_clk";
               width = "1";
            }
         }
         CLOCK_INFO 
         {
            CLOCK inclk0
            {
               clock_freq = "50000000";
               clock_unit = "MHz";
               type = "in_clk";
            }
            NUMBER_OF_INPUT_CLOCKS = "1";
            NUMBER_OF_OUTPUT_CLOCKS = "2";
            RECONFIG_ENABLED = "0";
            USED_OUTPUT_CLOCKS 
            {
               INDEX_0 = "0";
               INDEX_6 = "6";
            }
         }
         CLOCK_SOURCES 
         {
            CLOCK c0
            {
               DIVIDE_BY = "5";
               DUTY_CYCLE = "50";
               MULTIPLY_BY = "9";
               PHASE_SHIFT = "0";
               clk_index = "0";
               clock_freq = "90000000";
               clock_unit = "MHz";
               type = "out_clk";
            }
            CLOCK e0
            {
               DIVIDE_BY = "1";
               DUTY_CYCLE = "50";
               MULTIPLY_BY = "1";
               PHASE_SHIFT = "0";
               clk_index = "6";
               clock_freq = "50000000";
               clock_unit = "MHz";
               type = "out_clk";
            }
         }
         CNX_INFO 
         {
            CONSTANT 
            {
               NUMERIC 
               {
                  CLK0_DIVIDE_BY = "5";
                  CLK0_DUTY_CYCLE = "50";
                  CLK0_MULTIPLY_BY = "9";
                  EXTCLK0_DIVIDE_BY = "1";
                  EXTCLK0_DUTY_CYCLE = "50";
                  EXTCLK0_MULTIPLY_BY = "1";
                  INCLK0_INPUT_FREQUENCY = "20000";
               }
               STRING 
               {
                  CLK0_PHASE_SHIFT = "0";
                  COMPENSATE_CLOCK = "CLK0";
                  EXTCLK0_PHASE_SHIFT = "0";
                  INTENDED_DEVICE_FAMILY = "Cyclone";
                  LPM_TYPE = "altpll";
                  OPERATION_MODE = "NORMAL";
                  PLL_TYPE = "AUTO";
               }
            }
            GEN_FILE 
            {
               TYPE_NORMAL 
               {
                  FALSE 
                  {
                     name1 = ".inc";
                     name2 = ".cmp";
                     name3 = ".bsf";
                     name4 = "_inst.v";
                     name5 = "_bb.v";
                     name6 = "_waveforms.html";
                     name7 = "_wave*.jpg";
                  }
                  TRUE 
                  {
                     name0 = ".v";
                  }
               }
            }
            LIBRARY = "altera_mf altera_mf.altera_mf_components.all";
            PRIVATE 
            {
               NUMERIC 
               {
                  DEVICE_FAMILY = "11";
                  DIV_FACTOR0 = "5";
                  DIV_FACTOR6 = "1";
                  GLOCK_COUNTER_EDIT = "1048575";
                  LVDS_MODE_DATA_RATE_DIRTY = "0";
                  MULT_FACTOR0 = "9";
                  MULT_FACTOR6 = "1";
                  PLL_AUTOPLL_CHECK = "1";
                  PLL_ENHPLL_CHECK = "0";
                  PLL_FASTPLL_CHECK = "0";
                  PLL_LVDS_PLL_CHECK = "0";
                  SWITCHOVER_COUNT_EDIT = "1";
               }
               STRING 
               {
                  ACTIVECLK_CHECK = "0";
                  BANDWIDTH = "1.000";
                  BANDWIDTH_FEATURE_ENABLED = "0";
                  BANDWIDTH_FREQ_UNIT = "MHz";
                  BANDWIDTH_PRESET = "Low";
                  BANDWIDTH_USE_AUTO = "1";
                  BANDWIDTH_USE_CUSTOM = "0";
                  BANDWIDTH_USE_PRESET = "0";
                  CLKBAD_SWITCHOVER_CHECK = "0";
                  CLKLOSS_CHECK = "0";
                  CLKSWITCH_CHECK = "0";
                  CNX_NO_COMPENSATE_RADIO = "0";
                  CREATE_CLKBAD_CHECK = "0";
                  CREATE_INCLK1_CHECK = "0";
                  CUR_DEDICATED_CLK = "c0";
                  CUR_FBIN_CLK = "e0";
                  DEVICE_SPEED_GRADE = "Any";
                  DEV_FAMILY = "Cyclone";
                  DUTY_CYCLE0 = "50.00000000";
                  DUTY_CYCLE6 = "50.00000000";
                  EXT_FEEDBACK_RADIO = "0";
                  GLOCKED_COUNTER_EDIT_CHANGED = "1";
                  GLOCKED_FEATURE_ENABLED = "0";
                  GLOCKED_MODE_CHECK = "0";
                  HAS_MANUAL_SWITCHOVER = "1";
                  INCLK0_FREQ_EDIT = "50.000";
                  INCLK0_FREQ_UNIT_COMBO = "MHz";
                  INCLK1_FREQ_EDIT = "100.000";
                  INCLK1_FREQ_EDIT_CHANGED = "1";
                  INCLK1_FREQ_UNIT_CHANGED = "1";
                  INCLK1_FREQ_UNIT_COMBO = "MHz";
                  INT_FEEDBACK__MODE_RADIO = "1";
                  LOCKED_OUTPUT_CHECK = "0";
                  LOCK_LOSS_SWITCHOVER_CHECK = "0";
                  LONG_SCAN_RADIO = "1";
                  LVDS_MODE_DATA_RATE = "500.000";
                  LVDS_PHASE_SHIFT_UNIT0 = "deg";
                  LVDS_PHASE_SHIFT_UNIT6 = "ps";
                  MIRROR_CLK0 = "0";
                  MIRROR_CLK6 = "0";
                  NORMAL_MODE_RADIO = "1";
                  OUTPUT_FREQ0 = "100.000";
                  OUTPUT_FREQ6 = "100.000";
                  OUTPUT_FREQ_MODE0 = "0";
                  OUTPUT_FREQ_MODE6 = "0";
                  OUTPUT_FREQ_UNIT0 = "MHz";
                  OUTPUT_FREQ_UNIT6 = "MHz";
                  PHASE_SHIFT0 = "0.00000000";
                  PHASE_SHIFT6 = "0.00000000";
                  PHASE_SHIFT_UNIT0 = "deg";
                  PHASE_SHIFT_UNIT6 = "ps";
                  PLL_ADVANCED_PARAM_CHECK = "0";
                  PLL_ARESET_CHECK = "0";
                  PLL_ENA_CHECK = "0";
                  PLL_PFDENA_CHECK = "0";
                  PRIMARY_CLK_COMBO = "inclk0";
                  SACN_INPUTS_CHECK = "0";
                  SCAN_FEATURE_ENABLED = "0";
                  SHORT_SCAN_RADIO = "0";
                  SPREAD_FEATURE_ENABLED = "0";
                  SPREAD_FREQ = "50.000";
                  SPREAD_FREQ_UNIT = "KHz";
                  SPREAD_PERCENT = "0.500";
                  SPREAD_USE = "0";
                  SRC_SYNCH_COMP_RADIO = "0";
                  STICKY_CLK0 = "1";
                  STICKY_CLK6 = "0";
                  SWITCHOVER_FEATURE_ENABLED = "0";
                  USE_CLK0 = "1";
                  USE_CLK6 = "0";
                  USE_CLKENA0 = "0";
                  USE_CLKENA6 = "0";
                  ZERO_DELAY_RADIO = "0";
               }
            }
            USED_PORT 
            {
               c0 
               {
                  VALUE_0 = "0";
                  VALUE_1 = "0";
                  VALUE_2 = "0";
                  VALUE_3 = "0";
                  VALUE_4 = "OUTPUT";
                  VALUE_5 = "VCC";
               }
               e0 
               {
                  VALUE_0 = "0";
                  VALUE_1 = "0";
                  VALUE_2 = "0";
                  VALUE_3 = "0";
                  VALUE_4 = "OUTPUT";
                  VALUE_5 = "VCC";
               }
            }
         }
      }
      PORT_WIRING 
      {
      }
   }
   MODULE clock_0
   {
      class = "altera_avalon_clock_adapter";
      class_version = "1.0";
      SYSTEM_BUILDER_INFO 
      {
         Is_Adapter = "1";
         Rank_Order = "100";
         Has_Clock = "0";
         Is_Enabled = "1";
         Instantiate_In_System_Module = "1";
         Maximum_Pending_Read_Transactions_Multiplicand = "0";
         View 
         {
            Settings_Summary = "<i>altera_avalon_clock_adapter</i> is crossing 50.0MHz to 50.0MHz.";
            MESSAGES 
            {
            }
         }
      }
      SLAVE in
      {
         SYSTEM_BUILDER_INFO 
         {
            Bus_Type = "avalon";
            Clock_Source = "sysclk2";
            Has_IRQ = "0";
            Read_Wait_States = "peripheral_controlled";
            Write_Wait_States = "peripheral_controlled";
            MASTERED_BY cpu/data_master
            {
               priority = "1";
            }
            Address_Alignment = "native";
            Base_Address = "0x00800000";
            Address_Width = "4";
            Data_Width = "16";
            Maximum_Pending_Read_Transactions = "0";
         }
      }
      MASTER out
      {
         SYSTEM_BUILDER_INFO 
         {
            Bus_Type = "avalon";
            Clock_Source = "PLD_CLKFB";
            Address_Width = "4";
            Data_Width = "32";
            Is_Readable = "1";
            Maximum_Burst_Size = "1";
         }
      }
      WIZARD_SCRIPT_ARGUMENTS 
      {
         asp_debug = "0";
      }
   }
   MODULE clock_1
   {
      class = "altera_avalon_clock_adapter";
      class_version = "1.0";
      SYSTEM_BUILDER_INFO 
      {
         Is_Adapter = "1";
         Rank_Order = "100";
         Has_Clock = "0";
         Is_Enabled = "1";
         Instantiate_In_System_Module = "1";
         Maximum_Pending_Read_Transactions_Multiplicand = "0";
         View 
         {
            Settings_Summary = "<i>altera_avalon_clock_adapter</i> is crossing 50.0MHz to 50.0MHz.";
            MESSAGES 
            {
            }
         }
      }
      SLAVE in
      {
         SYSTEM_BUILDER_INFO 
         {
            Bus_Type = "avalon";
            Clock_Source = "sysclk2";
            Has_IRQ = "0";
            Read_Wait_States = "peripheral_controlled";
            Write_Wait_States = "peripheral_controlled";
            MASTERED_BY cpu/data_master
            {
               priority = "1";
            }
            Address_Alignment = "native";
            Base_Address = "0x00800020";
            Address_Width = "4";
            Data_Width = "16";
            Maximum_Pending_Read_Transactions = "0";
         }
      }
      MASTER out
      {
         SYSTEM_BUILDER_INFO 
         {
            Bus_Type = "avalon";
            Clock_Source = "PLD_CLOCKINPUT";
            Address_Width = "4";
            Data_Width = "32";
            Is_Readable = "1";
            Maximum_Burst_Size = "1";
         }
      }
      WIZARD_SCRIPT_ARGUMENTS 
      {
         asp_debug = "0";
      }
   }
}
