# Fitter report for standard

### Fri Apr 21 03:23:35 2006
Version 6.0 Build 176 04/19/2006 SJ Full Version

## Table of Contents

Top

1. Legal Notice
2. Fitter Summary
3. Fitter Settings
4. Fitter Netlist Optimizations
5. Fitter Equations
6. Pin-Out File
7. Fitter Resource Usage Summary
8. Input Pins
9. Output Pins
10. Bidir Pins
11. I/O Bank Usage
12. All Package Pins
13. PLL Summary
14. PLL Usage
15. Output Pin Default Load For Reported TCO
16. Fitter Resource Utilization by Entity
17. Delay Chain Summary
18. Pad To Core Delay Chain Fanout
19. Control Signals
20. Global & Other Fast Signals
21. Non-Global High Fan-Out Signals
22. Fitter RAM Summary
23. Interconnect Usage Summary
24. LAB Logic Elements
25. LAB-wide Signals
26. LAB Signals Sourced
27. LAB Signals Sourced Out
28. LAB Distinct Inputs
29. Fitter Device Options
30. Fitter Messages
31. Fitter Suppressed Messages

## Legal Notice

Top

    Copyright (C) 1991-2006 Altera Corporation
    Your use of Altera Corporation's design tools, logic functions
    and other software and tools, and its AMPP partner logic
    functions, and any output files any of the foregoing
    (including device programming or simulation files), and any
    associated documentation or information are expressly subject
    to the terms and conditions of the Altera Program License
    Subscription Agreement, Altera MegaCore Function License
    Agreement, or other applicable license agreement, including,
    without limitation, that your use is for the sole purpose of
    programming logic devices manufactured by Altera and sold by
    Altera or its authorized distributors.  Please refer to the
    applicable agreement for further details.

## Fitter Summary

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Fitter Status | Successful - Fri Apr 21 03:23:35 2006
Quartus II Version | 6.0 Build 176 04/19/2006 SJ Full Version
Revision Name | standard
Top-level Entity Name | standard
Family | Cyclone
Device | EP1C20F400C7
Timing Models | Final
Total logic elements | 4,930 / 20,060 ( 25 % )
Total pins | 180 / 301 ( 60 % )
Total virtual pins | 0
Total memory bits | 50,944 / 294,912 ( 17 % )
Total PLLs | 2 / 2 ( 100 % )

## Fitter Settings

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Option | Setting | Default Value
--- | --- | ---
Device | EP1C20F400C7 |
Perform Physical Synthesis for Combinational Logic | On | Off
Perform Register Duplication | On | Off
Perform Register Retiming | On | Off
Fitter Effort | Standard Fit | Auto Fit
Use smart compilation | Off | Off
Router Timing Optimization Level | Normal | Normal
Placement Effort Multiplier | 1.0 | 1.0
Router Effort Multiplier | 1.0 | 1.0
Optimize Hold Timing | IO Paths and Minimum TPD Paths | IO Paths and Minimum TPD Paths
Optimize Fast-Corner Timing | Off | Off
Optimize Timing | Normal compilation | Normal compilation
Optimize IOC Register Placement for Timing | On | On
Limit to One Fitting Attempt | Off | Off
Final Placement Optimizations | Automatically | Automatically
Fitter Aggressive Routability Optimizations | Automatically | Automatically
Fitter Initial Placement Seed | 1 | 1
Slow Slew Rate | Off | Off
PCI I/O | Off | Off
Weak Pull-Up Resistor | Off | Off
Enable Bus-Hold Circuitry | Off | Off
Auto Global Memory Control Signals | Off | Off
Auto Packed Registers -- Cyclone | Auto | Auto
Auto Delay Chains | On | On
Auto Merge PLLs | On | On
Perform Asynchronous Signal Pipelining | Off | Off
Physical Synthesis Effort Level | Normal | Normal
Logic Cell Insertion - Logic Duplication | Auto | Auto
Auto Register Duplication | Auto | Auto
Auto Global Clock | On | On
Auto Global Register Control Signals | On | On

## Fitter Netlist Optimizations

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Node | Action | Operation | Reason | Node Port | Destination Node | Destination Port
--- | --- | --- | --- | --- | --- | ---
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|be_n_to_the_ext_ram[0] | Packed Register | Register Packing | Fast Output Register assignment | REGOUT | be_n_to_the_ext_ram[0] | DATAIN
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|be_n_to_the_ext_ram[1] | Packed Register | Register Packing | Fast Output Register assignment | REGOUT | be_n_to_the_ext_ram[1] | DATAIN
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|be_n_to_the_ext_ram[2] | Packed Register | Register Packing | Fast Output Register assignment | REGOUT | be_n_to_the_ext_ram[2] | DATAIN
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|be_n_to_the_ext_ram[3] | Packed Register | Register Packing | Fast Output Register assignment | REGOUT | be_n_to_the_ext_ram[3] | DATAIN
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|byteenablen_to_the_lan91c111[0] | Packed Register | Register Packing | Fast Output Register assignment | REGOUT | byteenablen_to_the_lan91c111[0] | DATAIN
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|byteenablen_to_the_lan91c111[1] | Packed Register | Register Packing | Fast Output Register assignment | REGOUT | byteenablen_to_the_lan91c111[1] | DATAIN
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|byteenablen_to_the_lan91c111[2] | Packed Register | Register Packing | Fast Output Register assignment | REGOUT | byteenablen_to_the_lan91c111[2] | DATAIN
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|byteenablen_to_the_lan91c111[3] | Packed Register | Register Packing | Fast Output Register assignment | REGOUT | byteenablen_to_the_lan91c111[3] | DATAIN
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_in_a_write_cycle | Packed Register | Register Packing | Fast Output Enable Register assignment | REGOUT | ext_ram_bus_data[0] | OE
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_in_a_write_cycle | Duplicated | Register Packing | Fast Output Enable Register assignment | REGOUT | std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_in_a_write_cycle~_Duplicate_1 | REGOUT
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_in_a_write_cycle~_Duplicate_1 | Packed Register | Register Packing | Fast Output Enable Register assignment | REGOUT | ext_ram_bus_data[1] | OE
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_in_a_write_cycle~_Duplicate_1 | Duplicated | Register Packing | Fast Output Enable Register assignment | REGOUT | std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_in_a_write_cycle~_Duplicate_2 | REGOUT
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_in_a_write_cycle~_Duplicate_2 | Packed Register | Register Packing | Fast Output Enable Register assignment | REGOUT | ext_ram_bus_data[2] | OE
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_in_a_write_cycle~_Duplicate_2 | Duplicated | Register Packing | Fast Output Enable Register assignment | REGOUT | std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_in_a_write_cycle~_Duplicate_3 | REGOUT
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_in_a_write_cycle~_Duplicate_3 | Packed Register | Register Packing | Fast Output Enable Register assignment | REGOUT | ext_ram_bus_data[3] | OE
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_in_a_write_cycle~_Duplicate_3 | Duplicated | Register Packing | Fast Output Enable Register assignment | REGOUT | std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_in_a_write_cycle~_Duplicate_4 | REGOUT
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_in_a_write_cycle~_Duplicate_4 | Packed Register | Register Packing | Fast Output Enable Register assignment | REGOUT | ext_ram_bus_data[4] | OE
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_in_a_write_cycle~_Duplicate_4 | Duplicated | Register Packing | Fast Output Enable Register assignment | REGOUT | std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_in_a_write_cycle~_Duplicate_5 | REGOUT
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_in_a_write_cycle~_Duplicate_5 | Packed Register | Register Packing | Fast Output Enable Register assignment | REGOUT | ext_ram_bus_data[5] | OE
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_in_a_write_cycle~_Duplicate_5 | Duplicated | Register Packing | Fast Output Enable Register assignment | REGOUT | std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_in_a_write_cycle~_Duplicate_6 | REGOUT
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_in_a_write_cycle~_Duplicate_6 | Packed Register | Register Packing | Fast Output Enable Register assignment | REGOUT | ext_ram_bus_data[6] | OE
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_in_a_write_cycle~_Duplicate_6 | Duplicated | Register Packing | Fast Output Enable Register assignment | REGOUT | std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_in_a_write_cycle~_Duplicate_7 | REGOUT
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_in_a_write_cycle~_Duplicate_7 | Packed Register | Register Packing | Fast Output Enable Register assignment | REGOUT | ext_ram_bus_data[7] | OE
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_in_a_write_cycle~_Duplicate_7 | Duplicated | Register Packing | Fast Output Enable Register assignment | REGOUT | std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_in_a_write_cycle~_Duplicate_8 | REGOUT
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_in_a_write_cycle~_Duplicate_8 | Packed Register | Register Packing | Fast Output Enable Register assignment | REGOUT | ext_ram_bus_data[8] | OE
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_in_a_write_cycle~_Duplicate_8 | Duplicated | Register Packing | Fast Output Enable Register assignment | REGOUT | std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_in_a_write_cycle~_Duplicate_9 | REGOUT
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_in_a_write_cycle~_Duplicate_9 | Packed Register | Register Packing | Fast Output Enable Register assignment | REGOUT | ext_ram_bus_data[9] | OE
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_in_a_write_cycle~_Duplicate_9 | Duplicated | Register Packing | Fast Output Enable Register assignment | REGOUT | std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_in_a_write_cycle~_Duplicate_10 | REGOUT
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_in_a_write_cycle~_Duplicate_10 | Packed Register | Register Packing | Fast Output Enable Register assignment | REGOUT | ext_ram_bus_data[10] | OE
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_in_a_write_cycle~_Duplicate_10 | Duplicated | Register Packing | Fast Output Enable Register assignment | REGOUT | std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_in_a_write_cycle~_Duplicate_11 | REGOUT
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_in_a_write_cycle~_Duplicate_11 | Packed Register | Register Packing | Fast Output Enable Register assignment | REGOUT | ext_ram_bus_data[11] | OE
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_in_a_write_cycle~_Duplicate_11 | Duplicated | Register Packing | Fast Output Enable Register assignment | REGOUT | std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_in_a_write_cycle~_Duplicate_12 | REGOUT
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_in_a_write_cycle~_Duplicate_12 | Packed Register | Register Packing | Fast Output Enable Register assignment | REGOUT | ext_ram_bus_data[12] | OE
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_in_a_write_cycle~_Duplicate_12 | Duplicated | Register Packing | Fast Output Enable Register assignment | REGOUT | std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_in_a_write_cycle~_Duplicate_13 | REGOUT
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_in_a_write_cycle~_Duplicate_13 | Packed Register | Register Packing | Fast Output Enable Register assignment | REGOUT | ext_ram_bus_data[13] | OE
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_in_a_write_cycle~_Duplicate_13 | Duplicated | Register Packing | Fast Output Enable Register assignment | REGOUT | std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_in_a_write_cycle~_Duplicate_14 | REGOUT
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_in_a_write_cycle~_Duplicate_14 | Packed Register | Register Packing | Fast Output Enable Register assignment | REGOUT | ext_ram_bus_data[14] | OE
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_in_a_write_cycle~_Duplicate_14 | Duplicated | Register Packing | Fast Output Enable Register assignment | REGOUT | std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_in_a_write_cycle~_Duplicate_15 | REGOUT
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_in_a_write_cycle~_Duplicate_15 | Packed Register | Register Packing | Fast Output Enable Register assignment | REGOUT | ext_ram_bus_data[15] | OE
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_in_a_write_cycle~_Duplicate_15 | Duplicated | Register Packing | Fast Output Enable Register assignment | REGOUT | std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_in_a_write_cycle~_Duplicate_16 | REGOUT
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_in_a_write_cycle~_Duplicate_16 | Packed Register | Register Packing | Fast Output Enable Register assignment | REGOUT | ext_ram_bus_data[16] | OE
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_in_a_write_cycle~_Duplicate_16 | Duplicated | Register Packing | Fast Output Enable Register assignment | REGOUT | std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_in_a_write_cycle~_Duplicate_17 | REGOUT
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_in_a_write_cycle~_Duplicate_17 | Packed Register | Register Packing | Fast Output Enable Register assignment | REGOUT | ext_ram_bus_data[17] | OE
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_in_a_write_cycle~_Duplicate_17 | Duplicated | Register Packing | Fast Output Enable Register assignment | REGOUT | std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_in_a_write_cycle~_Duplicate_18 | REGOUT
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_in_a_write_cycle~_Duplicate_18 | Packed Register | Register Packing | Fast Output Enable Register assignment | REGOUT | ext_ram_bus_data[18] | OE
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_in_a_write_cycle~_Duplicate_18 | Duplicated | Register Packing | Fast Output Enable Register assignment | REGOUT | std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_in_a_write_cycle~_Duplicate_19 | REGOUT
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_in_a_write_cycle~_Duplicate_19 | Packed Register | Register Packing | Fast Output Enable Register assignment | REGOUT | ext_ram_bus_data[19] | OE
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_in_a_write_cycle~_Duplicate_19 | Duplicated | Register Packing | Fast Output Enable Register assignment | REGOUT | std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_in_a_write_cycle~_Duplicate_20 | REGOUT
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_in_a_write_cycle~_Duplicate_20 | Packed Register | Register Packing | Fast Output Enable Register assignment | REGOUT | ext_ram_bus_data[20] | OE
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_in_a_write_cycle~_Duplicate_20 | Duplicated | Register Packing | Fast Output Enable Register assignment | REGOUT | std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_in_a_write_cycle~_Duplicate_21 | REGOUT
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_in_a_write_cycle~_Duplicate_21 | Packed Register | Register Packing | Fast Output Enable Register assignment | REGOUT | ext_ram_bus_data[21] | OE
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_in_a_write_cycle~_Duplicate_21 | Duplicated | Register Packing | Fast Output Enable Register assignment | REGOUT | std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_in_a_write_cycle~_Duplicate_22 | REGOUT
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_in_a_write_cycle~_Duplicate_22 | Packed Register | Register Packing | Fast Output Enable Register assignment | REGOUT | ext_ram_bus_data[22] | OE
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_in_a_write_cycle~_Duplicate_22 | Duplicated | Register Packing | Fast Output Enable Register assignment | REGOUT | std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_in_a_write_cycle~_Duplicate_23 | REGOUT
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_in_a_write_cycle~_Duplicate_23 | Packed Register | Register Packing | Fast Output Enable Register assignment | REGOUT | ext_ram_bus_data[23] | OE
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_in_a_write_cycle~_Duplicate_23 | Duplicated | Register Packing | Fast Output Enable Register assignment | REGOUT | std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_in_a_write_cycle~_Duplicate_24 | REGOUT
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_in_a_write_cycle~_Duplicate_24 | Packed Register | Register Packing | Fast Output Enable Register assignment | REGOUT | ext_ram_bus_data[24] | OE
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_in_a_write_cycle~_Duplicate_24 | Duplicated | Register Packing | Fast Output Enable Register assignment | REGOUT | std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_in_a_write_cycle~_Duplicate_25 | REGOUT
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_in_a_write_cycle~_Duplicate_25 | Packed Register | Register Packing | Fast Output Enable Register assignment | REGOUT | ext_ram_bus_data[25] | OE
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_in_a_write_cycle~_Duplicate_25 | Duplicated | Register Packing | Fast Output Enable Register assignment | REGOUT | std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_in_a_write_cycle~_Duplicate_26 | REGOUT
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_in_a_write_cycle~_Duplicate_26 | Packed Register | Register Packing | Fast Output Enable Register assignment | REGOUT | ext_ram_bus_data[26] | OE
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_in_a_write_cycle~_Duplicate_26 | Duplicated | Register Packing | Fast Output Enable Register assignment | REGOUT | std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_in_a_write_cycle~_Duplicate_27 | REGOUT
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_in_a_write_cycle~_Duplicate_27 | Packed Register | Register Packing | Fast Output Enable Register assignment | REGOUT | ext_ram_bus_data[27] | OE
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_in_a_write_cycle~_Duplicate_27 | Duplicated | Register Packing | Fast Output Enable Register assignment | REGOUT | std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_in_a_write_cycle~_Duplicate_28 | REGOUT
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_in_a_write_cycle~_Duplicate_28 | Packed Register | Register Packing | Fast Output Enable Register assignment | REGOUT | ext_ram_bus_data[28] | OE
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_in_a_write_cycle~_Duplicate_28 | Duplicated | Register Packing | Fast Output Enable Register assignment | REGOUT | std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_in_a_write_cycle~_Duplicate_29 | REGOUT
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_in_a_write_cycle~_Duplicate_29 | Packed Register | Register Packing | Fast Output Enable Register assignment | REGOUT | ext_ram_bus_data[29] | OE
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_in_a_write_cycle~_Duplicate_29 | Duplicated | Register Packing | Fast Output Enable Register assignment | REGOUT | std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_in_a_write_cycle~_Duplicate_30 | REGOUT
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_in_a_write_cycle~_Duplicate_30 | Packed Register | Register Packing | Fast Output Enable Register assignment | REGOUT | ext_ram_bus_data[30] | OE
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_in_a_write_cycle~_Duplicate_30 | Duplicated | Register Packing | Fast Output Enable Register assignment | REGOUT | std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_in_a_write_cycle~_Duplicate_31 | REGOUT
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_in_a_write_cycle~_Duplicate_31 | Packed Register | Register Packing | Fast Output Enable Register assignment | REGOUT | ext_ram_bus_data[31] | OE
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_outgoing_ext_ram_bus_data[0] | Packed Register | Register Packing | Fast Output Register assignment | REGOUT | ext_ram_bus_data[0] | DATAIN
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_outgoing_ext_ram_bus_data[1] | Packed Register | Register Packing | Fast Output Register assignment | REGOUT | ext_ram_bus_data[1] | DATAIN
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_outgoing_ext_ram_bus_data[2] | Packed Register | Register Packing | Fast Output Register assignment | REGOUT | ext_ram_bus_data[2] | DATAIN
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_outgoing_ext_ram_bus_data[3] | Packed Register | Register Packing | Fast Output Register assignment | REGOUT | ext_ram_bus_data[3] | DATAIN
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_outgoing_ext_ram_bus_data[4] | Packed Register | Register Packing | Fast Output Register assignment | REGOUT | ext_ram_bus_data[4] | DATAIN
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_outgoing_ext_ram_bus_data[5] | Packed Register | Register Packing | Fast Output Register assignment | REGOUT | ext_ram_bus_data[5] | DATAIN
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_outgoing_ext_ram_bus_data[6] | Packed Register | Register Packing | Fast Output Register assignment | REGOUT | ext_ram_bus_data[6] | DATAIN
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_outgoing_ext_ram_bus_data[7] | Packed Register | Register Packing | Fast Output Register assignment | REGOUT | ext_ram_bus_data[7] | DATAIN
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_outgoing_ext_ram_bus_data[8] | Packed Register | Register Packing | Fast Output Register assignment | REGOUT | ext_ram_bus_data[8] | DATAIN
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_outgoing_ext_ram_bus_data[9] | Packed Register | Register Packing | Fast Output Register assignment | REGOUT | ext_ram_bus_data[9] | DATAIN
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_outgoing_ext_ram_bus_data[10] | Packed Register | Register Packing | Fast Output Register assignment | REGOUT | ext_ram_bus_data[10] | DATAIN
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_outgoing_ext_ram_bus_data[11] | Packed Register | Register Packing | Fast Output Register assignment | REGOUT | ext_ram_bus_data[11] | DATAIN
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_outgoing_ext_ram_bus_data[12] | Packed Register | Register Packing | Fast Output Register assignment | REGOUT | ext_ram_bus_data[12] | DATAIN
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_outgoing_ext_ram_bus_data[13] | Packed Register | Register Packing | Fast Output Register assignment | REGOUT | ext_ram_bus_data[13] | DATAIN
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_outgoing_ext_ram_bus_data[14] | Packed Register | Register Packing | Fast Output Register assignment | REGOUT | ext_ram_bus_data[14] | DATAIN
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_outgoing_ext_ram_bus_data[15] | Packed Register | Register Packing | Fast Output Register assignment | REGOUT | ext_ram_bus_data[15] | DATAIN
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_outgoing_ext_ram_bus_data[16] | Packed Register | Register Packing | Fast Output Register assignment | REGOUT | ext_ram_bus_data[16] | DATAIN
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_outgoing_ext_ram_bus_data[17] | Packed Register | Register Packing | Fast Output Register assignment | REGOUT | ext_ram_bus_data[17] | DATAIN
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_outgoing_ext_ram_bus_data[18] | Packed Register | Register Packing | Fast Output Register assignment | REGOUT | ext_ram_bus_data[18] | DATAIN
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_outgoing_ext_ram_bus_data[19] | Packed Register | Register Packing | Fast Output Register assignment | REGOUT | ext_ram_bus_data[19] | DATAIN
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_outgoing_ext_ram_bus_data[20] | Packed Register | Register Packing | Fast Output Register assignment | REGOUT | ext_ram_bus_data[20] | DATAIN
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_outgoing_ext_ram_bus_data[21] | Packed Register | Register Packing | Fast Output Register assignment | REGOUT | ext_ram_bus_data[21] | DATAIN
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_outgoing_ext_ram_bus_data[22] | Packed Register | Register Packing | Fast Output Register assignment | REGOUT | ext_ram_bus_data[22] | DATAIN
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_outgoing_ext_ram_bus_data[23] | Packed Register | Register Packing | Fast Output Register assignment | REGOUT | ext_ram_bus_data[23] | DATAIN
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_outgoing_ext_ram_bus_data[24] | Packed Register | Register Packing | Fast Output Register assignment | REGOUT | ext_ram_bus_data[24] | DATAIN
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_outgoing_ext_ram_bus_data[25] | Packed Register | Register Packing | Fast Output Register assignment | REGOUT | ext_ram_bus_data[25] | DATAIN
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_outgoing_ext_ram_bus_data[26] | Packed Register | Register Packing | Fast Output Register assignment | REGOUT | ext_ram_bus_data[26] | DATAIN
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_outgoing_ext_ram_bus_data[27] | Packed Register | Register Packing | Fast Output Register assignment | REGOUT | ext_ram_bus_data[27] | DATAIN
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_outgoing_ext_ram_bus_data[28] | Packed Register | Register Packing | Fast Output Register assignment | REGOUT | ext_ram_bus_data[28] | DATAIN
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_outgoing_ext_ram_bus_data[29] | Packed Register | Register Packing | Fast Output Register assignment | REGOUT | ext_ram_bus_data[29] | DATAIN
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_outgoing_ext_ram_bus_data[30] | Packed Register | Register Packing | Fast Output Register assignment | REGOUT | ext_ram_bus_data[30] | DATAIN
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_outgoing_ext_ram_bus_data[31] | Packed Register | Register Packing | Fast Output Register assignment | REGOUT | ext_ram_bus_data[31] | DATAIN
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_address[0] | Packed Register | Register Packing | Fast Output Register assignment | REGOUT | ext_ram_bus_address[0] | DATAIN
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_address[1] | Packed Register | Register Packing | Fast Output Register assignment | REGOUT | ext_ram_bus_address[1] | DATAIN
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_address[2] | Packed Register | Register Packing | Fast Output Register assignment | REGOUT | ext_ram_bus_address[2] | DATAIN
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_address[3] | Packed Register | Register Packing | Fast Output Register assignment | REGOUT | ext_ram_bus_address[3] | DATAIN
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_address[4] | Packed Register | Register Packing | Fast Output Register assignment | REGOUT | ext_ram_bus_address[4] | DATAIN
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_address[5] | Packed Register | Register Packing | Fast Output Register assignment | REGOUT | ext_ram_bus_address[5] | DATAIN
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_address[6] | Packed Register | Register Packing | Fast Output Register assignment | REGOUT | ext_ram_bus_address[6] | DATAIN
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_address[7] | Packed Register | Register Packing | Fast Output Register assignment | REGOUT | ext_ram_bus_address[7] | DATAIN
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_address[8] | Packed Register | Register Packing | Fast Output Register assignment | REGOUT | ext_ram_bus_address[8] | DATAIN
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_address[9] | Packed Register | Register Packing | Fast Output Register assignment | REGOUT | ext_ram_bus_address[9] | DATAIN
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_address[10] | Packed Register | Register Packing | Fast Output Register assignment | REGOUT | ext_ram_bus_address[10] | DATAIN
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_address[11] | Packed Register | Register Packing | Fast Output Register assignment | REGOUT | ext_ram_bus_address[11] | DATAIN
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_address[12] | Packed Register | Register Packing | Fast Output Register assignment | REGOUT | ext_ram_bus_address[12] | DATAIN
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_address[13] | Packed Register | Register Packing | Fast Output Register assignment | REGOUT | ext_ram_bus_address[13] | DATAIN
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_address[14] | Packed Register | Register Packing | Fast Output Register assignment | REGOUT | ext_ram_bus_address[14] | DATAIN
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_address[15] | Packed Register | Register Packing | Fast Output Register assignment | REGOUT | ext_ram_bus_address[15] | DATAIN
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_address[16] | Packed Register | Register Packing | Fast Output Register assignment | REGOUT | ext_ram_bus_address[16] | DATAIN
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_address[17] | Packed Register | Register Packing | Fast Output Register assignment | REGOUT | ext_ram_bus_address[17] | DATAIN
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_address[18] | Packed Register | Register Packing | Fast Output Register assignment | REGOUT | ext_ram_bus_address[18] | DATAIN
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_address[19] | Packed Register | Register Packing | Fast Output Register assignment | REGOUT | ext_ram_bus_address[19] | DATAIN
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_address[20] | Packed Register | Register Packing | Fast Output Register assignment | REGOUT | ext_ram_bus_address[20] | DATAIN
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_address[21] | Packed Register | Register Packing | Fast Output Register assignment | REGOUT | ext_ram_bus_address[21] | DATAIN
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_address[22] | Packed Register | Register Packing | Fast Output Register assignment | REGOUT | ext_ram_bus_address[22] | DATAIN
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|internal_incoming_ext_ram_bus_data[0] | Packed Register | Register Packing | Fast Input Register assignment | REGOUT | ext_ram_bus_data[0] | COMBOUT
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|internal_incoming_ext_ram_bus_data[1] | Packed Register | Register Packing | Fast Input Register assignment | REGOUT | ext_ram_bus_data[1] | COMBOUT
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|internal_incoming_ext_ram_bus_data[2] | Packed Register | Register Packing | Fast Input Register assignment | REGOUT | ext_ram_bus_data[2] | COMBOUT
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|internal_incoming_ext_ram_bus_data[3] | Packed Register | Register Packing | Fast Input Register assignment | REGOUT | ext_ram_bus_data[3] | COMBOUT
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|internal_incoming_ext_ram_bus_data[4] | Packed Register | Register Packing | Fast Input Register assignment | REGOUT | ext_ram_bus_data[4] | COMBOUT
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|internal_incoming_ext_ram_bus_data[5] | Packed Register | Register Packing | Fast Input Register assignment | REGOUT | ext_ram_bus_data[5] | COMBOUT
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|internal_incoming_ext_ram_bus_data[6] | Packed Register | Register Packing | Fast Input Register assignment | REGOUT | ext_ram_bus_data[6] | COMBOUT
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|internal_incoming_ext_ram_bus_data[7] | Packed Register | Register Packing | Fast Input Register assignment | REGOUT | ext_ram_bus_data[7] | COMBOUT
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|internal_incoming_ext_ram_bus_data[8] | Packed Register | Register Packing | Fast Input Register assignment | REGOUT | ext_ram_bus_data[8] | COMBOUT
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|internal_incoming_ext_ram_bus_data[9] | Packed Register | Register Packing | Fast Input Register assignment | REGOUT | ext_ram_bus_data[9] | COMBOUT
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|internal_incoming_ext_ram_bus_data[10] | Packed Register | Register Packing | Fast Input Register assignment | REGOUT | ext_ram_bus_data[10] | COMBOUT
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|internal_incoming_ext_ram_bus_data[11] | Packed Register | Register Packing | Fast Input Register assignment | REGOUT | ext_ram_bus_data[11] | COMBOUT
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|internal_incoming_ext_ram_bus_data[12] | Packed Register | Register Packing | Fast Input Register assignment | REGOUT | ext_ram_bus_data[12] | COMBOUT
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|internal_incoming_ext_ram_bus_data[13] | Packed Register | Register Packing | Fast Input Register assignment | REGOUT | ext_ram_bus_data[13] | COMBOUT
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|internal_incoming_ext_ram_bus_data[14] | Packed Register | Register Packing | Fast Input Register assignment | REGOUT | ext_ram_bus_data[14] | COMBOUT
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|internal_incoming_ext_ram_bus_data[15] | Packed Register | Register Packing | Fast Input Register assignment | REGOUT | ext_ram_bus_data[15] | COMBOUT
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|internal_incoming_ext_ram_bus_data[16] | Packed Register | Register Packing | Fast Input Register assignment | REGOUT | ext_ram_bus_data[16] | COMBOUT
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|internal_incoming_ext_ram_bus_data[17] | Packed Register | Register Packing | Fast Input Register assignment | REGOUT | ext_ram_bus_data[17] | COMBOUT
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|internal_incoming_ext_ram_bus_data[18] | Packed Register | Register Packing | Fast Input Register assignment | REGOUT | ext_ram_bus_data[18] | COMBOUT
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|internal_incoming_ext_ram_bus_data[19] | Packed Register | Register Packing | Fast Input Register assignment | REGOUT | ext_ram_bus_data[19] | COMBOUT
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|internal_incoming_ext_ram_bus_data[20] | Packed Register | Register Packing | Fast Input Register assignment | REGOUT | ext_ram_bus_data[20] | COMBOUT
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|internal_incoming_ext_ram_bus_data[21] | Packed Register | Register Packing | Fast Input Register assignment | REGOUT | ext_ram_bus_data[21] | COMBOUT
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|internal_incoming_ext_ram_bus_data[22] | Packed Register | Register Packing | Fast Input Register assignment | REGOUT | ext_ram_bus_data[22] | COMBOUT
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|internal_incoming_ext_ram_bus_data[23] | Packed Register | Register Packing | Fast Input Register assignment | REGOUT | ext_ram_bus_data[23] | COMBOUT
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|internal_incoming_ext_ram_bus_data[24] | Packed Register | Register Packing | Fast Input Register assignment | REGOUT | ext_ram_bus_data[24] | COMBOUT
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|internal_incoming_ext_ram_bus_data[25] | Packed Register | Register Packing | Fast Input Register assignment | REGOUT | ext_ram_bus_data[25] | COMBOUT
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|internal_incoming_ext_ram_bus_data[26] | Packed Register | Register Packing | Fast Input Register assignment | REGOUT | ext_ram_bus_data[26] | COMBOUT
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|internal_incoming_ext_ram_bus_data[27] | Packed Register | Register Packing | Fast Input Register assignment | REGOUT | ext_ram_bus_data[27] | COMBOUT
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|internal_incoming_ext_ram_bus_data[28] | Packed Register | Register Packing | Fast Input Register assignment | REGOUT | ext_ram_bus_data[28] | COMBOUT
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|internal_incoming_ext_ram_bus_data[29] | Packed Register | Register Packing | Fast Input Register assignment | REGOUT | ext_ram_bus_data[29] | COMBOUT
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|internal_incoming_ext_ram_bus_data[30] | Packed Register | Register Packing | Fast Input Register assignment | REGOUT | ext_ram_bus_data[30] | COMBOUT
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|internal_incoming_ext_ram_bus_data[31] | Packed Register | Register Packing | Fast Input Register assignment | REGOUT | ext_ram_bus_data[31] | COMBOUT
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ior_n_to_the_lan91c111 | Packed Register | Register Packing | Fast Output Register assignment | REGOUT | ior_n_to_the_lan91c111 | DATAIN
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|iow_n_to_the_lan91c111 | Packed Register | Register Packing | Fast Output Register assignment | REGOUT | iow_n_to_the_lan91c111 | DATAIN
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|read_n_to_the_ext_flash | Packed Register | Register Packing | Fast Output Register assignment | REGOUT | read_n_to_the_ext_flash | DATAIN
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|read_n_to_the_ext_ram | Packed Register | Register Packing | Fast Output Register assignment | REGOUT | read_n_to_the_ext_ram | DATAIN
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|select_n_to_the_ext_flash | Packed Register | Register Packing | Fast Output Register assignment | REGOUT | select_n_to_the_ext_flash | DATAIN
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|select_n_to_the_ext_ram | Packed Register | Register Packing | Fast Output Register assignment | REGOUT | select_n_to_the_ext_ram | DATAIN
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|write_n_to_the_ext_flash | Packed Register | Register Packing | Fast Output Register assignment | REGOUT | write_n_to_the_ext_flash | DATAIN
std_1c20:inst|sdram:the_sdram|m_addr[0] | Packed Register | Register Packing | Fast Output Register assignment | REGOUT | zs_addr_from_the_sdram[0] | DATAIN
std_1c20:inst|sdram:the_sdram|m_addr[0] | Duplicated | Register Packing | Fast Output Register assignment | REGOUT | std_1c20:inst|sdram:the_sdram|m_addr[0]~_Duplicate_1 | REGOUT
std_1c20:inst|sdram:the_sdram|m_addr[1] | Packed Register | Register Packing | Fast Output Register assignment | REGOUT | zs_addr_from_the_sdram[1] | DATAIN
std_1c20:inst|sdram:the_sdram|m_addr[1] | Duplicated | Register Packing | Fast Output Register assignment | REGOUT | std_1c20:inst|sdram:the_sdram|m_addr[1]~_Duplicate_1 | REGOUT
std_1c20:inst|sdram:the_sdram|m_addr[2] | Packed Register | Register Packing | Fast Output Register assignment | REGOUT | zs_addr_from_the_sdram[2] | DATAIN
std_1c20:inst|sdram:the_sdram|m_addr[2] | Duplicated | Register Packing | Fast Output Register assignment | REGOUT | std_1c20:inst|sdram:the_sdram|m_addr[2]~_Duplicate_1 | REGOUT
std_1c20:inst|sdram:the_sdram|m_addr[3] | Packed Register | Register Packing | Fast Output Register assignment | REGOUT | zs_addr_from_the_sdram[3] | DATAIN
std_1c20:inst|sdram:the_sdram|m_addr[3] | Duplicated | Register Packing | Fast Output Register assignment | REGOUT | std_1c20:inst|sdram:the_sdram|m_addr[3]~_Duplicate_1 | REGOUT
std_1c20:inst|sdram:the_sdram|m_addr[4] | Packed Register | Register Packing | Fast Output Register assignment | REGOUT | zs_addr_from_the_sdram[4] | DATAIN
std_1c20:inst|sdram:the_sdram|m_addr[4] | Duplicated | Register Packing | Fast Output Register assignment | REGOUT | std_1c20:inst|sdram:the_sdram|m_addr[4]~_Duplicate_1 | REGOUT
std_1c20:inst|sdram:the_sdram|m_addr[5] | Packed Register | Register Packing | Fast Output Register assignment | REGOUT | zs_addr_from_the_sdram[5] | DATAIN
std_1c20:inst|sdram:the_sdram|m_addr[5] | Duplicated | Register Packing | Fast Output Register assignment | REGOUT | std_1c20:inst|sdram:the_sdram|m_addr[5]~_Duplicate_1 | REGOUT
std_1c20:inst|sdram:the_sdram|m_addr[6] | Packed Register | Register Packing | Fast Output Register assignment | REGOUT | zs_addr_from_the_sdram[6] | DATAIN
std_1c20:inst|sdram:the_sdram|m_addr[6] | Duplicated | Register Packing | Fast Output Register assignment | REGOUT | std_1c20:inst|sdram:the_sdram|m_addr[6]~_Duplicate_1 | REGOUT
std_1c20:inst|sdram:the_sdram|m_addr[7] | Packed Register | Register Packing | Fast Output Register assignment | REGOUT | zs_addr_from_the_sdram[7] | DATAIN
std_1c20:inst|sdram:the_sdram|m_addr[7] | Duplicated | Register Packing | Fast Output Register assignment | REGOUT | std_1c20:inst|sdram:the_sdram|m_addr[7]~_Duplicate_1 | REGOUT
std_1c20:inst|sdram:the_sdram|m_addr[8] | Packed Register | Register Packing | Fast Output Register assignment | REGOUT | zs_addr_from_the_sdram[8] | DATAIN
std_1c20:inst|sdram:the_sdram|m_addr[8] | Duplicated | Register Packing | Fast Output Register assignment | REGOUT | std_1c20:inst|sdram:the_sdram|m_addr[8]~_Duplicate_1 | REGOUT
std_1c20:inst|sdram:the_sdram|m_addr[9] | Packed Register | Register Packing | Fast Output Register assignment | REGOUT | zs_addr_from_the_sdram[9] | DATAIN
std_1c20:inst|sdram:the_sdram|m_addr[9] | Duplicated | Register Packing | Fast Output Register assignment | REGOUT | std_1c20:inst|sdram:the_sdram|m_addr[9]~_Duplicate_1 | REGOUT
std_1c20:inst|sdram:the_sdram|m_addr[10] | Packed Register | Register Packing | Fast Output Register assignment | REGOUT | zs_addr_from_the_sdram[10] | DATAIN
std_1c20:inst|sdram:the_sdram|m_addr[10] | Duplicated | Register Packing | Fast Output Register assignment | REGOUT | std_1c20:inst|sdram:the_sdram|m_addr[10]~_Duplicate_1 | REGOUT
std_1c20:inst|sdram:the_sdram|m_addr[11] | Packed Register | Register Packing | Fast Output Register assignment | REGOUT | zs_addr_from_the_sdram[11] | DATAIN
std_1c20:inst|sdram:the_sdram|m_addr[11] | Duplicated | Register Packing | Fast Output Register assignment | REGOUT | std_1c20:inst|sdram:the_sdram|m_addr[11]~_Duplicate_1 | REGOUT
std_1c20:inst|sdram:the_sdram|m_bank[0] | Packed Register | Register Packing | Fast Output Register assignment | REGOUT | zs_ba_from_the_sdram[0] | DATAIN
std_1c20:inst|sdram:the_sdram|m_bank[0] | Duplicated | Register Packing | Fast Output Register assignment | REGOUT | std_1c20:inst|sdram:the_sdram|m_bank[0]~_Duplicate_1 | REGOUT
std_1c20:inst|sdram:the_sdram|m_bank[1] | Packed Register | Register Packing | Fast Output Register assignment | REGOUT | zs_ba_from_the_sdram[1] | DATAIN
std_1c20:inst|sdram:the_sdram|m_bank[1] | Duplicated | Register Packing | Fast Output Register assignment | REGOUT | std_1c20:inst|sdram:the_sdram|m_bank[1]~_Duplicate_1 | REGOUT
std_1c20:inst|sdram:the_sdram|m_cmd[0] | Packed Register | Register Packing | Fast Output Register assignment | REGOUT | zs_we_n_from_the_sdram | DATAIN
std_1c20:inst|sdram:the_sdram|m_cmd[0] | Duplicated | Register Packing | Fast Output Register assignment | REGOUT | std_1c20:inst|sdram:the_sdram|m_cmd[0]~_Duplicate_1 | REGOUT
std_1c20:inst|sdram:the_sdram|m_cmd[1] | Packed Register | Register Packing | Fast Output Register assignment | REGOUT | zs_cas_n_from_the_sdram | DATAIN
std_1c20:inst|sdram:the_sdram|m_cmd[1] | Duplicated | Register Packing | Fast Output Register assignment | REGOUT | std_1c20:inst|sdram:the_sdram|m_cmd[1]~_Duplicate_1 | REGOUT
std_1c20:inst|sdram:the_sdram|m_cmd[2] | Packed Register | Register Packing | Fast Output Register assignment | REGOUT | zs_ras_n_from_the_sdram | DATAIN
std_1c20:inst|sdram:the_sdram|m_cmd[2] | Duplicated | Register Packing | Fast Output Register assignment | REGOUT | std_1c20:inst|sdram:the_sdram|m_cmd[2]~_Duplicate_1 | REGOUT
std_1c20:inst|sdram:the_sdram|m_cmd[3] | Packed Register | Register Packing | Fast Output Register assignment | REGOUT | zs_cs_n_from_the_sdram | DATAIN
std_1c20:inst|sdram:the_sdram|m_data[0] | Packed Register | Register Packing | Fast Output Register assignment | REGOUT | zs_dq_to_and_from_the_sdram[0] | DATAIN
std_1c20:inst|sdram:the_sdram|m_data[0] | Duplicated | Register Packing | Fast Output Register assignment | REGOUT | std_1c20:inst|sdram:the_sdram|m_data[0]~_Duplicate_1 | REGOUT
std_1c20:inst|sdram:the_sdram|m_data[1] | Packed Register | Register Packing | Fast Output Register assignment | REGOUT | zs_dq_to_and_from_the_sdram[1] | DATAIN
std_1c20:inst|sdram:the_sdram|m_data[1] | Duplicated | Register Packing | Fast Output Register assignment | REGOUT | std_1c20:inst|sdram:the_sdram|m_data[1]~_Duplicate_1 | REGOUT
std_1c20:inst|sdram:the_sdram|m_data[2] | Packed Register | Register Packing | Fast Output Register assignment | REGOUT | zs_dq_to_and_from_the_sdram[2] | DATAIN
std_1c20:inst|sdram:the_sdram|m_data[2] | Duplicated | Register Packing | Fast Output Register assignment | REGOUT | std_1c20:inst|sdram:the_sdram|m_data[2]~_Duplicate_1 | REGOUT
std_1c20:inst|sdram:the_sdram|m_data[3] | Packed Register | Register Packing | Fast Output Register assignment | REGOUT | zs_dq_to_and_from_the_sdram[3] | DATAIN
std_1c20:inst|sdram:the_sdram|m_data[3] | Duplicated | Register Packing | Fast Output Register assignment | REGOUT | std_1c20:inst|sdram:the_sdram|m_data[3]~_Duplicate_1 | REGOUT
std_1c20:inst|sdram:the_sdram|m_data[4] | Packed Register | Register Packing | Fast Output Register assignment | REGOUT | zs_dq_to_and_from_the_sdram[4] | DATAIN
std_1c20:inst|sdram:the_sdram|m_data[4] | Duplicated | Register Packing | Fast Output Register assignment | REGOUT | std_1c20:inst|sdram:the_sdram|m_data[4]~_Duplicate_1 | REGOUT
std_1c20:inst|sdram:the_sdram|m_data[5] | Packed Register | Register Packing | Fast Output Register assignment | REGOUT | zs_dq_to_and_from_the_sdram[5] | DATAIN
std_1c20:inst|sdram:the_sdram|m_data[5] | Duplicated | Register Packing | Fast Output Register assignment | REGOUT | std_1c20:inst|sdram:the_sdram|m_data[5]~_Duplicate_1 | REGOUT
std_1c20:inst|sdram:the_sdram|m_data[6] | Packed Register | Register Packing | Fast Output Register assignment | REGOUT | zs_dq_to_and_from_the_sdram[6] | DATAIN
std_1c20:inst|sdram:the_sdram|m_data[6] | Duplicated | Register Packing | Fast Output Register assignment | REGOUT | std_1c20:inst|sdram:the_sdram|m_data[6]~_Duplicate_1 | REGOUT
std_1c20:inst|sdram:the_sdram|m_data[7] | Packed Register | Register Packing | Fast Output Register assignment | REGOUT | zs_dq_to_and_from_the_sdram[7] | DATAIN
std_1c20:inst|sdram:the_sdram|m_data[7] | Duplicated | Register Packing | Fast Output Register assignment | REGOUT | std_1c20:inst|sdram:the_sdram|m_data[7]~_Duplicate_1 | REGOUT
std_1c20:inst|sdram:the_sdram|m_data[8] | Packed Register | Register Packing | Fast Output Register assignment | REGOUT | zs_dq_to_and_from_the_sdram[8] | DATAIN
std_1c20:inst|sdram:the_sdram|m_data[8] | Duplicated | Register Packing | Fast Output Register assignment | REGOUT | std_1c20:inst|sdram:the_sdram|m_data[8]~_Duplicate_1 | REGOUT
std_1c20:inst|sdram:the_sdram|m_data[9] | Packed Register | Register Packing | Fast Output Register assignment | REGOUT | zs_dq_to_and_from_the_sdram[9] | DATAIN
std_1c20:inst|sdram:the_sdram|m_data[9] | Duplicated | Register Packing | Fast Output Register assignment | REGOUT | std_1c20:inst|sdram:the_sdram|m_data[9]~_Duplicate_1 | REGOUT
std_1c20:inst|sdram:the_sdram|m_data[10] | Packed Register | Register Packing | Fast Output Register assignment | REGOUT | zs_dq_to_and_from_the_sdram[10] | DATAIN
std_1c20:inst|sdram:the_sdram|m_data[10] | Duplicated | Register Packing | Fast Output Register assignment | REGOUT | std_1c20:inst|sdram:the_sdram|m_data[10]~_Duplicate_1 | REGOUT
std_1c20:inst|sdram:the_sdram|m_data[11] | Packed Register | Register Packing | Fast Output Register assignment | REGOUT | zs_dq_to_and_from_the_sdram[11] | DATAIN
std_1c20:inst|sdram:the_sdram|m_data[11] | Duplicated | Register Packing | Fast Output Register assignment | REGOUT | std_1c20:inst|sdram:the_sdram|m_data[11]~_Duplicate_1 | REGOUT
std_1c20:inst|sdram:the_sdram|m_data[12] | Packed Register | Register Packing | Fast Output Register assignment | REGOUT | zs_dq_to_and_from_the_sdram[12] | DATAIN
std_1c20:inst|sdram:the_sdram|m_data[12] | Duplicated | Register Packing | Fast Output Register assignment | REGOUT | std_1c20:inst|sdram:the_sdram|m_data[12]~_Duplicate_1 | REGOUT
std_1c20:inst|sdram:the_sdram|m_data[13] | Packed Register | Register Packing | Fast Output Register assignment | REGOUT | zs_dq_to_and_from_the_sdram[13] | DATAIN
std_1c20:inst|sdram:the_sdram|m_data[13] | Duplicated | Register Packing | Fast Output Register assignment | REGOUT | std_1c20:inst|sdram:the_sdram|m_data[13]~_Duplicate_1 | REGOUT
std_1c20:inst|sdram:the_sdram|m_data[14] | Packed Register | Register Packing | Fast Output Register assignment | REGOUT | zs_dq_to_and_from_the_sdram[14] | DATAIN
std_1c20:inst|sdram:the_sdram|m_data[14] | Duplicated | Register Packing | Fast Output Register assignment | REGOUT | std_1c20:inst|sdram:the_sdram|m_data[14]~_Duplicate_1 | REGOUT
std_1c20:inst|sdram:the_sdram|m_data[15] | Packed Register | Register Packing | Fast Output Register assignment | REGOUT | zs_dq_to_and_from_the_sdram[15] | DATAIN
std_1c20:inst|sdram:the_sdram|m_data[15] | Duplicated | Register Packing | Fast Output Register assignment | REGOUT | std_1c20:inst|sdram:the_sdram|m_data[15]~_Duplicate_1 | REGOUT
std_1c20:inst|sdram:the_sdram|m_data[16] | Packed Register | Register Packing | Fast Output Register assignment | REGOUT | zs_dq_to_and_from_the_sdram[16] | DATAIN
std_1c20:inst|sdram:the_sdram|m_data[16] | Duplicated | Register Packing | Fast Output Register assignment | REGOUT | std_1c20:inst|sdram:the_sdram|m_data[16]~_Duplicate_1 | REGOUT
std_1c20:inst|sdram:the_sdram|m_data[17] | Packed Register | Register Packing | Fast Output Register assignment | REGOUT | zs_dq_to_and_from_the_sdram[17] | DATAIN
std_1c20:inst|sdram:the_sdram|m_data[17] | Duplicated | Register Packing | Fast Output Register assignment | REGOUT | std_1c20:inst|sdram:the_sdram|m_data[17]~_Duplicate_1 | REGOUT
std_1c20:inst|sdram:the_sdram|m_data[18] | Packed Register | Register Packing | Fast Output Register assignment | REGOUT | zs_dq_to_and_from_the_sdram[18] | DATAIN
std_1c20:inst|sdram:the_sdram|m_data[18] | Duplicated | Register Packing | Fast Output Register assignment | REGOUT | std_1c20:inst|sdram:the_sdram|m_data[18]~_Duplicate_1 | REGOUT
std_1c20:inst|sdram:the_sdram|m_data[19] | Packed Register | Register Packing | Fast Output Register assignment | REGOUT | zs_dq_to_and_from_the_sdram[19] | DATAIN
std_1c20:inst|sdram:the_sdram|m_data[19] | Duplicated | Register Packing | Fast Output Register assignment | REGOUT | std_1c20:inst|sdram:the_sdram|m_data[19]~_Duplicate_1 | REGOUT
std_1c20:inst|sdram:the_sdram|m_data[20] | Packed Register | Register Packing | Fast Output Register assignment | REGOUT | zs_dq_to_and_from_the_sdram[20] | DATAIN
std_1c20:inst|sdram:the_sdram|m_data[20] | Duplicated | Register Packing | Fast Output Register assignment | REGOUT | std_1c20:inst|sdram:the_sdram|m_data[20]~_Duplicate_1 | REGOUT
std_1c20:inst|sdram:the_sdram|m_data[21] | Packed Register | Register Packing | Fast Output Register assignment | REGOUT | zs_dq_to_and_from_the_sdram[21] | DATAIN
std_1c20:inst|sdram:the_sdram|m_data[21] | Duplicated | Register Packing | Fast Output Register assignment | REGOUT | std_1c20:inst|sdram:the_sdram|m_data[21]~_Duplicate_1 | REGOUT
std_1c20:inst|sdram:the_sdram|m_data[22] | Packed Register | Register Packing | Fast Output Register assignment | REGOUT | zs_dq_to_and_from_the_sdram[22] | DATAIN
std_1c20:inst|sdram:the_sdram|m_data[22] | Duplicated | Register Packing | Fast Output Register assignment | REGOUT | std_1c20:inst|sdram:the_sdram|m_data[22]~_Duplicate_1 | REGOUT
std_1c20:inst|sdram:the_sdram|m_data[23] | Packed Register | Register Packing | Fast Output Register assignment | REGOUT | zs_dq_to_and_from_the_sdram[23] | DATAIN
std_1c20:inst|sdram:the_sdram|m_data[23] | Duplicated | Register Packing | Fast Output Register assignment | REGOUT | std_1c20:inst|sdram:the_sdram|m_data[23]~_Duplicate_1 | REGOUT
std_1c20:inst|sdram:the_sdram|m_data[24] | Packed Register | Register Packing | Fast Output Register assignment | REGOUT | zs_dq_to_and_from_the_sdram[24] | DATAIN
std_1c20:inst|sdram:the_sdram|m_data[24] | Duplicated | Register Packing | Fast Output Register assignment | REGOUT | std_1c20:inst|sdram:the_sdram|m_data[24]~_Duplicate_1 | REGOUT
std_1c20:inst|sdram:the_sdram|m_data[25] | Packed Register | Register Packing | Fast Output Register assignment | REGOUT | zs_dq_to_and_from_the_sdram[25] | DATAIN
std_1c20:inst|sdram:the_sdram|m_data[25] | Duplicated | Register Packing | Fast Output Register assignment | REGOUT | std_1c20:inst|sdram:the_sdram|m_data[25]~_Duplicate_1 | REGOUT
std_1c20:inst|sdram:the_sdram|m_data[26] | Packed Register | Register Packing | Fast Output Register assignment | REGOUT | zs_dq_to_and_from_the_sdram[26] | DATAIN
std_1c20:inst|sdram:the_sdram|m_data[26] | Duplicated | Register Packing | Fast Output Register assignment | REGOUT | std_1c20:inst|sdram:the_sdram|m_data[26]~_Duplicate_1 | REGOUT
std_1c20:inst|sdram:the_sdram|m_data[27] | Packed Register | Register Packing | Fast Output Register assignment | REGOUT | zs_dq_to_and_from_the_sdram[27] | DATAIN
std_1c20:inst|sdram:the_sdram|m_data[27] | Duplicated | Register Packing | Fast Output Register assignment | REGOUT | std_1c20:inst|sdram:the_sdram|m_data[27]~_Duplicate_1 | REGOUT
std_1c20:inst|sdram:the_sdram|m_data[28] | Packed Register | Register Packing | Fast Output Register assignment | REGOUT | zs_dq_to_and_from_the_sdram[28] | DATAIN
std_1c20:inst|sdram:the_sdram|m_data[28] | Duplicated | Register Packing | Fast Output Register assignment | REGOUT | std_1c20:inst|sdram:the_sdram|m_data[28]~_Duplicate_1 | REGOUT
std_1c20:inst|sdram:the_sdram|m_data[29] | Packed Register | Register Packing | Fast Output Register assignment | REGOUT | zs_dq_to_and_from_the_sdram[29] | DATAIN
std_1c20:inst|sdram:the_sdram|m_data[29] | Duplicated | Register Packing | Fast Output Register assignment | REGOUT | std_1c20:inst|sdram:the_sdram|m_data[29]~_Duplicate_1 | REGOUT
std_1c20:inst|sdram:the_sdram|m_data[30] | Packed Register | Register Packing | Fast Output Register assignment | REGOUT | zs_dq_to_and_from_the_sdram[30] | DATAIN
std_1c20:inst|sdram:the_sdram|m_data[30] | Duplicated | Register Packing | Fast Output Register assignment | REGOUT | std_1c20:inst|sdram:the_sdram|m_data[30]~_Duplicate_1 | REGOUT
std_1c20:inst|sdram:the_sdram|m_data[31] | Packed Register | Register Packing | Fast Output Register assignment | REGOUT | zs_dq_to_and_from_the_sdram[31] | DATAIN
std_1c20:inst|sdram:the_sdram|m_data[31] | Duplicated | Register Packing | Fast Output Register assignment | REGOUT | std_1c20:inst|sdram:the_sdram|m_data[31]~_Duplicate_1 | REGOUT
std_1c20:inst|sdram:the_sdram|m_dqm[0] | Packed Register | Register Packing | Fast Output Register assignment | REGOUT | zs_dqm_from_the_sdram[0] | DATAIN
std_1c20:inst|sdram:the_sdram|m_dqm[0] | Duplicated | Register Packing | Fast Output Register assignment | REGOUT | std_1c20:inst|sdram:the_sdram|m_dqm[0]~_Duplicate_1 | REGOUT
std_1c20:inst|sdram:the_sdram|m_dqm[1] | Packed Register | Register Packing | Fast Output Register assignment | REGOUT | zs_dqm_from_the_sdram[1] | DATAIN
std_1c20:inst|sdram:the_sdram|m_dqm[1] | Duplicated | Register Packing | Fast Output Register assignment | REGOUT | std_1c20:inst|sdram:the_sdram|m_dqm[1]~_Duplicate_1 | REGOUT
std_1c20:inst|sdram:the_sdram|m_dqm[2] | Packed Register | Register Packing | Fast Output Register assignment | REGOUT | zs_dqm_from_the_sdram[2] | DATAIN
std_1c20:inst|sdram:the_sdram|m_dqm[2] | Duplicated | Register Packing | Fast Output Register assignment | REGOUT | std_1c20:inst|sdram:the_sdram|m_dqm[2]~_Duplicate_1 | REGOUT
std_1c20:inst|sdram:the_sdram|m_dqm[3] | Packed Register | Register Packing | Fast Output Register assignment | REGOUT | zs_dqm_from_the_sdram[3] | DATAIN
std_1c20:inst|sdram:the_sdram|m_dqm[3] | Duplicated | Register Packing | Fast Output Register assignment | REGOUT | std_1c20:inst|sdram:the_sdram|m_dqm[3]~_Duplicate_1 | REGOUT
std_1c20:inst|sdram:the_sdram|za_data[0] | Packed Register | Register Packing | Fast Input Register assignment | REGOUT | zs_dq_to_and_from_the_sdram[0] | COMBOUT
std_1c20:inst|sdram:the_sdram|za_data[1] | Packed Register | Register Packing | Fast Input Register assignment | REGOUT | zs_dq_to_and_from_the_sdram[1] | COMBOUT
std_1c20:inst|sdram:the_sdram|za_data[2] | Packed Register | Register Packing | Fast Input Register assignment | REGOUT | zs_dq_to_and_from_the_sdram[2] | COMBOUT
std_1c20:inst|sdram:the_sdram|za_data[3] | Packed Register | Register Packing | Fast Input Register assignment | REGOUT | zs_dq_to_and_from_the_sdram[3] | COMBOUT
std_1c20:inst|sdram:the_sdram|za_data[4] | Packed Register | Register Packing | Fast Input Register assignment | REGOUT | zs_dq_to_and_from_the_sdram[4] | COMBOUT
std_1c20:inst|sdram:the_sdram|za_data[5] | Packed Register | Register Packing | Fast Input Register assignment | REGOUT | zs_dq_to_and_from_the_sdram[5] | COMBOUT
std_1c20:inst|sdram:the_sdram|za_data[6] | Packed Register | Register Packing | Fast Input Register assignment | REGOUT | zs_dq_to_and_from_the_sdram[6] | COMBOUT
std_1c20:inst|sdram:the_sdram|za_data[7] | Packed Register | Register Packing | Fast Input Register assignment | REGOUT | zs_dq_to_and_from_the_sdram[7] | COMBOUT
std_1c20:inst|sdram:the_sdram|za_data[8] | Packed Register | Register Packing | Fast Input Register assignment | REGOUT | zs_dq_to_and_from_the_sdram[8] | COMBOUT
std_1c20:inst|sdram:the_sdram|za_data[9] | Packed Register | Register Packing | Fast Input Register assignment | REGOUT | zs_dq_to_and_from_the_sdram[9] | COMBOUT
std_1c20:inst|sdram:the_sdram|za_data[10] | Packed Register | Register Packing | Fast Input Register assignment | REGOUT | zs_dq_to_and_from_the_sdram[10] | COMBOUT
std_1c20:inst|sdram:the_sdram|za_data[11] | Packed Register | Register Packing | Fast Input Register assignment | REGOUT | zs_dq_to_and_from_the_sdram[11] | COMBOUT
std_1c20:inst|sdram:the_sdram|za_data[12] | Packed Register | Register Packing | Fast Input Register assignment | REGOUT | zs_dq_to_and_from_the_sdram[12] | COMBOUT
std_1c20:inst|sdram:the_sdram|za_data[13] | Packed Register | Register Packing | Fast Input Register assignment | REGOUT | zs_dq_to_and_from_the_sdram[13] | COMBOUT
std_1c20:inst|sdram:the_sdram|za_data[14] | Packed Register | Register Packing | Fast Input Register assignment | REGOUT | zs_dq_to_and_from_the_sdram[14] | COMBOUT
std_1c20:inst|sdram:the_sdram|za_data[15] | Packed Register | Register Packing | Fast Input Register assignment | REGOUT | zs_dq_to_and_from_the_sdram[15] | COMBOUT
std_1c20:inst|sdram:the_sdram|za_data[16] | Packed Register | Register Packing | Fast Input Register assignment | REGOUT | zs_dq_to_and_from_the_sdram[16] | COMBOUT
std_1c20:inst|sdram:the_sdram|za_data[17] | Packed Register | Register Packing | Fast Input Register assignment | REGOUT | zs_dq_to_and_from_the_sdram[17] | COMBOUT
std_1c20:inst|sdram:the_sdram|za_data[18] | Packed Register | Register Packing | Fast Input Register assignment | REGOUT | zs_dq_to_and_from_the_sdram[18] | COMBOUT
std_1c20:inst|sdram:the_sdram|za_data[19] | Packed Register | Register Packing | Fast Input Register assignment | REGOUT | zs_dq_to_and_from_the_sdram[19] | COMBOUT
std_1c20:inst|sdram:the_sdram|za_data[20] | Packed Register | Register Packing | Fast Input Register assignment | REGOUT | zs_dq_to_and_from_the_sdram[20] | COMBOUT
std_1c20:inst|sdram:the_sdram|za_data[21] | Packed Register | Register Packing | Fast Input Register assignment | REGOUT | zs_dq_to_and_from_the_sdram[21] | COMBOUT
std_1c20:inst|sdram:the_sdram|za_data[22] | Packed Register | Register Packing | Fast Input Register assignment | REGOUT | zs_dq_to_and_from_the_sdram[22] | COMBOUT
std_1c20:inst|sdram:the_sdram|za_data[23] | Packed Register | Register Packing | Fast Input Register assignment | REGOUT | zs_dq_to_and_from_the_sdram[23] | COMBOUT
std_1c20:inst|sdram:the_sdram|za_data[24] | Packed Register | Register Packing | Fast Input Register assignment | REGOUT | zs_dq_to_and_from_the_sdram[24] | COMBOUT
std_1c20:inst|sdram:the_sdram|za_data[25] | Packed Register | Register Packing | Fast Input Register assignment | REGOUT | zs_dq_to_and_from_the_sdram[25] | COMBOUT
std_1c20:inst|sdram:the_sdram|za_data[26] | Packed Register | Register Packing | Fast Input Register assignment | REGOUT | zs_dq_to_and_from_the_sdram[26] | COMBOUT
std_1c20:inst|sdram:the_sdram|za_data[27] | Packed Register | Register Packing | Fast Input Register assignment | REGOUT | zs_dq_to_and_from_the_sdram[27] | COMBOUT
std_1c20:inst|sdram:the_sdram|za_data[28] | Packed Register | Register Packing | Fast Input Register assignment | REGOUT | zs_dq_to_and_from_the_sdram[28] | COMBOUT
std_1c20:inst|sdram:the_sdram|za_data[29] | Packed Register | Register Packing | Fast Input Register assignment | REGOUT | zs_dq_to_and_from_the_sdram[29] | COMBOUT
std_1c20:inst|sdram:the_sdram|za_data[30] | Packed Register | Register Packing | Fast Input Register assignment | REGOUT | zs_dq_to_and_from_the_sdram[30] | COMBOUT
std_1c20:inst|sdram:the_sdram|za_data[31] | Packed Register | Register Packing | Fast Input Register assignment | REGOUT | zs_dq_to_and_from_the_sdram[31] | COMBOUT
LCD_RW_from_the_lcd_display | Modified | Physical Synthesis | Timing optimization |  |  |
LCD_data_to_and_from_the_lcd_display[0] | Modified | Physical Synthesis | Timing optimization |  |  |
LCD_data_to_and_from_the_lcd_display[1] | Modified | Physical Synthesis | Timing optimization |  |  |
LCD_data_to_and_from_the_lcd_display[2] | Modified | Physical Synthesis | Timing optimization |  |  |
LCD_data_to_and_from_the_lcd_display[3] | Modified | Physical Synthesis | Timing optimization |  |  |
LCD_data_to_and_from_the_lcd_display[4] | Modified | Physical Synthesis | Timing optimization |  |  |
LCD_data_to_and_from_the_lcd_display[5] | Modified | Physical Synthesis | Timing optimization |  |  |
LCD_data_to_and_from_the_lcd_display[6] | Modified | Physical Synthesis | Timing optimization |  |  |
LCD_data_to_and_from_the_lcd_display[7] | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|button_pio:the_button_pio|edge_capture[0] | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|button_pio:the_button_pio|edge_capture[1] | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|button_pio:the_button_pio|edge_capture[2] | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|button_pio:the_button_pio|edge_capture[3] | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|button_pio:the_button_pio|irq_mask[0] | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|button_pio:the_button_pio|irq_mask[1] | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|button_pio:the_button_pio|irq_mask[2] | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|button_pio:the_button_pio|irq_mask[3] | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|button_pio:the_button_pio|process1~14 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|button_pio:the_button_pio|process1~15_BDD379 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|button_pio:the_button_pio|readdata[0] | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|button_pio:the_button_pio|readdata[1] | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|button_pio:the_button_pio|readdata[2] | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|button_pio:the_button_pio|readdata[3] | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|button_pio_s1_arbitrator:the_button_pio_s1|cpu_data_master_requests_button_pio_s1 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|button_pio_s1_arbitrator:the_button_pio_s1|cpu_data_master_requests_button_pio_s1~74 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|clock_0:the_clock_0|slave_nativeaddress_d1[0] | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|clock_0:the_clock_0|slave_nativeaddress_d1[2] | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|clock_0_in_arbitrator:the_clock_0_in|cpu_data_master_requests_clock_0_in | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|clock_0_in_arbitrator:the_clock_0_in|cpu_data_master_requests_clock_0_in~535 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|clock_0_in_arbitrator:the_clock_0_in|cpu_data_master_requests_clock_0_in~536 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|clock_0_in_arbitrator:the_clock_0_in|cpu_data_master_requests_clock_0_in~539_BDD155 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|clock_0_in_arbitrator:the_clock_0_in|cpu_data_master_requests_clock_0_in~541_BDD598 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|clock_0_in_arbitrator:the_clock_0_in|cpu_data_master_requests_clock_0_in~542_BDD599 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|clock_0_in_arbitrator:the_clock_0_in|cpu_data_master_requests_clock_0_in~543_BDD600 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|clock_1:the_clock_1|slave_nativeaddress_d1[0] | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|clock_1:the_clock_1|slave_nativeaddress_d1[2] | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|clock_1:the_clock_1|slave_readdata[0] | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|clock_1:the_clock_1|slave_readdata[1] | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|clock_1:the_clock_1|slave_readdata[2] | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|clock_1:the_clock_1|slave_readdata[3] | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|clock_1:the_clock_1|slave_readdata[4] | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|clock_1:the_clock_1|slave_readdata[5] | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|clock_1:the_clock_1|slave_readdata[6] | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|clock_1:the_clock_1|slave_readdata[7] | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|clock_1:the_clock_1|slave_readdata[8] | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|clock_1:the_clock_1|slave_readdata[9] | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|clock_1:the_clock_1|slave_readdata[10] | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|clock_1:the_clock_1|slave_readdata[12] | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|clock_1:the_clock_1|slave_readdata[13] | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|clock_1:the_clock_1|slave_readdata[14] | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|clock_1:the_clock_1|slave_readdata[15] | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|clock_1_in_arbitrator:the_clock_1_in|cpu_data_master_requests_clock_1_in | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|D_ic_fill_starting_d1 | Duplicated | Physical Synthesis | Timing optimization | COMBOUT | std_1c20:inst|cpu:the_cpu|D_ic_fill_starting_d1~_DUP_COMB | COMBOUT
std_1c20:inst|cpu:the_cpu|D_ic_fill_starting_d1 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|D_ic_fill_starting_d1~_DUP_COMB | Deleted | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|D_pc[0] | Duplicated | Physical Synthesis | Timing optimization | COMBOUT | std_1c20:inst|cpu:the_cpu|D_pc[0]~_DUP_COMB | COMBOUT
std_1c20:inst|cpu:the_cpu|D_pc[0] | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|E_src1[4]~2037 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|E_src1[4]~2047_BDD631 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|E_src1[16]~2022 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|E_src1_hazard_M~10 | Retimed Register | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|E_src1_prelim[1] | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|E_src1_prelim[2] | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|E_src1_prelim[3] | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|E_src1_prelim[4] | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|E_src1_prelim[5] | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|E_src1_prelim[6] | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|E_src1_prelim[20] | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|E_src1_prelim[21] | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|E_src1_prelim[22] | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|E_src1_prelim[23] | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|E_src2[0]~1528 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|E_src2[1]~1527 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|E_src2[2]~1503 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|E_src2[3]~1504 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|E_src2[4]~1525 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|E_src2[5]~1526 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|E_src2[6]~1524 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|E_src2[13]~1513 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|E_src2[13]~1569_BDD143 | Deleted | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|E_src2[13]~1570_BDD144 | Deleted | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|E_src2[13]~1599_BDD632 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|E_src2[13]~1600_BDD633 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|E_src2[16]~1587_BDD512 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|E_src2[17]~1590_BDD550 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|E_src2[18]~1596_BDD556 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|E_src2[19]~1507 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|E_src2[19]~1593_BDD553 | Deleted | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|E_src2[20]~1517 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|E_src2[21]~1506 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|E_src2[22]~1505 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|E_src2[23]~1518 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|E_src2_prelim[0] | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|E_src2_prelim[1] | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|E_src2_prelim[2] | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|E_src2_prelim[3] | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|E_src2_prelim[4] | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|E_src2_prelim[5] | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|E_src2_prelim[6] | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|E_src2_prelim[20] | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|E_src2_prelim[21] | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|E_src2_prelim[22] | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|E_src2_prelim[23] | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|Equal199~133 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|Equal199~136 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|M_alu_result[0] | Duplicated | Physical Synthesis | Timing optimization | REGOUT | std_1c20:inst|cpu:the_cpu|M_alu_result[0]~_DUP_REG | REGOUT
std_1c20:inst|cpu:the_cpu|M_alu_result[0]~_DUP_REG | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|M_alu_result[1] | Duplicated | Physical Synthesis | Timing optimization | COMBOUT | std_1c20:inst|cpu:the_cpu|M_alu_result[1]~_DUP_COMB | COMBOUT
std_1c20:inst|cpu:the_cpu|M_alu_result[1] | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|M_alu_result[2] | Duplicated | Physical Synthesis | Timing optimization | REGOUT | std_1c20:inst|cpu:the_cpu|M_alu_result[2]~_DUP_REG | REGOUT
std_1c20:inst|cpu:the_cpu|M_alu_result[2]~_DUP_REG | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|M_alu_result[4] | Duplicated | Physical Synthesis | Timing optimization | REGOUT | std_1c20:inst|cpu:the_cpu|M_alu_result[4]~_DUP_REG | REGOUT
std_1c20:inst|cpu:the_cpu|M_alu_result[4]~_DUP_REG | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|M_alu_result[5] | Duplicated | Physical Synthesis | Timing optimization | REGOUT | std_1c20:inst|cpu:the_cpu|M_alu_result[5]~_DUP_REG | REGOUT
std_1c20:inst|cpu:the_cpu|M_alu_result[5] | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|M_alu_result[5]~415_BDD210 | Deleted | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|M_alu_result[5]~416_BDD211 | Deleted | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|M_alu_result[5]~_DUP_REG | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|M_alu_result[7] | Duplicated | Physical Synthesis | Timing optimization | REGOUT | std_1c20:inst|cpu:the_cpu|M_alu_result[7]~_DUP_REG | REGOUT
std_1c20:inst|cpu:the_cpu|M_alu_result[7] | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|M_alu_result[7]~_DUP_REG | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|M_alu_result[10] | Duplicated | Physical Synthesis | Timing optimization | REGOUT | std_1c20:inst|cpu:the_cpu|M_alu_result[10]~_DUP_REG | REGOUT
std_1c20:inst|cpu:the_cpu|M_alu_result[10]~_DUP_REG | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|M_alu_result[14] | Duplicated | Physical Synthesis | Timing optimization | REGOUT | std_1c20:inst|cpu:the_cpu|M_alu_result[14]~_DUP_REG | REGOUT
std_1c20:inst|cpu:the_cpu|M_alu_result[14]~_DUP_REG | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|M_alu_result[15] | Duplicated | Physical Synthesis | Timing optimization | REGOUT | std_1c20:inst|cpu:the_cpu|M_alu_result[15]~_DUP_REG | REGOUT
std_1c20:inst|cpu:the_cpu|M_alu_result[16] | Duplicated | Physical Synthesis | Timing optimization | REGOUT | std_1c20:inst|cpu:the_cpu|M_alu_result[16]~_DUP_REG | REGOUT
std_1c20:inst|cpu:the_cpu|M_alu_result[17] | Duplicated | Physical Synthesis | Timing optimization | REGOUT | std_1c20:inst|cpu:the_cpu|M_alu_result[17]~_DUP_REG | REGOUT
std_1c20:inst|cpu:the_cpu|M_alu_result[17]~_DUP_REG | Duplicated | Physical Synthesis | Timing optimization | REGOUT | std_1c20:inst|cpu:the_cpu|M_alu_result[17]~_DUP_REG_DUP_REG | REGOUT
std_1c20:inst|cpu:the_cpu|M_alu_result[17]~_DUP_REG_DUP_REG | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|M_alu_result[18] | Duplicated | Physical Synthesis | Timing optimization | REGOUT | std_1c20:inst|cpu:the_cpu|M_alu_result[18]~_DUP_REG | REGOUT
std_1c20:inst|cpu:the_cpu|M_alu_result[18]~_DUP_REG | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|M_alu_result[19] | Duplicated | Physical Synthesis | Timing optimization | REGOUT | std_1c20:inst|cpu:the_cpu|M_alu_result[19]~_DUP_REG | REGOUT
std_1c20:inst|cpu:the_cpu|M_alu_result[19]~_DUP_REG | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|M_alu_result[20]~319 | Duplicated | Physical Synthesis | Timing optimization | COMBOUT | std_1c20:inst|cpu:the_cpu|M_alu_result[20]~319_DUP_COMB_481 | COMBOUT
std_1c20:inst|cpu:the_cpu|M_alu_result[20]~319 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|M_alu_result[20]~319_DUP_COMB_481 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|M_alu_result[20]~408_BDD68 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|M_alu_result[20]~411_BDD71 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|M_alu_result[20]~470 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|M_alu_result[21]~321 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|M_alu_result[21]~402_BDD61 | Deleted | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|M_alu_result[21]~405_BDD64 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|M_alu_result[22]~337 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|M_alu_result[22]~396_BDD55 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|M_alu_result[23]~335 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|M_alu_result[23]~381_BDD40 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|M_alu_result[23]~382_BDD41 | Deleted | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|M_alu_result[23]~385_BDD44 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|M_alu_result[24]~323 | Duplicated | Physical Synthesis | Timing optimization | COMBOUT | std_1c20:inst|cpu:the_cpu|M_alu_result[24]~323_DUP_COMB_483 | COMBOUT
std_1c20:inst|cpu:the_cpu|M_alu_result[24]~323 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|M_alu_result[24]~323_DUP_COMB_483 | Deleted | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|M_alu_result[24]~375_BDD25 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|M_alu_result[24]~376_BDD26 | Deleted | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|M_alu_result[24]~379_BDD29 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|M_alu_result[24]~467 | Duplicated | Physical Synthesis | Timing optimization | COMBOUT | std_1c20:inst|cpu:the_cpu|M_alu_result[24]~467_DUP_COMB | COMBOUT
std_1c20:inst|cpu:the_cpu|M_alu_result[24]~467 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|M_alu_result[24]~467_DUP_COMB | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|M_alu_result[25]~325 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|M_alu_result[25]~370_BDD20 | Deleted | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|M_alu_result[25]~373_BDD23 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|M_alu_result[25]~465 | Duplicated | Physical Synthesis | Timing optimization | COMBOUT | std_1c20:inst|cpu:the_cpu|M_alu_result[25]~465_DUP_COMB | COMBOUT
std_1c20:inst|cpu:the_cpu|M_alu_result[25]~465 | Duplicated | Physical Synthesis | Timing optimization | COMBOUT | std_1c20:inst|cpu:the_cpu|M_alu_result[25]~465_DUP_COMB_479 | COMBOUT
std_1c20:inst|cpu:the_cpu|M_alu_result[25]~465 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|M_alu_result[25]~465_DUP_COMB | Deleted | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|M_alu_result[25]~465_DUP_COMB_479 | Deleted | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|M_alu_result[25]~466 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|M_alu_result[26]~354_BDD1 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|M_alu_result[28]~366_BDD13 | Deleted | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|M_alu_result[28]~439_BDD486 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|M_alu_result[29]~362_BDD9 | Deleted | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|M_alu_result[29]~447_BDD494 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|M_alu_result[30]~392_BDD51 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|M_alu_result[31]~388_BDD47 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|M_alu_result[31]~389_BDD48 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|M_alu_result[31]~390_BDD49 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|M_ctrl_ld | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|M_ctrl_shift_rot~4 | Duplicated | Physical Synthesis | Timing optimization | REGOUT | std_1c20:inst|cpu:the_cpu|M_ctrl_shift_rot~4_DUP_REG | REGOUT
std_1c20:inst|cpu:the_cpu|M_ctrl_shift_rot~4 | Duplicated | Physical Synthesis | Timing optimization | REGOUT | std_1c20:inst|cpu:the_cpu|M_ctrl_shift_rot~4_DUP_REG_8 | REGOUT
std_1c20:inst|cpu:the_cpu|M_ctrl_shift_rot~4 | Duplicated | Physical Synthesis | Timing optimization | COMBOUT | std_1c20:inst|cpu:the_cpu|M_ctrl_shift_rot~4_DUP_COMB | COMBOUT
std_1c20:inst|cpu:the_cpu|M_ctrl_shift_rot~4 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|M_ctrl_shift_rot~4_DUP_REG_8 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|M_ienable_reg[1] | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|M_ienable_reg[5]~695_BDD506 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|M_ienable_reg[5]~696_BDD507 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|M_iw[3] | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|M_ld_align_sh8 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|M_mem_byte_en[0]~126 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|M_mem_byte_en[0]~126_DUP_COMB | Deleted | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|M_mem_byte_en[0]~140_BDD129 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|M_mem_byte_en[1]~124 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|M_mem_byte_en[1]~124_DUP_COMB | Deleted | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|M_mem_byte_en[1]~132 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|M_mem_byte_en[1]~138_BDD126 | Deleted | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|M_mem_byte_en[2]~122 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|M_mem_byte_en[2]~122_DUP_COMB | Deleted | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|M_mem_byte_en[2]~136_BDD103 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|M_mem_byte_en[3]~120 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|M_mem_byte_en[3]~120_DUP_COMB | Deleted | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|M_mem_byte_en[3]~134_BDD92 | Deleted | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|M_st_data[0] | Duplicated | Physical Synthesis | Timing optimization | COMBOUT | std_1c20:inst|cpu:the_cpu|M_st_data[0]~_DUP_COMB | COMBOUT
std_1c20:inst|cpu:the_cpu|M_st_data[0] | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|M_st_data[1] | Duplicated | Physical Synthesis | Timing optimization | COMBOUT | std_1c20:inst|cpu:the_cpu|M_st_data[1]~_DUP_COMB | COMBOUT
std_1c20:inst|cpu:the_cpu|M_st_data[1] | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|M_st_data[2] | Duplicated | Physical Synthesis | Timing optimization | COMBOUT | std_1c20:inst|cpu:the_cpu|M_st_data[2]~_DUP_COMB | COMBOUT
std_1c20:inst|cpu:the_cpu|M_st_data[2] | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|M_st_data[3] | Duplicated | Physical Synthesis | Timing optimization | COMBOUT | std_1c20:inst|cpu:the_cpu|M_st_data[3]~_DUP_COMB | COMBOUT
std_1c20:inst|cpu:the_cpu|M_st_data[3] | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|M_st_data[4] | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|M_st_data[5] | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|M_st_data[6] | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|M_st_data[7] | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|M_st_data[8]~_DUP_COMB | Deleted | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|M_st_data[8]~_DUP_COMB_116 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|M_st_data[9]~_DUP_COMB | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|M_st_data[9]~_DUP_COMB_119 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|M_st_data[10]~_DUP_COMB | Deleted | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|M_st_data[10]~_DUP_COMB_158 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|M_st_data[11]~_DUP_COMB | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|M_st_data[11]~_DUP_COMB_146 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|M_st_data[12]~_DUP_COMB | Deleted | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|M_st_data[12]~_DUP_COMB_155 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|M_st_data[13]~_DUP_COMB | Deleted | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|M_st_data[13]~_DUP_COMB_152 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|M_st_data[14]~COMBOUT | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|M_st_data[14]~_DUP_COMB | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|M_st_data[14]~_DUP_COMB_149 | Deleted | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|M_st_data[15]~_DUP_COMB | Deleted | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|M_st_data[15]~_DUP_COMB_122 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|M_st_data[16]~COMBOUT | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|M_st_data[18]~COMBOUT | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|M_st_data[20]~COMBOUT | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|M_st_data[20]~_DUP_COMB_128 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|M_st_data[21]~COMBOUT | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|M_st_data[21]~_DUP_COMB_143 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|M_st_data[22]~COMBOUT | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|M_st_data[22]~_DUP_COMB_113 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|M_st_data[23]~COMBOUT | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|M_st_data[23]~_DUP_COMB_125 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|M_st_data[24] | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|M_st_data[25] | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|M_st_data[26] | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|M_st_data[27] | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|M_st_data[28] | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|M_st_data[29] | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|M_st_data[30] | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|M_st_data[31] | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|M_wr_data_unfiltered[4]~3689 | Deleted | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|M_wr_data_unfiltered[4]~3690 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|M_wr_data_unfiltered[5]~3691 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|M_wr_data_unfiltered[6]~3688 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|M_wr_data_unfiltered[7]~3686 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|M_wr_data_unfiltered[8]~3684 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|M_wr_data_unfiltered[9]~3682 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|M_wr_data_unfiltered[10]~3680 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|M_wr_data_unfiltered[12]~3667 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|M_wr_data_unfiltered[12]~3668 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|M_wr_data_unfiltered[13]~3666 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|M_wr_data_unfiltered[14]~3663 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|M_wr_data_unfiltered[14]~3664 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|M_wr_data_unfiltered[15]~3662 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|M_wr_data_unfiltered[16]~3659 | Deleted | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|M_wr_data_unfiltered[16]~3660 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|M_wr_data_unfiltered[17]~3669 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|M_wr_data_unfiltered[17]~3670 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|M_wr_data_unfiltered[18]~3655 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|M_wr_data_unfiltered[18]~3656 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|M_wr_data_unfiltered[19]~3653 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|M_wr_data_unfiltered[19]~3654 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|M_wr_data_unfiltered[20]~3673 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|M_wr_data_unfiltered[21]~3651 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|M_wr_data_unfiltered[22]~3649 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|M_wr_data_unfiltered[23]~3675 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|M_wr_data_unfiltered[24]~3657 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|M_wr_data_unfiltered[26]~3697 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|M_wr_data_unfiltered[27]~3701 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|M_wr_data_unfiltered[28]~3707 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|M_wr_data_unfiltered[29]~3705 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|M_wr_data_unfiltered[30]~3703 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|M_wr_data_unfiltered[30]~3746_BDD118 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|M_wr_data_unfiltered[30]~3747_BDD119 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|M_wr_data_unfiltered[31]~3743_BDD115 | Deleted | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|M_wr_data_unfiltered[31]~3744_BDD116 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|W_wr_data[0] | Duplicated | Physical Synthesis | Timing optimization | COMBOUT | std_1c20:inst|cpu:the_cpu|W_wr_data[0]~_DUP_COMB | COMBOUT
std_1c20:inst|cpu:the_cpu|W_wr_data[0] | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|W_wr_data[1] | Duplicated | Physical Synthesis | Timing optimization | COMBOUT | std_1c20:inst|cpu:the_cpu|W_wr_data[1]~_DUP_COMB | COMBOUT
std_1c20:inst|cpu:the_cpu|W_wr_data[1] | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|W_wr_data[1]~_DUP_COMB | Deleted | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|W_wr_data[2] | Duplicated | Physical Synthesis | Timing optimization | COMBOUT | std_1c20:inst|cpu:the_cpu|W_wr_data[2]~_DUP_COMB | COMBOUT
std_1c20:inst|cpu:the_cpu|W_wr_data[2] | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|W_wr_data[2]~_DUP_COMB | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|W_wr_data[3] | Duplicated | Physical Synthesis | Timing optimization | COMBOUT | std_1c20:inst|cpu:the_cpu|W_wr_data[3]~_DUP_COMB | COMBOUT
std_1c20:inst|cpu:the_cpu|W_wr_data[3] | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|W_wr_data[3]~_DUP_COMB | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|W_wr_data[4] | Duplicated | Physical Synthesis | Timing optimization | COMBOUT | std_1c20:inst|cpu:the_cpu|W_wr_data[4]~_DUP_COMB | COMBOUT
std_1c20:inst|cpu:the_cpu|W_wr_data[4] | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|W_wr_data[4]~_DUP_COMB | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|W_wr_data[5] | Duplicated | Physical Synthesis | Timing optimization | COMBOUT | std_1c20:inst|cpu:the_cpu|W_wr_data[5]~_DUP_COMB | COMBOUT
std_1c20:inst|cpu:the_cpu|W_wr_data[5] | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|W_wr_data[5]~_DUP_COMB | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|W_wr_data[6] | Duplicated | Physical Synthesis | Timing optimization | COMBOUT | std_1c20:inst|cpu:the_cpu|W_wr_data[6]~_DUP_COMB | COMBOUT
std_1c20:inst|cpu:the_cpu|W_wr_data[6] | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|W_wr_data[6]~_DUP_COMB | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|W_wr_data[7] | Duplicated | Physical Synthesis | Timing optimization | COMBOUT | std_1c20:inst|cpu:the_cpu|W_wr_data[7]~_DUP_COMB | COMBOUT
std_1c20:inst|cpu:the_cpu|W_wr_data[7] | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|W_wr_data[14] | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|W_wr_data[16] | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|W_wr_data[17] | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|W_wr_data[18] | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|W_wr_data[19] | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|W_wr_data[20] | Duplicated | Physical Synthesis | Timing optimization | COMBOUT | std_1c20:inst|cpu:the_cpu|W_wr_data[20]~_DUP_COMB | COMBOUT
std_1c20:inst|cpu:the_cpu|W_wr_data[20] | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|W_wr_data[20]~_DUP_COMB | Deleted | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|W_wr_data[21] | Duplicated | Physical Synthesis | Timing optimization | COMBOUT | std_1c20:inst|cpu:the_cpu|W_wr_data[21]~_DUP_COMB | COMBOUT
std_1c20:inst|cpu:the_cpu|W_wr_data[21] | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|W_wr_data[21]~_DUP_COMB | Deleted | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|W_wr_data[22] | Duplicated | Physical Synthesis | Timing optimization | COMBOUT | std_1c20:inst|cpu:the_cpu|W_wr_data[22]~_DUP_COMB | COMBOUT
std_1c20:inst|cpu:the_cpu|W_wr_data[22] | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|W_wr_data[22]~_DUP_COMB | Deleted | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|W_wr_data[23] | Duplicated | Physical Synthesis | Timing optimization | COMBOUT | std_1c20:inst|cpu:the_cpu|W_wr_data[23]~_DUP_COMB | COMBOUT
std_1c20:inst|cpu:the_cpu|W_wr_data[23] | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|W_wr_data[23]~_DUP_COMB | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|W_wr_data[24] | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|W_wr_data[26] | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|W_wr_data[27] | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|W_wr_data[28] | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|W_wr_data[29] | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|W_wr_data[30] | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|av_ld_data_aligned_or_div[0] | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|av_ld_data_aligned_or_div[1] | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|av_ld_data_aligned_or_div[2] | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|av_ld_data_aligned_or_div[4] | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|av_ld_data_aligned_or_div[5] | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|av_ld_data_aligned_or_div[8] | Duplicated | Physical Synthesis | Timing optimization | COMBOUT | std_1c20:inst|cpu:the_cpu|av_ld_data_aligned_or_div[8]~_DUP_COMB | COMBOUT
std_1c20:inst|cpu:the_cpu|av_ld_data_aligned_or_div[8] | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|av_ld_data_aligned_or_div[8]~_DUP_COMB | Deleted | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|av_ld_data_aligned_or_div[9] | Duplicated | Physical Synthesis | Timing optimization | COMBOUT | std_1c20:inst|cpu:the_cpu|av_ld_data_aligned_or_div[9]~_DUP_COMB | COMBOUT
std_1c20:inst|cpu:the_cpu|av_ld_data_aligned_or_div[9] | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|av_ld_data_aligned_or_div[9]~_DUP_COMB | Deleted | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|av_ld_data_aligned_or_div[10] | Duplicated | Physical Synthesis | Timing optimization | COMBOUT | std_1c20:inst|cpu:the_cpu|av_ld_data_aligned_or_div[10]~_DUP_COMB | COMBOUT
std_1c20:inst|cpu:the_cpu|av_ld_data_aligned_or_div[10] | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|av_ld_data_aligned_or_div[10]~_DUP_COMB | Deleted | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|av_ld_data_aligned_or_div[11] | Duplicated | Physical Synthesis | Timing optimization | COMBOUT | std_1c20:inst|cpu:the_cpu|av_ld_data_aligned_or_div[11]~_DUP_COMB | COMBOUT
std_1c20:inst|cpu:the_cpu|av_ld_data_aligned_or_div[12] | Duplicated | Physical Synthesis | Timing optimization | COMBOUT | std_1c20:inst|cpu:the_cpu|av_ld_data_aligned_or_div[12]~_DUP_COMB | COMBOUT
std_1c20:inst|cpu:the_cpu|av_ld_data_aligned_or_div[12] | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|av_ld_data_aligned_or_div[12]~_DUP_COMB | Deleted | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|av_ld_data_aligned_or_div[13] | Duplicated | Physical Synthesis | Timing optimization | COMBOUT | std_1c20:inst|cpu:the_cpu|av_ld_data_aligned_or_div[13]~_DUP_COMB | COMBOUT
std_1c20:inst|cpu:the_cpu|av_ld_data_aligned_or_div[13] | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|av_ld_data_aligned_or_div[13]~_DUP_COMB | Deleted | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|av_ld_data_aligned_or_div[14] | Duplicated | Physical Synthesis | Timing optimization | COMBOUT | std_1c20:inst|cpu:the_cpu|av_ld_data_aligned_or_div[14]~_DUP_COMB | COMBOUT
std_1c20:inst|cpu:the_cpu|av_ld_data_aligned_or_div[15] | Duplicated | Physical Synthesis | Timing optimization | COMBOUT | std_1c20:inst|cpu:the_cpu|av_ld_data_aligned_or_div[15]~_DUP_COMB | COMBOUT
std_1c20:inst|cpu:the_cpu|av_ld_data_aligned_or_div[20]~128 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|av_ld_data_aligned_or_div[21]~127 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|av_ld_data_aligned_or_div[22]~69 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|av_ld_data_aligned_or_div[23]~129 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|av_ld_data_aligned_or_div[24]~130 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|av_ld_data_aligned_or_div[25]~105 | Duplicated | Physical Synthesis | Timing optimization | COMBOUT | std_1c20:inst|cpu:the_cpu|av_ld_data_aligned_or_div[25]~105_DUP_COMB_143 | COMBOUT
std_1c20:inst|cpu:the_cpu|av_ld_data_aligned_or_div[25]~105 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|av_ld_data_aligned_or_div[25]~105_DUP_COMB_143 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|av_ld_data_aligned_or_div[25]~125 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|av_ld_data_aligned_or_div[25]~126 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|av_ld_data_aligned_or_div[25]~131 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|av_ld_data_aligned_or_div[31] | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|av_ld_or_div_done | Duplicated | Physical Synthesis | Timing optimization | REGOUT | std_1c20:inst|cpu:the_cpu|av_ld_or_div_done~_DUP_REG | REGOUT
std_1c20:inst|cpu:the_cpu|av_ld_or_div_done | Duplicated | Physical Synthesis | Timing optimization | REGOUT | std_1c20:inst|cpu:the_cpu|av_ld_or_div_done~_DUP_REG_5 | REGOUT
std_1c20:inst|cpu:the_cpu|av_ld_or_div_done | Duplicated | Physical Synthesis | Timing optimization | COMBOUT | std_1c20:inst|cpu:the_cpu|av_ld_or_div_done~_DUP_COMB | COMBOUT
std_1c20:inst|cpu:the_cpu|av_ld_or_div_done | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|av_ld_or_div_done~_DUP_REG | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|av_ld_or_div_done~_DUP_REG_5 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|cpu_ic_data_module:cpu_ic_data|altsyncram:the_altsyncram|altsyncram_qmb1:auto_generated|q_b[0] | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|cpu_ic_data_module:cpu_ic_data|altsyncram:the_altsyncram|altsyncram_qmb1:auto_generated|q_b[1] | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|cpu_ic_data_module:cpu_ic_data|altsyncram:the_altsyncram|altsyncram_qmb1:auto_generated|q_b[2] | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|cpu_ic_data_module:cpu_ic_data|altsyncram:the_altsyncram|altsyncram_qmb1:auto_generated|q_b[3] | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|cpu_ic_data_module:cpu_ic_data|altsyncram:the_altsyncram|altsyncram_qmb1:auto_generated|q_b[6] | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|cpu_ic_data_module:cpu_ic_data|altsyncram:the_altsyncram|altsyncram_qmb1:auto_generated|q_b[7] | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|cpu_ic_data_module:cpu_ic_data|altsyncram:the_altsyncram|altsyncram_qmb1:auto_generated|q_b[8] | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|cpu_ic_data_module:cpu_ic_data|altsyncram:the_altsyncram|altsyncram_qmb1:auto_generated|q_b[10] | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|cpu_ic_data_module:cpu_ic_data|altsyncram:the_altsyncram|altsyncram_qmb1:auto_generated|q_b[11] | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|cpu_ic_data_module:cpu_ic_data|altsyncram:the_altsyncram|altsyncram_qmb1:auto_generated|q_b[14] | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|cpu_ic_data_module:cpu_ic_data|altsyncram:the_altsyncram|altsyncram_qmb1:auto_generated|q_b[17] | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|cpu_ic_data_module:cpu_ic_data|altsyncram:the_altsyncram|altsyncram_qmb1:auto_generated|q_b[19] | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_avalon_reg:the_cpu_nios2_avalon_reg|Equal0~74_BDD445 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|module_input6~27 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|readdata[4]~1367 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|readdata[5]~1368 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|readdata[6]~1366 | Deleted | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|cpu_register_bank_a_module:cpu_register_bank_a|altsyncram:the_altsyncram|altsyncram_3vd1:auto_generated|q_b[1] | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|cpu_register_bank_a_module:cpu_register_bank_a|altsyncram:the_altsyncram|altsyncram_3vd1:auto_generated|q_b[2] | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|cpu_register_bank_a_module:cpu_register_bank_a|altsyncram:the_altsyncram|altsyncram_3vd1:auto_generated|q_b[3] | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|cpu_register_bank_a_module:cpu_register_bank_a|altsyncram:the_altsyncram|altsyncram_3vd1:auto_generated|q_b[4] | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|cpu_register_bank_a_module:cpu_register_bank_a|altsyncram:the_altsyncram|altsyncram_3vd1:auto_generated|q_b[5] | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|cpu_register_bank_a_module:cpu_register_bank_a|altsyncram:the_altsyncram|altsyncram_3vd1:auto_generated|q_b[6] | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|cpu_register_bank_a_module:cpu_register_bank_a|altsyncram:the_altsyncram|altsyncram_3vd1:auto_generated|q_b[20] | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|cpu_register_bank_a_module:cpu_register_bank_a|altsyncram:the_altsyncram|altsyncram_3vd1:auto_generated|q_b[21] | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|cpu_register_bank_a_module:cpu_register_bank_a|altsyncram:the_altsyncram|altsyncram_3vd1:auto_generated|q_b[22] | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|cpu_register_bank_a_module:cpu_register_bank_a|altsyncram:the_altsyncram|altsyncram_3vd1:auto_generated|q_b[23] | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|cpu_register_bank_b_module:cpu_register_bank_b|altsyncram:the_altsyncram|altsyncram_4vd1:auto_generated|q_b[1] | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|cpu_register_bank_b_module:cpu_register_bank_b|altsyncram:the_altsyncram|altsyncram_4vd1:auto_generated|q_b[2] | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|cpu_register_bank_b_module:cpu_register_bank_b|altsyncram:the_altsyncram|altsyncram_4vd1:auto_generated|q_b[3] | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|cpu_register_bank_b_module:cpu_register_bank_b|altsyncram:the_altsyncram|altsyncram_4vd1:auto_generated|q_b[4] | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|cpu_register_bank_b_module:cpu_register_bank_b|altsyncram:the_altsyncram|altsyncram_4vd1:auto_generated|q_b[5] | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|cpu_register_bank_b_module:cpu_register_bank_b|altsyncram:the_altsyncram|altsyncram_4vd1:auto_generated|q_b[6] | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|cpu_register_bank_b_module:cpu_register_bank_b|altsyncram:the_altsyncram|altsyncram_4vd1:auto_generated|q_b[20] | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|cpu_register_bank_b_module:cpu_register_bank_b|altsyncram:the_altsyncram|altsyncram_4vd1:auto_generated|q_b[21] | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|cpu_register_bank_b_module:cpu_register_bank_b|altsyncram:the_altsyncram|altsyncram_4vd1:auto_generated|q_b[22] | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|cpu_register_bank_b_module:cpu_register_bank_b|altsyncram:the_altsyncram|altsyncram_4vd1:auto_generated|q_b[23] | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|d_readdata_d1[0]~205_BDD351 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|d_readdata_d1[0]~210_BDD562 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|d_readdata_d1[1]~201_BDD307 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|d_readdata_d1[2]~86 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|d_readdata_d1[2]~180_BDD215 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|d_readdata_d1[3]~184_BDD219 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|d_readdata_d1[4]~92 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|d_readdata_d1[5]~90 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|d_readdata_d1[5]~192_BDD227 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|d_readdata_d1[6]~88 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|d_readdata_d1[6]~89 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|d_readdata_d1[6]~188_BDD223 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|d_readdata_d1[7]~112 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|d_readdata_d1[7]~113 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|d_readdata_d1[8]~110 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|d_readdata_d1[11]~116 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|d_readdata_d1[11]~211 | Duplicated | Physical Synthesis | Timing optimization | COMBOUT | std_1c20:inst|cpu:the_cpu|d_readdata_d1[11]~211_DUP_COMB | COMBOUT
std_1c20:inst|cpu:the_cpu|d_readdata_d1[11]~211 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|d_readdata_d1[11]~211_DUP_COMB | Deleted | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|d_readdata_d1[12]~119 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|d_readdata_d1[13]~122 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|d_readdata_d1[14]~125 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|d_readdata_d1[16]~157 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|d_readdata_d1[16]~158 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|d_readdata_d1[17]~148 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|d_readdata_d1[17]~149 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|d_readdata_d1[18]~178 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|d_readdata_d1[18]~179 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|d_readdata_d1[19]~175 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|d_readdata_d1[19]~176 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|d_readdata_d1[20]~142 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|d_readdata_d1[20]~143 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|d_readdata_d1[21]~163 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|d_readdata_d1[21]~164 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|d_readdata_d1[22]~172 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|d_readdata_d1[22]~173 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|d_readdata_d1[23]~169 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|d_readdata_d1[23]~170 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|d_readdata_d1[24]~160 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|d_readdata_d1[24]~161 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|d_readdata_d1[25]~145 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|d_readdata_d1[25]~146 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|d_readdata_d1[26]~136 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|d_readdata_d1[26]~137 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|d_readdata_d1[27]~139 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|d_readdata_d1[27]~140 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|d_readdata_d1[28]~151 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|d_readdata_d1[28]~152 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|d_readdata_d1[29]~154 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|d_readdata_d1[29]~155 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|d_readdata_d1[30]~133 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|d_readdata_d1[30]~134 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|d_readdata_d1[31]~166 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|d_readdata_d1[31]~167 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|i_readdata_d1[0]~90 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|i_readdata_d1[1]~92 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|i_readdata_d1[2]~94 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|i_readdata_d1[2]~178_BDD362 | Deleted | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|i_readdata_d1[2]~179_BDD363 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|i_readdata_d1[3]~182_BDD366 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|i_readdata_d1[3]~183_BDD367 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|i_readdata_d1[4]~87 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|i_readdata_d1[4]~174_BDD358 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|i_readdata_d1[4]~175_BDD359 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|i_readdata_d1[5]~89 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|i_readdata_d1[5]~186_BDD370 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|i_readdata_d1[5]~187_BDD371 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|i_readdata_d1[6]~100 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|i_readdata_d1[6]~169_BDD332 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|i_readdata_d1[6]~170_BDD354 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|i_readdata_d1[6]~171_BDD355 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|i_readdata_d1[7]~160 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|i_readdata_d1[8]~150 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|i_readdata_d1[9]~144 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|i_readdata_d1[10]~140 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|i_readdata_d1[10]~142 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|i_readdata_d1[10]~142_DUP_COMB | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|i_readdata_d1[11]~152 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|i_readdata_d1[12]~154 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|i_readdata_d1[13]~156 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|i_readdata_d1[14]~158 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|i_readdata_d1[15]~147 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|i_readdata_d1[16] | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|i_readdata_d1[17] | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|i_readdata_d1[18] | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|i_readdata_d1[19] | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|i_readdata_d1[20] | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|i_readdata_d1[21] | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|i_readdata_d1[22] | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|i_readdata_d1[23] | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|i_readdata_d1[24] | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|i_readdata_d1[25] | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|i_readdata_d1[26] | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|i_readdata_d1[27] | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|i_readdata_d1[28] | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|i_readdata_d1[29] | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|i_readdata_d1[30] | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|i_readdata_d1[31] | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|ic_fill_active | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|ic_fill_ap_cnt[0]~23 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|ic_fill_ap_cnt[0]~24 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|ic_fill_ap_cnt[0]~24_DUP_COMB_56 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|ic_fill_ap_cnt[0]~25 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|ic_fill_ap_cnt[0]~45 | Duplicated | Physical Synthesis | Timing optimization | COMBOUT | std_1c20:inst|cpu:the_cpu|ic_fill_ap_cnt[0]~45_DUP_COMB_69 | COMBOUT
std_1c20:inst|cpu:the_cpu|ic_fill_ap_cnt[0]~45 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|ic_fill_ap_cnt[0]~45_DUP_COMB_69 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|ic_fill_ap_cnt[0]~50 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|ic_fill_ap_cnt[0]~64 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|ic_fill_ap_cnt[0]~65 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|ic_fill_ap_offset[0] | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|ic_fill_ap_offset[1] | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|ic_fill_ap_offset[2] | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|ic_fill_initial_offset[0] | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|ic_fill_initial_offset[1] | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|ic_fill_initial_offset[2] | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|ic_fill_line[2] | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|ic_fill_line[5] | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|ic_fill_line[6] | Duplicated | Physical Synthesis | Timing optimization | REGOUT | std_1c20:inst|cpu:the_cpu|ic_fill_line[6]~_DUP_REG | REGOUT
std_1c20:inst|cpu:the_cpu|ic_fill_line[6] | Duplicated | Physical Synthesis | Timing optimization | COMBOUT | std_1c20:inst|cpu:the_cpu|ic_fill_line[6]~_DUP_COMB | COMBOUT
std_1c20:inst|cpu:the_cpu|ic_fill_line[6] | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|ic_fill_line[6]~_DUP_COMB | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|ic_fill_line[6]~_DUP_REG | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|ic_fill_req_accepted | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|ic_fill_req_accepted~19_BDD171 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|ic_fill_tag[0]~77 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|ic_fill_tag[0]~112 | Duplicated | Physical Synthesis | Timing optimization | COMBOUT | std_1c20:inst|cpu:the_cpu|ic_fill_tag[0]~112_DUP_COMB_164 | COMBOUT
std_1c20:inst|cpu:the_cpu|ic_fill_tag[0]~112 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|ic_fill_tag[0]~112_DUP_COMB_164 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|ic_fill_tag[1]~78 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|ic_fill_tag[2]~70 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|ic_fill_tag[3]~69 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|ic_fill_tag[4]~68 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|ic_fill_tag[4]~83 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|ic_fill_tag[5]~101 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|ic_fill_tag[6] | Duplicated | Physical Synthesis | Timing optimization | COMBOUT | std_1c20:inst|cpu:the_cpu|ic_fill_tag[6]~_DUP_COMB | COMBOUT
std_1c20:inst|cpu:the_cpu|ic_fill_tag[6] | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|ic_fill_tag[6]~79 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|ic_fill_tag[6]~156 | Duplicated | Physical Synthesis | Timing optimization | REGOUT | std_1c20:inst|cpu:the_cpu|ic_fill_tag[6]~156_DUP_REG | REGOUT
std_1c20:inst|cpu:the_cpu|ic_fill_tag[6]~156 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|ic_fill_tag[6]~156_DUP_REG | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|ic_fill_tag[7] | Duplicated | Physical Synthesis | Timing optimization | COMBOUT | std_1c20:inst|cpu:the_cpu|ic_fill_tag[7]~_DUP_COMB | COMBOUT
std_1c20:inst|cpu:the_cpu|ic_fill_tag[7] | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|ic_fill_tag[8]~87 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|ic_fill_tag[9] | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|ic_fill_tag[9]~81 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|ic_fill_tag[9]~85 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|ic_fill_tag[9]~108 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|ic_fill_tag[9]~109 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|ic_fill_tag[9]~157 | Duplicated | Physical Synthesis | Timing optimization | REGOUT | std_1c20:inst|cpu:the_cpu|ic_fill_tag[9]~157_DUP_REG | REGOUT
std_1c20:inst|cpu:the_cpu|ic_fill_tag[9]~157 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|ic_fill_tag[9]~157_DUP_REG | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|ic_fill_tag[10] | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|ic_fill_tag[11]~66 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|ic_fill_tag[12]~65 | Duplicated | Physical Synthesis | Timing optimization | COMBOUT | std_1c20:inst|cpu:the_cpu|ic_fill_tag[12]~65_DUP_COMB | COMBOUT
std_1c20:inst|cpu:the_cpu|ic_fill_tag[12]~65 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|ic_fill_tag[12]~65_DUP_COMB | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|ic_fill_tag[12]~158 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|ic_fill_tag[13]~67 | Duplicated | Physical Synthesis | Timing optimization | COMBOUT | std_1c20:inst|cpu:the_cpu|ic_fill_tag[13]~67_DUP_COMB | COMBOUT
std_1c20:inst|cpu:the_cpu|ic_fill_tag[13]~67 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|ic_fill_tag[13]~67_DUP_COMB | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|ic_tag_wraddress[1] | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|ic_tag_wraddress[2] | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|ic_tag_wraddress[3] | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|ic_tag_wraddress[4] | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|ic_tag_wraddress[5] | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|ic_tag_wraddress[6] | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|internal_d_read | Duplicated | Physical Synthesis | Timing optimization | COMBOUT | std_1c20:inst|cpu:the_cpu|internal_d_read~_DUP_COMB | COMBOUT
std_1c20:inst|cpu:the_cpu|internal_d_read | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|internal_d_read~_DUP_COMB | Deleted | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|internal_d_write~67 | Duplicated | Physical Synthesis | Timing optimization | COMBOUT | std_1c20:inst|cpu:the_cpu|internal_d_write~67_DUP_COMB | COMBOUT
std_1c20:inst|cpu:the_cpu|internal_d_write~67 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|internal_d_write~67_DUP_COMB | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|internal_d_write~68 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|internal_d_write~69 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|internal_d_write~69_DUP_COMB_80 | Deleted | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|internal_d_write~71 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|internal_d_write~78 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|A_WE_StdLogicVector~1427 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|A_WE_StdLogicVector~1434 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|A_WE_StdLogicVector~1435 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|A_WE_StdLogicVector~1451_BDD170 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[0]~5323 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[1]~5331 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[1]~5338 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[1]~5386_BDD428 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[2]~5166 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[2]~5390_BDD436 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[4]~5203 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[4]~5306 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[4]~5387_BDD429 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[5]~5337 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[7]~5340_BDD231 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[8]~5291 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[8]~5352_BDD374 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[9]~5171 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[9]~5285 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[10]~5275 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[10]~5336 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[11]~5265 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[11]~5391_BDD579 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[12]~5224 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[12]~5247 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[12]~5355_BDD397 | Deleted | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[13]~5238 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[14]~5226 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[15]~5197 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[16]~5370_BDD412 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[17]~5376_BDD418 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[18]~5174 | Deleted | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[18]~5176 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[18]~5356_BDD398 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[19]~5189 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[19]~5358_BDD400 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[20]~5380_BDD422 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[21]~5216 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[21]~5366_BDD408 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[22]~5191 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[22]~5360_BDD402 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[23]~5362_BDD404 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[24]~5368_BDD410 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[25]~5378_BDD420 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[26]~5384_BDD426 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[27]~5382_BDD424 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[28]~5374_BDD416 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[29]~5372_BDD414 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[30]~5232 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[31]~5364_BDD406 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata~205 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata~206 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata~211 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata~568 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata~772 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata~775 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|internal_cpu_data_master_dbs_address[1]~55 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|internal_cpu_data_master_dbs_address[1]~65 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|internal_cpu_data_master_dbs_address[1]~66 | Duplicated | Physical Synthesis | Timing optimization | COMBOUT | std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|internal_cpu_data_master_dbs_address[1]~66_DUP_COMB | COMBOUT
std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|internal_cpu_data_master_dbs_address[1]~66 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|internal_cpu_data_master_dbs_address[1]~66_DUP_COMB | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|internal_cpu_data_master_dbs_address[1]~67 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|internal_cpu_data_master_dbs_address[1]~68 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|internal_cpu_data_master_dbs_address[1]~81 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|internal_cpu_data_master_waitrequest | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|internal_cpu_data_master_waitrequest~_DUP_COMB | Deleted | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|p1_registered_cpu_data_master_readdata[18]~2029 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|p1_registered_cpu_data_master_readdata[19]~2033 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|p1_registered_cpu_data_master_readdata[20]~2065 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|p1_registered_cpu_data_master_readdata[21]~2045 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|p1_registered_cpu_data_master_readdata[22]~2035 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|p1_registered_cpu_data_master_readdata[24]~2047 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|p1_registered_cpu_data_master_readdata[25]~2063 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|p1_registered_cpu_data_master_readdata[26]~2073 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|p1_registered_cpu_data_master_readdata[27]~2069 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|p1_registered_cpu_data_master_readdata[28]~2060 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|p1_registered_cpu_data_master_readdata[29]~2056 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|p1_registered_cpu_data_master_readdata[30]~2052 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|p1_registered_cpu_data_master_readdata[31]~2043 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_read_but_no_slave_selected~56 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_read_but_no_slave_selected~59 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_read_but_no_slave_selected~59_DUP_COMB | Deleted | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_read_but_no_slave_selected~61 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_read_but_no_slave_selected~62 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_readdata[9]~2541_BDD341 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_readdata[9]~2542_BDD342 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_readdata[10]~2546_BDD346 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_readdata[10]~2547_BDD347 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_readdata[15]~2536_BDD336 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_readdata[15]~2537_BDD337 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_readdata[16]~2491 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_readdata[17]~2533 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_readdata[18]~2526 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_readdata[19]~2522 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_readdata[20]~2518 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_readdata[21]~2487 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_readdata[22]~2498 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_readdata[23]~2502 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_readdata[24]~2506 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_readdata[25]~2510 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_readdata[26]~2514 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_readdata[27]~2451 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_readdata[28]~2455 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_readdata[29]~2459 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_readdata[30]~2463 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_readdata[31]~2467 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_readdatavalid~147 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_readdatavalid~150 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_run~170 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_run~175_BDD153 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_run~176_BDD154 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_run~178_BDD246 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|internal_cpu_instruction_master_dbs_address[0] | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|internal_cpu_instruction_master_dbs_address[1]~49 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|internal_cpu_instruction_master_dbs_address[1]~50 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|internal_cpu_instruction_master_dbs_address[1]~53_BDD193 | Deleted | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|internal_cpu_instruction_master_latency_counter[0] | Duplicated | Physical Synthesis | Timing optimization | COMBOUT | std_1c20:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|internal_cpu_instruction_master_latency_counter[0]~_DUP_COMB | COMBOUT
std_1c20:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|internal_cpu_instruction_master_latency_counter[0] | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|internal_cpu_instruction_master_latency_counter[0]~27_BDD573 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|internal_cpu_instruction_master_latency_counter[0]~_DUP_COMB | Deleted | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|internal_cpu_instruction_master_latency_counter[1]~25 | Duplicated | Physical Synthesis | Timing optimization | COMBOUT | std_1c20:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|internal_cpu_instruction_master_latency_counter[1]~25_DUP_COMB | COMBOUT
std_1c20:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|internal_cpu_instruction_master_latency_counter[1]~25 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|internal_cpu_instruction_master_latency_counter[1]~25_DUP_COMB | Deleted | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|r_0~69_BDD123 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|r_0~71_BDD592 | Deleted | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|r_0~72_BDD624 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|r_1~20 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|r_1~293 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu_jtag_debug_module_arbitrator:the_cpu_jtag_debug_module|Add2~348_BDD430 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu_jtag_debug_module_arbitrator:the_cpu_jtag_debug_module|cpu_data_master_granted_cpu_jtag_debug_module~64 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu_jtag_debug_module_arbitrator:the_cpu_jtag_debug_module|cpu_data_master_requests_cpu_jtag_debug_module~274 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu_jtag_debug_module_arbitrator:the_cpu_jtag_debug_module|cpu_jtag_debug_module_address[0]~98 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu_jtag_debug_module_arbitrator:the_cpu_jtag_debug_module|cpu_jtag_debug_module_address[1]~99_BDD250 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu_jtag_debug_module_arbitrator:the_cpu_jtag_debug_module|cpu_jtag_debug_module_arb_addend[0]~756 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu_jtag_debug_module_arbitrator:the_cpu_jtag_debug_module|cpu_jtag_debug_module_arb_addend[0]~757 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu_jtag_debug_module_arbitrator:the_cpu_jtag_debug_module|cpu_jtag_debug_module_arb_addend[0]~760 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu_jtag_debug_module_arbitrator:the_cpu_jtag_debug_module|cpu_jtag_debug_module_arb_addend[1]~752_DUP_COMB | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu_jtag_debug_module_arbitrator:the_cpu_jtag_debug_module|cpu_jtag_debug_module_arb_addend[1]~761 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu_jtag_debug_module_arbitrator:the_cpu_jtag_debug_module|cpu_jtag_debug_module_arb_addend[1]~762 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu_jtag_debug_module_arbitrator:the_cpu_jtag_debug_module|cpu_jtag_debug_module_arb_addend[1]~763 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu_jtag_debug_module_arbitrator:the_cpu_jtag_debug_module|cpu_jtag_debug_module_begintransfer~58 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu_jtag_debug_module_arbitrator:the_cpu_jtag_debug_module|cpu_jtag_debug_module_saved_chosen_master_vector[0] | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu_jtag_debug_module_arbitrator:the_cpu_jtag_debug_module|cpu_jtag_debug_module_saved_chosen_master_vector[0]~_DUP_COMB | Deleted | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu_jtag_debug_module_arbitrator:the_cpu_jtag_debug_module|d1_reasons_to_wait | Duplicated | Physical Synthesis | Timing optimization | COMBOUT | std_1c20:inst|cpu_jtag_debug_module_arbitrator:the_cpu_jtag_debug_module|d1_reasons_to_wait~_DUP_COMB | COMBOUT
std_1c20:inst|cpu_jtag_debug_module_arbitrator:the_cpu_jtag_debug_module|d1_reasons_to_wait | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu_jtag_debug_module_arbitrator:the_cpu_jtag_debug_module|d1_reasons_to_wait~_DUP_COMB | Deleted | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu_jtag_debug_module_arbitrator:the_cpu_jtag_debug_module|internal_cpu_instruction_master_qualified_request_cpu_jtag_debug_module~44 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|epcs_controller:the_epcs_controller|altsyncram:the_boot_copier_rom|altsyncram_3h31:auto_generated|q_a[0] | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|epcs_controller:the_epcs_controller|altsyncram:the_boot_copier_rom|altsyncram_3h31:auto_generated|q_a[1] | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|epcs_controller:the_epcs_controller|altsyncram:the_boot_copier_rom|altsyncram_3h31:auto_generated|q_a[2] | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|epcs_controller:the_epcs_controller|altsyncram:the_boot_copier_rom|altsyncram_3h31:auto_generated|q_a[3] | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|epcs_controller:the_epcs_controller|altsyncram:the_boot_copier_rom|altsyncram_3h31:auto_generated|q_a[4] | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|epcs_controller:the_epcs_controller|altsyncram:the_boot_copier_rom|altsyncram_3h31:auto_generated|q_a[5] | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|epcs_controller:the_epcs_controller|altsyncram:the_boot_copier_rom|altsyncram_3h31:auto_generated|q_a[6] | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|epcs_controller:the_epcs_controller|altsyncram:the_boot_copier_rom|altsyncram_3h31:auto_generated|q_a[7] | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|epcs_controller:the_epcs_controller|altsyncram:the_boot_copier_rom|altsyncram_3h31:auto_generated|q_a[8] | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|epcs_controller:the_epcs_controller|altsyncram:the_boot_copier_rom|altsyncram_3h31:auto_generated|q_a[9] | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|epcs_controller:the_epcs_controller|altsyncram:the_boot_copier_rom|altsyncram_3h31:auto_generated|q_a[10] | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|epcs_controller:the_epcs_controller|altsyncram:the_boot_copier_rom|altsyncram_3h31:auto_generated|q_a[11] | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|epcs_controller:the_epcs_controller|altsyncram:the_boot_copier_rom|altsyncram_3h31:auto_generated|q_a[12] | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|epcs_controller:the_epcs_controller|altsyncram:the_boot_copier_rom|altsyncram_3h31:auto_generated|q_a[13] | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|epcs_controller:the_epcs_controller|altsyncram:the_boot_copier_rom|altsyncram_3h31:auto_generated|q_a[14] | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|epcs_controller:the_epcs_controller|altsyncram:the_boot_copier_rom|altsyncram_3h31:auto_generated|q_a[15] | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|epcs_controller:the_epcs_controller|altsyncram:the_boot_copier_rom|altsyncram_3h31:auto_generated|q_a[16] | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|epcs_controller:the_epcs_controller|altsyncram:the_boot_copier_rom|altsyncram_3h31:auto_generated|q_a[17] | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|epcs_controller:the_epcs_controller|altsyncram:the_boot_copier_rom|altsyncram_3h31:auto_generated|q_a[18] | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|epcs_controller:the_epcs_controller|altsyncram:the_boot_copier_rom|altsyncram_3h31:auto_generated|q_a[19] | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|epcs_controller:the_epcs_controller|altsyncram:the_boot_copier_rom|altsyncram_3h31:auto_generated|q_a[20] | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|epcs_controller:the_epcs_controller|altsyncram:the_boot_copier_rom|altsyncram_3h31:auto_generated|q_a[21] | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|epcs_controller:the_epcs_controller|altsyncram:the_boot_copier_rom|altsyncram_3h31:auto_generated|q_a[22] | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|epcs_controller:the_epcs_controller|altsyncram:the_boot_copier_rom|altsyncram_3h31:auto_generated|q_a[23] | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|epcs_controller:the_epcs_controller|altsyncram:the_boot_copier_rom|altsyncram_3h31:auto_generated|q_a[24] | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|epcs_controller:the_epcs_controller|altsyncram:the_boot_copier_rom|altsyncram_3h31:auto_generated|q_a[25] | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|epcs_controller:the_epcs_controller|altsyncram:the_boot_copier_rom|altsyncram_3h31:auto_generated|q_a[26] | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|epcs_controller:the_epcs_controller|altsyncram:the_boot_copier_rom|altsyncram_3h31:auto_generated|q_a[27] | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|epcs_controller:the_epcs_controller|altsyncram:the_boot_copier_rom|altsyncram_3h31:auto_generated|q_a[28] | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|epcs_controller:the_epcs_controller|altsyncram:the_boot_copier_rom|altsyncram_3h31:auto_generated|q_a[29] | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|epcs_controller:the_epcs_controller|altsyncram:the_boot_copier_rom|altsyncram_3h31:auto_generated|q_a[30] | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|epcs_controller:the_epcs_controller|altsyncram:the_boot_copier_rom|altsyncram_3h31:auto_generated|q_a[31] | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|A_WE_StdLogicVector~1120 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|A_WE_StdLogicVector~1127 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|A_WE_StdLogicVector~1129 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|A_WE_StdLogicVector~1130 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|A_WE_StdLogicVector~1132 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|A_WE_StdLogicVector~1133 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|A_WE_StdLogicVector~1135 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|A_WE_StdLogicVector~1137_BDD395 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|A_WE_StdLogicVector~1138_BDD619 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|A_WE_StdLogicVector~1139_BDD622 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|A_WE_StdLogicVector~1140_BDD623 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|EOP~170 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|EOP~175 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|EOP~176 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|Equal0~142 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|RRDY | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|TOE | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|control_wr_strobe | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|data_rd_strobe | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|data_to_cpu[0]~38 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|data_to_cpu[0]~38_DUP_COMB | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|data_to_cpu[0]~49 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|data_to_cpu[1] | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|data_to_cpu[2] | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|data_to_cpu[5]~33 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|data_to_cpu[5]~52_BDD150 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|data_to_cpu[5]~53_BDD151 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|data_to_cpu[11] | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|data_to_cpu[12] | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|data_to_cpu[13] | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|data_to_cpu[14] | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|data_to_cpu[15] | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|data_wr_strobe | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|endofpacketvalue_wr_strobe | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|rd_strobe | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|rd_strobe~_DUP_COMB | Deleted | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|rx_holding_reg[3] | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|rx_holding_reg[4] | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|rx_holding_reg[6] | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|rx_holding_reg[7] | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|slaveselect_wr_strobe | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|tx_holding_primed | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|wr_strobe | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|wr_strobe~_DUP_COMB | Deleted | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|write_tx_holding | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|epcs_controller_epcs_control_port_arbitrator:the_epcs_controller_epcs_control_port|Add2~344 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|epcs_controller_epcs_control_port_arbitrator:the_epcs_controller_epcs_control_port|Add2~345_BDD587 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|epcs_controller_epcs_control_port_arbitrator:the_epcs_controller_epcs_control_port|cpu_data_master_granted_epcs_controller_epcs_control_port~33 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|epcs_controller_epcs_control_port_arbitrator:the_epcs_controller_epcs_control_port|cpu_instruction_master_granted_epcs_controller_epcs_control_port | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|epcs_controller_epcs_control_port_arbitrator:the_epcs_controller_epcs_control_port|cpu_instruction_master_granted_epcs_controller_epcs_control_port~91 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|epcs_controller_epcs_control_port_arbitrator:the_epcs_controller_epcs_control_port|cpu_instruction_master_qualified_request_epcs_controller_epcs_control_port | Duplicated | Physical Synthesis | Timing optimization | COMBOUT | std_1c20:inst|epcs_controller_epcs_control_port_arbitrator:the_epcs_controller_epcs_control_port|cpu_instruction_master_qualified_request_epcs_controller_epcs_control_port~_DUP_COMB | COMBOUT
std_1c20:inst|epcs_controller_epcs_control_port_arbitrator:the_epcs_controller_epcs_control_port|cpu_instruction_master_qualified_request_epcs_controller_epcs_control_port | Deleted | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|epcs_controller_epcs_control_port_arbitrator:the_epcs_controller_epcs_control_port|cpu_instruction_master_qualified_request_epcs_controller_epcs_control_port~_DUP_COMB | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|epcs_controller_epcs_control_port_arbitrator:the_epcs_controller_epcs_control_port|d1_reasons_to_wait~14_BDD451 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|epcs_controller_epcs_control_port_arbitrator:the_epcs_controller_epcs_control_port|epcs_controller_epcs_control_port_address[0]~74_BDD268 | Deleted | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|epcs_controller_epcs_control_port_arbitrator:the_epcs_controller_epcs_control_port|epcs_controller_epcs_control_port_address[1]~69 | Deleted | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|epcs_controller_epcs_control_port_arbitrator:the_epcs_controller_epcs_control_port|epcs_controller_epcs_control_port_address[1]~75_BDD563 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|epcs_controller_epcs_control_port_arbitrator:the_epcs_controller_epcs_control_port|epcs_controller_epcs_control_port_address[5]~72 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|epcs_controller_epcs_control_port_arbitrator:the_epcs_controller_epcs_control_port|epcs_controller_epcs_control_port_begins_xfer~59 | Deleted | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|A_WE_StdLogicVector~4277 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|A_WE_StdLogicVector~4288 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|A_WE_StdLogicVector~4296_BDD300 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|Add2~308 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|Add2~310 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|Add2~318 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|byteenablen_to_the_lan91c111[0]~COMB_OUT | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|byteenablen_to_the_lan91c111[1]~COMB_OUT | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|byteenablen_to_the_lan91c111[2]~COMB_OUT | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|byteenablen_to_the_lan91c111[3]~COMB_OUT | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|cpu_data_master_continuerequest~103 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|cpu_data_master_qualified_request_ext_flash_s1~151 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|cpu_data_master_qualified_request_lan91c111_s1~128 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|cpu_data_master_qualified_request_lan91c111_s1~128 | Duplicated | Physical Synthesis | Timing optimization | COMBOUT | std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|cpu_data_master_qualified_request_lan91c111_s1~128_DUP_COMB | COMBOUT
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|cpu_data_master_qualified_request_lan91c111_s1~128 | Duplicated | Physical Synthesis | Timing optimization | COMBOUT | std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|cpu_data_master_qualified_request_lan91c111_s1~128_DUP_COMB_133 | COMBOUT
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|cpu_data_master_qualified_request_lan91c111_s1~128 | Deleted | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|cpu_data_master_qualified_request_lan91c111_s1~128_DUP_COMB_133 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|cpu_data_master_qualified_request_lan91c111_s1~129 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|cpu_data_master_read_data_valid_ext_flash_s1_shift_register[0] | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|cpu_data_master_read_data_valid_ext_flash_s1_shift_register[0]~_DUP_COMB | Deleted | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|cpu_data_master_read_data_valid_ext_flash_s1_shift_register[1] | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|cpu_data_master_read_data_valid_ext_ram_s1_shift_register[0] | Duplicated | Physical Synthesis | Timing optimization | COMBOUT | std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|cpu_data_master_read_data_valid_ext_ram_s1_shift_register[0]~_DUP_COMB | COMBOUT
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|cpu_data_master_read_data_valid_ext_ram_s1_shift_register[0] | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|cpu_data_master_read_data_valid_ext_ram_s1_shift_register[0]~22 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|cpu_data_master_read_data_valid_ext_ram_s1_shift_register[0]~_DUP_COMB | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|cpu_data_master_read_data_valid_ext_ram_s1_shift_register[1] | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|cpu_data_master_read_data_valid_lan91c111_s1_shift_register[0] | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|cpu_data_master_read_data_valid_lan91c111_s1_shift_register[1] | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|cpu_instruction_master_continuerequest~64_BDD569 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|cpu_instruction_master_continuerequest~66_BDD613 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|cpu_instruction_master_continuerequest~72_BDD629 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|cpu_instruction_master_read_data_valid_ext_flash_s1_shift_register[0] | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|cpu_instruction_master_read_data_valid_lan91c111_s1_shift_register_in~17_BDD172 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|cpu_instruction_master_read_data_valid_lan91c111_s1_shift_register_in~18_BDD173 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|cpu_instruction_master_requests_ext_flash_s1~35 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_ext_ram_bus_avalon_slave_end_xfer~3 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_ext_ram_bus_avalon_slave_end_xfer~3_DUP_COMB_12 | Deleted | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_ext_ram_bus_avalon_slave_end_xfer~4 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_ext_ram_bus_avalon_slave_end_xfer~4_DUP_COMB | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_ext_ram_bus_avalon_slave_end_xfer~5 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_ext_ram_bus_avalon_slave_end_xfer~5_DUP_COMB | Deleted | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_ext_ram_bus_avalon_slave_end_xfer~7 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_ext_ram_bus_avalon_slave_end_xfer~8 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_in_a_write_cycle~3_BDD618 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_in_a_write_cycle~COMB_OUT | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_outgoing_ext_ram_bus_data[8]~COMB_OUT | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_outgoing_ext_ram_bus_data[9]~COMB_OUT | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_outgoing_ext_ram_bus_data[10]~COMB_OUT | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_outgoing_ext_ram_bus_data[11]~COMB_OUT | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_outgoing_ext_ram_bus_data[12]~COMB_OUT | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_outgoing_ext_ram_bus_data[13]~COMB_OUT | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_outgoing_ext_ram_bus_data[14]~COMB_OUT | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_outgoing_ext_ram_bus_data[15]~COMB_OUT | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_outgoing_ext_ram_bus_data[16]~COMB_OUT | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_outgoing_ext_ram_bus_data[17]~COMB_OUT | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_outgoing_ext_ram_bus_data[18]~COMB_OUT | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_outgoing_ext_ram_bus_data[19]~COMB_OUT | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_outgoing_ext_ram_bus_data[20]~COMB_OUT | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_outgoing_ext_ram_bus_data[21]~COMB_OUT | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_outgoing_ext_ram_bus_data[22]~COMB_OUT | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_outgoing_ext_ram_bus_data[23]~COMB_OUT | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_outgoing_ext_ram_bus_data[24]~COMB_OUT | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_outgoing_ext_ram_bus_data[25]~COMB_OUT | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_outgoing_ext_ram_bus_data[26]~COMB_OUT | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_outgoing_ext_ram_bus_data[27]~COMB_OUT | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_outgoing_ext_ram_bus_data[28]~COMB_OUT | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_outgoing_ext_ram_bus_data[29]~COMB_OUT | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_outgoing_ext_ram_bus_data[30]~COMB_OUT | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_outgoing_ext_ram_bus_data[31]~COMB_OUT | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_flash_s1_wait_counter[0]~96 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_flash_s1_wait_counter[1] | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_flash_s1_wait_counter[2]~91 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_flash_s1_wait_counter[3]~86 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_flash_s1_wait_counter[3]~87 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_flash_s1_wait_counter[3]~89 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_address[2]~COMB_OUT | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_address[3]~COMB_OUT | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_address[4]~COMB_OUT | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_address[5]~COMB_OUT | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_address[7]~COMB_OUT | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_address[8]~COMB_OUT | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_address[9]~COMB_OUT | Duplicated | Physical Synthesis | Timing optimization | COMBOUT | std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_address[9]~COMB_OUT_DUP_COMB | COMBOUT
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_address[9]~COMB_OUT | Deleted | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_address[9]~COMB_OUT_DUP_COMB | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_address[10]~COMB_OUT | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_address[12]~COMB_OUT | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_address[13]~COMB_OUT | Duplicated | Physical Synthesis | Timing optimization | COMBOUT | std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_address[13]~COMB_OUT_DUP_COMB | COMBOUT
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_address[13]~COMB_OUT | Deleted | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_address[14]~COMB_OUT | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_address[17]~46_BDD251 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_address[17]~48_BDD253 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_address[17]~COMB_OUT | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_address[20]~COMB_OUT | Duplicated | Physical Synthesis | Timing optimization | COMBOUT | std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_address[20]~COMB_OUT_DUP_COMB | COMBOUT
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_address[20]~COMB_OUT | Deleted | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_address[20]~COMB_OUT_DUP_COMB | Duplicated | Physical Synthesis | Timing optimization | COMBOUT | std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_address[20]~COMB_OUT_DUP_COMB_DUP_COMB | COMBOUT
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_address[20]~COMB_OUT_DUP_COMB | Deleted | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_address[20]~COMB_OUT_DUP_COMB_DUP_COMB | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_address[22]~50_BDD275 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_avalon_slave_arb_addend[0]~742 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_avalon_slave_arb_addend[0]~751 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_avalon_slave_arb_addend[0]~751_DUP_COMB | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_avalon_slave_arb_addend[0]~752 | Deleted | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_avalon_slave_arb_addend[0]~753 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_avalon_slave_arb_addend[0]~753_DUP_COMB | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_avalon_slave_arb_addend[0]~755 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_avalon_slave_arb_addend[0]~755_DUP_COMB | Deleted | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_avalon_slave_arb_addend[0]~759 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_avalon_slave_arb_addend[0]~759_DUP_COMB | Deleted | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_avalon_slave_arb_addend[0]~761 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_avalon_slave_arb_addend[0]~761_DUP_COMB | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_avalon_slave_arb_addend[0]~763 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_avalon_slave_arb_addend[0]~763_DUP_COMB | Deleted | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_avalon_slave_arb_addend[0]~764 | Deleted | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_avalon_slave_arb_addend[0]~765 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_avalon_slave_arb_addend[0]~765_DUP_COMB | Deleted | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_avalon_slave_arb_addend[0]~795 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_avalon_slave_arb_addend[0]~796 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_avalon_slave_arb_addend[0]~803 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_avalon_slave_arb_addend[0]~806 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_avalon_slave_arb_addend[0]~809 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_avalon_slave_arb_addend[0]~826_BDD89 | Deleted | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_avalon_slave_arb_addend[0]~827_BDD90 | Deleted | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_avalon_slave_arb_addend[0]~838_BDD145 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_avalon_slave_arb_addend[0]~839_BDD453 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_avalon_slave_arb_addend[0]~840_BDD454 | Deleted | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_avalon_slave_arb_addend[0]~841_BDD601 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_avalon_slave_arb_addend[0]~842_BDD602 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_avalon_slave_arb_addend[0]~869 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_avalon_slave_arb_addend[0]~871 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_avalon_slave_arb_addend[0]~873 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_avalon_slave_arb_addend[0]~875 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_avalon_slave_arb_addend[0]~876 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_avalon_slave_arb_addend[0]~956 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_avalon_slave_arb_addend[1]~720 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_avalon_slave_arb_addend[1]~720_DUP_COMB | Deleted | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_avalon_slave_arb_addend[2]~711 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_avalon_slave_arb_addend[2]~711_DUP_COMB | Deleted | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_avalon_slave_arb_addend[3]~850 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_avalon_slave_arb_addend[3]~867 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_avalon_slave_arb_addend[4]~707 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_avalon_slave_arb_addend[4]~707_DUP_COMB | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_avalon_slave_arb_addend[4]~844 | Duplicated | Physical Synthesis | Timing optimization | COMBOUT | std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_avalon_slave_arb_addend[4]~844_DUP_COMB | COMBOUT
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_avalon_slave_arb_addend[4]~844 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_avalon_slave_arb_addend[4]~844_DUP_COMB | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_avalon_slave_arb_addend[4]~846 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_avalon_slave_arb_addend[4]~864 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_avalon_slave_arb_addend[4]~957 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_avalon_slave_arb_addend[4]~960 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_avalon_slave_arb_addend[4]~961 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_avalon_slave_arb_addend[5]~848 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_avalon_slave_arb_addend[5]~865 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_avalon_slave_arb_share_counter[0]~597 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_avalon_slave_arb_share_counter[0]~603 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_avalon_slave_arb_share_counter[0]~604 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_avalon_slave_arb_share_counter[0]~605 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_avalon_slave_arb_share_counter[0]~608 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_avalon_slave_arb_share_counter[1]~601 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_avalon_slave_arb_winner~40_BDD469 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_avalon_slave_begins_xfer | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_avalon_slave_end_xfer~81 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_avalon_slave_saved_chosen_master_vector[0]~669 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_avalon_slave_saved_chosen_master_vector[0]~670 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_avalon_slave_saved_chosen_master_vector[0]~673 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_avalon_slave_saved_chosen_master_vector[0]~673_DUP_COMB | Deleted | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_avalon_slave_saved_chosen_master_vector[0]~707 | Duplicated | Physical Synthesis | Timing optimization | COMBOUT | std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_avalon_slave_saved_chosen_master_vector[0]~707_DUP_COMB_758 | COMBOUT
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_avalon_slave_saved_chosen_master_vector[0]~707 | Duplicated | Physical Synthesis | Timing optimization | COMBOUT | std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_avalon_slave_saved_chosen_master_vector[0]~707_DUP_COMB_760 | COMBOUT
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_avalon_slave_saved_chosen_master_vector[0]~707 | Duplicated | Physical Synthesis | Timing optimization | COMBOUT | std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_avalon_slave_saved_chosen_master_vector[0]~707_DUP_COMB_762 | COMBOUT
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_avalon_slave_saved_chosen_master_vector[0]~707 | Duplicated | Physical Synthesis | Timing optimization | COMBOUT | std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_avalon_slave_saved_chosen_master_vector[0]~707_DUP_COMB_764 | COMBOUT
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_avalon_slave_saved_chosen_master_vector[0]~707 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_avalon_slave_saved_chosen_master_vector[0]~707_DUP_COMB_758 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_avalon_slave_saved_chosen_master_vector[0]~707_DUP_COMB_760 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_avalon_slave_saved_chosen_master_vector[0]~707_DUP_COMB_762 | Deleted | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_avalon_slave_saved_chosen_master_vector[0]~707_DUP_COMB_764 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_avalon_slave_saved_chosen_master_vector[0]~708 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_avalon_slave_saved_chosen_master_vector[0]~745 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_avalon_slave_saved_chosen_master_vector[1]~660 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_avalon_slave_saved_chosen_master_vector[1]~661 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_avalon_slave_saved_chosen_master_vector[1]~671 | Duplicated | Physical Synthesis | Timing optimization | COMBOUT | std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_avalon_slave_saved_chosen_master_vector[1]~671_DUP_COMB | COMBOUT
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_avalon_slave_saved_chosen_master_vector[1]~671 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_avalon_slave_saved_chosen_master_vector[1]~671_DUP_COMB | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_avalon_slave_saved_chosen_master_vector[1]~706 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_avalon_slave_saved_chosen_master_vector[1]~748 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_avalon_slave_saved_chosen_master_vector[2]~666 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_avalon_slave_saved_chosen_master_vector[2]~667 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_avalon_slave_saved_chosen_master_vector[2]~677 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_avalon_slave_saved_chosen_master_vector[2]~680 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_avalon_slave_saved_chosen_master_vector[2]~688 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_avalon_slave_saved_chosen_master_vector[2]~691 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_avalon_slave_saved_chosen_master_vector[3]~657 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_avalon_slave_saved_chosen_master_vector[3]~658 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_avalon_slave_saved_chosen_master_vector[3]~678 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_avalon_slave_saved_chosen_master_vector[3]~681 | Duplicated | Physical Synthesis | Timing optimization | COMBOUT | std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_avalon_slave_saved_chosen_master_vector[3]~681_DUP_COMB_765 | COMBOUT
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_avalon_slave_saved_chosen_master_vector[3]~681 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_avalon_slave_saved_chosen_master_vector[3]~681_DUP_COMB_705 | Deleted | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_avalon_slave_saved_chosen_master_vector[3]~681_DUP_COMB_765 | Deleted | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_avalon_slave_saved_chosen_master_vector[3]~683 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_avalon_slave_saved_chosen_master_vector[3]~684 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_avalon_slave_saved_chosen_master_vector[3]~702 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_avalon_slave_saved_chosen_master_vector[3]~747 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_avalon_slave_saved_chosen_master_vector[4]~663 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_avalon_slave_saved_chosen_master_vector[4]~672 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_avalon_slave_saved_chosen_master_vector[4]~679 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_avalon_slave_saved_chosen_master_vector[4]~687 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_avalon_slave_saved_chosen_master_vector[4]~692 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_avalon_slave_saved_chosen_master_vector[5]~653 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_avalon_slave_saved_chosen_master_vector[5]~654 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_avalon_slave_saved_chosen_master_vector[5]~654_DUP_COMB_710 | Deleted | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_avalon_slave_slavearbiterlockenable~199 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_avalon_slave_slavearbiterlockenable~202 | Duplicated | Physical Synthesis | Timing optimization | REGOUT | std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_avalon_slave_slavearbiterlockenable~202_DUP_REG | REGOUT
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_avalon_slave_slavearbiterlockenable~202 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_avalon_slave_slavearbiterlockenable~202_DUP_REG | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|internal_cpu_instruction_master_qualified_request_ext_ram_s1~96 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|internal_cpu_instruction_master_qualified_request_ext_ram_s1~97_BDD630 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ior_n_to_the_lan91c111~COMB_OUT | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|iow_n_to_the_lan91c111~2_BDD437 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|iow_n_to_the_lan91c111~COMB_OUT | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|lan91c111_s1_in_a_read_cycle~61 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|lan91c111_s1_wait_counter[0]~113 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|lan91c111_s1_wait_counter[0]~114 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|lan91c111_s1_wait_counter[1]~104 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|lan91c111_s1_wait_counter[2]~111 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|lan91c111_s1_wait_counter[3] | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|last_cycle_cpu_data_master_granted_slave_ext_flash_s1~5 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|last_cycle_cpu_data_master_granted_slave_ext_flash_s1~9_DUP_COMB | Duplicated | Physical Synthesis | Timing optimization | COMBOUT | std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|last_cycle_cpu_data_master_granted_slave_ext_flash_s1~9_DUP_COMB_DUP_COMB | COMBOUT
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|last_cycle_cpu_data_master_granted_slave_ext_flash_s1~9_DUP_COMB | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|last_cycle_cpu_data_master_granted_slave_ext_flash_s1~9_DUP_COMB_DUP_COMB | Deleted | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|last_cycle_cpu_data_master_granted_slave_ext_ram_s1~5 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|last_cycle_cpu_data_master_granted_slave_ext_ram_s1~7 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|last_cycle_cpu_data_master_granted_slave_ext_ram_s1~8 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|last_cycle_cpu_data_master_granted_slave_ext_ram_s1~10 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|last_cycle_cpu_data_master_granted_slave_ext_ram_s1~12 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|last_cycle_cpu_data_master_granted_slave_ext_ram_s1~13_BDD196 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|last_cycle_cpu_data_master_granted_slave_ext_ram_s1~14_BDD197 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|last_cycle_cpu_data_master_granted_slave_ext_ram_s1~16_BDD199 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|last_cycle_cpu_data_master_granted_slave_ext_ram_s1~17_BDD200 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|last_cycle_cpu_data_master_granted_slave_lan91c111_s1~5 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|last_cycle_cpu_data_master_granted_slave_lan91c111_s1~5_DUP_COMB | Duplicated | Physical Synthesis | Timing optimization | COMBOUT | std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|last_cycle_cpu_data_master_granted_slave_lan91c111_s1~5_DUP_COMB_DUP_COMB | COMBOUT
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|last_cycle_cpu_data_master_granted_slave_lan91c111_s1~5_DUP_COMB | Duplicated | Physical Synthesis | Timing optimization | COMBOUT | std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|last_cycle_cpu_data_master_granted_slave_lan91c111_s1~5_DUP_COMB_DUP_COMB_11 | COMBOUT
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|last_cycle_cpu_data_master_granted_slave_lan91c111_s1~5_DUP_COMB | Duplicated | Physical Synthesis | Timing optimization | COMBOUT | std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|last_cycle_cpu_data_master_granted_slave_lan91c111_s1~5_DUP_COMB_DUP_COMB_12 | COMBOUT
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|last_cycle_cpu_data_master_granted_slave_lan91c111_s1~5_DUP_COMB | Deleted | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|last_cycle_cpu_data_master_granted_slave_lan91c111_s1~5_DUP_COMB_DUP_COMB | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|last_cycle_cpu_data_master_granted_slave_lan91c111_s1~5_DUP_COMB_DUP_COMB_11 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|last_cycle_cpu_data_master_granted_slave_lan91c111_s1~5_DUP_COMB_DUP_COMB_12 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|last_cycle_cpu_instruction_master_granted_slave_ext_flash_s1~5 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|last_cycle_cpu_instruction_master_granted_slave_lan91c111_s1~4 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|last_cycle_cpu_instruction_master_granted_slave_lan91c111_s1~6 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|p1_ext_ram_bus_address[0]~3431 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|p1_ext_ram_bus_address[22]~3406 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|p1_ext_ram_bus_address[22]~3412 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|p1_read_n_to_the_ext_ram~62 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|process4~73 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|write_n_to_the_ext_flash~COMB_OUT | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|write_n_to_the_ext_ram_local~13 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|write_n_to_the_ext_ram_local~14 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|write_n_to_the_ext_ram_local~15 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|high_res_timer:the_high_res_timer|counter_snapshot[4] | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|high_res_timer:the_high_res_timer|counter_snapshot[5] | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|high_res_timer:the_high_res_timer|counter_snapshot[7] | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|high_res_timer:the_high_res_timer|counter_snapshot[10] | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|high_res_timer:the_high_res_timer|counter_snapshot[11] | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|high_res_timer:the_high_res_timer|counter_snapshot[12] | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|high_res_timer:the_high_res_timer|counter_snapshot[13] | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|high_res_timer:the_high_res_timer|counter_snapshot[18] | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|high_res_timer:the_high_res_timer|counter_snapshot[19] | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|high_res_timer:the_high_res_timer|counter_snapshot[22] | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|high_res_timer:the_high_res_timer|counter_snapshot[24] | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|high_res_timer:the_high_res_timer|counter_snapshot[25] | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|high_res_timer:the_high_res_timer|counter_snapshot[30] | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|high_res_timer:the_high_res_timer|counter_snapshot[31] | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|high_res_timer:the_high_res_timer|readdata[4] | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|high_res_timer:the_high_res_timer|readdata[5] | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|high_res_timer:the_high_res_timer|readdata[6] | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|high_res_timer:the_high_res_timer|readdata[7] | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|high_res_timer:the_high_res_timer|readdata[8] | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|high_res_timer:the_high_res_timer|readdata[9] | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|high_res_timer:the_high_res_timer|readdata[10] | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|high_res_timer:the_high_res_timer|readdata[11] | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|high_res_timer:the_high_res_timer|readdata[12] | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|high_res_timer:the_high_res_timer|readdata[13] | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|high_res_timer:the_high_res_timer|readdata[14] | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|high_res_timer:the_high_res_timer|readdata[15] | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|high_res_timer:the_high_res_timer|snap_strobe~18 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|high_res_timer_s1_arbitrator:the_high_res_timer_s1|cpu_data_master_requests_high_res_timer_s1 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|jtag_uart:the_jtag_uart|fifo_rd~34 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|jtag_uart:the_jtag_uart|fifo_wr | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|jtag_uart:the_jtag_uart|ien_AE~19 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|jtag_uart:the_jtag_uart|woverflow | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|lcd_display_control_slave_arbitrator:the_lcd_display_control_slave|cpu_data_master_granted_lcd_display_control_slave~123 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|led_pio:the_led_pio|process0~1 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|reconfig_request_pio:the_reconfig_request_pio|readdata | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|reconfig_request_pio_s1_arbitrator:the_reconfig_request_pio_s1|cpu_data_master_requests_reconfig_request_pio_s1 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|reconfig_request_pio_s1_arbitrator:the_reconfig_request_pio_s1|cpu_data_master_requests_reconfig_request_pio_s1~48 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|sdram:the_sdram|Mux18~1365 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|sdram:the_sdram|Mux22~1323 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|sdram:the_sdram|Mux22~1324 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|sdram:the_sdram|Mux24~1466 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|sdram:the_sdram|Mux28~1630 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|sdram:the_sdram|Mux29~1325 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|sdram:the_sdram|Mux30~1231 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|sdram:the_sdram|Mux35~1201 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|sdram:the_sdram|Mux36~1271 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|sdram:the_sdram|Mux39~1243 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|sdram:the_sdram|Mux40~1465 | Deleted | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|sdram:the_sdram|Mux40~1469 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|sdram:the_sdram|Mux47~1291 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|sdram:the_sdram|Mux104~1607 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|sdram:the_sdram|Mux104~1610 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|sdram:the_sdram|Mux105~1397 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|sdram:the_sdram|Mux105~1400 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|sdram:the_sdram|Mux106~1397 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|sdram:the_sdram|Mux106~1400 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|sdram:the_sdram|Mux107~1397 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|sdram:the_sdram|Mux107~1400 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|sdram:the_sdram|Mux108~1493 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|sdram:the_sdram|Mux108~1503_BDD34 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|sdram:the_sdram|Mux108~1511_BDD577 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|sdram:the_sdram|Mux109~1373_BDD175 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|sdram:the_sdram|Mux109~1374_BDD176 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|sdram:the_sdram|Mux109~1375_BDD515 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|sdram:the_sdram|Mux110~1401_BDD455 | Deleted | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|sdram:the_sdram|Mux110~1402_BDD456 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|sdram:the_sdram|Mux110~1404_BDD458 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|sdram:the_sdram|Mux110~1405_BDD459 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|sdram:the_sdram|Mux111~1329_BDD463 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|sdram:the_sdram|Mux112~1358_BDD522 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|sdram:the_sdram|Mux112~1360_BDD524 | Deleted | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|sdram:the_sdram|Mux112~1361_BDD525 | Deleted | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|sdram:the_sdram|Mux112~1362_BDD526 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|sdram:the_sdram|Mux112~1363_BDD527 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|sdram:the_sdram|Mux112~1364_BDD528 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|sdram:the_sdram|Mux113~1358_BDD529 | Deleted | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|sdram:the_sdram|Mux113~1360_BDD531 | Deleted | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|sdram:the_sdram|Mux113~1361_BDD532 | Deleted | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|sdram:the_sdram|Mux113~1362_BDD533 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|sdram:the_sdram|Mux113~1363_BDD534 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|sdram:the_sdram|Mux113~1364_BDD535 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|sdram:the_sdram|Mux114~1356_BDD184 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|sdram:the_sdram|Mux114~1357_BDD185 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|sdram:the_sdram|Mux114~1358_BDD536 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|sdram:the_sdram|Mux114~1360_BDD538 | Deleted | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|sdram:the_sdram|Mux114~1361_BDD539 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|sdram:the_sdram|Mux114~1362_BDD540 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|sdram:the_sdram|Mux115~1358_BDD543 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|sdram:the_sdram|Mux115~1360_BDD545 | Deleted | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|sdram:the_sdram|Mux115~1361_BDD546 | Deleted | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|sdram:the_sdram|Mux115~1362_BDD547 | Deleted | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|sdram:the_sdram|Mux115~1363_BDD548 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|sdram:the_sdram|Mux115~1364_BDD549 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|sdram:the_sdram|m_addr[0]~_Duplicate_1 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|sdram:the_sdram|m_addr[0]~_Duplicate_1_DUP_COMB | Deleted | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|sdram:the_sdram|m_addr[1]~_Duplicate_1 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|sdram:the_sdram|m_addr[1]~_Duplicate_1_DUP_COMB | Deleted | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|sdram:the_sdram|m_addr[2]~_Duplicate_1 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|sdram:the_sdram|m_addr[2]~_Duplicate_1_DUP_COMB | Deleted | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|sdram:the_sdram|m_addr[3]~_Duplicate_1 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|sdram:the_sdram|m_addr[3]~_Duplicate_1_DUP_COMB | Deleted | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|sdram:the_sdram|m_addr[4]~_Duplicate_1 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|sdram:the_sdram|m_addr[4]~_Duplicate_1_DUP_COMB | Deleted | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|sdram:the_sdram|m_addr[5]~_Duplicate_1 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|sdram:the_sdram|m_addr[5]~_Duplicate_1_DUP_COMB | Deleted | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|sdram:the_sdram|m_addr[6]~_Duplicate_1 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|sdram:the_sdram|m_addr[6]~_Duplicate_1_DUP_COMB | Deleted | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|sdram:the_sdram|m_addr[7]~_Duplicate_1 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|sdram:the_sdram|m_addr[7]~_Duplicate_1_DUP_COMB | Deleted | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|sdram:the_sdram|m_cmd[1]~_Duplicate_1 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|sdram:the_sdram|m_cmd[1]~_Duplicate_1_DUP_COMB | Deleted | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|sdram:the_sdram|m_data[1]~_Duplicate_1 | Duplicated | Physical Synthesis | Timing optimization | COMBOUT | std_1c20:inst|sdram:the_sdram|m_data[1]~_Duplicate_1_DUP_COMB | COMBOUT
std_1c20:inst|sdram:the_sdram|m_data[1]~_Duplicate_1 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|sdram:the_sdram|m_data[1]~_Duplicate_1_DUP_COMB | Deleted | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|sdram:the_sdram|m_data[2]~_Duplicate_1 | Duplicated | Physical Synthesis | Timing optimization | COMBOUT | std_1c20:inst|sdram:the_sdram|m_data[2]~_Duplicate_1_DUP_COMB | COMBOUT
std_1c20:inst|sdram:the_sdram|m_data[2]~_Duplicate_1 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|sdram:the_sdram|m_data[2]~_Duplicate_1_DUP_COMB | Deleted | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|sdram:the_sdram|m_data[5]~_Duplicate_1 | Duplicated | Physical Synthesis | Timing optimization | COMBOUT | std_1c20:inst|sdram:the_sdram|m_data[5]~_Duplicate_1_DUP_COMB | COMBOUT
std_1c20:inst|sdram:the_sdram|m_data[5]~_Duplicate_1 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|sdram:the_sdram|m_data[5]~_Duplicate_1_DUP_COMB | Deleted | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|sdram:the_sdram|m_data[6]~_Duplicate_1 | Duplicated | Physical Synthesis | Timing optimization | COMBOUT | std_1c20:inst|sdram:the_sdram|m_data[6]~_Duplicate_1_DUP_COMB | COMBOUT
std_1c20:inst|sdram:the_sdram|m_data[6]~_Duplicate_1 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|sdram:the_sdram|m_data[6]~_Duplicate_1_DUP_COMB | Deleted | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|sdram:the_sdram|m_data[7]~_Duplicate_1 | Duplicated | Physical Synthesis | Timing optimization | COMBOUT | std_1c20:inst|sdram:the_sdram|m_data[7]~_Duplicate_1_DUP_COMB | COMBOUT
std_1c20:inst|sdram:the_sdram|m_data[7]~_Duplicate_1 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|sdram:the_sdram|m_data[7]~_Duplicate_1_DUP_COMB | Deleted | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|sdram:the_sdram|m_data[8]~_Duplicate_1 | Duplicated | Physical Synthesis | Timing optimization | COMBOUT | std_1c20:inst|sdram:the_sdram|m_data[8]~_Duplicate_1_DUP_COMB | COMBOUT
std_1c20:inst|sdram:the_sdram|m_data[8]~_Duplicate_1 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|sdram:the_sdram|m_data[8]~_Duplicate_1_DUP_COMB | Deleted | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|sdram:the_sdram|m_data[9]~_Duplicate_1 | Duplicated | Physical Synthesis | Timing optimization | COMBOUT | std_1c20:inst|sdram:the_sdram|m_data[9]~_Duplicate_1_DUP_COMB | COMBOUT
std_1c20:inst|sdram:the_sdram|m_data[9]~_Duplicate_1 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|sdram:the_sdram|m_data[9]~_Duplicate_1_DUP_COMB | Deleted | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|sdram:the_sdram|m_data[10]~_Duplicate_1 | Duplicated | Physical Synthesis | Timing optimization | COMBOUT | std_1c20:inst|sdram:the_sdram|m_data[10]~_Duplicate_1_DUP_COMB | COMBOUT
std_1c20:inst|sdram:the_sdram|m_data[10]~_Duplicate_1 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|sdram:the_sdram|m_data[10]~_Duplicate_1_DUP_COMB | Deleted | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|sdram:the_sdram|m_data[11]~_Duplicate_1 | Duplicated | Physical Synthesis | Timing optimization | COMBOUT | std_1c20:inst|sdram:the_sdram|m_data[11]~_Duplicate_1_DUP_COMB | COMBOUT
std_1c20:inst|sdram:the_sdram|m_data[11]~_Duplicate_1 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|sdram:the_sdram|m_data[11]~_Duplicate_1_DUP_COMB | Deleted | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|sdram:the_sdram|m_data[12]~_Duplicate_1 | Duplicated | Physical Synthesis | Timing optimization | COMBOUT | std_1c20:inst|sdram:the_sdram|m_data[12]~_Duplicate_1_DUP_COMB | COMBOUT
std_1c20:inst|sdram:the_sdram|m_data[12]~_Duplicate_1 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|sdram:the_sdram|m_data[12]~_Duplicate_1_DUP_COMB | Deleted | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|sdram:the_sdram|m_data[13]~_Duplicate_1 | Duplicated | Physical Synthesis | Timing optimization | COMBOUT | std_1c20:inst|sdram:the_sdram|m_data[13]~_Duplicate_1_DUP_COMB | COMBOUT
std_1c20:inst|sdram:the_sdram|m_data[13]~_Duplicate_1 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|sdram:the_sdram|m_data[13]~_Duplicate_1_DUP_COMB | Deleted | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|sdram:the_sdram|m_data[14]~_Duplicate_1 | Duplicated | Physical Synthesis | Timing optimization | COMBOUT | std_1c20:inst|sdram:the_sdram|m_data[14]~_Duplicate_1_DUP_COMB | COMBOUT
std_1c20:inst|sdram:the_sdram|m_data[14]~_Duplicate_1 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|sdram:the_sdram|m_data[14]~_Duplicate_1_DUP_COMB | Deleted | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|sdram:the_sdram|m_data[15]~_Duplicate_1 | Duplicated | Physical Synthesis | Timing optimization | COMBOUT | std_1c20:inst|sdram:the_sdram|m_data[15]~_Duplicate_1_DUP_COMB | COMBOUT
std_1c20:inst|sdram:the_sdram|m_data[15]~_Duplicate_1 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|sdram:the_sdram|m_data[15]~_Duplicate_1_DUP_COMB | Deleted | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|sdram:the_sdram|m_data[16]~_Duplicate_1 | Duplicated | Physical Synthesis | Timing optimization | COMBOUT | std_1c20:inst|sdram:the_sdram|m_data[16]~_Duplicate_1_DUP_COMB | COMBOUT
std_1c20:inst|sdram:the_sdram|m_data[16]~_Duplicate_1 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|sdram:the_sdram|m_data[16]~_Duplicate_1_DUP_COMB | Deleted | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|sdram:the_sdram|m_data[17]~_Duplicate_1 | Duplicated | Physical Synthesis | Timing optimization | COMBOUT | std_1c20:inst|sdram:the_sdram|m_data[17]~_Duplicate_1_DUP_COMB | COMBOUT
std_1c20:inst|sdram:the_sdram|m_data[17]~_Duplicate_1 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|sdram:the_sdram|m_data[17]~_Duplicate_1_DUP_COMB | Deleted | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|sdram:the_sdram|m_data[18]~_Duplicate_1 | Duplicated | Physical Synthesis | Timing optimization | COMBOUT | std_1c20:inst|sdram:the_sdram|m_data[18]~_Duplicate_1_DUP_COMB | COMBOUT
std_1c20:inst|sdram:the_sdram|m_data[19]~_Duplicate_1 | Duplicated | Physical Synthesis | Timing optimization | COMBOUT | std_1c20:inst|sdram:the_sdram|m_data[19]~_Duplicate_1_DUP_COMB | COMBOUT
std_1c20:inst|sdram:the_sdram|m_data[19]~_Duplicate_1 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|sdram:the_sdram|m_data[19]~_Duplicate_1_DUP_COMB | Deleted | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|sdram:the_sdram|m_data[20]~_Duplicate_1 | Duplicated | Physical Synthesis | Timing optimization | COMBOUT | std_1c20:inst|sdram:the_sdram|m_data[20]~_Duplicate_1_DUP_COMB | COMBOUT
std_1c20:inst|sdram:the_sdram|m_data[20]~_Duplicate_1 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|sdram:the_sdram|m_data[20]~_Duplicate_1_DUP_COMB | Deleted | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|sdram:the_sdram|m_data[21]~_Duplicate_1 | Duplicated | Physical Synthesis | Timing optimization | COMBOUT | std_1c20:inst|sdram:the_sdram|m_data[21]~_Duplicate_1_DUP_COMB | COMBOUT
std_1c20:inst|sdram:the_sdram|m_data[21]~_Duplicate_1 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|sdram:the_sdram|m_data[21]~_Duplicate_1_DUP_COMB | Deleted | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|sdram:the_sdram|m_data[22]~_Duplicate_1 | Duplicated | Physical Synthesis | Timing optimization | COMBOUT | std_1c20:inst|sdram:the_sdram|m_data[22]~_Duplicate_1_DUP_COMB | COMBOUT
std_1c20:inst|sdram:the_sdram|m_data[22]~_Duplicate_1 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|sdram:the_sdram|m_data[22]~_Duplicate_1_DUP_COMB | Deleted | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|sdram:the_sdram|m_data[23]~_Duplicate_1 | Duplicated | Physical Synthesis | Timing optimization | COMBOUT | std_1c20:inst|sdram:the_sdram|m_data[23]~_Duplicate_1_DUP_COMB | COMBOUT
std_1c20:inst|sdram:the_sdram|m_data[23]~_Duplicate_1 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|sdram:the_sdram|m_data[23]~_Duplicate_1_DUP_COMB | Deleted | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|sdram:the_sdram|m_data[24]~_Duplicate_1 | Duplicated | Physical Synthesis | Timing optimization | COMBOUT | std_1c20:inst|sdram:the_sdram|m_data[24]~_Duplicate_1_DUP_COMB | COMBOUT
std_1c20:inst|sdram:the_sdram|m_data[24]~_Duplicate_1 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|sdram:the_sdram|m_data[24]~_Duplicate_1_DUP_COMB | Deleted | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|sdram:the_sdram|m_data[25]~_Duplicate_1 | Duplicated | Physical Synthesis | Timing optimization | COMBOUT | std_1c20:inst|sdram:the_sdram|m_data[25]~_Duplicate_1_DUP_COMB | COMBOUT
std_1c20:inst|sdram:the_sdram|m_data[25]~_Duplicate_1 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|sdram:the_sdram|m_data[25]~_Duplicate_1_DUP_COMB | Deleted | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|sdram:the_sdram|m_data[26]~_Duplicate_1 | Duplicated | Physical Synthesis | Timing optimization | COMBOUT | std_1c20:inst|sdram:the_sdram|m_data[26]~_Duplicate_1_DUP_COMB | COMBOUT
std_1c20:inst|sdram:the_sdram|m_data[26]~_Duplicate_1 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|sdram:the_sdram|m_data[26]~_Duplicate_1_DUP_COMB | Deleted | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|sdram:the_sdram|m_data[27]~_Duplicate_1 | Duplicated | Physical Synthesis | Timing optimization | COMBOUT | std_1c20:inst|sdram:the_sdram|m_data[27]~_Duplicate_1_DUP_COMB_68 | COMBOUT
std_1c20:inst|sdram:the_sdram|m_data[27]~_Duplicate_1 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|sdram:the_sdram|m_data[27]~_Duplicate_1_DUP_COMB_68 | Deleted | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|sdram:the_sdram|m_data[28]~_Duplicate_1 | Duplicated | Physical Synthesis | Timing optimization | COMBOUT | std_1c20:inst|sdram:the_sdram|m_data[28]~_Duplicate_1_DUP_COMB | COMBOUT
std_1c20:inst|sdram:the_sdram|m_data[28]~_Duplicate_1 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|sdram:the_sdram|m_data[28]~_Duplicate_1_DUP_COMB | Deleted | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|sdram:the_sdram|m_data[29]~_Duplicate_1 | Duplicated | Physical Synthesis | Timing optimization | COMBOUT | std_1c20:inst|sdram:the_sdram|m_data[29]~_Duplicate_1_DUP_COMB | COMBOUT
std_1c20:inst|sdram:the_sdram|m_data[29]~_Duplicate_1 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|sdram:the_sdram|m_data[29]~_Duplicate_1_DUP_COMB | Deleted | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|sdram:the_sdram|m_data[30]~_Duplicate_1 | Duplicated | Physical Synthesis | Timing optimization | COMBOUT | std_1c20:inst|sdram:the_sdram|m_data[30]~_Duplicate_1_DUP_COMB | COMBOUT
std_1c20:inst|sdram:the_sdram|m_data[30]~_Duplicate_1 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|sdram:the_sdram|m_data[30]~_Duplicate_1_DUP_COMB | Deleted | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|sdram:the_sdram|m_data[31]~_Duplicate_1 | Duplicated | Physical Synthesis | Timing optimization | COMBOUT | std_1c20:inst|sdram:the_sdram|m_data[31]~_Duplicate_1_DUP_COMB | COMBOUT
std_1c20:inst|sdram:the_sdram|m_data[31]~_Duplicate_1 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|sdram:the_sdram|m_data[31]~_Duplicate_1_DUP_COMB | Deleted | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|sdram:the_sdram|m_next[3] | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|sdram:the_sdram|m_next[3]~850_BDD310 | Deleted | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|sdram:the_sdram|m_next[3]~851_BDD311 | Deleted | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|sdram:the_sdram|m_next[3]~854_BDD314 | Deleted | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|sdram:the_sdram|m_next[3]~855_BDD315 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|sdram:the_sdram|m_next[3]~856_BDD316 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|sdram:the_sdram|m_next[4]~857_BDD317 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|sdram:the_sdram|m_next[4]~858_BDD318 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|sdram:the_sdram|m_next[4]~861_BDD321 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|sdram:the_sdram|module_input~21 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_0[41] | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_0[44] | Duplicated | Physical Synthesis | Timing optimization | COMBOUT | std_1c20:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_0[44]~_DUP_COMB | COMBOUT
std_1c20:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_0[44] | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_0[45] | Duplicated | Physical Synthesis | Timing optimization | COMBOUT | std_1c20:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_0[45]~_DUP_COMB | COMBOUT
std_1c20:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_0[45] | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_0[46] | Duplicated | Physical Synthesis | Timing optimization | COMBOUT | std_1c20:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_0[46]~_DUP_COMB | COMBOUT
std_1c20:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_0[46] | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_0[47] | Duplicated | Physical Synthesis | Timing optimization | COMBOUT | std_1c20:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_0[47]~_DUP_COMB | COMBOUT
std_1c20:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_0[47] | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_0[49] | Duplicated | Physical Synthesis | Timing optimization | COMBOUT | std_1c20:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_0[49]~_DUP_COMB | COMBOUT
std_1c20:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_0[49] | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_0[50] | Duplicated | Physical Synthesis | Timing optimization | COMBOUT | std_1c20:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_0[50]~_DUP_COMB | COMBOUT
std_1c20:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_0[50] | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_0[51] | Duplicated | Physical Synthesis | Timing optimization | COMBOUT | std_1c20:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_0[51]~_DUP_COMB | COMBOUT
std_1c20:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_0[51] | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_0[52] | Duplicated | Physical Synthesis | Timing optimization | COMBOUT | std_1c20:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_0[52]~_DUP_COMB | COMBOUT
std_1c20:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_0[52] | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_0[53] | Duplicated | Physical Synthesis | Timing optimization | COMBOUT | std_1c20:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_0[53]~_DUP_COMB | COMBOUT
std_1c20:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_0[53] | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_0[54] | Duplicated | Physical Synthesis | Timing optimization | COMBOUT | std_1c20:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_0[54]~_DUP_COMB | COMBOUT
std_1c20:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_0[54] | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_0[55] | Duplicated | Physical Synthesis | Timing optimization | COMBOUT | std_1c20:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_0[55]~_DUP_COMB | COMBOUT
std_1c20:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_0[55] | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_0[56] | Duplicated | Physical Synthesis | Timing optimization | COMBOUT | std_1c20:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_0[56]~_DUP_COMB | COMBOUT
std_1c20:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_0[56] | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_1[44] | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_1[45] | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_1[46] | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_1[47] | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_1[48] | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_1[49] | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_1[50] | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_1[51] | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_1[52] | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_1[53] | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_1[54] | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_1[55] | Duplicated | Physical Synthesis | Timing optimization | COMBOUT | std_1c20:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_1[55]~_DUP_COMB | COMBOUT
std_1c20:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_1[55]~_DUP_COMB | Deleted | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_1[56] | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_1[57] | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|sdram_s1_arbitrator:the_sdram_s1|cpu_instruction_master_granted_sdram_s1~85 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|sdram_s1_arbitrator:the_sdram_s1|cpu_instruction_master_requests_sdram_s1~41 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|sdram_s1_arbitrator:the_sdram_s1|internal_cpu_instruction_master_qualified_request_sdram_s1~59 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|sdram_s1_arbitrator:the_sdram_s1|internal_cpu_instruction_master_qualified_request_sdram_s1~60 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|sdram_s1_arbitrator:the_sdram_s1|internal_cpu_instruction_master_qualified_request_sdram_s1~61_BDD634 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|sdram_s1_arbitrator:the_sdram_s1|module_input5~34 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|sdram_s1_arbitrator:the_sdram_s1|rdv_fifo_for_cpu_data_master_to_sdram_s1_module:rdv_fifo_for_cpu_data_master_to_sdram_s1|fifo_contains_ones_n~18 | Duplicated | Physical Synthesis | Timing optimization | COMBOUT | std_1c20:inst|sdram_s1_arbitrator:the_sdram_s1|rdv_fifo_for_cpu_data_master_to_sdram_s1_module:rdv_fifo_for_cpu_data_master_to_sdram_s1|fifo_contains_ones_n~18_DUP_COMB | COMBOUT
std_1c20:inst|sdram_s1_arbitrator:the_sdram_s1|rdv_fifo_for_cpu_data_master_to_sdram_s1_module:rdv_fifo_for_cpu_data_master_to_sdram_s1|fifo_contains_ones_n~18 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|sdram_s1_arbitrator:the_sdram_s1|rdv_fifo_for_cpu_data_master_to_sdram_s1_module:rdv_fifo_for_cpu_data_master_to_sdram_s1|fifo_contains_ones_n~18_DUP_COMB | Deleted | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|sdram_s1_arbitrator:the_sdram_s1|rdv_fifo_for_cpu_instruction_master_to_sdram_s1_module:rdv_fifo_for_cpu_instruction_master_to_sdram_s1|fifo_contains_ones_n~17 | Duplicated | Physical Synthesis | Timing optimization | COMBOUT | std_1c20:inst|sdram_s1_arbitrator:the_sdram_s1|rdv_fifo_for_cpu_instruction_master_to_sdram_s1_module:rdv_fifo_for_cpu_instruction_master_to_sdram_s1|fifo_contains_ones_n~17_DUP_COMB | COMBOUT
std_1c20:inst|sdram_s1_arbitrator:the_sdram_s1|rdv_fifo_for_cpu_instruction_master_to_sdram_s1_module:rdv_fifo_for_cpu_instruction_master_to_sdram_s1|fifo_contains_ones_n~17 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|sdram_s1_arbitrator:the_sdram_s1|rdv_fifo_for_cpu_instruction_master_to_sdram_s1_module:rdv_fifo_for_cpu_instruction_master_to_sdram_s1|fifo_contains_ones_n~17_DUP_COMB | Deleted | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|sdram_s1_arbitrator:the_sdram_s1|rdv_fifo_for_cpu_instruction_master_to_sdram_s1_module:rdv_fifo_for_cpu_instruction_master_to_sdram_s1|process15~0 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|sdram_s1_arbitrator:the_sdram_s1|rdv_fifo_for_cpu_instruction_master_to_sdram_s1_module:rdv_fifo_for_cpu_instruction_master_to_sdram_s1|stage_0~5 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|sdram_s1_arbitrator:the_sdram_s1|rdv_fifo_for_cpu_instruction_master_to_sdram_s1_module:rdv_fifo_for_cpu_instruction_master_to_sdram_s1|stage_1~5 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|sdram_s1_arbitrator:the_sdram_s1|rdv_fifo_for_cpu_instruction_master_to_sdram_s1_module:rdv_fifo_for_cpu_instruction_master_to_sdram_s1|stage_2~5 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|sdram_s1_arbitrator:the_sdram_s1|rdv_fifo_for_cpu_instruction_master_to_sdram_s1_module:rdv_fifo_for_cpu_instruction_master_to_sdram_s1|stage_3~5 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|sdram_s1_arbitrator:the_sdram_s1|rdv_fifo_for_cpu_instruction_master_to_sdram_s1_module:rdv_fifo_for_cpu_instruction_master_to_sdram_s1|stage_4~5 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|sdram_s1_arbitrator:the_sdram_s1|rdv_fifo_for_cpu_instruction_master_to_sdram_s1_module:rdv_fifo_for_cpu_instruction_master_to_sdram_s1|stage_5~5 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|sdram_s1_arbitrator:the_sdram_s1|sdram_s1_arb_addend[0]~737 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|sdram_s1_arbitrator:the_sdram_s1|sdram_s1_saved_chosen_master_vector[0] | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|sdram_s1_arbitrator:the_sdram_s1|sdram_s1_saved_chosen_master_vector[1] | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|seven_seg_pio:the_seven_seg_pio|process0~29 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|seven_seg_pio:the_seven_seg_pio|process0~30 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|seven_seg_pio:the_seven_seg_pio|process0~31 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|sys_clk_timer:the_sys_clk_timer|control_register[2] | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|sys_clk_timer:the_sys_clk_timer|control_wr_strobe | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|sys_clk_timer:the_sys_clk_timer|counter_snapshot[5] | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|sys_clk_timer:the_sys_clk_timer|counter_snapshot[6] | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|sys_clk_timer:the_sys_clk_timer|counter_snapshot[7] | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|sys_clk_timer:the_sys_clk_timer|counter_snapshot[9] | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|sys_clk_timer:the_sys_clk_timer|counter_snapshot[10] | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|sys_clk_timer:the_sys_clk_timer|counter_snapshot[11] | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|sys_clk_timer:the_sys_clk_timer|counter_snapshot[12] | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|sys_clk_timer:the_sys_clk_timer|counter_snapshot[14] | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|sys_clk_timer:the_sys_clk_timer|counter_snapshot[19] | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|sys_clk_timer:the_sys_clk_timer|counter_snapshot[20] | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|sys_clk_timer:the_sys_clk_timer|counter_snapshot[24] | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|sys_clk_timer:the_sys_clk_timer|counter_snapshot[29] | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|sys_clk_timer:the_sys_clk_timer|counter_snapshot[31] | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|sys_clk_timer:the_sys_clk_timer|readdata[4] | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|sys_clk_timer:the_sys_clk_timer|readdata[5] | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|sys_clk_timer:the_sys_clk_timer|readdata[6] | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|sys_clk_timer:the_sys_clk_timer|readdata[7] | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|sys_clk_timer:the_sys_clk_timer|readdata[8] | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|sys_clk_timer:the_sys_clk_timer|readdata[9] | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|sys_clk_timer:the_sys_clk_timer|readdata[10] | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|sys_clk_timer:the_sys_clk_timer|readdata[11] | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|sys_clk_timer:the_sys_clk_timer|readdata[12] | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|sys_clk_timer:the_sys_clk_timer|readdata[13] | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|sys_clk_timer:the_sys_clk_timer|readdata[14] | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|sys_clk_timer:the_sys_clk_timer|readdata[15] | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|sys_clk_timer:the_sys_clk_timer|snap_strobe~24 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|sys_clk_timer_s1_arbitrator:the_sys_clk_timer_s1|cpu_data_master_requests_sys_clk_timer_s1 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|sys_clk_timer_s1_arbitrator:the_sys_clk_timer_s1|cpu_data_master_requests_sys_clk_timer_s1~181 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|sys_clk_timer_s1_arbitrator:the_sys_clk_timer_s1|cpu_data_master_requests_sys_clk_timer_s1~182_BDD271 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|sys_clk_timer_s1_arbitrator:the_sys_clk_timer_s1|cpu_data_master_requests_sys_clk_timer_s1~183_BDD591 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|sysid_control_slave_arbitrator:the_sysid_control_slave|cpu_data_master_granted_sysid_control_slave | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|sysid_control_slave_arbitrator:the_sysid_control_slave|cpu_data_master_granted_sysid_control_slave~150 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|sysid_control_slave_arbitrator:the_sysid_control_slave|cpu_data_master_granted_sysid_control_slave~151 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|sysid_control_slave_arbitrator:the_sysid_control_slave|cpu_data_master_granted_sysid_control_slave~154 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|sysid_control_slave_arbitrator:the_sysid_control_slave|cpu_data_master_granted_sysid_control_slave~155 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|sysid_control_slave_arbitrator:the_sysid_control_slave|cpu_data_master_granted_sysid_control_slave~157 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|sysid_control_slave_arbitrator:the_sysid_control_slave|cpu_data_master_granted_sysid_control_slave~158 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|uart1:the_uart1|uart1_regs:the_uart1_regs|Equal1~116 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|uart1:the_uart1|uart1_regs:the_uart1_regs|Equal1~118 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|uart1:the_uart1|uart1_regs:the_uart1_regs|Equal1~119 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|uart1:the_uart1|uart1_regs:the_uart1_regs|Equal1~120 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|uart1:the_uart1|uart1_regs:the_uart1_regs|Equal1~121 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|uart1:the_uart1|uart1_regs:the_uart1_regs|Equal1~122 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|uart1:the_uart1|uart1_regs:the_uart1_regs|Equal1~123 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|uart1:the_uart1|uart1_regs:the_uart1_regs|Equal1~124 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|uart1:the_uart1|uart1_regs:the_uart1_regs|control_wr_strobe~26 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|uart1:the_uart1|uart1_regs:the_uart1_regs|control_wr_strobe~27 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|uart1:the_uart1|uart1_regs:the_uart1_regs|readdata[0] | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|uart1:the_uart1|uart1_regs:the_uart1_regs|readdata[1] | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|uart1:the_uart1|uart1_regs:the_uart1_regs|readdata[2] | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|uart1:the_uart1|uart1_regs:the_uart1_regs|readdata[3] | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|uart1:the_uart1|uart1_regs:the_uart1_regs|readdata[4] | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|uart1:the_uart1|uart1_regs:the_uart1_regs|readdata[5] | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|uart1:the_uart1|uart1_regs:the_uart1_regs|readdata[6] | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|uart1:the_uart1|uart1_regs:the_uart1_regs|readdata[7] | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|uart1:the_uart1|uart1_regs:the_uart1_regs|readdata[8] | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|uart1:the_uart1|uart1_regs:the_uart1_regs|readdata[9] | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|uart1:the_uart1|uart1_regs:the_uart1_regs|tx_wr_strobe~14 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|uart1:the_uart1|uart1_rx:the_uart1_rx|rx_data[0] | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|uart1:the_uart1|uart1_rx:the_uart1_rx|rx_rd_strobe_onset~18 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|uart1:the_uart1|uart1_tx:the_uart1_tx|tx_wr_strobe_onset~34 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|uart1:the_uart1|uart1_tx:the_uart1_tx|tx_wr_strobe_onset~35 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|uart1:the_uart1|uart1_tx:the_uart1_tx|tx_wr_strobe_onset~36 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|uart1_s1_arbitrator:the_uart1_s1|cpu_data_master_granted_uart1_s1 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|uart1_s1_arbitrator:the_uart1_s1|d1_reasons_to_wait | Modified | Physical Synthesis | Timing optimization |  |  |
zs_addr_from_the_sdram[0] | Modified | Physical Synthesis | Timing optimization |  |  |
zs_addr_from_the_sdram[1] | Modified | Physical Synthesis | Timing optimization |  |  |
zs_addr_from_the_sdram[2] | Modified | Physical Synthesis | Timing optimization |  |  |
zs_addr_from_the_sdram[3] | Modified | Physical Synthesis | Timing optimization |  |  |
zs_addr_from_the_sdram[4] | Modified | Physical Synthesis | Timing optimization |  |  |
zs_addr_from_the_sdram[5] | Modified | Physical Synthesis | Timing optimization |  |  |
zs_addr_from_the_sdram[6] | Modified | Physical Synthesis | Timing optimization |  |  |
zs_addr_from_the_sdram[7] | Modified | Physical Synthesis | Timing optimization |  |  |
zs_cas_n_from_the_sdram | Modified | Physical Synthesis | Timing optimization |  |  |
zs_dq_to_and_from_the_sdram[1] | Modified | Physical Synthesis | Timing optimization |  |  |
zs_dq_to_and_from_the_sdram[2] | Modified | Physical Synthesis | Timing optimization |  |  |
zs_dq_to_and_from_the_sdram[5] | Modified | Physical Synthesis | Timing optimization |  |  |
zs_dq_to_and_from_the_sdram[6] | Modified | Physical Synthesis | Timing optimization |  |  |
zs_dq_to_and_from_the_sdram[7] | Modified | Physical Synthesis | Timing optimization |  |  |
zs_dq_to_and_from_the_sdram[8] | Modified | Physical Synthesis | Timing optimization |  |  |
zs_dq_to_and_from_the_sdram[9] | Modified | Physical Synthesis | Timing optimization |  |  |
zs_dq_to_and_from_the_sdram[10] | Modified | Physical Synthesis | Timing optimization |  |  |
zs_dq_to_and_from_the_sdram[11] | Modified | Physical Synthesis | Timing optimization |  |  |
zs_dq_to_and_from_the_sdram[12] | Modified | Physical Synthesis | Timing optimization |  |  |
zs_dq_to_and_from_the_sdram[13] | Modified | Physical Synthesis | Timing optimization |  |  |
zs_dq_to_and_from_the_sdram[14] | Modified | Physical Synthesis | Timing optimization |  |  |
zs_dq_to_and_from_the_sdram[15] | Modified | Physical Synthesis | Timing optimization |  |  |
zs_dq_to_and_from_the_sdram[16] | Modified | Physical Synthesis | Timing optimization |  |  |
zs_dq_to_and_from_the_sdram[17] | Modified | Physical Synthesis | Timing optimization |  |  |
zs_dq_to_and_from_the_sdram[19] | Modified | Physical Synthesis | Timing optimization |  |  |
zs_dq_to_and_from_the_sdram[20] | Modified | Physical Synthesis | Timing optimization |  |  |
zs_dq_to_and_from_the_sdram[21] | Modified | Physical Synthesis | Timing optimization |  |  |
zs_dq_to_and_from_the_sdram[22] | Modified | Physical Synthesis | Timing optimization |  |  |
zs_dq_to_and_from_the_sdram[23] | Modified | Physical Synthesis | Timing optimization |  |  |
zs_dq_to_and_from_the_sdram[24] | Modified | Physical Synthesis | Timing optimization |  |  |
zs_dq_to_and_from_the_sdram[25] | Modified | Physical Synthesis | Timing optimization |  |  |
zs_dq_to_and_from_the_sdram[26] | Modified | Physical Synthesis | Timing optimization |  |  |
zs_dq_to_and_from_the_sdram[27] | Modified | Physical Synthesis | Timing optimization |  |  |
zs_dq_to_and_from_the_sdram[28] | Modified | Physical Synthesis | Timing optimization |  |  |
zs_dq_to_and_from_the_sdram[29] | Modified | Physical Synthesis | Timing optimization |  |  |
zs_dq_to_and_from_the_sdram[30] | Modified | Physical Synthesis | Timing optimization |  |  |
zs_dq_to_and_from_the_sdram[31] | Modified | Physical Synthesis | Timing optimization |  |  |
sld_hub:sld_hub_inst|sld_rom_sr:HUB_INFO_REG|Add0~74 | Modified | Physical Synthesis | Timing optimization |  |  |
sld_hub:sld_hub_inst|sld_rom_sr:HUB_INFO_REG|word_counter[0] | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|button_pio:the_button_pio|process1~14 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|button_pio:the_button_pio|process1~15_BDD379 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|clock_0_in_arbitrator:the_clock_0_in|cpu_data_master_requests_clock_0_in~534 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|clock_0_in_arbitrator:the_clock_0_in|cpu_data_master_requests_clock_0_in~537 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|clock_0_in_arbitrator:the_clock_0_in|cpu_data_master_requests_clock_0_in~539_BDD155 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|clock_0_in_arbitrator:the_clock_0_in|cpu_data_master_requests_clock_0_in~540_BDD156 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|clock_0_in_arbitrator:the_clock_0_in|cpu_data_master_requests_clock_0_in~541_BDD598 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|clock_0_in_arbitrator:the_clock_0_in|cpu_data_master_requests_clock_0_in~542_BDD599 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|clock_0_in_arbitrator:the_clock_0_in|cpu_data_master_requests_clock_0_in~543_BDD600 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|A_WE_StdLogicVector~14086 | Deleted | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|A_WE_StdLogicVector~14087 | Deleted | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|A_WE_StdLogicVector~14090 | Deleted | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|A_WE_StdLogicVector~14097 | Deleted | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|A_WE_StdLogicVector~14098 | Deleted | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|A_WE_StdLogicVector~14099 | Deleted | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|A_WE_StdLogicVector~14107 | Deleted | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|A_WE_StdLogicVector~14113 | Deleted | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|A_WE_StdLogicVector~14129 | Deleted | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|A_WE_StdLogicVector~14158 | Deleted | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|A_WE_StdLogicVector~14159 | Deleted | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|A_WE_StdLogicVector~14160 | Deleted | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|A_WE_StdLogicVector~14161 | Deleted | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|A_WE_StdLogicVector~14162 | Deleted | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|Add9~280 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|D_inst_ram_hit | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|D_inst_ram_hit~12_BDD593 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|D_inst_ram_hit~13_BDD594 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|D_inst_ram_hit~14_BDD595 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|D_issue | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|D_issue~3_BDD442 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|D_issue~4_BDD443 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|D_pc_plus_one[0] | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|E_alu_result[0]~2400 | Deleted | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|E_alu_result[0]~2401 | Deleted | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|E_alu_result[0]~2402 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|E_alu_result[0]~2404_BDD190 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|E_alu_result[0]~2405_BDD191 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|E_alu_result[0]~2406_BDD192 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|E_alu_result[1]~2397 | Deleted | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|E_alu_result[1]~2398 | Deleted | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|E_arith_src1~0 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|E_arith_src1~65_BDD329 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|E_arith_src1~66_BDD330 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|E_control_rd_data_without_mmu_regs[2] | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|E_control_rd_data_without_mmu_regs[3] | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|E_control_rd_data_without_mmu_regs[4] | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|E_control_rd_data_without_mmu_regs[5] | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|E_control_rd_data_without_mmu_regs[6] | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|E_logic_result[20]~15607 | Deleted | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|E_logic_result[21]~15596 | Deleted | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|E_logic_result[22]~15595 | Deleted | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|E_logic_result[23]~15608 | Deleted | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|E_logic_result[24]~15599 | Deleted | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|E_logic_result[25]~15606 | Deleted | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|E_logic_result[26]~15614 | Deleted | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|E_logic_result[27]~15616 | Deleted | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|E_logic_result[28]~15619 | Deleted | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|E_logic_result[29]~15618 | Deleted | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|E_src2[0]~1528 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|E_src2[0]~1535_BDD73 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|E_src2[0]~1536_BDD74 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|E_src2[1]~1527 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|E_src2[1]~1537_BDD75 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|E_src2[1]~1538_BDD76 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|E_src2[2]~1503 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|E_src2[2]~1541_BDD79 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|E_src2[2]~1542_BDD80 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|E_src2[3]~1504 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|E_src2[3]~1547_BDD85 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|E_src2[3]~1548_BDD86 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|E_src2[4]~1525 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|E_src2[4]~1545_BDD83 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|E_src2[4]~1546_BDD84 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|E_src2[5]~1526 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|E_src2[5]~1539_BDD77 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|E_src2[5]~1540_BDD78 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|E_src2[6]~1524 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|E_src2[6]~1543_BDD81 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|E_src2[6]~1544_BDD82 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|E_src2[7]~1523 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|E_src2[7]~1549_BDD87 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|E_src2[7]~1550_BDD88 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|E_src2[13]~1513 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|E_src2[13]~1569_BDD143 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|E_src2[13]~1570_BDD144 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|E_src2[14]~1512 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|E_src2[14]~1567_BDD141 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|E_src2[14]~1568_BDD142 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|E_src2[16]~1510 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|E_src2[16]~1587_BDD512 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|E_src2[16]~1588_BDD513 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|E_src2[16]~1589_BDD514 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|E_src2[17]~1515 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|E_src2[17]~1590_BDD550 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|E_src2[17]~1591_BDD551 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|E_src2[17]~1592_BDD552 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|E_src2[18]~1508 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|E_src2[18]~1596_BDD556 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|E_src2[18]~1597_BDD557 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|E_src2[18]~1598_BDD558 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|E_src2[19]~1507 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|E_src2[19]~1593_BDD553 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|E_src2[19]~1594_BDD554 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|E_src2[19]~1595_BDD555 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|E_src2[20]~1517 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|E_src2[20]~1559_BDD131 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|E_src2[20]~1560_BDD132 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|E_src2[21]~1506 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|E_src2[21]~1561_BDD133 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|E_src2[21]~1562_BDD134 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|E_src2[22]~1505 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|E_src2[22]~1563_BDD137 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|E_src2[22]~1564_BDD138 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|E_src2[23]~1518 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|E_src2[23]~1565_BDD139 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|E_src2[23]~1566_BDD140 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|E_src2[24]~1509 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|E_src2[24]~1571_BDD148 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|E_src2[24]~1572_BDD149 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|E_src2[25]~1516 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|E_src2[25]~1573_BDD206 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|E_src2[25]~1574_BDD207 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|E_src2[26]~1530 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|E_src2[26]~1575_BDD212 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|E_src2[26]~1576_BDD213 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|E_src2[27]~1532 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|E_src2[27]~1577_BDD237 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|E_src2[27]~1578_BDD238 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|E_src2[28]~1534 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|E_src2[28]~1579_BDD243 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|E_src2[28]~1580_BDD244 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|E_src2[29]~1533 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|E_src2[29]~1581_BDD254 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|E_src2[29]~1582_BDD255 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|E_src2[30]~1531 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|E_src2[30]~1583_BDD278 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|E_src2[30]~1584_BDD279 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|E_src2[31]~1529 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|E_src2[31]~1585_BDD333 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|E_src2[31]~1586_BDD334 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|Equal199~134 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|F_ic_data_rd_addr_nxt[0]~1822 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|F_ic_hit~122 | Deleted | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|F_ic_hit~123 | Deleted | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|F_ic_hit~126 | Deleted | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|F_ic_hit~127 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|F_ic_hit~128_BDD235 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|F_ic_hit~129_BDD236 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|M_alu_result[0]~_DUP_COMB | Retimed Register | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|M_alu_result[2] | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|M_alu_result[2]~421_BDD280 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|M_alu_result[2]~422_BDD281 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|M_alu_result[3] | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|M_alu_result[3]~419_BDD272 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|M_alu_result[3]~420_BDD273 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|M_alu_result[4] | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|M_alu_result[4]~417_BDD269 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|M_alu_result[4]~418_BDD270 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|M_alu_result[5] | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|M_alu_result[5]~415_BDD210 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|M_alu_result[5]~416_BDD211 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|M_alu_result[6] | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|M_alu_result[6]~413_BDD208 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|M_alu_result[6]~414_BDD209 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|M_alu_result[20]~318 | Deleted | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|M_alu_result[20]~319 | Retimed Register | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|M_alu_result[20]~407_BDD67 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|M_alu_result[20]~408_BDD68 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|M_alu_result[20]~409_BDD69 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|M_alu_result[20]~410_BDD70 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|M_alu_result[20]~411_BDD71 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|M_alu_result[21]~320 | Deleted | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|M_alu_result[21]~321 | Retimed Register | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|M_alu_result[21]~321_DUP_COMB_465 | Retimed Register | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|M_alu_result[21]~401_BDD60 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|M_alu_result[21]~402_BDD61 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|M_alu_result[21]~403_BDD62 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|M_alu_result[21]~404_BDD63 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|M_alu_result[21]~405_BDD64 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|M_alu_result[22]~336 | Deleted | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|M_alu_result[22]~337 | Retimed Register | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|M_alu_result[22]~337_DUP_COMB_463 | Retimed Register | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|M_alu_result[22]~395_BDD54 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|M_alu_result[22]~396_BDD55 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|M_alu_result[22]~397_BDD56 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|M_alu_result[22]~398_BDD57 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|M_alu_result[22]~399_BDD58 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|M_alu_result[23]~334 | Deleted | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|M_alu_result[23]~335 | Retimed Register | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|M_alu_result[23]~335_DUP_COMB_461 | Retimed Register | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|M_alu_result[23]~381_BDD40 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|M_alu_result[23]~382_BDD41 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|M_alu_result[23]~383_BDD42 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|M_alu_result[23]~384_BDD43 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|M_alu_result[23]~385_BDD44 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|M_alu_result[24]~322 | Deleted | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|M_alu_result[24]~323 | Retimed Register | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|M_alu_result[24]~323_DUP_COMB_459 | Retimed Register | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|M_alu_result[24]~375_BDD25 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|M_alu_result[24]~376_BDD26 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|M_alu_result[24]~377_BDD27 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|M_alu_result[24]~378_BDD28 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|M_alu_result[24]~379_BDD29 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|M_alu_result[25]~324 | Deleted | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|M_alu_result[25]~325 | Retimed Register | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|M_alu_result[25]~325_DUP_COMB_457 | Retimed Register | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|M_alu_result[25]~369_BDD19 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|M_alu_result[25]~370_BDD20 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|M_alu_result[25]~371_BDD21 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|M_alu_result[25]~372_BDD22 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|M_alu_result[25]~373_BDD23 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|M_alu_result[26]~326 | Deleted | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|M_alu_result[26]~327 | Retimed Register | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|M_alu_result[26]~354_BDD1 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|M_alu_result[26]~423_BDD470 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|M_alu_result[26]~424_BDD471 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|M_alu_result[26]~425_BDD472 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|M_alu_result[26]~426_BDD473 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|M_alu_result[26]~427_BDD474 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|M_alu_result[26]~428_BDD475 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|M_alu_result[26]~429_BDD476 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|M_alu_result[26]~430_BDD477 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|M_alu_result[27]~328 | Deleted | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|M_alu_result[27]~329 | Retimed Register | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|M_alu_result[27]~358_BDD5 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|M_alu_result[27]~431_BDD478 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|M_alu_result[27]~432_BDD479 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|M_alu_result[27]~433_BDD480 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|M_alu_result[27]~434_BDD481 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|M_alu_result[27]~435_BDD482 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|M_alu_result[27]~436_BDD483 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|M_alu_result[27]~437_BDD484 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|M_alu_result[27]~438_BDD485 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|M_alu_result[28]~330 | Deleted | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|M_alu_result[28]~331 | Retimed Register | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|M_alu_result[28]~366_BDD13 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|M_alu_result[28]~439_BDD486 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|M_alu_result[28]~440_BDD487 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|M_alu_result[28]~441_BDD488 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|M_alu_result[28]~442_BDD489 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|M_alu_result[28]~443_BDD490 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|M_alu_result[28]~444_BDD491 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|M_alu_result[28]~445_BDD492 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|M_alu_result[28]~446_BDD493 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|M_alu_result[29]~332 | Deleted | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|M_alu_result[29]~333 | Retimed Register | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|M_alu_result[29]~362_BDD9 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|M_alu_result[29]~447_BDD494 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|M_alu_result[29]~448_BDD495 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|M_alu_result[29]~449_BDD496 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|M_alu_result[29]~450_BDD497 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|M_alu_result[29]~451_BDD498 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|M_alu_result[29]~452_BDD499 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|M_alu_result[29]~453_BDD500 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|M_alu_result[29]~454_BDD501 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|M_alu_result[30]~299 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|M_alu_result[30]~300 | Retimed Register | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|M_alu_result[30]~308_DUP_COMB | Retimed Register | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|M_alu_result[30]~313 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|M_alu_result[30]~316 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|M_alu_result[30]~391_BDD50 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|M_alu_result[30]~392_BDD51 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|M_alu_result[30]~393_BDD52 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|M_alu_result[30]~394_BDD53 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|M_alu_result[30]~_DUP_COMB | Retimed Register | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|M_alu_result[31]~297 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|M_alu_result[31]~298 | Retimed Register | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|M_alu_result[31]~302 | Retimed Register | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|M_alu_result[31]~305_DUP_COMB | Retimed Register | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|M_alu_result[31]~309 | Retimed Register | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|M_alu_result[31]~314 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|M_alu_result[31]~317 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|M_alu_result[31]~387_BDD46 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|M_alu_result[31]~388_BDD47 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|M_alu_result[31]~389_BDD48 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|M_alu_result[31]~390_BDD49 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|M_alu_result[31]~_DUP_COMB | Retimed Register | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|M_bstatus_reg~4 | Retimed Register | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|M_bstatus_reg~10 | Retimed Register | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|M_bstatus_reg~_DUP_COMB | Retimed Register | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|M_ctrl_shift_rot~4 | Retimed Register | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|M_estatus_reg~4 | Retimed Register | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|M_estatus_reg~8 | Retimed Register | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|M_estatus_reg~_DUP_COMB | Retimed Register | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|M_ienable_reg[1] | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|M_ienable_reg[1]~697_BDD581 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|M_ienable_reg[1]~698_BDD582 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|M_ienable_reg[1]~699_BDD583 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|M_ienable_reg[1]~700_BDD584 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|M_ienable_reg[1]~701_BDD585 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|M_ienable_reg[2]~686 | Deleted | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|M_ienable_reg[2]~687 | Retimed Register | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|M_ienable_reg[3]~684 | Deleted | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|M_ienable_reg[3]~685 | Retimed Register | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|M_ienable_reg[4]~682 | Deleted | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|M_ienable_reg[4]~683 | Retimed Register | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|M_ienable_reg[5]~680 | Deleted | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|M_ienable_reg[5]~681 | Retimed Register | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|M_ienable_reg[5]~695_BDD506 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|M_ienable_reg[5]~696_BDD507 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|M_ienable_reg[6]~678 | Deleted | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|M_ienable_reg[6]~679 | Retimed Register | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|M_ienable_reg[6]~693_BDD504 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|M_ienable_reg[6]~694_BDD505 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|M_ipending_reg[2] | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|M_ipending_reg[3] | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|M_ipending_reg[4] | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|M_ipending_reg[5] | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|M_ipending_reg[6] | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|M_mem_byte_en[0]~126 | Retimed Register | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|M_mem_byte_en[0]~126_DUP_COMB | Retimed Register | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|M_mem_byte_en[0]~127 | Deleted | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|M_mem_byte_en[0]~139_BDD128 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|M_mem_byte_en[0]~140_BDD129 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|M_mem_byte_en[1]~124 | Retimed Register | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|M_mem_byte_en[1]~124_DUP_COMB | Retimed Register | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|M_mem_byte_en[1]~125 | Deleted | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|M_mem_byte_en[1]~132_DUP_COMB | Retimed Register | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|M_mem_byte_en[1]~137_BDD125 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|M_mem_byte_en[1]~138_BDD126 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|M_mem_byte_en[2]~122 | Retimed Register | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|M_mem_byte_en[2]~122_DUP_COMB | Retimed Register | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|M_mem_byte_en[2]~123 | Deleted | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|M_mem_byte_en[2]~135_BDD102 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|M_mem_byte_en[2]~136_BDD103 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|M_mem_byte_en[3]~120 | Retimed Register | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|M_mem_byte_en[3]~120_DUP_COMB | Retimed Register | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|M_mem_byte_en[3]~121 | Deleted | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|M_mem_byte_en[3]~133_BDD91 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|M_mem_byte_en[3]~134_BDD92 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|M_pipe_flush | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|M_pipe_flush~40_BDD239 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|M_pipe_flush~41_BDD240 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|M_shift_rot_cnt[0] | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|M_st_data[8]~116 | Retimed Register | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|M_st_data[8]~_DUP_COMB | Retimed Register | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|M_st_data[8]~_DUP_COMB_116 | Retimed Register | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|M_st_data[9]~119 | Retimed Register | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|M_st_data[9]~_DUP_COMB | Retimed Register | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|M_st_data[9]~_DUP_COMB_119 | Retimed Register | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|M_st_data[10]~158 | Retimed Register | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|M_st_data[10]~_DUP_COMB | Retimed Register | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|M_st_data[10]~_DUP_COMB_158 | Retimed Register | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|M_st_data[11]~146 | Retimed Register | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|M_st_data[11]~_DUP_COMB | Retimed Register | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|M_st_data[11]~_DUP_COMB_146 | Retimed Register | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|M_st_data[12]~155 | Retimed Register | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|M_st_data[12]~_DUP_COMB | Retimed Register | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|M_st_data[12]~_DUP_COMB_155 | Retimed Register | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|M_st_data[13]~152 | Retimed Register | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|M_st_data[13]~_DUP_COMB | Retimed Register | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|M_st_data[13]~_DUP_COMB_152 | Retimed Register | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|M_st_data[14]~149 | Retimed Register | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|M_st_data[14]~_DUP_COMB | Retimed Register | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|M_st_data[14]~_DUP_COMB_149 | Retimed Register | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|M_st_data[15]~122 | Retimed Register | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|M_st_data[15]~_DUP_COMB | Retimed Register | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|M_st_data[15]~_DUP_COMB_122 | Retimed Register | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|M_st_data[16]~134 | Retimed Register | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|M_st_data[16]~_DUP_COMB_134 | Retimed Register | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|M_st_data[17]~131 | Retimed Register | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|M_st_data[17]~_DUP_COMB_131 | Retimed Register | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|M_st_data[18]~137 | Retimed Register | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|M_st_data[18]~_DUP_COMB_137 | Retimed Register | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|M_st_data[19]~140 | Retimed Register | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|M_st_data[19]~_DUP_COMB_140 | Retimed Register | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|M_st_data[20]~128 | Retimed Register | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|M_st_data[20]~_DUP_COMB_128 | Retimed Register | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|M_st_data[21]~143 | Retimed Register | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|M_st_data[21]~_DUP_COMB_143 | Retimed Register | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|M_st_data[22]~113 | Retimed Register | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|M_st_data[22]~_DUP_COMB_113 | Retimed Register | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|M_st_data[23]~125 | Retimed Register | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|M_st_data[23]~_DUP_COMB_125 | Retimed Register | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|M_valid_from_E | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|M_valid_from_E~8_BDD444 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|M_wr_data_unfiltered[30]~3746_BDD118 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|M_wr_data_unfiltered[30]~3747_BDD119 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|M_wr_data_unfiltered[30]~3748_BDD120 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|M_wr_data_unfiltered[30]~3749_BDD121 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|M_wr_data_unfiltered[30]~3750_BDD122 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|M_wr_data_unfiltered[31]~3741_BDD113 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|M_wr_data_unfiltered[31]~3742_BDD114 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|M_wr_data_unfiltered[31]~3743_BDD115 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|M_wr_data_unfiltered[31]~3744_BDD116 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|M_wr_data_unfiltered[31]~3745_BDD117 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|av_ld_data_aligned_or_div[30]~85 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|av_ld_data_aligned_or_div[31]~87 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|DRsize[1] | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|DRsize[2] | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|internal_jdo1[25] | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_avalon_reg:the_cpu_nios2_avalon_reg|Equal0~71 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_avalon_reg:the_cpu_nios2_avalon_reg|Equal0~72 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_avalon_reg:the_cpu_nios2_avalon_reg|Equal0~74_BDD445 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_avalon_reg:the_cpu_nios2_avalon_reg|Equal0~75_BDD446 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_avalon_reg:the_cpu_nios2_avalon_reg|Equal0~76_BDD447 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_avalon_reg:the_cpu_nios2_avalon_reg|Equal0~77_BDD448 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_avalon_reg:the_cpu_nios2_avalon_reg|internal_oci_ienable1[0]~656 | Retimed Register | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_avalon_reg:the_cpu_nios2_avalon_reg|internal_oci_ienable1[0]~657 | Deleted | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_avalon_reg:the_cpu_nios2_avalon_reg|internal_oci_ienable1[0]~670_BDD202 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_avalon_reg:the_cpu_nios2_avalon_reg|internal_oci_ienable1[1]~658 | Retimed Register | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_avalon_reg:the_cpu_nios2_avalon_reg|internal_oci_ienable1[1]~659 | Deleted | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_avalon_reg:the_cpu_nios2_avalon_reg|internal_oci_ienable1[2]~668 | Retimed Register | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_avalon_reg:the_cpu_nios2_avalon_reg|internal_oci_ienable1[2]~669 | Deleted | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_avalon_reg:the_cpu_nios2_avalon_reg|internal_oci_ienable1[3]~666 | Retimed Register | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_avalon_reg:the_cpu_nios2_avalon_reg|internal_oci_ienable1[3]~667 | Deleted | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_avalon_reg:the_cpu_nios2_avalon_reg|internal_oci_ienable1[4]~660 | Retimed Register | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_avalon_reg:the_cpu_nios2_avalon_reg|internal_oci_ienable1[4]~661 | Deleted | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_avalon_reg:the_cpu_nios2_avalon_reg|internal_oci_ienable1[5]~664 | Retimed Register | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_avalon_reg:the_cpu_nios2_avalon_reg|internal_oci_ienable1[5]~665 | Deleted | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_avalon_reg:the_cpu_nios2_avalon_reg|internal_oci_ienable1[6]~662 | Retimed Register | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_avalon_reg:the_cpu_nios2_avalon_reg|internal_oci_ienable1[6]~663 | Deleted | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_debug:the_cpu_nios2_oci_debug|internal_monitor_ready | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_debug:the_cpu_nios2_oci_debug|internal_monitor_ready~123_BDD241 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_debug:the_cpu_nios2_oci_debug|internal_monitor_ready~124_BDD242 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|Add0~132 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|MonAReg~1144 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|readdata[3]~1373_BDD293 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|d_readdata_d1[0]~95 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|d_readdata_d1[0]~96 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|d_readdata_d1[0]~204_BDD350 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|d_readdata_d1[0]~205_BDD351 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|d_readdata_d1[0]~206_BDD352 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|d_readdata_d1[0]~207_BDD353 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|d_readdata_d1[0]~208_BDD560 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|d_readdata_d1[0]~209_BDD561 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|d_readdata_d1[0]~210_BDD562 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|d_readdata_d1[1]~94 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|d_readdata_d1[1]~200_BDD306 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|d_readdata_d1[1]~201_BDD307 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|d_readdata_d1[1]~202_BDD308 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|d_readdata_d1[1]~203_BDD309 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|d_readdata_d1[2]~86 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|d_readdata_d1[2]~180_BDD215 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|d_readdata_d1[2]~181_BDD216 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|d_readdata_d1[2]~182_BDD217 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|d_readdata_d1[2]~183_BDD218 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|d_readdata_d1[3]~87 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|d_readdata_d1[3]~184_BDD219 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|d_readdata_d1[3]~185_BDD220 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|d_readdata_d1[3]~186_BDD221 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|d_readdata_d1[3]~187_BDD222 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|d_readdata_d1[4]~92 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|d_readdata_d1[4]~196_BDD264 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|d_readdata_d1[4]~197_BDD265 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|d_readdata_d1[4]~198_BDD266 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|d_readdata_d1[4]~199_BDD267 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|d_readdata_d1[5]~90 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|d_readdata_d1[5]~192_BDD227 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|d_readdata_d1[5]~193_BDD228 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|d_readdata_d1[5]~194_BDD229 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|d_readdata_d1[5]~195_BDD230 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|d_readdata_d1[6]~88 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|d_readdata_d1[6]~188_BDD223 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|d_readdata_d1[6]~189_BDD224 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|d_readdata_d1[6]~190_BDD225 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|d_readdata_d1[6]~191_BDD226 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|d_readdata_d1[7]~112 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|d_readdata_d1[8]~107 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|d_readdata_d1[8]~107_DUP_COMB | Retimed Register | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|d_readdata_d1[8]~109 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|i_readdata_d1[0]~131 | Retimed Register | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|i_readdata_d1[0]~164 | Retimed Register | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|i_readdata_d1[0]~165 | Retimed Register | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|i_readdata_d1[1]~128 | Retimed Register | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|i_readdata_d1[1]~161 | Retimed Register | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|i_readdata_d1[1]~162 | Retimed Register | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|i_readdata_d1[1]~163 | Retimed Register | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|i_readdata_d1[2]~94 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|i_readdata_d1[2]~137 | Retimed Register | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|i_readdata_d1[2]~166 | Retimed Register | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|i_readdata_d1[2]~167 | Retimed Register | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|i_readdata_d1[2]~178_BDD362 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|i_readdata_d1[2]~179_BDD363 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|i_readdata_d1[2]~180_BDD364 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|i_readdata_d1[2]~181_BDD365 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|i_readdata_d1[3]~96 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|i_readdata_d1[3]~97 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|i_readdata_d1[3]~134 | Retimed Register | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|i_readdata_d1[3]~135 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|i_readdata_d1[3]~182_BDD366 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|i_readdata_d1[3]~183_BDD367 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|i_readdata_d1[3]~184_BDD368 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|i_readdata_d1[3]~185_BDD369 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|i_readdata_d1[4]~86 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|i_readdata_d1[4]~174_BDD358 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|i_readdata_d1[4]~175_BDD359 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|i_readdata_d1[4]~176_BDD360 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|i_readdata_d1[4]~177_BDD361 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|i_readdata_d1[5]~88 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|i_readdata_d1[5]~186_BDD370 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|i_readdata_d1[5]~187_BDD371 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|i_readdata_d1[5]~188_BDD372 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|i_readdata_d1[5]~189_BDD373 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|i_readdata_d1[6]~99 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|i_readdata_d1[6]~100 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|i_readdata_d1[6]~168_BDD331 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|i_readdata_d1[6]~169_BDD332 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|i_readdata_d1[6]~170_BDD354 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|i_readdata_d1[6]~171_BDD355 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|i_readdata_d1[6]~172_BDD356 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|i_readdata_d1[6]~173_BDD357 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|i_readdata_d1[9]~145 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|i_readdata_d1[10]~141 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|i_readdata_d1[10]~142_DUP_COMB | Retimed Register | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|i_readdata_d1[15]~148 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|ic_fill_ap_cnt[0]~23 | Retimed Register | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|ic_fill_ap_cnt[0]~24_DUP_COMB_56 | Retimed Register | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|ic_fill_ap_cnt[0]~45 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|ic_fill_ap_cnt[0]~45_DUP_COMB_57 | Retimed Register | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|ic_fill_ap_cnt[1]~26 | Retimed Register | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|ic_fill_ap_cnt[2]~28 | Retimed Register | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|ic_fill_ap_cnt[3]~30 | Retimed Register | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|ic_fill_req_accepted | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|ic_fill_req_accepted~19_BDD171 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|ic_fill_tag[0]~77 | Retimed Register | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|ic_fill_tag[0]~100 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|ic_fill_tag[1]~78 | Retimed Register | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|ic_fill_tag[2]~70 | Retimed Register | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|ic_fill_tag[3]~69 | Retimed Register | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|ic_fill_tag[4]~61 | Retimed Register | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|ic_fill_tag[4]~68 | Retimed Register | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|ic_fill_tag[4]~83 | Retimed Register | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|ic_fill_tag[4]~84 | Deleted | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|ic_fill_tag[5]~101 | Retimed Register | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|ic_fill_tag[6]~63 | Retimed Register | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|ic_fill_tag[6]~79 | Retimed Register | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|ic_fill_tag[6]~94_DUP_COMB | Retimed Register | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|ic_fill_tag[8] | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|ic_fill_tag[8]~87 | Retimed Register | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|ic_fill_tag[9]~62 | Retimed Register | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|ic_fill_tag[9]~64 | Retimed Register | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|ic_fill_tag[9]~81 | Retimed Register | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|ic_fill_tag[9]~85 | Retimed Register | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|ic_fill_tag[9]~97 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|ic_fill_tag[9]~98 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|ic_fill_tag[11]~66 | Retimed Register | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|ic_fill_tag[12]~65 | Retimed Register | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|ic_fill_tag[13]~67 | Retimed Register | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|internal_d_write~69_DUP_COMB_80 | Retimed Register | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|internal_d_write~70 | Retimed Register | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|internal_d_write~77_BDD66 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|internal_i_read~2 | Deleted | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|internal_i_read~2_DUP_COMB | Retimed Register | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu:the_cpu|internal_i_read~3 | Retimed Register | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|A_WE_StdLogicVector~1430 | Deleted | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|A_WE_StdLogicVector~1431 | Deleted | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|A_WE_StdLogicVector~1437 | Deleted | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|A_WE_StdLogicVector~1439 | Deleted | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|A_WE_StdLogicVector~1440 | Deleted | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|A_WE_StdLogicVector~1441 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|A_WE_StdLogicVector~1445 | Deleted | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|A_WE_StdLogicVector~1446 | Deleted | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|A_WE_StdLogicVector~1448_BDD167 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|A_WE_StdLogicVector~1449_BDD168 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|A_WE_StdLogicVector~1450_BDD169 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|A_WE_StdLogicVector~1451_BDD170 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[0]~5319 | Deleted | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[0]~5320 | Deleted | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[0]~5321 | Deleted | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[0]~5322 | Deleted | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[0]~5324 | Deleted | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[0]~5325 | Deleted | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[0]~5326 | Deleted | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[1]~5328 | Deleted | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[1]~5331 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[1]~5332 | Deleted | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[1]~5334 | Deleted | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[1]~5386_BDD428 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[2]~5162 | Deleted | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[2]~5163 | Deleted | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[2]~5164 | Deleted | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[2]~5165 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[2]~5166 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[2]~5168 | Deleted | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[2]~5169 | Deleted | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[2]~5339_BDD205 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[2]~5388_BDD434 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[2]~5389_BDD435 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[2]~5390_BDD436 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[3]~5178 | Deleted | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[3]~5179 | Deleted | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[3]~5182 | Deleted | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[3]~5183 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[3]~5184 | Deleted | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[3]~5185 | Deleted | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[3]~5350_BDD297 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[3]~5351_BDD298 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[4]~5303 | Deleted | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[4]~5304 | Deleted | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[4]~5306 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[4]~5307 | Deleted | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[4]~5309 | Deleted | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[4]~5387_BDD429 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[5]~5311 | Deleted | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[5]~5313 | Deleted | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[5]~5314 | Deleted | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[5]~5315 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[5]~5316 | Deleted | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[5]~5317 | Deleted | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[5]~5348_BDD291 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[5]~5349_BDD292 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[6]~5295 | Deleted | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[6]~5296 | Deleted | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[6]~5298 | Deleted | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[6]~5299 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[6]~5300 | Deleted | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[6]~5301 | Deleted | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[6]~5346_BDD289 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[6]~5347_BDD290 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[7]~5204 | Deleted | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[7]~5205 | Deleted | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[7]~5207 | Deleted | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[7]~5208 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[7]~5209 | Deleted | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[7]~5210 | Deleted | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[7]~5340_BDD231 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[7]~5341_BDD232 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[7]~5342_BDD233 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[7]~5343_BDD234 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[7]~5344_BDD287 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[7]~5345_BDD288 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[8]~5287 | Deleted | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[8]~5289 | Deleted | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[8]~5293 | Deleted | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[8]~5352_BDD374 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[8]~5353_BDD375 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[8]~5354_BDD376 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[11]~5236 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[11]~5391_BDD579 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[12]~5224 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[12]~5355_BDD397 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[16]~5221 | Deleted | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[16]~5222 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[16]~5370_BDD412 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[16]~5371_BDD413 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[17]~5255 | Deleted | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[17]~5256 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[17]~5376_BDD418 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[17]~5377_BDD419 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[18]~5175 | Deleted | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[18]~5176 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[18]~5356_BDD398 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[18]~5357_BDD399 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[19]~5188 | Deleted | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[19]~5189 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[19]~5358_BDD400 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[19]~5359_BDD401 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[20]~5261 | Deleted | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[20]~5262 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[20]~5380_BDD422 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[20]~5381_BDD423 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[21]~5215 | Deleted | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[21]~5216 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[21]~5366_BDD408 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[21]~5367_BDD409 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[22]~5192 | Deleted | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[22]~5193 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[22]~5360_BDD402 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[22]~5361_BDD403 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[23]~5200 | Deleted | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[23]~5201 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[23]~5362_BDD404 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[23]~5363_BDD405 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[24]~5218 | Deleted | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[24]~5219 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[24]~5368_BDD410 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[24]~5369_BDD411 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[25]~5258 | Deleted | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[25]~5259 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[25]~5378_BDD420 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[25]~5379_BDD421 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[26]~5279 | Deleted | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[26]~5280 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[26]~5384_BDD426 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[26]~5385_BDD427 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[27]~5270 | Deleted | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[27]~5271 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[27]~5382_BDD424 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[27]~5383_BDD425 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[28]~5252 | Deleted | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[28]~5253 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[28]~5374_BDD416 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[28]~5375_BDD417 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[29]~5243 | Deleted | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[29]~5244 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[29]~5372_BDD414 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[29]~5373_BDD415 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[31]~5212 | Deleted | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[31]~5213 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[31]~5364_BDD406 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[31]~5365_BDD407 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata~335 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata~336 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata~337 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata~338 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|dbs_8_reg_segment_0[0]~746 | Retimed Register | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|dbs_8_reg_segment_0[1]~744 | Retimed Register | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|dbs_8_reg_segment_0[2]~750 | Retimed Register | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|dbs_8_reg_segment_0[2]~756 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|dbs_8_reg_segment_0[3]~749 | Retimed Register | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|dbs_8_reg_segment_0[3]~758 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|dbs_8_reg_segment_0[4]~745 | Retimed Register | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|dbs_8_reg_segment_0[5]~747 | Retimed Register | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|dbs_8_reg_segment_0[5]~762 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|dbs_8_reg_segment_0[6]~748 | Retimed Register | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|dbs_8_reg_segment_0[6]~760 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|dbs_8_reg_segment_0[7]~751 | Retimed Register | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|dbs_8_reg_segment_0[7]~754 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|dbs_8_reg_segment_1[0]~747 | Retimed Register | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|dbs_8_reg_segment_1[0]~766 | Retimed Register | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|dbs_8_reg_segment_1[1]~745 | Retimed Register | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|dbs_8_reg_segment_1[1]~772 | Retimed Register | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|dbs_8_reg_segment_1[2]~744 | Retimed Register | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|dbs_8_reg_segment_1[2]~775 | Retimed Register | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|dbs_8_reg_segment_1[3]~748 | Retimed Register | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|dbs_8_reg_segment_1[3]~763 | Retimed Register | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|dbs_8_reg_segment_1[3]~764 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|dbs_8_reg_segment_1[4]~749 | Retimed Register | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|dbs_8_reg_segment_1[4]~760 | Retimed Register | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|dbs_8_reg_segment_1[4]~761 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|dbs_8_reg_segment_1[5]~750 | Retimed Register | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|dbs_8_reg_segment_1[5]~757 | Retimed Register | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|dbs_8_reg_segment_1[5]~758 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|dbs_8_reg_segment_1[6]~751 | Retimed Register | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|dbs_8_reg_segment_1[6]~753 | Retimed Register | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|dbs_8_reg_segment_1[6]~755 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|dbs_8_reg_segment_1[7]~746 | Retimed Register | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|dbs_8_reg_segment_1[7]~769 | Retimed Register | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|dbs_8_reg_segment_2[0]~746 | Retimed Register | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|dbs_8_reg_segment_2[0]~764 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|dbs_8_reg_segment_2[1]~745 | Retimed Register | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|dbs_8_reg_segment_2[1]~766 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|dbs_8_reg_segment_2[2]~751 | Retimed Register | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|dbs_8_reg_segment_2[2]~754 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|dbs_8_reg_segment_2[3]~750 | Retimed Register | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|dbs_8_reg_segment_2[3]~756 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|dbs_8_reg_segment_2[4]~744 | Retimed Register | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|dbs_8_reg_segment_2[4]~768 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|dbs_8_reg_segment_2[5]~747 | Retimed Register | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|dbs_8_reg_segment_2[5]~762 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|dbs_8_reg_segment_2[6]~749 | Retimed Register | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|dbs_8_reg_segment_2[6]~758 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|dbs_8_reg_segment_2[7]~748 | Retimed Register | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|dbs_8_reg_segment_2[7]~760 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|internal_cpu_data_master_dbs_address[0] | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|internal_cpu_data_master_dbs_address[0]~61_BDD135 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|internal_cpu_data_master_dbs_address[0]~62_BDD136 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|internal_cpu_data_master_dbs_address[0]~_DUP_COMB | Retimed Register | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|internal_cpu_data_master_dbs_address[1]~55_DUP_COMB | Retimed Register | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|internal_cpu_data_master_dbs_address[1]~_DUP_COMB | Retimed Register | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|internal_cpu_data_master_waitrequest | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|internal_cpu_data_master_waitrequest~26_BDD303 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|internal_cpu_data_master_waitrequest~29_BDD615 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|internal_cpu_data_master_waitrequest~30_BDD616 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|internal_cpu_data_master_waitrequest~31_BDD617 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|internal_cpu_data_master_waitrequest~_DUP_COMB | Retimed Register | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|p1_registered_cpu_data_master_readdata~49 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|p1_registered_cpu_data_master_readdata~50 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|p1_registered_cpu_data_master_readdata~2087 | Deleted | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|p1_registered_cpu_data_master_readdata~2092_BDD203 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|p1_registered_cpu_data_master_readdata~2093_BDD204 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|r_1~241 | Retimed Register | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|r_2~102 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|r_2~103_BDD590 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_read_but_no_slave_selected~59_DUP_COMB | Retimed Register | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_read_but_no_slave_selected~62_DUP_COMB | Retimed Register | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_readdata[2]~2440 | Deleted | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_readdata[3]~2443 | Deleted | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_readdata[4]~2428 | Deleted | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_readdata[5]~2446 | Deleted | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_readdata[6]~2425 | Deleted | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_readdata[9]~2493 | Deleted | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_readdata[9]~2540_BDD340 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_readdata[9]~2541_BDD341 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_readdata[9]~2542_BDD342 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_readdata[9]~2543_BDD343 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_readdata[9]~2544_BDD344 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_readdata[10]~2528 | Deleted | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_readdata[10]~2545_BDD345 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_readdata[10]~2546_BDD346 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_readdata[10]~2547_BDD347 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_readdata[10]~2548_BDD348 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_readdata[10]~2549_BDD349 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_readdata[15]~2431 | Deleted | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_readdata[15]~2535_BDD335 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_readdata[15]~2536_BDD336 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_readdata[15]~2537_BDD337 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_readdata[15]~2538_BDD338 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_readdata[15]~2539_BDD339 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_readdata~41 | Deleted | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_readdata~42 | Deleted | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_readdata~47 | Deleted | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_run~165 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_run~166 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_run~168 | Deleted | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_run~169 | Deleted | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_run~170 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_run~174 | Deleted | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_run~175_BDD153 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_run~176_BDD154 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_run~177_BDD245 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_run~178_BDD246 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_run~181_BDD249 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_run~182_BDD570 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_run~183_BDD571 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_run~184_BDD572 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|internal_cpu_instruction_master_dbs_address[1]~50 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|internal_cpu_instruction_master_dbs_address[1]~53_BDD193 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|internal_cpu_instruction_master_latency_counter[0] | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|internal_cpu_instruction_master_latency_counter[0]~27_BDD573 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|internal_cpu_instruction_master_latency_counter[0]~28_BDD574 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|internal_cpu_instruction_master_latency_counter[1]~23 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|p1_cpu_instruction_master_latency_counter[0]~149 | Deleted | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|r_0~1 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|r_0~69_BDD123 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|r_0~70_BDD124 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|r_0~71_BDD592 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|r_0~72_BDD624 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|r_2~1 | Deleted | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu_jtag_debug_module_arbitrator:the_cpu_jtag_debug_module|Add2~346 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu_jtag_debug_module_arbitrator:the_cpu_jtag_debug_module|Add2~348_BDD430 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu_jtag_debug_module_arbitrator:the_cpu_jtag_debug_module|cpu_instruction_master_qualified_request_cpu_jtag_debug_module | Deleted | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu_jtag_debug_module_arbitrator:the_cpu_jtag_debug_module|cpu_instruction_master_qualified_request_cpu_jtag_debug_module~_DUP_COMB | Retimed Register | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu_jtag_debug_module_arbitrator:the_cpu_jtag_debug_module|cpu_jtag_debug_module_address[1]~91 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu_jtag_debug_module_arbitrator:the_cpu_jtag_debug_module|cpu_jtag_debug_module_address[1]~99_BDD250 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu_jtag_debug_module_arbitrator:the_cpu_jtag_debug_module|cpu_jtag_debug_module_arb_addend[0]~755 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu_jtag_debug_module_arbitrator:the_cpu_jtag_debug_module|cpu_jtag_debug_module_arb_addend[1]~752_DUP_COMB | Retimed Register | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|cpu_jtag_debug_module_arbitrator:the_cpu_jtag_debug_module|cpu_jtag_debug_module_saved_chosen_master_vector[0]~_DUP_COMB | Retimed Register | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|A_WE_StdLogicVector~1116 | Deleted | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|A_WE_StdLogicVector~1118 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|A_WE_StdLogicVector~1128 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|A_WE_StdLogicVector~1136_BDD394 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|A_WE_StdLogicVector~1137_BDD395 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|A_WE_StdLogicVector~1138_BDD619 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|A_WE_StdLogicVector~1139_BDD622 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|A_WE_StdLogicVector~1140_BDD623 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|EOP~166 | Deleted | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|EOP~172 | Retimed Register | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|Equal0~144_BDD438 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|Equal0~145_BDD439 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|data_rd_strobe~_DUP_COMB | Retimed Register | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|data_to_cpu[0]~38_DUP_COMB | Retimed Register | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|data_to_cpu[0]~39 | Retimed Register | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|data_to_cpu[0]~40 | Retimed Register | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|data_to_cpu[0]~48 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|data_to_cpu[0]~50 | Retimed Register | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|data_to_cpu[0]~51 | Retimed Register | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|data_to_cpu[4]~43 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|data_to_cpu[4]~44 | Retimed Register | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|data_to_cpu[4]~_DUP_COMB | Retimed Register | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|data_to_cpu[5]~33 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|data_to_cpu[5]~34 | Retimed Register | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|data_to_cpu[5]~52_BDD150 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|data_to_cpu[5]~53_BDD151 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|data_to_cpu[5]~55_BDD511 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|data_to_cpu[6]~_DUP_COMB | Retimed Register | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|data_wr_strobe~_DUP_COMB | Retimed Register | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|endofpacketvalue_reg[0]~2507 | Retimed Register | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|endofpacketvalue_reg[0]~2508 | Deleted | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|endofpacketvalue_reg[1]~2505 | Retimed Register | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|endofpacketvalue_reg[1]~2506 | Deleted | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|endofpacketvalue_reg[2]~2504 | Retimed Register | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|endofpacketvalue_reg[3]~2502 | Retimed Register | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|endofpacketvalue_reg[4]~2497 | Retimed Register | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|endofpacketvalue_reg[5]~2499 | Retimed Register | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|endofpacketvalue_reg[6]~2498 | Retimed Register | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|endofpacketvalue_reg[7]~2503 | Retimed Register | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|endofpacketvalue_reg[8]~2509 | Retimed Register | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|endofpacketvalue_reg[8]~2510 | Deleted | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|endofpacketvalue_reg[9]~2511 | Retimed Register | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|endofpacketvalue_reg[9]~2512 | Deleted | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|endofpacketvalue_reg[10]~2513 | Retimed Register | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|endofpacketvalue_reg[10]~2514 | Deleted | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|endofpacketvalue_reg[11]~2515 | Retimed Register | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|endofpacketvalue_reg[11]~2516 | Deleted | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|endofpacketvalue_reg[12]~2501 | Retimed Register | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|endofpacketvalue_reg[13]~2517 | Retimed Register | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|endofpacketvalue_reg[13]~2518 | Deleted | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|endofpacketvalue_reg[14]~2496 | Retimed Register | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|endofpacketvalue_reg[15]~2500 | Retimed Register | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|epcs_slave_select_holding_reg[0]~7250 | Retimed Register | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|epcs_slave_select_holding_reg[0]~7251 | Deleted | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|epcs_slave_select_holding_reg[1]~7248 | Retimed Register | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|epcs_slave_select_holding_reg[1]~7249 | Deleted | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|epcs_slave_select_holding_reg[2]~7278 | Retimed Register | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|epcs_slave_select_holding_reg[2]~7279 | Deleted | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|epcs_slave_select_holding_reg[3]~7276 | Retimed Register | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|epcs_slave_select_holding_reg[3]~7277 | Deleted | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|epcs_slave_select_holding_reg[4]~7252 | Retimed Register | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|epcs_slave_select_holding_reg[4]~7253 | Deleted | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|epcs_slave_select_holding_reg[5]~7274 | Retimed Register | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|epcs_slave_select_holding_reg[5]~7275 | Deleted | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|epcs_slave_select_holding_reg[6]~7254 | Retimed Register | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|epcs_slave_select_holding_reg[6]~7255 | Deleted | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|epcs_slave_select_holding_reg[7]~7270 | Retimed Register | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|epcs_slave_select_holding_reg[7]~7271 | Deleted | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|epcs_slave_select_holding_reg[8]~7256 | Retimed Register | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|epcs_slave_select_holding_reg[8]~7257 | Deleted | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|epcs_slave_select_holding_reg[9]~7258 | Retimed Register | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|epcs_slave_select_holding_reg[9]~7259 | Deleted | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|epcs_slave_select_holding_reg[10]~7260 | Retimed Register | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|epcs_slave_select_holding_reg[10]~7261 | Deleted | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|epcs_slave_select_holding_reg[11]~7262 | Retimed Register | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|epcs_slave_select_holding_reg[11]~7263 | Deleted | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|epcs_slave_select_holding_reg[12]~7264 | Retimed Register | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|epcs_slave_select_holding_reg[12]~7265 | Deleted | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|epcs_slave_select_holding_reg[13]~7266 | Retimed Register | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|epcs_slave_select_holding_reg[13]~7267 | Deleted | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|epcs_slave_select_holding_reg[14]~7268 | Retimed Register | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|epcs_slave_select_holding_reg[14]~7269 | Deleted | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|epcs_slave_select_holding_reg[15]~7272 | Retimed Register | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|epcs_slave_select_holding_reg[15]~7273 | Deleted | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|epcs_slave_select_reg[0]~2505 | Retimed Register | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|epcs_slave_select_reg[1]~2509 | Retimed Register | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|epcs_slave_select_reg[2]~2510 | Retimed Register | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|epcs_slave_select_reg[3]~2514 | Retimed Register | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|epcs_slave_select_reg[4]~2511 | Retimed Register | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|epcs_slave_select_reg[5]~2515 | Retimed Register | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|epcs_slave_select_reg[6]~2512 | Retimed Register | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|epcs_slave_select_reg[7]~2513 | Retimed Register | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|epcs_slave_select_reg[8]~2506 | Retimed Register | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|epcs_slave_select_reg[9]~2507 | Retimed Register | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|epcs_slave_select_reg[10]~2508 | Retimed Register | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|epcs_slave_select_reg[11]~2516 | Retimed Register | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|epcs_slave_select_reg[11]~2517 | Deleted | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|epcs_slave_select_reg[12]~2518 | Retimed Register | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|epcs_slave_select_reg[12]~2519 | Deleted | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|epcs_slave_select_reg[13]~2520 | Retimed Register | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|epcs_slave_select_reg[13]~2521 | Deleted | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|epcs_slave_select_reg[14]~2522 | Retimed Register | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|epcs_slave_select_reg[14]~2523 | Deleted | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|epcs_slave_select_reg[15]~2524 | Retimed Register | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|epcs_slave_select_reg[15]~2525 | Deleted | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|p1_data_to_cpu[0]~873 | Deleted | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|p1_data_to_cpu[5]~869 | Deleted | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|p1_data_to_cpu[5]~870 | Deleted | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|p1_data_to_cpu[5]~871 | Deleted | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|p1_wr_strobe~41 | Deleted | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|rd_strobe~_DUP_COMB | Retimed Register | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|rx_holding_reg[0]~2396 | Retimed Register | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|wr_strobe~_DUP_COMB | Retimed Register | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|epcs_controller_epcs_control_port_arbitrator:the_epcs_controller_epcs_control_port|Add2~344 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|epcs_controller_epcs_control_port_arbitrator:the_epcs_controller_epcs_control_port|Add2~345_BDD587 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|epcs_controller_epcs_control_port_arbitrator:the_epcs_controller_epcs_control_port|cpu_instruction_master_requests_epcs_controller_epcs_control_port~67 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|epcs_controller_epcs_control_port_arbitrator:the_epcs_controller_epcs_control_port|cpu_instruction_master_requests_epcs_controller_epcs_control_port~69_BDD194 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|epcs_controller_epcs_control_port_arbitrator:the_epcs_controller_epcs_control_port|cpu_instruction_master_requests_epcs_controller_epcs_control_port~70_BDD195 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|epcs_controller_epcs_control_port_arbitrator:the_epcs_controller_epcs_control_port|d1_reasons_to_wait | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|epcs_controller_epcs_control_port_arbitrator:the_epcs_controller_epcs_control_port|d1_reasons_to_wait~12_BDD449 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|epcs_controller_epcs_control_port_arbitrator:the_epcs_controller_epcs_control_port|d1_reasons_to_wait~13_BDD450 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|epcs_controller_epcs_control_port_arbitrator:the_epcs_controller_epcs_control_port|d1_reasons_to_wait~14_BDD451 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|epcs_controller_epcs_control_port_arbitrator:the_epcs_controller_epcs_control_port|epcs_controller_epcs_control_port_address[0]~74_BDD268 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|epcs_controller_epcs_control_port_arbitrator:the_epcs_controller_epcs_control_port|epcs_controller_epcs_control_port_address[1]~69 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|epcs_controller_epcs_control_port_arbitrator:the_epcs_controller_epcs_control_port|epcs_controller_epcs_control_port_address[1]~75_BDD563 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|epcs_controller_epcs_control_port_arbitrator:the_epcs_controller_epcs_control_port|epcs_controller_epcs_control_port_arb_addend[0] | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|epcs_controller_epcs_control_port_arbitrator:the_epcs_controller_epcs_control_port|epcs_controller_epcs_control_port_arb_addend[0]~742 | Deleted | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|epcs_controller_epcs_control_port_arbitrator:the_epcs_controller_epcs_control_port|epcs_controller_epcs_control_port_arb_addend[1] | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|epcs_controller_epcs_control_port_arbitrator:the_epcs_controller_epcs_control_port|epcs_controller_epcs_control_port_arb_addend[1]~741 | Deleted | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|A_WE_StdLogicVector~4283 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|A_WE_StdLogicVector~4288 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|A_WE_StdLogicVector~4295_BDD296 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|A_WE_StdLogicVector~4296_BDD300 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|A_WE_StdLogicVector~4297_BDD301 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|A_WE_StdLogicVector~4298_BDD508 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|A_WE_StdLogicVector~4299_BDD509 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|A_WE_StdLogicVector~4300_BDD510 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|Add2~306 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|Equal3~105 | Deleted | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|Equal3~106 | Deleted | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|Equal3~107 | Deleted | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|LessThan1~92 | Retimed Register | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|cpu_data_master_continuerequest~105_BDD610 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|cpu_data_master_continuerequest~106_BDD611 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|cpu_data_master_qualified_request_ext_flash_s1~151 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|cpu_data_master_qualified_request_ext_ram_s1~140 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|cpu_data_master_qualified_request_ext_ram_s1~142 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|cpu_data_master_qualified_request_ext_ram_s1~145_BDD440 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|cpu_data_master_qualified_request_ext_ram_s1~146_BDD441 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|cpu_data_master_qualified_request_lan91c111_s1~128 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|cpu_data_master_read_data_valid_ext_flash_s1_shift_register[0]~23 | Retimed Register | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|cpu_data_master_read_data_valid_ext_flash_s1_shift_register[0]~_DUP_COMB | Retimed Register | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|cpu_data_master_read_data_valid_ext_flash_s1_shift_register[1] | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|cpu_data_master_read_data_valid_ext_ram_s1_shift_register[0] | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|cpu_data_master_read_data_valid_ext_ram_s1_shift_register[0]~22 | Retimed Register | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|cpu_data_master_read_data_valid_ext_ram_s1_shift_register[0]~24 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|cpu_data_master_read_data_valid_ext_ram_s1_shift_register[0]~25_BDD189 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|cpu_data_master_read_data_valid_ext_ram_s1_shift_register[1] | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|cpu_instruction_master_continuerequest~62_BDD147 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|cpu_instruction_master_continuerequest~63_BDD568 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|cpu_instruction_master_continuerequest~64_BDD569 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|cpu_instruction_master_continuerequest~65_BDD612 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|cpu_instruction_master_continuerequest~66_BDD613 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|cpu_instruction_master_continuerequest~67_BDD614 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|cpu_instruction_master_continuerequest~70_BDD627 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|cpu_instruction_master_continuerequest~72_BDD629 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|cpu_instruction_master_read_data_valid_ext_ram_s1_shift_register[0] | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|cpu_instruction_master_read_data_valid_lan91c111_s1_shift_register[0] | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|cpu_instruction_master_read_data_valid_lan91c111_s1_shift_register_in~15 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|cpu_instruction_master_read_data_valid_lan91c111_s1_shift_register_in~17_BDD172 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|cpu_instruction_master_read_data_valid_lan91c111_s1_shift_register_in~18_BDD173 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_ext_ram_bus_avalon_slave_end_xfer | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_ext_ram_bus_avalon_slave_end_xfer~3_DUP_COMB_12 | Retimed Register | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_ext_ram_bus_avalon_slave_end_xfer~4 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_ext_ram_bus_avalon_slave_end_xfer~4_DUP_COMB | Retimed Register | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_ext_ram_bus_avalon_slave_end_xfer~5_DUP_COMB | Retimed Register | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_ext_ram_bus_avalon_slave_end_xfer~6_DUP_COMB | Retimed Register | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_ext_ram_bus_avalon_slave_end_xfer~8_DUP_COMB | Retimed Register | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_ext_ram_bus_avalon_slave_end_xfer~_DUP_COMB | Retimed Register | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_in_a_write_cycle~2_BDD604 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_in_a_write_cycle~3_BDD618 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_in_a_write_cycle~COMB_OUT | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_outgoing_ext_ram_bus_data[5]~72_BDD606 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_outgoing_ext_ram_bus_data[5]~73_BDD607 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_outgoing_ext_ram_bus_data[5]~74_BDD608 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_outgoing_ext_ram_bus_data[5]~75_BDD609 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_outgoing_ext_ram_bus_data[5]~COMB_OUT | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_outgoing_ext_ram_bus_data[6]~68_BDD564 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_outgoing_ext_ram_bus_data[6]~69_BDD565 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_outgoing_ext_ram_bus_data[6]~70_BDD566 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_outgoing_ext_ram_bus_data[6]~71_BDD567 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_outgoing_ext_ram_bus_data[6]~COMB_OUT | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_outgoing_ext_ram_bus_data[7]~64_BDD283 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_outgoing_ext_ram_bus_data[7]~65_BDD284 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_outgoing_ext_ram_bus_data[7]~66_BDD285 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_outgoing_ext_ram_bus_data[7]~67_BDD286 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_outgoing_ext_ram_bus_data[7]~COMB_OUT | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_flash_s1_wait_counter[0]~95 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_flash_s1_wait_counter[0]~97 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_flash_s1_wait_counter[2]~91 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_flash_s1_wait_counter[2]~93 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_flash_s1_wait_counter[2]~104_BDD620 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_flash_s1_wait_counter[2]~105_BDD621 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_flash_s1_wait_counter[3]~86 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_flash_s1_wait_counter[3]~88 | Retimed Register | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_flash_s1_wait_counter[3]~89_DUP_COMB | Retimed Register | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_flash_s1_wait_counter[3]~102_BDD377 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_flash_s1_wait_counter[3]~103_BDD378 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_address[17]~46_BDD251 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_address[17]~47_BDD252 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_address[17]~48_BDD253 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_address[17]~55_BDD625 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_address[17]~56_BDD626 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_address[17]~COMB_OUT | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_address[21]~51_BDD276 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_address[21]~52_BDD277 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_address[21]~54_BDD603 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_address[21]~COMB_OUT | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_address[22]~49_BDD274 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_address[22]~50_BDD275 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_address[22]~53_BDD502 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_address[22]~COMB_OUT | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_avalon_slave_arb_addend[0]~679 | Deleted | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_avalon_slave_arb_addend[0]~680 | Retimed Register | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_avalon_slave_arb_addend[0]~681 | Retimed Register | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_avalon_slave_arb_addend[0]~684 | Retimed Register | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_avalon_slave_arb_addend[0]~724 | Retimed Register | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_avalon_slave_arb_addend[0]~726 | Retimed Register | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_avalon_slave_arb_addend[0]~731 | Retimed Register | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_avalon_slave_arb_addend[0]~732 | Retimed Register | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_avalon_slave_arb_addend[0]~733 | Retimed Register | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_avalon_slave_arb_addend[0]~734 | Retimed Register | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_avalon_slave_arb_addend[0]~735 | Retimed Register | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_avalon_slave_arb_addend[0]~736 | Retimed Register | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_avalon_slave_arb_addend[0]~737 | Retimed Register | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_avalon_slave_arb_addend[0]~738 | Retimed Register | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_avalon_slave_arb_addend[0]~739 | Retimed Register | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_avalon_slave_arb_addend[0]~742 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_avalon_slave_arb_addend[0]~749 | Deleted | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_avalon_slave_arb_addend[0]~750 | Retimed Register | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_avalon_slave_arb_addend[0]~751 | Retimed Register | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_avalon_slave_arb_addend[0]~751_DUP_COMB | Retimed Register | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_avalon_slave_arb_addend[0]~752 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_avalon_slave_arb_addend[0]~753 | Retimed Register | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_avalon_slave_arb_addend[0]~753_DUP_COMB | Retimed Register | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_avalon_slave_arb_addend[0]~754 | Deleted | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_avalon_slave_arb_addend[0]~755 | Retimed Register | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_avalon_slave_arb_addend[0]~755_DUP_COMB | Retimed Register | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_avalon_slave_arb_addend[0]~756 | Deleted | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_avalon_slave_arb_addend[0]~757 | Retimed Register | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_avalon_slave_arb_addend[0]~757_DUP_COMB | Retimed Register | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_avalon_slave_arb_addend[0]~758 | Deleted | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_avalon_slave_arb_addend[0]~759 | Retimed Register | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_avalon_slave_arb_addend[0]~759_DUP_COMB | Retimed Register | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_avalon_slave_arb_addend[0]~760 | Deleted | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_avalon_slave_arb_addend[0]~761 | Retimed Register | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_avalon_slave_arb_addend[0]~761_DUP_COMB | Retimed Register | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_avalon_slave_arb_addend[0]~762 | Deleted | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_avalon_slave_arb_addend[0]~763 | Retimed Register | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_avalon_slave_arb_addend[0]~763_DUP_COMB | Retimed Register | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_avalon_slave_arb_addend[0]~764 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_avalon_slave_arb_addend[0]~765 | Retimed Register | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_avalon_slave_arb_addend[0]~765_DUP_COMB | Retimed Register | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_avalon_slave_arb_addend[0]~766 | Deleted | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_avalon_slave_arb_addend[0]~795 | Retimed Register | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_avalon_slave_arb_addend[0]~795_DUP_COMB_879 | Retimed Register | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_avalon_slave_arb_addend[0]~796 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_avalon_slave_arb_addend[0]~811 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_avalon_slave_arb_addend[0]~826_BDD89 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_avalon_slave_arb_addend[0]~827_BDD90 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_avalon_slave_arb_addend[0]~828_BDD93 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_avalon_slave_arb_addend[0]~838_BDD145 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_avalon_slave_arb_addend[0]~839_BDD453 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_avalon_slave_arb_addend[0]~840_BDD454 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_avalon_slave_arb_addend[0]~841_BDD601 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_avalon_slave_arb_addend[0]~842_BDD602 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_avalon_slave_arb_addend[1]~688 | Retimed Register | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_avalon_slave_arb_addend[1]~720_DUP_COMB | Retimed Register | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_avalon_slave_arb_addend[1]~_DUP_COMB | Retimed Register | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_avalon_slave_arb_addend[1]~_DUP_COMB_688 | Retimed Register | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_avalon_slave_arb_addend[2]~697 | Retimed Register | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_avalon_slave_arb_addend[2]~711_DUP_COMB | Retimed Register | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_avalon_slave_arb_addend[2]~_DUP_COMB | Retimed Register | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_avalon_slave_arb_addend[2]~_DUP_COMB_697 | Retimed Register | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_avalon_slave_arb_addend[3]~691 | Retimed Register | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_avalon_slave_arb_addend[3]~717 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_avalon_slave_arb_addend[3]~829_BDD104 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_avalon_slave_arb_addend[3]~831_BDD106 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_avalon_slave_arb_addend[3]~_DUP_COMB | Retimed Register | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_avalon_slave_arb_addend[3]~_DUP_COMB_691 | Retimed Register | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_avalon_slave_arb_addend[4]~700 | Retimed Register | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_avalon_slave_arb_addend[4]~707_DUP_COMB | Retimed Register | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_avalon_slave_arb_addend[4]~707_DUP_COMB_862 | Retimed Register | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_avalon_slave_arb_addend[4]~708 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_avalon_slave_arb_addend[4]~743 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_avalon_slave_arb_addend[4]~835_BDD110 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_avalon_slave_arb_addend[4]~837_BDD112 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_avalon_slave_arb_addend[4]~_DUP_COMB | Retimed Register | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_avalon_slave_arb_addend[4]~_DUP_COMB_700 | Retimed Register | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_avalon_slave_arb_addend[5]~694 | Retimed Register | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_avalon_slave_arb_addend[5]~714 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_avalon_slave_arb_addend[5]~832_BDD107 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_avalon_slave_arb_addend[5]~834_BDD109 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_avalon_slave_arb_addend[5]~_DUP_COMB_694 | Retimed Register | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_avalon_slave_arb_counter_enable~20 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_avalon_slave_arb_share_counter[0]~594 | Retimed Register | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_avalon_slave_arb_share_counter[0]~605_DUP_COMB_612 | Retimed Register | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_avalon_slave_arb_share_counter[0]~606 | Retimed Register | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_avalon_slave_arb_share_counter[0]~607 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_avalon_slave_arb_share_counter[0]~608 | Retimed Register | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_avalon_slave_arb_share_counter[1]~592 | Retimed Register | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_avalon_slave_arb_winner~40_BDD469 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_avalon_slave_arbitration_holdoff_internal~10_BDD605 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_avalon_slave_begins_xfer | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_avalon_slave_begins_xfer~62_BDD503 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_avalon_slave_saved_chosen_master_vector[0] | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_avalon_slave_saved_chosen_master_vector[0]~646 | Retimed Register | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_avalon_slave_saved_chosen_master_vector[0]~669 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_avalon_slave_saved_chosen_master_vector[0]~670 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_avalon_slave_saved_chosen_master_vector[0]~673_DUP_COMB | Retimed Register | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_avalon_slave_saved_chosen_master_vector[0]~_DUP_COMB | Retimed Register | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_avalon_slave_saved_chosen_master_vector[1]~649 | Retimed Register | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_avalon_slave_saved_chosen_master_vector[1]~661 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_avalon_slave_saved_chosen_master_vector[1]~_DUP_COMB | Retimed Register | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_avalon_slave_saved_chosen_master_vector[2]~647 | Retimed Register | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_avalon_slave_saved_chosen_master_vector[2]~667 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_avalon_slave_saved_chosen_master_vector[2]~693 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_avalon_slave_saved_chosen_master_vector[2]~_DUP_COMB | Retimed Register | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_avalon_slave_saved_chosen_master_vector[3]~650 | Retimed Register | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_avalon_slave_saved_chosen_master_vector[3]~658 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_avalon_slave_saved_chosen_master_vector[3]~681_DUP_COMB_705 | Retimed Register | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_avalon_slave_saved_chosen_master_vector[3]~699 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_avalon_slave_saved_chosen_master_vector[3]~_DUP_COMB | Retimed Register | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_avalon_slave_saved_chosen_master_vector[4] | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_avalon_slave_saved_chosen_master_vector[4]~648 | Retimed Register | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_avalon_slave_saved_chosen_master_vector[4]~_DUP_COMB | Retimed Register | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_avalon_slave_saved_chosen_master_vector[5]~651 | Retimed Register | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_avalon_slave_saved_chosen_master_vector[5]~654 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_avalon_slave_saved_chosen_master_vector[5]~654_DUP_COMB_710 | Retimed Register | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_avalon_slave_saved_chosen_master_vector[5]~_DUP_COMB | Retimed Register | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_avalon_slave_slavearbiterlockenable~195_DUP_COMB | Retimed Register | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|internal_cpu_instruction_master_qualified_request_ext_ram_s1~96 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|internal_cpu_instruction_master_qualified_request_ext_ram_s1~97_BDD630 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|iow_n_to_the_lan91c111~2_BDD437 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|iow_n_to_the_lan91c111~COMB_OUT | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|lan91c111_s1_wait_counter[0]~115 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|lan91c111_s1_wait_counter[1]~101 | Retimed Register | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|lan91c111_s1_wait_counter[1]~102 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|lan91c111_s1_wait_counter[1]~104 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|lan91c111_s1_wait_counter[2]~105 | Retimed Register | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|lan91c111_s1_wait_counter[2]~111 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|last_cycle_cpu_data_master_granted_slave_ext_flash_s1~4 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|last_cycle_cpu_data_master_granted_slave_ext_flash_s1~4_DUP_COMB | Retimed Register | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|last_cycle_cpu_data_master_granted_slave_ext_flash_s1~5_DUP_COMB | Retimed Register | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|last_cycle_cpu_data_master_granted_slave_ext_flash_s1~6 | Retimed Register | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|last_cycle_cpu_data_master_granted_slave_ext_flash_s1~7 | Deleted | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|last_cycle_cpu_data_master_granted_slave_ext_flash_s1~8_DUP_COMB | Retimed Register | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|last_cycle_cpu_data_master_granted_slave_ext_flash_s1~9 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|last_cycle_cpu_data_master_granted_slave_ext_flash_s1~9_DUP_COMB | Retimed Register | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|last_cycle_cpu_data_master_granted_slave_ext_ram_s1~4 | Retimed Register | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|last_cycle_cpu_data_master_granted_slave_ext_ram_s1~5_DUP_COMB | Retimed Register | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|last_cycle_cpu_data_master_granted_slave_ext_ram_s1~7_DUP_COMB | Retimed Register | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|last_cycle_cpu_data_master_granted_slave_ext_ram_s1~9_DUP_COMB | Retimed Register | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|last_cycle_cpu_data_master_granted_slave_ext_ram_s1~12 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|last_cycle_cpu_data_master_granted_slave_ext_ram_s1~13_BDD196 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|last_cycle_cpu_data_master_granted_slave_ext_ram_s1~14_BDD197 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|last_cycle_cpu_data_master_granted_slave_ext_ram_s1~15_BDD198 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|last_cycle_cpu_data_master_granted_slave_ext_ram_s1~16_BDD199 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|last_cycle_cpu_data_master_granted_slave_ext_ram_s1~17_BDD200 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|last_cycle_cpu_data_master_granted_slave_lan91c111_s1~4 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|last_cycle_cpu_data_master_granted_slave_lan91c111_s1~4_DUP_COMB | Retimed Register | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|last_cycle_cpu_data_master_granted_slave_lan91c111_s1~5_DUP_COMB | Retimed Register | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|last_cycle_cpu_data_master_granted_slave_lan91c111_s1~6 | Retimed Register | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|last_cycle_cpu_data_master_granted_slave_lan91c111_s1~7 | Deleted | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|last_cycle_cpu_data_master_granted_slave_lan91c111_s1~8_DUP_COMB | Retimed Register | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|last_cycle_cpu_instruction_master_granted_slave_ext_flash_s1~4 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|last_cycle_cpu_instruction_master_granted_slave_ext_flash_s1~4_DUP_COMB | Retimed Register | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|last_cycle_cpu_instruction_master_granted_slave_ext_flash_s1~5_DUP_COMB | Retimed Register | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|last_cycle_cpu_instruction_master_granted_slave_ext_flash_s1~6 | Retimed Register | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|last_cycle_cpu_instruction_master_granted_slave_ext_flash_s1~7 | Deleted | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|last_cycle_cpu_instruction_master_granted_slave_ext_flash_s1~8_DUP_COMB | Retimed Register | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|last_cycle_cpu_instruction_master_granted_slave_ext_ram_s1~4 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|last_cycle_cpu_instruction_master_granted_slave_ext_ram_s1~4_DUP_COMB | Retimed Register | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|last_cycle_cpu_instruction_master_granted_slave_ext_ram_s1~5_DUP_COMB | Retimed Register | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|last_cycle_cpu_instruction_master_granted_slave_ext_ram_s1~6 | Retimed Register | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|last_cycle_cpu_instruction_master_granted_slave_ext_ram_s1~7 | Deleted | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|last_cycle_cpu_instruction_master_granted_slave_ext_ram_s1~8_DUP_COMB | Retimed Register | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|last_cycle_cpu_instruction_master_granted_slave_lan91c111_s1~4 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|last_cycle_cpu_instruction_master_granted_slave_lan91c111_s1~4_DUP_COMB | Retimed Register | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|last_cycle_cpu_instruction_master_granted_slave_lan91c111_s1~5 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|last_cycle_cpu_instruction_master_granted_slave_lan91c111_s1~5_DUP_COMB | Retimed Register | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|last_cycle_cpu_instruction_master_granted_slave_lan91c111_s1~6 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|last_cycle_cpu_instruction_master_granted_slave_lan91c111_s1~7 | Retimed Register | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|last_cycle_cpu_instruction_master_granted_slave_lan91c111_s1~8 | Deleted | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|last_cycle_cpu_instruction_master_granted_slave_lan91c111_s1~9_DUP_COMB | Retimed Register | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|last_cycle_cpu_instruction_master_granted_slave_lan91c111_s1~10 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|outgoing_ext_ram_bus_data[5]~2900 | Deleted | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|outgoing_ext_ram_bus_data[5]~2901 | Deleted | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|outgoing_ext_ram_bus_data[6]~2897 | Deleted | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|outgoing_ext_ram_bus_data[6]~2898 | Deleted | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|outgoing_ext_ram_bus_data[7]~2893 | Deleted | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|outgoing_ext_ram_bus_data[7]~2894 | Deleted | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|p1_read_n_to_the_ext_ram~60 | Deleted | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|p1_read_n_to_the_ext_ram~63_BDD130 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|read_n_to_the_ext_ram~2_BDD559 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|read_n_to_the_ext_ram~COMB_OUT | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|jtag_uart:the_jtag_uart|Add0~184 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|jtag_uart:the_jtag_uart|LessThan1~117 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|jtag_uart:the_jtag_uart|process2~47 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|jtag_uart:the_jtag_uart|process2~49_BDD282 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|jtag_uart:the_jtag_uart|rvalid~26 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|jtag_uart:the_jtag_uart|rvalid~28_BDD299 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|lcd_display_control_slave_arbitrator:the_lcd_display_control_slave|Add0~101 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|lcd_display_control_slave_arbitrator:the_lcd_display_control_slave|lcd_display_control_slave_in_a_write_cycle~48 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|lcd_display_control_slave_arbitrator:the_lcd_display_control_slave|lcd_display_control_slave_in_a_write_cycle~50_BDD127 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|lcd_display_control_slave_arbitrator:the_lcd_display_control_slave|lcd_display_control_slave_wait_counter[0] | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|sdram:the_sdram|Mux32~1281 | Deleted | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|sdram:the_sdram|Mux32~1282 | Deleted | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|sdram:the_sdram|Mux32~1284 | Deleted | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|sdram:the_sdram|Mux32~1285 | Deleted | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|sdram:the_sdram|Mux32~1286 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|sdram:the_sdram|Mux32~1288_BDD380 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|sdram:the_sdram|Mux32~1289_BDD381 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|sdram:the_sdram|Mux32~1291_BDD383 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|sdram:the_sdram|Mux32~1292_BDD384 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|sdram:the_sdram|Mux32~1293_BDD385 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|sdram:the_sdram|Mux32~1294_BDD386 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|sdram:the_sdram|Mux32~1295_BDD387 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|sdram:the_sdram|Mux35~1199 | Deleted | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|sdram:the_sdram|Mux35~1202 | Deleted | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|sdram:the_sdram|Mux35~1203 | Deleted | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|sdram:the_sdram|Mux35~1204 | Deleted | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|sdram:the_sdram|Mux35~1206 | Deleted | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|sdram:the_sdram|Mux36~1269 | Deleted | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|sdram:the_sdram|Mux36~1272 | Deleted | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|sdram:the_sdram|Mux36~1273 | Deleted | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|sdram:the_sdram|Mux36~1274 | Deleted | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|sdram:the_sdram|Mux36~1276 | Deleted | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|sdram:the_sdram|Mux38~1211 | Deleted | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|sdram:the_sdram|Mux38~1212 | Deleted | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|sdram:the_sdram|Mux38~1213 | Deleted | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|sdram:the_sdram|Mux38~1214 | Deleted | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|sdram:the_sdram|Mux38~1215 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|sdram:the_sdram|Mux38~1217_BDD389 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|sdram:the_sdram|Mux38~1218_BDD390 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|sdram:the_sdram|Mux38~1219_BDD391 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|sdram:the_sdram|Mux38~1220_BDD392 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|sdram:the_sdram|Mux38~1221_BDD393 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|sdram:the_sdram|Mux40~1472 | Deleted | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|sdram:the_sdram|Mux40~1473 | Deleted | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|sdram:the_sdram|Mux40~1476 | Deleted | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|sdram:the_sdram|Mux40~1477 | Deleted | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|sdram:the_sdram|Mux40~1478 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|sdram:the_sdram|Mux40~1483_BDD256 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|sdram:the_sdram|Mux40~1484_BDD257 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|sdram:the_sdram|Mux40~1486_BDD259 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|sdram:the_sdram|Mux40~1487_BDD260 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|sdram:the_sdram|Mux40~1488_BDD261 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|sdram:the_sdram|Mux40~1489_BDD262 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|sdram:the_sdram|Mux40~1490_BDD263 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|sdram:the_sdram|Mux108~1494 | Deleted | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|sdram:the_sdram|Mux108~1495 | Deleted | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|sdram:the_sdram|Mux108~1496 | Deleted | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|sdram:the_sdram|Mux108~1497 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|sdram:the_sdram|Mux108~1499 | Deleted | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|sdram:the_sdram|Mux108~1500_BDD31 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|sdram:the_sdram|Mux108~1501_BDD32 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|sdram:the_sdram|Mux108~1502_BDD33 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|sdram:the_sdram|Mux108~1503_BDD34 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|sdram:the_sdram|Mux108~1505_BDD36 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|sdram:the_sdram|Mux108~1509_BDD575 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|sdram:the_sdram|Mux108~1510_BDD576 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|sdram:the_sdram|Mux108~1511_BDD577 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|sdram:the_sdram|Mux108~1512_BDD578 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|sdram:the_sdram|Mux109~1365 | Deleted | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|sdram:the_sdram|Mux109~1366 | Deleted | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|sdram:the_sdram|Mux109~1367 | Deleted | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|sdram:the_sdram|Mux109~1368 | Deleted | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|sdram:the_sdram|Mux109~1369 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|sdram:the_sdram|Mux109~1371 | Deleted | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|sdram:the_sdram|Mux109~1372_BDD174 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|sdram:the_sdram|Mux109~1373_BDD175 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|sdram:the_sdram|Mux109~1374_BDD176 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|sdram:the_sdram|Mux109~1375_BDD515 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|sdram:the_sdram|Mux109~1376_BDD516 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|sdram:the_sdram|Mux109~1377_BDD517 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|sdram:the_sdram|Mux109~1378_BDD518 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|sdram:the_sdram|Mux109~1379_BDD519 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|sdram:the_sdram|Mux109~1380_BDD520 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|sdram:the_sdram|Mux109~1381_BDD521 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|sdram:the_sdram|Mux110~1389 | Deleted | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|sdram:the_sdram|Mux110~1390 | Deleted | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|sdram:the_sdram|Mux110~1391 | Deleted | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|sdram:the_sdram|Mux110~1392 | Deleted | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|sdram:the_sdram|Mux110~1393 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|sdram:the_sdram|Mux110~1395 | Deleted | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|sdram:the_sdram|Mux110~1396_BDD157 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|sdram:the_sdram|Mux110~1397_BDD158 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|sdram:the_sdram|Mux110~1400_BDD161 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|sdram:the_sdram|Mux110~1401_BDD455 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|sdram:the_sdram|Mux110~1402_BDD456 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|sdram:the_sdram|Mux110~1403_BDD457 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|sdram:the_sdram|Mux110~1404_BDD458 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|sdram:the_sdram|Mux110~1405_BDD459 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|sdram:the_sdram|Mux110~1406_BDD460 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|sdram:the_sdram|Mux110~1407_BDD461 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|sdram:the_sdram|Mux111~1316 | Deleted | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|sdram:the_sdram|Mux111~1317 | Deleted | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|sdram:the_sdram|Mux111~1318 | Deleted | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|sdram:the_sdram|Mux111~1319 | Deleted | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|sdram:the_sdram|Mux111~1320 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|sdram:the_sdram|Mux111~1322 | Deleted | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|sdram:the_sdram|Mux111~1323_BDD162 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|sdram:the_sdram|Mux111~1324_BDD163 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|sdram:the_sdram|Mux111~1327_BDD166 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|sdram:the_sdram|Mux111~1328_BDD462 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|sdram:the_sdram|Mux111~1329_BDD463 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|sdram:the_sdram|Mux111~1330_BDD464 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|sdram:the_sdram|Mux111~1331_BDD465 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|sdram:the_sdram|Mux111~1332_BDD466 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|sdram:the_sdram|Mux111~1333_BDD467 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|sdram:the_sdram|Mux111~1334_BDD468 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|sdram:the_sdram|Mux112~1348 | Deleted | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|sdram:the_sdram|Mux112~1349 | Deleted | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|sdram:the_sdram|Mux112~1350 | Deleted | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|sdram:the_sdram|Mux112~1351 | Deleted | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|sdram:the_sdram|Mux112~1352 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|sdram:the_sdram|Mux112~1354 | Deleted | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|sdram:the_sdram|Mux112~1355_BDD177 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|sdram:the_sdram|Mux112~1356_BDD178 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|sdram:the_sdram|Mux112~1357_BDD179 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|sdram:the_sdram|Mux112~1358_BDD522 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|sdram:the_sdram|Mux112~1359_BDD523 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|sdram:the_sdram|Mux112~1360_BDD524 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|sdram:the_sdram|Mux112~1361_BDD525 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|sdram:the_sdram|Mux112~1362_BDD526 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|sdram:the_sdram|Mux112~1363_BDD527 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|sdram:the_sdram|Mux112~1364_BDD528 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|sdram:the_sdram|Mux113~1348 | Deleted | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|sdram:the_sdram|Mux113~1349 | Deleted | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|sdram:the_sdram|Mux113~1350 | Deleted | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|sdram:the_sdram|Mux113~1351 | Deleted | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|sdram:the_sdram|Mux113~1352 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|sdram:the_sdram|Mux113~1354 | Deleted | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|sdram:the_sdram|Mux113~1355_BDD180 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|sdram:the_sdram|Mux113~1356_BDD181 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|sdram:the_sdram|Mux113~1357_BDD182 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|sdram:the_sdram|Mux113~1358_BDD529 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|sdram:the_sdram|Mux113~1359_BDD530 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|sdram:the_sdram|Mux113~1360_BDD531 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|sdram:the_sdram|Mux113~1361_BDD532 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|sdram:the_sdram|Mux113~1362_BDD533 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|sdram:the_sdram|Mux113~1363_BDD534 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|sdram:the_sdram|Mux113~1364_BDD535 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|sdram:the_sdram|Mux114~1348 | Deleted | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|sdram:the_sdram|Mux114~1349 | Deleted | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|sdram:the_sdram|Mux114~1350 | Deleted | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|sdram:the_sdram|Mux114~1351 | Deleted | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|sdram:the_sdram|Mux114~1352 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|sdram:the_sdram|Mux114~1354 | Deleted | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|sdram:the_sdram|Mux114~1355_BDD183 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|sdram:the_sdram|Mux114~1356_BDD184 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|sdram:the_sdram|Mux114~1357_BDD185 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|sdram:the_sdram|Mux114~1358_BDD536 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|sdram:the_sdram|Mux114~1359_BDD537 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|sdram:the_sdram|Mux114~1360_BDD538 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|sdram:the_sdram|Mux114~1361_BDD539 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|sdram:the_sdram|Mux114~1362_BDD540 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|sdram:the_sdram|Mux114~1363_BDD541 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|sdram:the_sdram|Mux114~1364_BDD542 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|sdram:the_sdram|Mux115~1348 | Deleted | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|sdram:the_sdram|Mux115~1349 | Deleted | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|sdram:the_sdram|Mux115~1350 | Deleted | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|sdram:the_sdram|Mux115~1351 | Deleted | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|sdram:the_sdram|Mux115~1352 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|sdram:the_sdram|Mux115~1354 | Deleted | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|sdram:the_sdram|Mux115~1355_BDD186 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|sdram:the_sdram|Mux115~1356_BDD187 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|sdram:the_sdram|Mux115~1357_BDD188 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|sdram:the_sdram|Mux115~1358_BDD543 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|sdram:the_sdram|Mux115~1359_BDD544 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|sdram:the_sdram|Mux115~1360_BDD545 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|sdram:the_sdram|Mux115~1361_BDD546 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|sdram:the_sdram|Mux115~1362_BDD547 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|sdram:the_sdram|Mux115~1363_BDD548 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|sdram:the_sdram|Mux115~1364_BDD549 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|sdram:the_sdram|f_select | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|sdram:the_sdram|f_select~12_BDD201 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|sdram:the_sdram|f_select~13_BDD586 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|sdram:the_sdram|m_addr[0]~_Duplicate_1_DUP_COMB | Retimed Register | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|sdram:the_sdram|m_addr[1]~_Duplicate_1_DUP_COMB | Retimed Register | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|sdram:the_sdram|m_addr[2]~_Duplicate_1_DUP_COMB | Retimed Register | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|sdram:the_sdram|m_addr[3]~_Duplicate_1_DUP_COMB | Retimed Register | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|sdram:the_sdram|m_addr[4]~_Duplicate_1_DUP_COMB | Retimed Register | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|sdram:the_sdram|m_addr[5]~_Duplicate_1_DUP_COMB | Retimed Register | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|sdram:the_sdram|m_addr[6]~_Duplicate_1_DUP_COMB | Retimed Register | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|sdram:the_sdram|m_addr[7]~_Duplicate_1_DUP_COMB | Retimed Register | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|sdram:the_sdram|m_cmd[1]~_Duplicate_1_DUP_COMB | Retimed Register | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|sdram:the_sdram|m_cmd~58 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|sdram:the_sdram|m_cmd~59_BDD580 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|sdram:the_sdram|m_next[3] | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|sdram:the_sdram|m_next[3]~850_BDD310 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|sdram:the_sdram|m_next[3]~851_BDD311 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|sdram:the_sdram|m_next[3]~852_BDD312 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|sdram:the_sdram|m_next[3]~853_BDD313 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|sdram:the_sdram|m_next[3]~854_BDD314 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|sdram:the_sdram|m_next[3]~855_BDD315 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|sdram:the_sdram|m_next[3]~856_BDD316 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|sdram:the_sdram|m_next[4] | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|sdram:the_sdram|m_next[4]~857_BDD317 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|sdram:the_sdram|m_next[4]~858_BDD318 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|sdram:the_sdram|m_next[4]~859_BDD319 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|sdram:the_sdram|m_next[4]~860_BDD320 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|sdram:the_sdram|m_next[4]~861_BDD321 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|sdram:the_sdram|m_next[4]~862_BDD322 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|sdram:the_sdram|m_next[4]~863_BDD323 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|sdram_s1_arbitrator:the_sdram_s1|Add1~99 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|sdram_s1_arbitrator:the_sdram_s1|cpu_data_master_qualified_request_sdram_s1~115 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|sdram_s1_arbitrator:the_sdram_s1|rdv_fifo_for_cpu_data_master_to_sdram_s1_module:rdv_fifo_for_cpu_data_master_to_sdram_s1|fifo_contains_ones_n~18 | Retimed Register | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|sdram_s1_arbitrator:the_sdram_s1|rdv_fifo_for_cpu_data_master_to_sdram_s1_module:rdv_fifo_for_cpu_data_master_to_sdram_s1|fifo_contains_ones_n~19 | Deleted | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|sdram_s1_arbitrator:the_sdram_s1|rdv_fifo_for_cpu_data_master_to_sdram_s1_module:rdv_fifo_for_cpu_data_master_to_sdram_s1|fifo_contains_ones_n~22_BDD588 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|sdram_s1_arbitrator:the_sdram_s1|rdv_fifo_for_cpu_data_master_to_sdram_s1_module:rdv_fifo_for_cpu_data_master_to_sdram_s1|fifo_contains_ones_n~23_BDD589 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|sdram_s1_arbitrator:the_sdram_s1|rdv_fifo_for_cpu_data_master_to_sdram_s1_module:rdv_fifo_for_cpu_data_master_to_sdram_s1|stage_0~578 | Retimed Register | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|sdram_s1_arbitrator:the_sdram_s1|rdv_fifo_for_cpu_data_master_to_sdram_s1_module:rdv_fifo_for_cpu_data_master_to_sdram_s1|stage_1~572 | Retimed Register | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|sdram_s1_arbitrator:the_sdram_s1|rdv_fifo_for_cpu_data_master_to_sdram_s1_module:rdv_fifo_for_cpu_data_master_to_sdram_s1|stage_2~980 | Retimed Register | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|sdram_s1_arbitrator:the_sdram_s1|rdv_fifo_for_cpu_data_master_to_sdram_s1_module:rdv_fifo_for_cpu_data_master_to_sdram_s1|stage_3~7020 | Retimed Register | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|sdram_s1_arbitrator:the_sdram_s1|rdv_fifo_for_cpu_data_master_to_sdram_s1_module:rdv_fifo_for_cpu_data_master_to_sdram_s1|stage_4~7020 | Retimed Register | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|sdram_s1_arbitrator:the_sdram_s1|rdv_fifo_for_cpu_data_master_to_sdram_s1_module:rdv_fifo_for_cpu_data_master_to_sdram_s1|stage_5~7020 | Retimed Register | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|sdram_s1_arbitrator:the_sdram_s1|rdv_fifo_for_cpu_data_master_to_sdram_s1_module:rdv_fifo_for_cpu_data_master_to_sdram_s1|stage_6~7021 | Retimed Register | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|sdram_s1_arbitrator:the_sdram_s1|rdv_fifo_for_cpu_data_master_to_sdram_s1_module:rdv_fifo_for_cpu_data_master_to_sdram_s1|updated_one_count~70 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|sdram_s1_arbitrator:the_sdram_s1|rdv_fifo_for_cpu_data_master_to_sdram_s1_module:rdv_fifo_for_cpu_data_master_to_sdram_s1|updated_one_count~72_BDD596 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|sdram_s1_arbitrator:the_sdram_s1|rdv_fifo_for_cpu_data_master_to_sdram_s1_module:rdv_fifo_for_cpu_data_master_to_sdram_s1|updated_one_count~73_BDD597 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|sdram_s1_arbitrator:the_sdram_s1|rdv_fifo_for_cpu_instruction_master_to_sdram_s1_module:rdv_fifo_for_cpu_instruction_master_to_sdram_s1|fifo_contains_ones_n~17 | Retimed Register | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|sdram_s1_arbitrator:the_sdram_s1|rdv_fifo_for_cpu_instruction_master_to_sdram_s1_module:rdv_fifo_for_cpu_instruction_master_to_sdram_s1|fifo_contains_ones_n~18 | Deleted | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|sdram_s1_arbitrator:the_sdram_s1|rdv_fifo_for_cpu_instruction_master_to_sdram_s1_module:rdv_fifo_for_cpu_instruction_master_to_sdram_s1|fifo_contains_ones_n~20_BDD396 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|sdram_s1_arbitrator:the_sdram_s1|rdv_fifo_for_cpu_instruction_master_to_sdram_s1_module:rdv_fifo_for_cpu_instruction_master_to_sdram_s1|process15~0 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|sdram_s1_arbitrator:the_sdram_s1|rdv_fifo_for_cpu_instruction_master_to_sdram_s1_module:rdv_fifo_for_cpu_instruction_master_to_sdram_s1|process15~1_BDD302 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|sdram_s1_arbitrator:the_sdram_s1|rdv_fifo_for_cpu_instruction_master_to_sdram_s1_module:rdv_fifo_for_cpu_instruction_master_to_sdram_s1|stage_0~4 | Retimed Register | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|sdram_s1_arbitrator:the_sdram_s1|rdv_fifo_for_cpu_instruction_master_to_sdram_s1_module:rdv_fifo_for_cpu_instruction_master_to_sdram_s1|stage_1~4 | Retimed Register | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|sdram_s1_arbitrator:the_sdram_s1|rdv_fifo_for_cpu_instruction_master_to_sdram_s1_module:rdv_fifo_for_cpu_instruction_master_to_sdram_s1|stage_2~4 | Retimed Register | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|sdram_s1_arbitrator:the_sdram_s1|rdv_fifo_for_cpu_instruction_master_to_sdram_s1_module:rdv_fifo_for_cpu_instruction_master_to_sdram_s1|stage_3~4 | Retimed Register | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|sdram_s1_arbitrator:the_sdram_s1|rdv_fifo_for_cpu_instruction_master_to_sdram_s1_module:rdv_fifo_for_cpu_instruction_master_to_sdram_s1|stage_4~4 | Retimed Register | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|sdram_s1_arbitrator:the_sdram_s1|rdv_fifo_for_cpu_instruction_master_to_sdram_s1_module:rdv_fifo_for_cpu_instruction_master_to_sdram_s1|stage_5~4 | Retimed Register | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|sdram_s1_arbitrator:the_sdram_s1|rdv_fifo_for_cpu_instruction_master_to_sdram_s1_module:rdv_fifo_for_cpu_instruction_master_to_sdram_s1|stage_6~5 | Retimed Register | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|sdram_s1_arbitrator:the_sdram_s1|rdv_fifo_for_cpu_instruction_master_to_sdram_s1_module:rdv_fifo_for_cpu_instruction_master_to_sdram_s1|stage_6~_DUP_COMB | Retimed Register | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|sdram_s1_arbitrator:the_sdram_s1|rdv_fifo_for_cpu_instruction_master_to_sdram_s1_module:rdv_fifo_for_cpu_instruction_master_to_sdram_s1|updated_one_count~71 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|sdram_s1_arbitrator:the_sdram_s1|rdv_fifo_for_cpu_instruction_master_to_sdram_s1_module:rdv_fifo_for_cpu_instruction_master_to_sdram_s1|updated_one_count~72_BDD431 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|sdram_s1_arbitrator:the_sdram_s1|rdv_fifo_for_cpu_instruction_master_to_sdram_s1_module:rdv_fifo_for_cpu_instruction_master_to_sdram_s1|updated_one_count~73_BDD432 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|sdram_s1_arbitrator:the_sdram_s1|sdram_s1_arb_share_counter[0] | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|sys_clk_timer:the_sys_clk_timer|control_wr_strobe | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|sys_clk_timer:the_sys_clk_timer|control_wr_strobe~43_BDD433 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|sys_clk_timer_s1_arbitrator:the_sys_clk_timer_s1|cpu_data_master_requests_sys_clk_timer_s1~180 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|sys_clk_timer_s1_arbitrator:the_sys_clk_timer_s1|cpu_data_master_requests_sys_clk_timer_s1~181 | Modified | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|sys_clk_timer_s1_arbitrator:the_sys_clk_timer_s1|cpu_data_master_requests_sys_clk_timer_s1~182_BDD271 | Created | Physical Synthesis | Timing optimization |  |  |
std_1c20:inst|sys_clk_timer_s1_arbitrator:the_sys_clk_timer_s1|cpu_data_master_requests_sys_clk_timer_s1~183_BDD591 | Created | Physical Synthesis | Timing optimization |  |  |

## Fitter Equations

Top

Fitter Equations

## Pin-Out File

Top

Pin-Out File

## Fitter Resource Usage Summary

Top

Resource | Usage
--- | ---
Total logic elements | 4,930 / 20,060 ( 25 % )
-- Combinational with no register | 2338
-- Register only | 417
-- Combinational with a register | 2175
Logic element usage by number of LUT inputs |
-- 4 input functions | 2461
-- 3 input functions | 1409
-- 2 input functions | 567
-- 1 input functions | 271
-- 0 input functions | 222
Logic elements by mode |
-- normal mode | 4637
-- arithmetic mode | 293
-- qfbk mode | 332
-- register cascade mode | 0
-- synchronous clear/load mode | 851
-- asynchronous clear/load mode | 2316
Total LABs | 594 / 2,006 ( 30 % )
Logic elements in carry chains | 320
User inserted logic elements | 0
Virtual pins | 0
I/O pins | 180 / 301 ( 60 % )
-- Clock pins | 2 / 2 ( 100 % )
Number of I/O registers | 220
Global signals | 8
M4Ks | 16 / 64 ( 25 % )
Total memory bits | 50,944 / 294,912 ( 17 % )
Total RAM block bits | 73,728 / 294,912 ( 25 % )
PLLs | 2 / 2 ( 100 % )
Global clocks | 8 / 8 ( 100 % )
Maximum fan-out node | std_1c20:inst|sdram_pll:the_sdram_pll|altpllsdram_pll:the_pll|altpll:altpll_component|_clk0
Maximum fan-out | 2390
Highest non-global fan-out signal | std_1c20:inst|cpu:the_cpu|W_stall
Highest non-global fan-out | 541
Total fan-out | 23545
Average fan-out | 4.59

## Input Pins

Top

Name | Pin # | I/O Bank | X coordinate | Y coordinate | Cell number | Combinational Fan-Out | Registered Fan-Out | Global | Input Register | Power Up High | PCI I/O Enabled | Bus Hold | Weak Pull Up | I/O Standard | Termination | Location assigned by
--- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | ---
PLD_CLEAR_N | C4 | 2 | 2 | 33 | 1 | 1 | 0 | no | no | no | no | no | Off | LVTTL | Off | User
PLD_CLKFB | L14 | 3 | 69 | 18 | 1 | 74 | 0 | yes | no | no | no | no | Off | LVTTL | Off | User
PLD_CLOCKINPUT[1] | K5 | 1 | 0 | 18 | 2 | 74 | 0 | yes | no | no | no | no | Off | LVTTL | Off | User
in_port_to_the_button_pio[0] | W3 | 4 | 2 | 0 | 1 | 2 | 0 | no | no | no | no | no | Off | LVTTL | Off | User
in_port_to_the_button_pio[1] | Y4 | 4 | 2 | 0 | 0 | 2 | 0 | no | no | no | no | no | Off | LVTTL | Off | User
in_port_to_the_button_pio[2] | V4 | 4 | 4 | 0 | 1 | 2 | 0 | no | no | no | no | no | Off | LVTTL | Off | User
in_port_to_the_button_pio[3] | W4 | 4 | 4 | 0 | 0 | 2 | 0 | no | no | no | no | no | Off | LVTTL | Off | User
irq_from_the_lan91c111 | D15 | 2 | 60 | 33 | 1 | 1 | 0 | no | no | no | no | no | Off | LVTTL | Off | User
rxd_to_the_uart1 | K16 | 3 | 69 | 19 | 0 | 1 | 0 | no | no | no | no | no | Off | LVTTL | Off | User

## Output Pins

Top

Name | Pin # | I/O Bank | X coordinate | Y coordinate | Cell number | Output Register | Output Enable Register | Power Up High | Slow Slew Rate | PCI I/O Enabled | Open Drain | TRI Primitive | Bus Hold | Weak Pull Up | I/O Standard | Current Strength | Termination | Location assigned by | Load
--- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | ---
ENET_ADS_N | A14 | 2 | 54 | 33 | 0 | no | no | no | no | no | no | no | no | Off | LVTTL | 24mA | Off | User | 10 pF
ENET_AEN | B15 | 2 | 58 | 33 | 0 | no | no | no | no | no | no | no | no | Off | LVTTL | 24mA | Off | User | 10 pF
LCD_E_from_the_lcd_display | J20 | 3 | 69 | 21 | 0 | no | no | no | no | no | no | no | no | Off | LVTTL | 24mA | Off | User | 10 pF
LCD_RS_from_the_lcd_display | J15 | 3 | 69 | 22 | 1 | no | no | no | no | no | no | no | no | Off | LVTTL | 24mA | Off | User | 10 pF
LCD_RW_from_the_lcd_display | J19 | 3 | 69 | 22 | 2 | no | no | no | no | no | no | no | no | Off | LVTTL | 24mA | Off | User | 10 pF
PLD_CLKOUT | L8 | 1 | 0 | 14 | 0 | no | no | no | no | no | no | no | no | Off | LVTTL | 24mA | Off | User | 10 pF
SDRAM_CLK | L13 | 3 | 69 | 15 | 0 | no | no | no | no | no | no | no | no | Off | LVTTL | 24mA | Off | User | 10 pF
be_n_to_the_ext_ram[0] | V17 | 4 | 66 | 0 | 1 | yes | no | yes | no | no | no | no | no | Off | LVTTL | 24mA | Off | User | 10 pF
be_n_to_the_ext_ram[1] | V16 | 4 | 64 | 0 | 0 | yes | no | yes | no | no | no | no | no | Off | LVTTL | 24mA | Off | User | 10 pF
be_n_to_the_ext_ram[2] | W16 | 4 | 64 | 0 | 1 | yes | no | yes | no | no | no | no | no | Off | LVTTL | 24mA | Off | User | 10 pF
be_n_to_the_ext_ram[3] | T16 | 4 | 62 | 0 | 0 | yes | no | yes | no | no | no | no | no | Off | LVTTL | 24mA | Off | User | 10 pF
byteenablen_to_the_lan91c111[0] | C16 | 2 | 64 | 33 | 0 | yes | no | yes | no | no | no | no | no | Off | LVTTL | 24mA | Off | User | 10 pF
byteenablen_to_the_lan91c111[1] | B16 | 2 | 64 | 33 | 1 | yes | no | yes | no | no | no | no | no | Off | LVTTL | 24mA | Off | User | 10 pF
byteenablen_to_the_lan91c111[2] | D16 | 2 | 62 | 33 | 0 | yes | no | yes | no | no | no | no | no | Off | LVTTL | 24mA | Off | User | 10 pF
byteenablen_to_the_lan91c111[3] | E16 | 2 | 62 | 33 | 1 | yes | no | yes | no | no | no | no | no | Off | LVTTL | 24mA | Off | User | 10 pF
ext_ram_bus_address[0] | B4 | 2 | 4 | 33 | 1 | yes | no | no | no | no | no | no | no | Off | LVTTL | 24mA | Off | User | 10 pF
ext_ram_bus_address[10] | E4 | 1 | 0 | 30 | 1 | yes | no | no | no | no | no | no | no | Off | LVTTL | 24mA | Off | User | 10 pF
ext_ram_bus_address[11] | E5 | 1 | 0 | 30 | 2 | yes | no | no | no | no | no | no | no | Off | LVTTL | 24mA | Off | User | 10 pF
ext_ram_bus_address[12] | F3 | 1 | 0 | 29 | 0 | yes | no | no | no | no | no | no | no | Off | LVTTL | 24mA | Off | User | 10 pF
ext_ram_bus_address[13] | E3 | 1 | 0 | 29 | 1 | yes | no | no | no | no | no | no | no | Off | LVTTL | 24mA | Off | User | 10 pF
ext_ram_bus_address[14] | E2 | 1 | 0 | 29 | 2 | yes | no | no | no | no | no | no | no | Off | LVTTL | 24mA | Off | User | 10 pF
ext_ram_bus_address[15] | F4 | 1 | 0 | 28 | 0 | yes | no | no | no | no | no | no | no | Off | LVTTL | 24mA | Off | User | 10 pF
ext_ram_bus_address[16] | F5 | 1 | 0 | 28 | 1 | yes | no | no | no | no | no | no | no | Off | LVTTL | 24mA | Off | User | 10 pF
ext_ram_bus_address[17] | F2 | 1 | 0 | 28 | 2 | yes | no | no | no | no | no | no | no | Off | LVTTL | 24mA | Off | User | 10 pF
ext_ram_bus_address[18] | F1 | 1 | 0 | 27 | 0 | yes | no | no | no | no | no | no | no | Off | LVTTL | 24mA | Off | User | 10 pF
ext_ram_bus_address[19] | F6 | 1 | 0 | 27 | 1 | yes | no | no | no | no | no | no | no | Off | LVTTL | 24mA | Off | User | 10 pF
ext_ram_bus_address[1] | A4 | 2 | 4 | 33 | 0 | yes | no | no | no | no | no | no | no | Off | LVTTL | 24mA | Off | User | 10 pF
ext_ram_bus_address[20] | G5 | 1 | 0 | 27 | 2 | yes | no | no | no | no | no | no | no | Off | LVTTL | 24mA | Off | User | 10 pF
ext_ram_bus_address[21] | G1 | 1 | 0 | 26 | 0 | yes | no | no | no | no | no | no | no | Off | LVTTL | 24mA | Off | User | 10 pF
ext_ram_bus_address[22] | G2 | 1 | 0 | 26 | 1 | yes | no | no | no | no | no | no | no | Off | LVTTL | 24mA | Off | User | 10 pF
ext_ram_bus_address[2] | D5 | 2 | 6 | 33 | 1 | yes | no | no | no | no | no | no | no | Off | LVTTL | 24mA | Off | User | 10 pF
ext_ram_bus_address[3] | D6 | 2 | 6 | 33 | 0 | yes | no | no | no | no | no | no | no | Off | LVTTL | 24mA | Off | User | 10 pF
ext_ram_bus_address[4] | C5 | 2 | 8 | 33 | 1 | yes | no | no | no | no | no | no | no | Off | LVTTL | 24mA | Off | User | 10 pF
ext_ram_bus_address[5] | B5 | 2 | 8 | 33 | 0 | yes | no | no | no | no | no | no | no | Off | LVTTL | 24mA | Off | User | 10 pF
ext_ram_bus_address[6] | C2 | 1 | 0 | 32 | 1 | yes | no | no | no | no | no | no | no | Off | LVTTL | 24mA | Off | User | 10 pF
ext_ram_bus_address[7] | D2 | 1 | 0 | 31 | 1 | yes | no | no | no | no | no | no | no | Off | LVTTL | 24mA | Off | User | 10 pF
ext_ram_bus_address[8] | D4 | 1 | 0 | 31 | 2 | yes | no | no | no | no | no | no | no | Off | LVTTL | 24mA | Off | User | 10 pF
ext_ram_bus_address[9] | D1 | 1 | 0 | 30 | 0 | yes | no | no | no | no | no | no | no | Off | LVTTL | 24mA | Off | User | 10 pF
ior_n_to_the_lan91c111 | A15 | 2 | 58 | 33 | 1 | yes | no | yes | no | no | no | no | no | Off | LVTTL | 24mA | Off | User | 10 pF
iow_n_to_the_lan91c111 | E15 | 2 | 56 | 33 | 0 | yes | no | yes | no | no | no | no | no | Off | LVTTL | 24mA | Off | User | 10 pF
out_port_from_the_led_pio[0] | E14 | 2 | 52 | 33 | 0 | no | no | no | no | no | no | no | no | Off | LVTTL | 24mA | Off | User | 10 pF
out_port_from_the_led_pio[1] | E13 | 2 | 52 | 33 | 1 | no | no | no | no | no | no | no | no | Off | LVTTL | 24mA | Off | User | 10 pF
out_port_from_the_led_pio[2] | C14 | 2 | 48 | 33 | 0 | no | no | no | no | no | no | no | no | Off | LVTTL | 24mA | Off | User | 10 pF
out_port_from_the_led_pio[3] | D14 | 2 | 48 | 33 | 1 | no | no | no | no | no | no | no | no | Off | LVTTL | 24mA | Off | User | 10 pF
out_port_from_the_led_pio[4] | E12 | 2 | 42 | 33 | 0 | no | no | no | no | no | no | no | no | Off | LVTTL | 24mA | Off | User | 10 pF
out_port_from_the_led_pio[5] | F12 | 2 | 42 | 33 | 1 | no | no | no | no | no | no | no | no | Off | LVTTL | 24mA | Off | User | 10 pF
out_port_from_the_led_pio[6] | B3 | 2 | 2 | 33 | 0 | no | no | no | no | no | no | no | no | Off | LVTTL | 24mA | Off | User | 10 pF
out_port_from_the_led_pio[7] | B14 | 2 | 54 | 33 | 1 | no | no | no | no | no | no | no | no | Off | LVTTL | 24mA | Off | User | 10 pF
out_port_from_the_seven_seg_pio[0] | V7 | 4 | 18 | 0 | 1 | no | no | no | no | no | no | no | no | Off | LVTTL | 24mA | Off | User | 10 pF
out_port_from_the_seven_seg_pio[10] | T6 | 4 | 10 | 0 | 2 | no | no | no | no | no | no | no | no | Off | LVTTL | 24mA | Off | User | 10 pF
out_port_from_the_seven_seg_pio[11] | W5 | 4 | 8 | 0 | 0 | no | no | no | no | no | no | no | no | Off | LVTTL | 24mA | Off | User | 10 pF
out_port_from_the_seven_seg_pio[12] | V5 | 4 | 8 | 0 | 1 | no | no | no | no | no | no | no | no | Off | LVTTL | 24mA | Off | User | 10 pF
out_port_from_the_seven_seg_pio[13] | U5 | 4 | 6 | 0 | 0 | no | no | no | no | no | no | no | no | Off | LVTTL | 24mA | Off | User | 10 pF
out_port_from_the_seven_seg_pio[14] | T5 | 4 | 6 | 0 | 1 | no | no | no | no | no | no | no | no | Off | LVTTL | 24mA | Off | User | 10 pF
out_port_from_the_seven_seg_pio[15] | Y6 | 4 | 12 | 0 | 1 | no | no | no | no | no | no | no | no | Off | LVTTL | 24mA | Off | User | 10 pF
out_port_from_the_seven_seg_pio[1] | T8 | 4 | 16 | 0 | 0 | no | no | no | no | no | no | no | no | Off | LVTTL | 24mA | Off | User | 10 pF
out_port_from_the_seven_seg_pio[2] | R7 | 4 | 16 | 0 | 1 | no | no | no | no | no | no | no | no | Off | LVTTL | 24mA | Off | User | 10 pF
out_port_from_the_seven_seg_pio[3] | Y7 | 4 | 14 | 0 | 0 | no | no | no | no | no | no | no | no | Off | LVTTL | 24mA | Off | User | 10 pF
out_port_from_the_seven_seg_pio[4] | W7 | 4 | 14 | 0 | 1 | no | no | no | no | no | no | no | no | Off | LVTTL | 24mA | Off | User | 10 pF
out_port_from_the_seven_seg_pio[5] | V6 | 4 | 14 | 0 | 2 | no | no | no | no | no | no | no | no | Off | LVTTL | 24mA | Off | User | 10 pF
out_port_from_the_seven_seg_pio[6] | U6 | 4 | 12 | 0 | 0 | no | no | no | no | no | no | no | no | Off | LVTTL | 24mA | Off | User | 10 pF
out_port_from_the_seven_seg_pio[7] | U7 | 4 | 18 | 0 | 0 | no | no | no | no | no | no | no | no | Off | LVTTL | 24mA | Off | User | 10 pF
out_port_from_the_seven_seg_pio[8] | W6 | 4 | 10 | 0 | 0 | no | no | no | no | no | no | no | no | Off | LVTTL | 24mA | Off | User | 10 pF
out_port_from_the_seven_seg_pio[9] | T7 | 4 | 10 | 0 | 1 | no | no | no | no | no | no | no | no | Off | LVTTL | 24mA | Off | User | 10 pF
read_n_to_the_ext_flash | B12 | 2 | 40 | 33 | 1 | yes | no | yes | no | no | no | no | no | Off | LVTTL | 24mA | Off | User | 10 pF
read_n_to_the_ext_ram | Y17 | 4 | 68 | 0 | 1 | yes | no | yes | no | no | no | no | no | Off | LVTTL | 24mA | Off | User | 10 pF
select_n_to_the_ext_flash | A12 | 2 | 40 | 33 | 0 | yes | no | yes | no | no | no | no | no | Off | LVTTL | 24mA | Off | User | 10 pF
select_n_to_the_ext_ram | W17 | 4 | 68 | 0 | 0 | yes | no | yes | no | no | no | no | no | Off | LVTTL | 24mA | Off | User | 10 pF
txd_from_the_uart1 | M14 | 3 | 69 | 14 | 0 | no | no | no | no | no | no | no | no | Off | LVTTL | 24mA | Off | User | 10 pF
write_n_to_the_ext_flash | D12 | 2 | 38 | 33 | 0 | yes | no | yes | no | no | no | no | no | Off | LVTTL | 24mA | Off | User | 10 pF
write_n_to_the_ext_ram | U16 | 4 | 66 | 0 | 0 | no | no | no | no | no | no | no | no | Off | LVTTL | 24mA | Off | User | 10 pF
zs_addr_from_the_sdram[0] | M2 | 1 | 0 | 13 | 0 | yes | no | no | no | no | no | no | no | Off | LVTTL | 24mA | Off | User | 10 pF
zs_addr_from_the_sdram[10] | H6 | 1 | 0 | 21 | 0 | yes | no | no | no | no | no | no | no | Off | LVTTL | 24mA | Off | User | 10 pF
zs_addr_from_the_sdram[11] | H5 | 1 | 0 | 22 | 2 | yes | no | no | no | no | no | no | no | Off | LVTTL | 24mA | Off | User | 10 pF
zs_addr_from_the_sdram[1] | M1 | 1 | 0 | 13 | 1 | yes | no | no | no | no | no | no | no | Off | LVTTL | 24mA | Off | User | 10 pF
zs_addr_from_the_sdram[2] | M6 | 1 | 0 | 12 | 0 | yes | no | no | no | no | no | no | no | Off | LVTTL | 24mA | Off | User | 10 pF
zs_addr_from_the_sdram[3] | M4 | 1 | 0 | 12 | 1 | yes | no | no | no | no | no | no | no | Off | LVTTL | 24mA | Off | User | 10 pF
zs_addr_from_the_sdram[4] | J8 | 1 | 0 | 19 | 0 | yes | no | no | no | no | no | no | no | Off | LVTTL | 24mA | Off | User | 10 pF
zs_addr_from_the_sdram[5] | J7 | 1 | 0 | 20 | 2 | yes | no | no | no | no | no | no | no | Off | LVTTL | 24mA | Off | User | 10 pF
zs_addr_from_the_sdram[6] | J6 | 1 | 0 | 20 | 1 | yes | no | no | no | no | no | no | no | Off | LVTTL | 24mA | Off | User | 10 pF
zs_addr_from_the_sdram[7] | J5 | 1 | 0 | 20 | 0 | yes | no | no | no | no | no | no | no | Off | LVTTL | 24mA | Off | User | 10 pF
zs_addr_from_the_sdram[8] | J4 | 1 | 0 | 21 | 2 | yes | no | no | no | no | no | no | no | Off | LVTTL | 24mA | Off | User | 10 pF
zs_addr_from_the_sdram[9] | J3 | 1 | 0 | 21 | 1 | yes | no | no | no | no | no | no | no | Off | LVTTL | 24mA | Off | User | 10 pF
zs_ba_from_the_sdram[0] | H7 | 1 | 0 | 24 | 0 | yes | no | no | no | no | no | no | no | Off | LVTTL | 24mA | Off | User | 10 pF
zs_ba_from_the_sdram[1] | H1 | 1 | 0 | 24 | 1 | yes | no | no | no | no | no | no | no | Off | LVTTL | 24mA | Off | User | 10 pF
zs_cas_n_from_the_sdram | G3 | 1 | 0 | 25 | 1 | yes | no | yes | no | no | no | no | no | Off | LVTTL | 24mA | Off | User | 10 pF
zs_cke_from_the_sdram | G7 | 1 | 0 | 25 | 0 | no | no | no | no | no | no | no | no | Off | LVTTL | 24mA | Off | User | 10 pF
zs_cs_n_from_the_sdram | G6 | 1 | 0 | 26 | 2 | yes | no | yes | no | no | no | no | no | Off | LVTTL | 24mA | Off | User | 10 pF
zs_dqm_from_the_sdram[0] | J2 | 1 | 0 | 22 | 1 | yes | no | no | no | no | no | no | no | Off | LVTTL | 24mA | Off | User | 10 pF
zs_dqm_from_the_sdram[1] | J1 | 1 | 0 | 22 | 0 | yes | no | no | no | no | no | no | no | Off | LVTTL | 24mA | Off | User | 10 pF
zs_dqm_from_the_sdram[2] | H4 | 1 | 0 | 23 | 1 | yes | no | no | no | no | no | no | no | Off | LVTTL | 24mA | Off | User | 10 pF
zs_dqm_from_the_sdram[3] | H3 | 1 | 0 | 23 | 0 | yes | no | no | no | no | no | no | no | Off | LVTTL | 24mA | Off | User | 10 pF
zs_ras_n_from_the_sdram | H2 | 1 | 0 | 24 | 2 | yes | no | yes | no | no | no | no | no | Off | LVTTL | 24mA | Off | User | 10 pF
zs_we_n_from_the_sdram | G4 | 1 | 0 | 25 | 2 | yes | no | yes | no | no | no | no | no | Off | LVTTL | 24mA | Off | User | 10 pF

## Bidir Pins

Top

Name | Pin # | I/O Bank | X coordinate | Y coordinate | Cell number | Combinational Fan-Out | Registered Fan-Out | Global | Input Register | Output Register | Output Enable Register | Power Up High | Slow Slew Rate | PCI I/O Enabled | Open Drain | Bus Hold | Weak Pull Up | I/O Standard | Current Strength | Termination | Location assigned by | Load
--- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | ---
LCD_data_to_and_from_the_lcd_display[0] | H14 | 3 | 69 | 21 | 1 | 1 | 0 | no | no | no | no | no | no | no | no | no | Off | LVTTL | 24mA | Off | User | 10 pF
LCD_data_to_and_from_the_lcd_display[1] | J14 | 3 | 69 | 21 | 2 | 1 | 0 | no | no | no | no | no | no | no | no | no | Off | LVTTL | 24mA | Off | User | 10 pF
LCD_data_to_and_from_the_lcd_display[2] | J17 | 3 | 69 | 20 | 0 | 1 | 0 | no | no | no | no | no | no | no | no | no | Off | LVTTL | 24mA | Off | User | 10 pF
LCD_data_to_and_from_the_lcd_display[3] | J18 | 3 | 69 | 20 | 1 | 1 | 0 | no | no | no | no | no | no | no | no | no | Off | LVTTL | 24mA | Off | User | 10 pF
LCD_data_to_and_from_the_lcd_display[4] | K15 | 3 | 69 | 20 | 2 | 1 | 0 | no | no | no | no | no | no | no | no | no | Off | LVTTL | 24mA | Off | User | 10 pF
LCD_data_to_and_from_the_lcd_display[5] | W18 | 3 | 69 | 1 | 1 | 1 | 0 | no | no | no | no | no | no | no | no | no | Off | LVTTL | 24mA | Off | User | 10 pF
LCD_data_to_and_from_the_lcd_display[6] | V18 | 3 | 69 | 1 | 0 | 1 | 0 | no | no | no | no | no | no | no | no | no | Off | LVTTL | 24mA | Off | User | 10 pF
LCD_data_to_and_from_the_lcd_display[7] | V19 | 3 | 69 | 2 | 2 | 1 | 0 | no | no | no | no | no | no | no | no | no | Off | LVTTL | 24mA | Off | User | 10 pF
bidir_port_to_and_from_the_reconfig_request_pio | V8 | 4 | 22 | 0 | 1 | 1 | 0 | no | no | no | no | no | no | no | no | no | Off | LVTTL | 24mA | Off | User | 10 pF
ext_ram_bus_data[0] | C6 | 2 | 10 | 33 | 2 | 0 | 8 | no | yes | yes | yes | no | no | no | no | no | Off | LVTTL | 24mA | Off | User | 10 pF
ext_ram_bus_data[10] | F8 | 2 | 18 | 33 | 1 | 0 | 2 | no | yes | yes | yes | no | no | no | no | no | Off | LVTTL | 24mA | Off | User | 10 pF
ext_ram_bus_data[11] | E8 | 2 | 18 | 33 | 0 | 0 | 2 | no | yes | yes | yes | no | no | no | no | no | Off | LVTTL | 24mA | Off | User | 10 pF
ext_ram_bus_data[12] | B8 | 2 | 22 | 33 | 1 | 0 | 2 | no | yes | yes | yes | no | no | no | no | no | Off | LVTTL | 24mA | Off | User | 10 pF
ext_ram_bus_data[13] | A8 | 2 | 22 | 33 | 0 | 0 | 2 | no | yes | yes | yes | no | no | no | no | no | Off | LVTTL | 24mA | Off | User | 10 pF
ext_ram_bus_data[14] | D8 | 2 | 24 | 33 | 1 | 0 | 2 | no | yes | yes | yes | no | no | no | no | no | Off | LVTTL | 24mA | Off | User | 10 pF
ext_ram_bus_data[15] | C8 | 2 | 24 | 33 | 0 | 0 | 2 | no | yes | yes | yes | no | no | no | no | no | Off | LVTTL | 24mA | Off | User | 10 pF
ext_ram_bus_data[16] | B9 | 2 | 26 | 33 | 1 | 0 | 2 | no | yes | yes | yes | no | no | no | no | no | Off | LVTTL | 24mA | Off | User | 10 pF
ext_ram_bus_data[17] | A9 | 2 | 26 | 33 | 0 | 0 | 2 | no | yes | yes | yes | no | no | no | no | no | Off | LVTTL | 24mA | Off | User | 10 pF
ext_ram_bus_data[18] | D9 | 2 | 28 | 33 | 1 | 0 | 2 | no | yes | yes | yes | no | no | no | no | no | Off | LVTTL | 24mA | Off | User | 10 pF
ext_ram_bus_data[19] | C9 | 2 | 28 | 33 | 0 | 0 | 2 | no | yes | yes | yes | no | no | no | no | no | Off | LVTTL | 24mA | Off | User | 10 pF
ext_ram_bus_data[1] | E6 | 2 | 10 | 33 | 1 | 0 | 8 | no | yes | yes | yes | no | no | no | no | no | Off | LVTTL | 24mA | Off | User | 10 pF
ext_ram_bus_data[20] | E9 | 2 | 30 | 33 | 1 | 0 | 2 | no | yes | yes | yes | no | no | no | no | no | Off | LVTTL | 24mA | Off | User | 10 pF
ext_ram_bus_data[21] | E10 | 2 | 30 | 33 | 0 | 0 | 2 | no | yes | yes | yes | no | no | no | no | no | Off | LVTTL | 24mA | Off | User | 10 pF
ext_ram_bus_data[22] | B10 | 2 | 32 | 33 | 2 | 0 | 2 | no | yes | yes | yes | no | no | no | no | no | Off | LVTTL | 24mA | Off | User | 10 pF
ext_ram_bus_data[23] | A10 | 2 | 32 | 33 | 1 | 0 | 2 | no | yes | yes | yes | no | no | no | no | no | Off | LVTTL | 24mA | Off | User | 10 pF
ext_ram_bus_data[24] | F10 | 2 | 32 | 33 | 0 | 0 | 2 | no | yes | yes | yes | no | no | no | no | no | Off | LVTTL | 24mA | Off | User | 10 pF
ext_ram_bus_data[25] | C10 | 2 | 34 | 33 | 2 | 0 | 2 | no | yes | yes | yes | no | no | no | no | no | Off | LVTTL | 24mA | Off | User | 10 pF
ext_ram_bus_data[26] | D10 | 2 | 34 | 33 | 1 | 0 | 2 | no | yes | yes | yes | no | no | no | no | no | Off | LVTTL | 24mA | Off | User | 10 pF
ext_ram_bus_data[27] | C11 | 2 | 34 | 33 | 0 | 0 | 2 | no | yes | yes | yes | no | no | no | no | no | Off | LVTTL | 24mA | Off | User | 10 pF
ext_ram_bus_data[28] | D11 | 2 | 36 | 33 | 2 | 0 | 2 | no | yes | yes | yes | no | no | no | no | no | Off | LVTTL | 24mA | Off | User | 10 pF
ext_ram_bus_data[29] | B11 | 2 | 36 | 33 | 1 | 0 | 2 | no | yes | yes | yes | no | no | no | no | no | Off | LVTTL | 24mA | Off | User | 10 pF
ext_ram_bus_data[2] | B6 | 2 | 10 | 33 | 0 | 0 | 8 | no | yes | yes | yes | no | no | no | no | no | Off | LVTTL | 24mA | Off | User | 10 pF
ext_ram_bus_data[30] | A11 | 2 | 36 | 33 | 0 | 0 | 2 | no | yes | yes | yes | no | no | no | no | no | Off | LVTTL | 24mA | Off | User | 10 pF
ext_ram_bus_data[31] | E11 | 2 | 38 | 33 | 2 | 0 | 2 | no | yes | yes | yes | no | no | no | no | no | Off | LVTTL | 24mA | Off | User | 10 pF
ext_ram_bus_data[3] | A6 | 2 | 12 | 33 | 1 | 0 | 8 | no | yes | yes | yes | no | no | no | no | no | Off | LVTTL | 24mA | Off | User | 10 pF
ext_ram_bus_data[4] | F7 | 2 | 12 | 33 | 0 | 0 | 8 | no | yes | yes | yes | no | no | no | no | no | Off | LVTTL | 24mA | Off | User | 10 pF
ext_ram_bus_data[5] | E7 | 2 | 14 | 33 | 2 | 0 | 8 | no | yes | yes | yes | no | no | no | no | no | Off | LVTTL | 24mA | Off | User | 10 pF
ext_ram_bus_data[6] | B7 | 2 | 14 | 33 | 1 | 0 | 8 | no | yes | yes | yes | no | no | no | no | no | Off | LVTTL | 24mA | Off | User | 10 pF
ext_ram_bus_data[7] | A7 | 2 | 14 | 33 | 0 | 0 | 8 | no | yes | yes | yes | no | no | no | no | no | Off | LVTTL | 24mA | Off | User | 10 pF
ext_ram_bus_data[8] | D7 | 2 | 16 | 33 | 1 | 0 | 2 | no | yes | yes | yes | no | no | no | no | no | Off | LVTTL | 24mA | Off | User | 10 pF
ext_ram_bus_data[9] | C7 | 2 | 16 | 33 | 0 | 0 | 2 | no | yes | yes | yes | no | no | no | no | no | Off | LVTTL | 24mA | Off | User | 10 pF
zs_dq_to_and_from_the_sdram[0] | M5 | 1 | 0 | 13 | 2 | 0 | 2 | no | yes | yes | no | no | no | no | no | no | Off | LVTTL | 24mA | Off | User | 10 pF
zs_dq_to_and_from_the_sdram[10] | P7 | 1 | 0 | 9 | 2 | 0 | 2 | no | yes | yes | no | no | no | no | no | no | Off | LVTTL | 24mA | Off | User | 10 pF
zs_dq_to_and_from_the_sdram[11] | P2 | 1 | 0 | 8 | 0 | 0 | 2 | no | yes | yes | no | no | no | no | no | no | Off | LVTTL | 24mA | Off | User | 10 pF
zs_dq_to_and_from_the_sdram[12] | P1 | 1 | 0 | 8 | 1 | 0 | 2 | no | yes | yes | no | no | no | no | no | no | Off | LVTTL | 24mA | Off | User | 10 pF
zs_dq_to_and_from_the_sdram[13] | P6 | 1 | 0 | 7 | 0 | 0 | 2 | no | yes | yes | no | no | no | no | no | no | Off | LVTTL | 24mA | Off | User | 10 pF
zs_dq_to_and_from_the_sdram[14] | P5 | 1 | 0 | 7 | 1 | 0 | 2 | no | yes | yes | no | no | no | no | no | no | Off | LVTTL | 24mA | Off | User | 10 pF
zs_dq_to_and_from_the_sdram[15] | P3 | 1 | 0 | 6 | 0 | 0 | 2 | no | yes | yes | no | no | no | no | no | no | Off | LVTTL | 24mA | Off | User | 10 pF
zs_dq_to_and_from_the_sdram[16] | P4 | 1 | 0 | 6 | 1 | 0 | 2 | no | yes | yes | no | no | no | no | no | no | Off | LVTTL | 24mA | Off | User | 10 pF
zs_dq_to_and_from_the_sdram[17] | R1 | 1 | 0 | 6 | 2 | 0 | 2 | no | yes | yes | no | no | no | no | no | no | Off | LVTTL | 24mA | Off | User | 10 pF
zs_dq_to_and_from_the_sdram[18] | R2 | 1 | 0 | 5 | 0 | 0 | 2 | no | yes | yes | no | no | no | no | no | no | Off | LVTTL | 24mA | Off | User | 10 pF
zs_dq_to_and_from_the_sdram[19] | R6 | 1 | 0 | 5 | 1 | 0 | 2 | no | yes | yes | no | no | no | no | no | no | Off | LVTTL | 24mA | Off | User | 10 pF
zs_dq_to_and_from_the_sdram[1] | M3 | 1 | 0 | 12 | 2 | 0 | 2 | no | yes | yes | no | no | no | no | no | no | Off | LVTTL | 24mA | Off | User | 10 pF
zs_dq_to_and_from_the_sdram[20] | R5 | 1 | 0 | 5 | 2 | 0 | 2 | no | yes | yes | no | no | no | no | no | no | Off | LVTTL | 24mA | Off | User | 10 pF
zs_dq_to_and_from_the_sdram[21] | R3 | 1 | 0 | 4 | 0 | 0 | 2 | no | yes | yes | no | no | no | no | no | no | Off | LVTTL | 24mA | Off | User | 10 pF
zs_dq_to_and_from_the_sdram[22] | R4 | 1 | 0 | 4 | 1 | 0 | 2 | no | yes | yes | no | no | no | no | no | no | Off | LVTTL | 24mA | Off | User | 10 pF
zs_dq_to_and_from_the_sdram[23] | T4 | 1 | 0 | 4 | 2 | 0 | 2 | no | yes | yes | no | no | no | no | no | no | Off | LVTTL | 24mA | Off | User | 10 pF
zs_dq_to_and_from_the_sdram[24] | T2 | 1 | 0 | 3 | 0 | 0 | 2 | no | yes | yes | no | no | no | no | no | no | Off | LVTTL | 24mA | Off | User | 10 pF
zs_dq_to_and_from_the_sdram[25] | T3 | 1 | 0 | 3 | 1 | 0 | 2 | no | yes | yes | no | no | no | no | no | no | Off | LVTTL | 24mA | Off | User | 10 pF
zs_dq_to_and_from_the_sdram[26] | U1 | 1 | 0 | 3 | 2 | 0 | 2 | no | yes | yes | no | no | no | no | no | no | Off | LVTTL | 24mA | Off | User | 10 pF
zs_dq_to_and_from_the_sdram[27] | U4 | 1 | 0 | 2 | 0 | 0 | 2 | no | yes | yes | no | no | no | no | no | no | Off | LVTTL | 24mA | Off | User | 10 pF
zs_dq_to_and_from_the_sdram[28] | U2 | 1 | 0 | 2 | 1 | 0 | 2 | no | yes | yes | no | no | no | no | no | no | Off | LVTTL | 24mA | Off | User | 10 pF
zs_dq_to_and_from_the_sdram[29] | U3 | 1 | 0 | 2 | 2 | 0 | 2 | no | yes | yes | no | no | no | no | no | no | Off | LVTTL | 24mA | Off | User | 10 pF
zs_dq_to_and_from_the_sdram[2] | M7 | 1 | 0 | 11 | 0 | 0 | 3 | no | yes | yes | no | no | no | no | no | no | Off | LVTTL | 24mA | Off | User | 10 pF
zs_dq_to_and_from_the_sdram[30] | V3 | 1 | 0 | 1 | 1 | 0 | 2 | no | yes | yes | no | no | no | no | no | no | Off | LVTTL | 24mA | Off | User | 10 pF
zs_dq_to_and_from_the_sdram[31] | V2 | 1 | 0 | 1 | 0 | 0 | 2 | no | yes | yes | no | no | no | no | no | no | Off | LVTTL | 24mA | Off | User | 10 pF
zs_dq_to_and_from_the_sdram[3] | N6 | 1 | 0 | 11 | 1 | 0 | 3 | no | yes | yes | no | no | no | no | no | no | Off | LVTTL | 24mA | Off | User | 10 pF
zs_dq_to_and_from_the_sdram[4] | N1 | 1 | 0 | 11 | 2 | 0 | 3 | no | yes | yes | no | no | no | no | no | no | Off | LVTTL | 24mA | Off | User | 10 pF
zs_dq_to_and_from_the_sdram[5] | N2 | 1 | 0 | 10 | 0 | 0 | 3 | no | yes | yes | no | no | no | no | no | no | Off | LVTTL | 24mA | Off | User | 10 pF
zs_dq_to_and_from_the_sdram[6] | N4 | 1 | 0 | 10 | 1 | 0 | 3 | no | yes | yes | no | no | no | no | no | no | Off | LVTTL | 24mA | Off | User | 10 pF
zs_dq_to_and_from_the_sdram[7] | N3 | 1 | 0 | 10 | 2 | 0 | 2 | no | yes | yes | no | no | no | no | no | no | Off | LVTTL | 24mA | Off | User | 10 pF
zs_dq_to_and_from_the_sdram[8] | N5 | 1 | 0 | 9 | 0 | 0 | 2 | no | yes | yes | no | no | no | no | no | no | Off | LVTTL | 24mA | Off | User | 10 pF
zs_dq_to_and_from_the_sdram[9] | N7 | 1 | 0 | 9 | 1 | 0 | 2 | no | yes | yes | no | no | no | no | no | no | Off | LVTTL | 24mA | Off | User | 10 pF

## I/O Bank Usage

Top

I/O Bank | Usage | VCCIO Voltage | VREF Voltage
--- | --- | --- | ---
1 | 76 / 80 ( 95 % ) | 3.3V | --
2 | 59 / 70 ( 84 % ) | 3.3V | --
3 | 15 / 81 ( 19 % ) | 3.3V | --
4 | 28 / 70 ( 40 % ) | 3.3V | --

## All Package Pins

Top

Location | Pad Number | I/O Bank | Pin Name/Usage | Dir. | I/O Standard | Voltage | I/O Type | User Assignment | Bus Hold | Weak Pull Up
--- | --- | --- | --- | --- | --- | --- | --- | --- | --- | ---
A1 |  |  | GND | gnd |  |  | -- |  | -- | --
A2 |  |  | VCCINT | power |  | 1.5V | -- |  | -- | --
A3 |  |  | GND | gnd |  |  | -- |  | -- | --
A4 | 310 | 2 | ext_ram_bus_address[1] | output | LVTTL |  | Column I/O | Y | no | Off
A5 |  | 2 | VCCIO2 | power |  | 3.3V | -- |  | -- | --
A6 | 302 | 2 | ext_ram_bus_data[3] | bidir | LVTTL |  | Column I/O | Y | no | Off
A7 | 298 | 2 | ext_ram_bus_data[7] | bidir | LVTTL |  | Column I/O | Y | no | Off
A8 | 292 | 2 | ext_ram_bus_data[13] | bidir | LVTTL |  | Column I/O | Y | no | Off
A9 | 288 | 2 | ext_ram_bus_data[17] | bidir | LVTTL |  | Column I/O | Y | no | Off
A10 | 282 | 2 | ext_ram_bus_data[23] | bidir | LVTTL |  | Column I/O | Y | no | Off
A11 | 275 | 2 | ext_ram_bus_data[30] | bidir | LVTTL |  | Column I/O | Y | no | Off
A12 | 270 | 2 | select_n_to_the_ext_flash | output | LVTTL |  | Column I/O | Y | no | Off
A13 | 264 | 2 | RESERVED_INPUT |  |  |  | Column I/O |  | no | Off
A14 | 258 | 2 | ENET_ADS_N | output | LVTTL |  | Column I/O | Y | no | Off
A15 | 255 | 2 | ior_n_to_the_lan91c111 | output | LVTTL |  | Column I/O | Y | no | Off
A16 |  | 2 | VCCIO2 | power |  | 3.3V | -- |  | -- | --
A17 | 247 | 2 | RESERVED_INPUT |  |  |  | Column I/O |  | no | Off
A18 |  |  | GND | gnd |  |  | -- |  | -- | --
A19 |  |  | VCCINT | power |  | 1.5V | -- |  | -- | --
A20 |  |  | GND | gnd |  |  | -- |  | -- | --
B1 |  |  | VCCINT | power |  | 1.5V | -- |  | -- | --
B2 |  |  | GND | gnd |  |  | -- |  | -- | --
B3 | 312 | 2 | out_port_from_the_led_pio[6] | output | LVTTL |  | Column I/O | Y | no | Off
B4 | 311 | 2 | ext_ram_bus_address[0] | output | LVTTL |  | Column I/O | Y | no | Off
B5 | 306 | 2 | ext_ram_bus_address[5] | output | LVTTL |  | Column I/O | Y | no | Off
B6 | 303 | 2 | ext_ram_bus_data[2] | bidir | LVTTL |  | Column I/O | Y | no | Off
B7 | 299 | 2 | ext_ram_bus_data[6] | bidir | LVTTL |  | Column I/O | Y | no | Off
B8 | 293 | 2 | ext_ram_bus_data[12] | bidir | LVTTL |  | Column I/O | Y | no | Off
B9 | 289 | 2 | ext_ram_bus_data[16] | bidir | LVTTL |  | Column I/O | Y | no | Off
B10 | 283 | 2 | ext_ram_bus_data[22] | bidir | LVTTL |  | Column I/O | Y | no | Off
B11 | 276 | 2 | ext_ram_bus_data[29] | bidir | LVTTL |  | Column I/O | Y | no | Off
B12 | 271 | 2 | read_n_to_the_ext_flash | output | LVTTL |  | Column I/O | Y | no | Off
B13 | 265 | 2 | RESERVED_INPUT |  |  |  | Column I/O |  | no | Off
B14 | 259 | 2 | out_port_from_the_led_pio[7] | output | LVTTL |  | Column I/O | Y | no | Off
B15 | 254 | 2 | ENET_AEN | output | LVTTL |  | Column I/O | Y | no | Off
B16 | 249 | 2 | byteenablen_to_the_lan91c111[1] | output | LVTTL |  | Column I/O | Y | no | Off
B17 | 246 | 2 | RESERVED_INPUT |  |  |  | Column I/O |  | no | Off
B18 | 245 | 2 | RESERVED_INPUT |  |  |  | Column I/O |  | no | Off
B19 |  |  | GND | gnd |  |  | -- |  | -- | --
B20 |  |  | VCCINT | power |  | 1.5V | -- |  | -- | --
C1 |  |  | GND | gnd |  |  | -- |  | -- | --
C2 | 1 | 1 | ext_ram_bus_address[6] | output | LVTTL |  | Row I/O | Y | no | Off
C3 | 0 | 1 | RESERVED_INPUT |  |  |  | Row I/O |  | no | Off
C4 | 313 | 2 | PLD_CLEAR_N | input | LVTTL |  | Column I/O | Y | no | Off
C5 | 307 | 2 | ext_ram_bus_address[4] | output | LVTTL |  | Column I/O | Y | no | Off
C6 | 305 | 2 | ext_ram_bus_data[0] | bidir | LVTTL |  | Column I/O | Y | no | Off
C7 | 296 | 2 | ext_ram_bus_data[9] | bidir | LVTTL |  | Column I/O | Y | no | Off
C8 | 290 | 2 | ext_ram_bus_data[15] | bidir | LVTTL |  | Column I/O | Y | no | Off
C9 | 286 | 2 | ext_ram_bus_data[19] | bidir | LVTTL |  | Column I/O | Y | no | Off
C10 | 280 | 2 | ext_ram_bus_data[25] | bidir | LVTTL |  | Column I/O | Y | no | Off
C11 | 278 | 2 | ext_ram_bus_data[27] | bidir | LVTTL |  | Column I/O | Y | no | Off
C12 | 273 | 2 | RESERVED_INPUT |  |  |  | Column I/O |  | no | Off
C13 | 266 | 2 | RESERVED_INPUT |  |  |  | Column I/O |  | no | Off
C14 | 262 | 2 | out_port_from_the_led_pio[2] | output | LVTTL |  | Column I/O | Y | no | Off
C15 | 252 | 2 | RESERVED_INPUT |  |  |  | Column I/O |  | no | Off
C16 | 248 | 2 | byteenablen_to_the_lan91c111[0] | output | LVTTL |  | Column I/O | Y | no | Off
C17 | 244 | 2 | RESERVED_INPUT |  |  |  | Column I/O |  | no | Off
C18 | 243 | 3 | RESERVED_INPUT |  |  |  | Row I/O |  | no | Off
C19 | 242 | 3 | RESERVED_INPUT |  |  |  | Row I/O |  | no | Off
C20 |  |  | GND | gnd |  |  | -- |  | -- | --
D1 | 5 | 1 | ext_ram_bus_address[9] | output | LVTTL |  | Row I/O | Y | no | Off
D2 | 3 | 1 | ext_ram_bus_address[7] | output | LVTTL |  | Row I/O | Y | no | Off
D3 | 2 | 1 | RESERVED_INPUT |  |  |  | Row I/O |  | no | Off
D4 | 4 | 1 | ext_ram_bus_address[8] | output | LVTTL |  | Row I/O | Y | no | Off
D5 | 309 | 2 | ext_ram_bus_address[2] | output | LVTTL |  | Column I/O | Y | no | Off
D6 | 308 | 2 | ext_ram_bus_address[3] | output | LVTTL |  | Column I/O | Y | no | Off
D7 | 297 | 2 | ext_ram_bus_data[8] | bidir | LVTTL |  | Column I/O | Y | no | Off
D8 | 291 | 2 | ext_ram_bus_data[14] | bidir | LVTTL |  | Column I/O | Y | no | Off
D9 | 287 | 2 | ext_ram_bus_data[18] | bidir | LVTTL |  | Column I/O | Y | no | Off
D10 | 279 | 2 | ext_ram_bus_data[26] | bidir | LVTTL |  | Column I/O | Y | no | Off
D11 | 277 | 2 | ext_ram_bus_data[28] | bidir | LVTTL |  | Column I/O | Y | no | Off
D12 | 272 | 2 | write_n_to_the_ext_flash | output | LVTTL |  | Column I/O | Y | no | Off
D13 | 267 | 2 | RESERVED_INPUT |  |  |  | Column I/O |  | no | Off
D14 | 263 | 2 | out_port_from_the_led_pio[3] | output | LVTTL |  | Column I/O | Y | no | Off
D15 | 253 | 2 | irq_from_the_lan91c111 | input | LVTTL |  | Column I/O | Y | no | Off
D16 | 250 | 2 | byteenablen_to_the_lan91c111[2] | output | LVTTL |  | Column I/O | Y | no | Off
D17 | 239 | 3 | RESERVED_INPUT |  |  |  | Row I/O |  | no | Off
D18 | 241 | 3 | RESERVED_INPUT |  |  |  | Row I/O |  | no | Off
D19 | 240 | 3 | RESERVED_INPUT |  |  |  | Row I/O |  | no | Off
D20 | 238 | 3 | RESERVED_INPUT |  |  |  | Row I/O |  | no | Off
E1 |  | 1 | VCCIO1 | power |  | 3.3V | -- |  | -- | --
E2 | 10 | 1 | ext_ram_bus_address[14] | output | LVTTL |  | Row I/O | Y | no | Off
E3 | 9 | 1 | ext_ram_bus_address[13] | output | LVTTL |  | Row I/O | Y | no | Off
E4 | 6 | 1 | ext_ram_bus_address[10] | output | LVTTL |  | Row I/O | Y | no | Off
E5 | 7 | 1 | ext_ram_bus_address[11] | output | LVTTL |  | Row I/O | Y | no | Off
E6 | 304 | 2 | ext_ram_bus_data[1] | bidir | LVTTL |  | Column I/O | Y | no | Off
E7 | 300 | 2 | ext_ram_bus_data[5] | bidir | LVTTL |  | Column I/O | Y | no | Off
E8 | 294 | 2 | ext_ram_bus_data[11] | bidir | LVTTL |  | Column I/O | Y | no | Off
E9 | 285 | 2 | ext_ram_bus_data[20] | bidir | LVTTL |  | Column I/O | Y | no | Off
E10 | 284 | 2 | ext_ram_bus_data[21] | bidir | LVTTL |  | Column I/O | Y | no | Off
E11 | 274 | 2 | ext_ram_bus_data[31] | bidir | LVTTL |  | Column I/O | Y | no | Off
E12 | 268 | 2 | out_port_from_the_led_pio[4] | output | LVTTL |  | Column I/O | Y | no | Off
E13 | 261 | 2 | out_port_from_the_led_pio[1] | output | LVTTL |  | Column I/O | Y | no | Off
E14 | 260 | 2 | out_port_from_the_led_pio[0] | output | LVTTL |  | Column I/O | Y | no | Off
E15 | 256 | 2 | iow_n_to_the_lan91c111 | output | LVTTL |  | Column I/O | Y | no | Off
E16 | 251 | 2 | byteenablen_to_the_lan91c111[3] | output | LVTTL |  | Column I/O | Y | no | Off
E17 | 237 | 3 | RESERVED_INPUT |  |  |  | Row I/O |  | no | Off
E18 | 234 | 3 | RESERVED_INPUT |  |  |  | Row I/O |  | no | Off
E19 | 233 | 3 | RESERVED_INPUT |  |  |  | Row I/O |  | no | Off
E20 |  | 3 | VCCIO3 | power |  | 3.3V | -- |  | -- | --
F1 | 14 | 1 | ext_ram_bus_address[18] | output | LVTTL |  | Row I/O | Y | no | Off
F2 | 13 | 1 | ext_ram_bus_address[17] | output | LVTTL |  | Row I/O | Y | no | Off
F3 | 8 | 1 | ext_ram_bus_address[12] | output | LVTTL |  | Row I/O | Y | no | Off
F4 | 11 | 1 | ext_ram_bus_address[15] | output | LVTTL |  | Row I/O | Y | no | Off
F5 | 12 | 1 | ext_ram_bus_address[16] | output | LVTTL |  | Row I/O | Y | no | Off
F6 | 15 | 1 | ext_ram_bus_address[19] | output | LVTTL |  | Row I/O | Y | no | Off
F7 | 301 | 2 | ext_ram_bus_data[4] | bidir | LVTTL |  | Column I/O | Y | no | Off
F8 | 295 | 2 | ext_ram_bus_data[10] | bidir | LVTTL |  | Column I/O | Y | no | Off
F9 |  | 2 | VCCIO2 | power |  | 3.3V | -- |  | -- | --
F10 | 281 | 2 | ext_ram_bus_data[24] | bidir | LVTTL |  | Column I/O | Y | no | Off
F11 |  | 2 | VCCIO2 | power |  | 3.3V | -- |  | -- | --
F12 | 269 | 2 | out_port_from_the_led_pio[5] | output | LVTTL |  | Column I/O | Y | no | Off
F13 |  | 2 | VCCIO2 | power |  | 3.3V | -- |  | -- | --
F14 | 257 | 2 | RESERVED_INPUT |  |  |  | Column I/O |  | no | Off
F15 | 231 | 3 | RESERVED_INPUT |  |  |  | Row I/O |  | no | Off
F16 | 232 | 3 | RESERVED_INPUT |  |  |  | Row I/O |  | no | Off
F17 | 236 | 3 | RESERVED_INPUT |  |  |  | Row I/O |  | no | Off
F18 | 235 | 3 | RESERVED_INPUT |  |  |  | Row I/O |  | no | Off
F19 | 230 | 3 | RESERVED_INPUT |  |  |  | Row I/O |  | no | Off
F20 | 229 | 3 | RESERVED_INPUT |  |  |  | Row I/O |  | no | Off
G1 | 17 | 1 | ext_ram_bus_address[21] | output | LVTTL |  | Row I/O | Y | no | Off
G2 | 18 | 1 | ext_ram_bus_address[22] | output | LVTTL |  | Row I/O | Y | no | Off
G3 | 21 | 1 | zs_cas_n_from_the_sdram | output | LVTTL |  | Row I/O | Y | no | Off
G4 | 22 | 1 | zs_we_n_from_the_sdram | output | LVTTL |  | Row I/O | Y | no | Off
G5 | 16 | 1 | ext_ram_bus_address[20] | output | LVTTL |  | Row I/O | Y | no | Off
G6 | 19 | 1 | zs_cs_n_from_the_sdram | output | LVTTL |  | Row I/O | Y | no | Off
G7 | 20 | 1 | zs_cke_from_the_sdram | output | LVTTL |  | Row I/O | Y | no | Off
G8 |  |  | GND | gnd |  |  | -- |  | -- | --
G9 |  |  | GND | gnd |  |  | -- |  | -- | --
G10 |  |  | GND | gnd |  |  | -- |  | -- | --
G11 |  |  | GND | gnd |  |  | -- |  | -- | --
G12 |  |  | GND | gnd |  |  | -- |  | -- | --
G13 |  |  | GND | gnd |  |  | -- |  | -- | --
G14 | 224 | 3 | RESERVED_INPUT |  |  |  | Row I/O |  | no | Off
G15 | 227 | 3 | RESERVED_INPUT |  |  |  | Row I/O |  | no | Off
G16 | 228 | 3 | RESERVED_INPUT |  |  |  | Row I/O |  | no | Off
G17 | 221 | 3 | RESERVED_INPUT |  |  |  | Row I/O |  | no | Off
G18 | 222 | 3 | RESERVED_INPUT |  |  |  | Row I/O |  | no | Off
G19 | 225 | 3 | RESERVED_INPUT |  |  |  | Row I/O |  | no | Off
G20 | 226 | 3 | RESERVED_INPUT |  |  |  | Row I/O |  | no | Off
H1 | 24 | 1 | zs_ba_from_the_sdram[1] | output | LVTTL |  | Row I/O | Y | no | Off
H2 | 25 | 1 | zs_ras_n_from_the_sdram | output | LVTTL |  | Row I/O | Y | no | Off
H3 | 26 | 1 | zs_dqm_from_the_sdram[3] | output | LVTTL |  | Row I/O | Y | no | Off
H4 | 27 | 1 | zs_dqm_from_the_sdram[2] | output | LVTTL |  | Row I/O | Y | no | Off
H5 | 30 | 1 | zs_addr_from_the_sdram[11] | output | LVTTL |  | Row I/O | Y | no | Off
H6 | 31 | 1 | zs_addr_from_the_sdram[10] | output | LVTTL |  | Row I/O | Y | no | Off
H7 | 23 | 1 | zs_ba_from_the_sdram[0] | output | LVTTL |  | Row I/O | Y | no | Off
H8 |  | 1 | VCCIO1 | power |  | 3.3V | -- |  | -- | --
H9 |  |  | GND | gnd |  |  | -- |  | -- | --
H10 |  |  | VCCINT | power |  | 1.5V | -- |  | -- | --
H11 |  |  | GND | gnd |  |  | -- |  | -- | --
H12 |  |  | VCCINT | power |  | 1.5V | -- |  | -- | --
H13 |  | 3 | VCCIO3 | power |  | 3.3V | -- |  | -- | --
H14 | 211 | 3 | LCD_data_to_and_from_the_lcd_display[0] | bidir | LVTTL |  | Row I/O | Y | no | Off
H15 | 223 | 3 | RESERVED_INPUT |  |  |  | Row I/O |  | no | Off
H16 | 220 | 3 | RESERVED_INPUT |  |  |  | Row I/O |  | no | Off
H17 | 218 | 3 | RESERVED_INPUT |  |  |  | Row I/O |  | no | Off
H18 | 219 | 3 | RESERVED_INPUT |  |  |  | Row I/O |  | no | Off
H19 | 217 | 3 | RESERVED_INPUT |  |  |  | Row I/O |  | no | Off
H20 | 216 | 3 | RESERVED_INPUT |  |  |  | Row I/O |  | no | Off
J1 | 28 | 1 | zs_dqm_from_the_sdram[1] | output | LVTTL |  | Row I/O | Y | no | Off
J2 | 29 | 1 | zs_dqm_from_the_sdram[0] | output | LVTTL |  | Row I/O | Y | no | Off
J3 | 32 | 1 | zs_addr_from_the_sdram[9] | output | LVTTL |  | Row I/O | Y | no | Off
J4 | 33 | 1 | zs_addr_from_the_sdram[8] | output | LVTTL |  | Row I/O | Y | no | Off
J5 | 34 | 1 | zs_addr_from_the_sdram[7] | output | LVTTL |  | Row I/O | Y | no | Off
J6 | 35 | 1 | zs_addr_from_the_sdram[6] | output | LVTTL |  | Row I/O | Y | no | Off
J7 | 36 | 1 | zs_addr_from_the_sdram[5] | output | LVTTL |  | Row I/O | Y | no | Off
J8 | 37 | 1 | zs_addr_from_the_sdram[4] | output | LVTTL |  | Row I/O | Y | no | Off
J9 |  |  | VCCINT | power |  | 1.5V | -- |  | -- | --
J10 |  |  | GND | gnd |  |  | -- |  | -- | --
J11 |  |  | VCCINT | power |  | 1.5V | -- |  | -- | --
J12 |  |  | GND | gnd |  |  | -- |  | -- | --
J13 | 205 | 3 | RESERVED_INPUT |  |  |  | Row I/O |  | no | Off
J14 | 210 | 3 | LCD_data_to_and_from_the_lcd_display[1] | bidir | LVTTL |  | Row I/O | Y | no | Off
J15 | 214 | 3 | LCD_RS_from_the_lcd_display | output | LVTTL |  | Row I/O | Y | no | Off
J16 | 215 | 3 | RESERVED_INPUT |  |  |  | Row I/O |  | no | Off
J17 | 209 | 3 | LCD_data_to_and_from_the_lcd_display[2] | bidir | LVTTL |  | Row I/O | Y | no | Off
J18 | 208 | 3 | LCD_data_to_and_from_the_lcd_display[3] | bidir | LVTTL |  | Row I/O | Y | no | Off
J19 | 213 | 3 | LCD_RW_from_the_lcd_display | output | LVTTL |  | Row I/O | Y | no | Off
J20 | 212 | 3 | LCD_E_from_the_lcd_display | output | LVTTL |  | Row I/O | Y | no | Off
K1 | 40 | 1 | ^nCONFIG |  |  |  | -- |  | -- | --
K2 | 38 | 1 | +~nCSO~ | input | LVTTL |  | Row I/O | N | no | Off
K3 | 39 | 1 | ^DATA0 | input |  |  | -- |  | -- | --
K4 |  |  | VCCA_PLL1 | power |  | 1.5V | -- |  | -- | --
K5 | 41 | 1 | PLD_CLOCKINPUT[1] | input | LVTTL |  | Row I/O | Y | no | Off
K6 | 42 | 1 | GND+ |  |  |  | Row I/O |  | -- | --
K7 |  |  | GNDA_PLL1 | gnd |  |  | -- |  | -- | --
K8 |  | 1 | VCCIO1 | power |  | 3.3V | -- |  | -- | --
K9 |  |  | GND | gnd |  |  | -- |  | -- | --
K10 |  |  | VCCINT | power |  | 1.5V | -- |  | -- | --
K11 |  |  | GND | gnd |  |  | -- |  | -- | --
K12 |  |  | VCCINT | power |  | 1.5V | -- |  | -- | --
K13 |  | 3 | VCCIO3 | power |  | 3.3V | -- |  | -- | --
K14 | 201 | 3 | GND+ |  |  |  | Row I/O |  | -- | --
K15 | 207 | 3 | LCD_data_to_and_from_the_lcd_display[4] | bidir | LVTTL |  | Row I/O | Y | no | Off
K16 | 206 | 3 | rxd_to_the_uart1 | input | LVTTL |  | Row I/O | Y | no | Off
K17 |  |  | VCCA_PLL2 | power |  | 1.5V | -- |  | -- | --
K18 | 203 | 3 | #altera_reserved_tdi | input | LVTTL |  | -- | N | no | Off
K19 | 204 | 3 | RESERVED_INPUT |  |  |  | Row I/O |  | no | Off
K20 |  |  | GNDA_PLL2 | gnd |  |  | -- |  | -- | --
L1 | 45 | 1 | ^MSEL0 |  |  |  | -- |  | -- | --
L2 | 43 | 1 | ^nCEO |  |  |  | -- |  | -- | --
L3 | 47 | 1 | ^DCLK | bidir |  |  | -- |  | -- | --
L4 | 48 | 1 | +~ASDO~ | input | LVTTL |  | Row I/O | N | no | Off
L5 | 44 | 1 | ^nCE |  |  |  | -- |  | -- | --
L6 | 46 | 1 | ^MSEL1 |  |  |  | -- |  | -- | --
L7 |  |  | GNDG_PLL1 | gnd |  |  | -- |  | -- | --
L8 | 49 | 1 | PLD_CLKOUT | output | LVTTL |  | Row I/O | Y | no | Off
L9 |  |  | VCCINT | power |  | 1.5V | -- |  | -- | --
L10 |  |  | GND | gnd |  |  | -- |  | -- | --
L11 |  |  | VCCINT | power |  | 1.5V | -- |  | -- | --
L12 |  |  | GND | gnd |  |  | -- |  | -- | --
L13 | 195 | 3 | SDRAM_CLK | output | LVTTL |  | Row I/O | Y | no | Off
L14 | 202 | 3 | PLD_CLKFB | input | LVTTL |  | Row I/O | Y | no | Off
L15 |  |  | GNDG_PLL2 | gnd |  |  | -- |  | -- | --
L16 | 199 | 3 | #altera_reserved_tms | input | LVTTL |  | -- | N | no | Off
L17 | 197 | 3 | ^nSTATUS |  |  |  | -- |  | -- | --
L18 | 196 | 3 | ^CONF_DONE |  |  |  | -- |  | -- | --
L19 | 198 | 3 | #altera_reserved_tck | input | LVTTL |  | -- | N | no | Off
L20 | 200 | 3 | #altera_reserved_tdo | output | LVTTL |  | -- | N | no | Off
M1 | 52 | 1 | zs_addr_from_the_sdram[1] | output | LVTTL |  | Row I/O | Y | no | Off
M2 | 51 | 1 | zs_addr_from_the_sdram[0] | output | LVTTL |  | Row I/O | Y | no | Off
M3 | 56 | 1 | zs_dq_to_and_from_the_sdram[1] | bidir | LVTTL |  | Row I/O | Y | no | Off
M4 | 55 | 1 | zs_addr_from_the_sdram[3] | output | LVTTL |  | Row I/O | Y | no | Off
M5 | 53 | 1 | zs_dq_to_and_from_the_sdram[0] | bidir | LVTTL |  | Row I/O | Y | no | Off
M6 | 54 | 1 | zs_addr_from_the_sdram[2] | output | LVTTL |  | Row I/O | Y | no | Off
M7 | 57 | 1 | zs_dq_to_and_from_the_sdram[2] | bidir | LVTTL |  | Row I/O | Y | no | Off
M8 | 50 | 1 | RESERVED_INPUT |  |  |  | Row I/O |  | no | Off
M9 |  |  | GND | gnd |  |  | -- |  | -- | --
M10 |  |  | VCCINT | power |  | 1.5V | -- |  | -- | --
M11 |  |  | GND | gnd |  |  | -- |  | -- | --
M12 |  |  | VCCINT | power |  | 1.5V | -- |  | -- | --
M13 | 194 | 3 | RESERVED_INPUT |  |  |  | Row I/O |  | no | Off
M14 | 193 | 3 | txd_from_the_uart1 | output | LVTTL |  | Row I/O | Y | no | Off
M15 | 189 | 3 | RESERVED_INPUT |  |  |  | Row I/O |  | no | Off
M16 | 190 | 3 | RESERVED_INPUT |  |  |  | Row I/O |  | no | Off
M17 | 188 | 3 | RESERVED_INPUT |  |  |  | Row I/O |  | no | Off
M18 | 187 | 3 | RESERVED_INPUT |  |  |  | Row I/O |  | no | Off
M19 | 192 | 3 | RESERVED_INPUT |  |  |  | Row I/O |  | no | Off
M20 | 191 | 3 | RESERVED_INPUT |  |  |  | Row I/O |  | no | Off
N1 | 59 | 1 | zs_dq_to_and_from_the_sdram[4] | bidir | LVTTL |  | Row I/O | Y | no | Off
N2 | 60 | 1 | zs_dq_to_and_from_the_sdram[5] | bidir | LVTTL |  | Row I/O | Y | no | Off
N3 | 62 | 1 | zs_dq_to_and_from_the_sdram[7] | bidir | LVTTL |  | Row I/O | Y | no | Off
N4 | 61 | 1 | zs_dq_to_and_from_the_sdram[6] | bidir | LVTTL |  | Row I/O | Y | no | Off
N5 | 63 | 1 | zs_dq_to_and_from_the_sdram[8] | bidir | LVTTL |  | Row I/O | Y | no | Off
N6 | 58 | 1 | zs_dq_to_and_from_the_sdram[3] | bidir | LVTTL |  | Row I/O | Y | no | Off
N7 | 64 | 1 | zs_dq_to_and_from_the_sdram[9] | bidir | LVTTL |  | Row I/O | Y | no | Off
N8 |  | 1 | VCCIO1 | power |  | 3.3V | -- |  | -- | --
N9 |  |  | VCCINT | power |  | 1.5V | -- |  | -- | --
N10 |  |  | GND | gnd |  |  | -- |  | -- | --
N11 |  |  | VCCINT | power |  | 1.5V | -- |  | -- | --
N12 |  |  | GND | gnd |  |  | -- |  | -- | --
N13 |  | 3 | VCCIO3 | power |  | 3.3V | -- |  | -- | --
N14 | 180 | 3 | RESERVED_INPUT |  |  |  | Row I/O |  | no | Off
N15 | 186 | 3 | RESERVED_INPUT |  |  |  | Row I/O |  | no | Off
N16 | 185 | 3 | RESERVED_INPUT |  |  |  | Row I/O |  | no | Off
N17 | 182 | 3 | RESERVED_INPUT |  |  |  | Row I/O |  | no | Off
N18 | 181 | 3 | RESERVED_INPUT |  |  |  | Row I/O |  | no | Off
N19 | 183 | 3 | RESERVED_INPUT |  |  |  | Row I/O |  | no | Off
N20 | 184 | 3 | RESERVED_INPUT |  |  |  | Row I/O |  | no | Off
P1 | 67 | 1 | zs_dq_to_and_from_the_sdram[12] | bidir | LVTTL |  | Row I/O | Y | no | Off
P2 | 66 | 1 | zs_dq_to_and_from_the_sdram[11] | bidir | LVTTL |  | Row I/O | Y | no | Off
P3 | 70 | 1 | zs_dq_to_and_from_the_sdram[15] | bidir | LVTTL |  | Row I/O | Y | no | Off
P4 | 71 | 1 | zs_dq_to_and_from_the_sdram[16] | bidir | LVTTL |  | Row I/O | Y | no | Off
P5 | 69 | 1 | zs_dq_to_and_from_the_sdram[14] | bidir | LVTTL |  | Row I/O | Y | no | Off
P6 | 68 | 1 | zs_dq_to_and_from_the_sdram[13] | bidir | LVTTL |  | Row I/O | Y | no | Off
P7 | 65 | 1 | zs_dq_to_and_from_the_sdram[10] | bidir | LVTTL |  | Row I/O | Y | no | Off
P8 |  |  | GND | gnd |  |  | -- |  | -- | --
P9 |  |  | GND | gnd |  |  | -- |  | -- | --
P10 |  |  | GND | gnd |  |  | -- |  | -- | --
P11 |  |  | GND | gnd |  |  | -- |  | -- | --
P12 |  |  | GND | gnd |  |  | -- |  | -- | --
P13 |  |  | GND | gnd |  |  | -- |  | -- | --
P14 | 173 | 3 | RESERVED_INPUT |  |  |  | Row I/O |  | no | Off
P15 | 177 | 3 | RESERVED_INPUT |  |  |  | Row I/O |  | no | Off
P16 | 176 | 3 | RESERVED_INPUT |  |  |  | Row I/O |  | no | Off
P17 | 175 | 3 | RESERVED_INPUT |  |  |  | Row I/O |  | no | Off
P18 | 174 | 3 | RESERVED_INPUT |  |  |  | Row I/O |  | no | Off
P19 | 178 | 3 | RESERVED_INPUT |  |  |  | Row I/O |  | no | Off
P20 | 179 | 3 | RESERVED_INPUT |  |  |  | Row I/O |  | no | Off
R1 | 72 | 1 | zs_dq_to_and_from_the_sdram[17] | bidir | LVTTL |  | Row I/O | Y | no | Off
R2 | 73 | 1 | zs_dq_to_and_from_the_sdram[18] | bidir | LVTTL |  | Row I/O | Y | no | Off
R3 | 76 | 1 | zs_dq_to_and_from_the_sdram[21] | bidir | LVTTL |  | Row I/O | Y | no | Off
R4 | 77 | 1 | zs_dq_to_and_from_the_sdram[22] | bidir | LVTTL |  | Row I/O | Y | no | Off
R5 | 75 | 1 | zs_dq_to_and_from_the_sdram[20] | bidir | LVTTL |  | Row I/O | Y | no | Off
R6 | 74 | 1 | zs_dq_to_and_from_the_sdram[19] | bidir | LVTTL |  | Row I/O | Y | no | Off
R7 | 103 | 4 | out_port_from_the_seven_seg_pio[2] | output | LVTTL |  | Column I/O | Y | no | Off
R8 |  | 4 | VCCIO4 | power |  | 3.3V | -- |  | -- | --
R9 | 114 | 4 | RESERVED_INPUT |  |  |  | Column I/O |  | no | Off
R10 |  | 4 | VCCIO4 | power |  | 3.3V | -- |  | -- | --
R11 | 126 | 4 | RESERVED_INPUT |  |  |  | Column I/O |  | no | Off
R12 |  | 4 | VCCIO4 | power |  | 3.3V | -- |  | -- | --
R13 | 134 | 4 | RESERVED_INPUT |  |  |  | Column I/O |  | no | Off
R14 | 139 | 4 | RESERVED_INPUT |  |  |  | Column I/O |  | no | Off
R15 | 172 | 3 | RESERVED_INPUT |  |  |  | Row I/O |  | no | Off
R16 | 167 | 3 | RESERVED_INPUT |  |  |  | Row I/O |  | no | Off
R17 | 170 | 3 | RESERVED_INPUT |  |  |  | Row I/O |  | no | Off
R18 | 171 | 3 | RESERVED_INPUT |  |  |  | Row I/O |  | no | Off
R19 | 168 | 3 | RESERVED_INPUT |  |  |  | Row I/O |  | no | Off
R20 | 169 | 3 | RESERVED_INPUT |  |  |  | Row I/O |  | no | Off
T1 |  | 1 | VCCIO1 | power |  | 3.3V | -- |  | -- | --
T2 | 79 | 1 | zs_dq_to_and_from_the_sdram[24] | bidir | LVTTL |  | Row I/O | Y | no | Off
T3 | 80 | 1 | zs_dq_to_and_from_the_sdram[25] | bidir | LVTTL |  | Row I/O | Y | no | Off
T4 | 78 | 1 | zs_dq_to_and_from_the_sdram[23] | bidir | LVTTL |  | Row I/O | Y | no | Off
T5 | 91 | 4 | out_port_from_the_seven_seg_pio[14] | output | LVTTL |  | Column I/O | Y | no | Off
T6 | 95 | 4 | out_port_from_the_seven_seg_pio[10] | output | LVTTL |  | Column I/O | Y | no | Off
T7 | 96 | 4 | out_port_from_the_seven_seg_pio[9] | output | LVTTL |  | Column I/O | Y | no | Off
T8 | 104 | 4 | out_port_from_the_seven_seg_pio[1] | output | LVTTL |  | Column I/O | Y | no | Off
T9 | 113 | 4 | RESERVED_INPUT |  |  |  | Column I/O |  | no | Off
T10 | 117 | 4 | RESERVED_INPUT |  |  |  | Column I/O |  | no | Off
T11 | 129 | 4 | RESERVED_INPUT |  |  |  | Column I/O |  | no | Off
T12 | 130 | 4 | RESERVED_INPUT |  |  |  | Column I/O |  | no | Off
T13 | 133 | 4 | RESERVED_INPUT |  |  |  | Column I/O |  | no | Off
T14 | 140 | 4 | RESERVED_INPUT |  |  |  | Column I/O |  | no | Off
T15 | 149 | 4 | RESERVED_INPUT |  |  |  | Column I/O |  | no | Off
T16 | 150 | 4 | be_n_to_the_ext_ram[3] | output | LVTTL |  | Column I/O | Y | no | Off
T17 | 166 | 3 | RESERVED_INPUT |  |  |  | Row I/O |  | no | Off
T18 | 164 | 3 | RESERVED_INPUT |  |  |  | Row I/O |  | no | Off
T19 | 165 | 3 | RESERVED_INPUT |  |  |  | Row I/O |  | no | Off
T20 |  | 3 | VCCIO3 | power |  | 3.3V | -- |  | -- | --
U1 | 81 | 1 | zs_dq_to_and_from_the_sdram[26] | bidir | LVTTL |  | Row I/O | Y | no | Off
U2 | 83 | 1 | zs_dq_to_and_from_the_sdram[28] | bidir | LVTTL |  | Row I/O | Y | no | Off
U3 | 84 | 1 | zs_dq_to_and_from_the_sdram[29] | bidir | LVTTL |  | Row I/O | Y | no | Off
U4 | 82 | 1 | zs_dq_to_and_from_the_sdram[27] | bidir | LVTTL |  | Row I/O | Y | no | Off
U5 | 92 | 4 | out_port_from_the_seven_seg_pio[13] | output | LVTTL |  | Column I/O | Y | no | Off
U6 | 99 | 4 | out_port_from_the_seven_seg_pio[6] | output | LVTTL |  | Column I/O | Y | no | Off
U7 | 106 | 4 | out_port_from_the_seven_seg_pio[7] | output | LVTTL |  | Column I/O | Y | no | Off
U8 | 108 | 4 | RESERVED_INPUT |  |  |  | Column I/O |  | no | Off
U9 | 111 | 4 | RESERVED_INPUT |  |  |  | Column I/O |  | no | Off
U10 | 118 | 4 | RESERVED_INPUT |  |  |  | Column I/O |  | no | Off
U11 | 123 | 4 | RESERVED_INPUT |  |  |  | Column I/O |  | no | Off
U12 | 131 | 4 | RESERVED_INPUT |  |  |  | Column I/O |  | no | Off
U13 | 137 | 4 | RESERVED_INPUT |  |  |  | Column I/O |  | no | Off
U14 | 143 | 4 | RESERVED_INPUT |  |  |  | Column I/O |  | no | Off
U15 | 146 | 4 | RESERVED_INPUT |  |  |  | Column I/O |  | no | Off
U16 | 154 | 4 | write_n_to_the_ext_ram | output | LVTTL |  | Column I/O | Y | no | Off
U17 | 163 | 3 | RESERVED_INPUT |  |  |  | Row I/O |  | no | Off
U18 | 161 | 3 | RESERVED_INPUT |  |  |  | Row I/O |  | no | Off
U19 | 162 | 3 | RESERVED_INPUT |  |  |  | Row I/O |  | no | Off
U20 | 160 | 3 | RESERVED_INPUT |  |  |  | Row I/O |  | no | Off
V1 |  |  | GND | gnd |  |  | -- |  | -- | --
V2 | 85 | 1 | zs_dq_to_and_from_the_sdram[31] | bidir | LVTTL |  | Row I/O | Y | no | Off
V3 | 86 | 1 | zs_dq_to_and_from_the_sdram[30] | bidir | LVTTL |  | Row I/O | Y | no | Off
V4 | 89 | 4 | in_port_to_the_button_pio[2] | input | LVTTL |  | Column I/O | Y | no | Off
V5 | 93 | 4 | out_port_from_the_seven_seg_pio[12] | output | LVTTL |  | Column I/O | Y | no | Off
V6 | 100 | 4 | out_port_from_the_seven_seg_pio[5] | output | LVTTL |  | Column I/O | Y | no | Off
V7 | 105 | 4 | out_port_from_the_seven_seg_pio[0] | output | LVTTL |  | Column I/O | Y | no | Off
V8 | 107 | 4 | bidir_port_to_and_from_the_reconfig_request_pio | bidir | LVTTL |  | Column I/O | Y | no | Off
V9 | 112 | 4 | RESERVED_INPUT |  |  |  | Column I/O |  | no | Off
V10 | 119 | 4 | RESERVED_INPUT |  |  |  | Column I/O |  | no | Off
V11 | 122 | 4 | RESERVED_INPUT |  |  |  | Column I/O |  | no | Off
V12 | 132 | 4 | RESERVED_INPUT |  |  |  | Column I/O |  | no | Off
V13 | 138 | 4 | RESERVED_INPUT |  |  |  | Column I/O |  | no | Off
V14 | 144 | 4 | RESERVED_INPUT |  |  |  | Column I/O |  | no | Off
V15 | 145 | 4 | RESERVED_INPUT |  |  |  | Column I/O |  | no | Off
V16 | 152 | 4 | be_n_to_the_ext_ram[1] | output | LVTTL |  | Column I/O | Y | no | Off
V17 | 153 | 4 | be_n_to_the_ext_ram[0] | output | LVTTL |  | Column I/O | Y | no | Off
V18 | 158 | 3 | LCD_data_to_and_from_the_lcd_display[6] | bidir | LVTTL |  | Row I/O | Y | no | Off
V19 | 159 | 3 | LCD_data_to_and_from_the_lcd_display[7] | bidir | LVTTL |  | Row I/O | Y | no | Off
V20 |  |  | GND | gnd |  |  | -- |  | -- | --
W1 |  |  | VCCINT | power |  | 1.5V | -- |  | -- | --
W2 |  |  | GND | gnd |  |  | -- |  | -- | --
W3 | 87 | 4 | in_port_to_the_button_pio[0] | input | LVTTL |  | Column I/O | Y | no | Off
W4 | 90 | 4 | in_port_to_the_button_pio[3] | input | LVTTL |  | Column I/O | Y | no | Off
W5 | 94 | 4 | out_port_from_the_seven_seg_pio[11] | output | LVTTL |  | Column I/O | Y | no | Off
W6 | 97 | 4 | out_port_from_the_seven_seg_pio[8] | output | LVTTL |  | Column I/O | Y | no | Off
W7 | 101 | 4 | out_port_from_the_seven_seg_pio[4] | output | LVTTL |  | Column I/O | Y | no | Off
W8 | 109 | 4 | RESERVED_INPUT |  |  |  | Column I/O |  | no | Off
W9 | 116 | 4 | RESERVED_INPUT |  |  |  | Column I/O |  | no | Off
W10 | 120 | 4 | RESERVED_INPUT |  |  |  | Column I/O |  | no | Off
W11 | 124 | 4 | RESERVED_INPUT |  |  |  | Column I/O |  | no | Off
W12 | 128 | 4 | RESERVED_INPUT |  |  |  | Column I/O |  | no | Off
W13 | 136 | 4 | RESERVED_INPUT |  |  |  | Column I/O |  | no | Off
W14 | 141 | 4 | RESERVED_INPUT |  |  |  | Column I/O |  | no | Off
W15 | 148 | 4 | RESERVED_INPUT |  |  |  | Column I/O |  | no | Off
W16 | 151 | 4 | be_n_to_the_ext_ram[2] | output | LVTTL |  | Column I/O | Y | no | Off
W17 | 156 | 4 | select_n_to_the_ext_ram | output | LVTTL |  | Column I/O | Y | no | Off
W18 | 157 | 3 | LCD_data_to_and_from_the_lcd_display[5] | bidir | LVTTL |  | Row I/O | Y | no | Off
W19 |  |  | GND | gnd |  |  | -- |  | -- | --
W20 |  |  | VCCINT | power |  | 1.5V | -- |  | -- | --
Y1 |  |  | GND | gnd |  |  | -- |  | -- | --
Y2 |  |  | VCCINT | power |  | 1.5V | -- |  | -- | --
Y3 |  |  | GND | gnd |  |  | -- |  | -- | --
Y4 | 88 | 4 | in_port_to_the_button_pio[1] | input | LVTTL |  | Column I/O | Y | no | Off
Y5 |  | 4 | VCCIO4 | power |  | 3.3V | -- |  | -- | --
Y6 | 98 | 4 | out_port_from_the_seven_seg_pio[15] | output | LVTTL |  | Column I/O | Y | no | Off
Y7 | 102 | 4 | out_port_from_the_seven_seg_pio[3] | output | LVTTL |  | Column I/O | Y | no | Off
Y8 | 110 | 4 | RESERVED_INPUT |  |  |  | Column I/O |  | no | Off
Y9 | 115 | 4 | RESERVED_INPUT |  |  |  | Column I/O |  | no | Off
Y10 | 121 | 4 | RESERVED_INPUT |  |  |  | Column I/O |  | no | Off
Y11 | 125 | 4 | RESERVED_INPUT |  |  |  | Column I/O |  | no | Off
Y12 | 127 | 4 | RESERVED_INPUT |  |  |  | Column I/O |  | no | Off
Y13 | 135 | 4 | RESERVED_INPUT |  |  |  | Column I/O |  | no | Off
Y14 | 142 | 4 | RESERVED_INPUT |  |  |  | Column I/O |  | no | Off
Y15 | 147 | 4 | RESERVED_INPUT |  |  |  | Column I/O |  | no | Off
Y16 |  | 4 | VCCIO4 | power |  | 3.3V | -- |  | -- | --
Y17 | 155 | 4 | read_n_to_the_ext_ram | output | LVTTL |  | Column I/O | Y | no | Off
Y18 |  |  | GND | gnd |  |  | -- |  | -- | --
Y19 |  |  | VCCINT | power |  | 1.5V | -- |  | -- | --
Y20 |  |  | GND | gnd |  |  | -- |  | -- | --

## PLL Summary

Top

Name | std_1c20:inst|sdram_pll:the_sdram_pll|altpllsdram_pll:the_pll|altpll:altpll_component|pll | std_1c20:inst|connector_pll:the_connector_pll|altpllconnector_pll:the_pll|altpll:altpll_component|pll
--- | --- | ---
PLL type | - | -
Scan chain | None | None
PLL mode | Normal | Zero Delay Buffer
Feedback source | -- | --
Compensate clock | clock0 | extclock0
Switchover on loss of clock | -- | --
Switchover counter | -- | --
Primary clock | -- | --
Input frequency 0 | 50.0 MHz | 50.0 MHz
Input frequency 1 | -- | --
Nominal PFD frequency | 50.0 MHz | 50.0 MHz
Nominal VCO frequency | 1000.0 MHz | 800.0 MHz
Freq min lock | 24.55 MHz | 30.68 MHz
Freq max lock | 50.0 MHz | 62.5 MHz
Clock Offset | 0 ps | 0 ps
M VCO Tap | 0 | 0
M Initial | 5 | 1
M value | 20 | 16
N value | 1 | 1
M counter delay | -- | --
N counter delay | -- | --
M2 value | -- | --
N2 value | -- | --
SS counter | -- | --
Downspread | -- | --
Spread frequency | -- | --
enable0 counter | -- | --
enable1 counter | -- | --
Real time reconfigurable | -- | --
Scan chain MIF file | -- | --
Preserve counter order | Off | Off
PLL location | PLL_2 | PLL_1
Inclk0 signal | PLD_CLKFB | PLD_CLOCKINPUT[1]
Inclk1 signal | -- | --
Inclk0 signal type | Dedicated Pin | Dedicated Pin
Inclk1 signal type | -- | --

## PLL Usage

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Name | Output Clock | Mult | Div | Output Frequency | Phase Shift | Delay | Duty Cycle | Counter | Counter Delay | Counter Value | High / Low | Initial | VCO Tap
--- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | ---
std_1c20:inst|sdram_pll:the_sdram_pll|altpllsdram_pll:the_pll|altpll:altpll_component|_clk0 | clock0 | 1 | 1 | 50.0 MHz | 0 (0 ps) | 0 ps | 50/50 | G1 | -- | 20 | 10/10 Even | 5 | 0
std_1c20:inst|sdram_pll:the_sdram_pll|altpllsdram_pll:the_pll|altpll:altpll_component|_extclk0 | extclock0 | 1 | 1 | 50.0 MHz | -63 (-3499 ps) | 0 ps | 50/50 | E0 | -- | 20 | 10/10 Even | 1 | 4
std_1c20:inst|connector_pll:the_connector_pll|altpllconnector_pll:the_pll|altpll:altpll_component|_extclk0 | extclock0 | 1 | 1 | 50.0 MHz | 0 (0 ps) | 0 ps | 50/50 | E0 | -- | 16 | 8/8 Even | 1 | 0

## Output Pin Default Load For Reported TCO

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I/O Standard | Load | Termination Resistance
--- | --- | ---
LVTTL | 10 pF | Not Available
LVCMOS | 10 pF | Not Available
2.5 V | 10 pF | Not Available
1.8 V | 10 pF | Not Available
1.5 V | 10 pF | Not Available
SSTL-3 Class I | 30 pF | 50 Ohm (Parallel), 25 Ohm (Serial)
SSTL-3 Class II | 30 pF | 25 Ohm (Parallel), 25 Ohm (Serial)
SSTL-2 Class I | 30 pF | 50 Ohm (Parallel), 25 Ohm (Serial)
SSTL-2 Class II | 30 pF | 25 Ohm (Parallel), 25 Ohm (Serial)
Differential SSTL-2 | 10 pF | (See SSTL-2)
3.3-V PCI | 10 pF | 25 Ohm (Parallel)
LVDS | 4 pF | 100 Ohm (Differential)
RSDS | 10 pF | 100 Ohm (Differential)

Note: User assignments will override these defaults. The user specified values are listed in the Output Pins and Bidir Pins tables.

## Fitter Resource Utilization by Entity

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Compilation Hierarchy Node | Logic Cells | LC Registers | Memory Bits | M4Ks | Pins | Virtual Pins | LUT-Only LCs | Register-Only LCs | LUT/Register LCs | Carry Chain LCs | Packed LCs | Full Hierarchy Name
--- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | ---
|standard | 4930 (1) | 2592 | 50944 | 16 | 180 | 0 | 2338 (1) | 404 (0) | 2188 (0) | 320 (0) | 305 (0) | |standard
|sld_hub:sld_hub_inst| | 109 (28) | 73 | 0 | 0 | 0 | 0 | 36 (16) | 10 (0) | 63 (12) | 5 (0) | 5 (5) | |standard|sld_hub:sld_hub_inst
|lpm_decode:instruction_decoder| | 5 (0) | 5 | 0 | 0 | 0 | 0 | 0 (0) | 0 (0) | 5 (0) | 0 (0) | 0 (0) | |standard|sld_hub:sld_hub_inst|lpm_decode:instruction_decoder
|decode_ogi:auto_generated| | 5 (5) | 5 | 0 | 0 | 0 | 0 | 0 (0) | 0 (0) | 5 (5) | 0 (0) | 0 (0) | |standard|sld_hub:sld_hub_inst|lpm_decode:instruction_decoder|decode_ogi:auto_generated
|lpm_shiftreg:jtag_ir_register| | 10 (10) | 10 | 0 | 0 | 0 | 0 | 0 (0) | 8 (8) | 2 (2) | 0 (0) | 0 (0) | |standard|sld_hub:sld_hub_inst|lpm_shiftreg:jtag_ir_register
|sld_dffex:BROADCAST| | 1 (1) | 1 | 0 | 0 | 0 | 0 | 0 (0) | 0 (0) | 1 (1) | 0 (0) | 0 (0) | |standard|sld_hub:sld_hub_inst|sld_dffex:BROADCAST
|sld_dffex:IRF_ENA_0| | 1 (1) | 1 | 0 | 0 | 0 | 0 | 0 (0) | 0 (0) | 1 (1) | 0 (0) | 0 (0) | |standard|sld_hub:sld_hub_inst|sld_dffex:IRF_ENA_0
|sld_dffex:IRF_ENA| | 2 (2) | 2 | 0 | 0 | 0 | 0 | 0 (0) | 0 (0) | 2 (2) | 0 (0) | 0 (0) | |standard|sld_hub:sld_hub_inst|sld_dffex:IRF_ENA
|sld_dffex:IRSR| | 9 (9) | 7 | 0 | 0 | 0 | 0 | 2 (2) | 0 (0) | 7 (7) | 0 (0) | 0 (0) | |standard|sld_hub:sld_hub_inst|sld_dffex:IRSR
|sld_dffex:RESET| | 1 (1) | 1 | 0 | 0 | 0 | 0 | 0 (0) | 0 (0) | 1 (1) | 0 (0) | 0 (0) | |standard|sld_hub:sld_hub_inst|sld_dffex:RESET
|sld_dffex:\GEN_IRF:1:IRF| | 2 (2) | 2 | 0 | 0 | 0 | 0 | 0 (0) | 0 (0) | 2 (2) | 0 (0) | 0 (0) | |standard|sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:1:IRF
|sld_dffex:\GEN_IRF:2:IRF| | 2 (2) | 1 | 0 | 0 | 0 | 0 | 1 (1) | 0 (0) | 1 (1) | 0 (0) | 0 (0) | |standard|sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:2:IRF
|sld_dffex:\GEN_SHADOW_IRF:1:S_IRF| | 2 (2) | 2 | 0 | 0 | 0 | 0 | 0 (0) | 2 (2) | 0 (0) | 0 (0) | 0 (0) | |standard|sld_hub:sld_hub_inst|sld_dffex:\GEN_SHADOW_IRF:1:S_IRF
|sld_dffex:\GEN_SHADOW_IRF:2:S_IRF| | 1 (1) | 1 | 0 | 0 | 0 | 0 | 0 (0) | 0 (0) | 1 (1) | 0 (0) | 0 (0) | |standard|sld_hub:sld_hub_inst|sld_dffex:\GEN_SHADOW_IRF:2:S_IRF
|sld_jtag_state_machine:jtag_state_machine| | 21 (21) | 19 | 0 | 0 | 0 | 0 | 2 (2) | 0 (0) | 19 (19) | 0 (0) | 0 (0) | |standard|sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine
|sld_rom_sr:HUB_INFO_REG| | 24 (24) | 9 | 0 | 0 | 0 | 0 | 15 (15) | 0 (0) | 9 (9) | 5 (5) | 0 (0) | |standard|sld_hub:sld_hub_inst|sld_rom_sr:HUB_INFO_REG
|std_1c20:inst| | 4820 (1) | 2519 | 50944 | 16 | 0 | 0 | 2301 (1) | 394 (0) | 2125 (0) | 315 (0) | 300 (0) | |standard|std_1c20:inst
|button_pio:the_button_pio| | 23 (23) | 20 | 0 | 0 | 0 | 0 | 3 (3) | 4 (4) | 16 (16) | 0 (0) | 8 (8) | |standard|std_1c20:inst|button_pio:the_button_pio
|button_pio_s1_arbitrator:the_button_pio_s1| | 2 (2) | 0 | 0 | 0 | 0 | 0 | 2 (2) | 0 (0) | 0 (0) | 0 (0) | 0 (0) | |standard|std_1c20:inst|button_pio_s1_arbitrator:the_button_pio_s1
|clock_0:the_clock_0| | 101 (71) | 92 | 0 | 0 | 0 | 0 | 9 (1) | 57 (52) | 35 (18) | 0 (0) | 6 (0) | |standard|std_1c20:inst|clock_0:the_clock_0
|clock_0_edge_to_pulse:read_done_edge_to_pulse| | 1 (1) | 1 | 0 | 0 | 0 | 0 | 0 (0) | 0 (0) | 1 (1) | 0 (0) | 0 (0) | |standard|std_1c20:inst|clock_0:the_clock_0|clock_0_edge_to_pulse:read_done_edge_to_pulse
|clock_0_edge_to_pulse:read_request_edge_to_pulse| | 1 (1) | 1 | 0 | 0 | 0 | 0 | 0 (0) | 0 (0) | 1 (1) | 0 (0) | 0 (0) | |standard|std_1c20:inst|clock_0:the_clock_0|clock_0_edge_to_pulse:read_request_edge_to_pulse
|clock_0_edge_to_pulse:write_done_edge_to_pulse| | 1 (1) | 1 | 0 | 0 | 0 | 0 | 0 (0) | 0 (0) | 1 (1) | 0 (0) | 0 (0) | |standard|std_1c20:inst|clock_0:the_clock_0|clock_0_edge_to_pulse:write_done_edge_to_pulse
|clock_0_edge_to_pulse:write_request_edge_to_pulse| | 1 (1) | 1 | 0 | 0 | 0 | 0 | 0 (0) | 0 (0) | 1 (1) | 0 (0) | 0 (0) | |standard|std_1c20:inst|clock_0:the_clock_0|clock_0_edge_to_pulse:write_request_edge_to_pulse
|clock_0_master_FSM:master_FSM| | 8 (8) | 5 | 0 | 0 | 0 | 0 | 3 (3) | 0 (0) | 5 (5) | 0 (0) | 3 (3) | |standard|std_1c20:inst|clock_0:the_clock_0|clock_0_master_FSM:master_FSM
|clock_0_master_read_done_sync_module:clock_0_master_read_done_sync| | 2 (2) | 2 | 0 | 0 | 0 | 0 | 0 (0) | 1 (1) | 1 (1) | 0 (0) | 0 (0) | |standard|std_1c20:inst|clock_0:the_clock_0|clock_0_master_read_done_sync_module:clock_0_master_read_done_sync
|clock_0_master_write_done_sync_module:clock_0_master_write_done_sync| | 2 (2) | 2 | 0 | 0 | 0 | 0 | 0 (0) | 1 (1) | 1 (1) | 0 (0) | 0 (0) | |standard|std_1c20:inst|clock_0:the_clock_0|clock_0_master_write_done_sync_module:clock_0_master_write_done_sync
|clock_0_slave_FSM:slave_FSM| | 10 (10) | 5 | 0 | 0 | 0 | 0 | 5 (5) | 0 (0) | 5 (5) | 0 (0) | 3 (3) | |standard|std_1c20:inst|clock_0:the_clock_0|clock_0_slave_FSM:slave_FSM
|clock_0_slave_read_request_sync_module:clock_0_slave_read_request_sync| | 2 (2) | 2 | 0 | 0 | 0 | 0 | 0 (0) | 1 (1) | 1 (1) | 0 (0) | 0 (0) | |standard|std_1c20:inst|clock_0:the_clock_0|clock_0_slave_read_request_sync_module:clock_0_slave_read_request_sync
|clock_0_slave_write_request_sync_module:clock_0_slave_write_request_sync| | 2 (2) | 2 | 0 | 0 | 0 | 0 | 0 (0) | 2 (2) | 0 (0) | 0 (0) | 0 (0) | |standard|std_1c20:inst|clock_0:the_clock_0|clock_0_slave_write_request_sync_module:clock_0_slave_write_request_sync
|clock_0_in_arbitrator:the_clock_0_in| | 12 (12) | 0 | 0 | 0 | 0 | 0 | 12 (12) | 0 (0) | 0 (0) | 0 (0) | 0 (0) | |standard|std_1c20:inst|clock_0_in_arbitrator:the_clock_0_in
|clock_1:the_clock_1| | 101 (71) | 92 | 0 | 0 | 0 | 0 | 9 (1) | 43 (38) | 49 (32) | 0 (0) | 6 (0) | |standard|std_1c20:inst|clock_1:the_clock_1
|clock_1_edge_to_pulse:read_done_edge_to_pulse| | 1 (1) | 1 | 0 | 0 | 0 | 0 | 0 (0) | 0 (0) | 1 (1) | 0 (0) | 0 (0) | |standard|std_1c20:inst|clock_1:the_clock_1|clock_1_edge_to_pulse:read_done_edge_to_pulse
|clock_1_edge_to_pulse:read_request_edge_to_pulse| | 1 (1) | 1 | 0 | 0 | 0 | 0 | 0 (0) | 0 (0) | 1 (1) | 0 (0) | 0 (0) | |standard|std_1c20:inst|clock_1:the_clock_1|clock_1_edge_to_pulse:read_request_edge_to_pulse
|clock_1_edge_to_pulse:write_done_edge_to_pulse| | 1 (1) | 1 | 0 | 0 | 0 | 0 | 0 (0) | 0 (0) | 1 (1) | 0 (0) | 0 (0) | |standard|std_1c20:inst|clock_1:the_clock_1|clock_1_edge_to_pulse:write_done_edge_to_pulse
|clock_1_edge_to_pulse:write_request_edge_to_pulse| | 1 (1) | 1 | 0 | 0 | 0 | 0 | 0 (0) | 0 (0) | 1 (1) | 0 (0) | 0 (0) | |standard|std_1c20:inst|clock_1:the_clock_1|clock_1_edge_to_pulse:write_request_edge_to_pulse
|clock_1_master_FSM:master_FSM| | 8 (8) | 5 | 0 | 0 | 0 | 0 | 3 (3) | 0 (0) | 5 (5) | 0 (0) | 3 (3) | |standard|std_1c20:inst|clock_1:the_clock_1|clock_1_master_FSM:master_FSM
|clock_1_master_read_done_sync_module:clock_1_master_read_done_sync| | 2 (2) | 2 | 0 | 0 | 0 | 0 | 0 (0) | 1 (1) | 1 (1) | 0 (0) | 0 (0) | |standard|std_1c20:inst|clock_1:the_clock_1|clock_1_master_read_done_sync_module:clock_1_master_read_done_sync
|clock_1_master_write_done_sync_module:clock_1_master_write_done_sync| | 2 (2) | 2 | 0 | 0 | 0 | 0 | 0 (0) | 1 (1) | 1 (1) | 0 (0) | 0 (0) | |standard|std_1c20:inst|clock_1:the_clock_1|clock_1_master_write_done_sync_module:clock_1_master_write_done_sync
|clock_1_slave_FSM:slave_FSM| | 10 (10) | 5 | 0 | 0 | 0 | 0 | 5 (5) | 0 (0) | 5 (5) | 0 (0) | 3 (3) | |standard|std_1c20:inst|clock_1:the_clock_1|clock_1_slave_FSM:slave_FSM
|clock_1_slave_read_request_sync_module:clock_1_slave_read_request_sync| | 2 (2) | 2 | 0 | 0 | 0 | 0 | 0 (0) | 1 (1) | 1 (1) | 0 (0) | 0 (0) | |standard|std_1c20:inst|clock_1:the_clock_1|clock_1_slave_read_request_sync_module:clock_1_slave_read_request_sync
|clock_1_slave_write_request_sync_module:clock_1_slave_write_request_sync| | 2 (2) | 2 | 0 | 0 | 0 | 0 | 0 (0) | 2 (2) | 0 (0) | 0 (0) | 0 (0) | |standard|std_1c20:inst|clock_1:the_clock_1|clock_1_slave_write_request_sync_module:clock_1_slave_write_request_sync
|clock_1_in_arbitrator:the_clock_1_in| | 2 (2) | 0 | 0 | 0 | 0 | 0 | 2 (2) | 0 (0) | 0 (0) | 0 (0) | 0 (0) | |standard|std_1c20:inst|clock_1_in_arbitrator:the_clock_1_in
|connector_pll:the_connector_pll| | 25 (25) | 24 | 0 | 0 | 0 | 0 | 1 (1) | 15 (15) | 9 (9) | 5 (5) | 1 (1) | |standard|std_1c20:inst|connector_pll:the_connector_pll
|altpllconnector_pll:the_pll| | 0 (0) | 0 | 0 | 0 | 0 | 0 | 0 (0) | 0 (0) | 0 (0) | 0 (0) | 0 (0) | |standard|std_1c20:inst|connector_pll:the_connector_pll|altpllconnector_pll:the_pll
|altpll:altpll_component| | 0 (0) | 0 | 0 | 0 | 0 | 0 | 0 (0) | 0 (0) | 0 (0) | 0 (0) | 0 (0) | |standard|std_1c20:inst|connector_pll:the_connector_pll|altpllconnector_pll:the_pll|altpll:altpll_component
|connector_pll_s1_arbitrator:the_connector_pll_s1| | 1 (1) | 1 | 0 | 0 | 0 | 0 | 0 (0) | 0 (0) | 1 (1) | 0 (0) | 0 (0) | |standard|std_1c20:inst|connector_pll_s1_arbitrator:the_connector_pll_s1
|cpu:the_cpu| | 1895 (1477) | 974 | 45824 | 13 | 0 | 0 | 921 (713) | 116 (77) | 858 (687) | 130 (55) | 66 (59) | |standard|std_1c20:inst|cpu:the_cpu
|cpu_ic_data_module:cpu_ic_data| | 0 (0) | 0 | 32768 | 8 | 0 | 0 | 0 (0) | 0 (0) | 0 (0) | 0 (0) | 0 (0) | |standard|std_1c20:inst|cpu:the_cpu|cpu_ic_data_module:cpu_ic_data
|altsyncram:the_altsyncram| | 0 (0) | 0 | 32768 | 8 | 0 | 0 | 0 (0) | 0 (0) | 0 (0) | 0 (0) | 0 (0) | |standard|std_1c20:inst|cpu:the_cpu|cpu_ic_data_module:cpu_ic_data|altsyncram:the_altsyncram
|altsyncram_qmb1:auto_generated| | 0 (0) | 0 | 32768 | 8 | 0 | 0 | 0 (0) | 0 (0) | 0 (0) | 0 (0) | 0 (0) | |standard|std_1c20:inst|cpu:the_cpu|cpu_ic_data_module:cpu_ic_data|altsyncram:the_altsyncram|altsyncram_qmb1:auto_generated
|cpu_ic_tag_module:cpu_ic_tag| | 0 (0) | 0 | 2816 | 1 | 0 | 0 | 0 (0) | 0 (0) | 0 (0) | 0 (0) | 0 (0) | |standard|std_1c20:inst|cpu:the_cpu|cpu_ic_tag_module:cpu_ic_tag
|altsyncram:the_altsyncram| | 0 (0) | 0 | 2816 | 1 | 0 | 0 | 0 (0) | 0 (0) | 0 (0) | 0 (0) | 0 (0) | |standard|std_1c20:inst|cpu:the_cpu|cpu_ic_tag_module:cpu_ic_tag|altsyncram:the_altsyncram
|altsyncram_09e1:auto_generated| | 0 (0) | 0 | 2816 | 1 | 0 | 0 | 0 (0) | 0 (0) | 0 (0) | 0 (0) | 0 (0) | |standard|std_1c20:inst|cpu:the_cpu|cpu_ic_tag_module:cpu_ic_tag|altsyncram:the_altsyncram|altsyncram_09e1:auto_generated
|cpu_nios2_oci:the_cpu_nios2_oci| | 352 (33) | 210 | 8192 | 2 | 0 | 0 | 142 (6) | 39 (0) | 171 (27) | 9 (0) | 7 (0) | |standard|std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci
|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper| | 184 (0) | 91 | 0 | 0 | 0 | 0 | 93 (0) | 39 (0) | 52 (0) | 0 (0) | 4 (0) | |standard|std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper
|cpu_jtag_debug_module:the_cpu_jtag_debug_module1| | 184 (184) | 91 | 0 | 0 | 0 | 0 | 93 (93) | 39 (39) | 52 (52) | 0 (0) | 4 (4) | |standard|std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1
|cpu_nios2_avalon_reg:the_cpu_nios2_avalon_reg| | 18 (18) | 9 | 0 | 0 | 0 | 0 | 9 (9) | 0 (0) | 9 (9) | 0 (0) | 0 (0) | |standard|std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_avalon_reg:the_cpu_nios2_avalon_reg
|cpu_nios2_oci_break:the_cpu_nios2_oci_break| | 32 (32) | 32 | 0 | 0 | 0 | 0 | 0 (0) | 0 (0) | 32 (32) | 0 (0) | 0 (0) | |standard|std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_break:the_cpu_nios2_oci_break
|cpu_nios2_oci_debug:the_cpu_nios2_oci_debug| | 12 (12) | 7 | 0 | 0 | 0 | 0 | 5 (5) | 0 (0) | 7 (7) | 0 (0) | 1 (1) | |standard|std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_debug:the_cpu_nios2_oci_debug
|cpu_nios2_ocimem:the_cpu_nios2_ocimem| | 73 (73) | 44 | 8192 | 2 | 0 | 0 | 29 (29) | 0 (0) | 44 (44) | 9 (9) | 2 (2) | |standard|std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem
|cpu_ociram_lpm_dram_bdp_component_module:cpu_ociram_lpm_dram_bdp_component| | 0 (0) | 0 | 8192 | 2 | 0 | 0 | 0 (0) | 0 (0) | 0 (0) | 0 (0) | 0 (0) | |standard|std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|cpu_ociram_lpm_dram_bdp_component_module:cpu_ociram_lpm_dram_bdp_component
|altsyncram:the_altsyncram| | 0 (0) | 0 | 8192 | 2 | 0 | 0 | 0 (0) | 0 (0) | 0 (0) | 0 (0) | 0 (0) | |standard|std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|cpu_ociram_lpm_dram_bdp_component_module:cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram
|altsyncram_bp62:auto_generated| | 0 (0) | 0 | 8192 | 2 | 0 | 0 | 0 (0) | 0 (0) | 0 (0) | 0 (0) | 0 (0) | |standard|std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|cpu_ociram_lpm_dram_bdp_component_module:cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_bp62:auto_generated
|cpu_register_bank_a_module:cpu_register_bank_a| | 0 (0) | 0 | 1024 | 1 | 0 | 0 | 0 (0) | 0 (0) | 0 (0) | 0 (0) | 0 (0) | |standard|std_1c20:inst|cpu:the_cpu|cpu_register_bank_a_module:cpu_register_bank_a
|altsyncram:the_altsyncram| | 0 (0) | 0 | 1024 | 1 | 0 | 0 | 0 (0) | 0 (0) | 0 (0) | 0 (0) | 0 (0) | |standard|std_1c20:inst|cpu:the_cpu|cpu_register_bank_a_module:cpu_register_bank_a|altsyncram:the_altsyncram
|altsyncram_3vd1:auto_generated| | 0 (0) | 0 | 1024 | 1 | 0 | 0 | 0 (0) | 0 (0) | 0 (0) | 0 (0) | 0 (0) | |standard|std_1c20:inst|cpu:the_cpu|cpu_register_bank_a_module:cpu_register_bank_a|altsyncram:the_altsyncram|altsyncram_3vd1:auto_generated
|cpu_register_bank_b_module:cpu_register_bank_b| | 0 (0) | 0 | 1024 | 1 | 0 | 0 | 0 (0) | 0 (0) | 0 (0) | 0 (0) | 0 (0) | |standard|std_1c20:inst|cpu:the_cpu|cpu_register_bank_b_module:cpu_register_bank_b
|altsyncram:the_altsyncram| | 0 (0) | 0 | 1024 | 1 | 0 | 0 | 0 (0) | 0 (0) | 0 (0) | 0 (0) | 0 (0) | |standard|std_1c20:inst|cpu:the_cpu|cpu_register_bank_b_module:cpu_register_bank_b|altsyncram:the_altsyncram
|altsyncram_4vd1:auto_generated| | 0 (0) | 0 | 1024 | 1 | 0 | 0 | 0 (0) | 0 (0) | 0 (0) | 0 (0) | 0 (0) | |standard|std_1c20:inst|cpu:the_cpu|cpu_register_bank_b_module:cpu_register_bank_b|altsyncram:the_altsyncram|altsyncram_4vd1:auto_generated
|cpu_test_bench:the_cpu_test_bench| | 33 (33) | 0 | 0 | 0 | 0 | 0 | 33 (33) | 0 (0) | 0 (0) | 33 (33) | 0 (0) | |standard|std_1c20:inst|cpu:the_cpu|cpu_test_bench:the_cpu_test_bench
|lpm_add_sub:Add8| | 33 (0) | 0 | 0 | 0 | 0 | 0 | 33 (0) | 0 (0) | 0 (0) | 33 (0) | 0 (0) | |standard|std_1c20:inst|cpu:the_cpu|lpm_add_sub:Add8
|alt_stratix_add_sub:stratix_adder| | 33 (33) | 0 | 0 | 0 | 0 | 0 | 33 (33) | 0 (0) | 0 (0) | 33 (33) | 0 (0) | |standard|std_1c20:inst|cpu:the_cpu|lpm_add_sub:Add8|alt_stratix_add_sub:stratix_adder
|cpu_data_master_arbitrator:the_cpu_data_master| | 317 (317) | 96 | 0 | 0 | 0 | 0 | 221 (221) | 8 (8) | 88 (88) | 0 (0) | 19 (19) | |standard|std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master
|cpu_instruction_master_arbitrator:the_cpu_instruction_master| | 164 (164) | 51 | 0 | 0 | 0 | 0 | 113 (113) | 0 (0) | 51 (51) | 0 (0) | 19 (19) | |standard|std_1c20:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master
|cpu_jtag_debug_module_arbitrator:the_cpu_jtag_debug_module| | 32 (32) | 10 | 0 | 0 | 0 | 0 | 22 (22) | 0 (0) | 10 (10) | 0 (0) | 5 (5) | |standard|std_1c20:inst|cpu_jtag_debug_module_arbitrator:the_cpu_jtag_debug_module
|epcs_controller:the_epcs_controller| | 195 (15) | 130 | 4096 | 1 | 0 | 0 | 65 (15) | 10 (0) | 120 (0) | 5 (0) | 24 (1) | |standard|std_1c20:inst|epcs_controller:the_epcs_controller
|altsyncram:the_boot_copier_rom| | 0 (0) | 0 | 4096 | 1 | 0 | 0 | 0 (0) | 0 (0) | 0 (0) | 0 (0) | 0 (0) | |standard|std_1c20:inst|epcs_controller:the_epcs_controller|altsyncram:the_boot_copier_rom
|altsyncram_3h31:auto_generated| | 0 (0) | 0 | 4096 | 1 | 0 | 0 | 0 (0) | 0 (0) | 0 (0) | 0 (0) | 0 (0) | |standard|std_1c20:inst|epcs_controller:the_epcs_controller|altsyncram:the_boot_copier_rom|altsyncram_3h31:auto_generated
|epcs_controller_sub:the_epcs_controller_sub| | 180 (180) | 130 | 0 | 0 | 0 | 0 | 50 (50) | 10 (10) | 120 (120) | 5 (5) | 23 (23) | |standard|std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub
|tornado_epcs_controller_atom:the_tornado_epcs_controller_atom| | 0 (0) | 0 | 0 | 0 | 0 | 0 | 0 (0) | 0 (0) | 0 (0) | 0 (0) | 0 (0) | |standard|std_1c20:inst|epcs_controller:the_epcs_controller|tornado_epcs_controller_atom:the_tornado_epcs_controller_atom
|epcs_controller_epcs_control_port_arbitrator:the_epcs_controller_epcs_control_port| | 30 (30) | 10 | 0 | 0 | 0 | 0 | 20 (20) | 0 (0) | 10 (10) | 0 (0) | 0 (0) | |standard|std_1c20:inst|epcs_controller_epcs_control_port_arbitrator:the_epcs_controller_epcs_control_port
|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave| | 380 (380) | 177 | 0 | 0 | 0 | 0 | 203 (203) | 5 (5) | 172 (172) | 12 (12) | 1 (1) | |standard|std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave
|high_res_timer:the_high_res_timer| | 141 (141) | 120 | 0 | 0 | 0 | 0 | 21 (21) | 18 (18) | 102 (102) | 32 (32) | 32 (32) | |standard|std_1c20:inst|high_res_timer:the_high_res_timer
|high_res_timer_s1_arbitrator:the_high_res_timer_s1| | 1 (1) | 0 | 0 | 0 | 0 | 0 | 1 (1) | 0 (0) | 0 (0) | 0 (0) | 0 (0) | |standard|std_1c20:inst|high_res_timer_s1_arbitrator:the_high_res_timer_s1
|jtag_uart:the_jtag_uart| | 169 (50) | 106 | 1024 | 2 | 0 | 0 | 63 (37) | 15 (0) | 91 (13) | 51 (15) | 11 (1) | |standard|std_1c20:inst|jtag_uart:the_jtag_uart
|alt_jtag_atlantic:jtag_uart_alt_jtag_atlantic| | 68 (68) | 53 | 0 | 0 | 0 | 0 | 15 (15) | 15 (15) | 38 (38) | 0 (0) | 10 (10) | |standard|std_1c20:inst|jtag_uart:the_jtag_uart|alt_jtag_atlantic:jtag_uart_alt_jtag_atlantic
|jtag_uart_scfifo_r:the_jtag_uart_scfifo_r| | 26 (0) | 20 | 512 | 1 | 0 | 0 | 6 (0) | 0 (0) | 20 (0) | 18 (0) | 0 (0) | |standard|std_1c20:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_r:the_jtag_uart_scfifo_r
|scfifo:rfifo| | 26 (0) | 20 | 512 | 1 | 0 | 0 | 6 (0) | 0 (0) | 20 (0) | 18 (0) | 0 (0) | |standard|std_1c20:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_r:the_jtag_uart_scfifo_r|scfifo:rfifo
|scfifo_jf21:auto_generated| | 26 (0) | 20 | 512 | 1 | 0 | 0 | 6 (0) | 0 (0) | 20 (0) | 18 (0) | 0 (0) | |standard|std_1c20:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_r:the_jtag_uart_scfifo_r|scfifo:rfifo|scfifo_jf21:auto_generated
|a_dpfifo_ml21:dpfifo| | 26 (0) | 20 | 512 | 1 | 0 | 0 | 6 (0) | 0 (0) | 20 (0) | 18 (0) | 0 (0) | |standard|std_1c20:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_r:the_jtag_uart_scfifo_r|scfifo:rfifo|scfifo_jf21:auto_generated|a_dpfifo_ml21:dpfifo
|a_fefifo_7cf:fifo_state| | 14 (8) | 8 | 0 | 0 | 0 | 0 | 6 (6) | 0 (0) | 8 (2) | 6 (0) | 0 (0) | |standard|std_1c20:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_r:the_jtag_uart_scfifo_r|scfifo:rfifo|scfifo_jf21:auto_generated|a_dpfifo_ml21:dpfifo|a_fefifo_7cf:fifo_state
|cntr_9c7:count_usedw| | 6 (6) | 6 | 0 | 0 | 0 | 0 | 0 (0) | 0 (0) | 6 (6) | 6 (6) | 0 (0) | |standard|std_1c20:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_r:the_jtag_uart_scfifo_r|scfifo:rfifo|scfifo_jf21:auto_generated|a_dpfifo_ml21:dpfifo|a_fefifo_7cf:fifo_state|cntr_9c7:count_usedw
|cntr_rd8:rd_ptr_count| | 6 (6) | 6 | 0 | 0 | 0 | 0 | 0 (0) | 0 (0) | 6 (6) | 6 (6) | 0 (0) | |standard|std_1c20:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_r:the_jtag_uart_scfifo_r|scfifo:rfifo|scfifo_jf21:auto_generated|a_dpfifo_ml21:dpfifo|cntr_rd8:rd_ptr_count
|cntr_rd8:wr_ptr| | 6 (6) | 6 | 0 | 0 | 0 | 0 | 0 (0) | 0 (0) | 6 (6) | 6 (6) | 0 (0) | |standard|std_1c20:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_r:the_jtag_uart_scfifo_r|scfifo:rfifo|scfifo_jf21:auto_generated|a_dpfifo_ml21:dpfifo|cntr_rd8:wr_ptr
|dpram_j921:FIFOram| | 0 (0) | 0 | 512 | 1 | 0 | 0 | 0 (0) | 0 (0) | 0 (0) | 0 (0) | 0 (0) | |standard|std_1c20:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_r:the_jtag_uart_scfifo_r|scfifo:rfifo|scfifo_jf21:auto_generated|a_dpfifo_ml21:dpfifo|dpram_j921:FIFOram
|altsyncram_nll1:altsyncram1| | 0 (0) | 0 | 512 | 1 | 0 | 0 | 0 (0) | 0 (0) | 0 (0) | 0 (0) | 0 (0) | |standard|std_1c20:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_r:the_jtag_uart_scfifo_r|scfifo:rfifo|scfifo_jf21:auto_generated|a_dpfifo_ml21:dpfifo|dpram_j921:FIFOram|altsyncram_nll1:altsyncram1
|jtag_uart_scfifo_w:the_jtag_uart_scfifo_w| | 25 (0) | 20 | 512 | 1 | 0 | 0 | 5 (0) | 0 (0) | 20 (0) | 18 (0) | 0 (0) | |standard|std_1c20:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_w:the_jtag_uart_scfifo_w
|scfifo:wfifo| | 25 (0) | 20 | 512 | 1 | 0 | 0 | 5 (0) | 0 (0) | 20 (0) | 18 (0) | 0 (0) | |standard|std_1c20:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_w:the_jtag_uart_scfifo_w|scfifo:wfifo
|scfifo_jf21:auto_generated| | 25 (0) | 20 | 512 | 1 | 0 | 0 | 5 (0) | 0 (0) | 20 (0) | 18 (0) | 0 (0) | |standard|std_1c20:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_w:the_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_jf21:auto_generated
|a_dpfifo_ml21:dpfifo| | 25 (0) | 20 | 512 | 1 | 0 | 0 | 5 (0) | 0 (0) | 20 (0) | 18 (0) | 0 (0) | |standard|std_1c20:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_w:the_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_jf21:auto_generated|a_dpfifo_ml21:dpfifo
|a_fefifo_7cf:fifo_state| | 13 (7) | 8 | 0 | 0 | 0 | 0 | 5 (5) | 0 (0) | 8 (2) | 6 (0) | 0 (0) | |standard|std_1c20:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_w:the_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_jf21:auto_generated|a_dpfifo_ml21:dpfifo|a_fefifo_7cf:fifo_state
|cntr_9c7:count_usedw| | 6 (6) | 6 | 0 | 0 | 0 | 0 | 0 (0) | 0 (0) | 6 (6) | 6 (6) | 0 (0) | |standard|std_1c20:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_w:the_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_jf21:auto_generated|a_dpfifo_ml21:dpfifo|a_fefifo_7cf:fifo_state|cntr_9c7:count_usedw
|cntr_rd8:rd_ptr_count| | 6 (6) | 6 | 0 | 0 | 0 | 0 | 0 (0) | 0 (0) | 6 (6) | 6 (6) | 0 (0) | |standard|std_1c20:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_w:the_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_jf21:auto_generated|a_dpfifo_ml21:dpfifo|cntr_rd8:rd_ptr_count
|cntr_rd8:wr_ptr| | 6 (6) | 6 | 0 | 0 | 0 | 0 | 0 (0) | 0 (0) | 6 (6) | 6 (6) | 0 (0) | |standard|std_1c20:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_w:the_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_jf21:auto_generated|a_dpfifo_ml21:dpfifo|cntr_rd8:wr_ptr
|dpram_j921:FIFOram| | 0 (0) | 0 | 512 | 1 | 0 | 0 | 0 (0) | 0 (0) | 0 (0) | 0 (0) | 0 (0) | |standard|std_1c20:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_w:the_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_jf21:auto_generated|a_dpfifo_ml21:dpfifo|dpram_j921:FIFOram
|altsyncram_nll1:altsyncram1| | 0 (0) | 0 | 512 | 1 | 0 | 0 | 0 (0) | 0 (0) | 0 (0) | 0 (0) | 0 (0) | |standard|std_1c20:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_w:the_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_jf21:auto_generated|a_dpfifo_ml21:dpfifo|dpram_j921:FIFOram|altsyncram_nll1:altsyncram1
|jtag_uart_avalon_jtag_slave_arbitrator:the_jtag_uart_avalon_jtag_slave| | 2 (2) | 0 | 0 | 0 | 0 | 0 | 2 (2) | 0 (0) | 0 (0) | 0 (0) | 0 (0) | |standard|std_1c20:inst|jtag_uart_avalon_jtag_slave_arbitrator:the_jtag_uart_avalon_jtag_slave
|lcd_display:the_lcd_display| | 5 (5) | 0 | 0 | 0 | 0 | 0 | 5 (5) | 0 (0) | 0 (0) | 0 (0) | 0 (0) | |standard|std_1c20:inst|lcd_display:the_lcd_display
|lcd_display_control_slave_arbitrator:the_lcd_display_control_slave| | 25 (25) | 7 | 0 | 0 | 0 | 0 | 18 (18) | 0 (0) | 7 (7) | 6 (6) | 0 (0) | |standard|std_1c20:inst|lcd_display_control_slave_arbitrator:the_lcd_display_control_slave
|led_pio:the_led_pio| | 9 (9) | 8 | 0 | 0 | 0 | 0 | 1 (1) | 8 (8) | 0 (0) | 0 (0) | 0 (0) | |standard|std_1c20:inst|led_pio:the_led_pio
|reconfig_request_pio:the_reconfig_request_pio| | 4 (4) | 3 | 0 | 0 | 0 | 0 | 1 (1) | 0 (0) | 3 (3) | 0 (0) | 0 (0) | |standard|std_1c20:inst|reconfig_request_pio:the_reconfig_request_pio
|reconfig_request_pio_s1_arbitrator:the_reconfig_request_pio_s1| | 3 (3) | 0 | 0 | 0 | 0 | 0 | 3 (3) | 0 (0) | 0 (0) | 0 (0) | 0 (0) | |standard|std_1c20:inst|reconfig_request_pio_s1_arbitrator:the_reconfig_request_pio_s1
|sdram:the_sdram| | 708 (567) | 290 | 0 | 0 | 0 | 0 | 418 (399) | 36 (4) | 254 (164) | 13 (13) | 47 (3) | |standard|std_1c20:inst|sdram:the_sdram
|sdram_input_efifo_module:the_sdram_input_efifo_module| | 141 (141) | 122 | 0 | 0 | 0 | 0 | 19 (19) | 32 (32) | 90 (90) | 0 (0) | 44 (44) | |standard|std_1c20:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module
|sdram_pll:the_sdram_pll| | 25 (25) | 24 | 0 | 0 | 0 | 0 | 1 (1) | 15 (15) | 9 (9) | 5 (5) | 1 (1) | |standard|std_1c20:inst|sdram_pll:the_sdram_pll
|altpllsdram_pll:the_pll| | 0 (0) | 0 | 0 | 0 | 0 | 0 | 0 (0) | 0 (0) | 0 (0) | 0 (0) | 0 (0) | |standard|std_1c20:inst|sdram_pll:the_sdram_pll|altpllsdram_pll:the_pll
|altpll:altpll_component| | 0 (0) | 0 | 0 | 0 | 0 | 0 | 0 (0) | 0 (0) | 0 (0) | 0 (0) | 0 (0) | |standard|std_1c20:inst|sdram_pll:the_sdram_pll|altpllsdram_pll:the_pll|altpll:altpll_component
|sdram_pll_s1_arbitrator:the_sdram_pll_s1| | 1 (1) | 1 | 0 | 0 | 0 | 0 | 0 (0) | 0 (0) | 1 (1) | 0 (0) | 0 (0) | |standard|std_1c20:inst|sdram_pll_s1_arbitrator:the_sdram_pll_s1
|sdram_s1_arbitrator:the_sdram_s1| | 117 (48) | 47 | 0 | 0 | 0 | 0 | 70 (32) | 0 (0) | 47 (16) | 6 (6) | 3 (3) | |standard|std_1c20:inst|sdram_s1_arbitrator:the_sdram_s1
|rdv_fifo_for_cpu_data_master_to_sdram_s1_module:rdv_fifo_for_cpu_data_master_to_sdram_s1| | 27 (27) | 12 | 0 | 0 | 0 | 0 | 15 (15) | 0 (0) | 12 (12) | 0 (0) | 0 (0) | |standard|std_1c20:inst|sdram_s1_arbitrator:the_sdram_s1|rdv_fifo_for_cpu_data_master_to_sdram_s1_module:rdv_fifo_for_cpu_data_master_to_sdram_s1
|rdv_fifo_for_cpu_instruction_master_to_sdram_s1_module:rdv_fifo_for_cpu_instruction_master_to_sdram_s1| | 42 (42) | 19 | 0 | 0 | 0 | 0 | 23 (23) | 0 (0) | 19 (19) | 0 (0) | 0 (0) | |standard|std_1c20:inst|sdram_s1_arbitrator:the_sdram_s1|rdv_fifo_for_cpu_instruction_master_to_sdram_s1_module:rdv_fifo_for_cpu_instruction_master_to_sdram_s1
|seven_seg_pio:the_seven_seg_pio| | 20 (20) | 16 | 0 | 0 | 0 | 0 | 4 (4) | 16 (16) | 0 (0) | 0 (0) | 0 (0) | |standard|std_1c20:inst|seven_seg_pio:the_seven_seg_pio
|seven_seg_pio_s1_arbitrator:the_seven_seg_pio_s1| | 2 (2) | 1 | 0 | 0 | 0 | 0 | 1 (1) | 0 (0) | 1 (1) | 0 (0) | 0 (0) | |standard|std_1c20:inst|seven_seg_pio_s1_arbitrator:the_seven_seg_pio_s1
|std_1c20_reset_PLD_CLKFB_domain_synch_module:std_1c20_reset_PLD_CLKFB_domain_synch| | 2 (2) | 2 | 0 | 0 | 0 | 0 | 0 (0) | 1 (1) | 1 (1) | 0 (0) | 0 (0) | |standard|std_1c20:inst|std_1c20_reset_PLD_CLKFB_domain_synch_module:std_1c20_reset_PLD_CLKFB_domain_synch
|std_1c20_reset_PLD_CLOCKINPUT_domain_synch_module:std_1c20_reset_PLD_CLOCKINPUT_domain_synch| | 2 (2) | 2 | 0 | 0 | 0 | 0 | 0 (0) | 1 (1) | 1 (1) | 0 (0) | 0 (0) | |standard|std_1c20:inst|std_1c20_reset_PLD_CLOCKINPUT_domain_synch_module:std_1c20_reset_PLD_CLOCKINPUT_domain_synch
|std_1c20_reset_sysclk2_domain_synch_module:std_1c20_reset_sysclk2_domain_synch| | 2 (2) | 2 | 0 | 0 | 0 | 0 | 0 (0) | 0 (0) | 2 (2) | 0 (0) | 0 (0) | |standard|std_1c20:inst|std_1c20_reset_sysclk2_domain_synch_module:std_1c20_reset_sysclk2_domain_synch
|sys_clk_timer:the_sys_clk_timer| | 146 (146) | 120 | 0 | 0 | 0 | 0 | 26 (26) | 17 (17) | 103 (103) | 32 (32) | 29 (29) | |standard|std_1c20:inst|sys_clk_timer:the_sys_clk_timer
|sys_clk_timer_s1_arbitrator:the_sys_clk_timer_s1| | 5 (5) | 0 | 0 | 0 | 0 | 0 | 5 (5) | 0 (0) | 0 (0) | 0 (0) | 0 (0) | |standard|std_1c20:inst|sys_clk_timer_s1_arbitrator:the_sys_clk_timer_s1
|sysid_control_slave_arbitrator:the_sysid_control_slave| | 10 (10) | 0 | 0 | 0 | 0 | 0 | 10 (10) | 0 (0) | 0 (0) | 0 (0) | 0 (0) | |standard|std_1c20:inst|sysid_control_slave_arbitrator:the_sysid_control_slave
|uart1:the_uart1| | 138 (0) | 92 | 0 | 0 | 0 | 0 | 46 (0) | 9 (0) | 83 (0) | 18 (0) | 22 (0) | |standard|std_1c20:inst|uart1:the_uart1
|uart1_regs:the_uart1_regs| | 42 (42) | 29 | 0 | 0 | 0 | 0 | 13 (13) | 7 (7) | 22 (22) | 0 (0) | 19 (19) | |standard|std_1c20:inst|uart1:the_uart1|uart1_regs:the_uart1_regs
|uart1_rx:the_uart1_rx| | 59 (59) | 37 | 0 | 0 | 0 | 0 | 22 (22) | 2 (2) | 35 (35) | 9 (9) | 2 (2) | |standard|std_1c20:inst|uart1:the_uart1|uart1_rx:the_uart1_rx
|uart1_tx:the_uart1_tx| | 37 (37) | 26 | 0 | 0 | 0 | 0 | 11 (11) | 0 (0) | 26 (26) | 9 (9) | 1 (1) | |standard|std_1c20:inst|uart1:the_uart1|uart1_tx:the_uart1_tx
|uart1_s1_arbitrator:the_uart1_s1| | 2 (2) | 1 | 0 | 0 | 0 | 0 | 1 (1) | 0 (0) | 1 (1) | 0 (0) | 0 (0) | |standard|std_1c20:inst|uart1_s1_arbitrator:the_uart1_s1

Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.

## Delay Chain Summary

Top

Name | Pin Type | Pad to Core 0 | Pad to Core 1 | Pad to Input Register | TCO
--- | --- | --- | --- | --- | ---
PLD_CLKFB | Input | -- | -- | -- | --
PLD_CLOCKINPUT[1] | Input | -- | -- | -- | --
PLD_CLEAR_N | Input | ON | ON | -- | --
in_port_to_the_button_pio[2] | Input | ON | ON | -- | --
in_port_to_the_button_pio[3] | Input | ON | ON | -- | --
irq_from_the_lan91c111 | Input | ON | ON | -- | --
in_port_to_the_button_pio[1] | Input | ON | ON | -- | --
in_port_to_the_button_pio[0] | Input | ON | ON | -- | --
rxd_to_the_uart1 | Input | ON | ON | -- | --
SDRAM_CLK | Output | -- | -- | -- | --
PLD_CLKOUT | Output | -- | -- | -- | --
ENET_ADS_N | Output | -- | -- | -- | --
ENET_AEN | Output | -- | -- | -- | --
ior_n_to_the_lan91c111 | Output | -- | -- | -- | OFF
write_n_to_the_ext_flash | Output | -- | -- | -- | OFF
iow_n_to_the_lan91c111 | Output | -- | -- | -- | OFF
read_n_to_the_ext_flash | Output | -- | -- | -- | OFF
read_n_to_the_ext_ram | Output | -- | -- | -- | OFF
select_n_to_the_ext_flash | Output | -- | -- | -- | OFF
select_n_to_the_ext_ram | Output | -- | -- | -- | OFF
write_n_to_the_ext_ram | Output | -- | -- | -- | --
zs_cas_n_from_the_sdram | Output | -- | -- | -- | OFF
zs_cke_from_the_sdram | Output | -- | -- | -- | --
zs_cs_n_from_the_sdram | Output | -- | -- | -- | OFF
zs_ras_n_from_the_sdram | Output | -- | -- | -- | OFF
zs_we_n_from_the_sdram | Output | -- | -- | -- | OFF
txd_from_the_uart1 | Output | -- | -- | -- | --
LCD_RW_from_the_lcd_display | Output | -- | -- | -- | --
LCD_RS_from_the_lcd_display | Output | -- | -- | -- | --
LCD_E_from_the_lcd_display | Output | -- | -- | -- | --
be_n_to_the_ext_ram[3] | Output | -- | -- | -- | OFF
be_n_to_the_ext_ram[2] | Output | -- | -- | -- | OFF
be_n_to_the_ext_ram[1] | Output | -- | -- | -- | OFF
be_n_to_the_ext_ram[0] | Output | -- | -- | -- | OFF
byteenablen_to_the_lan91c111[3] | Output | -- | -- | -- | OFF
byteenablen_to_the_lan91c111[2] | Output | -- | -- | -- | OFF
byteenablen_to_the_lan91c111[1] | Output | -- | -- | -- | OFF
byteenablen_to_the_lan91c111[0] | Output | -- | -- | -- | OFF
ext_ram_bus_address[22] | Output | -- | -- | -- | OFF
ext_ram_bus_address[21] | Output | -- | -- | -- | OFF
ext_ram_bus_address[20] | Output | -- | -- | -- | OFF
ext_ram_bus_address[19] | Output | -- | -- | -- | OFF
ext_ram_bus_address[18] | Output | -- | -- | -- | OFF
ext_ram_bus_address[17] | Output | -- | -- | -- | OFF
ext_ram_bus_address[16] | Output | -- | -- | -- | OFF
ext_ram_bus_address[15] | Output | -- | -- | -- | OFF
ext_ram_bus_address[14] | Output | -- | -- | -- | OFF
ext_ram_bus_address[13] | Output | -- | -- | -- | OFF
ext_ram_bus_address[12] | Output | -- | -- | -- | OFF
ext_ram_bus_address[11] | Output | -- | -- | -- | OFF
ext_ram_bus_address[10] | Output | -- | -- | -- | OFF
ext_ram_bus_address[9] | Output | -- | -- | -- | OFF
ext_ram_bus_address[8] | Output | -- | -- | -- | OFF
ext_ram_bus_address[7] | Output | -- | -- | -- | OFF
ext_ram_bus_address[6] | Output | -- | -- | -- | OFF
ext_ram_bus_address[5] | Output | -- | -- | -- | OFF
ext_ram_bus_address[4] | Output | -- | -- | -- | OFF
ext_ram_bus_address[3] | Output | -- | -- | -- | OFF
ext_ram_bus_address[2] | Output | -- | -- | -- | OFF
ext_ram_bus_address[1] | Output | -- | -- | -- | OFF
ext_ram_bus_address[0] | Output | -- | -- | -- | OFF
out_port_from_the_led_pio[7] | Output | -- | -- | -- | --
out_port_from_the_led_pio[6] | Output | -- | -- | -- | --
out_port_from_the_led_pio[5] | Output | -- | -- | -- | --
out_port_from_the_led_pio[4] | Output | -- | -- | -- | --
out_port_from_the_led_pio[3] | Output | -- | -- | -- | --
out_port_from_the_led_pio[2] | Output | -- | -- | -- | --
out_port_from_the_led_pio[1] | Output | -- | -- | -- | --
out_port_from_the_led_pio[0] | Output | -- | -- | -- | --
out_port_from_the_seven_seg_pio[15] | Output | -- | -- | -- | --
out_port_from_the_seven_seg_pio[14] | Output | -- | -- | -- | --
out_port_from_the_seven_seg_pio[13] | Output | -- | -- | -- | --
out_port_from_the_seven_seg_pio[12] | Output | -- | -- | -- | --
out_port_from_the_seven_seg_pio[11] | Output | -- | -- | -- | --
out_port_from_the_seven_seg_pio[10] | Output | -- | -- | -- | --
out_port_from_the_seven_seg_pio[9] | Output | -- | -- | -- | --
out_port_from_the_seven_seg_pio[8] | Output | -- | -- | -- | --
out_port_from_the_seven_seg_pio[7] | Output | -- | -- | -- | --
out_port_from_the_seven_seg_pio[6] | Output | -- | -- | -- | --
out_port_from_the_seven_seg_pio[5] | Output | -- | -- | -- | --
out_port_from_the_seven_seg_pio[4] | Output | -- | -- | -- | --
out_port_from_the_seven_seg_pio[3] | Output | -- | -- | -- | --
out_port_from_the_seven_seg_pio[2] | Output | -- | -- | -- | --
out_port_from_the_seven_seg_pio[1] | Output | -- | -- | -- | --
out_port_from_the_seven_seg_pio[0] | Output | -- | -- | -- | --
zs_addr_from_the_sdram[11] | Output | -- | -- | -- | OFF
zs_addr_from_the_sdram[10] | Output | -- | -- | -- | OFF
zs_addr_from_the_sdram[9] | Output | -- | -- | -- | OFF
zs_addr_from_the_sdram[8] | Output | -- | -- | -- | OFF
zs_addr_from_the_sdram[7] | Output | -- | -- | -- | OFF
zs_addr_from_the_sdram[6] | Output | -- | -- | -- | OFF
zs_addr_from_the_sdram[5] | Output | -- | -- | -- | OFF
zs_addr_from_the_sdram[4] | Output | -- | -- | -- | OFF
zs_addr_from_the_sdram[3] | Output | -- | -- | -- | OFF
zs_addr_from_the_sdram[2] | Output | -- | -- | -- | OFF
zs_addr_from_the_sdram[1] | Output | -- | -- | -- | OFF
zs_addr_from_the_sdram[0] | Output | -- | -- | -- | OFF
zs_ba_from_the_sdram[1] | Output | -- | -- | -- | OFF
zs_ba_from_the_sdram[0] | Output | -- | -- | -- | OFF
zs_dqm_from_the_sdram[3] | Output | -- | -- | -- | OFF
zs_dqm_from_the_sdram[2] | Output | -- | -- | -- | OFF
zs_dqm_from_the_sdram[1] | Output | -- | -- | -- | OFF
zs_dqm_from_the_sdram[0] | Output | -- | -- | -- | OFF
bidir_port_to_and_from_the_reconfig_request_pio | Bidir | ON | ON | -- | --
ext_ram_bus_data[31] | Bidir | OFF | OFF | OFF | OFF
ext_ram_bus_data[30] | Bidir | OFF | OFF | OFF | OFF
ext_ram_bus_data[29] | Bidir | OFF | OFF | OFF | OFF
ext_ram_bus_data[28] | Bidir | OFF | OFF | OFF | OFF
ext_ram_bus_data[27] | Bidir | OFF | OFF | OFF | OFF
ext_ram_bus_data[26] | Bidir | OFF | OFF | OFF | OFF
ext_ram_bus_data[25] | Bidir | OFF | OFF | OFF | OFF
ext_ram_bus_data[24] | Bidir | OFF | OFF | OFF | OFF
ext_ram_bus_data[23] | Bidir | OFF | OFF | OFF | OFF
ext_ram_bus_data[22] | Bidir | OFF | OFF | OFF | OFF
ext_ram_bus_data[21] | Bidir | OFF | OFF | OFF | OFF
ext_ram_bus_data[20] | Bidir | OFF | OFF | OFF | OFF
ext_ram_bus_data[19] | Bidir | OFF | OFF | OFF | OFF
ext_ram_bus_data[18] | Bidir | OFF | OFF | OFF | OFF
ext_ram_bus_data[17] | Bidir | OFF | OFF | OFF | OFF
ext_ram_bus_data[16] | Bidir | OFF | OFF | OFF | OFF
ext_ram_bus_data[15] | Bidir | OFF | OFF | OFF | OFF
ext_ram_bus_data[14] | Bidir | OFF | OFF | OFF | OFF
ext_ram_bus_data[13] | Bidir | OFF | OFF | OFF | OFF
ext_ram_bus_data[12] | Bidir | OFF | OFF | OFF | OFF
ext_ram_bus_data[11] | Bidir | OFF | OFF | OFF | OFF
ext_ram_bus_data[10] | Bidir | OFF | OFF | OFF | OFF
ext_ram_bus_data[9] | Bidir | OFF | OFF | OFF | OFF
ext_ram_bus_data[8] | Bidir | OFF | OFF | OFF | OFF
ext_ram_bus_data[7] | Bidir | OFF | OFF | OFF | OFF
ext_ram_bus_data[6] | Bidir | OFF | OFF | OFF | OFF
ext_ram_bus_data[5] | Bidir | OFF | OFF | OFF | OFF
ext_ram_bus_data[4] | Bidir | OFF | OFF | OFF | OFF
ext_ram_bus_data[3] | Bidir | OFF | OFF | OFF | OFF
ext_ram_bus_data[2] | Bidir | OFF | OFF | OFF | OFF
ext_ram_bus_data[1] | Bidir | OFF | OFF | OFF | OFF
ext_ram_bus_data[0] | Bidir | OFF | OFF | OFF | OFF
LCD_data_to_and_from_the_lcd_display[7] | Bidir | ON | ON | -- | --
LCD_data_to_and_from_the_lcd_display[6] | Bidir | ON | ON | -- | --
LCD_data_to_and_from_the_lcd_display[5] | Bidir | ON | ON | -- | --
LCD_data_to_and_from_the_lcd_display[4] | Bidir | ON | ON | -- | --
LCD_data_to_and_from_the_lcd_display[3] | Bidir | ON | ON | -- | --
LCD_data_to_and_from_the_lcd_display[2] | Bidir | ON | ON | -- | --
LCD_data_to_and_from_the_lcd_display[1] | Bidir | ON | ON | -- | --
LCD_data_to_and_from_the_lcd_display[0] | Bidir | ON | ON | -- | --
zs_dq_to_and_from_the_sdram[31] | Bidir | OFF | OFF | OFF | OFF
zs_dq_to_and_from_the_sdram[30] | Bidir | OFF | OFF | OFF | OFF
zs_dq_to_and_from_the_sdram[29] | Bidir | OFF | OFF | OFF | OFF
zs_dq_to_and_from_the_sdram[28] | Bidir | OFF | OFF | OFF | OFF
zs_dq_to_and_from_the_sdram[27] | Bidir | OFF | OFF | OFF | OFF
zs_dq_to_and_from_the_sdram[26] | Bidir | OFF | OFF | OFF | OFF
zs_dq_to_and_from_the_sdram[25] | Bidir | OFF | OFF | OFF | OFF
zs_dq_to_and_from_the_sdram[24] | Bidir | OFF | OFF | OFF | OFF
zs_dq_to_and_from_the_sdram[23] | Bidir | OFF | OFF | OFF | OFF
zs_dq_to_and_from_the_sdram[22] | Bidir | OFF | OFF | OFF | OFF
zs_dq_to_and_from_the_sdram[21] | Bidir | OFF | OFF | OFF | OFF
zs_dq_to_and_from_the_sdram[20] | Bidir | OFF | OFF | OFF | OFF
zs_dq_to_and_from_the_sdram[19] | Bidir | OFF | OFF | OFF | OFF
zs_dq_to_and_from_the_sdram[18] | Bidir | OFF | OFF | OFF | OFF
zs_dq_to_and_from_the_sdram[17] | Bidir | OFF | OFF | OFF | OFF
zs_dq_to_and_from_the_sdram[16] | Bidir | OFF | OFF | OFF | OFF
zs_dq_to_and_from_the_sdram[15] | Bidir | OFF | OFF | OFF | OFF
zs_dq_to_and_from_the_sdram[14] | Bidir | OFF | OFF | OFF | OFF
zs_dq_to_and_from_the_sdram[13] | Bidir | OFF | OFF | OFF | OFF
zs_dq_to_and_from_the_sdram[12] | Bidir | OFF | OFF | OFF | OFF
zs_dq_to_and_from_the_sdram[11] | Bidir | OFF | OFF | OFF | OFF
zs_dq_to_and_from_the_sdram[10] | Bidir | OFF | OFF | OFF | OFF
zs_dq_to_and_from_the_sdram[9] | Bidir | OFF | OFF | OFF | OFF
zs_dq_to_and_from_the_sdram[8] | Bidir | OFF | OFF | OFF | OFF
zs_dq_to_and_from_the_sdram[7] | Bidir | OFF | OFF | OFF | OFF
zs_dq_to_and_from_the_sdram[6] | Bidir | OFF | OFF | OFF | OFF
zs_dq_to_and_from_the_sdram[5] | Bidir | OFF | OFF | OFF | OFF
zs_dq_to_and_from_the_sdram[4] | Bidir | OFF | OFF | OFF | OFF
zs_dq_to_and_from_the_sdram[3] | Bidir | OFF | OFF | OFF | OFF
zs_dq_to_and_from_the_sdram[2] | Bidir | OFF | OFF | OFF | OFF
zs_dq_to_and_from_the_sdram[1] | Bidir | OFF | OFF | OFF | OFF
zs_dq_to_and_from_the_sdram[0] | Bidir | OFF | OFF | OFF | OFF

## Pad To Core Delay Chain Fanout

Top

Source Pin / Fanout | Pad To Core Index | Setting
--- | --- | ---
PLD_CLKFB |  |
PLD_CLOCKINPUT[1] |  |
PLD_CLEAR_N |  |
- std_1c20:inst|reset_n_sources~23 | 0 | ON
in_port_to_the_button_pio[2] |  |
- std_1c20:inst|button_pio:the_button_pio|readdata[2] | 0 | ON
- std_1c20:inst|button_pio:the_button_pio|d1_data_in[2] | 0 | ON
in_port_to_the_button_pio[3] |  |
- std_1c20:inst|button_pio:the_button_pio|readdata[3] | 0 | ON
- std_1c20:inst|button_pio:the_button_pio|d1_data_in[3] | 0 | ON
irq_from_the_lan91c111 |  |
- std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_irq_from_the_lan91c111 | 0 | ON
in_port_to_the_button_pio[1] |  |
- std_1c20:inst|button_pio:the_button_pio|readdata[1] | 0 | ON
- std_1c20:inst|button_pio:the_button_pio|d1_data_in[1] | 0 | ON
in_port_to_the_button_pio[0] |  |
- std_1c20:inst|button_pio:the_button_pio|readdata[0] | 1 | ON
- std_1c20:inst|button_pio:the_button_pio|d1_data_in[0] | 1 | ON
rxd_to_the_uart1 |  |
- std_1c20:inst|uart1:the_uart1|uart1_rx:the_uart1_rx|d1_source_rxd | 0 | ON
bidir_port_to_and_from_the_reconfig_request_pio |  |
- std_1c20:inst|reconfig_request_pio:the_reconfig_request_pio|readdata | 0 | ON
ext_ram_bus_data[31] |  |
ext_ram_bus_data[30] |  |
ext_ram_bus_data[29] |  |
ext_ram_bus_data[28] |  |
ext_ram_bus_data[27] |  |
ext_ram_bus_data[26] |  |
ext_ram_bus_data[25] |  |
ext_ram_bus_data[24] |  |
ext_ram_bus_data[23] |  |
ext_ram_bus_data[22] |  |
ext_ram_bus_data[21] |  |
ext_ram_bus_data[20] |  |
ext_ram_bus_data[19] |  |
ext_ram_bus_data[18] |  |
ext_ram_bus_data[17] |  |
ext_ram_bus_data[16] |  |
ext_ram_bus_data[15] |  |
ext_ram_bus_data[14] |  |
ext_ram_bus_data[13] |  |
ext_ram_bus_data[12] |  |
ext_ram_bus_data[11] |  |
ext_ram_bus_data[10] |  |
ext_ram_bus_data[9] |  |
ext_ram_bus_data[8] |  |
ext_ram_bus_data[7] |  |
ext_ram_bus_data[6] |  |
ext_ram_bus_data[5] |  |
ext_ram_bus_data[4] |  |
ext_ram_bus_data[3] |  |
ext_ram_bus_data[2] |  |
ext_ram_bus_data[1] |  |
ext_ram_bus_data[0] |  |
LCD_data_to_and_from_the_lcd_display[7] |  |
- std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[7]~5208 | 0 | ON
LCD_data_to_and_from_the_lcd_display[6] |  |
- std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[6]~5299 | 0 | ON
LCD_data_to_and_from_the_lcd_display[5] |  |
- std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[5]~5315 | 1 | ON
LCD_data_to_and_from_the_lcd_display[4] |  |
- std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata~568 | 0 | ON
LCD_data_to_and_from_the_lcd_display[3] |  |
- std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[3]~5183 | 1 | ON
LCD_data_to_and_from_the_lcd_display[2] |  |
- std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[2]~5166 | 0 | ON
LCD_data_to_and_from_the_lcd_display[1] |  |
- std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[1]~5338 | 0 | ON
LCD_data_to_and_from_the_lcd_display[0] |  |
- std_1c20:inst|cpu:the_cpu|d_readdata_d1[0]~210 | 1 | ON
zs_dq_to_and_from_the_sdram[31] |  |
zs_dq_to_and_from_the_sdram[30] |  |
zs_dq_to_and_from_the_sdram[29] |  |
zs_dq_to_and_from_the_sdram[28] |  |
zs_dq_to_and_from_the_sdram[27] |  |
zs_dq_to_and_from_the_sdram[26] |  |
zs_dq_to_and_from_the_sdram[25] |  |
zs_dq_to_and_from_the_sdram[24] |  |
zs_dq_to_and_from_the_sdram[23] |  |
zs_dq_to_and_from_the_sdram[22] |  |
zs_dq_to_and_from_the_sdram[21] |  |
zs_dq_to_and_from_the_sdram[20] |  |
zs_dq_to_and_from_the_sdram[19] |  |
zs_dq_to_and_from_the_sdram[18] |  |
zs_dq_to_and_from_the_sdram[17] |  |
zs_dq_to_and_from_the_sdram[16] |  |
zs_dq_to_and_from_the_sdram[15] |  |
zs_dq_to_and_from_the_sdram[14] |  |
zs_dq_to_and_from_the_sdram[13] |  |
zs_dq_to_and_from_the_sdram[12] |  |
zs_dq_to_and_from_the_sdram[11] |  |
zs_dq_to_and_from_the_sdram[10] |  |
zs_dq_to_and_from_the_sdram[9] |  |
zs_dq_to_and_from_the_sdram[8] |  |
zs_dq_to_and_from_the_sdram[7] |  |
zs_dq_to_and_from_the_sdram[6] |  |
zs_dq_to_and_from_the_sdram[5] |  |
zs_dq_to_and_from_the_sdram[4] |  |
zs_dq_to_and_from_the_sdram[3] |  |
zs_dq_to_and_from_the_sdram[2] |  |
zs_dq_to_and_from_the_sdram[1] |  |
zs_dq_to_and_from_the_sdram[0] |  |

## Control Signals

Top

Name | Location | Fan-Out | Usage | Global | Global Resource Used | Global Line Name
--- | --- | --- | --- | --- | --- | ---
PLD_CLKFB | PIN_L14 | 74 | Clock | yes | Global clock | GCLK6
PLD_CLOCKINPUT[1] | PIN_K5 | 74 | Clock | yes | Global clock | GCLK2
altera_internal_jtag~TCKUTAP | JTAG_X1_Y16_N1 | 159 | Clock | yes | Global clock | GCLK1
altera_internal_jtag~TMSUTAP | JTAG_X1_Y16_N1 | 22 | Sync. clear | no | -- | --
altera_internal_jtag~UPDATEUSER | JTAG_X1_Y16_N1 | 41 | Async. clear, Async. load, Clock | yes | Global clock | GCLK0
sld_hub:sld_hub_inst|CLR_SIGNAL | LC_X61_Y16_N5 | 183 | Async. clear, Async. load | yes | Global clock | GCLK5
sld_hub:sld_hub_inst|GEN_SHADOW_IRF~1 | LC_X57_Y16_N9 | 2 | Clock enable | no | -- | --
sld_hub:sld_hub_inst|IRF_ENABLE[1]~136 | LC_X57_Y16_N2 | 2 | Clock enable | no | -- | --
sld_hub:sld_hub_inst|IRF_ENA_ENABLE~29 | LC_X58_Y17_N7 | 3 | Clock enable | no | -- | --
sld_hub:sld_hub_inst|IRSR_ENA | LC_X56_Y18_N2 | 2 | Clock enable | no | -- | --
sld_hub:sld_hub_inst|comb~99 | LC_X58_Y17_N8 | 5 | Clock enable | no | -- | --
sld_hub:sld_hub_inst|jtag_debug_mode_usr1 | LC_X58_Y16_N4 | 16 | Async. clear | no | -- | --
sld_hub:sld_hub_inst|sld_dffex:IRSR|Q[0]~7721 | LC_X57_Y18_N9 | 5 | Clock enable | no | -- | --
sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state[0] | LC_X57_Y15_N1 | 15 | Async. clear | no | -- | --
sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state[11] | LC_X57_Y15_N7 | 12 | Clock enable | no | -- | --
sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state[12] | LC_X58_Y15_N9 | 5 | Clock enable | no | -- | --
sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state[4] | LC_X58_Y17_N3 | 41 | Sync. clear, Sync. load | no | -- | --
sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state[8] | LC_X58_Y15_N5 | 16 | Async. clear | no | -- | --
sld_hub:sld_hub_inst|sld_rom_sr:HUB_INFO_REG|clear_signal | LC_X58_Y17_N5 | 8 | Sync. clear | no | -- | --
sld_hub:sld_hub_inst|sld_rom_sr:HUB_INFO_REG|word_counter[0]~1278 | LC_X58_Y17_N1 | 5 | Clock enable | no | -- | --
sld_hub:sld_hub_inst|sld_rom_sr:HUB_INFO_REG|word_counter[0]~1282 | LC_X57_Y17_N6 | 4 | Clock enable | no | -- | --
std_1c20:inst|button_pio:the_button_pio|process1~14 | LC_X45_Y20_N6 | 4 | Clock enable | no | -- | --
std_1c20:inst|clock_0:the_clock_0|process0~11 | LC_X44_Y28_N7 | 16 | Clock enable | no | -- | --
std_1c20:inst|clock_1:the_clock_1|process0~11 | LC_X47_Y29_N2 | 16 | Clock enable | no | -- | --
std_1c20:inst|connector_pll:the_connector_pll|control_reg_en~18 | LC_X48_Y29_N1 | 16 | Clock enable | no | -- | --
std_1c20:inst|connector_pll:the_connector_pll|count_done | LC_X18_Y24_N3 | 8 | Clock enable | no | -- | --
std_1c20:inst|connector_pll:the_connector_pll|not_areset | LC_X18_Y24_N4 | 7 | Async. clear | no | -- | --
std_1c20:inst|cpu:the_cpu|D_ic_fill_starting | LC_X24_Y20_N3 | 37 | Clock enable | no | -- | --
std_1c20:inst|cpu:the_cpu|D_src1_hazard_M | LC_X33_Y16_N8 | 32 | Sync. load | no | -- | --
std_1c20:inst|cpu:the_cpu|D_src2_hazard_M~45 | LC_X34_Y15_N9 | 32 | Sync. load | no | -- | --
std_1c20:inst|cpu:the_cpu|E_ctrl_alu_subtract | LC_X31_Y13_N8 | 33 | Invert A | no | -- | --
std_1c20:inst|cpu:the_cpu|E_ctrl_dst_data_sel_cmp | LC_X30_Y13_N2 | 59 | Sync. clear | no | -- | --
std_1c20:inst|cpu:the_cpu|E_ctrl_rdctl_inst | LC_X32_Y14_N9 | 54 | Sync. load | no | -- | --
std_1c20:inst|cpu:the_cpu|E_hbreak_req | LC_X30_Y15_N5 | 26 | Sync. load | no | -- | --
std_1c20:inst|cpu:the_cpu|E_iw[4] | LC_X31_Y15_N0 | 24 | Sync. load | no | -- | --
std_1c20:inst|cpu:the_cpu|Equal145~6 | LC_X39_Y20_N4 | 8 | Sync. load | no | -- | --
std_1c20:inst|cpu:the_cpu|M_alu_result[2]~_DUP_REG | LC_X38_Y15_N9 | 82 | Output enable | no | -- | --
std_1c20:inst|cpu:the_cpu|M_ienable_reg[2]~4 | LC_X32_Y19_N4 | 7 | Clock enable | no | -- | --
std_1c20:inst|cpu:the_cpu|M_ld_align_sh8 | LC_X39_Y20_N5 | 8 | Sync. load | no | -- | --
std_1c20:inst|cpu:the_cpu|M_pipe_flush | LC_X30_Y18_N8 | 32 | Sync. load | no | -- | --
std_1c20:inst|cpu:the_cpu|M_shift_rot_stall | LC_X38_Y13_N2 | 41 | Sync. load | no | -- | --
std_1c20:inst|cpu:the_cpu|M_wr_dst_reg | LC_X34_Y15_N4 | 5 | Clock enable | no | -- | --
std_1c20:inst|cpu:the_cpu|W_stall | LC_X34_Y18_N3 | 541 | Clock enable | no | -- | --
std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|DRsize[0]~19971 | LC_X52_Y14_N6 | 16 | Clock enable | no | -- | --
std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|DRsize[0]~19978 | LC_X52_Y15_N4 | 20 | Clock enable | no | -- | --
std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|DRsize[0]~20003 | LC_X52_Y15_N6 | 2 | Clock enable | no | -- | --
std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|ir[0] | LC_X52_Y15_N3 | 56 | Sync. load | no | -- | --
std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|ir[0]~0 | LC_X54_Y16_N7 | 2 | Clock enable | no | -- | --
std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|process2~312 | LC_X46_Y15_N0 | 25 | Sync. load | no | -- | --
std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|process3~14 | LC_X56_Y16_N2 | 73 | Clock enable | no | -- | --
std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|st_updateir | LC_X54_Y16_N4 | 8 | Clock enable | no | -- | --
std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|take_action_break_c~48 | LC_X46_Y17_N4 | 32 | Clock enable | no | -- | --
std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|take_action_ocimem_a~54 | LC_X46_Y17_N3 | 8 | Clock enable | no | -- | --
std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|take_action_ocimem_a~55 | LC_X46_Y18_N6 | 15 | Clock enable, Sync. load | no | -- | --
std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|take_action_ocimem_b~30 | LC_X46_Y17_N8 | 14 | Sync. load | no | -- | --
std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|take_no_action_ocimem_a~20 | LC_X46_Y18_N9 | 9 | Sync. load | no | -- | --
std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|MonWr | LC_X45_Y18_N4 | 3 | Write enable | no | -- | --
std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|internal_MonDReg[1]~7325 | LC_X9_Y22_N2 | 2 | Clock enable | no | -- | --
std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|internal_MonDReg[1]~7328 | LC_X48_Y18_N8 | 32 | Clock enable | no | -- | --
std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|internal_MonDReg[1]~7329 | LC_X48_Y18_N9 | 31 | Sync. load | no | -- | --
std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|module_input6~27 | LC_X43_Y19_N7 | 2 | Write enable | no | -- | --
std_1c20:inst|cpu:the_cpu|i_readdatavalid_d1 | LC_X33_Y24_N8 | 11 | Clock enable | no | -- | --
std_1c20:inst|cpu:the_cpu|ic_fill_dp_offset_en~5 | LC_X23_Y20_N6 | 4 | Clock enable | no | -- | --
std_1c20:inst|cpu:the_cpu|ic_fill_prevent_refill_nxt~0 | LC_X23_Y20_N0 | 9 | Sync. load | no | -- | --
std_1c20:inst|cpu:the_cpu|ic_fill_req_accepted | LC_X26_Y22_N1 | 3 | Sync. load | no | -- | --
std_1c20:inst|cpu:the_cpu|ic_fill_valid_bits_en | LC_X23_Y20_N4 | 8 | Clock enable | no | -- | --
std_1c20:inst|cpu:the_cpu|ic_tag_wren | LC_X23_Y20_N5 | 1 | Clock enable | no | -- | --
std_1c20:inst|cpu:the_cpu|reset_d1 | LC_X26_Y20_N5 | 9 | Sync. clear | no | -- | --
std_1c20:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|process2~0 | LC_X37_Y25_N4 | 8 | Clock enable | no | -- | --
std_1c20:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|process3~0 | LC_X37_Y25_N1 | 8 | Clock enable | no | -- | --
std_1c20:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|process4~0 | LC_X37_Y25_N3 | 8 | Clock enable | no | -- | --
std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|Equal0~142 | LC_X36_Y27_N6 | 7 | Sync. load | no | -- | --
std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|Equal0~143 | LC_X36_Y26_N4 | 4 | Sync. load | no | -- | --
std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|SCLK_reg | LC_X41_Y28_N6 | 11 | Clock | no | -- | --
std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|control_wr_strobe | LC_X37_Y27_N0 | 7 | Clock enable | no | -- | --
std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|process11~0 | LC_X41_Y28_N9 | 6 | Clock enable | no | -- | --
std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|rx_holding_reg[7]~7 | LC_X41_Y29_N7 | 10 | Clock enable | no | -- | --
std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|slowcount[0] | LC_X41_Y28_N2 | 14 | Sync. load | no | -- | --
std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|write_tx_holding | LC_X38_Y28_N3 | 8 | Clock enable | no | -- | --
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|cpu_instruction_master_read_data_valid_ext_flash_s1_shift_register[1] | LC_X39_Y25_N0 | 45 | Clock enable | no | -- | --
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_in_a_write_cycle~COMB_OUT | LC_X29_Y26_N4 | 32 | Output enable | no | -- | --
std_1c20:inst|high_res_timer:the_high_res_timer|control_wr_strobe | LC_X47_Y23_N7 | 5 | Clock enable | no | -- | --
std_1c20:inst|high_res_timer:the_high_res_timer|period_h_wr_strobe | LC_X54_Y25_N1 | 16 | Clock enable | no | -- | --
std_1c20:inst|high_res_timer:the_high_res_timer|period_l_wr_strobe | LC_X54_Y25_N4 | 16 | Clock enable | no | -- | --
std_1c20:inst|high_res_timer:the_high_res_timer|process0~0 | LC_X54_Y23_N5 | 32 | Clock enable | no | -- | --
std_1c20:inst|high_res_timer:the_high_res_timer|process0~1 | LC_X54_Y23_N7 | 32 | Sync. load | no | -- | --
std_1c20:inst|high_res_timer:the_high_res_timer|snap_strobe~18 | LC_X53_Y24_N9 | 32 | Clock enable | no | -- | --
std_1c20:inst|jtag_uart:the_jtag_uart|alt_jtag_atlantic:jtag_uart_alt_jtag_atlantic|r_ena~0 | LC_X52_Y20_N8 | 8 | Clock enable | no | -- | --
std_1c20:inst|jtag_uart:the_jtag_uart|alt_jtag_atlantic:jtag_uart_alt_jtag_atlantic|td_shift[9]~3551 | LC_X55_Y19_N5 | 21 | Clock enable | no | -- | --
std_1c20:inst|jtag_uart:the_jtag_uart|alt_jtag_atlantic:jtag_uart_alt_jtag_atlantic|wdata[0]~7 | LC_X52_Y19_N6 | 4 | Clock enable | no | -- | --
std_1c20:inst|jtag_uart:the_jtag_uart|alt_jtag_atlantic:jtag_uart_alt_jtag_atlantic|wdata[1]~6 | LC_X54_Y19_N7 | 8 | Clock enable | no | -- | --
std_1c20:inst|jtag_uart:the_jtag_uart|fifo_wr | LC_X46_Y24_N4 | 15 | Clock enable | no | -- | --
std_1c20:inst|jtag_uart:the_jtag_uart|ien_AE~19 | LC_X46_Y24_N2 | 3 | Clock enable | no | -- | --
std_1c20:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_r:the_jtag_uart_scfifo_r|scfifo:rfifo|scfifo_jf21:auto_generated|a_dpfifo_ml21:dpfifo|a_fefifo_7cf:fifo_state|_~28 | LC_X45_Y21_N5 | 6 | Clock enable | no | -- | --
std_1c20:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_w:the_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_jf21:auto_generated|a_dpfifo_ml21:dpfifo|a_fefifo_7cf:fifo_state|_~28 | LC_X47_Y20_N7 | 6 | Clock enable | no | -- | --
std_1c20:inst|jtag_uart:the_jtag_uart|rd_wfifo | LC_X52_Y20_N2 | 10 | Clock enable | no | -- | --
std_1c20:inst|jtag_uart:the_jtag_uart|rvalid~26 | LC_X44_Y21_N4 | 7 | Clock enable | no | -- | --
std_1c20:inst|jtag_uart:the_jtag_uart|wr_rfifo | LC_X45_Y21_N7 | 13 | Clock enable | no | -- | --
std_1c20:inst|led_pio:the_led_pio|process0~1 | LC_X47_Y24_N4 | 8 | Clock enable | no | -- | --
std_1c20:inst|reconfig_request_pio:the_reconfig_request_pio|data_dir | LC_X47_Y22_N3 | 3 | Output enable | no | -- | --
std_1c20:inst|reset_n_sources~23 | LC_X18_Y24_N2 | 6 | Async. clear | no | -- | --
std_1c20:inst|sdram:the_sdram|Mux10~96 | LC_X10_Y22_N2 | 3 | Clock enable | no | -- | --
std_1c20:inst|sdram:the_sdram|Mux39~1240 | LC_X14_Y24_N2 | 5 | Clock enable | no | -- | --
std_1c20:inst|sdram:the_sdram|i_cmd[0]~642 | LC_X11_Y22_N2 | 4 | Clock enable | no | -- | --
std_1c20:inst|sdram:the_sdram|m_state[6] | LC_X12_Y22_N3 | 48 | Clock enable | no | -- | --
std_1c20:inst|sdram:the_sdram|oe | LC_X12_Y22_N2 | 32 | Output enable | no | -- | --
std_1c20:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_0[56]~56 | LC_X23_Y23_N0 | 59 | Clock enable | no | -- | --
std_1c20:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_1[56]~56 | LC_X23_Y23_N7 | 59 | Clock enable | no | -- | --
std_1c20:inst|sdram_pll:the_sdram_pll|altpllsdram_pll:the_pll|altpll:altpll_component|_clk0 | PLL_2 | 2389 | Clock | yes | Global clock | GCLK4
std_1c20:inst|sdram_pll:the_sdram_pll|control_reg_en~18 | LC_X43_Y29_N1 | 16 | Clock enable | no | -- | --
std_1c20:inst|sdram_pll:the_sdram_pll|count_done | LC_X18_Y25_N1 | 8 | Clock enable | no | -- | --
std_1c20:inst|sdram_pll:the_sdram_pll|not_areset | LC_X18_Y25_N3 | 7 | Async. clear | no | -- | --
std_1c20:inst|sdram_s1_arbitrator:the_sdram_s1|rdv_fifo_for_cpu_data_master_to_sdram_s1_module:rdv_fifo_for_cpu_data_master_to_sdram_s1|process1~3 | LC_X23_Y26_N2 | 7 | Clock enable | no | -- | --
std_1c20:inst|sdram_s1_arbitrator:the_sdram_s1|rdv_fifo_for_cpu_instruction_master_to_sdram_s1_module:rdv_fifo_for_cpu_instruction_master_to_sdram_s1|process15~0 | LC_X24_Y24_N0 | 11 | Clock enable | no | -- | --
std_1c20:inst|sdram_s1_arbitrator:the_sdram_s1|sdram_s1_arb_counter_enable~45 | LC_X21_Y22_N9 | 6 | Clock enable | no | -- | --
std_1c20:inst|sdram_s1_arbitrator:the_sdram_s1|sdram_s1_arb_winner~0 | LC_X23_Y22_N3 | 2 | Clock enable | no | -- | --
std_1c20:inst|seven_seg_pio:the_seven_seg_pio|process0~1 | LC_X36_Y25_N2 | 16 | Clock enable | no | -- | --
std_1c20:inst|std_1c20_reset_PLD_CLKFB_domain_synch_module:std_1c20_reset_PLD_CLKFB_domain_synch|data_out | LC_X61_Y16_N4 | 63 | Async. clear | yes | Global clock | GCLK7
std_1c20:inst|std_1c20_reset_PLD_CLOCKINPUT_domain_synch_module:std_1c20_reset_PLD_CLOCKINPUT_domain_synch|data_out | LC_X48_Y28_N0 | 63 | Async. clear | no | -- | --
std_1c20:inst|std_1c20_reset_sysclk2_domain_synch_module:std_1c20_reset_sysclk2_domain_synch|data_out | LC_X8_Y16_N4 | 2108 | Async. clear, Async. load | yes | Global clock | GCLK3
std_1c20:inst|sys_clk_timer:the_sys_clk_timer|control_wr_strobe | LC_X47_Y25_N8 | 5 | Clock enable | no | -- | --
std_1c20:inst|sys_clk_timer:the_sys_clk_timer|period_h_wr_strobe | LC_X47_Y25_N2 | 16 | Clock enable | no | -- | --
std_1c20:inst|sys_clk_timer:the_sys_clk_timer|period_l_wr_strobe | LC_X51_Y27_N8 | 16 | Clock enable | no | -- | --
std_1c20:inst|sys_clk_timer:the_sys_clk_timer|process0~0 | LC_X52_Y23_N5 | 32 | Clock enable | no | -- | --
std_1c20:inst|sys_clk_timer:the_sys_clk_timer|process0~1 | LC_X53_Y23_N6 | 32 | Sync. load | no | -- | --
std_1c20:inst|sys_clk_timer:the_sys_clk_timer|snap_strobe~24 | LC_X53_Y24_N4 | 32 | Clock enable | no | -- | --
std_1c20:inst|uart1:the_uart1|uart1_regs:the_uart1_regs|control_wr_strobe~27 | LC_X48_Y22_N1 | 10 | Clock enable | no | -- | --
std_1c20:inst|uart1:the_uart1|uart1_regs:the_uart1_regs|tx_wr_strobe~14 | LC_X47_Y22_N9 | 8 | Clock enable | no | -- | --
std_1c20:inst|uart1:the_uart1|uart1_rx:the_uart1_rx|got_new_char | LC_X52_Y22_N7 | 9 | Clock enable | no | -- | --
std_1c20:inst|uart1:the_uart1|uart1_rx:the_uart1_rx|unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[3]~7355 | LC_X53_Y22_N2 | 9 | Clock enable | no | -- | --
std_1c20:inst|uart1:the_uart1|uart1_tx:the_uart1_tx|process4~0 | LC_X48_Y25_N7 | 9 | Sync. load | no | -- | --
std_1c20:inst|uart1:the_uart1|uart1_tx:the_uart1_tx|unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out[3]~2822 | LC_X48_Y25_N6 | 10 | Clock enable | no | -- | --

## Global & Other Fast Signals

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Name | Location | Fan-Out | Global Resource Used | Global Line Name
--- | --- | --- | --- | ---
PLD_CLKFB | PIN_L14 | 74 | Global clock | GCLK6
PLD_CLOCKINPUT[1] | PIN_K5 | 74 | Global clock | GCLK2
altera_internal_jtag~TCKUTAP | JTAG_X1_Y16_N1 | 159 | Global clock | GCLK1
altera_internal_jtag~UPDATEUSER | JTAG_X1_Y16_N1 | 41 | Global clock | GCLK0
sld_hub:sld_hub_inst|CLR_SIGNAL | LC_X61_Y16_N5 | 183 | Global clock | GCLK5
std_1c20:inst|sdram_pll:the_sdram_pll|altpllsdram_pll:the_pll|altpll:altpll_component|_clk0 | PLL_2 | 2389 | Global clock | GCLK4
std_1c20:inst|std_1c20_reset_PLD_CLKFB_domain_synch_module:std_1c20_reset_PLD_CLKFB_domain_synch|data_out | LC_X61_Y16_N4 | 63 | Global clock | GCLK7
std_1c20:inst|std_1c20_reset_sysclk2_domain_synch_module:std_1c20_reset_sysclk2_domain_synch|data_out | LC_X8_Y16_N4 | 2108 | Global clock | GCLK3

## Non-Global High Fan-Out Signals

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Name | Fan-Out
--- | ---
std_1c20:inst|cpu:the_cpu|W_stall | 541
std_1c20:inst|sdram:the_sdram|m_state[1] | 89
std_1c20:inst|cpu:the_cpu|E_src2_hazard_M | 86
std_1c20:inst|cpu:the_cpu|M_alu_result[4]~_DUP_REG | 85
std_1c20:inst|cpu:the_cpu|M_alu_result[2]~_DUP_REG | 82
std_1c20:inst|cpu:the_cpu|M_alu_result[3] | 75
std_1c20:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|rd_address | 75
std_1c20:inst|cpu:the_cpu|E_ctrl_dst_data_sel_logic_result | 74
std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|process3~14 | 73
std_1c20:inst|epcs_controller:the_epcs_controller|epcs_select~62 | 68
std_1c20:inst|sdram:the_sdram|m_state[4] | 67
std_1c20:inst|sdram:the_sdram|m_state[0] | 66
std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|take_action_break_c~48 | 64
std_1c20:inst|std_1c20_reset_PLD_CLOCKINPUT_domain_synch_module:std_1c20_reset_PLD_CLOCKINPUT_domain_synch|data_out | 63
std_1c20:inst|sdram:the_sdram|m_state[3] | 63
std_1c20:inst|cpu:the_cpu|E_ctrl_src2_is_imm | 61
std_1c20:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_1[56]~56 | 59
std_1c20:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_0[56]~56 | 59
std_1c20:inst|cpu:the_cpu|E_ctrl_dst_data_sel_cmp | 59
std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|ir[0] | 56
std_1c20:inst|cpu:the_cpu|D_iw[21] | 55
std_1c20:inst|cpu:the_cpu|internal_d_write | 55
std_1c20:inst|cpu:the_cpu|E_ctrl_rdctl_inst | 54
std_1c20:inst|sdram_s1_arbitrator:the_sdram_s1|cpu_data_master_granted_sdram_s1~36 | 53
std_1c20:inst|cpu:the_cpu|M_ctrl_shift_rot~4_DUP_REG_8 | 51
std_1c20:inst|sysid_control_slave_arbitrator:the_sysid_control_slave|cpu_data_master_granted_sysid_control_slave~157 | 50
std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|ir[1] | 49
std_1c20:inst|sdram:the_sdram|f_select | 48
std_1c20:inst|cpu_jtag_debug_module_arbitrator:the_cpu_jtag_debug_module|cpu_data_master_granted_cpu_jtag_debug_module~64 | 48
std_1c20:inst|sdram:the_sdram|m_state[6] | 48
std_1c20:inst|epcs_controller_epcs_control_port_arbitrator:the_epcs_controller_epcs_control_port|cpu_instruction_master_qualified_request_epcs_controller_epcs_control_port~_DUP_COMB | 47
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|cpu_instruction_master_read_data_valid_ext_flash_s1_shift_register[1] | 45
std_1c20:inst|jtag_uart_avalon_jtag_slave_arbitrator:the_jtag_uart_avalon_jtag_slave|cpu_data_master_requests_jtag_uart_avalon_jtag_slave~554 | 45
std_1c20:inst|cpu:the_cpu|E_logic_op[0] | 45
std_1c20:inst|cpu:the_cpu|M_alu_result[5]~_DUP_REG | 43
std_1c20:inst|cpu:the_cpu|M_ctrl_shift_rot~4 | 43
std_1c20:inst|cpu:the_cpu|E_logic_op[1] | 43
std_1c20:inst|cpu:the_cpu|ic_fill_line[5] | 42
sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state[4] | 41
std_1c20:inst|cpu:the_cpu|M_shift_rot_stall | 41
std_1c20:inst|cpu:the_cpu|internal_d_write~71 | 40
std_1c20:inst|cpu:the_cpu|M_alu_result[10]~_DUP_REG | 39
std_1c20:inst|sdram:the_sdram|Mux118~1221 | 39
std_1c20:inst|sdram:the_sdram|m_state[8] | 39
std_1c20:inst|cpu:the_cpu|internal_d_write~69 | 38
std_1c20:inst|sdram_s1_arbitrator:the_sdram_s1|cpu_instruction_master_read_data_valid_sdram_s1 | 38
std_1c20:inst|cpu:the_cpu|d_readdata_d1[8]~108 | 38
std_1c20:inst|cpu:the_cpu|D_ic_fill_starting | 37
std_1c20:inst|cpu:the_cpu|D_iw[2] | 36
std_1c20:inst|cpu:the_cpu|E_ctrl_dst_data_sel_pc_plus_one | 36

## Fitter RAM Summary

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Name | Type | Mode | Port A Depth | Port A Width | Port B Depth | Port B Width | Port A Input Registers | Port A Output Registers | Port B Input Registers | Port B Output Registers | Size | Implementation Port A Depth | Implementation Port A Width | Implementation Port B Depth | Implementation Port B Width | Implementation Bits | M4Ks | MIF | Location
--- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | ---
std_1c20:inst|cpu:the_cpu|cpu_ic_data_module:cpu_ic_data|altsyncram:the_altsyncram|altsyncram_qmb1:auto_generated|ALTSYNCRAM | AUTO | Simple Dual Port | 1024 | 32 | 1024 | 32 | yes | no | yes | no | 32768 | 1024 | 32 | 1024 | 32 | 32768 | 8 | None | M4K_X19_Y22, M4K_X19_Y23, M4K_X19_Y16, M4K_X19_Y18, M4K_X19_Y24, M4K_X19_Y19, M4K_X19_Y17, M4K_X19_Y21
std_1c20:inst|cpu:the_cpu|cpu_ic_tag_module:cpu_ic_tag|altsyncram:the_altsyncram|altsyncram_09e1:auto_generated|ALTSYNCRAM | AUTO | Simple Dual Port | 128 | 22 | 128 | 22 | yes | no | yes | no | 2816 | 128 | 22 | 128 | 22 | 2816 | 1 | cpu_ic_tag_ram.mif | M4K_X19_Y20
std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|cpu_ociram_lpm_dram_bdp_component_module:cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_bp62:auto_generated|ALTSYNCRAM | AUTO | True Dual Port | 256 | 32 | 256 | 32 | yes | no | yes | no | 8192 | 256 | 32 | 256 | 32 | 8192 | 2 | cpu_ociram_default_contents.mif | M4K_X49_Y19, M4K_X49_Y18
std_1c20:inst|cpu:the_cpu|cpu_register_bank_a_module:cpu_register_bank_a|altsyncram:the_altsyncram|altsyncram_3vd1:auto_generated|ALTSYNCRAM | AUTO | Simple Dual Port | 32 | 32 | 32 | 32 | yes | no | yes | no | 1024 | 32 | 32 | 32 | 32 | 1024 | 1 | cpu_rf_ram_a.mif | M4K_X49_Y16
std_1c20:inst|cpu:the_cpu|cpu_register_bank_b_module:cpu_register_bank_b|altsyncram:the_altsyncram|altsyncram_4vd1:auto_generated|ALTSYNCRAM | AUTO | Simple Dual Port | 32 | 32 | 32 | 32 | yes | no | yes | no | 1024 | 32 | 32 | 32 | 32 | 1024 | 1 | cpu_rf_ram_b.mif | M4K_X49_Y15
std_1c20:inst|epcs_controller:the_epcs_controller|altsyncram:the_boot_copier_rom|altsyncram_3h31:auto_generated|ALTSYNCRAM | AUTO | ROM | 128 | 32 | -- | -- | yes | no | -- | -- | 4096 | 128 | 32 | -- | -- | 4096 | 1 | epcs_controller_boot_rom.hex | M4K_X49_Y23
std_1c20:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_r:the_jtag_uart_scfifo_r|scfifo:rfifo|scfifo_jf21:auto_generated|a_dpfifo_ml21:dpfifo|dpram_j921:FIFOram|altsyncram_nll1:altsyncram1|ALTSYNCRAM | AUTO | Simple Dual Port | 64 | 8 | 64 | 8 | yes | no | yes | no | 512 | 64 | 8 | 64 | 8 | 512 | 1 | None | M4K_X49_Y21
std_1c20:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_w:the_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_jf21:auto_generated|a_dpfifo_ml21:dpfifo|dpram_j921:FIFOram|altsyncram_nll1:altsyncram1|ALTSYNCRAM | AUTO | Simple Dual Port | 64 | 8 | 64 | 8 | yes | no | yes | no | 512 | 64 | 8 | 64 | 8 | 512 | 1 | None | M4K_X49_Y20

Note: Fitter may spread logical memories into multiple blocks to improve timing. The actual required RAM blocks can be found in the Fitter Resource Usage section.

## Interconnect Usage Summary

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Interconnect Resource Type | Usage
--- | ---
C4s | 5,362 / 48,240 ( 11 % )
Direct links | 824 / 69,520 ( 1 % )
Global clocks | 8 / 8 ( 100 % )
LAB clocks | 146 / 384 ( 38 % )
LUT chains | 413 / 18,054 ( 2 % )
Local interconnects | 8,591 / 69,520 ( 12 % )
M4K buffers | 230 / 2,304 ( 10 % )
R4s | 6,892 / 45,520 ( 15 % )

## LAB Logic Elements

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Number of Logic Elements (Average = 8.30) | Number of LABs (Total = 594)
--- | ---
1 | 22
2 | 20
3 | 19
4 | 15
5 | 18
6 | 24
7 | 19
8 | 51
9 | 84
10 | 322

## LAB-wide Signals

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LAB-wide Signals (Average = 2.33) | Number of LABs (Total = 594)
--- | ---
1 Async. clear | 467
1 Async. load | 2
1 Clock | 499
1 Clock enable | 204
1 Invert A | 4
1 Sync. clear | 10
1 Sync. load | 86
2 Async. clears | 24
2 Clock enables | 52
2 Clocks | 36

## LAB Signals Sourced

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Number of Signals Sourced (Average = 8.94) | Number of LABs (Total = 594)
--- | ---
0 | 4
1 | 17
2 | 18
3 | 22
4 | 16
5 | 18
6 | 19
7 | 12
8 | 36
9 | 66
10 | 223
11 | 71
12 | 32
13 | 21
14 | 9
15 | 4
16 | 3
17 | 1
18 | 0
19 | 0
20 | 2

## LAB Signals Sourced Out

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Number of Signals Sourced Out (Average = 5.85) | Number of LABs (Total = 594)
--- | ---
0 | 4
1 | 42
2 | 44
3 | 48
4 | 56
5 | 75
6 | 79
7 | 71
8 | 69
9 | 41
10 | 48
11 | 4
12 | 2
13 | 5
14 | 3
15 | 1
16 | 0
17 | 0
18 | 0
19 | 1
20 | 1

## LAB Distinct Inputs

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Number of Distinct Inputs (Average = 14.03) | Number of LABs (Total = 594)
--- | ---
0 | 0
1 | 1
2 | 4
3 | 12
4 | 11
5 | 31
6 | 17
7 | 20
8 | 24
9 | 22
10 | 25
11 | 28
12 | 34
13 | 31
14 | 30
15 | 46
16 | 29
17 | 26
18 | 36
19 | 33
20 | 53
21 | 46
22 | 35

## Fitter Device Options

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Option | Setting
--- | ---
Enable user-supplied start-up clock (CLKUSR) | Off
Enable device-wide reset (DEV_CLRn) | Off
Enable device-wide output enable (DEV_OE) | Off
Enable INIT_DONE output | Off
Configuration scheme | Active Serial
Error detection CRC | Off
Reserve all unused pins | As input tri-stated
Base pin-out file on sameframe device | Off

## Fitter Messages

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    Info: *******************************************************************
    Info: Running Quartus II Fitter
        Info: Version 6.0 Build 176 04/19/2006 SJ Full Version
        Info: Processing started: Fri Apr 21 03:01:16 2006
    Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off standard -c standard
    Info: Selected device EP1C20F400C7 for design "standard"
    Info: Implementing parameter values for PLL "std_1c20:inst|sdram_pll:the_sdram_pll|altpllsdram_pll:the_pll|altpll:altpll_component|pll"
        Info: Implementing clock multiplication of 1, clock division of 1, and phase shift of 0 degrees (0 ps) for std_1c20:inst|sdram_pll:the_sdram_pll|altpllsdram_pll:the_pll|altpll:altpll_component|_clk0 port
        Info: Implementing clock multiplication of 1, clock division of 1, and phase shift of -63 degrees (-3499 ps) for std_1c20:inst|sdram_pll:the_sdram_pll|altpllsdram_pll:the_pll|altpll:altpll_component|_extclk0 port
    Info: Implementing parameter values for PLL "std_1c20:inst|connector_pll:the_connector_pll|altpllconnector_pll:the_pll|altpll:altpll_component|pll"
        Info: Implementing clock multiplication of 1, clock division of 1, and phase shift of 0 degrees (0 ps) for std_1c20:inst|connector_pll:the_connector_pll|altpllconnector_pll:the_pll|altpll:altpll_component|_extclk0 port
    Critical Warning: Changed operation mode of PLL "std_1c20:inst|connector_pll:the_connector_pll|altpllconnector_pll:the_pll|altpll:altpll_component|pll" to Zero delay buffer
    Info: Fitter is performing a Standard Fit compilation using maximum Fitter effort to optimize design performance
    Info: Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices
        Info: Device EP1C4F400C7 is compatible
        Info: Device EP1C4F400I7 is compatible
        Info: Device EP1C20F400I7 is compatible
    Info: Detected fmax, tsu, tco, and/or tpd requirements -- optimizing circuit to achieve only the specified requirements
    Info: Completed User Assigned Global Signals Promotion Operation
    Info: DQS I/O pins require 0 global routing resources
    Info: Promoted PLL clock signals
        Info: Promoted signal "PLD_CLKFB" to use global clock
        Info: Promoted signal "std_1c20:inst|sdram_pll:the_sdram_pll|altpllsdram_pll:the_pll|altpll:altpll_component|_clk0" to use global clock (user assigned)
        Info: Promoted signal "PLD_CLOCKINPUT[1]" to use global clock
    Info: Completed PLL Placement Operation
    Info: Automatically promoted signal "altera_internal_jtag~TCKUTAP" to use Global clock
    Info: Automatically promoted signal "altera_internal_jtag~UPDATEUSER" to use Global clock
    Info: Automatically promoted some destinations of signal "std_1c20:inst|std_1c20_reset_sysclk2_domain_synch_module:std_1c20_reset_sysclk2_domain_synch|data_out" to use Global clock
        Info: Destination "std_1c20:inst|sdram:the_sdram|active_addr[9]" may be non-global or may not use global clock
        Info: Destination "std_1c20:inst|sdram:the_sdram|active_addr[14]" may be non-global or may not use global clock
        Info: Destination "std_1c20:inst|sdram:the_sdram|active_addr[13]" may be non-global or may not use global clock
        Info: Destination "std_1c20:inst|sdram:the_sdram|active_addr[11]" may be non-global or may not use global clock
        Info: Destination "std_1c20:inst|sdram:the_sdram|active_addr[16]" may be non-global or may not use global clock
        Info: Destination "std_1c20:inst|sdram:the_sdram|active_addr[15]" may be non-global or may not use global clock
        Info: Destination "std_1c20:inst|sdram:the_sdram|active_addr[17]" may be non-global or may not use global clock
        Info: Destination "std_1c20:inst|sdram:the_sdram|active_addr[10]" may be non-global or may not use global clock
        Info: Destination "std_1c20:inst|sdram:the_sdram|active_addr[20]" may be non-global or may not use global clock
        Info: Destination "std_1c20:inst|sdram:the_sdram|active_addr[18]" may be non-global or may not use global clock
        Info: Limited to 10 non-global destinations
    Info: Automatically promoted some destinations of signal "sld_hub:sld_hub_inst|CLR_SIGNAL" to use Global clock
        Info: Destination "std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|ir[0]~0" may be non-global or may not use global clock
        Info: Destination "std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_debug:the_cpu_nios2_oci_debug|internal_resetlatch~185" may be non-global or may not use global clock
    Info: Automatically promoted signal "std_1c20:inst|std_1c20_reset_PLD_CLKFB_domain_synch_module:std_1c20_reset_PLD_CLKFB_domain_synch|data_out" to use Global clock
    Info: Completed Auto Global Promotion Operation
    Info: Starting register packing
    Info: Ignoring invalid fast I/O register assignments
    Info: Fitter is using Normal packing mode for logic elements with Auto setting for Auto Packed Registers logic option
    Info: Finished moving registers into I/O cells, LUTs, and RAM blocks
    Info: Finished register packing: elapsed time is 00:00:07
    Info: Starting physical synthesis optimizations
    Info: Starting physical synthesis algorithm register retiming
    Info: Physical synthesis algorithm register retiming complete: estimated performance improvement of up to 0 percent
    Info: Starting physical synthesis algorithm register retiming
    Info: Physical synthesis algorithm register retiming complete: estimated performance improvement of up to 0 percent
    Info: Starting physical synthesis algorithm combinational resynthesis 1
    Info: Physical synthesis algorithm combinational resynthesis 1 complete: estimated performance improvement of up to 0 percent
    Info: Starting physical synthesis algorithm register retiming
    Info: Physical synthesis algorithm register retiming complete: estimated performance improvement of up to 0 percent
    Info: Starting physical synthesis algorithm register retiming
    Info: Physical synthesis algorithm register retiming complete: estimated performance improvement of up to 0 percent
    Info: Starting physical synthesis algorithm combinational resynthesis 1
    Info: Physical synthesis algorithm combinational resynthesis 1 complete: estimated performance improvement of up to 0 percent
    Info: Starting physical synthesis algorithm logic and register replication
    Info: Physical synthesis algorithm logic and register replication complete: estimated performance improvement of up to 0 percent
    Info: Physical synthesis optimizations complete: elapsed time is 00:08:07
    Info: Design uses memory blocks. Violating setup or hold times of memory block address registers could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements.
    Warning: Ignored locations or region assignments to the following nodes
        Warning: Node "CTS[1]" is assigned to location or region, but does not exist in design
        Warning: Node "DCD[1]" is assigned to location or region, but does not exist in design
        Warning: Node "DSR[1]" is assigned to location or region, but does not exist in design
        Warning: Node "DTR[1]" is assigned to location or region, but does not exist in design
        Warning: Node "ENET_CYCLE_N" is assigned to location or region, but does not exist in design
        Warning: Node "ENET_DATACS_N" is assigned to location or region, but does not exist in design
        Warning: Node "ENET_LCLK" is assigned to location or region, but does not exist in design
        Warning: Node "ENET_LDEV_N" is assigned to location or region, but does not exist in design
        Warning: Node "ENET_RDYRTN_N" is assigned to location or region, but does not exist in design
        Warning: Node "ENET_SRDY_N" is assigned to location or region, but does not exist in design
        Warning: Node "ENET_W_R_N" is assigned to location or region, but does not exist in design
        Warning: Node "FLASH_RY_BY_N" is assigned to location or region, but does not exist in design
        Warning: Node "INIT_DONE" is assigned to location or region, but does not exist in design
        Warning: Node "PLD_ASDO" is assigned to location or region, but does not exist in design
        Warning: Node "PLD_CE_N" is assigned to location or region, but does not exist in design
        Warning: Node "PLD_CS_N" is assigned to location or region, but does not exist in design
        Warning: Node "PLD_DATA[0]" is assigned to location or region, but does not exist in design
        Warning: Node "PLD_MSEL[0]" is assigned to location or region, but does not exist in design
        Warning: Node "PLD_MSEL[1]" is assigned to location or region, but does not exist in design
        Warning: Node "PROTO1_CLKOUT" is assigned to location or region, but does not exist in design
        Warning: Node "PROTO1_IO[16]" is assigned to location or region, but does not exist in design
        Warning: Node "PROTO1_IO[19]" is assigned to location or region, but does not exist in design
        Warning: Node "PROTO1_IO[22]" is assigned to location or region, but does not exist in design
        Warning: Node "PROTO1_IO[23]" is assigned to location or region, but does not exist in design
        Warning: Node "PROTO1_IO[28]" is assigned to location or region, but does not exist in design
        Warning: Node "PROTO1_IO[40]" is assigned to location or region, but does not exist in design
        Warning: Node "PROTO2_CARDSEL_N" is assigned to location or region, but does not exist in design
        Warning: Node "PROTO2_CLKOUT" is assigned to location or region, but does not exist in design
        Warning: Node "PROTO2_IO[0]" is assigned to location or region, but does not exist in design
        Warning: Node "PROTO2_IO[10]" is assigned to location or region, but does not exist in design
        Warning: Node "PROTO2_IO[11]" is assigned to location or region, but does not exist in design
        Warning: Node "PROTO2_IO[12]" is assigned to location or region, but does not exist in design
        Warning: Node "PROTO2_IO[13]" is assigned to location or region, but does not exist in design
        Warning: Node "PROTO2_IO[14]" is assigned to location or region, but does not exist in design
        Warning: Node "PROTO2_IO[15]" is assigned to location or region, but does not exist in design
        Warning: Node "PROTO2_IO[16]" is assigned to location or region, but does not exist in design
        Warning: Node "PROTO2_IO[17]" is assigned to location or region, but does not exist in design
        Warning: Node "PROTO2_IO[18]" is assigned to location or region, but does not exist in design
        Warning: Node "PROTO2_IO[19]" is assigned to location or region, but does not exist in design
        Warning: Node "PROTO2_IO[1]" is assigned to location or region, but does not exist in design
        Warning: Node "PROTO2_IO[20]" is assigned to location or region, but does not exist in design
        Warning: Node "PROTO2_IO[21]" is assigned to location or region, but does not exist in design
        Warning: Node "PROTO2_IO[22]" is assigned to location or region, but does not exist in design
        Warning: Node "PROTO2_IO[23]" is assigned to location or region, but does not exist in design
        Warning: Node "PROTO2_IO[24]" is assigned to location or region, but does not exist in design
        Warning: Node "PROTO2_IO[25]" is assigned to location or region, but does not exist in design
        Warning: Node "PROTO2_IO[26]" is assigned to location or region, but does not exist in design
        Warning: Node "PROTO2_IO[27]" is assigned to location or region, but does not exist in design
        Warning: Node "PROTO2_IO[28]" is assigned to location or region, but does not exist in design
        Warning: Node "PROTO2_IO[29]" is assigned to location or region, but does not exist in design
        Warning: Node "PROTO2_IO[2]" is assigned to location or region, but does not exist in design
        Warning: Node "PROTO2_IO[30]" is assigned to location or region, but does not exist in design
        Warning: Node "PROTO2_IO[31]" is assigned to location or region, but does not exist in design
        Warning: Node "PROTO2_IO[32]" is assigned to location or region, but does not exist in design
        Warning: Node "PROTO2_IO[33]" is assigned to location or region, but does not exist in design
        Warning: Node "PROTO2_IO[34]" is assigned to location or region, but does not exist in design
        Warning: Node "PROTO2_IO[35]" is assigned to location or region, but does not exist in design
        Warning: Node "PROTO2_IO[36]" is assigned to location or region, but does not exist in design
        Warning: Node "PROTO2_IO[37]" is assigned to location or region, but does not exist in design
        Warning: Node "PROTO2_IO[38]" is assigned to location or region, but does not exist in design
        Warning: Node "PROTO2_IO[39]" is assigned to location or region, but does not exist in design
        Warning: Node "PROTO2_IO[3]" is assigned to location or region, but does not exist in design
        Warning: Node "PROTO2_IO[40]" is assigned to location or region, but does not exist in design
        Warning: Node "PROTO2_IO[4]" is assigned to location or region, but does not exist in design
        Warning: Node "PROTO2_IO[5]" is assigned to location or region, but does not exist in design
        Warning: Node "PROTO2_IO[6]" is assigned to location or region, but does not exist in design
        Warning: Node "PROTO2_IO[7]" is assigned to location or region, but does not exist in design
        Warning: Node "PROTO2_IO[8]" is assigned to location or region, but does not exist in design
        Warning: Node "PROTO2_IO[9]" is assigned to location or region, but does not exist in design
        Warning: Node "RI[1]" is assigned to location or region, but does not exist in design
        Warning: Node "RTS[1]" is assigned to location or region, but does not exist in design
        Warning: Node "TR_DEBUGACK" is assigned to location or region, but does not exist in design
        Warning: Node "TR_DEBUGREQ" is assigned to location or region, but does not exist in design
        Warning: Node "ardy_from_the_lan91c111" is assigned to location or region, but does not exist in design
        Warning: Node "cf_addr[0]" is assigned to location or region, but does not exist in design
        Warning: Node "cf_addr[10]" is assigned to location or region, but does not exist in design
        Warning: Node "cf_addr[1]" is assigned to location or region, but does not exist in design
        Warning: Node "cf_addr[2]" is assigned to location or region, but does not exist in design
        Warning: Node "cf_addr[3]" is assigned to location or region, but does not exist in design
        Warning: Node "cf_addr[4]" is assigned to location or region, but does not exist in design
        Warning: Node "cf_addr[5]" is assigned to location or region, but does not exist in design
        Warning: Node "cf_addr[6]" is assigned to location or region, but does not exist in design
        Warning: Node "cf_addr[7]" is assigned to location or region, but does not exist in design
        Warning: Node "cf_addr[8]" is assigned to location or region, but does not exist in design
        Warning: Node "cf_addr[9]" is assigned to location or region, but does not exist in design
        Warning: Node "cf_atasel" is assigned to location or region, but does not exist in design
        Warning: Node "cf_cs_n[0]" is assigned to location or region, but does not exist in design
        Warning: Node "cf_cs_n[1]" is assigned to location or region, but does not exist in design
        Warning: Node "cf_data[0]" is assigned to location or region, but does not exist in design
        Warning: Node "cf_data[10]" is assigned to location or region, but does not exist in design
        Warning: Node "cf_data[11]" is assigned to location or region, but does not exist in design
        Warning: Node "cf_data[12]" is assigned to location or region, but does not exist in design
        Warning: Node "cf_data[13]" is assigned to location or region, but does not exist in design
        Warning: Node "cf_data[14]" is assigned to location or region, but does not exist in design
        Warning: Node "cf_data[15]" is assigned to location or region, but does not exist in design
        Warning: Node "cf_data[1]" is assigned to location or region, but does not exist in design
        Warning: Node "cf_data[2]" is assigned to location or region, but does not exist in design
        Warning: Node "cf_data[3]" is assigned to location or region, but does not exist in design
        Warning: Node "cf_data[4]" is assigned to location or region, but does not exist in design
        Warning: Node "cf_data[5]" is assigned to location or region, but does not exist in design
        Warning: Node "cf_data[6]" is assigned to location or region, but does not exist in design
        Warning: Node "cf_data[7]" is assigned to location or region, but does not exist in design
        Warning: Node "cf_data[8]" is assigned to location or region, but does not exist in design
        Warning: Node "cf_data[9]" is assigned to location or region, but does not exist in design
        Warning: Node "cf_detect" is assigned to location or region, but does not exist in design
        Warning: Node "cf_intrq" is assigned to location or region, but does not exist in design
        Warning: Node "cf_iord_n" is assigned to location or region, but does not exist in design
        Warning: Node "cf_iordy" is assigned to location or region, but does not exist in design
        Warning: Node "cf_iowr_n" is assigned to location or region, but does not exist in design
        Warning: Node "cf_power" is assigned to location or region, but does not exist in design
        Warning: Node "cf_rfu" is assigned to location or region, but does not exist in design
        Warning: Node "cf_we_n" is assigned to location or region, but does not exist in design
        Warning: Node "jtag_debug_offchip_trace_clk_from_the_cpu" is assigned to location or region, but does not exist in design
        Warning: Node "jtag_debug_offchip_trace_data_from_the_cpu[0]" is assigned to location or region, but does not exist in design
        Warning: Node "jtag_debug_offchip_trace_data_from_the_cpu[10]" is assigned to location or region, but does not exist in design
        Warning: Node "jtag_debug_offchip_trace_data_from_the_cpu[11]" is assigned to location or region, but does not exist in design
        Warning: Node "jtag_debug_offchip_trace_data_from_the_cpu[12]" is assigned to location or region, but does not exist in design
        Warning: Node "jtag_debug_offchip_trace_data_from_the_cpu[13]" is assigned to location or region, but does not exist in design
        Warning: Node "jtag_debug_offchip_trace_data_from_the_cpu[14]" is assigned to location or region, but does not exist in design
        Warning: Node "jtag_debug_offchip_trace_data_from_the_cpu[15]" is assigned to location or region, but does not exist in design
        Warning: Node "jtag_debug_offchip_trace_data_from_the_cpu[16]" is assigned to location or region, but does not exist in design
        Warning: Node "jtag_debug_offchip_trace_data_from_the_cpu[17]" is assigned to location or region, but does not exist in design
        Warning: Node "jtag_debug_offchip_trace_data_from_the_cpu[1]" is assigned to location or region, but does not exist in design
        Warning: Node "jtag_debug_offchip_trace_data_from_the_cpu[2]" is assigned to location or region, but does not exist in design
        Warning: Node "jtag_debug_offchip_trace_data_from_the_cpu[3]" is assigned to location or region, but does not exist in design
        Warning: Node "jtag_debug_offchip_trace_data_from_the_cpu[4]" is assigned to location or region, but does not exist in design
        Warning: Node "jtag_debug_offchip_trace_data_from_the_cpu[5]" is assigned to location or region, but does not exist in design
        Warning: Node "jtag_debug_offchip_trace_data_from_the_cpu[6]" is assigned to location or region, but does not exist in design
        Warning: Node "jtag_debug_offchip_trace_data_from_the_cpu[7]" is assigned to location or region, but does not exist in design
        Warning: Node "jtag_debug_offchip_trace_data_from_the_cpu[8]" is assigned to location or region, but does not exist in design
        Warning: Node "jtag_debug_offchip_trace_data_from_the_cpu[9]" is assigned to location or region, but does not exist in design
        Warning: Node "jtag_debug_trigout_from_the_cpu" is assigned to location or region, but does not exist in design
        Warning: Node "rxd_to_the_uart2" is assigned to location or region, but does not exist in design
        Warning: Node "txd_from_the_uart2" is assigned to location or region, but does not exist in design
    Info: Fitter placement preparation operations beginning
    Info: Fitter placement preparation operations ending: elapsed time is 00:01:11
    Info: Fitter placement operations beginning
    Info: Starting physical synthesis optimizations
    Info: Starting physical synthesis algorithm register retiming
    Info: Physical synthesis algorithm register retiming complete: estimated performance improvement of up to 0 percent
    Info: Starting physical synthesis algorithm combinational resynthesis 2
    Info: Physical synthesis algorithm combinational resynthesis 2 complete: estimated performance improvement of up to 0 percent
    Info: Starting physical synthesis algorithm logic and register replication
    Info: Physical synthesis algorithm logic and register replication complete: estimated performance improvement of up to 0 percent
    Info: Starting physical synthesis algorithm register unpacking
    Info: Physical synthesis algorithm register unpacking complete: estimated performance improvement of up to 0 percent
    Info: Starting physical synthesis algorithm combinational resynthesis 1
    Info: Physical synthesis algorithm combinational resynthesis 1 complete: estimated performance improvement of up to 0 percent
    Info: Starting physical synthesis algorithm combinational resynthesis 2
    Info: Physical synthesis algorithm combinational resynthesis 2 complete: estimated performance improvement of up to 0 percent
    Info: Starting physical synthesis algorithm RESPLIT
    Info: Physical synthesis algorithm RESPLIT complete: estimated performance improvement of up to 0 percent
    Info: Physical synthesis optimizations complete: elapsed time is 00:08:39
    Info: Fitter placement was successful
    Info: Fitter placement operations ending: elapsed time is 00:11:06
    Info: Estimated most critical path is register to register delay of 12.108 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X32_Y20; Fanout = 3; REG Node = 'std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|last_cycle_cpu_data_master_granted_slave_ext_ram_s1~12'
        Info: 2: + IC(0.597 ns) + CELL(0.258 ns) = 0.855 ns; Loc. = LAB_X31_Y20; Fanout = 2; COMB Node = 'std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|cpu_data_master_continuerequest~3'
        Info: 3: + IC(0.691 ns) + CELL(0.522 ns) = 2.068 ns; Loc. = LAB_X30_Y23; Fanout = 4; COMB Node = 'std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|cpu_data_master_continuerequest~103'
        Info: 4: + IC(0.319 ns) + CELL(0.258 ns) = 2.645 ns; Loc. = LAB_X30_Y23; Fanout = 17; COMB Node = 'std_1c20:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|internal_cpu_instruction_master_dbs_address[1]~49'
        Info: 5: + IC(0.469 ns) + CELL(0.382 ns) = 3.496 ns; Loc. = LAB_X30_Y23; Fanout = 2; COMB Node = 'std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|Add2~319COUT1_727'
        Info: 6: + IC(0.000 ns) + CELL(0.071 ns) = 3.567 ns; Loc. = LAB_X30_Y23; Fanout = 2; COMB Node = 'std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|Add2~315COUT1_729'
        Info: 7: + IC(0.000 ns) + CELL(0.071 ns) = 3.638 ns; Loc. = LAB_X30_Y23; Fanout = 2; COMB Node = 'std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|Add2~323COUT1_731'
        Info: 8: + IC(0.000 ns) + CELL(0.228 ns) = 3.866 ns; Loc. = LAB_X30_Y23; Fanout = 6; COMB Node = 'std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|Add2~327'
        Info: 9: + IC(0.000 ns) + CELL(0.601 ns) = 4.467 ns; Loc. = LAB_X30_Y22; Fanout = 6; COMB Node = 'std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|Add2~324'
        Info: 10: + IC(0.928 ns) + CELL(0.258 ns) = 5.653 ns; Loc. = LAB_X31_Y23; Fanout = 6; COMB Node = 'std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_avalon_slave_saved_chosen_master_vector[4]~_DUP_COMB'
        Info: 11: + IC(0.055 ns) + CELL(0.522 ns) = 6.230 ns; Loc. = LAB_X31_Y23; Fanout = 1; COMB Node = 'std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|select_n_to_the_ext_ram~COMB_OUT'
        Info: 12: + IC(5.701 ns) + CELL(0.177 ns) = 12.108 ns; Loc. = IOC_X68_Y0_N0; Fanout = 1; REG Node = 'std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|select_n_to_the_ext_ram'
        Info: Total cell delay = 3.348 ns ( 27.65 % )
        Info: Total interconnect delay = 8.760 ns ( 72.35 % )
    Info: Fitter routing operations beginning
    Info: Average interconnect usage is 12% of the available device resources. Peak interconnect usage is 43%
        Info: The peak interconnect region extends from location x35_y11 to location x45_y21
    Info: Fitter routing operations ending: elapsed time is 00:00:39
    Info: Completed Fixed Delay Chain Operation
    Info: Started post-fitting delay annotation
    Info: Delay annotation completed successfully
    Info: Completed Auto Delay Chain Operation
    Info: Design uses memory blocks. Violating setup or hold times of memory block address registers could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements.
    Info: Node std_1c20:inst|std_1c20_reset_sysclk2_domain_synch_module:std_1c20_reset_sysclk2_domain_synch|data_out uses non-global routing resources to route signals to global destination nodes
        Info: Port clear -- assigned as a global for destination node std_1c20:inst|clock_0:the_clock_0|clock_0_slave_FSM:slave_FSM|internal_slave_read_request -- routed using non-global resources
        Info: Port clear -- assigned as a global for destination node std_1c20:inst|clock_0:the_clock_0|clock_0_slave_FSM:slave_FSM|internal_slave_write_request -- routed using non-global resources
        Info: Port clear -- assigned as a global for destination node std_1c20:inst|clock_0:the_clock_0|clock_0_slave_FSM:slave_FSM|slave_state[2] -- routed using non-global resources
        Info: Port clear -- assigned as a global for destination node std_1c20:inst|clock_0:the_clock_0|slave_writedata_d1[13] -- routed using non-global resources
        Info: Port clear -- assigned as a global for destination node std_1c20:inst|clock_0:the_clock_0|slave_nativeaddress_d1[0] -- routed using non-global resources
        Info: Port clear -- assigned as a global for destination node std_1c20:inst|clock_0:the_clock_0|slave_nativeaddress_d1[2] -- routed using non-global resources
        Info: Port clear -- assigned as a global for destination node std_1c20:inst|clock_0:the_clock_0|clock_0_master_write_done_sync_module:clock_0_master_write_done_sync|data_in_d1 -- routed using non-global resources
        Info: Port clear -- assigned as a global for destination node std_1c20:inst|clock_0:the_clock_0|slave_writedata_d1[0] -- routed using non-global resources
        Info: Port clear -- assigned as a global for destination node std_1c20:inst|clock_0:the_clock_0|slave_writedata_d1[11] -- routed using non-global resources
        Info: Port clear -- assigned as a global for destination node std_1c20:inst|clock_1:the_clock_1|slave_writedata_d1[11] -- routed using non-global resources
        Info: Port clear -- assigned as a global for destination node std_1c20:inst|clock_0:the_clock_0|slave_writedata_d1[5] -- routed using non-global resources
        Info: Port clear -- assigned as a global for destination node std_1c20:inst|clock_0:the_clock_0|slave_writedata_d1[1] -- routed using non-global resources
        Info: Port clear -- assigned as a global for destination node std_1c20:inst|clock_1:the_clock_1|slave_writedata_d1[1] -- routed using non-global resources
        Info: Port clear -- assigned as a global for destination node std_1c20:inst|cpu:the_cpu|latched_oci_tb_hbreak_req -- routed using non-global resources
        Info: Port clear -- assigned as a global for destination node std_1c20:inst|cpu:the_cpu|wait_for_one_post_bret_inst -- routed using non-global resources
        Info: Port clear -- assigned as a global for destination node std_1c20:inst|clock_0:the_clock_0|slave_readdata[1] -- routed using non-global resources
        Info: Port clear -- assigned as a global for destination node std_1c20:inst|clock_0:the_clock_0|clock_0_master_read_done_sync_module:clock_0_master_read_done_sync|data_in_d1 -- routed using non-global resources
        Info: Port clear -- assigned as a global for destination node std_1c20:inst|clock_0:the_clock_0|slave_writedata_d1[10] -- routed using non-global resources
        Info: Port clear -- assigned as a global for destination node std_1c20:inst|clock_0:the_clock_0|slave_writedata_d1[12] -- routed using non-global resources
        Info: Port clear -- assigned as a global for destination node std_1c20:inst|clock_1:the_clock_1|slave_writedata_d1[12] -- routed using non-global resources
        Info: Port clear -- assigned as a global for destination node std_1c20:inst|clock_0:the_clock_0|slave_readdata[14] -- routed using non-global resources
        Info: Port clear -- assigned as a global for destination node std_1c20:inst|clock_1:the_clock_1|slave_readdata[6] -- routed using non-global resources
        Info: Port clear -- assigned as a global for destination node std_1c20:inst|clock_0:the_clock_0|slave_readdata[7] -- routed using non-global resources
        Info: Port clear -- assigned as a global for destination node std_1c20:inst|clock_0:the_clock_0|slave_readdata[6] -- routed using non-global resources
        Info: Port clear -- assigned as a global for destination node std_1c20:inst|clock_1:the_clock_1|slave_readdata[0] -- routed using non-global resources
        Info: Port clear -- assigned as a global for destination node std_1c20:inst|clock_1:the_clock_1|slave_readdata[7] -- routed using non-global resources
        Info: Port clear -- assigned as a global for destination node std_1c20:inst|clock_0:the_clock_0|slave_readdata[0] -- routed using non-global resources
        Info: Port clear -- assigned as a global for destination node std_1c20:inst|clock_1:the_clock_1|slave_readdata[14] -- routed using non-global resources
        Info: Port clear -- assigned as a global for destination node std_1c20:inst|clock_0:the_clock_0|slave_writedata_d1[3] -- routed using non-global resources
        Info: Port clear -- assigned as a global for destination node std_1c20:inst|clock_1:the_clock_1|slave_writedata_d1[3] -- routed using non-global resources
        Info: Port clear -- assigned as a global for destination node std_1c20:inst|cpu:the_cpu|i_readdata_d1[1]~161 -- routed using non-global resources
        Info: Port clear -- assigned as a global for destination node std_1c20:inst|cpu:the_cpu|i_readdata_d1[1]~163 -- routed using non-global resources
        Info: Port clear -- assigned as a global for destination node std_1c20:inst|cpu:the_cpu|i_readdata_d1[2]~167 -- routed using non-global resources
        Info: Port clear -- assigned as a global for destination node std_1c20:inst|cpu:the_cpu|i_readdata_d1[0]~164 -- routed using non-global resources
        Info: Port clear -- assigned as a global for destination node std_1c20:inst|cpu:the_cpu|i_readdata_d1[1]~162 -- routed using non-global resources
        Info: Port clear -- assigned as a global for destination node std_1c20:inst|cpu:the_cpu|i_readdata_d1[2]~166 -- routed using non-global resources
        Info: Port clear -- assigned as a global for destination node std_1c20:inst|clock_0:the_clock_0|slave_writedata_d1[7] -- routed using non-global resources
        Info: Port clear -- assigned as a global for destination node std_1c20:inst|clock_1:the_clock_1|slave_writedata_d1[7] -- routed using non-global resources
        Info: Port clear -- assigned as a global for destination node std_1c20:inst|clock_0:the_clock_0|slave_writedata_d1[8] -- routed using non-global resources
        Info: Port clear -- assigned as a global for destination node std_1c20:inst|clock_1:the_clock_1|slave_writedata_d1[8] -- routed using non-global resources
        Info: Port clear -- assigned as a global for destination node std_1c20:inst|clock_1:the_clock_1|slave_writedata_d1[2] -- routed using non-global resources
        Info: Port clear -- assigned as a global for destination node std_1c20:inst|clock_0:the_clock_0|slave_writedata_d1[2] -- routed using non-global resources
        Info: Port clear -- assigned as a global for destination node std_1c20:inst|jtag_uart:the_jtag_uart|alt_jtag_atlantic:jtag_uart_alt_jtag_atlantic|rvalid -- routed using non-global resources
        Info: Port clear -- assigned as a global for destination node std_1c20:inst|jtag_uart:the_jtag_uart|t_dav -- routed using non-global resources
        Info: Port clear -- assigned as a global for destination node std_1c20:inst|jtag_uart:the_jtag_uart|alt_jtag_atlantic:jtag_uart_alt_jtag_atlantic|read_write2 -- routed using non-global resources
        Info: Port clear -- assigned as a global for destination node std_1c20:inst|jtag_uart:the_jtag_uart|alt_jtag_atlantic:jtag_uart_alt_jtag_atlantic|jupdate1 -- routed using non-global resources
        Info: Port clear -- assigned as a global for destination node std_1c20:inst|jtag_uart:the_jtag_uart|alt_jtag_atlantic:jtag_uart_alt_jtag_atlantic|jupdate2 -- routed using non-global resources
        Info: Port clear -- assigned as a global for destination node std_1c20:inst|jtag_uart:the_jtag_uart|alt_jtag_atlantic:jtag_uart_alt_jtag_atlantic|t_pause~reg0 -- routed using non-global resources
        Info: Port clear -- assigned as a global for destination node std_1c20:inst|jtag_uart:the_jtag_uart|alt_jtag_atlantic:jtag_uart_alt_jtag_atlantic|read_write1 -- routed using non-global resources
        Info: Port clear -- assigned as a global for destination node std_1c20:inst|jtag_uart:the_jtag_uart|alt_jtag_atlantic:jtag_uart_alt_jtag_atlantic|t_ena~reg0 -- routed using non-global resources
        Info: Total of 61 global destination nodes routed using non-global resources -- displayed first 50
    Warning: Following 3 pins have nothing, GND, or VCC driving datain port -- changes to this connectivity may change fitting results
        Info: Pin ENET_ADS_N has GND driving its datain port
        Info: Pin ENET_AEN has GND driving its datain port
        Info: Pin zs_cke_from_the_sdram has VCC driving its datain port
    Info: Following groups of pins have the same output enable
        Info: Following pins have the same output enable: std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_in_a_write_cycle~COMB_OUT
            Info: Type bidirectional pin ext_ram_bus_data[31] uses the LVTTL I/O standard
            Info: Type bidirectional pin ext_ram_bus_data[8] uses the LVTTL I/O standard
            Info: Type bidirectional pin ext_ram_bus_data[17] uses the LVTTL I/O standard
            Info: Type bidirectional pin ext_ram_bus_data[26] uses the LVTTL I/O standard
            Info: Type bidirectional pin ext_ram_bus_data[10] uses the LVTTL I/O standard
            Info: Type bidirectional pin ext_ram_bus_data[19] uses the LVTTL I/O standard
            Info: Type bidirectional pin ext_ram_bus_data[3] uses the LVTTL I/O standard
            Info: Type bidirectional pin ext_ram_bus_data[28] uses the LVTTL I/O standard
            Info: Type bidirectional pin ext_ram_bus_data[12] uses the LVTTL I/O standard
            Info: Type bidirectional pin ext_ram_bus_data[21] uses the LVTTL I/O standard
            Info: Type bidirectional pin ext_ram_bus_data[5] uses the LVTTL I/O standard
            Info: Type bidirectional pin ext_ram_bus_data[30] uses the LVTTL I/O standard
            Info: Type bidirectional pin ext_ram_bus_data[14] uses the LVTTL I/O standard
            Info: Type bidirectional pin ext_ram_bus_data[23] uses the LVTTL I/O standard
            Info: Type bidirectional pin ext_ram_bus_data[7] uses the LVTTL I/O standard
            Info: Type bidirectional pin ext_ram_bus_data[16] uses the LVTTL I/O standard
            Info: Type bidirectional pin ext_ram_bus_data[0] uses the LVTTL I/O standard
            Info: Type bidirectional pin ext_ram_bus_data[25] uses the LVTTL I/O standard
            Info: Type bidirectional pin ext_ram_bus_data[9] uses the LVTTL I/O standard
            Info: Type bidirectional pin ext_ram_bus_data[18] uses the LVTTL I/O standard
            Info: Type bidirectional pin ext_ram_bus_data[2] uses the LVTTL I/O standard
            Info: Type bidirectional pin ext_ram_bus_data[27] uses the LVTTL I/O standard
            Info: Type bidirectional pin ext_ram_bus_data[11] uses the LVTTL I/O standard
            Info: Type bidirectional pin ext_ram_bus_data[20] uses the LVTTL I/O standard
            Info: Type bidirectional pin ext_ram_bus_data[4] uses the LVTTL I/O standard
            Info: Type bidirectional pin ext_ram_bus_data[29] uses the LVTTL I/O standard
            Info: Type bidirectional pin ext_ram_bus_data[13] uses the LVTTL I/O standard
            Info: Type bidirectional pin ext_ram_bus_data[22] uses the LVTTL I/O standard
            Info: Type bidirectional pin ext_ram_bus_data[6] uses the LVTTL I/O standard
            Info: Type bidirectional pin ext_ram_bus_data[15] uses the LVTTL I/O standard
            Info: Type bidirectional pin ext_ram_bus_data[24] uses the LVTTL I/O standard
            Info: Type bidirectional pin ext_ram_bus_data[1] uses the LVTTL I/O standard
        Info: Following pins have the same output enable: std_1c20:inst|cpu:the_cpu|M_alu_result[2]~_DUP_REG (inverted)
            Info: Type bidirectional pin LCD_data_to_and_from_the_lcd_display[7] uses the LVTTL I/O standard
            Info: Type bidirectional pin LCD_data_to_and_from_the_lcd_display[2] uses the LVTTL I/O standard
            Info: Type bidirectional pin LCD_data_to_and_from_the_lcd_display[4] uses the LVTTL I/O standard
            Info: Type bidirectional pin LCD_data_to_and_from_the_lcd_display[6] uses the LVTTL I/O standard
            Info: Type bidirectional pin LCD_data_to_and_from_the_lcd_display[1] uses the LVTTL I/O standard
            Info: Type bidirectional pin LCD_data_to_and_from_the_lcd_display[3] uses the LVTTL I/O standard
            Info: Type bidirectional pin LCD_data_to_and_from_the_lcd_display[5] uses the LVTTL I/O standard
            Info: Type bidirectional pin LCD_data_to_and_from_the_lcd_display[0] uses the LVTTL I/O standard
        Info: Following pins have the same output enable: std_1c20:inst|sdram:the_sdram|oe
            Info: Type bidirectional pin zs_dq_to_and_from_the_sdram[7] uses the LVTTL I/O standard
            Info: Type bidirectional pin zs_dq_to_and_from_the_sdram[16] uses the LVTTL I/O standard
            Info: Type bidirectional pin zs_dq_to_and_from_the_sdram[25] uses the LVTTL I/O standard
            Info: Type bidirectional pin zs_dq_to_and_from_the_sdram[18] uses the LVTTL I/O standard
            Info: Type bidirectional pin zs_dq_to_and_from_the_sdram[2] uses the LVTTL I/O standard
            Info: Type bidirectional pin zs_dq_to_and_from_the_sdram[27] uses the LVTTL I/O standard
            Info: Type bidirectional pin zs_dq_to_and_from_the_sdram[11] uses the LVTTL I/O standard
            Info: Type bidirectional pin zs_dq_to_and_from_the_sdram[20] uses the LVTTL I/O standard
            Info: Type bidirectional pin zs_dq_to_and_from_the_sdram[4] uses the LVTTL I/O standard
            Info: Type bidirectional pin zs_dq_to_and_from_the_sdram[29] uses the LVTTL I/O standard
            Info: Type bidirectional pin zs_dq_to_and_from_the_sdram[13] uses the LVTTL I/O standard
            Info: Type bidirectional pin zs_dq_to_and_from_the_sdram[22] uses the LVTTL I/O standard
            Info: Type bidirectional pin zs_dq_to_and_from_the_sdram[6] uses the LVTTL I/O standard
            Info: Type bidirectional pin zs_dq_to_and_from_the_sdram[31] uses the LVTTL I/O standard
            Info: Type bidirectional pin zs_dq_to_and_from_the_sdram[15] uses the LVTTL I/O standard
            Info: Type bidirectional pin zs_dq_to_and_from_the_sdram[24] uses the LVTTL I/O standard
            Info: Type bidirectional pin zs_dq_to_and_from_the_sdram[8] uses the LVTTL I/O standard
            Info: Type bidirectional pin zs_dq_to_and_from_the_sdram[17] uses the LVTTL I/O standard
            Info: Type bidirectional pin zs_dq_to_and_from_the_sdram[1] uses the LVTTL I/O standard
            Info: Type bidirectional pin zs_dq_to_and_from_the_sdram[26] uses the LVTTL I/O standard
            Info: Type bidirectional pin zs_dq_to_and_from_the_sdram[10] uses the LVTTL I/O standard
            Info: Type bidirectional pin zs_dq_to_and_from_the_sdram[19] uses the LVTTL I/O standard
            Info: Type bidirectional pin zs_dq_to_and_from_the_sdram[3] uses the LVTTL I/O standard
            Info: Type bidirectional pin zs_dq_to_and_from_the_sdram[28] uses the LVTTL I/O standard
            Info: Type bidirectional pin zs_dq_to_and_from_the_sdram[12] uses the LVTTL I/O standard
            Info: Type bidirectional pin zs_dq_to_and_from_the_sdram[21] uses the LVTTL I/O standard
            Info: Type bidirectional pin zs_dq_to_and_from_the_sdram[5] uses the LVTTL I/O standard
            Info: Type bidirectional pin zs_dq_to_and_from_the_sdram[30] uses the LVTTL I/O standard
            Info: Type bidirectional pin zs_dq_to_and_from_the_sdram[14] uses the LVTTL I/O standard
            Info: Type bidirectional pin zs_dq_to_and_from_the_sdram[23] uses the LVTTL I/O standard
            Info: Type bidirectional pin zs_dq_to_and_from_the_sdram[0] uses the LVTTL I/O standard
            Info: Type bidirectional pin zs_dq_to_and_from_the_sdram[9] uses the LVTTL I/O standard
        Info: Following pins have the same output enable: std_1c20:inst|reconfig_request_pio:the_reconfig_request_pio|data_dir
            Info: Type bidirectional pin bidir_port_to_and_from_the_reconfig_request_pio uses the LVTTL I/O standard
    Info: Quartus II Fitter was successful. 0 errors, 137 warnings
        Info: Processing ended: Fri Apr 21 03:23:35 2006
        Info: Elapsed time: 00:22:19
    Info: Generated suppressed messages file /data/job/20060421/1014742/examples/vhdl/niosII_cyclone_1c20/standard/standard.fit.smsg

## Fitter Suppressed Messages

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Fitter Suppressed Messages

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