Version 6.0 Build 178 04/27/2006 SJ Web Edition
35
1776
OFF
OFF
OFF
OFF
OFF
FV_OFF
Level2
0
0
VRSM_ON
VHSM_ON
0
-- Start Partition --
-- End Partition --
-- Start Library Paths --
-- End Library Paths --
-- Start VHDL Libraries --
-- End VHDL Libraries --
# entity
standard
# storage
db|standard.(0).cnf
db|standard.(0).cnf
# case_insensitive
# source_file
standard.bdf
7b9ab83f0122e989029fe6c166e5180
24
# hierarchies {
|
}
# end
# entity
button_pio
# storage
db|standard.(3).cnf
db|standard.(3).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
button_pio.vhd
efdd556d5c272f6579ffa1721764ce
4
# internal_option {
AUTO_RESOURCE_SHARING
OFF
}
# user_parameter {
 constraint(address)
1 downto 0
PARAMETER_STRING
USR
 constraint(in_port)
3 downto 0
PARAMETER_STRING
USR
 constraint(writedata)
3 downto 0
PARAMETER_STRING
USR
 constraint(readdata)
3 downto 0
PARAMETER_STRING
USR
}
# hierarchies {
std_1c20:inst|button_pio:the_button_pio
}
# end
# entity
clock_0
# storage
db|standard.(6).cnf
db|standard.(6).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
clock_0.vhd
dbe1e6a05ee6fa3e0d157e96a5e49fd
4
# internal_option {
AUTO_RESOURCE_SHARING
OFF
}
# user_parameter {
 constraint(master_readdata)
15 downto 0
PARAMETER_STRING
USR
 constraint(slave_address)
3 downto 0
PARAMETER_STRING
USR
 constraint(slave_byteenable)
1 downto 0
PARAMETER_STRING
USR
 constraint(slave_nativeaddress)
2 downto 0
PARAMETER_STRING
USR
 constraint(slave_writedata)
15 downto 0
PARAMETER_STRING
USR
 constraint(master_address)
3 downto 0
PARAMETER_STRING
USR
 constraint(master_byteenable)
1 downto 0
PARAMETER_STRING
USR
 constraint(master_nativeaddress)
2 downto 0
PARAMETER_STRING
USR
 constraint(master_writedata)
15 downto 0
PARAMETER_STRING
USR
 constraint(slave_readdata)
15 downto 0
PARAMETER_STRING
USR
}
# hierarchies {
std_1c20:inst|clock_0:the_clock_0
}
# end
# entity
clock_0_master_read_done_sync_module
# storage
db|standard.(7).cnf
db|standard.(7).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
clock_0.vhd
dbe1e6a05ee6fa3e0d157e96a5e49fd
4
# internal_option {
AUTO_RESOURCE_SHARING
OFF
}
# hierarchies {
std_1c20:inst|clock_0:the_clock_0|clock_0_master_read_done_sync_module:clock_0_master_read_done_sync
}
# end
# entity
clock_0_master_write_done_sync_module
# storage
db|standard.(8).cnf
db|standard.(8).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
clock_0.vhd
dbe1e6a05ee6fa3e0d157e96a5e49fd
4
# internal_option {
AUTO_RESOURCE_SHARING
OFF
}
# hierarchies {
std_1c20:inst|clock_0:the_clock_0|clock_0_master_write_done_sync_module:clock_0_master_write_done_sync
}
# end
# entity
clock_0_edge_to_pulse
# storage
db|standard.(9).cnf
db|standard.(9).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
clock_0.vhd
dbe1e6a05ee6fa3e0d157e96a5e49fd
4
# internal_option {
AUTO_RESOURCE_SHARING
OFF
}
# hierarchies {
std_1c20:inst|clock_0:the_clock_0|clock_0_edge_to_pulse:read_done_edge_to_pulse
std_1c20:inst|clock_0:the_clock_0|clock_0_edge_to_pulse:write_done_edge_to_pulse
std_1c20:inst|clock_0:the_clock_0|clock_0_edge_to_pulse:read_request_edge_to_pulse
std_1c20:inst|clock_0:the_clock_0|clock_0_edge_to_pulse:write_request_edge_to_pulse
}
# end
# entity
clock_0_slave_FSM
# storage
db|standard.(10).cnf
db|standard.(10).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
clock_0.vhd
dbe1e6a05ee6fa3e0d157e96a5e49fd
4
# internal_option {
AUTO_RESOURCE_SHARING
OFF
}
# hierarchies {
std_1c20:inst|clock_0:the_clock_0|clock_0_slave_FSM:slave_FSM
}
# end
# entity
clock_0_slave_read_request_sync_module
# storage
db|standard.(11).cnf
db|standard.(11).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
clock_0.vhd
dbe1e6a05ee6fa3e0d157e96a5e49fd
4
# internal_option {
AUTO_RESOURCE_SHARING
OFF
}
# hierarchies {
std_1c20:inst|clock_0:the_clock_0|clock_0_slave_read_request_sync_module:clock_0_slave_read_request_sync
}
# end
# entity
clock_0_slave_write_request_sync_module
# storage
db|standard.(12).cnf
db|standard.(12).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
clock_0.vhd
dbe1e6a05ee6fa3e0d157e96a5e49fd
4
# internal_option {
AUTO_RESOURCE_SHARING
OFF
}
# hierarchies {
std_1c20:inst|clock_0:the_clock_0|clock_0_slave_write_request_sync_module:clock_0_slave_write_request_sync
}
# end
# entity
clock_0_master_FSM
# storage
db|standard.(13).cnf
db|standard.(13).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
clock_0.vhd
dbe1e6a05ee6fa3e0d157e96a5e49fd
4
# internal_option {
AUTO_RESOURCE_SHARING
OFF
}
# hierarchies {
std_1c20:inst|clock_0:the_clock_0|clock_0_master_FSM:master_FSM
}
# end
# entity
clock_0_bit_pipe
# storage
db|standard.(14).cnf
db|standard.(14).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
clock_0.vhd
dbe1e6a05ee6fa3e0d157e96a5e49fd
4
# internal_option {
AUTO_RESOURCE_SHARING
OFF
}
# hierarchies {
std_1c20:inst|clock_0:the_clock_0|clock_0_bit_pipe:endofpacket_bit_pipe
}
# end
# entity
clock_1
# storage
db|standard.(17).cnf
db|standard.(17).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
clock_1.vhd
84cf22f4b1a1a61b4f20afcbf1767
4
# internal_option {
AUTO_RESOURCE_SHARING
OFF
}
# user_parameter {
 constraint(master_readdata)
15 downto 0
PARAMETER_STRING
USR
 constraint(slave_address)
3 downto 0
PARAMETER_STRING
USR
 constraint(slave_byteenable)
1 downto 0
PARAMETER_STRING
USR
 constraint(slave_nativeaddress)
2 downto 0
PARAMETER_STRING
USR
 constraint(slave_writedata)
15 downto 0
PARAMETER_STRING
USR
 constraint(master_address)
3 downto 0
PARAMETER_STRING
USR
 constraint(master_byteenable)
1 downto 0
PARAMETER_STRING
USR
 constraint(master_nativeaddress)
2 downto 0
PARAMETER_STRING
USR
 constraint(master_writedata)
15 downto 0
PARAMETER_STRING
USR
 constraint(slave_readdata)
15 downto 0
PARAMETER_STRING
USR
}
# hierarchies {
std_1c20:inst|clock_1:the_clock_1
}
# end
# entity
clock_1_master_read_done_sync_module
# storage
db|standard.(18).cnf
db|standard.(18).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
clock_1.vhd
84cf22f4b1a1a61b4f20afcbf1767
4
# internal_option {
AUTO_RESOURCE_SHARING
OFF
}
# hierarchies {
std_1c20:inst|clock_1:the_clock_1|clock_1_master_read_done_sync_module:clock_1_master_read_done_sync
}
# end
# entity
clock_1_master_write_done_sync_module
# storage
db|standard.(19).cnf
db|standard.(19).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
clock_1.vhd
84cf22f4b1a1a61b4f20afcbf1767
4
# internal_option {
AUTO_RESOURCE_SHARING
OFF
}
# hierarchies {
std_1c20:inst|clock_1:the_clock_1|clock_1_master_write_done_sync_module:clock_1_master_write_done_sync
}
# end
# entity
clock_1_edge_to_pulse
# storage
db|standard.(20).cnf
db|standard.(20).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
clock_1.vhd
84cf22f4b1a1a61b4f20afcbf1767
4
# internal_option {
AUTO_RESOURCE_SHARING
OFF
}
# hierarchies {
std_1c20:inst|clock_1:the_clock_1|clock_1_edge_to_pulse:read_done_edge_to_pulse
std_1c20:inst|clock_1:the_clock_1|clock_1_edge_to_pulse:write_done_edge_to_pulse
std_1c20:inst|clock_1:the_clock_1|clock_1_edge_to_pulse:read_request_edge_to_pulse
std_1c20:inst|clock_1:the_clock_1|clock_1_edge_to_pulse:write_request_edge_to_pulse
}
# end
# entity
clock_1_slave_FSM
# storage
db|standard.(21).cnf
db|standard.(21).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
clock_1.vhd
84cf22f4b1a1a61b4f20afcbf1767
4
# internal_option {
AUTO_RESOURCE_SHARING
OFF
}
# hierarchies {
std_1c20:inst|clock_1:the_clock_1|clock_1_slave_FSM:slave_FSM
}
# end
# entity
clock_1_slave_read_request_sync_module
# storage
db|standard.(22).cnf
db|standard.(22).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
clock_1.vhd
84cf22f4b1a1a61b4f20afcbf1767
4
# internal_option {
AUTO_RESOURCE_SHARING
OFF
}
# hierarchies {
std_1c20:inst|clock_1:the_clock_1|clock_1_slave_read_request_sync_module:clock_1_slave_read_request_sync
}
# end
# entity
clock_1_slave_write_request_sync_module
# storage
db|standard.(23).cnf
db|standard.(23).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
clock_1.vhd
84cf22f4b1a1a61b4f20afcbf1767
4
# internal_option {
AUTO_RESOURCE_SHARING
OFF
}
# hierarchies {
std_1c20:inst|clock_1:the_clock_1|clock_1_slave_write_request_sync_module:clock_1_slave_write_request_sync
}
# end
# entity
clock_1_master_FSM
# storage
db|standard.(24).cnf
db|standard.(24).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
clock_1.vhd
84cf22f4b1a1a61b4f20afcbf1767
4
# internal_option {
AUTO_RESOURCE_SHARING
OFF
}
# hierarchies {
std_1c20:inst|clock_1:the_clock_1|clock_1_master_FSM:master_FSM
}
# end
# entity
clock_1_bit_pipe
# storage
db|standard.(25).cnf
db|standard.(25).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
clock_1.vhd
84cf22f4b1a1a61b4f20afcbf1767
4
# internal_option {
AUTO_RESOURCE_SHARING
OFF
}
# hierarchies {
std_1c20:inst|clock_1:the_clock_1|clock_1_bit_pipe:endofpacket_bit_pipe
}
# end
# entity
connector_pll
# storage
db|standard.(27).cnf
db|standard.(27).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
connector_pll.vhd
17bfc9e8d7316681e8b8b6b5b467c02c
4
# internal_option {
AUTO_RESOURCE_SHARING
OFF
}
# user_parameter {
 constraint(address)
2 downto 0
PARAMETER_STRING
USR
 constraint(writedata)
15 downto 0
PARAMETER_STRING
USR
 constraint(readdata)
15 downto 0
PARAMETER_STRING
USR
}
# hierarchies {
std_1c20:inst|connector_pll:the_connector_pll
}
# end
# entity
altpllconnector_pll
# storage
db|standard.(28).cnf
db|standard.(28).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
altpllconnector_pll.vhd
afe82d273f8e1d4fd1de9bb253e8ce
4
# internal_option {
AUTO_RESOURCE_SHARING
OFF
}
# hierarchies {
std_1c20:inst|connector_pll:the_connector_pll|altpllconnector_pll:the_pll
}
# end
# entity
altpll
# storage
db|standard.(29).cnf
db|standard.(29).cnf
# case_insensitive
# source_file
..|..|..|..|quartus60|libraries|megafunctions|altpll.tdf
eda762e5901c3e66939b23e413541e
6
# user_parameter {
OPERATION_MODE
NORMAL
PARAMETER_UNKNOWN
USR
PLL_TYPE
AUTO
PARAMETER_UNKNOWN
USR
QUALIFY_CONF_DONE
OFF
PARAMETER_UNKNOWN
DEF
COMPENSATE_CLOCK
CLK0
PARAMETER_UNKNOWN
USR
SCAN_CHAIN
LONG
PARAMETER_UNKNOWN
DEF
PRIMARY_CLOCK
INCLK0
PARAMETER_UNKNOWN
DEF
INCLK0_INPUT_FREQUENCY
20000
PARAMETER_DEC
USR
INCLK1_INPUT_FREQUENCY
0
PARAMETER_UNKNOWN
DEF
GATE_LOCK_SIGNAL
NO
PARAMETER_UNKNOWN
DEF
GATE_LOCK_COUNTER
0
PARAMETER_UNKNOWN
DEF
LOCK_HIGH
1
PARAMETER_UNKNOWN
DEF
LOCK_LOW
1
PARAMETER_UNKNOWN
DEF
VALID_LOCK_MULTIPLIER
1
PARAMETER_UNKNOWN
DEF
INVALID_LOCK_MULTIPLIER
5
PARAMETER_UNKNOWN
DEF
SWITCH_OVER_ON_LOSSCLK
OFF
PARAMETER_UNKNOWN
DEF
SWITCH_OVER_ON_GATED_LOCK
OFF
PARAMETER_UNKNOWN
DEF
ENABLE_SWITCH_OVER_COUNTER
OFF
PARAMETER_UNKNOWN
DEF
SKIP_VCO
OFF
PARAMETER_UNKNOWN
DEF
SWITCH_OVER_COUNTER
0
PARAMETER_UNKNOWN
DEF
SWITCH_OVER_TYPE
AUTO
PARAMETER_UNKNOWN
DEF
FEEDBACK_SOURCE
EXTCLK0
PARAMETER_UNKNOWN
DEF
BANDWIDTH
0
PARAMETER_UNKNOWN
DEF
BANDWIDTH_TYPE
AUTO
PARAMETER_UNKNOWN
DEF
SPREAD_FREQUENCY
0
PARAMETER_UNKNOWN
DEF
DOWN_SPREAD
0
PARAMETER_UNKNOWN
DEF
SELF_RESET_ON_GATED_LOSS_LOCK
OFF
PARAMETER_UNKNOWN
DEF
CLK5_MULTIPLY_BY
1
PARAMETER_UNKNOWN
DEF
CLK4_MULTIPLY_BY
1
PARAMETER_UNKNOWN
DEF
CLK3_MULTIPLY_BY
1
PARAMETER_UNKNOWN
DEF
CLK2_MULTIPLY_BY
1
PARAMETER_UNKNOWN
DEF
CLK1_MULTIPLY_BY
1
PARAMETER_UNKNOWN
DEF
CLK0_MULTIPLY_BY
9
PARAMETER_DEC
USR
CLK5_DIVIDE_BY
1
PARAMETER_UNKNOWN
DEF
CLK4_DIVIDE_BY
1
PARAMETER_UNKNOWN
DEF
CLK3_DIVIDE_BY
1
PARAMETER_UNKNOWN
DEF
CLK2_DIVIDE_BY
1
PARAMETER_UNKNOWN
DEF
CLK1_DIVIDE_BY
1
PARAMETER_UNKNOWN
DEF
CLK0_DIVIDE_BY
5
PARAMETER_DEC
USR
CLK5_PHASE_SHIFT
0
PARAMETER_UNKNOWN
DEF
CLK4_PHASE_SHIFT
0
PARAMETER_UNKNOWN
DEF
CLK3_PHASE_SHIFT
0
PARAMETER_UNKNOWN
DEF
CLK2_PHASE_SHIFT
0
PARAMETER_UNKNOWN
DEF
CLK1_PHASE_SHIFT
0
PARAMETER_UNKNOWN
DEF
CLK0_PHASE_SHIFT
0
PARAMETER_UNKNOWN
USR
CLK5_TIME_DELAY
0
PARAMETER_UNKNOWN
DEF
CLK4_TIME_DELAY
0
PARAMETER_UNKNOWN
DEF
CLK3_TIME_DELAY
0
PARAMETER_UNKNOWN
DEF
CLK2_TIME_DELAY
0
PARAMETER_UNKNOWN
DEF
CLK1_TIME_DELAY
0
PARAMETER_UNKNOWN
DEF
CLK0_TIME_DELAY
0
PARAMETER_UNKNOWN
DEF
CLK5_DUTY_CYCLE
50
PARAMETER_UNKNOWN
DEF
CLK4_DUTY_CYCLE
50
PARAMETER_UNKNOWN
DEF
CLK3_DUTY_CYCLE
50
PARAMETER_UNKNOWN
DEF
CLK2_DUTY_CYCLE
50
PARAMETER_UNKNOWN
DEF
CLK1_DUTY_CYCLE
50
PARAMETER_UNKNOWN
DEF
CLK0_DUTY_CYCLE
50
PARAMETER_DEC
USR
EXTCLK3_MULTIPLY_BY
1
PARAMETER_UNKNOWN
DEF
EXTCLK2_MULTIPLY_BY
1
PARAMETER_UNKNOWN
DEF
EXTCLK1_MULTIPLY_BY
1
PARAMETER_UNKNOWN
DEF
EXTCLK0_MULTIPLY_BY
1
PARAMETER_DEC
USR
EXTCLK3_DIVIDE_BY
1
PARAMETER_UNKNOWN
DEF
EXTCLK2_DIVIDE_BY
1
PARAMETER_UNKNOWN
DEF
EXTCLK1_DIVIDE_BY
1
PARAMETER_UNKNOWN
DEF
EXTCLK0_DIVIDE_BY
1
PARAMETER_DEC
USR
EXTCLK3_PHASE_SHIFT
0
PARAMETER_UNKNOWN
DEF
EXTCLK2_PHASE_SHIFT
0
PARAMETER_UNKNOWN
DEF
EXTCLK1_PHASE_SHIFT
0
PARAMETER_UNKNOWN
DEF
EXTCLK0_PHASE_SHIFT
0
PARAMETER_UNKNOWN
USR
EXTCLK3_TIME_DELAY
0
PARAMETER_UNKNOWN
DEF
EXTCLK2_TIME_DELAY
0
PARAMETER_UNKNOWN
DEF
EXTCLK1_TIME_DELAY
0
PARAMETER_UNKNOWN
DEF
EXTCLK0_TIME_DELAY
0
PARAMETER_UNKNOWN
DEF
EXTCLK3_DUTY_CYCLE
50
PARAMETER_UNKNOWN
DEF
EXTCLK2_DUTY_CYCLE
50
PARAMETER_UNKNOWN
DEF
EXTCLK1_DUTY_CYCLE
50
PARAMETER_UNKNOWN
DEF
EXTCLK0_DUTY_CYCLE
50
PARAMETER_DEC
USR
VCO_MULTIPLY_BY
0
PARAMETER_UNKNOWN
DEF
VCO_DIVIDE_BY
0
PARAMETER_UNKNOWN
DEF
SCLKOUT0_PHASE_SHIFT
0
PARAMETER_UNKNOWN
DEF
SCLKOUT1_PHASE_SHIFT
0
PARAMETER_UNKNOWN
DEF
VCO_MIN
0
PARAMETER_UNKNOWN
DEF
VCO_MAX
0
PARAMETER_UNKNOWN
DEF
VCO_CENTER
0
PARAMETER_UNKNOWN
DEF
PFD_MIN
0
PARAMETER_UNKNOWN
DEF
PFD_MAX
0
PARAMETER_UNKNOWN
DEF
M_INITIAL
0
PARAMETER_UNKNOWN
DEF
M
0
PARAMETER_UNKNOWN
DEF
N
1
PARAMETER_UNKNOWN
DEF
M2
1
PARAMETER_UNKNOWN
DEF
N2
1
PARAMETER_UNKNOWN
DEF
SS
1
PARAMETER_UNKNOWN
DEF
C0_HIGH
0
PARAMETER_UNKNOWN
DEF
C1_HIGH
0
PARAMETER_UNKNOWN
DEF
C2_HIGH
0
PARAMETER_UNKNOWN
DEF
C3_HIGH
0
PARAMETER_UNKNOWN
DEF
C4_HIGH
0
PARAMETER_UNKNOWN
DEF
C5_HIGH
0
PARAMETER_UNKNOWN
DEF
C0_LOW
0
PARAMETER_UNKNOWN
DEF
C1_LOW
0
PARAMETER_UNKNOWN
DEF
C2_LOW
0
PARAMETER_UNKNOWN
DEF
C3_LOW
0
PARAMETER_UNKNOWN
DEF
C4_LOW
0
PARAMETER_UNKNOWN
DEF
C5_LOW
0
PARAMETER_UNKNOWN
DEF
C0_INITIAL
0
PARAMETER_UNKNOWN
DEF
C1_INITIAL
0
PARAMETER_UNKNOWN
DEF
C2_INITIAL
0
PARAMETER_UNKNOWN
DEF
C3_INITIAL
0
PARAMETER_UNKNOWN
DEF
C4_INITIAL
0
PARAMETER_UNKNOWN
DEF
C5_INITIAL
0
PARAMETER_UNKNOWN
DEF
C0_MODE
BYPASS
PARAMETER_UNKNOWN
DEF
C1_MODE
BYPASS
PARAMETER_UNKNOWN
DEF
C2_MODE
BYPASS
PARAMETER_UNKNOWN
DEF
C3_MODE
BYPASS
PARAMETER_UNKNOWN
DEF
C4_MODE
BYPASS
PARAMETER_UNKNOWN
DEF
C5_MODE
BYPASS
PARAMETER_UNKNOWN
DEF
C0_PH
0
PARAMETER_UNKNOWN
DEF
C1_PH
0
PARAMETER_UNKNOWN
DEF
C2_PH
0
PARAMETER_UNKNOWN
DEF
C3_PH
0
PARAMETER_UNKNOWN
DEF
C4_PH
0
PARAMETER_UNKNOWN
DEF
C5_PH
0
PARAMETER_UNKNOWN
DEF
L0_HIGH
1
PARAMETER_UNKNOWN
DEF
L1_HIGH
1
PARAMETER_UNKNOWN
DEF
G0_HIGH
1
PARAMETER_UNKNOWN
DEF
G1_HIGH
1
PARAMETER_UNKNOWN
DEF
G2_HIGH
1
PARAMETER_UNKNOWN
DEF
G3_HIGH
1
PARAMETER_UNKNOWN
DEF
E0_HIGH
1
PARAMETER_UNKNOWN
DEF
E1_HIGH
1
PARAMETER_UNKNOWN
DEF
E2_HIGH
1
PARAMETER_UNKNOWN
DEF
E3_HIGH
1
PARAMETER_UNKNOWN
DEF
L0_LOW
1
PARAMETER_UNKNOWN
DEF
L1_LOW
1
PARAMETER_UNKNOWN
DEF
G0_LOW
1
PARAMETER_UNKNOWN
DEF
G1_LOW
1
PARAMETER_UNKNOWN
DEF
G2_LOW
1
PARAMETER_UNKNOWN
DEF
G3_LOW
1
PARAMETER_UNKNOWN
DEF
E0_LOW
1
PARAMETER_UNKNOWN
DEF
E1_LOW
1
PARAMETER_UNKNOWN
DEF
E2_LOW
1
PARAMETER_UNKNOWN
DEF
E3_LOW
1
PARAMETER_UNKNOWN
DEF
L0_INITIAL
1
PARAMETER_UNKNOWN
DEF
L1_INITIAL
1
PARAMETER_UNKNOWN
DEF
G0_INITIAL
1
PARAMETER_UNKNOWN
DEF
G1_INITIAL
1
PARAMETER_UNKNOWN
DEF
G2_INITIAL
1
PARAMETER_UNKNOWN
DEF
G3_INITIAL
1
PARAMETER_UNKNOWN
DEF
E0_INITIAL
1
PARAMETER_UNKNOWN
DEF
E1_INITIAL
1
PARAMETER_UNKNOWN
DEF
E2_INITIAL
1
PARAMETER_UNKNOWN
DEF
E3_INITIAL
1
PARAMETER_UNKNOWN
DEF
L0_MODE
BYPASS
PARAMETER_UNKNOWN
DEF
L1_MODE
BYPASS
PARAMETER_UNKNOWN
DEF
G0_MODE
BYPASS
PARAMETER_UNKNOWN
DEF
G1_MODE
BYPASS
PARAMETER_UNKNOWN
DEF
G2_MODE
BYPASS
PARAMETER_UNKNOWN
DEF
G3_MODE
BYPASS
PARAMETER_UNKNOWN
DEF
E0_MODE
BYPASS
PARAMETER_UNKNOWN
DEF
E1_MODE
BYPASS
PARAMETER_UNKNOWN
DEF
E2_MODE
BYPASS
PARAMETER_UNKNOWN
DEF
E3_MODE
BYPASS
PARAMETER_UNKNOWN
DEF
L0_PH
0
PARAMETER_UNKNOWN
DEF
L1_PH
0
PARAMETER_UNKNOWN
DEF
G0_PH
0
PARAMETER_UNKNOWN
DEF
G1_PH
0
PARAMETER_UNKNOWN
DEF
G2_PH
0
PARAMETER_UNKNOWN
DEF
G3_PH
0
PARAMETER_UNKNOWN
DEF
E0_PH
0
PARAMETER_UNKNOWN
DEF
E1_PH
0
PARAMETER_UNKNOWN
DEF
E2_PH
0
PARAMETER_UNKNOWN
DEF
E3_PH
0
PARAMETER_UNKNOWN
DEF
M_PH
0
PARAMETER_UNKNOWN
DEF
C1_USE_CASC_IN
0
PARAMETER_UNKNOWN
DEF
C2_USE_CASC_IN
0
PARAMETER_UNKNOWN
DEF
C3_USE_CASC_IN
0
PARAMETER_UNKNOWN
DEF
C4_USE_CASC_IN
0
PARAMETER_UNKNOWN
DEF
C5_USE_CASC_IN
0
PARAMETER_UNKNOWN
DEF
CLK0_COUNTER
G0
PARAMETER_UNKNOWN
DEF
CLK1_COUNTER
G0
PARAMETER_UNKNOWN
DEF
CLK2_COUNTER
G0
PARAMETER_UNKNOWN
DEF
CLK3_COUNTER
G0
PARAMETER_UNKNOWN
DEF
CLK4_COUNTER
G0
PARAMETER_UNKNOWN
DEF
CLK5_COUNTER
G0
PARAMETER_UNKNOWN
DEF
L0_TIME_DELAY
0
PARAMETER_UNKNOWN
DEF
L1_TIME_DELAY
0
PARAMETER_UNKNOWN
DEF
G0_TIME_DELAY
0
PARAMETER_UNKNOWN
DEF
G1_TIME_DELAY
0
PARAMETER_UNKNOWN
DEF
G2_TIME_DELAY
0
PARAMETER_UNKNOWN
DEF
G3_TIME_DELAY
0
PARAMETER_UNKNOWN
DEF
E0_TIME_DELAY
0
PARAMETER_UNKNOWN
DEF
E1_TIME_DELAY
0
PARAMETER_UNKNOWN
DEF
E2_TIME_DELAY
0
PARAMETER_UNKNOWN
DEF
E3_TIME_DELAY
0
PARAMETER_UNKNOWN
DEF
M_TIME_DELAY
0
PARAMETER_UNKNOWN
DEF
N_TIME_DELAY
0
PARAMETER_UNKNOWN
DEF
EXTCLK3_COUNTER
E3
PARAMETER_UNKNOWN
DEF
EXTCLK2_COUNTER
E2
PARAMETER_UNKNOWN
DEF
EXTCLK1_COUNTER
E1
PARAMETER_UNKNOWN
DEF
EXTCLK0_COUNTER
E0
PARAMETER_UNKNOWN
DEF
ENABLE0_COUNTER
L0
PARAMETER_UNKNOWN
DEF
ENABLE1_COUNTER
L0
PARAMETER_UNKNOWN
DEF
CHARGE_PUMP_CURRENT
2
PARAMETER_UNKNOWN
DEF
LOOP_FILTER_R
 1.000000
PARAMETER_UNKNOWN
DEF
LOOP_FILTER_C
5
PARAMETER_UNKNOWN
DEF
VCO_POST_SCALE
0
PARAMETER_UNKNOWN
DEF
CLK2_OUTPUT_FREQUENCY
0
PARAMETER_UNKNOWN
DEF
CLK1_OUTPUT_FREQUENCY
0
PARAMETER_UNKNOWN
DEF
CLK0_OUTPUT_FREQUENCY
0
PARAMETER_UNKNOWN
DEF
INTENDED_DEVICE_FAMILY
Cyclone
PARAMETER_UNKNOWN
USR
PORT_CLKENA0
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_CLKENA1
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_CLKENA2
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
PORT_CLKENA3
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_CLKENA4
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_CLKENA5
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_EXTCLKENA0
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_EXTCLKENA1
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_EXTCLKENA2
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_EXTCLKENA3
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_EXTCLK0
PORT_USED
PARAMETER_UNKNOWN
USR
PORT_EXTCLK1
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_EXTCLK2
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_EXTCLK3
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_CLKBAD0
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_CLKBAD1
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_CLK0
PORT_USED
PARAMETER_UNKNOWN
USR
PORT_CLK1
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_CLK2
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
PORT_CLK3
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_CLK4
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_CLK5
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_SCANDATA
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_SCANDATAOUT
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_SCANDONE
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_SCLKOUT1
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_SCLKOUT0
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_ACTIVECLOCK
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_CLKLOSS
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_INCLK1
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_INCLK0
PORT_USED
PARAMETER_UNKNOWN
USR
PORT_FBIN
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_PLLENA
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_CLKSWITCH
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_ARESET
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_PFDENA
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_SCANCLK
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_SCANACLR
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_SCANREAD
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_SCANWRITE
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_ENABLE0
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_ENABLE1
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_LOCKED
PORT_UNUSED
PARAMETER_UNKNOWN
USR
M_TEST_SOURCE
5
PARAMETER_UNKNOWN
DEF
C0_TEST_SOURCE
5
PARAMETER_UNKNOWN
DEF
C1_TEST_SOURCE
5
PARAMETER_UNKNOWN
DEF
C2_TEST_SOURCE
5
PARAMETER_UNKNOWN
DEF
C3_TEST_SOURCE
5
PARAMETER_UNKNOWN
DEF
C4_TEST_SOURCE
5
PARAMETER_UNKNOWN
DEF
C5_TEST_SOURCE
5
PARAMETER_UNKNOWN
DEF
DEVICE_FAMILY
Cyclone
PARAMETER_UNKNOWN
USR
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
}
# used_port {
inclk0
-1
3
extclk0
-1
3
clk0
-1
3
inclk1
-1
1
}
# include_file {
..|..|..|..|quartus60|libraries|megafunctions|stratix_pll.inc
5f8211898149ceae8264a0ea5036254f
..|..|..|..|quartus60|libraries|megafunctions|aglobal60.inc
b3d07c643dae10ab2b3e646e99ec45fc
..|..|..|..|quartus60|libraries|megafunctions|stratixii_pll.inc
6d1985e16ab5f59a1fd6b0ae20978a4e
..|..|..|..|quartus60|libraries|megafunctions|cycloneii_pll.inc
39a0d9d1237d1db39c848c3f9faffc
}
# hierarchies {
std_1c20:inst|connector_pll:the_connector_pll|altpllconnector_pll:the_pll|altpll:altpll_component
}
# end
# entity
altsyncram
# storage
db|standard.(36).cnf
db|standard.(36).cnf
# case_insensitive
# source_file
..|..|..|..|quartus60|libraries|megafunctions|altsyncram.tdf
c9a54fc8e33741c15b27e3d74d615aff
6
# user_parameter {
BYTE_SIZE_BLOCK
8
PARAMETER_UNKNOWN
DEF
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
OPERATION_MODE
DUAL_PORT
PARAMETER_UNKNOWN
USR
WIDTH_A
32
PARAMETER_DEC
USR
WIDTHAD_A
10
PARAMETER_DEC
USR
NUMWORDS_A
1024
PARAMETER_DEC
USR
OUTDATA_REG_A
UNREGISTERED
PARAMETER_UNKNOWN
DEF
ADDRESS_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
OUTDATA_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
WRCONTROL_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
INDATA_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
BYTEENA_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
WIDTH_B
32
PARAMETER_DEC
USR
WIDTHAD_B
10
PARAMETER_DEC
USR
NUMWORDS_B
1024
PARAMETER_DEC
USR
INDATA_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
WRCONTROL_WRADDRESS_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
RDCONTROL_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
ADDRESS_REG_B
CLOCK1
PARAMETER_UNKNOWN
USR
OUTDATA_REG_B
UNREGISTERED
PARAMETER_UNKNOWN
USR
BYTEENA_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
INDATA_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
WRCONTROL_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
ADDRESS_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
OUTDATA_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
RDCONTROL_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
BYTEENA_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
WIDTH_BYTEENA_A
1
PARAMETER_UNKNOWN
DEF
WIDTH_BYTEENA_B
1
PARAMETER_UNKNOWN
DEF
RAM_BLOCK_TYPE
AUTO
PARAMETER_UNKNOWN
USR
BYTE_SIZE
8
PARAMETER_UNKNOWN
DEF
READ_DURING_WRITE_MODE_MIXED_PORTS
DONT_CARE
PARAMETER_UNKNOWN
USR
INIT_FILE
UNUSED
PARAMETER_UNKNOWN
DEF
INIT_FILE_LAYOUT
PORT_A
PARAMETER_UNKNOWN
DEF
MAXIMUM_DEPTH
0
PARAMETER_DEC
USR
CLOCK_ENABLE_INPUT_A
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_INPUT_B
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_OUTPUT_A
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_OUTPUT_B
NORMAL
PARAMETER_UNKNOWN
DEF
DEVICE_FAMILY
Cyclone
PARAMETER_UNKNOWN
USR
CBXI_PARAMETER
altsyncram_qmb1
PARAMETER_UNKNOWN
USR
}
# used_port {
wren_a
-1
3
q_b9
-1
3
q_b8
-1
3
q_b7
-1
3
q_b6
-1
3
q_b5
-1
3
q_b4
-1
3
q_b31
-1
3
q_b30
-1
3
q_b3
-1
3
q_b29
-1
3
q_b28
-1
3
q_b27
-1
3
q_b26
-1
3
q_b25
-1
3
q_b24
-1
3
q_b23
-1
3
q_b22
-1
3
q_b21
-1
3
q_b20
-1
3
q_b2
-1
3
q_b19
-1
3
q_b18
-1
3
q_b17
-1
3
q_b16
-1
3
q_b15
-1
3
q_b14
-1
3
q_b13
-1
3
q_b12
-1
3
q_b11
-1
3
q_b10
-1
3
q_b1
-1
3
q_b0
-1
3
data_a9
-1
3
data_a8
-1
3
data_a7
-1
3
data_a6
-1
3
data_a5
-1
3
data_a4
-1
3
data_a31
-1
3
data_a30
-1
3
data_a3
-1
3
data_a29
-1
3
data_a28
-1
3
data_a27
-1
3
data_a26
-1
3
data_a25
-1
3
data_a24
-1
3
data_a23
-1
3
data_a22
-1
3
data_a21
-1
3
data_a20
-1
3
data_a2
-1
3
data_a19
-1
3
data_a18
-1
3
data_a17
-1
3
data_a16
-1
3
data_a15
-1
3
data_a14
-1
3
data_a13
-1
3
data_a12
-1
3
data_a11
-1
3
data_a10
-1
3
data_a1
-1
3
data_a0
-1
3
clocken1
-1
3
clock1
-1
3
clock0
-1
3
address_b9
-1
3
address_b8
-1
3
address_b7
-1
3
address_b6
-1
3
address_b5
-1
3
address_b4
-1
3
address_b3
-1
3
address_b2
-1
3
address_b1
-1
3
address_b0
-1
3
address_a9
-1
3
address_a8
-1
3
address_a7
-1
3
address_a6
-1
3
address_a5
-1
3
address_a4
-1
3
address_a3
-1
3
address_a2
-1
3
address_a1
-1
3
address_a0
-1
3
clocken0
-1
2
}
# include_file {
..|..|..|..|quartus60|libraries|megafunctions|aglobal60.inc
b3d07c643dae10ab2b3e646e99ec45fc
..|..|..|..|quartus60|libraries|megafunctions|stratix_ram_block.inc
2263a3bdfffeb150af977ee13902f70
..|..|..|..|quartus60|libraries|megafunctions|lpm_mux.inc
c22bfd353214c01495b560fc34e47d79
..|..|..|..|quartus60|libraries|megafunctions|lpm_decode.inc
bd0e2f5e01c1bd360461dceb53d48
..|..|..|..|quartus60|libraries|megafunctions|altsyncram.inc
2d485e3cf75d4048974bdbf0d920cb89
..|..|..|..|quartus60|libraries|megafunctions|a_rdenreg.inc
60d229340bc3c24acb0a137b4849830
..|..|..|..|quartus60|libraries|megafunctions|altrom.inc
d4e3a69a331d3a99d3281790d99a1ebd
..|..|..|..|quartus60|libraries|megafunctions|altram.inc
e66a83eccf6717bed97c99d891ad085
..|..|..|..|quartus60|libraries|megafunctions|altdpram.inc
4e1931f9814db9f22f22b9eb377c65d6
..|..|..|..|quartus60|libraries|megafunctions|altqpram.inc
74e08939f96a7ea8e7a4d59a5b01fe7
}
# hierarchies {
std_1c20:inst|cpu:the_cpu|cpu_ic_data_module:cpu_ic_data|altsyncram:the_altsyncram
}
# end
# entity
altsyncram_qmb1
# storage
db|standard.(37).cnf
db|standard.(37).cnf
# case_insensitive
# source_file
db|altsyncram_qmb1.tdf
ac7cf72683a13dd5c2a6dbd866f8137
6
# user_parameter {
PORT_A_ADDRESS_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_A_BYTE_ENABLE_MASK_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_A_DATA_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_B_ADDRESS_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_B_BYTE_ENABLE_MASK_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_B_DATA_WIDTH
1
PARAMETER_UNKNOWN
DEF
}
# used_port {
wren_a
-1
3
q_b9
-1
3
q_b8
-1
3
q_b7
-1
3
q_b6
-1
3
q_b5
-1
3
q_b4
-1
3
q_b31
-1
3
q_b30
-1
3
q_b3
-1
3
q_b29
-1
3
q_b28
-1
3
q_b27
-1
3
q_b26
-1
3
q_b25
-1
3
q_b24
-1
3
q_b23
-1
3
q_b22
-1
3
q_b21
-1
3
q_b20
-1
3
q_b2
-1
3
q_b19
-1
3
q_b18
-1
3
q_b17
-1
3
q_b16
-1
3
q_b15
-1
3
q_b14
-1
3
q_b13
-1
3
q_b12
-1
3
q_b11
-1
3
q_b10
-1
3
q_b1
-1
3
q_b0
-1
3
data_a9
-1
3
data_a8
-1
3
data_a7
-1
3
data_a6
-1
3
data_a5
-1
3
data_a4
-1
3
data_a31
-1
3
data_a30
-1
3
data_a3
-1
3
data_a29
-1
3
data_a28
-1
3
data_a27
-1
3
data_a26
-1
3
data_a25
-1
3
data_a24
-1
3
data_a23
-1
3
data_a22
-1
3
data_a21
-1
3
data_a20
-1
3
data_a2
-1
3
data_a19
-1
3
data_a18
-1
3
data_a17
-1
3
data_a16
-1
3
data_a15
-1
3
data_a14
-1
3
data_a13
-1
3
data_a12
-1
3
data_a11
-1
3
data_a10
-1
3
data_a1
-1
3
data_a0
-1
3
clocken1
-1
3
clock1
-1
3
clock0
-1
3
address_b9
-1
3
address_b8
-1
3
address_b7
-1
3
address_b6
-1
3
address_b5
-1
3
address_b4
-1
3
address_b3
-1
3
address_b2
-1
3
address_b1
-1
3
address_b0
-1
3
address_a9
-1
3
address_a8
-1
3
address_a7
-1
3
address_a6
-1
3
address_a5
-1
3
address_a4
-1
3
address_a3
-1
3
address_a2
-1
3
address_a1
-1
3
address_a0
-1
3
}
# memory_file {
none
0
}
# hierarchies {
std_1c20:inst|cpu:the_cpu|cpu_ic_data_module:cpu_ic_data|altsyncram:the_altsyncram|altsyncram_qmb1:auto_generated
}
# end
# entity
altsyncram
# storage
db|standard.(39).cnf
db|standard.(39).cnf
# case_insensitive
# source_file
..|..|..|..|quartus60|libraries|megafunctions|altsyncram.tdf
c9a54fc8e33741c15b27e3d74d615aff
6
# user_parameter {
BYTE_SIZE_BLOCK
8
PARAMETER_UNKNOWN
DEF
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
OPERATION_MODE
DUAL_PORT
PARAMETER_UNKNOWN
USR
WIDTH_A
22
PARAMETER_DEC
USR
WIDTHAD_A
7
PARAMETER_DEC
USR
NUMWORDS_A
128
PARAMETER_DEC
USR
OUTDATA_REG_A
UNREGISTERED
PARAMETER_UNKNOWN
DEF
ADDRESS_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
OUTDATA_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
WRCONTROL_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
INDATA_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
BYTEENA_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
WIDTH_B
22
PARAMETER_DEC
USR
WIDTHAD_B
7
PARAMETER_DEC
USR
NUMWORDS_B
128
PARAMETER_DEC
USR
INDATA_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
WRCONTROL_WRADDRESS_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
RDCONTROL_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
ADDRESS_REG_B
CLOCK1
PARAMETER_UNKNOWN
USR
OUTDATA_REG_B
UNREGISTERED
PARAMETER_UNKNOWN
USR
BYTEENA_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
INDATA_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
WRCONTROL_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
ADDRESS_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
OUTDATA_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
RDCONTROL_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
BYTEENA_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
WIDTH_BYTEENA_A
1
PARAMETER_UNKNOWN
DEF
WIDTH_BYTEENA_B
1
PARAMETER_UNKNOWN
DEF
RAM_BLOCK_TYPE
AUTO
PARAMETER_UNKNOWN
USR
BYTE_SIZE
8
PARAMETER_UNKNOWN
DEF
READ_DURING_WRITE_MODE_MIXED_PORTS
OLD_DATA
PARAMETER_UNKNOWN
USR
INIT_FILE
cpu_ic_tag_ram.mif
PARAMETER_UNKNOWN
USR
INIT_FILE_LAYOUT
PORT_A
PARAMETER_UNKNOWN
DEF
MAXIMUM_DEPTH
0
PARAMETER_DEC
USR
CLOCK_ENABLE_INPUT_A
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_INPUT_B
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_OUTPUT_A
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_OUTPUT_B
NORMAL
PARAMETER_UNKNOWN
DEF
DEVICE_FAMILY
Cyclone
PARAMETER_UNKNOWN
USR
CBXI_PARAMETER
altsyncram_09e1
PARAMETER_UNKNOWN
USR
}
# used_port {
wren_a
-1
3
q_b9
-1
3
q_b8
-1
3
q_b7
-1
3
q_b6
-1
3
q_b5
-1
3
q_b4
-1
3
q_b3
-1
3
q_b21
-1
3
q_b20
-1
3
q_b2
-1
3
q_b19
-1
3
q_b18
-1
3
q_b17
-1
3
q_b16
-1
3
q_b15
-1
3
q_b14
-1
3
q_b13
-1
3
q_b12
-1
3
q_b11
-1
3
q_b10
-1
3
q_b1
-1
3
q_b0
-1
3
data_a9
-1
3
data_a8
-1
3
data_a7
-1
3
data_a6
-1
3
data_a5
-1
3
data_a4
-1
3
data_a3
-1
3
data_a21
-1
3
data_a20
-1
3
data_a2
-1
3
data_a19
-1
3
data_a18
-1
3
data_a17
-1
3
data_a16
-1
3
data_a15
-1
3
data_a14
-1
3
data_a13
-1
3
data_a12
-1
3
data_a11
-1
3
data_a10
-1
3
data_a1
-1
3
data_a0
-1
3
clocken1
-1
3
clock1
-1
3
clock0
-1
3
address_b6
-1
3
address_b5
-1
3
address_b4
-1
3
address_b3
-1
3
address_b2
-1
3
address_b1
-1
3
address_b0
-1
3
address_a6
-1
3
address_a5
-1
3
address_a4
-1
3
address_a3
-1
3
address_a2
-1
3
address_a1
-1
3
address_a0
-1
3
clocken0
-1
2
}
# include_file {
..|..|..|..|quartus60|libraries|megafunctions|aglobal60.inc
b3d07c643dae10ab2b3e646e99ec45fc
..|..|..|..|quartus60|libraries|megafunctions|stratix_ram_block.inc
2263a3bdfffeb150af977ee13902f70
..|..|..|..|quartus60|libraries|megafunctions|lpm_mux.inc
c22bfd353214c01495b560fc34e47d79
..|..|..|..|quartus60|libraries|megafunctions|lpm_decode.inc
bd0e2f5e01c1bd360461dceb53d48
..|..|..|..|quartus60|libraries|megafunctions|altsyncram.inc
2d485e3cf75d4048974bdbf0d920cb89
..|..|..|..|quartus60|libraries|megafunctions|a_rdenreg.inc
60d229340bc3c24acb0a137b4849830
..|..|..|..|quartus60|libraries|megafunctions|altrom.inc
d4e3a69a331d3a99d3281790d99a1ebd
..|..|..|..|quartus60|libraries|megafunctions|altram.inc
e66a83eccf6717bed97c99d891ad085
..|..|..|..|quartus60|libraries|megafunctions|altdpram.inc
4e1931f9814db9f22f22b9eb377c65d6
..|..|..|..|quartus60|libraries|megafunctions|altqpram.inc
74e08939f96a7ea8e7a4d59a5b01fe7
}
# hierarchies {
std_1c20:inst|cpu:the_cpu|cpu_ic_tag_module:cpu_ic_tag|altsyncram:the_altsyncram
}
# end
# entity
altsyncram
# storage
db|standard.(42).cnf
db|standard.(42).cnf
# case_insensitive
# source_file
..|..|..|..|quartus60|libraries|megafunctions|altsyncram.tdf
c9a54fc8e33741c15b27e3d74d615aff
6
# user_parameter {
BYTE_SIZE_BLOCK
8
PARAMETER_UNKNOWN
DEF
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
OPERATION_MODE
DUAL_PORT
PARAMETER_UNKNOWN
USR
WIDTH_A
32
PARAMETER_DEC
USR
WIDTHAD_A
5
PARAMETER_DEC
USR
NUMWORDS_A
32
PARAMETER_DEC
USR
OUTDATA_REG_A
UNREGISTERED
PARAMETER_UNKNOWN
DEF
ADDRESS_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
OUTDATA_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
WRCONTROL_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
INDATA_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
BYTEENA_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
WIDTH_B
32
PARAMETER_DEC
USR
WIDTHAD_B
5
PARAMETER_DEC
USR
NUMWORDS_B
32
PARAMETER_DEC
USR
INDATA_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
WRCONTROL_WRADDRESS_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
RDCONTROL_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
ADDRESS_REG_B
CLOCK1
PARAMETER_UNKNOWN
USR
OUTDATA_REG_B
UNREGISTERED
PARAMETER_UNKNOWN
USR
BYTEENA_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
INDATA_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
WRCONTROL_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
ADDRESS_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
OUTDATA_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
RDCONTROL_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
BYTEENA_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
WIDTH_BYTEENA_A
1
PARAMETER_UNKNOWN
DEF
WIDTH_BYTEENA_B
1
PARAMETER_UNKNOWN
DEF
RAM_BLOCK_TYPE
AUTO
PARAMETER_UNKNOWN
USR
BYTE_SIZE
8
PARAMETER_UNKNOWN
DEF
READ_DURING_WRITE_MODE_MIXED_PORTS
OLD_DATA
PARAMETER_UNKNOWN
USR
INIT_FILE
cpu_rf_ram_a.mif
PARAMETER_UNKNOWN
USR
INIT_FILE_LAYOUT
PORT_A
PARAMETER_UNKNOWN
DEF
MAXIMUM_DEPTH
0
PARAMETER_DEC
USR
CLOCK_ENABLE_INPUT_A
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_INPUT_B
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_OUTPUT_A
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_OUTPUT_B
NORMAL
PARAMETER_UNKNOWN
DEF
DEVICE_FAMILY
Cyclone
PARAMETER_UNKNOWN
USR
CBXI_PARAMETER
altsyncram_3vd1
PARAMETER_UNKNOWN
USR
}
# used_port {
wren_a
-1
3
q_b9
-1
3
q_b8
-1
3
q_b7
-1
3
q_b6
-1
3
q_b5
-1
3
q_b4
-1
3
q_b31
-1
3
q_b30
-1
3
q_b3
-1
3
q_b29
-1
3
q_b28
-1
3
q_b27
-1
3
q_b26
-1
3
q_b25
-1
3
q_b24
-1
3
q_b23
-1
3
q_b22
-1
3
q_b21
-1
3
q_b20
-1
3
q_b2
-1
3
q_b19
-1
3
q_b18
-1
3
q_b17
-1
3
q_b16
-1
3
q_b15
-1
3
q_b14
-1
3
q_b13
-1
3
q_b12
-1
3
q_b11
-1
3
q_b10
-1
3
q_b1
-1
3
q_b0
-1
3
data_a9
-1
3
data_a8
-1
3
data_a7
-1
3
data_a6
-1
3
data_a5
-1
3
data_a4
-1
3
data_a31
-1
3
data_a30
-1
3
data_a3
-1
3
data_a29
-1
3
data_a28
-1
3
data_a27
-1
3
data_a26
-1
3
data_a25
-1
3
data_a24
-1
3
data_a23
-1
3
data_a22
-1
3
data_a21
-1
3
data_a20
-1
3
data_a2
-1
3
data_a19
-1
3
data_a18
-1
3
data_a17
-1
3
data_a16
-1
3
data_a15
-1
3
data_a14
-1
3
data_a13
-1
3
data_a12
-1
3
data_a11
-1
3
data_a10
-1
3
data_a1
-1
3
data_a0
-1
3
clocken1
-1
3
clock1
-1
3
clock0
-1
3
address_b4
-1
3
address_b3
-1
3
address_b2
-1
3
address_b1
-1
3
address_b0
-1
3
address_a4
-1
3
address_a3
-1
3
address_a2
-1
3
address_a1
-1
3
address_a0
-1
3
clocken0
-1
2
}
# include_file {
..|..|..|..|quartus60|libraries|megafunctions|aglobal60.inc
b3d07c643dae10ab2b3e646e99ec45fc
..|..|..|..|quartus60|libraries|megafunctions|stratix_ram_block.inc
2263a3bdfffeb150af977ee13902f70
..|..|..|..|quartus60|libraries|megafunctions|lpm_mux.inc
c22bfd353214c01495b560fc34e47d79
..|..|..|..|quartus60|libraries|megafunctions|lpm_decode.inc
bd0e2f5e01c1bd360461dceb53d48
..|..|..|..|quartus60|libraries|megafunctions|altsyncram.inc
2d485e3cf75d4048974bdbf0d920cb89
..|..|..|..|quartus60|libraries|megafunctions|a_rdenreg.inc
60d229340bc3c24acb0a137b4849830
..|..|..|..|quartus60|libraries|megafunctions|altrom.inc
d4e3a69a331d3a99d3281790d99a1ebd
..|..|..|..|quartus60|libraries|megafunctions|altram.inc
e66a83eccf6717bed97c99d891ad085
..|..|..|..|quartus60|libraries|megafunctions|altdpram.inc
4e1931f9814db9f22f22b9eb377c65d6
..|..|..|..|quartus60|libraries|megafunctions|altqpram.inc
74e08939f96a7ea8e7a4d59a5b01fe7
}
# hierarchies {
std_1c20:inst|cpu:the_cpu|cpu_register_bank_a_module:cpu_register_bank_a|altsyncram:the_altsyncram
}
# end
# entity
altsyncram_3vd1
# storage
db|standard.(43).cnf
db|standard.(43).cnf
# case_insensitive
# source_file
db|altsyncram_3vd1.tdf
972bf5d1b6b2a91386440fff6cfcad
6
# user_parameter {
PORT_A_ADDRESS_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_A_BYTE_ENABLE_MASK_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_A_DATA_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_B_ADDRESS_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_B_BYTE_ENABLE_MASK_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_B_DATA_WIDTH
1
PARAMETER_UNKNOWN
DEF
}
# used_port {
wren_a
-1
3
q_b9
-1
3
q_b8
-1
3
q_b7
-1
3
q_b6
-1
3
q_b5
-1
3
q_b4
-1
3
q_b31
-1
3
q_b30
-1
3
q_b3
-1
3
q_b29
-1
3
q_b28
-1
3
q_b27
-1
3
q_b26
-1
3
q_b25
-1
3
q_b24
-1
3
q_b23
-1
3
q_b22
-1
3
q_b21
-1
3
q_b20
-1
3
q_b2
-1
3
q_b19
-1
3
q_b18
-1
3
q_b17
-1
3
q_b16
-1
3
q_b15
-1
3
q_b14
-1
3
q_b13
-1
3
q_b12
-1
3
q_b11
-1
3
q_b10
-1
3
q_b1
-1
3
q_b0
-1
3
data_a9
-1
3
data_a8
-1
3
data_a7
-1
3
data_a6
-1
3
data_a5
-1
3
data_a4
-1
3
data_a31
-1
3
data_a30
-1
3
data_a3
-1
3
data_a29
-1
3
data_a28
-1
3
data_a27
-1
3
data_a26
-1
3
data_a25
-1
3
data_a24
-1
3
data_a23
-1
3
data_a22
-1
3
data_a21
-1
3
data_a20
-1
3
data_a2
-1
3
data_a19
-1
3
data_a18
-1
3
data_a17
-1
3
data_a16
-1
3
data_a15
-1
3
data_a14
-1
3
data_a13
-1
3
data_a12
-1
3
data_a11
-1
3
data_a10
-1
3
data_a1
-1
3
data_a0
-1
3
clocken1
-1
3
clock1
-1
3
clock0
-1
3
address_b4
-1
3
address_b3
-1
3
address_b2
-1
3
address_b1
-1
3
address_b0
-1
3
address_a4
-1
3
address_a3
-1
3
address_a2
-1
3
address_a1
-1
3
address_a0
-1
3
}
# memory_file {
cpu_rf_ram_a.mif
55d713de4db17accc269d4dfa42c9c44
}
# hierarchies {
std_1c20:inst|cpu:the_cpu|cpu_register_bank_a_module:cpu_register_bank_a|altsyncram:the_altsyncram|altsyncram_3vd1:auto_generated
}
# end
# entity
altsyncram
# storage
db|standard.(45).cnf
db|standard.(45).cnf
# case_insensitive
# source_file
..|..|..|..|quartus60|libraries|megafunctions|altsyncram.tdf
c9a54fc8e33741c15b27e3d74d615aff
6
# user_parameter {
BYTE_SIZE_BLOCK
8
PARAMETER_UNKNOWN
DEF
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
OPERATION_MODE
DUAL_PORT
PARAMETER_UNKNOWN
USR
WIDTH_A
32
PARAMETER_DEC
USR
WIDTHAD_A
5
PARAMETER_DEC
USR
NUMWORDS_A
32
PARAMETER_DEC
USR
OUTDATA_REG_A
UNREGISTERED
PARAMETER_UNKNOWN
DEF
ADDRESS_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
OUTDATA_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
WRCONTROL_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
INDATA_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
BYTEENA_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
WIDTH_B
32
PARAMETER_DEC
USR
WIDTHAD_B
5
PARAMETER_DEC
USR
NUMWORDS_B
32
PARAMETER_DEC
USR
INDATA_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
WRCONTROL_WRADDRESS_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
RDCONTROL_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
ADDRESS_REG_B
CLOCK1
PARAMETER_UNKNOWN
USR
OUTDATA_REG_B
UNREGISTERED
PARAMETER_UNKNOWN
USR
BYTEENA_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
INDATA_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
WRCONTROL_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
ADDRESS_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
OUTDATA_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
RDCONTROL_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
BYTEENA_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
WIDTH_BYTEENA_A
1
PARAMETER_UNKNOWN
DEF
WIDTH_BYTEENA_B
1
PARAMETER_UNKNOWN
DEF
RAM_BLOCK_TYPE
AUTO
PARAMETER_UNKNOWN
USR
BYTE_SIZE
8
PARAMETER_UNKNOWN
DEF
READ_DURING_WRITE_MODE_MIXED_PORTS
OLD_DATA
PARAMETER_UNKNOWN
USR
INIT_FILE
cpu_rf_ram_b.mif
PARAMETER_UNKNOWN
USR
INIT_FILE_LAYOUT
PORT_A
PARAMETER_UNKNOWN
DEF
MAXIMUM_DEPTH
0
PARAMETER_DEC
USR
CLOCK_ENABLE_INPUT_A
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_INPUT_B
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_OUTPUT_A
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_OUTPUT_B
NORMAL
PARAMETER_UNKNOWN
DEF
DEVICE_FAMILY
Cyclone
PARAMETER_UNKNOWN
USR
CBXI_PARAMETER
altsyncram_4vd1
PARAMETER_UNKNOWN
USR
}
# used_port {
wren_a
-1
3
q_b9
-1
3
q_b8
-1
3
q_b7
-1
3
q_b6
-1
3
q_b5
-1
3
q_b4
-1
3
q_b31
-1
3
q_b30
-1
3
q_b3
-1
3
q_b29
-1
3
q_b28
-1
3
q_b27
-1
3
q_b26
-1
3
q_b25
-1
3
q_b24
-1
3
q_b23
-1
3
q_b22
-1
3
q_b21
-1
3
q_b20
-1
3
q_b2
-1
3
q_b19
-1
3
q_b18
-1
3
q_b17
-1
3
q_b16
-1
3
q_b15
-1
3
q_b14
-1
3
q_b13
-1
3
q_b12
-1
3
q_b11
-1
3
q_b10
-1
3
q_b1
-1
3
q_b0
-1
3
data_a9
-1
3
data_a8
-1
3
data_a7
-1
3
data_a6
-1
3
data_a5
-1
3
data_a4
-1
3
data_a31
-1
3
data_a30
-1
3
data_a3
-1
3
data_a29
-1
3
data_a28
-1
3
data_a27
-1
3
data_a26
-1
3
data_a25
-1
3
data_a24
-1
3
data_a23
-1
3
data_a22
-1
3
data_a21
-1
3
data_a20
-1
3
data_a2
-1
3
data_a19
-1
3
data_a18
-1
3
data_a17
-1
3
data_a16
-1
3
data_a15
-1
3
data_a14
-1
3
data_a13
-1
3
data_a12
-1
3
data_a11
-1
3
data_a10
-1
3
data_a1
-1
3
data_a0
-1
3
clocken1
-1
3
clock1
-1
3
clock0
-1
3
address_b4
-1
3
address_b3
-1
3
address_b2
-1
3
address_b1
-1
3
address_b0
-1
3
address_a4
-1
3
address_a3
-1
3
address_a2
-1
3
address_a1
-1
3
address_a0
-1
3
clocken0
-1
2
}
# include_file {
..|..|..|..|quartus60|libraries|megafunctions|aglobal60.inc
b3d07c643dae10ab2b3e646e99ec45fc
..|..|..|..|quartus60|libraries|megafunctions|stratix_ram_block.inc
2263a3bdfffeb150af977ee13902f70
..|..|..|..|quartus60|libraries|megafunctions|lpm_mux.inc
c22bfd353214c01495b560fc34e47d79
..|..|..|..|quartus60|libraries|megafunctions|lpm_decode.inc
bd0e2f5e01c1bd360461dceb53d48
..|..|..|..|quartus60|libraries|megafunctions|altsyncram.inc
2d485e3cf75d4048974bdbf0d920cb89
..|..|..|..|quartus60|libraries|megafunctions|a_rdenreg.inc
60d229340bc3c24acb0a137b4849830
..|..|..|..|quartus60|libraries|megafunctions|altrom.inc
d4e3a69a331d3a99d3281790d99a1ebd
..|..|..|..|quartus60|libraries|megafunctions|altram.inc
e66a83eccf6717bed97c99d891ad085
..|..|..|..|quartus60|libraries|megafunctions|altdpram.inc
4e1931f9814db9f22f22b9eb377c65d6
..|..|..|..|quartus60|libraries|megafunctions|altqpram.inc
74e08939f96a7ea8e7a4d59a5b01fe7
}
# hierarchies {
std_1c20:inst|cpu:the_cpu|cpu_register_bank_b_module:cpu_register_bank_b|altsyncram:the_altsyncram
}
# end
# entity
altsyncram_4vd1
# storage
db|standard.(46).cnf
db|standard.(46).cnf
# case_insensitive
# source_file
db|altsyncram_4vd1.tdf
6911f6a81e91d535a03e598a3470441
6
# user_parameter {
PORT_A_ADDRESS_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_A_BYTE_ENABLE_MASK_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_A_DATA_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_B_ADDRESS_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_B_BYTE_ENABLE_MASK_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_B_DATA_WIDTH
1
PARAMETER_UNKNOWN
DEF
}
# used_port {
wren_a
-1
3
q_b9
-1
3
q_b8
-1
3
q_b7
-1
3
q_b6
-1
3
q_b5
-1
3
q_b4
-1
3
q_b31
-1
3
q_b30
-1
3
q_b3
-1
3
q_b29
-1
3
q_b28
-1
3
q_b27
-1
3
q_b26
-1
3
q_b25
-1
3
q_b24
-1
3
q_b23
-1
3
q_b22
-1
3
q_b21
-1
3
q_b20
-1
3
q_b2
-1
3
q_b19
-1
3
q_b18
-1
3
q_b17
-1
3
q_b16
-1
3
q_b15
-1
3
q_b14
-1
3
q_b13
-1
3
q_b12
-1
3
q_b11
-1
3
q_b10
-1
3
q_b1
-1
3
q_b0
-1
3
data_a9
-1
3
data_a8
-1
3
data_a7
-1
3
data_a6
-1
3
data_a5
-1
3
data_a4
-1
3
data_a31
-1
3
data_a30
-1
3
data_a3
-1
3
data_a29
-1
3
data_a28
-1
3
data_a27
-1
3
data_a26
-1
3
data_a25
-1
3
data_a24
-1
3
data_a23
-1
3
data_a22
-1
3
data_a21
-1
3
data_a20
-1
3
data_a2
-1
3
data_a19
-1
3
data_a18
-1
3
data_a17
-1
3
data_a16
-1
3
data_a15
-1
3
data_a14
-1
3
data_a13
-1
3
data_a12
-1
3
data_a11
-1
3
data_a10
-1
3
data_a1
-1
3
data_a0
-1
3
clocken1
-1
3
clock1
-1
3
clock0
-1
3
address_b4
-1
3
address_b3
-1
3
address_b2
-1
3
address_b1
-1
3
address_b0
-1
3
address_a4
-1
3
address_a3
-1
3
address_a2
-1
3
address_a1
-1
3
address_a0
-1
3
}
# memory_file {
cpu_rf_ram_b.mif
55d713de4db17accc269d4dfa42c9c44
}
# hierarchies {
std_1c20:inst|cpu:the_cpu|cpu_register_bank_b_module:cpu_register_bank_b|altsyncram:the_altsyncram|altsyncram_4vd1:auto_generated
}
# end
# entity
altsyncram
# storage
db|standard.(51).cnf
db|standard.(51).cnf
# case_insensitive
# source_file
..|..|..|..|quartus60|libraries|megafunctions|altsyncram.tdf
c9a54fc8e33741c15b27e3d74d615aff
6
# user_parameter {
BYTE_SIZE_BLOCK
8
PARAMETER_UNKNOWN
DEF
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
OPERATION_MODE
BIDIR_DUAL_PORT
PARAMETER_UNKNOWN
USR
WIDTH_A
32
PARAMETER_DEC
USR
WIDTHAD_A
8
PARAMETER_DEC
USR
NUMWORDS_A
256
PARAMETER_DEC
USR
OUTDATA_REG_A
UNREGISTERED
PARAMETER_UNKNOWN
USR
ADDRESS_ACLR_A
NONE
PARAMETER_UNKNOWN
USR
OUTDATA_ACLR_A
NONE
PARAMETER_UNKNOWN
USR
WRCONTROL_ACLR_A
NONE
PARAMETER_UNKNOWN
USR
INDATA_ACLR_A
NONE
PARAMETER_UNKNOWN
USR
BYTEENA_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
WIDTH_B
32
PARAMETER_DEC
USR
WIDTHAD_B
8
PARAMETER_DEC
USR
NUMWORDS_B
256
PARAMETER_DEC
USR
INDATA_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
WRCONTROL_WRADDRESS_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
RDCONTROL_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
ADDRESS_REG_B
CLOCK1
PARAMETER_UNKNOWN
USR
OUTDATA_REG_B
UNREGISTERED
PARAMETER_UNKNOWN
USR
BYTEENA_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
INDATA_ACLR_B
NONE
PARAMETER_UNKNOWN
USR
WRCONTROL_ACLR_B
NONE
PARAMETER_UNKNOWN
USR
ADDRESS_ACLR_B
NONE
PARAMETER_UNKNOWN
USR
OUTDATA_ACLR_B
NONE
PARAMETER_UNKNOWN
USR
RDCONTROL_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
BYTEENA_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
WIDTH_BYTEENA_A
4
PARAMETER_DEC
USR
WIDTH_BYTEENA_B
1
PARAMETER_UNKNOWN
DEF
RAM_BLOCK_TYPE
AUTO
PARAMETER_UNKNOWN
USR
BYTE_SIZE
8
PARAMETER_UNKNOWN
DEF
READ_DURING_WRITE_MODE_MIXED_PORTS
OLD_DATA
PARAMETER_UNKNOWN
USR
INIT_FILE
cpu_ociram_default_contents.mif
PARAMETER_UNKNOWN
USR
INIT_FILE_LAYOUT
PORT_A
PARAMETER_UNKNOWN
DEF
MAXIMUM_DEPTH
0
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_INPUT_A
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_INPUT_B
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_OUTPUT_A
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_OUTPUT_B
NORMAL
PARAMETER_UNKNOWN
DEF
DEVICE_FAMILY
Cyclone
PARAMETER_UNKNOWN
USR
CBXI_PARAMETER
altsyncram_bp62
PARAMETER_UNKNOWN
USR
}
# used_port {
wren_b
-1
3
wren_a
-1
3
q_b9
-1
3
q_b8
-1
3
q_b7
-1
3
q_b6
-1
3
q_b5
-1
3
q_b4
-1
3
q_b31
-1
3
q_b30
-1
3
q_b3
-1
3
q_b29
-1
3
q_b28
-1
3
q_b27
-1
3
q_b26
-1
3
q_b25
-1
3
q_b24
-1
3
q_b23
-1
3
q_b22
-1
3
q_b21
-1
3
q_b20
-1
3
q_b2
-1
3
q_b19
-1
3
q_b18
-1
3
q_b17
-1
3
q_b16
-1
3
q_b15
-1
3
q_b14
-1
3
q_b13
-1
3
q_b12
-1
3
q_b11
-1
3
q_b10
-1
3
q_b1
-1
3
q_b0
-1
3
q_a9
-1
3
q_a8
-1
3
q_a7
-1
3
q_a6
-1
3
q_a5
-1
3
q_a4
-1
3
q_a31
-1
3
q_a30
-1
3
q_a3
-1
3
q_a29
-1
3
q_a28
-1
3
q_a27
-1
3
q_a26
-1
3
q_a25
-1
3
q_a24
-1
3
q_a23
-1
3
q_a22
-1
3
q_a21
-1
3
q_a20
-1
3
q_a2
-1
3
q_a19
-1
3
q_a18
-1
3
q_a17
-1
3
q_a16
-1
3
q_a15
-1
3
q_a14
-1
3
q_a13
-1
3
q_a12
-1
3
q_a11
-1
3
q_a10
-1
3
q_a1
-1
3
q_a0
-1
3
data_b9
-1
3
data_b8
-1
3
data_b7
-1
3
data_b6
-1
3
data_b5
-1
3
data_b4
-1
3
data_b31
-1
3
data_b30
-1
3
data_b3
-1
3
data_b29
-1
3
data_b28
-1
3
data_b27
-1
3
data_b26
-1
3
data_b25
-1
3
data_b24
-1
3
data_b23
-1
3
data_b22
-1
3
data_b21
-1
3
data_b20
-1
3
data_b2
-1
3
data_b19
-1
3
data_b18
-1
3
data_b17
-1
3
data_b16
-1
3
data_b15
-1
3
data_b14
-1
3
data_b13
-1
3
data_b12
-1
3
data_b11
-1
3
data_b10
-1
3
data_b1
-1
3
data_b0
-1
3
data_a9
-1
3
data_a8
-1
3
data_a7
-1
3
data_a6
-1
3
data_a5
-1
3
data_a4
-1
3
data_a31
-1
3
data_a30
-1
3
data_a3
-1
3
data_a29
-1
3
data_a28
-1
3
data_a27
-1
3
data_a26
-1
3
data_a25
-1
3
data_a24
-1
3
data_a23
-1
3
data_a22
-1
3
data_a21
-1
3
data_a20
-1
3
data_a2
-1
3
data_a19
-1
3
data_a18
-1
3
data_a17
-1
3
data_a16
-1
3
data_a15
-1
3
data_a14
-1
3
data_a13
-1
3
data_a12
-1
3
data_a11
-1
3
data_a10
-1
3
data_a1
-1
3
data_a0
-1
3
clocken1
-1
3
clocken0
-1
3
clock1
-1
3
clock0
-1
3
byteena_a3
-1
3
byteena_a2
-1
3
byteena_a1
-1
3
byteena_a0
-1
3
address_b7
-1
3
address_b6
-1
3
address_b5
-1
3
address_b4
-1
3
address_b3
-1
3
address_b2
-1
3
address_b1
-1
3
address_b0
-1
3
address_a7
-1
3
address_a6
-1
3
address_a5
-1
3
address_a4
-1
3
address_a3
-1
3
address_a2
-1
3
address_a1
-1
3
address_a0
-1
3
}
# include_file {
..|..|..|..|quartus60|libraries|megafunctions|aglobal60.inc
b3d07c643dae10ab2b3e646e99ec45fc
..|..|..|..|quartus60|libraries|megafunctions|stratix_ram_block.inc
2263a3bdfffeb150af977ee13902f70
..|..|..|..|quartus60|libraries|megafunctions|lpm_mux.inc
c22bfd353214c01495b560fc34e47d79
..|..|..|..|quartus60|libraries|megafunctions|lpm_decode.inc
bd0e2f5e01c1bd360461dceb53d48
..|..|..|..|quartus60|libraries|megafunctions|altsyncram.inc
2d485e3cf75d4048974bdbf0d920cb89
..|..|..|..|quartus60|libraries|megafunctions|a_rdenreg.inc
60d229340bc3c24acb0a137b4849830
..|..|..|..|quartus60|libraries|megafunctions|altrom.inc
d4e3a69a331d3a99d3281790d99a1ebd
..|..|..|..|quartus60|libraries|megafunctions|altram.inc
e66a83eccf6717bed97c99d891ad085
..|..|..|..|quartus60|libraries|megafunctions|altdpram.inc
4e1931f9814db9f22f22b9eb377c65d6
..|..|..|..|quartus60|libraries|megafunctions|altqpram.inc
74e08939f96a7ea8e7a4d59a5b01fe7
}
# hierarchies {
std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|cpu_ociram_lpm_dram_bdp_component_module:cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram
}
# end
# entity
altsyncram
# storage
db|standard.(69).cnf
db|standard.(69).cnf
# case_insensitive
# source_file
..|..|..|..|quartus60|libraries|megafunctions|altsyncram.tdf
c9a54fc8e33741c15b27e3d74d615aff
6
# user_parameter {
BYTE_SIZE_BLOCK
8
PARAMETER_UNKNOWN
DEF
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
OPERATION_MODE
BIDIR_DUAL_PORT
PARAMETER_UNKNOWN
USR
WIDTH_A
36
PARAMETER_DEC
USR
WIDTHAD_A
7
PARAMETER_DEC
USR
NUMWORDS_A
128
PARAMETER_DEC
USR
OUTDATA_REG_A
UNREGISTERED
PARAMETER_UNKNOWN
USR
ADDRESS_ACLR_A
NONE
PARAMETER_UNKNOWN
USR
OUTDATA_ACLR_A
NONE
PARAMETER_UNKNOWN
USR
WRCONTROL_ACLR_A
NONE
PARAMETER_UNKNOWN
USR
INDATA_ACLR_A
NONE
PARAMETER_UNKNOWN
USR
BYTEENA_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
WIDTH_B
36
PARAMETER_DEC
USR
WIDTHAD_B
7
PARAMETER_DEC
USR
NUMWORDS_B
128
PARAMETER_DEC
USR
INDATA_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
WRCONTROL_WRADDRESS_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
RDCONTROL_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
ADDRESS_REG_B
CLOCK1
PARAMETER_UNKNOWN
USR
OUTDATA_REG_B
UNREGISTERED
PARAMETER_UNKNOWN
USR
BYTEENA_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
INDATA_ACLR_B
NONE
PARAMETER_UNKNOWN
USR
WRCONTROL_ACLR_B
NONE
PARAMETER_UNKNOWN
USR
ADDRESS_ACLR_B
NONE
PARAMETER_UNKNOWN
USR
OUTDATA_ACLR_B
NONE
PARAMETER_UNKNOWN
USR
RDCONTROL_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
BYTEENA_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
WIDTH_BYTEENA_A
1
PARAMETER_UNKNOWN
DEF
WIDTH_BYTEENA_B
1
PARAMETER_UNKNOWN
DEF
RAM_BLOCK_TYPE
AUTO
PARAMETER_UNKNOWN
USR
BYTE_SIZE
8
PARAMETER_UNKNOWN
DEF
READ_DURING_WRITE_MODE_MIXED_PORTS
OLD_DATA
PARAMETER_UNKNOWN
USR
INIT_FILE

PARAMETER_UNKNOWN
USR
INIT_FILE_LAYOUT
PORT_A
PARAMETER_UNKNOWN
DEF
MAXIMUM_DEPTH
0
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_INPUT_A
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_INPUT_B
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_OUTPUT_A
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_OUTPUT_B
NORMAL
PARAMETER_UNKNOWN
DEF
DEVICE_FAMILY
Cyclone
PARAMETER_UNKNOWN
USR
CBXI_PARAMETER
altsyncram_stv1
PARAMETER_UNKNOWN
USR
}
# used_port {
wren_b
-1
3
wren_a
-1
3
q_b9
-1
3
q_b8
-1
3
q_b7
-1
3
q_b6
-1
3
q_b5
-1
3
q_b4
-1
3
q_b35
-1
3
q_b34
-1
3
q_b33
-1
3
q_b32
-1
3
q_b31
-1
3
q_b30
-1
3
q_b3
-1
3
q_b29
-1
3
q_b28
-1
3
q_b27
-1
3
q_b26
-1
3
q_b25
-1
3
q_b24
-1
3
q_b23
-1
3
q_b22
-1
3
q_b21
-1
3
q_b20
-1
3
q_b2
-1
3
q_b19
-1
3
q_b18
-1
3
q_b17
-1
3
q_b16
-1
3
q_b15
-1
3
q_b14
-1
3
q_b13
-1
3
q_b12
-1
3
q_b11
-1
3
q_b10
-1
3
q_b1
-1
3
q_b0
-1
3
q_a9
-1
3
q_a8
-1
3
q_a7
-1
3
q_a6
-1
3
q_a5
-1
3
q_a4
-1
3
q_a35
-1
3
q_a34
-1
3
q_a33
-1
3
q_a32
-1
3
q_a31
-1
3
q_a30
-1
3
q_a3
-1
3
q_a29
-1
3
q_a28
-1
3
q_a27
-1
3
q_a26
-1
3
q_a25
-1
3
q_a24
-1
3
q_a23
-1
3
q_a22
-1
3
q_a21
-1
3
q_a20
-1
3
q_a2
-1
3
q_a19
-1
3
q_a18
-1
3
q_a17
-1
3
q_a16
-1
3
q_a15
-1
3
q_a14
-1
3
q_a13
-1
3
q_a12
-1
3
q_a11
-1
3
q_a10
-1
3
q_a1
-1
3
q_a0
-1
3
data_b9
-1
3
data_b8
-1
3
data_b7
-1
3
data_b6
-1
3
data_b5
-1
3
data_b4
-1
3
data_b35
-1
3
data_b34
-1
3
data_b33
-1
3
data_b32
-1
3
data_b31
-1
3
data_b30
-1
3
data_b3
-1
3
data_b29
-1
3
data_b28
-1
3
data_b27
-1
3
data_b26
-1
3
data_b25
-1
3
data_b24
-1
3
data_b23
-1
3
data_b22
-1
3
data_b21
-1
3
data_b20
-1
3
data_b2
-1
3
data_b19
-1
3
data_b18
-1
3
data_b17
-1
3
data_b16
-1
3
data_b15
-1
3
data_b14
-1
3
data_b13
-1
3
data_b12
-1
3
data_b11
-1
3
data_b10
-1
3
data_b1
-1
3
data_b0
-1
3
data_a9
-1
3
data_a8
-1
3
data_a7
-1
3
data_a6
-1
3
data_a5
-1
3
data_a4
-1
3
data_a35
-1
3
data_a34
-1
3
data_a33
-1
3
data_a32
-1
3
data_a31
-1
3
data_a30
-1
3
data_a3
-1
3
data_a29
-1
3
data_a28
-1
3
data_a27
-1
3
data_a26
-1
3
data_a25
-1
3
data_a24
-1
3
data_a23
-1
3
data_a22
-1
3
data_a21
-1
3
data_a20
-1
3
data_a2
-1
3
data_a19
-1
3
data_a18
-1
3
data_a17
-1
3
data_a16
-1
3
data_a15
-1
3
data_a14
-1
3
data_a13
-1
3
data_a12
-1
3
data_a11
-1
3
data_a10
-1
3
data_a1
-1
3
data_a0
-1
3
clocken1
-1
3
clocken0
-1
3
clock1
-1
3
clock0
-1
3
address_b6
-1
3
address_b5
-1
3
address_b4
-1
3
address_b3
-1
3
address_b2
-1
3
address_b1
-1
3
address_b0
-1
3
address_a6
-1
3
address_a5
-1
3
address_a4
-1
3
address_a3
-1
3
address_a2
-1
3
address_a1
-1
3
address_a0
-1
3
}
# include_file {
..|..|..|..|quartus60|libraries|megafunctions|aglobal60.inc
b3d07c643dae10ab2b3e646e99ec45fc
..|..|..|..|quartus60|libraries|megafunctions|stratix_ram_block.inc
2263a3bdfffeb150af977ee13902f70
..|..|..|..|quartus60|libraries|megafunctions|lpm_mux.inc
c22bfd353214c01495b560fc34e47d79
..|..|..|..|quartus60|libraries|megafunctions|lpm_decode.inc
bd0e2f5e01c1bd360461dceb53d48
..|..|..|..|quartus60|libraries|megafunctions|altsyncram.inc
2d485e3cf75d4048974bdbf0d920cb89
..|..|..|..|quartus60|libraries|megafunctions|a_rdenreg.inc
60d229340bc3c24acb0a137b4849830
..|..|..|..|quartus60|libraries|megafunctions|altrom.inc
d4e3a69a331d3a99d3281790d99a1ebd
..|..|..|..|quartus60|libraries|megafunctions|altram.inc
e66a83eccf6717bed97c99d891ad085
..|..|..|..|quartus60|libraries|megafunctions|altdpram.inc
4e1931f9814db9f22f22b9eb377c65d6
..|..|..|..|quartus60|libraries|megafunctions|altqpram.inc
74e08939f96a7ea8e7a4d59a5b01fe7
}
# hierarchies {
std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_im:the_cpu_nios2_oci_im|cpu_traceram_lpm_dram_bdp_component_module:cpu_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram
}
# end
# entity
altsyncram_stv1
# storage
db|standard.(70).cnf
db|standard.(70).cnf
# case_insensitive
# source_file
db|altsyncram_stv1.tdf
a764528a5fddace13259d1ded199c
6
# user_parameter {
PORT_A_ADDRESS_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_A_BYTE_ENABLE_MASK_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_A_DATA_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_B_ADDRESS_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_B_BYTE_ENABLE_MASK_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_B_DATA_WIDTH
1
PARAMETER_UNKNOWN
DEF
}
# used_port {
wren_b
-1
3
wren_a
-1
3
q_b9
-1
3
q_b8
-1
3
q_b7
-1
3
q_b6
-1
3
q_b5
-1
3
q_b4
-1
3
q_b35
-1
3
q_b34
-1
3
q_b33
-1
3
q_b32
-1
3
q_b31
-1
3
q_b30
-1
3
q_b3
-1
3
q_b29
-1
3
q_b28
-1
3
q_b27
-1
3
q_b26
-1
3
q_b25
-1
3
q_b24
-1
3
q_b23
-1
3
q_b22
-1
3
q_b21
-1
3
q_b20
-1
3
q_b2
-1
3
q_b19
-1
3
q_b18
-1
3
q_b17
-1
3
q_b16
-1
3
q_b15
-1
3
q_b14
-1
3
q_b13
-1
3
q_b12
-1
3
q_b11
-1
3
q_b10
-1
3
q_b1
-1
3
q_b0
-1
3
q_a9
-1
3
q_a8
-1
3
q_a7
-1
3
q_a6
-1
3
q_a5
-1
3
q_a4
-1
3
q_a35
-1
3
q_a34
-1
3
q_a33
-1
3
q_a32
-1
3
q_a31
-1
3
q_a30
-1
3
q_a3
-1
3
q_a29
-1
3
q_a28
-1
3
q_a27
-1
3
q_a26
-1
3
q_a25
-1
3
q_a24
-1
3
q_a23
-1
3
q_a22
-1
3
q_a21
-1
3
q_a20
-1
3
q_a2
-1
3
q_a19
-1
3
q_a18
-1
3
q_a17
-1
3
q_a16
-1
3
q_a15
-1
3
q_a14
-1
3
q_a13
-1
3
q_a12
-1
3
q_a11
-1
3
q_a10
-1
3
q_a1
-1
3
q_a0
-1
3
data_b9
-1
3
data_b8
-1
3
data_b7
-1
3
data_b6
-1
3
data_b5
-1
3
data_b4
-1
3
data_b35
-1
3
data_b34
-1
3
data_b33
-1
3
data_b32
-1
3
data_b31
-1
3
data_b30
-1
3
data_b3
-1
3
data_b29
-1
3
data_b28
-1
3
data_b27
-1
3
data_b26
-1
3
data_b25
-1
3
data_b24
-1
3
data_b23
-1
3
data_b22
-1
3
data_b21
-1
3
data_b20
-1
3
data_b2
-1
3
data_b19
-1
3
data_b18
-1
3
data_b17
-1
3
data_b16
-1
3
data_b15
-1
3
data_b14
-1
3
data_b13
-1
3
data_b12
-1
3
data_b11
-1
3
data_b10
-1
3
data_b1
-1
3
data_b0
-1
3
data_a9
-1
3
data_a8
-1
3
data_a7
-1
3
data_a6
-1
3
data_a5
-1
3
data_a4
-1
3
data_a35
-1
3
data_a34
-1
3
data_a33
-1
3
data_a32
-1
3
data_a31
-1
3
data_a30
-1
3
data_a3
-1
3
data_a29
-1
3
data_a28
-1
3
data_a27
-1
3
data_a26
-1
3
data_a25
-1
3
data_a24
-1
3
data_a23
-1
3
data_a22
-1
3
data_a21
-1
3
data_a20
-1
3
data_a2
-1
3
data_a19
-1
3
data_a18
-1
3
data_a17
-1
3
data_a16
-1
3
data_a15
-1
3
data_a14
-1
3
data_a13
-1
3
data_a12
-1
3
data_a11
-1
3
data_a10
-1
3
data_a1
-1
3
data_a0
-1
3
clocken1
-1
3
clocken0
-1
3
clock1
-1
3
clock0
-1
3
address_b6
-1
3
address_b5
-1
3
address_b4
-1
3
address_b3
-1
3
address_b2
-1
3
address_b1
-1
3
address_b0
-1
3
address_a6
-1
3
address_a5
-1
3
address_a4
-1
3
address_a3
-1
3
address_a2
-1
3
address_a1
-1
3
address_a0
-1
3
}
# memory_file {
none
0
}
# hierarchies {
std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_im:the_cpu_nios2_oci_im|cpu_traceram_lpm_dram_bdp_component_module:cpu_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_stv1:auto_generated
}
# end
# entity
altsyncram
# storage
db|standard.(77).cnf
db|standard.(77).cnf
# case_insensitive
# source_file
..|..|..|..|quartus60|libraries|megafunctions|altsyncram.tdf
c9a54fc8e33741c15b27e3d74d615aff
6
# user_parameter {
BYTE_SIZE_BLOCK
8
PARAMETER_UNKNOWN
DEF
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
OPERATION_MODE
ROM
PARAMETER_UNKNOWN
USR
WIDTH_A
32
PARAMETER_DEC
USR
WIDTHAD_A
7
PARAMETER_DEC
USR
NUMWORDS_A
128
PARAMETER_DEC
USR
OUTDATA_REG_A
UNREGISTERED
PARAMETER_UNKNOWN
USR
ADDRESS_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
OUTDATA_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
WRCONTROL_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
INDATA_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
BYTEENA_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
WIDTH_B
1
PARAMETER_UNKNOWN
DEF
WIDTHAD_B
1
PARAMETER_UNKNOWN
DEF
NUMWORDS_B
1
PARAMETER_UNKNOWN
DEF
INDATA_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
WRCONTROL_WRADDRESS_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
RDCONTROL_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
ADDRESS_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
OUTDATA_REG_B
UNREGISTERED
PARAMETER_UNKNOWN
DEF
BYTEENA_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
INDATA_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
WRCONTROL_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
ADDRESS_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
OUTDATA_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
RDCONTROL_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
BYTEENA_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
WIDTH_BYTEENA_A
1
PARAMETER_UNKNOWN
DEF
WIDTH_BYTEENA_B
1
PARAMETER_UNKNOWN
DEF
RAM_BLOCK_TYPE
AUTO
PARAMETER_UNKNOWN
DEF
BYTE_SIZE
8
PARAMETER_DEC
USR
READ_DURING_WRITE_MODE_MIXED_PORTS
DONT_CARE
PARAMETER_UNKNOWN
USR
INIT_FILE
epcs_controller_boot_rom.hex
PARAMETER_UNKNOWN
USR
INIT_FILE_LAYOUT
PORT_A
PARAMETER_UNKNOWN
DEF
MAXIMUM_DEPTH
0
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_INPUT_A
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_INPUT_B
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_OUTPUT_A
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_OUTPUT_B
NORMAL
PARAMETER_UNKNOWN
DEF
DEVICE_FAMILY
Cyclone
PARAMETER_UNKNOWN
USR
CBXI_PARAMETER
altsyncram_3h31
PARAMETER_UNKNOWN
USR
}
# used_port {
q_a9
-1
3
q_a8
-1
3
q_a7
-1
3
q_a6
-1
3
q_a5
-1
3
q_a4
-1
3
q_a31
-1
3
q_a30
-1
3
q_a3
-1
3
q_a29
-1
3
q_a28
-1
3
q_a27
-1
3
q_a26
-1
3
q_a25
-1
3
q_a24
-1
3
q_a23
-1
3
q_a22
-1
3
q_a21
-1
3
q_a20
-1
3
q_a2
-1
3
q_a19
-1
3
q_a18
-1
3
q_a17
-1
3
q_a16
-1
3
q_a15
-1
3
q_a14
-1
3
q_a13
-1
3
q_a12
-1
3
q_a11
-1
3
q_a10
-1
3
q_a1
-1
3
q_a0
-1
3
clock0
-1
3
address_a6
-1
3
address_a5
-1
3
address_a4
-1
3
address_a3
-1
3
address_a2
-1
3
address_a1
-1
3
address_a0
-1
3
}
# include_file {
..|..|..|..|quartus60|libraries|megafunctions|aglobal60.inc
b3d07c643dae10ab2b3e646e99ec45fc
..|..|..|..|quartus60|libraries|megafunctions|stratix_ram_block.inc
2263a3bdfffeb150af977ee13902f70
..|..|..|..|quartus60|libraries|megafunctions|lpm_mux.inc
c22bfd353214c01495b560fc34e47d79
..|..|..|..|quartus60|libraries|megafunctions|lpm_decode.inc
bd0e2f5e01c1bd360461dceb53d48
..|..|..|..|quartus60|libraries|megafunctions|altsyncram.inc
2d485e3cf75d4048974bdbf0d920cb89
..|..|..|..|quartus60|libraries|megafunctions|a_rdenreg.inc
60d229340bc3c24acb0a137b4849830
..|..|..|..|quartus60|libraries|megafunctions|altrom.inc
d4e3a69a331d3a99d3281790d99a1ebd
..|..|..|..|quartus60|libraries|megafunctions|altram.inc
e66a83eccf6717bed97c99d891ad085
..|..|..|..|quartus60|libraries|megafunctions|altdpram.inc
4e1931f9814db9f22f22b9eb377c65d6
..|..|..|..|quartus60|libraries|megafunctions|altqpram.inc
74e08939f96a7ea8e7a4d59a5b01fe7
}
# hierarchies {
std_1c20:inst|epcs_controller:the_epcs_controller|altsyncram:the_boot_copier_rom
}
# end
# entity
altsyncram_3h31
# storage
db|standard.(78).cnf
db|standard.(78).cnf
# case_insensitive
# source_file
db|altsyncram_3h31.tdf
5ab26ca1aff84f319386be1a63fe81
6
# user_parameter {
PORT_A_ADDRESS_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_A_BYTE_ENABLE_MASK_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_A_DATA_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_B_ADDRESS_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_B_BYTE_ENABLE_MASK_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_B_DATA_WIDTH
1
PARAMETER_UNKNOWN
DEF
}
# used_port {
q_a9
-1
3
q_a8
-1
3
q_a7
-1
3
q_a6
-1
3
q_a5
-1
3
q_a4
-1
3
q_a31
-1
3
q_a30
-1
3
q_a3
-1
3
q_a29
-1
3
q_a28
-1
3
q_a27
-1
3
q_a26
-1
3
q_a25
-1
3
q_a24
-1
3
q_a23
-1
3
q_a22
-1
3
q_a21
-1
3
q_a20
-1
3
q_a2
-1
3
q_a19
-1
3
q_a18
-1
3
q_a17
-1
3
q_a16
-1
3
q_a15
-1
3
q_a14
-1
3
q_a13
-1
3
q_a12
-1
3
q_a11
-1
3
q_a10
-1
3
q_a1
-1
3
q_a0
-1
3
clock0
-1
3
address_a6
-1
3
address_a5
-1
3
address_a4
-1
3
address_a3
-1
3
address_a2
-1
3
address_a1
-1
3
address_a0
-1
3
}
# memory_file {
epcs_controller_boot_rom.hex
d86d17f199903c5cf264c7b2416f745
}
# hierarchies {
std_1c20:inst|epcs_controller:the_epcs_controller|altsyncram:the_boot_copier_rom|altsyncram_3h31:auto_generated
}
# end
# entity
high_res_timer
# storage
db|standard.(81).cnf
db|standard.(81).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
high_res_timer.vhd
a621baa1db5d17eb73d192d43293d82
4
# internal_option {
AUTO_RESOURCE_SHARING
OFF
}
# user_parameter {
 constraint(address)
2 downto 0
PARAMETER_STRING
USR
 constraint(writedata)
15 downto 0
PARAMETER_STRING
USR
 constraint(readdata)
15 downto 0
PARAMETER_STRING
USR
}
# hierarchies {
std_1c20:inst|high_res_timer:the_high_res_timer
}
# end
# entity
scfifo
# storage
db|standard.(85).cnf
db|standard.(85).cnf
# case_insensitive
# source_file
..|..|..|..|quartus60|libraries|megafunctions|scfifo.tdf
b67e14bc943b20b2659e8ef1077457
6
# user_parameter {
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
lpm_width
8
PARAMETER_DEC
USR
LPM_NUMWORDS
64
PARAMETER_DEC
USR
LPM_WIDTHU
6
PARAMETER_DEC
USR
LPM_SHOWAHEAD
OFF
PARAMETER_UNKNOWN
USR
UNDERFLOW_CHECKING
OFF
PARAMETER_UNKNOWN
USR
OVERFLOW_CHECKING
OFF
PARAMETER_UNKNOWN
USR
ALLOW_RWCYCLE_WHEN_FULL
OFF
PARAMETER_UNKNOWN
DEF
ADD_RAM_OUTPUT_REGISTER
OFF
PARAMETER_UNKNOWN
DEF
ALMOST_FULL_VALUE
0
PARAMETER_UNKNOWN
DEF
ALMOST_EMPTY_VALUE
0
PARAMETER_UNKNOWN
DEF
USE_EAB
ON
PARAMETER_UNKNOWN
USR
MAXIMIZE_SPEED
5
PARAMETER_UNKNOWN
DEF
DEVICE_FAMILY
Cyclone
PARAMETER_UNKNOWN
USR
OPTIMIZE_FOR_SPEED
9
PARAMETER_UNKNOWN
USR
CBXI_PARAMETER
scfifo_jf21
PARAMETER_UNKNOWN
USR
}
# used_port {
wrreq
-1
3
usedw5
-1
3
usedw4
-1
3
usedw3
-1
3
usedw2
-1
3
usedw1
-1
3
usedw0
-1
3
rdreq
-1
3
q7
-1
3
q6
-1
3
q5
-1
3
q4
-1
3
q3
-1
3
q2
-1
3
q1
-1
3
q0
-1
3
full
-1
3
empty
-1
3
data7
-1
3
data6
-1
3
data5
-1
3
data4
-1
3
data3
-1
3
data2
-1
3
data1
-1
3
data0
-1
3
clock
-1
3
aclr
-1
3
}
# include_file {
..|..|..|..|quartus60|libraries|megafunctions|aglobal60.inc
b3d07c643dae10ab2b3e646e99ec45fc
..|..|..|..|quartus60|libraries|megafunctions|a_regfifo.inc
afe6bfc54c15224ce61beaea9e71dc
..|..|..|..|quartus60|libraries|megafunctions|a_dpfifo.inc
748303753a041187a5d4113b5f62acf
..|..|..|..|quartus60|libraries|megafunctions|a_i2fifo.inc
ca5bb76c5a51df22b24c8b01cbcc918
..|..|..|..|quartus60|libraries|megafunctions|a_fffifo.inc
ebf62e69b8fb10b5db33a57861298d55
..|..|..|..|quartus60|libraries|megafunctions|a_f2fifo.inc
9bc132bd4e9e2ef1fb9633f6a742f
}
# hierarchies {
std_1c20:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_w:the_jtag_uart_scfifo_w|scfifo:wfifo
std_1c20:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_r:the_jtag_uart_scfifo_r|scfifo:rfifo
}
# end
# entity
scfifo_jf21
# storage
db|standard.(86).cnf
db|standard.(86).cnf
# case_insensitive
# source_file
db|scfifo_jf21.tdf
a363b854fa46e4ad521cdadca23712
6
# used_port {
wrreq
-1
3
usedw5
-1
3
usedw4
-1
3
usedw3
-1
3
usedw2
-1
3
usedw1
-1
3
usedw0
-1
3
rdreq
-1
3
q7
-1
3
q6
-1
3
q5
-1
3
q4
-1
3
q3
-1
3
q2
-1
3
q1
-1
3
q0
-1
3
full
-1
3
empty
-1
3
data7
-1
3
data6
-1
3
data5
-1
3
data4
-1
3
data3
-1
3
data2
-1
3
data1
-1
3
data0
-1
3
clock
-1
3
aclr
-1
3
}
# hierarchies {
std_1c20:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_w:the_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_jf21:auto_generated
std_1c20:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_r:the_jtag_uart_scfifo_r|scfifo:rfifo|scfifo_jf21:auto_generated
}
# end
# entity
a_dpfifo_ml21
# storage
db|standard.(87).cnf
db|standard.(87).cnf
# case_insensitive
# source_file
db|a_dpfifo_ml21.tdf
4aeef459a0a4fa4a75f89859a8617819
6
# used_port {
wreq
-1
3
usedw5
-1
3
usedw4
-1
3
usedw3
-1
3
usedw2
-1
3
usedw1
-1
3
usedw0
-1
3
sclr
-1
3
rreq
-1
3
q7
-1
3
q6
-1
3
q5
-1
3
q4
-1
3
q3
-1
3
q2
-1
3
q1
-1
3
q0
-1
3
full
-1
3
empty
-1
3
data7
-1
3
data6
-1
3
data5
-1
3
data4
-1
3
data3
-1
3
data2
-1
3
data1
-1
3
data0
-1
3
clock
-1
3
aclr
-1
3
}
# hierarchies {
std_1c20:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_w:the_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_jf21:auto_generated|a_dpfifo_ml21:dpfifo
std_1c20:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_r:the_jtag_uart_scfifo_r|scfifo:rfifo|scfifo_jf21:auto_generated|a_dpfifo_ml21:dpfifo
}
# end
# entity
a_fefifo_7cf
# storage
db|standard.(88).cnf
db|standard.(88).cnf
# case_insensitive
# source_file
db|a_fefifo_7cf.tdf
119533e147462484aa03f899d6683e8
6
# used_port {
wreq
-1
3
usedw_out5
-1
3
usedw_out4
-1
3
usedw_out3
-1
3
usedw_out2
-1
3
usedw_out1
-1
3
usedw_out0
-1
3
sclr
-1
3
rreq
-1
3
full
-1
3
empty
-1
3
clock
-1
3
aclr
-1
3
}
# hierarchies {
std_1c20:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_w:the_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_jf21:auto_generated|a_dpfifo_ml21:dpfifo|a_fefifo_7cf:fifo_state
std_1c20:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_r:the_jtag_uart_scfifo_r|scfifo:rfifo|scfifo_jf21:auto_generated|a_dpfifo_ml21:dpfifo|a_fefifo_7cf:fifo_state
}
# end
# entity
cntr_9c7
# storage
db|standard.(89).cnf
db|standard.(89).cnf
# case_insensitive
# source_file
db|cntr_9c7.tdf
c8ca9890e802882a2a2d1f846ef2d7e
6
# used_port {
updown
-1
3
sclr
-1
3
q5
-1
3
q4
-1
3
q3
-1
3
q2
-1
3
q1
-1
3
q0
-1
3
cnt_en
-1
3
clock
-1
3
aclr
-1
3
}
# hierarchies {
std_1c20:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_w:the_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_jf21:auto_generated|a_dpfifo_ml21:dpfifo|a_fefifo_7cf:fifo_state|cntr_9c7:count_usedw
std_1c20:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_r:the_jtag_uart_scfifo_r|scfifo:rfifo|scfifo_jf21:auto_generated|a_dpfifo_ml21:dpfifo|a_fefifo_7cf:fifo_state|cntr_9c7:count_usedw
}
# end
# entity
dpram_j921
# storage
db|standard.(90).cnf
db|standard.(90).cnf
# case_insensitive
# source_file
db|dpram_j921.tdf
fd424f276797727e813b54c451b266b
6
# used_port {
wren
-1
3
wraddress5
-1
3
wraddress4
-1
3
wraddress3
-1
3
wraddress2
-1
3
wraddress1
-1
3
wraddress0
-1
3
rdaddress5
-1
3
rdaddress4
-1
3
rdaddress3
-1
3
rdaddress2
-1
3
rdaddress1
-1
3
rdaddress0
-1
3
q7
-1
3
q6
-1
3
q5
-1
3
q4
-1
3
q3
-1
3
q2
-1
3
q1
-1
3
q0
-1
3
outclocken
-1
3
outclock
-1
3
inclock
-1
3
data7
-1
3
data6
-1
3
data5
-1
3
data4
-1
3
data3
-1
3
data2
-1
3
data1
-1
3
data0
-1
3
}
# hierarchies {
std_1c20:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_w:the_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_jf21:auto_generated|a_dpfifo_ml21:dpfifo|dpram_j921:FIFOram
std_1c20:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_r:the_jtag_uart_scfifo_r|scfifo:rfifo|scfifo_jf21:auto_generated|a_dpfifo_ml21:dpfifo|dpram_j921:FIFOram
}
# end
# entity
altsyncram_nll1
# storage
db|standard.(91).cnf
db|standard.(91).cnf
# case_insensitive
# source_file
db|altsyncram_nll1.tdf
fa51be277e4d8991b26968980545e8d
6
# user_parameter {
PORT_A_ADDRESS_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_A_BYTE_ENABLE_MASK_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_A_DATA_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_B_ADDRESS_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_B_BYTE_ENABLE_MASK_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_B_DATA_WIDTH
1
PARAMETER_UNKNOWN
DEF
}
# used_port {
wren_a
-1
3
q_b7
-1
3
q_b6
-1
3
q_b5
-1
3
q_b4
-1
3
q_b3
-1
3
q_b2
-1
3
q_b1
-1
3
q_b0
-1
3
data_a7
-1
3
data_a6
-1
3
data_a5
-1
3
data_a4
-1
3
data_a3
-1
3
data_a2
-1
3
data_a1
-1
3
data_a0
-1
3
clocken1
-1
3
clock1
-1
3
clock0
-1
3
address_b5
-1
3
address_b4
-1
3
address_b3
-1
3
address_b2
-1
3
address_b1
-1
3
address_b0
-1
3
address_a5
-1
3
address_a4
-1
3
address_a3
-1
3
address_a2
-1
3
address_a1
-1
3
address_a0
-1
3
}
# memory_file {
none
0
}
# hierarchies {
std_1c20:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_w:the_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_jf21:auto_generated|a_dpfifo_ml21:dpfifo|dpram_j921:FIFOram|altsyncram_nll1:altsyncram1
std_1c20:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_r:the_jtag_uart_scfifo_r|scfifo:rfifo|scfifo_jf21:auto_generated|a_dpfifo_ml21:dpfifo|dpram_j921:FIFOram|altsyncram_nll1:altsyncram1
}
# end
# entity
cntr_rd8
# storage
db|standard.(92).cnf
db|standard.(92).cnf
# case_insensitive
# source_file
db|cntr_rd8.tdf
f76a32bd10c370e90eb24e83df0627
6
# used_port {
sclr
-1
3
q5
-1
3
q4
-1
3
q3
-1
3
q2
-1
3
q1
-1
3
q0
-1
3
cnt_en
-1
3
clock
-1
3
aclr
-1
3
}
# hierarchies {
std_1c20:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_w:the_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_jf21:auto_generated|a_dpfifo_ml21:dpfifo|cntr_rd8:rd_ptr_count
std_1c20:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_w:the_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_jf21:auto_generated|a_dpfifo_ml21:dpfifo|cntr_rd8:wr_ptr
std_1c20:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_r:the_jtag_uart_scfifo_r|scfifo:rfifo|scfifo_jf21:auto_generated|a_dpfifo_ml21:dpfifo|cntr_rd8:rd_ptr_count
std_1c20:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_r:the_jtag_uart_scfifo_r|scfifo:rfifo|scfifo_jf21:auto_generated|a_dpfifo_ml21:dpfifo|cntr_rd8:wr_ptr
}
# end
# entity
alt_jtag_atlantic
# storage
db|standard.(94).cnf
db|standard.(94).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
..|..|..|..|quartus60|libraries|megafunctions|alt_jtag_atlantic.v
87ff42208e2dedfb02b115079ccac7e
7
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
AUTO_RESOURCE_SHARING
OFF
}
# user_parameter {
INSTANCE_ID
0
PARAMETER_DEC
USR
SLD_NODE_INFO
00001100000000000110111000000000
PARAMETER_BIN
DEF
LOG2_TXFIFO_DEPTH
6
PARAMETER_DEC
USR
LOG2_RXFIFO_DEPTH
6
PARAMETER_DEC
USR
RESERVED
0
PARAMETER_DEC
DEF
DATA_WIDTH
8
PARAMETER_DEC
DEF
NODE_IR_WIDTH
1
PARAMETER_DEC
DEF
SCAN_LENGTH
11
PARAMETER_DEC
DEF
}
# hierarchies {
std_1c20:inst|jtag_uart:the_jtag_uart|alt_jtag_atlantic:jtag_uart_alt_jtag_atlantic
}
# end
# entity
lcd_display
# storage
db|standard.(96).cnf
db|standard.(96).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
lcd_display.vhd
7477485873425eb734a43d6ef83b4219
4
# internal_option {
AUTO_RESOURCE_SHARING
OFF
}
# user_parameter {
 constraint(address)
1 downto 0
PARAMETER_STRING
USR
 constraint(writedata)
7 downto 0
PARAMETER_STRING
USR
 constraint(lcd_data)
7 downto 0
PARAMETER_STRING
USR
 constraint(readdata)
7 downto 0
PARAMETER_STRING
USR
}
# hierarchies {
std_1c20:inst|lcd_display:the_lcd_display
}
# end
# entity
led_pio
# storage
db|standard.(98).cnf
db|standard.(98).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
led_pio.vhd
578899f7f5a8c07e47b99deeeedf2b24
4
# internal_option {
AUTO_RESOURCE_SHARING
OFF
}
# user_parameter {
 constraint(address)
1 downto 0
PARAMETER_STRING
USR
 constraint(writedata)
7 downto 0
PARAMETER_STRING
USR
 constraint(out_port)
7 downto 0
PARAMETER_STRING
USR
}
# hierarchies {
std_1c20:inst|led_pio:the_led_pio
}
# end
# entity
reconfig_request_pio
# storage
db|standard.(100).cnf
db|standard.(100).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
reconfig_request_pio.vhd
2e6cf1781e2d50401e1c217c4162198
4
# internal_option {
AUTO_RESOURCE_SHARING
OFF
}
# user_parameter {
 constraint(address)
1 downto 0
PARAMETER_STRING
USR
}
# hierarchies {
std_1c20:inst|reconfig_request_pio:the_reconfig_request_pio
}
# end
# entity
sdram
# storage
db|standard.(104).cnf
db|standard.(104).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
sdram.vhd
674289ebe18fd3eb5635b8db78c6cd9
4
# internal_option {
AUTO_RESOURCE_SHARING
OFF
}
# user_parameter {
 constraint(az_addr)
21 downto 0
PARAMETER_STRING
USR
 constraint(az_be_n)
3 downto 0
PARAMETER_STRING
USR
 constraint(az_data)
31 downto 0
PARAMETER_STRING
USR
 constraint(za_data)
31 downto 0
PARAMETER_STRING
USR
 constraint(zs_addr)
11 downto 0
PARAMETER_STRING
USR
 constraint(zs_ba)
1 downto 0
PARAMETER_STRING
USR
 constraint(zs_dq)
31 downto 0
PARAMETER_STRING
USR
 constraint(zs_dqm)
3 downto 0
PARAMETER_STRING
USR
}
# hierarchies {
std_1c20:inst|sdram:the_sdram
}
# end
# entity
sdram_input_efifo_module
# storage
db|standard.(105).cnf
db|standard.(105).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
sdram.vhd
674289ebe18fd3eb5635b8db78c6cd9
4
# internal_option {
AUTO_RESOURCE_SHARING
OFF
}
# user_parameter {
 constraint(wr_data)
58 downto 0
PARAMETER_STRING
USR
 constraint(rd_data)
58 downto 0
PARAMETER_STRING
USR
}
# hierarchies {
std_1c20:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module
}
# end
# entity
sdram_pll
# storage
db|standard.(107).cnf
db|standard.(107).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
sdram_pll.vhd
f5bba314a10667136ca4fea1b819
4
# internal_option {
AUTO_RESOURCE_SHARING
OFF
}
# user_parameter {
 constraint(address)
2 downto 0
PARAMETER_STRING
USR
 constraint(writedata)
15 downto 0
PARAMETER_STRING
USR
 constraint(readdata)
15 downto 0
PARAMETER_STRING
USR
}
# hierarchies {
std_1c20:inst|sdram_pll:the_sdram_pll
}
# end
# entity
altpllsdram_pll
# storage
db|standard.(108).cnf
db|standard.(108).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
altpllsdram_pll.vhd
b13c65229dd11915a335eff0bf8a4be9
4
# internal_option {
AUTO_RESOURCE_SHARING
OFF
}
# hierarchies {
std_1c20:inst|sdram_pll:the_sdram_pll|altpllsdram_pll:the_pll
}
# end
# entity
altpll
# storage
db|standard.(109).cnf
db|standard.(109).cnf
# case_insensitive
# source_file
..|..|..|..|quartus60|libraries|megafunctions|altpll.tdf
eda762e5901c3e66939b23e413541e
6
# user_parameter {
OPERATION_MODE
NORMAL
PARAMETER_UNKNOWN
USR
PLL_TYPE
AUTO
PARAMETER_UNKNOWN
USR
QUALIFY_CONF_DONE
OFF
PARAMETER_UNKNOWN
DEF
COMPENSATE_CLOCK
CLK0
PARAMETER_UNKNOWN
USR
SCAN_CHAIN
LONG
PARAMETER_UNKNOWN
DEF
PRIMARY_CLOCK
INCLK0
PARAMETER_UNKNOWN
DEF
INCLK0_INPUT_FREQUENCY
20000
PARAMETER_DEC
USR
INCLK1_INPUT_FREQUENCY
0
PARAMETER_UNKNOWN
DEF
GATE_LOCK_SIGNAL
NO
PARAMETER_UNKNOWN
DEF
GATE_LOCK_COUNTER
0
PARAMETER_UNKNOWN
DEF
LOCK_HIGH
1
PARAMETER_UNKNOWN
DEF
LOCK_LOW
1
PARAMETER_UNKNOWN
DEF
VALID_LOCK_MULTIPLIER
1
PARAMETER_UNKNOWN
DEF
INVALID_LOCK_MULTIPLIER
5
PARAMETER_UNKNOWN
DEF
SWITCH_OVER_ON_LOSSCLK
OFF
PARAMETER_UNKNOWN
DEF
SWITCH_OVER_ON_GATED_LOCK
OFF
PARAMETER_UNKNOWN
DEF
ENABLE_SWITCH_OVER_COUNTER
OFF
PARAMETER_UNKNOWN
DEF
SKIP_VCO
OFF
PARAMETER_UNKNOWN
DEF
SWITCH_OVER_COUNTER
0
PARAMETER_UNKNOWN
DEF
SWITCH_OVER_TYPE
AUTO
PARAMETER_UNKNOWN
DEF
FEEDBACK_SOURCE
EXTCLK0
PARAMETER_UNKNOWN
DEF
BANDWIDTH
0
PARAMETER_UNKNOWN
DEF
BANDWIDTH_TYPE
AUTO
PARAMETER_UNKNOWN
DEF
SPREAD_FREQUENCY
0
PARAMETER_UNKNOWN
DEF
DOWN_SPREAD
0
PARAMETER_UNKNOWN
DEF
SELF_RESET_ON_GATED_LOSS_LOCK
OFF
PARAMETER_UNKNOWN
DEF
CLK5_MULTIPLY_BY
1
PARAMETER_UNKNOWN
DEF
CLK4_MULTIPLY_BY
1
PARAMETER_UNKNOWN
DEF
CLK3_MULTIPLY_BY
1
PARAMETER_UNKNOWN
DEF
CLK2_MULTIPLY_BY
1
PARAMETER_UNKNOWN
DEF
CLK1_MULTIPLY_BY
1
PARAMETER_UNKNOWN
DEF
CLK0_MULTIPLY_BY
1
PARAMETER_DEC
USR
CLK5_DIVIDE_BY
1
PARAMETER_UNKNOWN
DEF
CLK4_DIVIDE_BY
1
PARAMETER_UNKNOWN
DEF
CLK3_DIVIDE_BY
1
PARAMETER_UNKNOWN
DEF
CLK2_DIVIDE_BY
1
PARAMETER_UNKNOWN
DEF
CLK1_DIVIDE_BY
1
PARAMETER_UNKNOWN
DEF
CLK0_DIVIDE_BY
1
PARAMETER_DEC
USR
CLK5_PHASE_SHIFT
0
PARAMETER_UNKNOWN
DEF
CLK4_PHASE_SHIFT
0
PARAMETER_UNKNOWN
DEF
CLK3_PHASE_SHIFT
0
PARAMETER_UNKNOWN
DEF
CLK2_PHASE_SHIFT
0
PARAMETER_UNKNOWN
DEF
CLK1_PHASE_SHIFT
0
PARAMETER_UNKNOWN
DEF
CLK0_PHASE_SHIFT
0
PARAMETER_UNKNOWN
USR
CLK5_TIME_DELAY
0
PARAMETER_UNKNOWN
DEF
CLK4_TIME_DELAY
0
PARAMETER_UNKNOWN
DEF
CLK3_TIME_DELAY
0
PARAMETER_UNKNOWN
DEF
CLK2_TIME_DELAY
0
PARAMETER_UNKNOWN
DEF
CLK1_TIME_DELAY
0
PARAMETER_UNKNOWN
DEF
CLK0_TIME_DELAY
0
PARAMETER_UNKNOWN
DEF
CLK5_DUTY_CYCLE
50
PARAMETER_UNKNOWN
DEF
CLK4_DUTY_CYCLE
50
PARAMETER_UNKNOWN
DEF
CLK3_DUTY_CYCLE
50
PARAMETER_UNKNOWN
DEF
CLK2_DUTY_CYCLE
50
PARAMETER_UNKNOWN
DEF
CLK1_DUTY_CYCLE
50
PARAMETER_UNKNOWN
DEF
CLK0_DUTY_CYCLE
50
PARAMETER_DEC
USR
EXTCLK3_MULTIPLY_BY
1
PARAMETER_UNKNOWN
DEF
EXTCLK2_MULTIPLY_BY
1
PARAMETER_UNKNOWN
DEF
EXTCLK1_MULTIPLY_BY
1
PARAMETER_UNKNOWN
DEF
EXTCLK0_MULTIPLY_BY
1
PARAMETER_DEC
USR
EXTCLK3_DIVIDE_BY
1
PARAMETER_UNKNOWN
DEF
EXTCLK2_DIVIDE_BY
1
PARAMETER_UNKNOWN
DEF
EXTCLK1_DIVIDE_BY
1
PARAMETER_UNKNOWN
DEF
EXTCLK0_DIVIDE_BY
1
PARAMETER_DEC
USR
EXTCLK3_PHASE_SHIFT
0
PARAMETER_UNKNOWN
DEF
EXTCLK2_PHASE_SHIFT
0
PARAMETER_UNKNOWN
DEF
EXTCLK1_PHASE_SHIFT
0
PARAMETER_UNKNOWN
DEF
EXTCLK0_PHASE_SHIFT
-3500
PARAMETER_UNKNOWN
USR
EXTCLK3_TIME_DELAY
0
PARAMETER_UNKNOWN
DEF
EXTCLK2_TIME_DELAY
0
PARAMETER_UNKNOWN
DEF
EXTCLK1_TIME_DELAY
0
PARAMETER_UNKNOWN
DEF
EXTCLK0_TIME_DELAY
0
PARAMETER_UNKNOWN
DEF
EXTCLK3_DUTY_CYCLE
50
PARAMETER_UNKNOWN
DEF
EXTCLK2_DUTY_CYCLE
50
PARAMETER_UNKNOWN
DEF
EXTCLK1_DUTY_CYCLE
50
PARAMETER_UNKNOWN
DEF
EXTCLK0_DUTY_CYCLE
50
PARAMETER_DEC
USR
VCO_MULTIPLY_BY
0
PARAMETER_UNKNOWN
DEF
VCO_DIVIDE_BY
0
PARAMETER_UNKNOWN
DEF
SCLKOUT0_PHASE_SHIFT
0
PARAMETER_UNKNOWN
DEF
SCLKOUT1_PHASE_SHIFT
0
PARAMETER_UNKNOWN
DEF
VCO_MIN
0
PARAMETER_UNKNOWN
DEF
VCO_MAX
0
PARAMETER_UNKNOWN
DEF
VCO_CENTER
0
PARAMETER_UNKNOWN
DEF
PFD_MIN
0
PARAMETER_UNKNOWN
DEF
PFD_MAX
0
PARAMETER_UNKNOWN
DEF
M_INITIAL
0
PARAMETER_UNKNOWN
DEF
M
0
PARAMETER_UNKNOWN
DEF
N
1
PARAMETER_UNKNOWN
DEF
M2
1
PARAMETER_UNKNOWN
DEF
N2
1
PARAMETER_UNKNOWN
DEF
SS
1
PARAMETER_UNKNOWN
DEF
C0_HIGH
0
PARAMETER_UNKNOWN
DEF
C1_HIGH
0
PARAMETER_UNKNOWN
DEF
C2_HIGH
0
PARAMETER_UNKNOWN
DEF
C3_HIGH
0
PARAMETER_UNKNOWN
DEF
C4_HIGH
0
PARAMETER_UNKNOWN
DEF
C5_HIGH
0
PARAMETER_UNKNOWN
DEF
C0_LOW
0
PARAMETER_UNKNOWN
DEF
C1_LOW
0
PARAMETER_UNKNOWN
DEF
C2_LOW
0
PARAMETER_UNKNOWN
DEF
C3_LOW
0
PARAMETER_UNKNOWN
DEF
C4_LOW
0
PARAMETER_UNKNOWN
DEF
C5_LOW
0
PARAMETER_UNKNOWN
DEF
C0_INITIAL
0
PARAMETER_UNKNOWN
DEF
C1_INITIAL
0
PARAMETER_UNKNOWN
DEF
C2_INITIAL
0
PARAMETER_UNKNOWN
DEF
C3_INITIAL
0
PARAMETER_UNKNOWN
DEF
C4_INITIAL
0
PARAMETER_UNKNOWN
DEF
C5_INITIAL
0
PARAMETER_UNKNOWN
DEF
C0_MODE
BYPASS
PARAMETER_UNKNOWN
DEF
C1_MODE
BYPASS
PARAMETER_UNKNOWN
DEF
C2_MODE
BYPASS
PARAMETER_UNKNOWN
DEF
C3_MODE
BYPASS
PARAMETER_UNKNOWN
DEF
C4_MODE
BYPASS
PARAMETER_UNKNOWN
DEF
C5_MODE
BYPASS
PARAMETER_UNKNOWN
DEF
C0_PH
0
PARAMETER_UNKNOWN
DEF
C1_PH
0
PARAMETER_UNKNOWN
DEF
C2_PH
0
PARAMETER_UNKNOWN
DEF
C3_PH
0
PARAMETER_UNKNOWN
DEF
C4_PH
0
PARAMETER_UNKNOWN
DEF
C5_PH
0
PARAMETER_UNKNOWN
DEF
L0_HIGH
1
PARAMETER_UNKNOWN
DEF
L1_HIGH
1
PARAMETER_UNKNOWN
DEF
G0_HIGH
1
PARAMETER_UNKNOWN
DEF
G1_HIGH
1
PARAMETER_UNKNOWN
DEF
G2_HIGH
1
PARAMETER_UNKNOWN
DEF
G3_HIGH
1
PARAMETER_UNKNOWN
DEF
E0_HIGH
1
PARAMETER_UNKNOWN
DEF
E1_HIGH
1
PARAMETER_UNKNOWN
DEF
E2_HIGH
1
PARAMETER_UNKNOWN
DEF
E3_HIGH
1
PARAMETER_UNKNOWN
DEF
L0_LOW
1
PARAMETER_UNKNOWN
DEF
L1_LOW
1
PARAMETER_UNKNOWN
DEF
G0_LOW
1
PARAMETER_UNKNOWN
DEF
G1_LOW
1
PARAMETER_UNKNOWN
DEF
G2_LOW
1
PARAMETER_UNKNOWN
DEF
G3_LOW
1
PARAMETER_UNKNOWN
DEF
E0_LOW
1
PARAMETER_UNKNOWN
DEF
E1_LOW
1
PARAMETER_UNKNOWN
DEF
E2_LOW
1
PARAMETER_UNKNOWN
DEF
E3_LOW
1
PARAMETER_UNKNOWN
DEF
L0_INITIAL
1
PARAMETER_UNKNOWN
DEF
L1_INITIAL
1
PARAMETER_UNKNOWN
DEF
G0_INITIAL
1
PARAMETER_UNKNOWN
DEF
G1_INITIAL
1
PARAMETER_UNKNOWN
DEF
G2_INITIAL
1
PARAMETER_UNKNOWN
DEF
G3_INITIAL
1
PARAMETER_UNKNOWN
DEF
E0_INITIAL
1
PARAMETER_UNKNOWN
DEF
E1_INITIAL
1
PARAMETER_UNKNOWN
DEF
E2_INITIAL
1
PARAMETER_UNKNOWN
DEF
E3_INITIAL
1
PARAMETER_UNKNOWN
DEF
L0_MODE
BYPASS
PARAMETER_UNKNOWN
DEF
L1_MODE
BYPASS
PARAMETER_UNKNOWN
DEF
G0_MODE
BYPASS
PARAMETER_UNKNOWN
DEF
G1_MODE
BYPASS
PARAMETER_UNKNOWN
DEF
G2_MODE
BYPASS
PARAMETER_UNKNOWN
DEF
G3_MODE
BYPASS
PARAMETER_UNKNOWN
DEF
E0_MODE
BYPASS
PARAMETER_UNKNOWN
DEF
E1_MODE
BYPASS
PARAMETER_UNKNOWN
DEF
E2_MODE
BYPASS
PARAMETER_UNKNOWN
DEF
E3_MODE
BYPASS
PARAMETER_UNKNOWN
DEF
L0_PH
0
PARAMETER_UNKNOWN
DEF
L1_PH
0
PARAMETER_UNKNOWN
DEF
G0_PH
0
PARAMETER_UNKNOWN
DEF
G1_PH
0
PARAMETER_UNKNOWN
DEF
G2_PH
0
PARAMETER_UNKNOWN
DEF
G3_PH
0
PARAMETER_UNKNOWN
DEF
E0_PH
0
PARAMETER_UNKNOWN
DEF
E1_PH
0
PARAMETER_UNKNOWN
DEF
E2_PH
0
PARAMETER_UNKNOWN
DEF
E3_PH
0
PARAMETER_UNKNOWN
DEF
M_PH
0
PARAMETER_UNKNOWN
DEF
C1_USE_CASC_IN
0
PARAMETER_UNKNOWN
DEF
C2_USE_CASC_IN
0
PARAMETER_UNKNOWN
DEF
C3_USE_CASC_IN
0
PARAMETER_UNKNOWN
DEF
C4_USE_CASC_IN
0
PARAMETER_UNKNOWN
DEF
C5_USE_CASC_IN
0
PARAMETER_UNKNOWN
DEF
CLK0_COUNTER
G0
PARAMETER_UNKNOWN
DEF
CLK1_COUNTER
G0
PARAMETER_UNKNOWN
DEF
CLK2_COUNTER
G0
PARAMETER_UNKNOWN
DEF
CLK3_COUNTER
G0
PARAMETER_UNKNOWN
DEF
CLK4_COUNTER
G0
PARAMETER_UNKNOWN
DEF
CLK5_COUNTER
G0
PARAMETER_UNKNOWN
DEF
L0_TIME_DELAY
0
PARAMETER_UNKNOWN
DEF
L1_TIME_DELAY
0
PARAMETER_UNKNOWN
DEF
G0_TIME_DELAY
0
PARAMETER_UNKNOWN
DEF
G1_TIME_DELAY
0
PARAMETER_UNKNOWN
DEF
G2_TIME_DELAY
0
PARAMETER_UNKNOWN
DEF
G3_TIME_DELAY
0
PARAMETER_UNKNOWN
DEF
E0_TIME_DELAY
0
PARAMETER_UNKNOWN
DEF
E1_TIME_DELAY
0
PARAMETER_UNKNOWN
DEF
E2_TIME_DELAY
0
PARAMETER_UNKNOWN
DEF
E3_TIME_DELAY
0
PARAMETER_UNKNOWN
DEF
M_TIME_DELAY
0
PARAMETER_UNKNOWN
DEF
N_TIME_DELAY
0
PARAMETER_UNKNOWN
DEF
EXTCLK3_COUNTER
E3
PARAMETER_UNKNOWN
DEF
EXTCLK2_COUNTER
E2
PARAMETER_UNKNOWN
DEF
EXTCLK1_COUNTER
E1
PARAMETER_UNKNOWN
DEF
EXTCLK0_COUNTER
E0
PARAMETER_UNKNOWN
DEF
ENABLE0_COUNTER
L0
PARAMETER_UNKNOWN
DEF
ENABLE1_COUNTER
L0
PARAMETER_UNKNOWN
DEF
CHARGE_PUMP_CURRENT
2
PARAMETER_UNKNOWN
DEF
LOOP_FILTER_R
 1.000000
PARAMETER_UNKNOWN
DEF
LOOP_FILTER_C
5
PARAMETER_UNKNOWN
DEF
VCO_POST_SCALE
0
PARAMETER_UNKNOWN
DEF
CLK2_OUTPUT_FREQUENCY
0
PARAMETER_UNKNOWN
DEF
CLK1_OUTPUT_FREQUENCY
0
PARAMETER_UNKNOWN
DEF
CLK0_OUTPUT_FREQUENCY
0
PARAMETER_UNKNOWN
DEF
INTENDED_DEVICE_FAMILY
Cyclone
PARAMETER_UNKNOWN
USR
PORT_CLKENA0
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_CLKENA1
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_CLKENA2
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
PORT_CLKENA3
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_CLKENA4
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_CLKENA5
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_EXTCLKENA0
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_EXTCLKENA1
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_EXTCLKENA2
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_EXTCLKENA3
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_EXTCLK0
PORT_USED
PARAMETER_UNKNOWN
USR
PORT_EXTCLK1
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_EXTCLK2
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_EXTCLK3
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_CLKBAD0
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_CLKBAD1
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_CLK0
PORT_USED
PARAMETER_UNKNOWN
USR
PORT_CLK1
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_CLK2
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
PORT_CLK3
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_CLK4
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_CLK5
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_SCANDATA
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_SCANDATAOUT
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_SCANDONE
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_SCLKOUT1
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_SCLKOUT0
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_ACTIVECLOCK
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_CLKLOSS
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_INCLK1
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_INCLK0
PORT_USED
PARAMETER_UNKNOWN
USR
PORT_FBIN
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_PLLENA
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_CLKSWITCH
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_ARESET
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_PFDENA
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_SCANCLK
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_SCANACLR
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_SCANREAD
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_SCANWRITE
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_ENABLE0
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_ENABLE1
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_LOCKED
PORT_UNUSED
PARAMETER_UNKNOWN
USR
M_TEST_SOURCE
5
PARAMETER_UNKNOWN
DEF
C0_TEST_SOURCE
5
PARAMETER_UNKNOWN
DEF
C1_TEST_SOURCE
5
PARAMETER_UNKNOWN
DEF
C2_TEST_SOURCE
5
PARAMETER_UNKNOWN
DEF
C3_TEST_SOURCE
5
PARAMETER_UNKNOWN
DEF
C4_TEST_SOURCE
5
PARAMETER_UNKNOWN
DEF
C5_TEST_SOURCE
5
PARAMETER_UNKNOWN
DEF
DEVICE_FAMILY
Cyclone
PARAMETER_UNKNOWN
USR
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
}
# used_port {
inclk0
-1
3
extclk0
-1
3
clk0
-1
3
inclk1
-1
1
}
# include_file {
..|..|..|..|quartus60|libraries|megafunctions|stratix_pll.inc
5f8211898149ceae8264a0ea5036254f
..|..|..|..|quartus60|libraries|megafunctions|aglobal60.inc
b3d07c643dae10ab2b3e646e99ec45fc
..|..|..|..|quartus60|libraries|megafunctions|stratixii_pll.inc
6d1985e16ab5f59a1fd6b0ae20978a4e
..|..|..|..|quartus60|libraries|megafunctions|cycloneii_pll.inc
39a0d9d1237d1db39c848c3f9faffc
}
# hierarchies {
std_1c20:inst|sdram_pll:the_sdram_pll|altpllsdram_pll:the_pll|altpll:altpll_component
}
# end
# entity
seven_seg_pio
# storage
db|standard.(111).cnf
db|standard.(111).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
seven_seg_pio.vhd
a3677123d6eca3f11b2fe9da7a64941
4
# internal_option {
AUTO_RESOURCE_SHARING
OFF
}
# user_parameter {
 constraint(address)
1 downto 0
PARAMETER_STRING
USR
 constraint(writedata)
15 downto 0
PARAMETER_STRING
USR
 constraint(out_port)
15 downto 0
PARAMETER_STRING
USR
}
# hierarchies {
std_1c20:inst|seven_seg_pio:the_seven_seg_pio
}
# end
# entity
sys_clk_timer
# storage
db|standard.(113).cnf
db|standard.(113).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
sys_clk_timer.vhd
86e8d96aeef5acbd646d06c6cb974ff
4
# internal_option {
AUTO_RESOURCE_SHARING
OFF
}
# user_parameter {
 constraint(address)
2 downto 0
PARAMETER_STRING
USR
 constraint(writedata)
15 downto 0
PARAMETER_STRING
USR
 constraint(readdata)
15 downto 0
PARAMETER_STRING
USR
}
# hierarchies {
std_1c20:inst|sys_clk_timer:the_sys_clk_timer
}
# end
# entity
sld_hub
# storage
db|standard.(125).cnf
db|standard.(125).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
..|..|..|..|quartus60|libraries|megafunctions|sld_hub.vhd
5510376c98712ae04829215cf7121b6
4
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
AUTO_RESOURCE_SHARING
OFF
}
# user_parameter {
sld_hub_ip_version
1
PARAMETER_UNKNOWN
USR
sld_hub_ip_minor_version
3
PARAMETER_UNKNOWN
USR
sld_common_ip_version
0
PARAMETER_UNKNOWN
USR
device_family
Cyclone
PARAMETER_UNKNOWN
USR
n_nodes
2
PARAMETER_UNKNOWN
USR
n_sel_bits
2
PARAMETER_UNKNOWN
USR
n_node_ir_bits
5
PARAMETER_UNKNOWN
USR
node_info
0000110000000000011011100000000000010001000100000100011000000000
PARAMETER_BIN
USR
compilation_mode
0
PARAMETER_UNKNOWN
USR
}
# end
# entity
sld_jtag_state_machine
# storage
db|standard.(126).cnf
db|standard.(126).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
..|..|..|..|quartus60|libraries|megafunctions|sld_hub.vhd
5510376c98712ae04829215cf7121b6
4
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
AUTO_RESOURCE_SHARING
OFF
}
# user_parameter {
ip_major_version
1
PARAMETER_DEC
USR
ip_minor_version
3
PARAMETER_DEC
USR
common_ip_version
0
PARAMETER_DEC
USR
 constraint(jtag_state)
15 downto 0
PARAMETER_STRING
USR
}
# end
# entity
lpm_shiftreg
# storage
db|standard.(127).cnf
db|standard.(127).cnf
# case_insensitive
# source_file
..|..|..|..|quartus60|libraries|megafunctions|lpm_shiftreg.tdf
5c3a6ccfa9758137252ac34dcc2420
6
# user_parameter {
LPM_WIDTH
10
PARAMETER_DEC
USR
LPM_DIRECTION
RIGHT
PARAMETER_UNKNOWN
USR
LPM_AVALUE
UNUSED
PARAMETER_UNKNOWN
DEF
LPM_SVALUE
UNUSED
PARAMETER_UNKNOWN
DEF
DEVICE_FAMILY
Cyclone
PARAMETER_UNKNOWN
USR
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
}
# used_port {
shiftin
-1
3
q9
-1
3
q8
-1
3
q7
-1
3
q6
-1
3
q5
-1
3
q4
-1
3
q3
-1
3
q2
-1
3
q1
-1
3
q0
-1
3
enable
-1
3
clock
-1
3
aclr
-1
3
}
# include_file {
..|..|..|..|quartus60|libraries|megafunctions|aglobal60.inc
b3d07c643dae10ab2b3e646e99ec45fc
..|..|..|..|quartus60|libraries|megafunctions|lpm_constant.inc
dcde44eee59335c1e2fe75d574f9646
..|..|..|..|quartus60|libraries|megafunctions|dffeea.inc
55d29d20f7e852c37746bec4e2495ec
}
# end
# entity
lpm_decode
# storage
db|standard.(128).cnf
db|standard.(128).cnf
# case_insensitive
# source_file
..|..|..|..|quartus60|libraries|megafunctions|lpm_decode.tdf
2c635cd4e4aadce939ff33a1912efcc
6
# user_parameter {
LPM_WIDTH
3
PARAMETER_DEC
USR
LPM_DECODES
8
PARAMETER_DEC
USR
LPM_PIPELINE
1
PARAMETER_DEC
USR
CASCADE_CHAIN
MANUAL
PARAMETER_UNKNOWN
USR
DEVICE_FAMILY
Cyclone
PARAMETER_UNKNOWN
USR
CBXI_PARAMETER
decode_ogi
PARAMETER_UNKNOWN
USR
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
}
# used_port {
eq7
-1
3
eq3
-1
3
eq2
-1
3
eq1
-1
3
eq0
-1
3
enable
-1
3
data2
-1
3
data1
-1
3
data0
-1
3
clock
-1
3
clken
-1
3
aclr
-1
3
}
# include_file {
..|..|..|..|quartus60|libraries|megafunctions|aglobal60.inc
b3d07c643dae10ab2b3e646e99ec45fc
..|..|..|..|quartus60|libraries|megafunctions|lpm_constant.inc
dcde44eee59335c1e2fe75d574f9646
..|..|..|..|quartus60|libraries|megafunctions|declut.inc
b1d5939399e5c04dfe1d209af8cc490
..|..|..|..|quartus60|libraries|megafunctions|altshift.inc
70fa13aee7d6d160ef20b2de32813a
..|..|..|..|quartus60|libraries|megafunctions|lpm_compare.inc
aec4ea1b78f4cda1c3effe18f1abbf63
}
# end
# entity
decode_ogi
# storage
db|standard.(129).cnf
db|standard.(129).cnf
# case_insensitive
# source_file
db|decode_ogi.tdf
ffc7173ea4e253ca8971cc1a77d92062
6
# used_port {
eq7
-1
3
eq6
-1
3
eq5
-1
3
eq4
-1
3
eq3
-1
3
eq2
-1
3
eq1
-1
3
eq0
-1
3
enable
-1
3
data2
-1
3
data1
-1
3
data0
-1
3
clock
-1
3
clken
-1
3
aclr
-1
3
}
# end
# entity
sld_dffex
# storage
db|standard.(130).cnf
db|standard.(130).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
..|..|..|..|quartus60|libraries|megafunctions|sld_dffex.vhd
e07a659f3de75fb323a077607414df48
4
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
AUTO_RESOURCE_SHARING
OFF
}
# user_parameter {
size
1
PARAMETER_DEC
USR
 constraint(d)
0 downto 0
PARAMETER_STRING
USR
 constraint(q)
0 downto 0
PARAMETER_STRING
USR
}
# end
# entity
sld_dffex
# storage
db|standard.(131).cnf
db|standard.(131).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
..|..|..|..|quartus60|libraries|megafunctions|sld_dffex.vhd
e07a659f3de75fb323a077607414df48
4
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
AUTO_RESOURCE_SHARING
OFF
}
# user_parameter {
size
7
PARAMETER_DEC
USR
 constraint(d)
6 downto 0
PARAMETER_STRING
USR
 constraint(q)
6 downto 0
PARAMETER_STRING
USR
}
# end
# entity
sld_dffex
# storage
db|standard.(132).cnf
db|standard.(132).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
..|..|..|..|quartus60|libraries|megafunctions|sld_dffex.vhd
e07a659f3de75fb323a077607414df48
4
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
AUTO_RESOURCE_SHARING
OFF
}
# user_parameter {
size
5
PARAMETER_DEC
USR
 constraint(d)
4 downto 0
PARAMETER_STRING
USR
 constraint(q)
4 downto 0
PARAMETER_STRING
USR
}
# end
# entity
sld_dffex
# storage
db|standard.(133).cnf
db|standard.(133).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
..|..|..|..|quartus60|libraries|megafunctions|sld_dffex.vhd
e07a659f3de75fb323a077607414df48
4
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
AUTO_RESOURCE_SHARING
OFF
}
# user_parameter {
size
2
PARAMETER_DEC
USR
 constraint(d)
1 downto 0
PARAMETER_STRING
USR
 constraint(q)
1 downto 0
PARAMETER_STRING
USR
}
# end
# entity
sld_rom_sr
# storage
db|standard.(134).cnf
db|standard.(134).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
..|..|..|..|quartus60|libraries|megafunctions|sld_rom_sr.vhd
e685b197d41e27ef5fe9d8f6d2755ee3
4
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
AUTO_RESOURCE_SHARING
OFF
}
# user_parameter {
common_ip_version
0
PARAMETER_DEC
USR
n_bits
96
PARAMETER_DEC
USR
word_size
4
PARAMETER_DEC
USR
 constraint(rom_data)
95 downto 0
PARAMETER_STRING
USR
}
# end
# entity
lpm_add_sub
# storage
db|standard.(135).cnf
db|standard.(135).cnf
# case_insensitive
# source_file
..|..|..|..|quartus60|libraries|megafunctions|lpm_add_sub.tdf
fd2aba47a9ae5274232d645edd0f35f
6
# user_parameter {
LPM_WIDTH
33
PARAMETER_UNKNOWN
USR
LPM_REPRESENTATION
UNSIGNED
PARAMETER_UNKNOWN
USR
LPM_DIRECTION
DEFAULT
PARAMETER_UNKNOWN
DEF
ONE_INPUT_IS_CONSTANT
NO
PARAMETER_UNKNOWN
USR
LPM_PIPELINE
0
PARAMETER_UNKNOWN
DEF
MAXIMIZE_SPEED
5
PARAMETER_UNKNOWN
DEF
REGISTERED_AT_END
0
PARAMETER_UNKNOWN
DEF
OPTIMIZE_FOR_SPEED
9
PARAMETER_UNKNOWN
USR
USE_CS_BUFFERS
1
PARAMETER_UNKNOWN
DEF
CARRY_CHAIN
MANUAL
PARAMETER_UNKNOWN
USR
CARRY_CHAIN_LENGTH
48
CARRY_CHAIN_LENGTH
USR
DEVICE_FAMILY
Cyclone
PARAMETER_UNKNOWN
USR
USE_WYS
OFF
PARAMETER_UNKNOWN
DEF
STYLE
FAST
PARAMETER_UNKNOWN
USR
CBXI_PARAMETER
add_sub_7cg
PARAMETER_UNKNOWN
USR
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
}
# used_port {
result9
-1
3
result8
-1
3
result7
-1
3
result6
-1
3
result5
-1
3
result4
-1
3
result32
-1
3
result31
-1
3
result30
-1
3
result3
-1
3
result29
-1
3
result28
-1
3
result27
-1
3
result26
-1
3
result25
-1
3
result24
-1
3
result23
-1
3
result22
-1
3
result21
-1
3
result20
-1
3
result2
-1
3
result19
-1
3
result18
-1
3
result17
-1
3
result16
-1
3
result15
-1
3
result14
-1
3
result13
-1
3
result12
-1
3
result11
-1
3
result10
-1
3
result1
-1
3
result0
-1
3
datab9
-1
3
datab8
-1
3
datab7
-1
3
datab6
-1
3
datab5
-1
3
datab4
-1
3
datab31
-1
3
datab30
-1
3
datab3
-1
3
datab29
-1
3
datab28
-1
3
datab27
-1
3
datab26
-1
3
datab25
-1
3
datab24
-1
3
datab23
-1
3
datab22
-1
3
datab21
-1
3
datab20
-1
3
datab2
-1
3
datab19
-1
3
datab18
-1
3
datab17
-1
3
datab16
-1
3
datab15
-1
3
datab14
-1
3
datab13
-1
3
datab12
-1
3
datab11
-1
3
datab10
-1
3
datab1
-1
3
datab0
-1
3
dataa9
-1
3
dataa8
-1
3
dataa7
-1
3
dataa6
-1
3
dataa5
-1
3
dataa4
-1
3
dataa31
-1
3
dataa30
-1
3
dataa3
-1
3
dataa29
-1
3
dataa28
-1
3
dataa27
-1
3
dataa26
-1
3
dataa25
-1
3
dataa24
-1
3
dataa23
-1
3
dataa22
-1
3
dataa21
-1
3
dataa20
-1
3
dataa2
-1
3
dataa19
-1
3
dataa18
-1
3
dataa17
-1
3
dataa16
-1
3
dataa15
-1
3
dataa14
-1
3
dataa13
-1
3
dataa12
-1
3
dataa11
-1
3
dataa10
-1
3
dataa1
-1
3
dataa0
-1
3
add_sub
-1
3
datab32
-1
1
dataa32
-1
1
}
# include_file {
..|..|..|..|quartus60|libraries|megafunctions|aglobal60.inc
b3d07c643dae10ab2b3e646e99ec45fc
..|..|..|..|quartus60|libraries|megafunctions|altshift.inc
70fa13aee7d6d160ef20b2de32813a
..|..|..|..|quartus60|libraries|megafunctions|alt_stratix_add_sub.inc
c08f604aefba5b4f1f554e565113c6
..|..|..|..|quartus60|libraries|megafunctions|addcore.inc
ff795e21e4847824c03218724f1a1252
..|..|..|..|quartus60|libraries|megafunctions|look_add.inc
ab9f577d30c5ef3166fab6c1c32c4a
..|..|..|..|quartus60|libraries|megafunctions|alt_mercury_add_sub.inc
ae39f15ed67cc9a095d29f68f6ad0f8
..|..|..|..|quartus60|libraries|megafunctions|bypassff.inc
8e8df160d449a63ec15dc86ecf2b373f
}
# end
# entity
alt_stratix_add_sub
# storage
db|standard.(136).cnf
db|standard.(136).cnf
# case_insensitive
# source_file
..|..|..|..|quartus60|libraries|megafunctions|alt_stratix_add_sub.tdf
af43494388bfac3b339ff8613d25051
6
# user_parameter {
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
LPM_WIDTH
33
PARAMETER_UNKNOWN
USR
LPM_REPRESENTATION
UNSIGNED
PARAMETER_UNKNOWN
USR
LPM_DIRECTION
DEFAULT
PARAMETER_UNKNOWN
USR
ONE_INPUT_IS_CONSTANT
NO
PARAMETER_UNKNOWN
USR
LPM_PIPELINE
0
PARAMETER_UNKNOWN
USR
MAXIMIZE_SPEED
5
PARAMETER_UNKNOWN
USR
REGISTERED_AT_END
0
PARAMETER_UNKNOWN
USR
OPTIMIZE_FOR_SPEED
9
PARAMETER_UNKNOWN
USR
USE_CS_BUFFERS
1
PARAMETER_UNKNOWN
USR
CARRY_CHAIN
MANUAL
PARAMETER_UNKNOWN
USR
CARRY_CHAIN_LENGTH
48
CARRY_CHAIN_LENGTH
USR
DEVICE_FAMILY
Cyclone
PARAMETER_UNKNOWN
USR
STYLE
FAST
PARAMETER_UNKNOWN
USR
}
# used_port {
result9
-1
3
result8
-1
3
result7
-1
3
result6
-1
3
result5
-1
3
result4
-1
3
result32
-1
3
result31
-1
3
result30
-1
3
result3
-1
3
result29
-1
3
result28
-1
3
result27
-1
3
result26
-1
3
result25
-1
3
result24
-1
3
result23
-1
3
result22
-1
3
result21
-1
3
result20
-1
3
result2
-1
3
result19
-1
3
result18
-1
3
result17
-1
3
result16
-1
3
result15
-1
3
result14
-1
3
result13
-1
3
result12
-1
3
result11
-1
3
result10
-1
3
result1
-1
3
result0
-1
3
datab9
-1
3
datab8
-1
3
datab7
-1
3
datab6
-1
3
datab5
-1
3
datab4
-1
3
datab32
-1
3
datab31
-1
3
datab30
-1
3
datab3
-1
3
datab29
-1
3
datab28
-1
3
datab27
-1
3
datab26
-1
3
datab25
-1
3
datab24
-1
3
datab23
-1
3
datab22
-1
3
datab21
-1
3
datab20
-1
3
datab2
-1
3
datab19
-1
3
datab18
-1
3
datab17
-1
3
datab16
-1
3
datab15
-1
3
datab14
-1
3
datab13
-1
3
datab12
-1
3
datab11
-1
3
datab10
-1
3
datab1
-1
3
datab0
-1
3
dataa9
-1
3
dataa8
-1
3
dataa7
-1
3
dataa6
-1
3
dataa5
-1
3
dataa4
-1
3
dataa32
-1
3
dataa31
-1
3
dataa30
-1
3
dataa3
-1
3
dataa29
-1
3
dataa28
-1
3
dataa27
-1
3
dataa26
-1
3
dataa25
-1
3
dataa24
-1
3
dataa23
-1
3
dataa22
-1
3
dataa21
-1
3
dataa20
-1
3
dataa2
-1
3
dataa19
-1
3
dataa18
-1
3
dataa17
-1
3
dataa16
-1
3
dataa15
-1
3
dataa14
-1
3
dataa13
-1
3
dataa12
-1
3
dataa11
-1
3
dataa10
-1
3
dataa1
-1
3
dataa0
-1
3
add_sub
-1
3
}
# include_file {
..|..|..|..|quartus60|libraries|megafunctions|aglobal60.inc
b3d07c643dae10ab2b3e646e99ec45fc
..|..|..|..|quartus60|libraries|megafunctions|stratix_lcell.inc
1aad1342a15da19fe8b79bc4e5ad56
}
# end
# entity
std_1c20
# storage
db|standard.(1).cnf
db|standard.(1).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
std_1c20.vhd
67356db08fbff5d04aed26fe53d6daae
4
# internal_option {
AUTO_RESOURCE_SHARING
OFF
}
# hierarchies {
std_1c20:inst
}
# end
# entity
button_pio_s1_arbitrator
# storage
db|standard.(2).cnf
db|standard.(2).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
std_1c20.vhd
67356db08fbff5d04aed26fe53d6daae
4
# internal_option {
AUTO_RESOURCE_SHARING
OFF
}
# user_parameter {
 constraint(button_pio_s1_readdata)
3 downto 0
PARAMETER_STRING
USR
 constraint(cpu_data_master_address_to_slave)
25 downto 0
PARAMETER_STRING
USR
 constraint(cpu_data_master_writedata)
31 downto 0
PARAMETER_STRING
USR
 constraint(button_pio_s1_address)
1 downto 0
PARAMETER_STRING
USR
 constraint(button_pio_s1_readdata_from_sa)
3 downto 0
PARAMETER_STRING
USR
 constraint(button_pio_s1_writedata)
3 downto 0
PARAMETER_STRING
USR
}
# hierarchies {
std_1c20:inst|button_pio_s1_arbitrator:the_button_pio_s1
}
# end
# entity
clock_0_in_arbitrator
# storage
db|standard.(4).cnf
db|standard.(4).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
std_1c20.vhd
67356db08fbff5d04aed26fe53d6daae
4
# internal_option {
AUTO_RESOURCE_SHARING
OFF
}
# user_parameter {
 constraint(clock_0_in_readdata)
15 downto 0
PARAMETER_STRING
USR
 constraint(cpu_data_master_address_to_slave)
25 downto 0
PARAMETER_STRING
USR
 constraint(cpu_data_master_byteenable)
3 downto 0
PARAMETER_STRING
USR
 constraint(cpu_data_master_writedata)
31 downto 0
PARAMETER_STRING
USR
 constraint(clock_0_in_address)
3 downto 0
PARAMETER_STRING
USR
 constraint(clock_0_in_byteenable)
1 downto 0
PARAMETER_STRING
USR
 constraint(clock_0_in_nativeaddress)
2 downto 0
PARAMETER_STRING
USR
 constraint(clock_0_in_readdata_from_sa)
15 downto 0
PARAMETER_STRING
USR
 constraint(clock_0_in_writedata)
15 downto 0
PARAMETER_STRING
USR
}
# hierarchies {
std_1c20:inst|clock_0_in_arbitrator:the_clock_0_in
}
# end
# entity
clock_0_out_arbitrator
# storage
db|standard.(5).cnf
db|standard.(5).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
std_1c20.vhd
67356db08fbff5d04aed26fe53d6daae
4
# internal_option {
AUTO_RESOURCE_SHARING
OFF
}
# user_parameter {
 constraint(clock_0_out_address)
3 downto 0
PARAMETER_STRING
USR
 constraint(clock_0_out_writedata)
15 downto 0
PARAMETER_STRING
USR
 constraint(sdram_pll_s1_readdata_from_sa)
15 downto 0
PARAMETER_STRING
USR
 constraint(clock_0_out_address_to_slave)
3 downto 0
PARAMETER_STRING
USR
 constraint(clock_0_out_readdata)
15 downto 0
PARAMETER_STRING
USR
}
# hierarchies {
std_1c20:inst|clock_0_out_arbitrator:the_clock_0_out
}
# end
# entity
clock_1_in_arbitrator
# storage
db|standard.(15).cnf
db|standard.(15).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
std_1c20.vhd
67356db08fbff5d04aed26fe53d6daae
4
# internal_option {
AUTO_RESOURCE_SHARING
OFF
}
# user_parameter {
 constraint(clock_1_in_readdata)
15 downto 0
PARAMETER_STRING
USR
 constraint(cpu_data_master_address_to_slave)
25 downto 0
PARAMETER_STRING
USR
 constraint(cpu_data_master_byteenable)
3 downto 0
PARAMETER_STRING
USR
 constraint(cpu_data_master_writedata)
31 downto 0
PARAMETER_STRING
USR
 constraint(clock_1_in_address)
3 downto 0
PARAMETER_STRING
USR
 constraint(clock_1_in_byteenable)
1 downto 0
PARAMETER_STRING
USR
 constraint(clock_1_in_nativeaddress)
2 downto 0
PARAMETER_STRING
USR
 constraint(clock_1_in_readdata_from_sa)
15 downto 0
PARAMETER_STRING
USR
 constraint(clock_1_in_writedata)
15 downto 0
PARAMETER_STRING
USR
}
# hierarchies {
std_1c20:inst|clock_1_in_arbitrator:the_clock_1_in
}
# end
# entity
clock_1_out_arbitrator
# storage
db|standard.(16).cnf
db|standard.(16).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
std_1c20.vhd
67356db08fbff5d04aed26fe53d6daae
4
# internal_option {
AUTO_RESOURCE_SHARING
OFF
}
# user_parameter {
 constraint(clock_1_out_address)
3 downto 0
PARAMETER_STRING
USR
 constraint(clock_1_out_writedata)
15 downto 0
PARAMETER_STRING
USR
 constraint(connector_pll_s1_readdata_from_sa)
15 downto 0
PARAMETER_STRING
USR
 constraint(clock_1_out_address_to_slave)
3 downto 0
PARAMETER_STRING
USR
 constraint(clock_1_out_readdata)
15 downto 0
PARAMETER_STRING
USR
}
# hierarchies {
std_1c20:inst|clock_1_out_arbitrator:the_clock_1_out
}
# end
# entity
connector_pll_s1_arbitrator
# storage
db|standard.(26).cnf
db|standard.(26).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
std_1c20.vhd
67356db08fbff5d04aed26fe53d6daae
4
# internal_option {
AUTO_RESOURCE_SHARING
OFF
}
# user_parameter {
 constraint(clock_1_out_address_to_slave)
3 downto 0
PARAMETER_STRING
USR
 constraint(clock_1_out_nativeaddress)
2 downto 0
PARAMETER_STRING
USR
 constraint(clock_1_out_writedata)
15 downto 0
PARAMETER_STRING
USR
 constraint(connector_pll_s1_readdata)
15 downto 0
PARAMETER_STRING
USR
 constraint(connector_pll_s1_address)
2 downto 0
PARAMETER_STRING
USR
 constraint(connector_pll_s1_readdata_from_sa)
15 downto 0
PARAMETER_STRING
USR
 constraint(connector_pll_s1_writedata)
15 downto 0
PARAMETER_STRING
USR
}
# hierarchies {
std_1c20:inst|connector_pll_s1_arbitrator:the_connector_pll_s1
}
# end
# entity
cpu_jtag_debug_module_arbitrator
# storage
db|standard.(30).cnf
db|standard.(30).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
std_1c20.vhd
67356db08fbff5d04aed26fe53d6daae
4
# internal_option {
AUTO_RESOURCE_SHARING
OFF
}
# user_parameter {
 constraint(cpu_data_master_address_to_slave)
25 downto 0
PARAMETER_STRING
USR
 constraint(cpu_data_master_byteenable)
3 downto 0
PARAMETER_STRING
USR
 constraint(cpu_data_master_writedata)
31 downto 0
PARAMETER_STRING
USR
 constraint(cpu_instruction_master_address_to_slave)
25 downto 0
PARAMETER_STRING
USR
 constraint(cpu_instruction_master_latency_counter)
1 downto 0
PARAMETER_STRING
USR
 constraint(cpu_jtag_debug_module_readdata)
31 downto 0
PARAMETER_STRING
USR
 constraint(cpu_jtag_debug_module_address)
8 downto 0
PARAMETER_STRING
USR
 constraint(cpu_jtag_debug_module_byteenable)
3 downto 0
PARAMETER_STRING
USR
 constraint(cpu_jtag_debug_module_readdata_from_sa)
31 downto 0
PARAMETER_STRING
USR
 constraint(cpu_jtag_debug_module_writedata)
31 downto 0
PARAMETER_STRING
USR
}
# hierarchies {
std_1c20:inst|cpu_jtag_debug_module_arbitrator:the_cpu_jtag_debug_module
}
# end
# entity
cpu_custom_instruction_master_arbitrator
# storage
db|standard.(31).cnf
db|standard.(31).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
std_1c20.vhd
67356db08fbff5d04aed26fe53d6daae
4
# internal_option {
AUTO_RESOURCE_SHARING
OFF
}
# user_parameter {
 constraint(cpu_custom_instruction_master_combo_n)
7 downto 0
PARAMETER_STRING
USR
 constraint(custominstruction1_cpu_s1_result_from_sa)
31 downto 0
PARAMETER_STRING
USR
 constraint(custominstruction2_cpu_s1_result_from_sa)
31 downto 0
PARAMETER_STRING
USR
 constraint(custominstruction3_cpu_s1_result_from_sa)
31 downto 0
PARAMETER_STRING
USR
 constraint(custominstruction_cpu_s1_result_from_sa)
31 downto 0
PARAMETER_STRING
USR
 constraint(cpu_custom_instruction_master_combo_result)
31 downto 0
PARAMETER_STRING
USR
}
# hierarchies {
std_1c20:inst|cpu_custom_instruction_master_arbitrator:the_cpu_custom_instruction_master
}
# end
# entity
cpu_data_master_arbitrator
# storage
db|standard.(32).cnf
db|standard.(32).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
std_1c20.vhd
67356db08fbff5d04aed26fe53d6daae
4
# internal_option {
AUTO_RESOURCE_SHARING
OFF
}
# user_parameter {
 constraint(button_pio_s1_readdata_from_sa)
3 downto 0
PARAMETER_STRING
USR
 constraint(clock_0_in_readdata_from_sa)
15 downto 0
PARAMETER_STRING
USR
 constraint(clock_1_in_readdata_from_sa)
15 downto 0
PARAMETER_STRING
USR
 constraint(cpu_data_master_address)
25 downto 0
PARAMETER_STRING
USR
 constraint(cpu_data_master_writedata)
31 downto 0
PARAMETER_STRING
USR
 constraint(cpu_jtag_debug_module_readdata_from_sa)
31 downto 0
PARAMETER_STRING
USR
 constraint(epcs_controller_epcs_control_port_readdata_from_sa)
31 downto 0
PARAMETER_STRING
USR
 constraint(high_res_timer_s1_readdata_from_sa)
15 downto 0
PARAMETER_STRING
USR
 constraint(incoming_ext_ram_bus_data)
31 downto 0
PARAMETER_STRING
USR
 constraint(incoming_ext_ram_bus_data_with_xs_converted_to_0)
7 downto 0
PARAMETER_STRING
USR
 constraint(jtag_uart_avalon_jtag_slave_readdata_from_sa)
31 downto 0
PARAMETER_STRING
USR
 constraint(lcd_display_control_slave_readdata_from_sa)
7 downto 0
PARAMETER_STRING
USR
 constraint(sdram_s1_readdata_from_sa)
31 downto 0
PARAMETER_STRING
USR
 constraint(sys_clk_timer_s1_readdata_from_sa)
15 downto 0
PARAMETER_STRING
USR
 constraint(sysid_control_slave_readdata_from_sa)
31 downto 0
PARAMETER_STRING
USR
 constraint(uart1_s1_readdata_from_sa)
15 downto 0
PARAMETER_STRING
USR
 constraint(cpu_data_master_address_to_slave)
25 downto 0
PARAMETER_STRING
USR
 constraint(cpu_data_master_dbs_address)
1 downto 0
PARAMETER_STRING
USR
 constraint(cpu_data_master_dbs_write_8)
7 downto 0
PARAMETER_STRING
USR
 constraint(cpu_data_master_irq)
31 downto 0
PARAMETER_STRING
USR
 constraint(cpu_data_master_readdata)
31 downto 0
PARAMETER_STRING
USR
}
# hierarchies {
std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master
}
# end
# entity
cpu_instruction_master_arbitrator
# storage
db|standard.(33).cnf
db|standard.(33).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
std_1c20.vhd
67356db08fbff5d04aed26fe53d6daae
4
# internal_option {
AUTO_RESOURCE_SHARING
OFF
}
# user_parameter {
 constraint(cpu_instruction_master_address)
25 downto 0
PARAMETER_STRING
USR
 constraint(cpu_jtag_debug_module_readdata_from_sa)
31 downto 0
PARAMETER_STRING
USR
 constraint(epcs_controller_epcs_control_port_readdata_from_sa)
31 downto 0
PARAMETER_STRING
USR
 constraint(incoming_ext_ram_bus_data)
31 downto 0
PARAMETER_STRING
USR
 constraint(sdram_s1_readdata_from_sa)
31 downto 0
PARAMETER_STRING
USR
 constraint(cpu_instruction_master_address_to_slave)
25 downto 0
PARAMETER_STRING
USR
 constraint(cpu_instruction_master_dbs_address)
1 downto 0
PARAMETER_STRING
USR
 constraint(cpu_instruction_master_latency_counter)
1 downto 0
PARAMETER_STRING
USR
 constraint(cpu_instruction_master_readdata)
31 downto 0
PARAMETER_STRING
USR
}
# hierarchies {
std_1c20:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master
}
# end
# entity
cpu
# storage
db|standard.(34).cnf
db|standard.(34).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
cpu.vhd
e9ec71d96ec33ff62ec32bca866f37f6
4
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
AUTO_RESOURCE_SHARING
OFF
}
# user_parameter {
 constraint(e_ci_combo_result)
31 downto 0
PARAMETER_STRING
USR
 constraint(d_irq)
31 downto 0
PARAMETER_STRING
USR
 constraint(d_readdata)
31 downto 0
PARAMETER_STRING
USR
 constraint(i_readdata)
31 downto 0
PARAMETER_STRING
USR
 constraint(jtag_debug_module_address)
8 downto 0
PARAMETER_STRING
USR
 constraint(jtag_debug_module_byteenable)
3 downto 0
PARAMETER_STRING
USR
 constraint(jtag_debug_module_writedata)
31 downto 0
PARAMETER_STRING
USR
 constraint(e_ci_combo_a)
4 downto 0
PARAMETER_STRING
USR
 constraint(e_ci_combo_b)
4 downto 0
PARAMETER_STRING
USR
 constraint(e_ci_combo_c)
4 downto 0
PARAMETER_STRING
USR
 constraint(e_ci_combo_dataa)
31 downto 0
PARAMETER_STRING
USR
 constraint(e_ci_combo_datab)
31 downto 0
PARAMETER_STRING
USR
 constraint(e_ci_combo_ipending)
31 downto 0
PARAMETER_STRING
USR
 constraint(e_ci_combo_n)
7 downto 0
PARAMETER_STRING
USR
 constraint(d_address)
25 downto 0
PARAMETER_STRING
USR
 constraint(d_byteenable)
3 downto 0
PARAMETER_STRING
USR
 constraint(d_writedata)
31 downto 0
PARAMETER_STRING
USR
 constraint(i_address)
25 downto 0
PARAMETER_STRING
USR
 constraint(jtag_debug_module_readdata)
31 downto 0
PARAMETER_STRING
USR
}
# hierarchies {
std_1c20:inst|cpu:the_cpu
}
# end
# entity
cpu_test_bench
# storage
db|standard.(35).cnf
db|standard.(35).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
cpu_test_bench.vhd
851f357fe5242740281b1558bd09c20
4
# internal_option {
AUTO_RESOURCE_SHARING
OFF
}
# user_parameter {
 constraint(e_src1)
31 downto 0
PARAMETER_STRING
USR
 constraint(e_src2)
31 downto 0
PARAMETER_STRING
USR
 constraint(m_alu_result)
31 downto 0
PARAMETER_STRING
USR
 constraint(m_dst_regnum)
4 downto 0
PARAMETER_STRING
USR
 constraint(m_ienable_reg)
31 downto 0
PARAMETER_STRING
USR
 constraint(m_ipending_reg)
31 downto 0
PARAMETER_STRING
USR
 constraint(m_iw)
31 downto 0
PARAMETER_STRING
USR
 constraint(m_mem_byte_en)
3 downto 0
PARAMETER_STRING
USR
 constraint(m_pcb)
25 downto 0
PARAMETER_STRING
USR
 constraint(m_st_data)
31 downto 0
PARAMETER_STRING
USR
 constraint(m_wr_data_unfiltered)
31 downto 0
PARAMETER_STRING
USR
 constraint(w_dst_regnum)
4 downto 0
PARAMETER_STRING
USR
 constraint(w_iw)
31 downto 0
PARAMETER_STRING
USR
 constraint(w_iw_custom_n)
7 downto 0
PARAMETER_STRING
USR
 constraint(w_iw_op)
5 downto 0
PARAMETER_STRING
USR
 constraint(w_iw_opx)
5 downto 0
PARAMETER_STRING
USR
 constraint(w_pcb)
25 downto 0
PARAMETER_STRING
USR
 constraint(w_wr_data)
31 downto 0
PARAMETER_STRING
USR
 constraint(d_address)
25 downto 0
PARAMETER_STRING
USR
 constraint(d_byteenable)
3 downto 0
PARAMETER_STRING
USR
 constraint(i_address)
25 downto 0
PARAMETER_STRING
USR
 constraint(m_wr_data_filtered)
31 downto 0
PARAMETER_STRING
USR
}
# hierarchies {
std_1c20:inst|cpu:the_cpu|cpu_test_bench:the_cpu_test_bench
}
# end
# entity
cpu_ic_data_module
# storage
db|standard.(38).cnf
db|standard.(38).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
cpu.vhd
e9ec71d96ec33ff62ec32bca866f37f6
4
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
AUTO_RESOURCE_SHARING
OFF
}
# user_parameter {
lpm_file

PARAMETER_STRING
USR
 constraint(data)
31 downto 0
PARAMETER_STRING
USR
 constraint(rdaddress)
9 downto 0
PARAMETER_STRING
USR
 constraint(wraddress)
9 downto 0
PARAMETER_STRING
USR
 constraint(q)
31 downto 0
PARAMETER_STRING
USR
}
# hierarchies {
std_1c20:inst|cpu:the_cpu|cpu_ic_data_module:cpu_ic_data
}
# end
# entity
cpu_ic_tag_module
# storage
db|standard.(40).cnf
db|standard.(40).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
cpu.vhd
e9ec71d96ec33ff62ec32bca866f37f6
4
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
AUTO_RESOURCE_SHARING
OFF
}
# user_parameter {
lpm_file
cpu_ic_tag_ram.mif
PARAMETER_STRING
USR
 constraint(data)
21 downto 0
PARAMETER_STRING
USR
 constraint(rdaddress)
6 downto 0
PARAMETER_STRING
USR
 constraint(wraddress)
6 downto 0
PARAMETER_STRING
USR
 constraint(q)
21 downto 0
PARAMETER_STRING
USR
}
# hierarchies {
std_1c20:inst|cpu:the_cpu|cpu_ic_tag_module:cpu_ic_tag
}
# end
# entity
altsyncram_09e1
# storage
db|standard.(41).cnf
db|standard.(41).cnf
# case_insensitive
# source_file
db|altsyncram_09e1.tdf
9af9dd7bc4592d8f7143b24e38765349
6
# user_parameter {
PORT_A_ADDRESS_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_A_BYTE_ENABLE_MASK_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_A_DATA_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_B_ADDRESS_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_B_BYTE_ENABLE_MASK_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_B_DATA_WIDTH
1
PARAMETER_UNKNOWN
DEF
}
# used_port {
wren_a
-1
3
q_b9
-1
3
q_b8
-1
3
q_b7
-1
3
q_b6
-1
3
q_b5
-1
3
q_b4
-1
3
q_b3
-1
3
q_b21
-1
3
q_b20
-1
3
q_b2
-1
3
q_b19
-1
3
q_b18
-1
3
q_b17
-1
3
q_b16
-1
3
q_b15
-1
3
q_b14
-1
3
q_b13
-1
3
q_b12
-1
3
q_b11
-1
3
q_b10
-1
3
q_b1
-1
3
q_b0
-1
3
data_a9
-1
3
data_a8
-1
3
data_a7
-1
3
data_a6
-1
3
data_a5
-1
3
data_a4
-1
3
data_a3
-1
3
data_a21
-1
3
data_a20
-1
3
data_a2
-1
3
data_a19
-1
3
data_a18
-1
3
data_a17
-1
3
data_a16
-1
3
data_a15
-1
3
data_a14
-1
3
data_a13
-1
3
data_a12
-1
3
data_a11
-1
3
data_a10
-1
3
data_a1
-1
3
data_a0
-1
3
clocken1
-1
3
clock1
-1
3
clock0
-1
3
address_b6
-1
3
address_b5
-1
3
address_b4
-1
3
address_b3
-1
3
address_b2
-1
3
address_b1
-1
3
address_b0
-1
3
address_a6
-1
3
address_a5
-1
3
address_a4
-1
3
address_a3
-1
3
address_a2
-1
3
address_a1
-1
3
address_a0
-1
3
}
# memory_file {
cpu_ic_tag_ram.mif
10733d5458307d84e04c83aaff85923c
}
# hierarchies {
std_1c20:inst|cpu:the_cpu|cpu_ic_tag_module:cpu_ic_tag|altsyncram:the_altsyncram|altsyncram_09e1:auto_generated
}
# end
# entity
cpu_register_bank_a_module
# storage
db|standard.(44).cnf
db|standard.(44).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
cpu.vhd
e9ec71d96ec33ff62ec32bca866f37f6
4
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
AUTO_RESOURCE_SHARING
OFF
}
# user_parameter {
lpm_file
cpu_rf_ram_a.mif
PARAMETER_STRING
USR
 constraint(data)
31 downto 0
PARAMETER_STRING
USR
 constraint(rdaddress)
4 downto 0
PARAMETER_STRING
USR
 constraint(wraddress)
4 downto 0
PARAMETER_STRING
USR
 constraint(q)
31 downto 0
PARAMETER_STRING
USR
}
# hierarchies {
std_1c20:inst|cpu:the_cpu|cpu_register_bank_a_module:cpu_register_bank_a
}
# end
# entity
cpu_register_bank_b_module
# storage
db|standard.(47).cnf
db|standard.(47).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
cpu.vhd
e9ec71d96ec33ff62ec32bca866f37f6
4
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
AUTO_RESOURCE_SHARING
OFF
}
# user_parameter {
lpm_file
cpu_rf_ram_b.mif
PARAMETER_STRING
USR
 constraint(data)
31 downto 0
PARAMETER_STRING
USR
 constraint(rdaddress)
4 downto 0
PARAMETER_STRING
USR
 constraint(wraddress)
4 downto 0
PARAMETER_STRING
USR
 constraint(q)
31 downto 0
PARAMETER_STRING
USR
}
# hierarchies {
std_1c20:inst|cpu:the_cpu|cpu_register_bank_b_module:cpu_register_bank_b
}
# end
# entity
cpu_nios2_oci
# storage
db|standard.(48).cnf
db|standard.(48).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
cpu.vhd
e9ec71d96ec33ff62ec32bca866f37f6
4
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
AUTO_RESOURCE_SHARING
OFF
}
# user_parameter {
 constraint(f_pc)
23 downto 0
PARAMETER_STRING
USR
 constraint(m_mem_baddr)
25 downto 0
PARAMETER_STRING
USR
 constraint(m_pcb)
25 downto 0
PARAMETER_STRING
USR
 constraint(m_st_data)
31 downto 0
PARAMETER_STRING
USR
 constraint(m_wr_data_filtered)
31 downto 0
PARAMETER_STRING
USR
 constraint(address)
8 downto 0
PARAMETER_STRING
USR
 constraint(byteenable)
3 downto 0
PARAMETER_STRING
USR
 constraint(writedata)
31 downto 0
PARAMETER_STRING
USR
 constraint(oci_ienable)
31 downto 0
PARAMETER_STRING
USR
 constraint(readdata)
31 downto 0
PARAMETER_STRING
USR
}
# hierarchies {
std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci
}
# end
# entity
cpu_nios2_oci_debug
# storage
db|standard.(49).cnf
db|standard.(49).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
cpu.vhd
e9ec71d96ec33ff62ec32bca866f37f6
4
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
AUTO_RESOURCE_SHARING
OFF
}
# user_parameter {
 constraint(jdo)
37 downto 0
PARAMETER_STRING
USR
}
# hierarchies {
std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_debug:the_cpu_nios2_oci_debug
}
# end
# entity
cpu_nios2_ocimem
# storage
db|standard.(50).cnf
db|standard.(50).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
cpu.vhd
e9ec71d96ec33ff62ec32bca866f37f6
4
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
AUTO_RESOURCE_SHARING
OFF
}
# user_parameter {
 constraint(address)
8 downto 0
PARAMETER_STRING
USR
 constraint(byteenable)
3 downto 0
PARAMETER_STRING
USR
 constraint(jdo)
37 downto 0
PARAMETER_STRING
USR
 constraint(writedata)
31 downto 0
PARAMETER_STRING
USR
 constraint(mondreg)
31 downto 0
PARAMETER_STRING
USR
 constraint(oci_ram_readdata)
31 downto 0
PARAMETER_STRING
USR
}
# hierarchies {
std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem
}
# end
# entity
cpu_ociram_lpm_dram_bdp_component_module
# storage
db|standard.(52).cnf
db|standard.(52).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
cpu.vhd
e9ec71d96ec33ff62ec32bca866f37f6
4
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
AUTO_RESOURCE_SHARING
OFF
}
# user_parameter {
lpm_file
cpu_ociram_default_contents.mif
PARAMETER_STRING
USR
 constraint(address_a)
7 downto 0
PARAMETER_STRING
USR
 constraint(address_b)
7 downto 0
PARAMETER_STRING
USR
 constraint(byteena_a)
3 downto 0
PARAMETER_STRING
USR
 constraint(data_a)
31 downto 0
PARAMETER_STRING
USR
 constraint(data_b)
31 downto 0
PARAMETER_STRING
USR
 constraint(q_a)
31 downto 0
PARAMETER_STRING
USR
 constraint(q_b)
31 downto 0
PARAMETER_STRING
USR
}
# hierarchies {
std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|cpu_ociram_lpm_dram_bdp_component_module:cpu_ociram_lpm_dram_bdp_component
}
# end
# entity
cpu_nios2_avalon_reg
# storage
db|standard.(54).cnf
db|standard.(54).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
cpu.vhd
e9ec71d96ec33ff62ec32bca866f37f6
4
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
AUTO_RESOURCE_SHARING
OFF
}
# user_parameter {
 constraint(address)
8 downto 0
PARAMETER_STRING
USR
 constraint(writedata)
31 downto 0
PARAMETER_STRING
USR
 constraint(oci_ienable)
31 downto 0
PARAMETER_STRING
USR
 constraint(oci_reg_readdata)
31 downto 0
PARAMETER_STRING
USR
}
# hierarchies {
std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_avalon_reg:the_cpu_nios2_avalon_reg
}
# end
# entity
cpu_nios2_oci_break
# storage
db|standard.(55).cnf
db|standard.(55).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
cpu.vhd
e9ec71d96ec33ff62ec32bca866f37f6
4
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
AUTO_RESOURCE_SHARING
OFF
}
# user_parameter {
 constraint(jdo)
37 downto 0
PARAMETER_STRING
USR
 constraint(break_readreg)
31 downto 0
PARAMETER_STRING
USR
 constraint(dbrk0)
77 downto 0
PARAMETER_STRING
USR
 constraint(dbrk1)
77 downto 0
PARAMETER_STRING
USR
 constraint(dbrk2)
77 downto 0
PARAMETER_STRING
USR
 constraint(dbrk3)
77 downto 0
PARAMETER_STRING
USR
 constraint(xbrk0)
25 downto 0
PARAMETER_STRING
USR
 constraint(xbrk1)
25 downto 0
PARAMETER_STRING
USR
 constraint(xbrk2)
25 downto 0
PARAMETER_STRING
USR
 constraint(xbrk3)
25 downto 0
PARAMETER_STRING
USR
 constraint(xbrk_ctrl0)
7 downto 0
PARAMETER_STRING
USR
 constraint(xbrk_ctrl1)
7 downto 0
PARAMETER_STRING
USR
 constraint(xbrk_ctrl2)
7 downto 0
PARAMETER_STRING
USR
 constraint(xbrk_ctrl3)
7 downto 0
PARAMETER_STRING
USR
}
# hierarchies {
std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_break:the_cpu_nios2_oci_break
}
# end
# entity
cpu_nios2_oci_xbrk
# storage
db|standard.(56).cnf
db|standard.(56).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
cpu.vhd
e9ec71d96ec33ff62ec32bca866f37f6
4
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
AUTO_RESOURCE_SHARING
OFF
}
# user_parameter {
 constraint(f_pc)
23 downto 0
PARAMETER_STRING
USR
 constraint(xbrk0)
25 downto 0
PARAMETER_STRING
USR
 constraint(xbrk1)
25 downto 0
PARAMETER_STRING
USR
 constraint(xbrk2)
25 downto 0
PARAMETER_STRING
USR
 constraint(xbrk3)
25 downto 0
PARAMETER_STRING
USR
 constraint(xbrk_ctrl0)
7 downto 0
PARAMETER_STRING
USR
 constraint(xbrk_ctrl1)
7 downto 0
PARAMETER_STRING
USR
 constraint(xbrk_ctrl2)
7 downto 0
PARAMETER_STRING
USR
 constraint(xbrk_ctrl3)
7 downto 0
PARAMETER_STRING
USR
}
# hierarchies {
std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_xbrk:the_cpu_nios2_oci_xbrk
}
# end
# entity
cpu_nios2_oci_dbrk
# storage
db|standard.(57).cnf
db|standard.(57).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
cpu.vhd
e9ec71d96ec33ff62ec32bca866f37f6
4
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
AUTO_RESOURCE_SHARING
OFF
}
# user_parameter {
 constraint(m_mem_baddr)
25 downto 0
PARAMETER_STRING
USR
 constraint(m_st_data)
31 downto 0
PARAMETER_STRING
USR
 constraint(m_wr_data_filtered)
31 downto 0
PARAMETER_STRING
USR
 constraint(dbrk0)
77 downto 0
PARAMETER_STRING
USR
 constraint(dbrk1)
77 downto 0
PARAMETER_STRING
USR
 constraint(dbrk2)
77 downto 0
PARAMETER_STRING
USR
 constraint(dbrk3)
77 downto 0
PARAMETER_STRING
USR
 constraint(cpu_d_address)
25 downto 0
PARAMETER_STRING
USR
 constraint(cpu_d_readdata)
31 downto 0
PARAMETER_STRING
USR
 constraint(cpu_d_writedata)
31 downto 0
PARAMETER_STRING
USR
}
# hierarchies {
std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_dbrk:the_cpu_nios2_oci_dbrk
}
# end
# entity
cpu_nios2_oci_match_paired
# storage
db|standard.(58).cnf
db|standard.(58).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
cpu.vhd
e9ec71d96ec33ff62ec32bca866f37f6
4
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
AUTO_RESOURCE_SHARING
OFF
}
# user_parameter {
 constraint(addr)
25 downto 0
PARAMETER_STRING
USR
 constraint(data)
31 downto 0
PARAMETER_STRING
USR
 constraint(dbrka)
70 downto 0
PARAMETER_STRING
USR
 constraint(dbrkb)
70 downto 0
PARAMETER_STRING
USR
}
# hierarchies {
std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_dbrk:the_cpu_nios2_oci_dbrk|cpu_nios2_oci_match_paired:cpu_nios2_oci_dbrk_hit0_match_paired
std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_dbrk:the_cpu_nios2_oci_dbrk|cpu_nios2_oci_match_paired:cpu_nios2_oci_dbrk_hit2_match_paired
}
# end
# entity
cpu_nios2_oci_match_single
# storage
db|standard.(59).cnf
db|standard.(59).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
cpu.vhd
e9ec71d96ec33ff62ec32bca866f37f6
4
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
AUTO_RESOURCE_SHARING
OFF
}
# user_parameter {
 constraint(addr)
25 downto 0
PARAMETER_STRING
USR
 constraint(data)
31 downto 0
PARAMETER_STRING
USR
 constraint(dbrk)
70 downto 0
PARAMETER_STRING
USR
}
# hierarchies {
std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_dbrk:the_cpu_nios2_oci_dbrk|cpu_nios2_oci_match_single:cpu_nios2_oci_dbrk_hit0_match_single
std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_dbrk:the_cpu_nios2_oci_dbrk|cpu_nios2_oci_match_single:cpu_nios2_oci_dbrk_hit1_match_single
std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_dbrk:the_cpu_nios2_oci_dbrk|cpu_nios2_oci_match_single:cpu_nios2_oci_dbrk_hit2_match_single
std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_dbrk:the_cpu_nios2_oci_dbrk|cpu_nios2_oci_match_single:cpu_nios2_oci_dbrk_hit3_match_single
}
# end
# entity
cpu_nios2_oci_itrace
# storage
db|standard.(60).cnf
db|standard.(60).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
cpu.vhd
e9ec71d96ec33ff62ec32bca866f37f6
4
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
AUTO_RESOURCE_SHARING
OFF
}
# user_parameter {
 constraint(m_pcb)
25 downto 0
PARAMETER_STRING
USR
 constraint(m_wr_data_filtered)
31 downto 0
PARAMETER_STRING
USR
 constraint(jdo)
15 downto 0
PARAMETER_STRING
USR
 constraint(itm)
35 downto 0
PARAMETER_STRING
USR
 constraint(trc_ctrl)
15 downto 0
PARAMETER_STRING
USR
}
# hierarchies {
std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_itrace:the_cpu_nios2_oci_itrace
}
# end
# entity
cpu_nios2_oci_dtrace
# storage
db|standard.(61).cnf
db|standard.(61).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
cpu.vhd
e9ec71d96ec33ff62ec32bca866f37f6
4
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
AUTO_RESOURCE_SHARING
OFF
}
# user_parameter {
 constraint(cpu_d_address)
25 downto 0
PARAMETER_STRING
USR
 constraint(cpu_d_readdata)
31 downto 0
PARAMETER_STRING
USR
 constraint(cpu_d_writedata)
31 downto 0
PARAMETER_STRING
USR
 constraint(trc_ctrl)
15 downto 0
PARAMETER_STRING
USR
 constraint(atm)
35 downto 0
PARAMETER_STRING
USR
 constraint(dtm)
35 downto 0
PARAMETER_STRING
USR
}
# hierarchies {
std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_dtrace:the_cpu_nios2_oci_dtrace
}
# end
# entity
cpu_nios2_oci_td_mode
# storage
db|standard.(62).cnf
db|standard.(62).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
cpu.vhd
e9ec71d96ec33ff62ec32bca866f37f6
4
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
AUTO_RESOURCE_SHARING
OFF
}
# user_parameter {
 constraint(ctrl)
8 downto 0
PARAMETER_STRING
USR
 constraint(td_mode)
3 downto 0
PARAMETER_STRING
USR
}
# hierarchies {
std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_dtrace:the_cpu_nios2_oci_dtrace|cpu_nios2_oci_td_mode:cpu_nios2_oci_trc_ctrl_td_mode
}
# end
# entity
cpu_nios2_oci_fifo
# storage
db|standard.(63).cnf
db|standard.(63).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
cpu.vhd
e9ec71d96ec33ff62ec32bca866f37f6
4
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
AUTO_RESOURCE_SHARING
OFF
}
# user_parameter {
 constraint(atm)
35 downto 0
PARAMETER_STRING
USR
 constraint(dtm)
35 downto 0
PARAMETER_STRING
USR
 constraint(itm)
35 downto 0
PARAMETER_STRING
USR
 constraint(tw)
35 downto 0
PARAMETER_STRING
USR
}
# hierarchies {
std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_fifo:the_cpu_nios2_oci_fifo
}
# end
# entity
cpu_nios2_oci_compute_tm_count
# storage
db|standard.(64).cnf
db|standard.(64).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
cpu.vhd
e9ec71d96ec33ff62ec32bca866f37f6
4
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
AUTO_RESOURCE_SHARING
OFF
}
# user_parameter {
 constraint(compute_tm_count)
1 downto 0
PARAMETER_STRING
USR
}
# hierarchies {
std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_fifo:the_cpu_nios2_oci_fifo|cpu_nios2_oci_compute_tm_count:cpu_nios2_oci_compute_tm_count_tm_count
}
# end
# entity
cpu_nios2_oci_fifowp_inc
# storage
db|standard.(65).cnf
db|standard.(65).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
cpu.vhd
e9ec71d96ec33ff62ec32bca866f37f6
4
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
AUTO_RESOURCE_SHARING
OFF
}
# user_parameter {
 constraint(tm_count)
1 downto 0
PARAMETER_STRING
USR
 constraint(fifowp_inc)
3 downto 0
PARAMETER_STRING
USR
}
# hierarchies {
std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_fifo:the_cpu_nios2_oci_fifo|cpu_nios2_oci_fifowp_inc:cpu_nios2_oci_fifowp_inc_fifowp
}
# end
# entity
cpu_nios2_oci_fifocount_inc
# storage
db|standard.(66).cnf
db|standard.(66).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
cpu.vhd
e9ec71d96ec33ff62ec32bca866f37f6
4
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
AUTO_RESOURCE_SHARING
OFF
}
# user_parameter {
 constraint(tm_count)
1 downto 0
PARAMETER_STRING
USR
 constraint(fifocount_inc)
4 downto 0
PARAMETER_STRING
USR
}
# hierarchies {
std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_fifo:the_cpu_nios2_oci_fifo|cpu_nios2_oci_fifocount_inc:cpu_nios2_oci_fifocount_inc_fifocount
}
# end
# entity
cpu_nios2_oci_pib
# storage
db|standard.(67).cnf
db|standard.(67).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
cpu.vhd
e9ec71d96ec33ff62ec32bca866f37f6
4
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
AUTO_RESOURCE_SHARING
OFF
}
# user_parameter {
 constraint(tw)
35 downto 0
PARAMETER_STRING
USR
 constraint(tr_data)
17 downto 0
PARAMETER_STRING
USR
}
# hierarchies {
std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_pib:the_cpu_nios2_oci_pib
}
# end
# entity
cpu_nios2_oci_im
# storage
db|standard.(68).cnf
db|standard.(68).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
cpu.vhd
e9ec71d96ec33ff62ec32bca866f37f6
4
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
AUTO_RESOURCE_SHARING
OFF
}
# user_parameter {
 constraint(jdo)
37 downto 0
PARAMETER_STRING
USR
 constraint(trc_ctrl)
15 downto 0
PARAMETER_STRING
USR
 constraint(tw)
35 downto 0
PARAMETER_STRING
USR
 constraint(tracemem_trcdata)
35 downto 0
PARAMETER_STRING
USR
 constraint(trc_im_addr)
6 downto 0
PARAMETER_STRING
USR
}
# hierarchies {
std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_im:the_cpu_nios2_oci_im
}
# end
# entity
cpu_traceram_lpm_dram_bdp_component_module
# storage
db|standard.(71).cnf
db|standard.(71).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
cpu.vhd
e9ec71d96ec33ff62ec32bca866f37f6
4
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
AUTO_RESOURCE_SHARING
OFF
}
# user_parameter {
lpm_file

PARAMETER_STRING
USR
 constraint(address_a)
6 downto 0
PARAMETER_STRING
USR
 constraint(address_b)
6 downto 0
PARAMETER_STRING
USR
 constraint(data_a)
35 downto 0
PARAMETER_STRING
USR
 constraint(data_b)
35 downto 0
PARAMETER_STRING
USR
 constraint(q_a)
35 downto 0
PARAMETER_STRING
USR
 constraint(q_b)
35 downto 0
PARAMETER_STRING
USR
}
# hierarchies {
std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_im:the_cpu_nios2_oci_im|cpu_traceram_lpm_dram_bdp_component_module:cpu_traceram_lpm_dram_bdp_component
}
# end
# entity
cpu_jtag_debug_module_wrapper
# storage
db|standard.(72).cnf
db|standard.(72).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
cpu_jtag_debug_module_wrapper.vhd
fd45931bfd2752fbe13f499b384a479
4
# internal_option {
AUTO_RESOURCE_SHARING
OFF
}
# user_parameter {
 constraint(mondreg)
31 downto 0
PARAMETER_STRING
USR
 constraint(break_readreg)
31 downto 0
PARAMETER_STRING
USR
 constraint(tracemem_trcdata)
35 downto 0
PARAMETER_STRING
USR
 constraint(trc_im_addr)
6 downto 0
PARAMETER_STRING
USR
 constraint(jdo)
37 downto 0
PARAMETER_STRING
USR
}
# hierarchies {
std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper
}
# end
# entity
cpu_jtag_debug_module
# storage
db|standard.(73).cnf
db|standard.(73).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
cpu_jtag_debug_module.vhd
2280471290461421f905627974d35
4
# internal_option {
AUTO_RESOURCE_SHARING
OFF
}
# user_parameter {
sld_node_info
286279168
PARAMETER_DEC
USR
 constraint(mondreg)
31 downto 0
PARAMETER_STRING
USR
 constraint(break_readreg)
31 downto 0
PARAMETER_STRING
USR
 constraint(tracemem_trcdata)
35 downto 0
PARAMETER_STRING
USR
 constraint(trc_im_addr)
6 downto 0
PARAMETER_STRING
USR
 constraint(jdo)
37 downto 0
PARAMETER_STRING
USR
}
# hierarchies {
std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1
}
# end
# entity
custominstruction1_cpu_s1_arbitrator
# storage
db|standard.(74).cnf
db|standard.(74).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
std_1c20.vhd
67356db08fbff5d04aed26fe53d6daae
4
# internal_option {
AUTO_RESOURCE_SHARING
OFF
}
# user_parameter {
 constraint(cpu_custom_instruction_master_combo_dataa)
31 downto 0
PARAMETER_STRING
USR
 constraint(cpu_custom_instruction_master_combo_datab)
31 downto 0
PARAMETER_STRING
USR
 constraint(custominstruction1_cpu_s1_result)
31 downto 0
PARAMETER_STRING
USR
 constraint(custominstruction1_cpu_s1_dataa)
31 downto 0
PARAMETER_STRING
USR
 constraint(custominstruction1_cpu_s1_datab)
31 downto 0
PARAMETER_STRING
USR
 constraint(custominstruction1_cpu_s1_result_from_sa)
31 downto 0
PARAMETER_STRING
USR
}
# hierarchies {
std_1c20:inst|custominstruction1_cpu_s1_arbitrator:the_custominstruction1_cpu_s1
}
# end
# entity
custominstruction1_cpu
# storage
db|standard.(75).cnf
db|standard.(75).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
custominstruction1_cpu.vhd
7a263d29040ce92e4ecc2d7b6a4fb7
4
# internal_option {
AUTO_RESOURCE_SHARING
OFF
}
# user_parameter {
 constraint(dataa)
31 downto 0
PARAMETER_STRING
USR
 constraint(datab)
31 downto 0
PARAMETER_STRING
USR
 constraint(result)
31 downto 0
PARAMETER_STRING
USR
}
# hierarchies {
std_1c20:inst|custominstruction1_cpu:the_custominstruction1_cpu
}
# end
# entity
subbytes
# storage
db|standard.(76).cnf
db|standard.(76).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
subbytes.vhd
cc79838fcf7f205be6747fb56bd24f54
4
# internal_option {
AUTO_RESOURCE_SHARING
OFF
}
# user_parameter {
 constraint(dataa)
31 downto 0
PARAMETER_STRING
USR
 constraint(datab)
31 downto 0
PARAMETER_STRING
USR
 constraint(result)
31 downto 0
PARAMETER_STRING
USR
}
# hierarchies {
std_1c20:inst|custominstruction1_cpu:the_custominstruction1_cpu|subbytes:the_subbytes
}
# end
# entity
custominstruction2_cpu_s1_arbitrator
# storage
db|standard.(79).cnf
db|standard.(79).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
std_1c20.vhd
67356db08fbff5d04aed26fe53d6daae
4
# internal_option {
AUTO_RESOURCE_SHARING
OFF
}
# user_parameter {
 constraint(cpu_custom_instruction_master_combo_dataa)
31 downto 0
PARAMETER_STRING
USR
 constraint(cpu_custom_instruction_master_combo_datab)
31 downto 0
PARAMETER_STRING
USR
 constraint(custominstruction2_cpu_s1_result)
31 downto 0
PARAMETER_STRING
USR
 constraint(custominstruction2_cpu_s1_datab)
31 downto 0
PARAMETER_STRING
USR
 constraint(custominstruction2_cpu_s1_result_from_sa)
31 downto 0
PARAMETER_STRING
USR
}
# hierarchies {
std_1c20:inst|custominstruction2_cpu_s1_arbitrator:the_custominstruction2_cpu_s1
}
# end
# entity
custominstruction2_cpu
# storage
db|standard.(80).cnf
db|standard.(80).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
custominstruction2_cpu.vhd
b8bf489380ac35e96f93dddec41e489a
4
# internal_option {
AUTO_RESOURCE_SHARING
OFF
}
# user_parameter {
 constraint(dataa)
31 downto 0
PARAMETER_STRING
USR
 constraint(datab)
31 downto 0
PARAMETER_STRING
USR
 constraint(result)
31 downto 0
PARAMETER_STRING
USR
}
# hierarchies {
std_1c20:inst|custominstruction2_cpu:the_custominstruction2_cpu
}
# end
# entity
addroundkey
# storage
db|standard.(82).cnf
db|standard.(82).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
addroundkey.vhd
895e67d285d818e3c1cf3eb0625866
4
# internal_option {
AUTO_RESOURCE_SHARING
OFF
}
# user_parameter {
 constraint(dataa)
31 downto 0
PARAMETER_STRING
USR
 constraint(datab)
31 downto 0
PARAMETER_STRING
USR
 constraint(result)
31 downto 0
PARAMETER_STRING
USR
}
# hierarchies {
std_1c20:inst|custominstruction2_cpu:the_custominstruction2_cpu|addroundkey:the_addroundkey
}
# end
# entity
custominstruction3_cpu_s1_arbitrator
# storage
db|standard.(83).cnf
db|standard.(83).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
std_1c20.vhd
67356db08fbff5d04aed26fe53d6daae
4
# internal_option {
AUTO_RESOURCE_SHARING
OFF
}
# user_parameter {
 constraint(cpu_custom_instruction_master_combo_dataa)
31 downto 0
PARAMETER_STRING
USR
 constraint(custominstruction3_cpu_s1_result)
31 downto 0
PARAMETER_STRING
USR
 constraint(custominstruction3_cpu_s1_dataa)
31 downto 0
PARAMETER_STRING
USR
 constraint(custominstruction3_cpu_s1_result_from_sa)
31 downto 0
PARAMETER_STRING
USR
}
# hierarchies {
std_1c20:inst|custominstruction3_cpu_s1_arbitrator:the_custominstruction3_cpu_s1
}
# end
# entity
custominstruction3_cpu
# storage
db|standard.(84).cnf
db|standard.(84).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
custominstruction3_cpu.vhd
75e11b91eb419662dbd5d3ac5987fde0
4
# internal_option {
AUTO_RESOURCE_SHARING
OFF
}
# user_parameter {
 constraint(dataa)
31 downto 0
PARAMETER_STRING
USR
 constraint(result)
31 downto 0
PARAMETER_STRING
USR
}
# hierarchies {
std_1c20:inst|custominstruction3_cpu:the_custominstruction3_cpu
}
# end
# entity
custominstruction_cpu_s1_arbitrator
# storage
db|standard.(95).cnf
db|standard.(95).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
std_1c20.vhd
67356db08fbff5d04aed26fe53d6daae
4
# internal_option {
AUTO_RESOURCE_SHARING
OFF
}
# user_parameter {
 constraint(cpu_custom_instruction_master_combo_dataa)
31 downto 0
PARAMETER_STRING
USR
 constraint(cpu_custom_instruction_master_combo_datab)
31 downto 0
PARAMETER_STRING
USR
 constraint(custominstruction_cpu_s1_result)
31 downto 0
PARAMETER_STRING
USR
 constraint(custominstruction_cpu_s1_dataa)
31 downto 0
PARAMETER_STRING
USR
 constraint(custominstruction_cpu_s1_datab)
31 downto 0
PARAMETER_STRING
USR
 constraint(custominstruction_cpu_s1_result_from_sa)
31 downto 0
PARAMETER_STRING
USR
}
# hierarchies {
std_1c20:inst|custominstruction_cpu_s1_arbitrator:the_custominstruction_cpu_s1
}
# end
# entity
custominstruction_cpu
# storage
db|standard.(97).cnf
db|standard.(97).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
custominstruction_cpu.vhd
59dc5e6458aee5f6e2e06ed73c8eb9d
4
# internal_option {
AUTO_RESOURCE_SHARING
OFF
}
# user_parameter {
 constraint(dataa)
31 downto 0
PARAMETER_STRING
USR
 constraint(datab)
31 downto 0
PARAMETER_STRING
USR
 constraint(result)
31 downto 0
PARAMETER_STRING
USR
}
# hierarchies {
std_1c20:inst|custominstruction_cpu:the_custominstruction_cpu
}
# end
# entity
xor32
# storage
db|standard.(99).cnf
db|standard.(99).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
xor32.vhd
aeb6d66eed60f4d7b176af33779cc5e4
4
# internal_option {
AUTO_RESOURCE_SHARING
OFF
}
# user_parameter {
 constraint(dataa)
31 downto 0
PARAMETER_STRING
USR
 constraint(datab)
31 downto 0
PARAMETER_STRING
USR
 constraint(result)
31 downto 0
PARAMETER_STRING
USR
}
# hierarchies {
std_1c20:inst|custominstruction_cpu:the_custominstruction_cpu|xor32:the_xor32
}
# end
# entity
epcs_controller_epcs_control_port_arbitrator
# storage
db|standard.(101).cnf
db|standard.(101).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
std_1c20.vhd
67356db08fbff5d04aed26fe53d6daae
4
# internal_option {
AUTO_RESOURCE_SHARING
OFF
}
# user_parameter {
 constraint(cpu_data_master_address_to_slave)
25 downto 0
PARAMETER_STRING
USR
 constraint(cpu_data_master_writedata)
31 downto 0
PARAMETER_STRING
USR
 constraint(cpu_instruction_master_address_to_slave)
25 downto 0
PARAMETER_STRING
USR
 constraint(cpu_instruction_master_latency_counter)
1 downto 0
PARAMETER_STRING
USR
 constraint(epcs_controller_epcs_control_port_readdata)
31 downto 0
PARAMETER_STRING
USR
 constraint(epcs_controller_epcs_control_port_address)
8 downto 0
PARAMETER_STRING
USR
 constraint(epcs_controller_epcs_control_port_readdata_from_sa)
31 downto 0
PARAMETER_STRING
USR
 constraint(epcs_controller_epcs_control_port_writedata)
31 downto 0
PARAMETER_STRING
USR
}
# hierarchies {
std_1c20:inst|epcs_controller_epcs_control_port_arbitrator:the_epcs_controller_epcs_control_port
}
# end
# entity
epcs_controller
# storage
db|standard.(102).cnf
db|standard.(102).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
epcs_controller.vhd
1d9fa2375cee578634d6e1dd4a804286
4
# internal_option {
AUTO_RESOURCE_SHARING
OFF
}
# user_parameter {
 constraint(address)
8 downto 0
PARAMETER_STRING
USR
 constraint(writedata)
31 downto 0
PARAMETER_STRING
USR
 constraint(readdata)
31 downto 0
PARAMETER_STRING
USR
}
# hierarchies {
std_1c20:inst|epcs_controller:the_epcs_controller
}
# end
# entity
epcs_controller_sub
# storage
db|standard.(103).cnf
db|standard.(103).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
epcs_controller.vhd
1d9fa2375cee578634d6e1dd4a804286
4
# internal_option {
AUTO_RESOURCE_SHARING
OFF
}
# user_parameter {
 constraint(data_from_cpu)
15 downto 0
PARAMETER_STRING
USR
 constraint(mem_addr)
2 downto 0
PARAMETER_STRING
USR
 constraint(data_to_cpu)
15 downto 0
PARAMETER_STRING
USR
}
# hierarchies {
std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub
}
# end
# entity
tornado_epcs_controller_atom
# storage
db|standard.(106).cnf
db|standard.(106).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
epcs_controller.vhd
1d9fa2375cee578634d6e1dd4a804286
4
# internal_option {
AUTO_RESOURCE_SHARING
OFF
}
# hierarchies {
std_1c20:inst|epcs_controller:the_epcs_controller|tornado_epcs_controller_atom:the_tornado_epcs_controller_atom
}
# end
# entity
ext_ram_bus_avalon_slave_arbitrator
# storage
db|standard.(110).cnf
db|standard.(110).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
std_1c20.vhd
67356db08fbff5d04aed26fe53d6daae
4
# internal_option {
AUTO_RESOURCE_SHARING
OFF
}
# user_parameter {
 constraint(cpu_data_master_address_to_slave)
25 downto 0
PARAMETER_STRING
USR
 constraint(cpu_data_master_byteenable)
3 downto 0
PARAMETER_STRING
USR
 constraint(cpu_data_master_dbs_address)
1 downto 0
PARAMETER_STRING
USR
 constraint(cpu_data_master_dbs_write_8)
7 downto 0
PARAMETER_STRING
USR
 constraint(cpu_data_master_writedata)
31 downto 0
PARAMETER_STRING
USR
 constraint(cpu_instruction_master_address_to_slave)
25 downto 0
PARAMETER_STRING
USR
 constraint(cpu_instruction_master_dbs_address)
1 downto 0
PARAMETER_STRING
USR
 constraint(cpu_instruction_master_latency_counter)
1 downto 0
PARAMETER_STRING
USR
 constraint(be_n_to_the_ext_ram)
3 downto 0
PARAMETER_STRING
USR
 constraint(byteenablen_to_the_lan91c111)
3 downto 0
PARAMETER_STRING
USR
 constraint(ext_ram_bus_address)
22 downto 0
PARAMETER_STRING
USR
 constraint(ext_ram_bus_data)
31 downto 0
PARAMETER_STRING
USR
 constraint(incoming_ext_ram_bus_data)
31 downto 0
PARAMETER_STRING
USR
 constraint(incoming_ext_ram_bus_data_with_xs_converted_to_0)
7 downto 0
PARAMETER_STRING
USR
}
# hierarchies {
std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave
}
# end
# entity
high_res_timer_s1_arbitrator
# storage
db|standard.(112).cnf
db|standard.(112).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
std_1c20.vhd
67356db08fbff5d04aed26fe53d6daae
4
# internal_option {
AUTO_RESOURCE_SHARING
OFF
}
# user_parameter {
 constraint(cpu_data_master_address_to_slave)
25 downto 0
PARAMETER_STRING
USR
 constraint(cpu_data_master_writedata)
31 downto 0
PARAMETER_STRING
USR
 constraint(high_res_timer_s1_readdata)
15 downto 0
PARAMETER_STRING
USR
 constraint(high_res_timer_s1_address)
2 downto 0
PARAMETER_STRING
USR
 constraint(high_res_timer_s1_readdata_from_sa)
15 downto 0
PARAMETER_STRING
USR
 constraint(high_res_timer_s1_writedata)
15 downto 0
PARAMETER_STRING
USR
}
# hierarchies {
std_1c20:inst|high_res_timer_s1_arbitrator:the_high_res_timer_s1
}
# end
# entity
jtag_uart_avalon_jtag_slave_arbitrator
# storage
db|standard.(114).cnf
db|standard.(114).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
std_1c20.vhd
67356db08fbff5d04aed26fe53d6daae
4
# internal_option {
AUTO_RESOURCE_SHARING
OFF
}
# user_parameter {
 constraint(cpu_data_master_address_to_slave)
25 downto 0
PARAMETER_STRING
USR
 constraint(cpu_data_master_writedata)
31 downto 0
PARAMETER_STRING
USR
 constraint(jtag_uart_avalon_jtag_slave_readdata)
31 downto 0
PARAMETER_STRING
USR
 constraint(jtag_uart_avalon_jtag_slave_readdata_from_sa)
31 downto 0
PARAMETER_STRING
USR
 constraint(jtag_uart_avalon_jtag_slave_writedata)
31 downto 0
PARAMETER_STRING
USR
}
# hierarchies {
std_1c20:inst|jtag_uart_avalon_jtag_slave_arbitrator:the_jtag_uart_avalon_jtag_slave
}
# end
# entity
jtag_uart
# storage
db|standard.(115).cnf
db|standard.(115).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
jtag_uart.vhd
bcbc375561fa5a926297b129185ef36
4
# internal_option {
AUTO_RESOURCE_SHARING
OFF
}
# user_parameter {
 constraint(av_writedata)
31 downto 0
PARAMETER_STRING
USR
 constraint(av_readdata)
31 downto 0
PARAMETER_STRING
USR
}
# hierarchies {
std_1c20:inst|jtag_uart:the_jtag_uart
}
# end
# entity
jtag_uart_scfifo_w
# storage
db|standard.(116).cnf
db|standard.(116).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
jtag_uart.vhd
bcbc375561fa5a926297b129185ef36
4
# internal_option {
AUTO_RESOURCE_SHARING
OFF
}
# user_parameter {
 constraint(fifo_wdata)
7 downto 0
PARAMETER_STRING
USR
 constraint(r_dat)
7 downto 0
PARAMETER_STRING
USR
 constraint(wfifo_used)
5 downto 0
PARAMETER_STRING
USR
}
# hierarchies {
std_1c20:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_w:the_jtag_uart_scfifo_w
}
# end
# entity
jtag_uart_scfifo_r
# storage
db|standard.(117).cnf
db|standard.(117).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
jtag_uart.vhd
bcbc375561fa5a926297b129185ef36
4
# internal_option {
AUTO_RESOURCE_SHARING
OFF
}
# user_parameter {
 constraint(t_dat)
7 downto 0
PARAMETER_STRING
USR
 constraint(fifo_rdata)
7 downto 0
PARAMETER_STRING
USR
 constraint(rfifo_used)
5 downto 0
PARAMETER_STRING
USR
}
# hierarchies {
std_1c20:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_r:the_jtag_uart_scfifo_r
}
# end
# entity
lcd_display_control_slave_arbitrator
# storage
db|standard.(118).cnf
db|standard.(118).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
std_1c20.vhd
67356db08fbff5d04aed26fe53d6daae
4
# internal_option {
AUTO_RESOURCE_SHARING
OFF
}
# user_parameter {
 constraint(cpu_data_master_address_to_slave)
25 downto 0
PARAMETER_STRING
USR
 constraint(cpu_data_master_byteenable)
3 downto 0
PARAMETER_STRING
USR
 constraint(cpu_data_master_writedata)
31 downto 0
PARAMETER_STRING
USR
 constraint(lcd_display_control_slave_readdata)
7 downto 0
PARAMETER_STRING
USR
 constraint(lcd_display_control_slave_address)
1 downto 0
PARAMETER_STRING
USR
 constraint(lcd_display_control_slave_readdata_from_sa)
7 downto 0
PARAMETER_STRING
USR
 constraint(lcd_display_control_slave_writedata)
7 downto 0
PARAMETER_STRING
USR
}
# hierarchies {
std_1c20:inst|lcd_display_control_slave_arbitrator:the_lcd_display_control_slave
}
# end
# entity
led_pio_s1_arbitrator
# storage
db|standard.(119).cnf
db|standard.(119).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
std_1c20.vhd
67356db08fbff5d04aed26fe53d6daae
4
# internal_option {
AUTO_RESOURCE_SHARING
OFF
}
# user_parameter {
 constraint(cpu_data_master_address_to_slave)
25 downto 0
PARAMETER_STRING
USR
 constraint(cpu_data_master_byteenable)
3 downto 0
PARAMETER_STRING
USR
 constraint(cpu_data_master_writedata)
31 downto 0
PARAMETER_STRING
USR
 constraint(led_pio_s1_address)
1 downto 0
PARAMETER_STRING
USR
 constraint(led_pio_s1_writedata)
7 downto 0
PARAMETER_STRING
USR
}
# hierarchies {
std_1c20:inst|led_pio_s1_arbitrator:the_led_pio_s1
}
# end
# entity
reconfig_request_pio_s1_arbitrator
# storage
db|standard.(120).cnf
db|standard.(120).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
std_1c20.vhd
67356db08fbff5d04aed26fe53d6daae
4
# internal_option {
AUTO_RESOURCE_SHARING
OFF
}
# user_parameter {
 constraint(cpu_data_master_address_to_slave)
25 downto 0
PARAMETER_STRING
USR
 constraint(cpu_data_master_writedata)
31 downto 0
PARAMETER_STRING
USR
 constraint(reconfig_request_pio_s1_address)
1 downto 0
PARAMETER_STRING
USR
}
# hierarchies {
std_1c20:inst|reconfig_request_pio_s1_arbitrator:the_reconfig_request_pio_s1
}
# end
# entity
sdram_s1_arbitrator
# storage
db|standard.(121).cnf
db|standard.(121).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
std_1c20.vhd
67356db08fbff5d04aed26fe53d6daae
4
# internal_option {
AUTO_RESOURCE_SHARING
OFF
}
# user_parameter {
 constraint(cpu_data_master_address_to_slave)
25 downto 0
PARAMETER_STRING
USR
 constraint(cpu_data_master_byteenable)
3 downto 0
PARAMETER_STRING
USR
 constraint(cpu_data_master_writedata)
31 downto 0
PARAMETER_STRING
USR
 constraint(cpu_instruction_master_address_to_slave)
25 downto 0
PARAMETER_STRING
USR
 constraint(cpu_instruction_master_latency_counter)
1 downto 0
PARAMETER_STRING
USR
 constraint(sdram_s1_readdata)
31 downto 0
PARAMETER_STRING
USR
 constraint(sdram_s1_address)
21 downto 0
PARAMETER_STRING
USR
 constraint(sdram_s1_byteenable_n)
3 downto 0
PARAMETER_STRING
USR
 constraint(sdram_s1_readdata_from_sa)
31 downto 0
PARAMETER_STRING
USR
 constraint(sdram_s1_writedata)
31 downto 0
PARAMETER_STRING
USR
}
# hierarchies {
std_1c20:inst|sdram_s1_arbitrator:the_sdram_s1
}
# end
# entity
rdv_fifo_for_cpu_data_master_to_sdram_s1_module
# storage
db|standard.(122).cnf
db|standard.(122).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
std_1c20.vhd
67356db08fbff5d04aed26fe53d6daae
4
# internal_option {
AUTO_RESOURCE_SHARING
OFF
}
# hierarchies {
std_1c20:inst|sdram_s1_arbitrator:the_sdram_s1|rdv_fifo_for_cpu_data_master_to_sdram_s1_module:rdv_fifo_for_cpu_data_master_to_sdram_s1
}
# end
# entity
rdv_fifo_for_cpu_instruction_master_to_sdram_s1_module
# storage
db|standard.(123).cnf
db|standard.(123).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
std_1c20.vhd
67356db08fbff5d04aed26fe53d6daae
4
# internal_option {
AUTO_RESOURCE_SHARING
OFF
}
# hierarchies {
std_1c20:inst|sdram_s1_arbitrator:the_sdram_s1|rdv_fifo_for_cpu_instruction_master_to_sdram_s1_module:rdv_fifo_for_cpu_instruction_master_to_sdram_s1
}
# end
# entity
sdram_pll_s1_arbitrator
# storage
db|standard.(124).cnf
db|standard.(124).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
std_1c20.vhd
67356db08fbff5d04aed26fe53d6daae
4
# internal_option {
AUTO_RESOURCE_SHARING
OFF
}
# user_parameter {
 constraint(clock_0_out_address_to_slave)
3 downto 0
PARAMETER_STRING
USR
 constraint(clock_0_out_nativeaddress)
2 downto 0
PARAMETER_STRING
USR
 constraint(clock_0_out_writedata)
15 downto 0
PARAMETER_STRING
USR
 constraint(sdram_pll_s1_readdata)
15 downto 0
PARAMETER_STRING
USR
 constraint(sdram_pll_s1_address)
2 downto 0
PARAMETER_STRING
USR
 constraint(sdram_pll_s1_readdata_from_sa)
15 downto 0
PARAMETER_STRING
USR
 constraint(sdram_pll_s1_writedata)
15 downto 0
PARAMETER_STRING
USR
}
# hierarchies {
std_1c20:inst|sdram_pll_s1_arbitrator:the_sdram_pll_s1
}
# end
# entity
seven_seg_pio_s1_arbitrator
# storage
db|standard.(137).cnf
db|standard.(137).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
std_1c20.vhd
67356db08fbff5d04aed26fe53d6daae
4
# internal_option {
AUTO_RESOURCE_SHARING
OFF
}
# user_parameter {
 constraint(cpu_data_master_address_to_slave)
25 downto 0
PARAMETER_STRING
USR
 constraint(cpu_data_master_writedata)
31 downto 0
PARAMETER_STRING
USR
 constraint(seven_seg_pio_s1_address)
1 downto 0
PARAMETER_STRING
USR
 constraint(seven_seg_pio_s1_writedata)
15 downto 0
PARAMETER_STRING
USR
}
# hierarchies {
std_1c20:inst|seven_seg_pio_s1_arbitrator:the_seven_seg_pio_s1
}
# end
# entity
sys_clk_timer_s1_arbitrator
# storage
db|standard.(138).cnf
db|standard.(138).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
std_1c20.vhd
67356db08fbff5d04aed26fe53d6daae
4
# internal_option {
AUTO_RESOURCE_SHARING
OFF
}
# user_parameter {
 constraint(cpu_data_master_address_to_slave)
25 downto 0
PARAMETER_STRING
USR
 constraint(cpu_data_master_writedata)
31 downto 0
PARAMETER_STRING
USR
 constraint(sys_clk_timer_s1_readdata)
15 downto 0
PARAMETER_STRING
USR
 constraint(sys_clk_timer_s1_address)
2 downto 0
PARAMETER_STRING
USR
 constraint(sys_clk_timer_s1_readdata_from_sa)
15 downto 0
PARAMETER_STRING
USR
 constraint(sys_clk_timer_s1_writedata)
15 downto 0
PARAMETER_STRING
USR
}
# hierarchies {
std_1c20:inst|sys_clk_timer_s1_arbitrator:the_sys_clk_timer_s1
}
# end
# entity
sysid_control_slave_arbitrator
# storage
db|standard.(139).cnf
db|standard.(139).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
std_1c20.vhd
67356db08fbff5d04aed26fe53d6daae
4
# internal_option {
AUTO_RESOURCE_SHARING
OFF
}
# user_parameter {
 constraint(cpu_data_master_address_to_slave)
25 downto 0
PARAMETER_STRING
USR
 constraint(sysid_control_slave_readdata)
31 downto 0
PARAMETER_STRING
USR
 constraint(sysid_control_slave_readdata_from_sa)
31 downto 0
PARAMETER_STRING
USR
}
# hierarchies {
std_1c20:inst|sysid_control_slave_arbitrator:the_sysid_control_slave
}
# end
# entity
uart1_s1_arbitrator
# storage
db|standard.(141).cnf
db|standard.(141).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
std_1c20.vhd
67356db08fbff5d04aed26fe53d6daae
4
# internal_option {
AUTO_RESOURCE_SHARING
OFF
}
# user_parameter {
 constraint(cpu_data_master_address_to_slave)
25 downto 0
PARAMETER_STRING
USR
 constraint(cpu_data_master_writedata)
31 downto 0
PARAMETER_STRING
USR
 constraint(uart1_s1_readdata)
15 downto 0
PARAMETER_STRING
USR
 constraint(uart1_s1_address)
2 downto 0
PARAMETER_STRING
USR
 constraint(uart1_s1_readdata_from_sa)
15 downto 0
PARAMETER_STRING
USR
 constraint(uart1_s1_writedata)
15 downto 0
PARAMETER_STRING
USR
}
# hierarchies {
std_1c20:inst|uart1_s1_arbitrator:the_uart1_s1
}
# end
# entity
uart1
# storage
db|standard.(142).cnf
db|standard.(142).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
uart1.vhd
b20eee1d136eb2672bb582ea422d728
4
# internal_option {
AUTO_RESOURCE_SHARING
OFF
}
# user_parameter {
 constraint(address)
2 downto 0
PARAMETER_STRING
USR
 constraint(writedata)
15 downto 0
PARAMETER_STRING
USR
 constraint(readdata)
15 downto 0
PARAMETER_STRING
USR
}
# hierarchies {
std_1c20:inst|uart1:the_uart1
}
# end
# entity
uart1_tx
# storage
db|standard.(143).cnf
db|standard.(143).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
uart1.vhd
b20eee1d136eb2672bb582ea422d728
4
# internal_option {
AUTO_RESOURCE_SHARING
OFF
}
# user_parameter {
 constraint(baud_divisor)
8 downto 0
PARAMETER_STRING
USR
 constraint(tx_data)
7 downto 0
PARAMETER_STRING
USR
}
# hierarchies {
std_1c20:inst|uart1:the_uart1|uart1_tx:the_uart1_tx
}
# end
# entity
uart1_rx
# storage
db|standard.(144).cnf
db|standard.(144).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
uart1.vhd
b20eee1d136eb2672bb582ea422d728
4
# internal_option {
AUTO_RESOURCE_SHARING
OFF
}
# user_parameter {
 constraint(baud_divisor)
8 downto 0
PARAMETER_STRING
USR
 constraint(rx_data)
7 downto 0
PARAMETER_STRING
USR
}
# hierarchies {
std_1c20:inst|uart1:the_uart1|uart1_rx:the_uart1_rx
}
# end
# entity
uart1_rx_stimulus_source
# storage
db|standard.(145).cnf
db|standard.(145).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
uart1.vhd
b20eee1d136eb2672bb582ea422d728
4
# internal_option {
AUTO_RESOURCE_SHARING
OFF
}
# user_parameter {
 constraint(baud_divisor)
8 downto 0
PARAMETER_STRING
USR
}
# hierarchies {
std_1c20:inst|uart1:the_uart1|uart1_rx:the_uart1_rx|uart1_rx_stimulus_source:the_uart1_rx_stimulus_source
}
# end
# entity
uart1_regs
# storage
db|standard.(146).cnf
db|standard.(146).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
uart1.vhd
b20eee1d136eb2672bb582ea422d728
4
# internal_option {
AUTO_RESOURCE_SHARING
OFF
}
# user_parameter {
 constraint(address)
2 downto 0
PARAMETER_STRING
USR
 constraint(rx_data)
7 downto 0
PARAMETER_STRING
USR
 constraint(writedata)
15 downto 0
PARAMETER_STRING
USR
 constraint(baud_divisor)
8 downto 0
PARAMETER_STRING
USR
 constraint(readdata)
15 downto 0
PARAMETER_STRING
USR
 constraint(tx_data)
7 downto 0
PARAMETER_STRING
USR
}
# hierarchies {
std_1c20:inst|uart1:the_uart1|uart1_regs:the_uart1_regs
}
# end
# entity
std_1c20_reset_sysclk2_domain_synch_module
# storage
db|standard.(147).cnf
db|standard.(147).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
std_1c20.vhd
67356db08fbff5d04aed26fe53d6daae
4
# internal_option {
AUTO_RESOURCE_SHARING
OFF
}
# hierarchies {
std_1c20:inst|std_1c20_reset_sysclk2_domain_synch_module:std_1c20_reset_sysclk2_domain_synch
}
# end
# entity
std_1c20_reset_PLD_CLOCKINPUT_domain_synch_module
# storage
db|standard.(148).cnf
db|standard.(148).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
std_1c20.vhd
67356db08fbff5d04aed26fe53d6daae
4
# internal_option {
AUTO_RESOURCE_SHARING
OFF
}
# hierarchies {
std_1c20:inst|std_1c20_reset_PLD_CLOCKINPUT_domain_synch_module:std_1c20_reset_PLD_CLOCKINPUT_domain_synch
}
# end
# entity
std_1c20_reset_PLD_CLKFB_domain_synch_module
# storage
db|standard.(149).cnf
db|standard.(149).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
std_1c20.vhd
67356db08fbff5d04aed26fe53d6daae
4
# internal_option {
AUTO_RESOURCE_SHARING
OFF
}
# hierarchies {
std_1c20:inst|std_1c20_reset_PLD_CLKFB_domain_synch_module:std_1c20_reset_PLD_CLKFB_domain_synch
}
# end
# entity
altsyncram_bp62
# storage
db|standard.(53).cnf
db|standard.(53).cnf
# case_insensitive
# source_file
db|altsyncram_bp62.tdf
b484d3982642b81674a1667823e9ebab
6
# user_parameter {
PORT_A_ADDRESS_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_A_BYTE_ENABLE_MASK_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_A_DATA_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_B_ADDRESS_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_B_BYTE_ENABLE_MASK_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_B_DATA_WIDTH
1
PARAMETER_UNKNOWN
DEF
}
# used_port {
wren_b
-1
3
wren_a
-1
3
q_b9
-1
3
q_b8
-1
3
q_b7
-1
3
q_b6
-1
3
q_b5
-1
3
q_b4
-1
3
q_b31
-1
3
q_b30
-1
3
q_b3
-1
3
q_b29
-1
3
q_b28
-1
3
q_b27
-1
3
q_b26
-1
3
q_b25
-1
3
q_b24
-1
3
q_b23
-1
3
q_b22
-1
3
q_b21
-1
3
q_b20
-1
3
q_b2
-1
3
q_b19
-1
3
q_b18
-1
3
q_b17
-1
3
q_b16
-1
3
q_b15
-1
3
q_b14
-1
3
q_b13
-1
3
q_b12
-1
3
q_b11
-1
3
q_b10
-1
3
q_b1
-1
3
q_b0
-1
3
q_a9
-1
3
q_a8
-1
3
q_a7
-1
3
q_a6
-1
3
q_a5
-1
3
q_a4
-1
3
q_a31
-1
3
q_a30
-1
3
q_a3
-1
3
q_a29
-1
3
q_a28
-1
3
q_a27
-1
3
q_a26
-1
3
q_a25
-1
3
q_a24
-1
3
q_a23
-1
3
q_a22
-1
3
q_a21
-1
3
q_a20
-1
3
q_a2
-1
3
q_a19
-1
3
q_a18
-1
3
q_a17
-1
3
q_a16
-1
3
q_a15
-1
3
q_a14
-1
3
q_a13
-1
3
q_a12
-1
3
q_a11
-1
3
q_a10
-1
3
q_a1
-1
3
q_a0
-1
3
data_b9
-1
3
data_b8
-1
3
data_b7
-1
3
data_b6
-1
3
data_b5
-1
3
data_b4
-1
3
data_b31
-1
3
data_b30
-1
3
data_b3
-1
3
data_b29
-1
3
data_b28
-1
3
data_b27
-1
3
data_b26
-1
3
data_b25
-1
3
data_b24
-1
3
data_b23
-1
3
data_b22
-1
3
data_b21
-1
3
data_b20
-1
3
data_b2
-1
3
data_b19
-1
3
data_b18
-1
3
data_b17
-1
3
data_b16
-1
3
data_b15
-1
3
data_b14
-1
3
data_b13
-1
3
data_b12
-1
3
data_b11
-1
3
data_b10
-1
3
data_b1
-1
3
data_b0
-1
3
data_a9
-1
3
data_a8
-1
3
data_a7
-1
3
data_a6
-1
3
data_a5
-1
3
data_a4
-1
3
data_a31
-1
3
data_a30
-1
3
data_a3
-1
3
data_a29
-1
3
data_a28
-1
3
data_a27
-1
3
data_a26
-1
3
data_a25
-1
3
data_a24
-1
3
data_a23
-1
3
data_a22
-1
3
data_a21
-1
3
data_a20
-1
3
data_a2
-1
3
data_a19
-1
3
data_a18
-1
3
data_a17
-1
3
data_a16
-1
3
data_a15
-1
3
data_a14
-1
3
data_a13
-1
3
data_a12
-1
3
data_a11
-1
3
data_a10
-1
3
data_a1
-1
3
data_a0
-1
3
clocken1
-1
3
clocken0
-1
3
clock1
-1
3
clock0
-1
3
byteena_a3
-1
3
byteena_a2
-1
3
byteena_a1
-1
3
byteena_a0
-1
3
address_b7
-1
3
address_b6
-1
3
address_b5
-1
3
address_b4
-1
3
address_b3
-1
3
address_b2
-1
3
address_b1
-1
3
address_b0
-1
3
address_a7
-1
3
address_a6
-1
3
address_a5
-1
3
address_a4
-1
3
address_a3
-1
3
address_a2
-1
3
address_a1
-1
3
address_a0
-1
3
}
# memory_file {
cpu_ociram_default_contents.mif
afdfb73ac9fcb1f0c9b39dc3d771c8ba
}
# hierarchies {
std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|cpu_ociram_lpm_dram_bdp_component_module:cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_bp62:auto_generated
}
# end
# entity
mixcolumn
# storage
db|standard.(93).cnf
db|standard.(93).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
mixcolumn.vhd
5e923e4c109b974d830db71d6d6cd84
4
# internal_option {
AUTO_RESOURCE_SHARING
OFF
}
# user_parameter {
 constraint(dataa)
31 downto 0
PARAMETER_STRING
USR
 constraint(result)
31 downto 0
PARAMETER_STRING
USR
}
# hierarchies {
std_1c20:inst|custominstruction3_cpu:the_custominstruction3_cpu|mixcolumn:the_mixcolumn
}
# end
# entity
sysid
# storage
db|standard.(140).cnf
db|standard.(140).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
sysid.vhd
a242a5b6af0c5a9bd9dce15394a2a8b
4
# internal_option {
AUTO_RESOURCE_SHARING
OFF
}
# user_parameter {
 constraint(readdata)
31 downto 0
PARAMETER_STRING
USR
}
# hierarchies {
std_1c20:inst|sysid:the_sysid
}
# end
# complete

