/* system.h
 *
 * Machine generated for a CPU named "cpu" as defined in:
 * D:\ALTERA\examples\vhdl\niosII_cyclone_1c20\standard\software\blank_project_0_syslib\..\..\std_1c20.ptf
 *
 * Generated: 2011-09-23 15:48:17.89
 *
 */

#ifndef __SYSTEM_H_
#define __SYSTEM_H_

/*

DO NOT MODIFY THIS FILE

   Changing this file will have subtle consequences
   which will almost certainly lead to a nonfunctioning
   system. If you do modify this file, be aware that your
   changes will be overwritten and lost when this file
   is generated again.

DO NOT MODIFY THIS FILE

*/

/******************************************************************************
*                                                                             *
* License Agreement                                                           *
*                                                                             *
* Copyright (c) 2003 Altera Corporation, San Jose, California, USA.           *
* All rights reserved.                                                        *
*                                                                             *
* Permission is hereby granted, free of charge, to any person obtaining a     *
* copy of this software and associated documentation files (the "Software"),  *
* to deal in the Software without restriction, including without limitation   *
* the rights to use, copy, modify, merge, publish, distribute, sublicense,    *
* and/or sell copies of the Software, and to permit persons to whom the       *
* Software is furnished to do so, subject to the following conditions:        *
*                                                                             *
* The above copyright notice and this permission notice shall be included in  *
* all copies or substantial portions of the Software.                         *
*                                                                             *
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR  *
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,    *
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE *
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER      *
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING     *
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER         *
* DEALINGS IN THE SOFTWARE.                                                   *
*                                                                             *
* This agreement shall be governed in all respects by the laws of the State   *
* of California and by the laws of the United States of America.              *
*                                                                             *
******************************************************************************/

/*
 * system configuration
 *
 */

#define ALT_SYSTEM_NAME "std_1c20"
#define ALT_CPU_NAME "cpu"
#define ALT_CPU_ARCHITECTURE "altera_nios2"
#define ALT_DEVICE_FAMILY "CYCLONE"
#define ALTERA_NIOS_DEV_BOARD_CYCLONE_1C20
#define ALT_STDIN "/dev/jtag_uart"
#define ALT_STDIN_TYPE "altera_avalon_jtag_uart"
#define ALT_STDIN_BASE 0x021208B0
#define ALT_STDOUT "/dev/jtag_uart"
#define ALT_STDOUT_TYPE "altera_avalon_jtag_uart"
#define ALT_STDOUT_BASE 0x021208B0
#define ALT_STDERR "/dev/jtag_uart"
#define ALT_STDERR_TYPE "altera_avalon_jtag_uart"
#define ALT_STDERR_BASE 0x021208B0
#define ALT_CPU_FREQ 50000000
#define ALT_IRQ_BASE NULL

/*
 * processor configuration
 *
 */

#define NIOS2_CPU_IMPLEMENTATION "small"
#define NIOS2_BIG_ENDIAN 0

#define NIOS2_ICACHE_SIZE 4096
#define NIOS2_DCACHE_SIZE 0
#define NIOS2_ICACHE_LINE_SIZE 32
#define NIOS2_ICACHE_LINE_SIZE_LOG2 5
#define NIOS2_DCACHE_LINE_SIZE 0
#define NIOS2_DCACHE_LINE_SIZE_LOG2 0
#define NIOS2_FLUSHDA_SUPPORTED

#define NIOS2_EXCEPTION_ADDR 0x01000020
#define NIOS2_RESET_ADDR 0x00000000
#define NIOS2_BREAK_ADDR 0x02120020

#define NIOS2_HAS_DEBUG_STUB

#define NIOS2_CPU_ID_SIZE 1
#define NIOS2_CPU_ID_VALUE 0

/*
 * A define for each class of peripheral
 *
 */

#define __ALTERA_AVALON_TRI_STATE_BRIDGE
#define __ALTERA_AVALON_CFI_FLASH
#define __ALTERA_NIOS_DEV_KIT_STRATIX_EDITION_SRAM2
#define __ALTERA_AVALON_EPCS_FLASH_CONTROLLER
#define __ALTERA_AVALON_LAN91C111
#define __ALTERA_AVALON_TIMER
#define __ALTERA_AVALON_JTAG_UART
#define __ALTERA_AVALON_PIO
#define __ALTERA_AVALON_LCD_16207
#define __ALTERA_AVALON_UART
#define __ALTERA_AVALON_SYSID
#define __ALTERA_AVALON_NEW_SDRAM_CONTROLLER
#define __ALTERA_AVALON_PLL

/*
 * ext_ram_bus configuration
 *
 */

#define EXT_RAM_BUS_NAME "/dev/ext_ram_bus"
#define EXT_RAM_BUS_TYPE "altera_avalon_tri_state_bridge"

/*
 * ext_flash configuration
 *
 */

#define EXT_FLASH_NAME "/dev/ext_flash"
#define EXT_FLASH_TYPE "altera_avalon_cfi_flash"
#define EXT_FLASH_BASE 0x00000000
#define EXT_FLASH_SPAN 8388608
#define EXT_FLASH_SETUP_VALUE 40
#define EXT_FLASH_WAIT_VALUE 160
#define EXT_FLASH_HOLD_VALUE 40
#define EXT_FLASH_TIMING_UNITS "ns"
#define EXT_FLASH_UNIT_MULTIPLIER 1
#define EXT_FLASH_SIZE 8388608
#define EXT_FLASH_CONTENTS_INFO "SIMDIR/ext_flash.dat 1124853268"

/*
 * ext_ram configuration
 *
 */

#define EXT_RAM_NAME "/dev/ext_ram"
#define EXT_RAM_TYPE "altera_nios_dev_kit_stratix_edition_sram2"
#define EXT_RAM_BASE 0x02000000
#define EXT_RAM_SPAN 1048576
#define EXT_RAM_SRAM_MEMORY_SIZE 1024
#define EXT_RAM_SRAM_MEMORY_UNITS 1024
#define EXT_RAM_SRAM_DATA_WIDTH 32
#define EXT_RAM_CONTENTS_INFO "SIMDIR/ext_ram_lane0.dat 1124853270 SIMDIR/ext_ram_lane3.dat 1124853270 SIMDIR/ext_ram_lane2.dat 1124853270 SIMDIR/ext_ram.dat 1124853270 SIMDIR/ext_ram_lane1.dat 1124853270"

/*
 * epcs_controller configuration
 *
 */

#define EPCS_CONTROLLER_NAME "/dev/epcs_controller"
#define EPCS_CONTROLLER_TYPE "altera_avalon_epcs_flash_controller"
#define EPCS_CONTROLLER_BASE 0x02100000
#define EPCS_CONTROLLER_SPAN 2048
#define EPCS_CONTROLLER_IRQ 5
#define EPCS_CONTROLLER_DATABITS 8
#define EPCS_CONTROLLER_TARGETCLOCK 20
#define EPCS_CONTROLLER_CLOCKUNITS "MHz"
#define EPCS_CONTROLLER_CLOCKMULT 1000000
#define EPCS_CONTROLLER_NUMSLAVES 1
#define EPCS_CONTROLLER_ISMASTER 1
#define EPCS_CONTROLLER_CLOCKPOLARITY 0
#define EPCS_CONTROLLER_CLOCKPHASE 0
#define EPCS_CONTROLLER_LSBFIRST 0
#define EPCS_CONTROLLER_EXTRADELAY 0
#define EPCS_CONTROLLER_TARGETSSDELAY 100
#define EPCS_CONTROLLER_DELAYUNITS "us"
#define EPCS_CONTROLLER_DELAYMULT "1e-06"
#define EPCS_CONTROLLER_PREFIX "epcs_"
#define EPCS_CONTROLLER_REGISTER_OFFSET 0x200
#define EPCS_CONTROLLER_CLOCKUNIT "kHz"
#define EPCS_CONTROLLER_CONTENTS_INFO "SIMDIR/epcs_controller_boot_rom.hex 1124853272 SIMDIR/epcs_controller_boot_rom.dat 1124853272"
#define EPCS_CONTROLLER_DELAYUNIT "us"

/*
 * lan91c111 configuration
 *
 */

#define LAN91C111_NAME "/dev/lan91c111"
#define LAN91C111_TYPE "altera_avalon_lan91c111"
#define LAN91C111_BASE 0x02110000
#define LAN91C111_SPAN 65536
#define LAN91C111_IRQ 6
#define LAN91C111_IS_ETHERNET_MAC 1
#define LAN91C111_LAN91C111_REGISTERS_OFFSET 0x0300
#define LAN91C111_LAN91C111_DATA_BUS_WIDTH 32

/*
 * sys_clk_timer configuration
 *
 */

#define SYS_CLK_TIMER_NAME "/dev/sys_clk_timer"
#define SYS_CLK_TIMER_TYPE "altera_avalon_timer"
#define SYS_CLK_TIMER_BASE 0x02120800
#define SYS_CLK_TIMER_SPAN 32
#define SYS_CLK_TIMER_IRQ 0
#define SYS_CLK_TIMER_ALWAYS_RUN 0
#define SYS_CLK_TIMER_FIXED_PERIOD 0
#define SYS_CLK_TIMER_SNAPSHOT 1
#define SYS_CLK_TIMER_PERIOD 10
#define SYS_CLK_TIMER_PERIOD_UNITS "ms"
#define SYS_CLK_TIMER_RESET_OUTPUT 0
#define SYS_CLK_TIMER_TIMEOUT_PULSE_OUTPUT 0
#define SYS_CLK_TIMER_MULT 0.001
#define SYS_CLK_TIMER_FREQ 50000000

/*
 * jtag_uart configuration
 *
 */

#define JTAG_UART_NAME "/dev/jtag_uart"
#define JTAG_UART_TYPE "altera_avalon_jtag_uart"
#define JTAG_UART_BASE 0x021208B0
#define JTAG_UART_SPAN 8
#define JTAG_UART_IRQ 1
#define JTAG_UART_WRITE_DEPTH 64
#define JTAG_UART_READ_DEPTH 64
#define JTAG_UART_WRITE_THRESHOLD 8
#define JTAG_UART_READ_THRESHOLD 8
#define JTAG_UART_READ_CHAR_STREAM ""
#define JTAG_UART_SHOWASCII 1
#define JTAG_UART_READ_LE 0
#define JTAG_UART_WRITE_LE 0
#define JTAG_UART_ALTERA_SHOW_UNRELEASED_JTAG_UART_FEATURES 0

/*
 * button_pio configuration
 *
 */

#define BUTTON_PIO_NAME "/dev/button_pio"
#define BUTTON_PIO_TYPE "altera_avalon_pio"
#define BUTTON_PIO_BASE 0x02120860
#define BUTTON_PIO_SPAN 16
#define BUTTON_PIO_IRQ 2
#define BUTTON_PIO_DO_TEST_BENCH_WIRING 1
#define BUTTON_PIO_DRIVEN_SIM_VALUE 0x000F
#define BUTTON_PIO_HAS_TRI 0
#define BUTTON_PIO_HAS_OUT 0
#define BUTTON_PIO_HAS_IN 1
#define BUTTON_PIO_CAPTURE 1
#define BUTTON_PIO_EDGE_TYPE "ANY"
#define BUTTON_PIO_IRQ_TYPE "EDGE"
#define BUTTON_PIO_FREQ 50000000

/*
 * led_pio configuration
 *
 */

#define LED_PIO_NAME "/dev/led_pio"
#define LED_PIO_TYPE "altera_avalon_pio"
#define LED_PIO_BASE 0x02120870
#define LED_PIO_SPAN 16
#define LED_PIO_DO_TEST_BENCH_WIRING 0
#define LED_PIO_DRIVEN_SIM_VALUE 0x0000
#define LED_PIO_HAS_TRI 0
#define LED_PIO_HAS_OUT 1
#define LED_PIO_HAS_IN 0
#define LED_PIO_CAPTURE 0
#define LED_PIO_EDGE_TYPE "NONE"
#define LED_PIO_IRQ_TYPE "NONE"
#define LED_PIO_FREQ 50000000

/*
 * lcd_display configuration
 *
 */

#define LCD_DISPLAY_NAME "/dev/lcd_display"
#define LCD_DISPLAY_TYPE "altera_avalon_lcd_16207"
#define LCD_DISPLAY_BASE 0x02120880
#define LCD_DISPLAY_SPAN 16

/*
 * high_res_timer configuration
 *
 */

#define HIGH_RES_TIMER_NAME "/dev/high_res_timer"
#define HIGH_RES_TIMER_TYPE "altera_avalon_timer"
#define HIGH_RES_TIMER_BASE 0x02120820
#define HIGH_RES_TIMER_SPAN 32
#define HIGH_RES_TIMER_IRQ 3
#define HIGH_RES_TIMER_ALWAYS_RUN 0
#define HIGH_RES_TIMER_FIXED_PERIOD 0
#define HIGH_RES_TIMER_SNAPSHOT 1
#define HIGH_RES_TIMER_PERIOD 1
#define HIGH_RES_TIMER_PERIOD_UNITS "ms"
#define HIGH_RES_TIMER_RESET_OUTPUT 0
#define HIGH_RES_TIMER_TIMEOUT_PULSE_OUTPUT 0
#define HIGH_RES_TIMER_MULT 0.001
#define HIGH_RES_TIMER_FREQ 50000000

/*
 * seven_seg_pio configuration
 *
 */

#define SEVEN_SEG_PIO_NAME "/dev/seven_seg_pio"
#define SEVEN_SEG_PIO_TYPE "altera_avalon_pio"
#define SEVEN_SEG_PIO_BASE 0x02120890
#define SEVEN_SEG_PIO_SPAN 16
#define SEVEN_SEG_PIO_DO_TEST_BENCH_WIRING 0
#define SEVEN_SEG_PIO_DRIVEN_SIM_VALUE 0x0000
#define SEVEN_SEG_PIO_HAS_TRI 0
#define SEVEN_SEG_PIO_HAS_OUT 1
#define SEVEN_SEG_PIO_HAS_IN 0
#define SEVEN_SEG_PIO_CAPTURE 0
#define SEVEN_SEG_PIO_EDGE_TYPE "NONE"
#define SEVEN_SEG_PIO_IRQ_TYPE "NONE"
#define SEVEN_SEG_PIO_FREQ 50000000

/*
 * reconfig_request_pio configuration
 *
 */

#define RECONFIG_REQUEST_PIO_NAME "/dev/reconfig_request_pio"
#define RECONFIG_REQUEST_PIO_TYPE "altera_avalon_pio"
#define RECONFIG_REQUEST_PIO_BASE 0x021208A0
#define RECONFIG_REQUEST_PIO_SPAN 16
#define RECONFIG_REQUEST_PIO_DO_TEST_BENCH_WIRING 0
#define RECONFIG_REQUEST_PIO_DRIVEN_SIM_VALUE 0x0000
#define RECONFIG_REQUEST_PIO_HAS_TRI 1
#define RECONFIG_REQUEST_PIO_HAS_OUT 0
#define RECONFIG_REQUEST_PIO_HAS_IN 0
#define RECONFIG_REQUEST_PIO_CAPTURE 0
#define RECONFIG_REQUEST_PIO_EDGE_TYPE "NONE"
#define RECONFIG_REQUEST_PIO_IRQ_TYPE "NONE"
#define RECONFIG_REQUEST_PIO_FREQ 50000000

/*
 * uart1 configuration
 *
 */

#define UART1_NAME "/dev/uart1"
#define UART1_TYPE "altera_avalon_uart"
#define UART1_BASE 0x02120840
#define UART1_SPAN 32
#define UART1_IRQ 4
#define UART1_BAUD 115200
#define UART1_DATA_BITS 8
#define UART1_FIXED_BAUD 1
#define UART1_PARITY 'N'
#define UART1_STOP_BITS 1
#define UART1_USE_CTS_RTS 0
#define UART1_USE_EOP_REGISTER 0
#define UART1_SIM_TRUE_BAUD 0
#define UART1_SIM_CHAR_STREAM ""
#define UART1_FREQ 50000000

/*
 * sysid configuration
 *
 */

#define SYSID_NAME "/dev/sysid"
#define SYSID_TYPE "altera_avalon_sysid"
#define SYSID_BASE 0x021208B8
#define SYSID_SPAN 8
#define SYSID_ID 1253279441u
#define SYSID_TIMESTAMP 1145613282u

/*
 * sdram configuration
 *
 */

#define SDRAM_NAME "/dev/sdram"
#define SDRAM_TYPE "altera_avalon_new_sdram_controller"
#define SDRAM_BASE 0x01000000
#define SDRAM_SPAN 16777216
#define SDRAM_REGISTER_DATA_IN 1
#define SDRAM_SIM_MODEL_BASE 1
#define SDRAM_SDRAM_DATA_WIDTH 32
#define SDRAM_SDRAM_ADDR_WIDTH 12
#define SDRAM_SDRAM_ROW_WIDTH 12
#define SDRAM_SDRAM_COL_WIDTH 8
#define SDRAM_SDRAM_NUM_CHIPSELECTS 1
#define SDRAM_SDRAM_NUM_BANKS 4
#define SDRAM_REFRESH_PERIOD 15.625
#define SDRAM_POWERUP_DELAY 100
#define SDRAM_CAS_LATENCY 3
#define SDRAM_T_RFC 70
#define SDRAM_T_RP 20
#define SDRAM_T_MRD 3
#define SDRAM_T_RCD 20
#define SDRAM_T_AC 5.5
#define SDRAM_T_WR 14
#define SDRAM_INIT_REFRESH_COMMANDS 2
#define SDRAM_INIT_NOP_DELAY 0
#define SDRAM_SHARED_DATA 0
#define SDRAM_STARVATION_INDICATOR 0
#define SDRAM_TRISTATE_BRIDGE_SLAVE ""
#define SDRAM_IS_INITIALIZED 1
#define SDRAM_SDRAM_BANK_WIDTH 2
#define SDRAM_CONTENTS_INFO "SIMDIR/sdram.dat 1124853293"

/*
 * sdram_pll configuration
 *
 */

#define SDRAM_PLL_NAME "/dev/sdram_pll"
#define SDRAM_PLL_TYPE "altera_avalon_pll"
#define SDRAM_PLL_BASE 0x00800000
#define SDRAM_PLL_SPAN 32
#define SDRAM_PLL_LOCKED "None"
#define SDRAM_PLL_ARESET "None"
#define SDRAM_PLL_PLLENA "None"
#define SDRAM_PLL_PFDENA "None"
#define SDRAM_PLL_CONFIG_DONE 1

/*
 * connector_pll configuration
 *
 */

#define CONNECTOR_PLL_NAME "/dev/connector_pll"
#define CONNECTOR_PLL_TYPE "altera_avalon_pll"
#define CONNECTOR_PLL_BASE 0x00800020
#define CONNECTOR_PLL_SPAN 32
#define CONNECTOR_PLL_LOCKED "None"
#define CONNECTOR_PLL_ARESET "None"
#define CONNECTOR_PLL_PLLENA "None"
#define CONNECTOR_PLL_PFDENA "None"
#define CONNECTOR_PLL_CONFIG_DONE 1

/*
 * system library configuration
 *
 */

#define ALT_MAX_FD 32
#define ALT_SYS_CLK SYS_CLK_TIMER
#define ALT_TIMESTAMP_CLK HIGH_RES_TIMER

/*
 * Devices associated with code sections.
 *
 */

#define ALT_TEXT_DEVICE       SDRAM
#define ALT_RODATA_DEVICE     SDRAM
#define ALT_RWDATA_DEVICE     SDRAM
#define ALT_EXCEPTIONS_DEVICE SDRAM
#define ALT_RESET_DEVICE      EXT_FLASH


#endif /* __SYSTEM_H_ */
