{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Fitter Quartus II " "Info: Running Quartus II Fitter" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 6.0 Build 178 04/27/2006 SJ Web Edition " "Info: Version 6.0 Build 178 04/27/2006 SJ Web Edition" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Thu Oct 06 16:03:16 2011 " "Info: Processing started: Thu Oct 06 16:03:16 2011" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_fit --read_settings_files=off --write_settings_files=off standard -c standard " "Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off standard -c standard" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Info" "IMPP_MPP_USER_DEVICE" "standard EP1C20F400C7 " "Info: Selected device EP1C20F400C7 for design \"standard\"" {  } {  } 0 0 "Selected device %2!s! for design \"%1!s!\"" 0 0}
{ "Info" "ICUT_CUT_YGR_PLL_CAN_ACHIEVE_RATIO_AND_PHASE_SHIFT" "std_1c20:inst\|sdram_pll:the_sdram_pll\|altpllsdram_pll:the_pll\|altpll:altpll_component\|pll " "Info: Implementing parameter values for PLL \"std_1c20:inst\|sdram_pll:the_sdram_pll\|altpllsdram_pll:the_pll\|altpll:altpll_component\|pll\"" { { "Info" "ICUT_CUT_YGR_PLL_PARAMETERS_FACTORS" "std_1c20:inst\|sdram_pll:the_sdram_pll\|altpllsdram_pll:the_pll\|altpll:altpll_component\|_clk0 1 1 0 0 " "Info: Implementing clock multiplication of 1, clock division of 1, and phase shift of 0 degrees (0 ps) for std_1c20:inst\|sdram_pll:the_sdram_pll\|altpllsdram_pll:the_pll\|altpll:altpll_component\|_clk0 port" {  } {  } 0 0 "Implementing clock multiplication of %2!d!, clock division of %3!d!, and phase shift of %4!d! degrees (%5!d! ps) for %1!s! port" 0 0} { "Info" "ICUT_CUT_YGR_PLL_PARAMETERS_FACTORS" "std_1c20:inst\|sdram_pll:the_sdram_pll\|altpllsdram_pll:the_pll\|altpll:altpll_component\|_extclk0 1 1 -63 -3499 " "Info: Implementing clock multiplication of 1, clock division of 1, and phase shift of -63 degrees (-3499 ps) for std_1c20:inst\|sdram_pll:the_sdram_pll\|altpllsdram_pll:the_pll\|altpll:altpll_component\|_extclk0 port" {  } {  } 0 0 "Implementing clock multiplication of %2!d!, clock division of %3!d!, and phase shift of %4!d! degrees (%5!d! ps) for %1!s! port" 0 0}  } { { "altpll.tdf" "" { Text "d:/altera/quartus60/libraries/megafunctions/altpll.tdf" 767 3 0 } } { "altpllsdram_pll.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/altpllsdram_pll.vhd" 137 -1 0 } } { "sdram_pll.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/sdram_pll.vhd" 145 -1 0 } } { "std_1c20.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/std_1c20.vhd" 10450 -1 0 } } { "standard.bdf" "" { Schematic "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/standard.bdf" { { 560 808 1272 1296 "inst" "" } } } }  } 0 0 "Implementing parameter values for PLL \"%1!s!\"" 0 0}
{ "Info" "ICUT_CUT_YGR_PLL_CAN_ACHIEVE_RATIO_AND_PHASE_SHIFT" "std_1c20:inst\|connector_pll:the_connector_pll\|altpllconnector_pll:the_pll\|altpll:altpll_component\|pll " "Info: Implementing parameter values for PLL \"std_1c20:inst\|connector_pll:the_connector_pll\|altpllconnector_pll:the_pll\|altpll:altpll_component\|pll\"" { { "Info" "ICUT_CUT_YGR_PLL_PARAMETERS_FACTORS" "std_1c20:inst\|connector_pll:the_connector_pll\|altpllconnector_pll:the_pll\|altpll:altpll_component\|_extclk0 1 1 0 0 " "Info: Implementing clock multiplication of 1, clock division of 1, and phase shift of 0 degrees (0 ps) for std_1c20:inst\|connector_pll:the_connector_pll\|altpllconnector_pll:the_pll\|altpll:altpll_component\|_extclk0 port" {  } {  } 0 0 "Implementing clock multiplication of %2!d!, clock division of %3!d!, and phase shift of %4!d! degrees (%5!d! ps) for %1!s! port" 0 0}  } { { "altpll.tdf" "" { Text "d:/altera/quartus60/libraries/megafunctions/altpll.tdf" 767 3 0 } } { "altpllconnector_pll.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/altpllconnector_pll.vhd" 137 -1 0 } } { "connector_pll.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/connector_pll.vhd" 145 -1 0 } } { "std_1c20.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/std_1c20.vhd" 9599 -1 0 } } { "standard.bdf" "" { Schematic "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/standard.bdf" { { 560 808 1272 1296 "inst" "" } } } }  } 0 0 "Implementing parameter values for PLL \"%1!s!\"" 0 0}
{ "Critical Warning" "WCUT_CUT_YGR_PLL_MODE_CHANGED" "std_1c20:inst\|connector_pll:the_connector_pll\|altpllconnector_pll:the_pll\|altpll:altpll_component\|pll Zero delay buffer " "Critical Warning: Changed operation mode of PLL \"std_1c20:inst\|connector_pll:the_connector_pll\|altpllconnector_pll:the_pll\|altpll:altpll_component\|pll\" to Zero delay buffer" {  } { { "altpll.tdf" "" { Text "d:/altera/quartus60/libraries/megafunctions/altpll.tdf" 767 3 0 } } { "altpllconnector_pll.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/altpllconnector_pll.vhd" 137 -1 0 } } { "connector_pll.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/connector_pll.vhd" 145 -1 0 } } { "std_1c20.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/std_1c20.vhd" 9599 -1 0 } } { "standard.bdf" "" { Schematic "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/standard.bdf" { { 560 808 1272 1296 "inst" "" } } } }  } 1 0 "Changed operation mode of PLL \"%1!s!\" to %2!s!" 0 0}
{ "Info" "IFITCC_FITCC_INFO_STANDARD_FIT_COMPILATION_ON" "" "Info: Fitter is performing a Standard Fit compilation using maximum Fitter effort to optimize design performance" {  } {  } 0 0 "Fitter is performing a Standard Fit compilation using maximum Fitter effort to optimize design performance" 0 0}
{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Info: Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP1C4F400C7 " "Info: Device EP1C4F400C7 is compatible" {  } {  } 2 0 "Device %1!s! is compatible" 0 0} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP1C4F400I7 " "Info: Device EP1C4F400I7 is compatible" {  } {  } 2 0 "Device %1!s! is compatible" 0 0} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP1C20F400I7 " "Info: Device EP1C20F400I7 is compatible" {  } {  } 2 0 "Device %1!s! is compatible" 0 0}  } {  } 2 0 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0}
{ "Info" "ITAN_TDC_USER_OPTIMIZATION_GOALS" "" "Info: Detected fmax, tsu, tco, and/or tpd requirements -- optimizing circuit to achieve only the specified requirements" {  } {  } 0 0 "Detected fmax, tsu, tco, and/or tpd requirements -- optimizing circuit to achieve only the specified requirements" 0 0}
{ "Extra Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Extra Info: Performing register packing on registers with non-logic cell location assignments" {  } {  } 1 0 "Performing register packing on registers with non-logic cell location assignments" 1 0}
{ "Extra Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Extra Info: Completed register packing on registers with non-logic cell location assignments" {  } {  } 1 0 "Completed register packing on registers with non-logic cell location assignments" 1 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "User Assigned Global Signals Promotion Operation " "Info: Completed User Assigned Global Signals Promotion Operation" {  } {  } 0 0 "Completed %1!s!" 0 0}
{ "Info" "IFYGR_FYGR_GLOBAL_LINES_NEEDED_FOR_TORNADO_DQS" "0 " "Info: DQS I/O pins require 0 global routing resources" {  } {  } 0 0 "DQS I/O pins require %1!d! global routing resources" 0 0}
{ "Info" "IFYGR_FYGR_PLL_CLK_PROMOTION" "" "Info: Promoted PLL clock signals" { { "Info" "IFYGR_FYGR_PLL_PROMOTE_GCLK" "PLD_CLKFB " "Info: Promoted signal \"PLD_CLKFB\" to use global clock" {  } { { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "PLD_CLKFB" } { 0 "PLD_CLKFB" } } } } { "standard.bdf" "" { Schematic "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/standard.bdf" { { 584 520 688 600 "PLD_CLKFB" "" } } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { PLD_CLKFB } "NODE_NAME" } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { PLD_CLKFB } "NODE_NAME" } }  } 0 0 "Promoted signal \"%1!s!\" to use global clock" 0 0} { "Info" "IFYGR_FYGR_PLL_PROMOTE_GCLK_USER" "std_1c20:inst\|sdram_pll:the_sdram_pll\|altpllsdram_pll:the_pll\|altpll:altpll_component\|_clk0 " "Info: Promoted signal \"std_1c20:inst\|sdram_pll:the_sdram_pll\|altpllsdram_pll:the_pll\|altpll:altpll_component\|_clk0\" to use global clock (user assigned)" {  } { { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "std_1c20:inst\|sdram_pll:the_sdram_pll\|altpllsdram_pll:the_pll\|altpll:altpll_component\|_clk0" } { 0 "std_1c20:inst\|sdram_pll:the_sdram_pll\|altpllsdram_pll:the_pll\|altpll:altpll_component\|_clk0" } } } } { "standard.bdf" "" { Schematic "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/standard.bdf" { { 560 808 1272 1296 "inst" "" } } } } { "altpll.tdf" "" { Text "d:/altera/quartus60/libraries/megafunctions/altpll.tdf" 767 3 0 } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { std_1c20:inst|sdram_pll:the_sdram_pll|altpllsdram_pll:the_pll|altpll:altpll_component|_clk0 } "NODE_NAME" } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { std_1c20:inst|sdram_pll:the_sdram_pll|altpllsdram_pll:the_pll|altpll:altpll_component|_clk0 } "NODE_NAME" } }  } 0 0 "Promoted signal \"%1!s!\" to use global clock (user assigned)" 0 0} { "Info" "IFYGR_FYGR_PLL_PROMOTE_GCLK" "PLD_CLOCKINPUT\[1\] " "Info: Promoted signal \"PLD_CLOCKINPUT\[1\]\" to use global clock" {  } { { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "PLD_CLOCKINPUT\[1\]" } { 0 "PLD_CLOCKINPUT\[1\]" } } } } { "standard.bdf" "" { Schematic "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/standard.bdf" { { 600 520 688 616 "PLD_CLOCKINPUT\[1\]" "" } } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { PLD_CLOCKINPUT[1] } "NODE_NAME" } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { PLD_CLOCKINPUT[1] } "NODE_NAME" } }  } 0 0 "Promoted signal \"%1!s!\" to use global clock" 0 0}  } {  } 0 0 "Promoted PLL clock signals" 0 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "PLL Placement Operation " "Info: Completed PLL Placement Operation" {  } {  } 0 0 "Completed %1!s!" 0 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "altera_internal_jtag~TCKUTAP Global clock " "Info: Automatically promoted signal \"altera_internal_jtag~TCKUTAP\" to use Global clock" {  } { { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "altera_internal_jtag~TDO" } } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { altera_internal_jtag~TDO } "NODE_NAME" } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { altera_internal_jtag~TDO } "NODE_NAME" } }  } 0 0 "Automatically promoted signal \"%1!s!\" to use %2!s!" 0 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "std_1c20:inst\|std_1c20_reset_sysclk2_domain_synch_module:std_1c20_reset_sysclk2_domain_synch\|data_out Global clock " "Info: Automatically promoted some destinations of signal \"std_1c20:inst\|std_1c20_reset_sysclk2_domain_synch_module:std_1c20_reset_sysclk2_domain_synch\|data_out\" to use Global clock" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "std_1c20:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_oci_debug:the_cpu_nios2_oci_debug\|jtag_break " "Info: Destination \"std_1c20:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_oci_debug:the_cpu_nios2_oci_debug\|jtag_break\" may be non-global or may not use global clock" {  } { { "cpu.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/cpu.vhd" 741 -1 0 } }  } 0 0 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "std_1c20:inst\|sdram:the_sdram\|active_addr\[8\]~4920 " "Info: Destination \"std_1c20:inst\|sdram:the_sdram\|active_addr\[8\]~4920\" may be non-global or may not use global clock" {  } { { "sdram.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/sdram.vhd" 443 -1 0 } }  } 0 0 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "std_1c20:inst\|sdram:the_sdram\|active_cs_n~318 " "Info: Destination \"std_1c20:inst\|sdram:the_sdram\|active_cs_n~318\" may be non-global or may not use global clock" {  } { { "sdram.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/sdram.vhd" 213 -1 0 } }  } 0 0 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "std_1c20:inst\|sdram:the_sdram\|i_refs\[2\]~287 " "Info: Destination \"std_1c20:inst\|sdram:the_sdram\|i_refs\[2\]~287\" may be non-global or may not use global clock" {  } { { "sdram.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/sdram.vhd" 364 -1 0 } }  } 0 0 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "std_1c20:inst\|sdram:the_sdram\|i_refs\[0\]~288 " "Info: Destination \"std_1c20:inst\|sdram:the_sdram\|i_refs\[0\]~288\" may be non-global or may not use global clock" {  } { { "sdram.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/sdram.vhd" 364 -1 0 } }  } 0 0 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "std_1c20:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_oci_debug:the_cpu_nios2_oci_debug\|internal_resetlatch~185 " "Info: Destination \"std_1c20:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_oci_debug:the_cpu_nios2_oci_debug\|internal_resetlatch~185\" may be non-global or may not use global clock" {  } { { "cpu.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/cpu.vhd" 748 -1 0 } }  } 0 0 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0}  } { { "std_1c20.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/std_1c20.vhd" 7300 -1 0 } }  } 0 0 "Automatically promoted some destinations of signal \"%1!s!\" to use %2!s!" 0 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "sld_hub:sld_hub_inst\|CLR_SIGNAL Global clock " "Info: Automatically promoted some destinations of signal \"sld_hub:sld_hub_inst\|CLR_SIGNAL\" to use Global clock" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "std_1c20:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper\|cpu_jtag_debug_module:the_cpu_jtag_debug_module1\|ir\[0\]~0 " "Info: Destination \"std_1c20:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper\|cpu_jtag_debug_module:the_cpu_jtag_debug_module1\|ir\[0\]~0\" may be non-global or may not use global clock" {  } { { "cpu_jtag_debug_module.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/cpu_jtag_debug_module.vhd" 138 -1 0 } }  } 0 0 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "std_1c20:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_oci_debug:the_cpu_nios2_oci_debug\|internal_resetlatch~185 " "Info: Destination \"std_1c20:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_oci_debug:the_cpu_nios2_oci_debug\|internal_resetlatch~185\" may be non-global or may not use global clock" {  } { { "cpu.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/cpu.vhd" 748 -1 0 } }  } 0 0 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0}  } { { "../../../../quartus60/libraries/megafunctions/sld_hub.vhd" "" { Text "D:/ALTERA/quartus60/libraries/megafunctions/sld_hub.vhd" 316 -1 0 } }  } 0 0 "Automatically promoted some destinations of signal \"%1!s!\" to use %2!s!" 0 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "std_1c20:inst\|std_1c20_reset_PLD_CLKFB_domain_synch_module:std_1c20_reset_PLD_CLKFB_domain_synch\|data_out Global clock " "Info: Automatically promoted signal \"std_1c20:inst\|std_1c20_reset_PLD_CLKFB_domain_synch_module:std_1c20_reset_PLD_CLKFB_domain_synch\|data_out\" to use Global clock" {  } { { "std_1c20.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/std_1c20.vhd" 7424 -1 0 } }  } 0 0 "Automatically promoted signal \"%1!s!\" to use %2!s!" 0 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "std_1c20:inst\|std_1c20_reset_PLD_CLOCKINPUT_domain_synch_module:std_1c20_reset_PLD_CLOCKINPUT_domain_synch\|data_out Global clock " "Info: Automatically promoted signal \"std_1c20:inst\|std_1c20_reset_PLD_CLOCKINPUT_domain_synch_module:std_1c20_reset_PLD_CLOCKINPUT_domain_synch\|data_out\" to use Global clock" {  } { { "std_1c20.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/std_1c20.vhd" 7362 -1 0 } }  } 0 0 "Automatically promoted signal \"%1!s!\" to use %2!s!" 0 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Auto Global Promotion Operation " "Info: Completed Auto Global Promotion Operation" {  } {  } 0 0 "Completed %1!s!" 0 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_FYGR_REGPACKING_INFO" "" "Info: Starting register packing" {  } {  } 0 0 "Starting register packing" 0 0}
{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Extra Info: Started Fast Input/Output/OE register processing" {  } {  } 1 0 "Started Fast Input/Output/OE register processing" 1 0}
{ "Info" "IFSAC_FSAC_IGNORED_FAST_REGISTER_IO_ASSIGNMENTS" "" "Info: Ignoring invalid fast I/O register assignments" {  } {  } 0 0 "Ignoring invalid fast I/O register assignments" 0 0}
{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Extra Info: Finished Fast Input/Output/OE register processing" {  } {  } 1 0 "Finished Fast Input/Output/OE register processing" 1 0}
{ "Info" "IFYGR_FYGR_INFO_AUTO_MODE_REGISTER_PACKING" "Auto Normal " "Info: Fitter is using Normal packing mode for logic elements with Auto setting for Auto Packed Registers logic option" {  } {  } 0 0 "Fitter is using %2!s! packing mode for logic elements with %1!s! setting for Auto Packed Registers logic option" 0 0}
{ "Extra Info" "IFSAC_FSAC_START_LUT_IO_RAM_PACKING" "" "Extra Info: Moving registers into I/O cells, LUTs, and RAM blocks to improve timing and density" {  } {  } 1 0 "Moving registers into I/O cells, LUTs, and RAM blocks to improve timing and density" 1 0}
{ "Info" "IFSAC_FSAC_FINISH_LUT_IO_RAM_PACKING" "" "Info: Finished moving registers into I/O cells, LUTs, and RAM blocks" {  } {  } 0 0 "Finished moving registers into I/O cells, LUTs, and RAM blocks" 0 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "00:00:04 " "Info: Finished register packing: elapsed time is 00:00:04" {  } {  } 0 0 "Finished register packing: elapsed time is %1!s!" 0 0}
{ "Info" "IFSYN_PHYSICAL_SYNTHESIS_START" "" "Info: Starting physical synthesis optimizations" {  } {  } 0 0 "Starting physical synthesis optimizations" 0 0}
{ "Info" "IFSYN_PHYSICAL_SYNTHESIS_ALGO_START" "register retiming " "Info: Starting physical synthesis algorithm register retiming" {  } {  } 0 0 "Starting physical synthesis algorithm %1!s!" 0 0}
{ "Info" "IFSYN_PHYSICAL_SYNTHESIS_ALGO_END" "register retiming 0 " "Info: Physical synthesis algorithm register retiming complete: estimated performance improvement of up to 0 percent" {  } {  } 0 0 "Physical synthesis algorithm %1!s! complete: estimated performance improvement of up to %2!d! percent" 0 0}
{ "Info" "IFSYN_PHYSICAL_SYNTHESIS_ALGO_START" "register retiming " "Info: Starting physical synthesis algorithm register retiming" {  } {  } 0 0 "Starting physical synthesis algorithm %1!s!" 0 0}
{ "Info" "IFSYN_PHYSICAL_SYNTHESIS_ALGO_END" "register retiming 0 " "Info: Physical synthesis algorithm register retiming complete: estimated performance improvement of up to 0 percent" {  } {  } 0 0 "Physical synthesis algorithm %1!s! complete: estimated performance improvement of up to %2!d! percent" 0 0}
{ "Info" "IFSYN_PHYSICAL_SYNTHESIS_ALGO_START" "combinational resynthesis 1 " "Info: Starting physical synthesis algorithm combinational resynthesis 1" {  } {  } 0 0 "Starting physical synthesis algorithm %1!s!" 0 0}
{ "Info" "IFSYN_PHYSICAL_SYNTHESIS_ALGO_END" "combinational resynthesis 1 0 " "Info: Physical synthesis algorithm combinational resynthesis 1 complete: estimated performance improvement of up to 0 percent" {  } {  } 0 0 "Physical synthesis algorithm %1!s! complete: estimated performance improvement of up to %2!d! percent" 0 0}
{ "Info" "IFSYN_PHYSICAL_SYNTHESIS_ALGO_START" "register retiming " "Info: Starting physical synthesis algorithm register retiming" {  } {  } 0 0 "Starting physical synthesis algorithm %1!s!" 0 0}
{ "Info" "IFSYN_PHYSICAL_SYNTHESIS_ALGO_END" "register retiming 0 " "Info: Physical synthesis algorithm register retiming complete: estimated performance improvement of up to 0 percent" {  } {  } 0 0 "Physical synthesis algorithm %1!s! complete: estimated performance improvement of up to %2!d! percent" 0 0}
{ "Info" "IFSYN_PHYSICAL_SYNTHESIS_ALGO_START" "register retiming " "Info: Starting physical synthesis algorithm register retiming" {  } {  } 0 0 "Starting physical synthesis algorithm %1!s!" 0 0}
{ "Info" "IFSYN_PHYSICAL_SYNTHESIS_ALGO_END" "register retiming 0 " "Info: Physical synthesis algorithm register retiming complete: estimated performance improvement of up to 0 percent" {  } {  } 0 0 "Physical synthesis algorithm %1!s! complete: estimated performance improvement of up to %2!d! percent" 0 0}
{ "Info" "IFSYN_PHYSICAL_SYNTHESIS_ALGO_START" "combinational resynthesis 1 " "Info: Starting physical synthesis algorithm combinational resynthesis 1" {  } {  } 0 0 "Starting physical synthesis algorithm %1!s!" 0 0}
{ "Info" "IFSYN_PHYSICAL_SYNTHESIS_ALGO_END" "combinational resynthesis 1 0 " "Info: Physical synthesis algorithm combinational resynthesis 1 complete: estimated performance improvement of up to 0 percent" {  } {  } 0 0 "Physical synthesis algorithm %1!s! complete: estimated performance improvement of up to %2!d! percent" 0 0}
{ "Info" "IFSYN_PHYSICAL_SYNTHESIS_ALGO_START" "logic and register replication " "Info: Starting physical synthesis algorithm logic and register replication" {  } {  } 0 0 "Starting physical synthesis algorithm %1!s!" 0 0}
{ "Info" "IFSYN_PHYSICAL_SYNTHESIS_ALGO_END" "logic and register replication 0 " "Info: Physical synthesis algorithm logic and register replication complete: estimated performance improvement of up to 0 percent" {  } {  } 0 0 "Physical synthesis algorithm %1!s! complete: estimated performance improvement of up to %2!d! percent" 0 0}
{ "Info" "IFSYN_PHYSICAL_SYNTHESIS_END" "00:05:20 " "Info: Physical synthesis optimizations complete: elapsed time is 00:05:20" {  } {  } 0 0 "Physical synthesis optimizations complete: elapsed time is %1!s!" 0 0}
{ "Info" "IFSAC_FSAC_RAM_METASTABILITY_INFO" "" "Info: Design uses memory blocks. Violating setup or hold times of memory block address registers could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements." {  } {  } 0 0 "Design uses memory blocks. Violating setup or hold times of memory block address registers could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements." 0 0}
{ "Warning" "WCUT_CUT_UNATTACHED_ASGN" "" "Warning: Ignored locations or region assignments to the following nodes" { { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "CTS\[1\] " "Warning: Node \"CTS\[1\]\" is assigned to location or region, but does not exist in design" {  } { { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "CTS\[1\]" } } } }  } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DCD\[1\] " "Warning: Node \"DCD\[1\]\" is assigned to location or region, but does not exist in design" {  } { { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "DCD\[1\]" } } } }  } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DSR\[1\] " "Warning: Node \"DSR\[1\]\" is assigned to location or region, but does not exist in design" {  } { { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "DSR\[1\]" } } } }  } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DTR\[1\] " "Warning: Node \"DTR\[1\]\" is assigned to location or region, but does not exist in design" {  } { { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "DTR\[1\]" } } } }  } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET_CYCLE_N " "Warning: Node \"ENET_CYCLE_N\" is assigned to location or region, but does not exist in design" {  } { { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "ENET_CYCLE_N" } } } }  } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET_DATACS_N " "Warning: Node \"ENET_DATACS_N\" is assigned to location or region, but does not exist in design" {  } { { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "ENET_DATACS_N" } } } }  } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET_LCLK " "Warning: Node \"ENET_LCLK\" is assigned to location or region, but does not exist in design" {  } { { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "ENET_LCLK" } } } }  } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET_LDEV_N " "Warning: Node \"ENET_LDEV_N\" is assigned to location or region, but does not exist in design" {  } { { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "ENET_LDEV_N" } } } }  } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET_RDYRTN_N " "Warning: Node \"ENET_RDYRTN_N\" is assigned to location or region, but does not exist in design" {  } { { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "ENET_RDYRTN_N" } } } }  } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET_SRDY_N " "Warning: Node \"ENET_SRDY_N\" is assigned to location or region, but does not exist in design" {  } { { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "ENET_SRDY_N" } } } }  } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET_W_R_N " "Warning: Node \"ENET_W_R_N\" is assigned to location or region, but does not exist in design" {  } { { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "ENET_W_R_N" } } } }  } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FLASH_RY_BY_N " "Warning: Node \"FLASH_RY_BY_N\" is assigned to location or region, but does not exist in design" {  } { { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "FLASH_RY_BY_N" } } } }  } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "INIT_DONE " "Warning: Node \"INIT_DONE\" is assigned to location or region, but does not exist in design" {  } { { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "INIT_DONE" } } } }  } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "PLD_ASDO " "Warning: Node \"PLD_ASDO\" is assigned to location or region, but does not exist in design" {  } { { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "PLD_ASDO" } } } }  } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "PLD_CE_N " "Warning: Node \"PLD_CE_N\" is assigned to location or region, but does not exist in design" {  } { { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "PLD_CE_N" } } } }  } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "PLD_CS_N " "Warning: Node \"PLD_CS_N\" is assigned to location or region, but does not exist in design" {  } { { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "PLD_CS_N" } } } }  } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "PLD_DATA\[0\] " "Warning: Node \"PLD_DATA\[0\]\" is assigned to location or region, but does not exist in design" {  } { { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "PLD_DATA\[0\]" } } } }  } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "PLD_MSEL\[0\] " "Warning: Node \"PLD_MSEL\[0\]\" is assigned to location or region, but does not exist in design" {  } { { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "PLD_MSEL\[0\]" } } } }  } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "PLD_MSEL\[1\] " "Warning: Node \"PLD_MSEL\[1\]\" is assigned to location or region, but does not exist in design" {  } { { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "PLD_MSEL\[1\]" } } } }  } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "PROTO1_CLKOUT " "Warning: Node \"PROTO1_CLKOUT\" is assigned to location or region, but does not exist in design" {  } { { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "PROTO1_CLKOUT" } } } }  } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "PROTO1_IO\[16\] " "Warning: Node \"PROTO1_IO\[16\]\" is assigned to location or region, but does not exist in design" {  } { { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "PROTO1_IO\[16\]" } } } }  } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "PROTO1_IO\[19\] " "Warning: Node \"PROTO1_IO\[19\]\" is assigned to location or region, but does not exist in design" {  } { { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "PROTO1_IO\[19\]" } } } }  } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "PROTO1_IO\[22\] " "Warning: Node \"PROTO1_IO\[22\]\" is assigned to location or region, but does not exist in design" {  } { { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "PROTO1_IO\[22\]" } } } }  } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "PROTO1_IO\[23\] " "Warning: Node \"PROTO1_IO\[23\]\" is assigned to location or region, but does not exist in design" {  } { { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "PROTO1_IO\[23\]" } } } }  } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "PROTO1_IO\[28\] " "Warning: Node \"PROTO1_IO\[28\]\" is assigned to location or region, but does not exist in design" {  } { { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "PROTO1_IO\[28\]" } } } }  } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "PROTO1_IO\[40\] " "Warning: Node \"PROTO1_IO\[40\]\" is assigned to location or region, but does not exist in design" {  } { { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "PROTO1_IO\[40\]" } } } }  } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "PROTO2_CARDSEL_N " "Warning: Node \"PROTO2_CARDSEL_N\" is assigned to location or region, but does not exist in design" {  } { { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "PROTO2_CARDSEL_N" } } } }  } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "PROTO2_CLKOUT " "Warning: Node \"PROTO2_CLKOUT\" is assigned to location or region, but does not exist in design" {  } { { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "PROTO2_CLKOUT" } } } }  } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "PROTO2_IO\[0\] " "Warning: Node \"PROTO2_IO\[0\]\" is assigned to location or region, but does not exist in design" {  } { { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "PROTO2_IO\[0\]" } } } }  } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "PROTO2_IO\[10\] " "Warning: Node \"PROTO2_IO\[10\]\" is assigned to location or region, but does not exist in design" {  } { { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "PROTO2_IO\[10\]" } } } }  } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "PROTO2_IO\[11\] " "Warning: Node \"PROTO2_IO\[11\]\" is assigned to location or region, but does not exist in design" {  } { { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "PROTO2_IO\[11\]" } } } }  } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "PROTO2_IO\[12\] " "Warning: Node \"PROTO2_IO\[12\]\" is assigned to location or region, but does not exist in design" {  } { { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "PROTO2_IO\[12\]" } } } }  } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "PROTO2_IO\[13\] " "Warning: Node \"PROTO2_IO\[13\]\" is assigned to location or region, but does not exist in design" {  } { { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "PROTO2_IO\[13\]" } } } }  } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "PROTO2_IO\[14\] " "Warning: Node \"PROTO2_IO\[14\]\" is assigned to location or region, but does not exist in design" {  } { { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "PROTO2_IO\[14\]" } } } }  } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "PROTO2_IO\[15\] " "Warning: Node \"PROTO2_IO\[15\]\" is assigned to location or region, but does not exist in design" {  } { { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "PROTO2_IO\[15\]" } } } }  } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "PROTO2_IO\[16\] " "Warning: Node \"PROTO2_IO\[16\]\" is assigned to location or region, but does not exist in design" {  } { { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "PROTO2_IO\[16\]" } } } }  } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "PROTO2_IO\[17\] " "Warning: Node \"PROTO2_IO\[17\]\" is assigned to location or region, but does not exist in design" {  } { { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "PROTO2_IO\[17\]" } } } }  } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "PROTO2_IO\[18\] " "Warning: Node \"PROTO2_IO\[18\]\" is assigned to location or region, but does not exist in design" {  } { { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "PROTO2_IO\[18\]" } } } }  } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "PROTO2_IO\[19\] " "Warning: Node \"PROTO2_IO\[19\]\" is assigned to location or region, but does not exist in design" {  } { { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "PROTO2_IO\[19\]" } } } }  } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "PROTO2_IO\[1\] " "Warning: Node \"PROTO2_IO\[1\]\" is assigned to location or region, but does not exist in design" {  } { { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "PROTO2_IO\[1\]" } } } }  } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "PROTO2_IO\[20\] " "Warning: Node \"PROTO2_IO\[20\]\" is assigned to location or region, but does not exist in design" {  } { { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "PROTO2_IO\[20\]" } } } }  } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "PROTO2_IO\[21\] " "Warning: Node \"PROTO2_IO\[21\]\" is assigned to location or region, but does not exist in design" {  } { { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "PROTO2_IO\[21\]" } } } }  } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "PROTO2_IO\[22\] " "Warning: Node \"PROTO2_IO\[22\]\" is assigned to location or region, but does not exist in design" {  } { { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "PROTO2_IO\[22\]" } } } }  } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "PROTO2_IO\[23\] " "Warning: Node \"PROTO2_IO\[23\]\" is assigned to location or region, but does not exist in design" {  } { { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "PROTO2_IO\[23\]" } } } }  } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "PROTO2_IO\[24\] " "Warning: Node \"PROTO2_IO\[24\]\" is assigned to location or region, but does not exist in design" {  } { { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "PROTO2_IO\[24\]" } } } }  } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "PROTO2_IO\[25\] " "Warning: Node \"PROTO2_IO\[25\]\" is assigned to location or region, but does not exist in design" {  } { { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "PROTO2_IO\[25\]" } } } }  } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "PROTO2_IO\[26\] " "Warning: Node \"PROTO2_IO\[26\]\" is assigned to location or region, but does not exist in design" {  } { { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "PROTO2_IO\[26\]" } } } }  } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "PROTO2_IO\[27\] " "Warning: Node \"PROTO2_IO\[27\]\" is assigned to location or region, but does not exist in design" {  } { { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "PROTO2_IO\[27\]" } } } }  } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "PROTO2_IO\[28\] " "Warning: Node \"PROTO2_IO\[28\]\" is assigned to location or region, but does not exist in design" {  } { { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "PROTO2_IO\[28\]" } } } }  } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "PROTO2_IO\[29\] " "Warning: Node \"PROTO2_IO\[29\]\" is assigned to location or region, but does not exist in design" {  } { { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "PROTO2_IO\[29\]" } } } }  } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "PROTO2_IO\[2\] " "Warning: Node \"PROTO2_IO\[2\]\" is assigned to location or region, but does not exist in design" {  } { { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "PROTO2_IO\[2\]" } } } }  } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "PROTO2_IO\[30\] " "Warning: Node \"PROTO2_IO\[30\]\" is assigned to location or region, but does not exist in design" {  } { { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "PROTO2_IO\[30\]" } } } }  } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "PROTO2_IO\[31\] " "Warning: Node \"PROTO2_IO\[31\]\" is assigned to location or region, but does not exist in design" {  } { { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "PROTO2_IO\[31\]" } } } }  } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "PROTO2_IO\[32\] " "Warning: Node \"PROTO2_IO\[32\]\" is assigned to location or region, but does not exist in design" {  } { { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "PROTO2_IO\[32\]" } } } }  } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "PROTO2_IO\[33\] " "Warning: Node \"PROTO2_IO\[33\]\" is assigned to location or region, but does not exist in design" {  } { { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "PROTO2_IO\[33\]" } } } }  } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "PROTO2_IO\[34\] " "Warning: Node \"PROTO2_IO\[34\]\" is assigned to location or region, but does not exist in design" {  } { { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "PROTO2_IO\[34\]" } } } }  } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "PROTO2_IO\[35\] " "Warning: Node \"PROTO2_IO\[35\]\" is assigned to location or region, but does not exist in design" {  } { { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "PROTO2_IO\[35\]" } } } }  } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "PROTO2_IO\[36\] " "Warning: Node \"PROTO2_IO\[36\]\" is assigned to location or region, but does not exist in design" {  } { { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "PROTO2_IO\[36\]" } } } }  } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "PROTO2_IO\[37\] " "Warning: Node \"PROTO2_IO\[37\]\" is assigned to location or region, but does not exist in design" {  } { { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "PROTO2_IO\[37\]" } } } }  } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "PROTO2_IO\[38\] " "Warning: Node \"PROTO2_IO\[38\]\" is assigned to location or region, but does not exist in design" {  } { { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "PROTO2_IO\[38\]" } } } }  } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "PROTO2_IO\[39\] " "Warning: Node \"PROTO2_IO\[39\]\" is assigned to location or region, but does not exist in design" {  } { { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "PROTO2_IO\[39\]" } } } }  } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "PROTO2_IO\[3\] " "Warning: Node \"PROTO2_IO\[3\]\" is assigned to location or region, but does not exist in design" {  } { { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "PROTO2_IO\[3\]" } } } }  } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "PROTO2_IO\[40\] " "Warning: Node \"PROTO2_IO\[40\]\" is assigned to location or region, but does not exist in design" {  } { { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "PROTO2_IO\[40\]" } } } }  } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "PROTO2_IO\[4\] " "Warning: Node \"PROTO2_IO\[4\]\" is assigned to location or region, but does not exist in design" {  } { { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "PROTO2_IO\[4\]" } } } }  } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "PROTO2_IO\[5\] " "Warning: Node \"PROTO2_IO\[5\]\" is assigned to location or region, but does not exist in design" {  } { { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "PROTO2_IO\[5\]" } } } }  } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "PROTO2_IO\[6\] " "Warning: Node \"PROTO2_IO\[6\]\" is assigned to location or region, but does not exist in design" {  } { { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "PROTO2_IO\[6\]" } } } }  } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "PROTO2_IO\[7\] " "Warning: Node \"PROTO2_IO\[7\]\" is assigned to location or region, but does not exist in design" {  } { { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "PROTO2_IO\[7\]" } } } }  } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "PROTO2_IO\[8\] " "Warning: Node \"PROTO2_IO\[8\]\" is assigned to location or region, but does not exist in design" {  } { { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "PROTO2_IO\[8\]" } } } }  } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "PROTO2_IO\[9\] " "Warning: Node \"PROTO2_IO\[9\]\" is assigned to location or region, but does not exist in design" {  } { { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "PROTO2_IO\[9\]" } } } }  } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "RI\[1\] " "Warning: Node \"RI\[1\]\" is assigned to location or region, but does not exist in design" {  } { { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "RI\[1\]" } } } }  } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "RTS\[1\] " "Warning: Node \"RTS\[1\]\" is assigned to location or region, but does not exist in design" {  } { { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "RTS\[1\]" } } } }  } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "TR_DEBUGACK " "Warning: Node \"TR_DEBUGACK\" is assigned to location or region, but does not exist in design" {  } { { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "TR_DEBUGACK" } } } }  } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "TR_DEBUGREQ " "Warning: Node \"TR_DEBUGREQ\" is assigned to location or region, but does not exist in design" {  } { { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "TR_DEBUGREQ" } } } }  } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ardy_from_the_lan91c111 " "Warning: Node \"ardy_from_the_lan91c111\" is assigned to location or region, but does not exist in design" {  } { { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "ardy_from_the_lan91c111" } } } }  } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "cf_addr\[0\] " "Warning: Node \"cf_addr\[0\]\" is assigned to location or region, but does not exist in design" {  } { { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "cf_addr\[0\]" } } } }  } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "cf_addr\[10\] " "Warning: Node \"cf_addr\[10\]\" is assigned to location or region, but does not exist in design" {  } { { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "cf_addr\[10\]" } } } }  } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "cf_addr\[1\] " "Warning: Node \"cf_addr\[1\]\" is assigned to location or region, but does not exist in design" {  } { { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "cf_addr\[1\]" } } } }  } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "cf_addr\[2\] " "Warning: Node \"cf_addr\[2\]\" is assigned to location or region, but does not exist in design" {  } { { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "cf_addr\[2\]" } } } }  } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "cf_addr\[3\] " "Warning: Node \"cf_addr\[3\]\" is assigned to location or region, but does not exist in design" {  } { { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "cf_addr\[3\]" } } } }  } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "cf_addr\[4\] " "Warning: Node \"cf_addr\[4\]\" is assigned to location or region, but does not exist in design" {  } { { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "cf_addr\[4\]" } } } }  } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "cf_addr\[5\] " "Warning: Node \"cf_addr\[5\]\" is assigned to location or region, but does not exist in design" {  } { { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "cf_addr\[5\]" } } } }  } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "cf_addr\[6\] " "Warning: Node \"cf_addr\[6\]\" is assigned to location or region, but does not exist in design" {  } { { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "cf_addr\[6\]" } } } }  } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "cf_addr\[7\] " "Warning: Node \"cf_addr\[7\]\" is assigned to location or region, but does not exist in design" {  } { { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "cf_addr\[7\]" } } } }  } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "cf_addr\[8\] " "Warning: Node \"cf_addr\[8\]\" is assigned to location or region, but does not exist in design" {  } { { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "cf_addr\[8\]" } } } }  } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "cf_addr\[9\] " "Warning: Node \"cf_addr\[9\]\" is assigned to location or region, but does not exist in design" {  } { { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "cf_addr\[9\]" } } } }  } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "cf_atasel " "Warning: Node \"cf_atasel\" is assigned to location or region, but does not exist in design" {  } { { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "cf_atasel" } } } }  } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "cf_cs_n\[0\] " "Warning: Node \"cf_cs_n\[0\]\" is assigned to location or region, but does not exist in design" {  } { { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "cf_cs_n\[0\]" } } } }  } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "cf_cs_n\[1\] " "Warning: Node \"cf_cs_n\[1\]\" is assigned to location or region, but does not exist in design" {  } { { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "cf_cs_n\[1\]" } } } }  } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "cf_data\[0\] " "Warning: Node \"cf_data\[0\]\" is assigned to location or region, but does not exist in design" {  } { { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "cf_data\[0\]" } } } }  } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "cf_data\[10\] " "Warning: Node \"cf_data\[10\]\" is assigned to location or region, but does not exist in design" {  } { { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "cf_data\[10\]" } } } }  } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "cf_data\[11\] " "Warning: Node \"cf_data\[11\]\" is assigned to location or region, but does not exist in design" {  } { { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "cf_data\[11\]" } } } }  } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "cf_data\[12\] " "Warning: Node \"cf_data\[12\]\" is assigned to location or region, but does not exist in design" {  } { { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "cf_data\[12\]" } } } }  } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "cf_data\[13\] " "Warning: Node \"cf_data\[13\]\" is assigned to location or region, but does not exist in design" {  } { { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "cf_data\[13\]" } } } }  } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "cf_data\[14\] " "Warning: Node \"cf_data\[14\]\" is assigned to location or region, but does not exist in design" {  } { { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "cf_data\[14\]" } } } }  } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "cf_data\[15\] " "Warning: Node \"cf_data\[15\]\" is assigned to location or region, but does not exist in design" {  } { { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "cf_data\[15\]" } } } }  } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "cf_data\[1\] " "Warning: Node \"cf_data\[1\]\" is assigned to location or region, but does not exist in design" {  } { { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "cf_data\[1\]" } } } }  } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "cf_data\[2\] " "Warning: Node \"cf_data\[2\]\" is assigned to location or region, but does not exist in design" {  } { { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "cf_data\[2\]" } } } }  } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "cf_data\[3\] " "Warning: Node \"cf_data\[3\]\" is assigned to location or region, but does not exist in design" {  } { { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "cf_data\[3\]" } } } }  } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "cf_data\[4\] " "Warning: Node \"cf_data\[4\]\" is assigned to location or region, but does not exist in design" {  } { { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "cf_data\[4\]" } } } }  } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "cf_data\[5\] " "Warning: Node \"cf_data\[5\]\" is assigned to location or region, but does not exist in design" {  } { { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "cf_data\[5\]" } } } }  } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "cf_data\[6\] " "Warning: Node \"cf_data\[6\]\" is assigned to location or region, but does not exist in design" {  } { { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "cf_data\[6\]" } } } }  } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "cf_data\[7\] " "Warning: Node \"cf_data\[7\]\" is assigned to location or region, but does not exist in design" {  } { { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "cf_data\[7\]" } } } }  } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "cf_data\[8\] " "Warning: Node \"cf_data\[8\]\" is assigned to location or region, but does not exist in design" {  } { { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "cf_data\[8\]" } } } }  } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "cf_data\[9\] " "Warning: Node \"cf_data\[9\]\" is assigned to location or region, but does not exist in design" {  } { { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "cf_data\[9\]" } } } }  } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "cf_detect " "Warning: Node \"cf_detect\" is assigned to location or region, but does not exist in design" {  } { { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "cf_detect" } } } }  } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "cf_intrq " "Warning: Node \"cf_intrq\" is assigned to location or region, but does not exist in design" {  } { { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "cf_intrq" } } } }  } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "cf_iord_n " "Warning: Node \"cf_iord_n\" is assigned to location or region, but does not exist in design" {  } { { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "cf_iord_n" } } } }  } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "cf_iordy " "Warning: Node \"cf_iordy\" is assigned to location or region, but does not exist in design" {  } { { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "cf_iordy" } } } }  } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "cf_iowr_n " "Warning: Node \"cf_iowr_n\" is assigned to location or region, but does not exist in design" {  } { { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "cf_iowr_n" } } } }  } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "cf_power " "Warning: Node \"cf_power\" is assigned to location or region, but does not exist in design" {  } { { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "cf_power" } } } }  } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "cf_rfu " "Warning: Node \"cf_rfu\" is assigned to location or region, but does not exist in design" {  } { { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "cf_rfu" } } } }  } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "cf_we_n " "Warning: Node \"cf_we_n\" is assigned to location or region, but does not exist in design" {  } { { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "cf_we_n" } } } }  } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "jtag_debug_offchip_trace_clk_from_the_cpu " "Warning: Node \"jtag_debug_offchip_trace_clk_from_the_cpu\" is assigned to location or region, but does not exist in design" {  } { { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "jtag_debug_offchip_trace_clk_from_the_cpu" } } } }  } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "jtag_debug_offchip_trace_data_from_the_cpu\[0\] " "Warning: Node \"jtag_debug_offchip_trace_data_from_the_cpu\[0\]\" is assigned to location or region, but does not exist in design" {  } { { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "jtag_debug_offchip_trace_data_from_the_cpu\[0\]" } } } }  } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "jtag_debug_offchip_trace_data_from_the_cpu\[10\] " "Warning: Node \"jtag_debug_offchip_trace_data_from_the_cpu\[10\]\" is assigned to location or region, but does not exist in design" {  } { { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "jtag_debug_offchip_trace_data_from_the_cpu\[10\]" } } } }  } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "jtag_debug_offchip_trace_data_from_the_cpu\[11\] " "Warning: Node \"jtag_debug_offchip_trace_data_from_the_cpu\[11\]\" is assigned to location or region, but does not exist in design" {  } { { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "jtag_debug_offchip_trace_data_from_the_cpu\[11\]" } } } }  } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "jtag_debug_offchip_trace_data_from_the_cpu\[12\] " "Warning: Node \"jtag_debug_offchip_trace_data_from_the_cpu\[12\]\" is assigned to location or region, but does not exist in design" {  } { { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "jtag_debug_offchip_trace_data_from_the_cpu\[12\]" } } } }  } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "jtag_debug_offchip_trace_data_from_the_cpu\[13\] " "Warning: Node \"jtag_debug_offchip_trace_data_from_the_cpu\[13\]\" is assigned to location or region, but does not exist in design" {  } { { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "jtag_debug_offchip_trace_data_from_the_cpu\[13\]" } } } }  } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "jtag_debug_offchip_trace_data_from_the_cpu\[14\] " "Warning: Node \"jtag_debug_offchip_trace_data_from_the_cpu\[14\]\" is assigned to location or region, but does not exist in design" {  } { { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "jtag_debug_offchip_trace_data_from_the_cpu\[14\]" } } } }  } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "jtag_debug_offchip_trace_data_from_the_cpu\[15\] " "Warning: Node \"jtag_debug_offchip_trace_data_from_the_cpu\[15\]\" is assigned to location or region, but does not exist in design" {  } { { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "jtag_debug_offchip_trace_data_from_the_cpu\[15\]" } } } }  } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "jtag_debug_offchip_trace_data_from_the_cpu\[16\] " "Warning: Node \"jtag_debug_offchip_trace_data_from_the_cpu\[16\]\" is assigned to location or region, but does not exist in design" {  } { { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "jtag_debug_offchip_trace_data_from_the_cpu\[16\]" } } } }  } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "jtag_debug_offchip_trace_data_from_the_cpu\[17\] " "Warning: Node \"jtag_debug_offchip_trace_data_from_the_cpu\[17\]\" is assigned to location or region, but does not exist in design" {  } { { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "jtag_debug_offchip_trace_data_from_the_cpu\[17\]" } } } }  } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "jtag_debug_offchip_trace_data_from_the_cpu\[1\] " "Warning: Node \"jtag_debug_offchip_trace_data_from_the_cpu\[1\]\" is assigned to location or region, but does not exist in design" {  } { { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "jtag_debug_offchip_trace_data_from_the_cpu\[1\]" } } } }  } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "jtag_debug_offchip_trace_data_from_the_cpu\[2\] " "Warning: Node \"jtag_debug_offchip_trace_data_from_the_cpu\[2\]\" is assigned to location or region, but does not exist in design" {  } { { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "jtag_debug_offchip_trace_data_from_the_cpu\[2\]" } } } }  } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "jtag_debug_offchip_trace_data_from_the_cpu\[3\] " "Warning: Node \"jtag_debug_offchip_trace_data_from_the_cpu\[3\]\" is assigned to location or region, but does not exist in design" {  } { { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "jtag_debug_offchip_trace_data_from_the_cpu\[3\]" } } } }  } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "jtag_debug_offchip_trace_data_from_the_cpu\[4\] " "Warning: Node \"jtag_debug_offchip_trace_data_from_the_cpu\[4\]\" is assigned to location or region, but does not exist in design" {  } { { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "jtag_debug_offchip_trace_data_from_the_cpu\[4\]" } } } }  } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "jtag_debug_offchip_trace_data_from_the_cpu\[5\] " "Warning: Node \"jtag_debug_offchip_trace_data_from_the_cpu\[5\]\" is assigned to location or region, but does not exist in design" {  } { { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "jtag_debug_offchip_trace_data_from_the_cpu\[5\]" } } } }  } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "jtag_debug_offchip_trace_data_from_the_cpu\[6\] " "Warning: Node \"jtag_debug_offchip_trace_data_from_the_cpu\[6\]\" is assigned to location or region, but does not exist in design" {  } { { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "jtag_debug_offchip_trace_data_from_the_cpu\[6\]" } } } }  } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "jtag_debug_offchip_trace_data_from_the_cpu\[7\] " "Warning: Node \"jtag_debug_offchip_trace_data_from_the_cpu\[7\]\" is assigned to location or region, but does not exist in design" {  } { { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "jtag_debug_offchip_trace_data_from_the_cpu\[7\]" } } } }  } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "jtag_debug_offchip_trace_data_from_the_cpu\[8\] " "Warning: Node \"jtag_debug_offchip_trace_data_from_the_cpu\[8\]\" is assigned to location or region, but does not exist in design" {  } { { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "jtag_debug_offchip_trace_data_from_the_cpu\[8\]" } } } }  } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "jtag_debug_offchip_trace_data_from_the_cpu\[9\] " "Warning: Node \"jtag_debug_offchip_trace_data_from_the_cpu\[9\]\" is assigned to location or region, but does not exist in design" {  } { { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "jtag_debug_offchip_trace_data_from_the_cpu\[9\]" } } } }  } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "jtag_debug_trigout_from_the_cpu " "Warning: Node \"jtag_debug_trigout_from_the_cpu\" is assigned to location or region, but does not exist in design" {  } { { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "jtag_debug_trigout_from_the_cpu" } } } }  } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "rxd_to_the_uart2 " "Warning: Node \"rxd_to_the_uart2\" is assigned to location or region, but does not exist in design" {  } { { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "rxd_to_the_uart2" } } } }  } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "txd_from_the_uart2 " "Warning: Node \"txd_from_the_uart2\" is assigned to location or region, but does not exist in design" {  } { { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "txd_from_the_uart2" } } } }  } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0}  } {  } 0 0 "Ignored locations or region assignments to the following nodes" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Info: Fitter placement preparation operations beginning" {  } {  } 0 0 "Fitter placement preparation operations beginning" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:34 " "Info: Fitter placement preparation operations ending: elapsed time is 00:00:34" {  } {  } 0 0 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Info: Fitter placement operations beginning" {  } {  } 0 0 "Fitter placement operations beginning" 0 0}
{ "Info" "IFSYN_PHYSICAL_SYNTHESIS_START" "" "Info: Starting physical synthesis optimizations" {  } {  } 0 0 "Starting physical synthesis optimizations" 0 0}
{ "Info" "IFSYN_PHYSICAL_SYNTHESIS_ALGO_START" "combinational resynthesis 1 " "Info: Starting physical synthesis algorithm combinational resynthesis 1" {  } {  } 0 0 "Starting physical synthesis algorithm %1!s!" 0 0}
{ "Info" "IFSYN_PHYSICAL_SYNTHESIS_ALGO_END" "combinational resynthesis 1 0 " "Info: Physical synthesis algorithm combinational resynthesis 1 complete: estimated performance improvement of up to 0 percent" {  } {  } 0 0 "Physical synthesis algorithm %1!s! complete: estimated performance improvement of up to %2!d! percent" 0 0}
{ "Info" "IFSYN_PHYSICAL_SYNTHESIS_ALGO_START" "logic and register replication " "Info: Starting physical synthesis algorithm logic and register replication" {  } {  } 0 0 "Starting physical synthesis algorithm %1!s!" 0 0}
{ "Info" "IFSYN_PHYSICAL_SYNTHESIS_ALGO_END" "logic and register replication 0 " "Info: Physical synthesis algorithm logic and register replication complete: estimated performance improvement of up to 0 percent" {  } {  } 0 0 "Physical synthesis algorithm %1!s! complete: estimated performance improvement of up to %2!d! percent" 0 0}
{ "Info" "IFSYN_PHYSICAL_SYNTHESIS_ALGO_START" "register unpacking " "Info: Starting physical synthesis algorithm register unpacking" {  } {  } 0 0 "Starting physical synthesis algorithm %1!s!" 0 0}
{ "Info" "IFSYN_PHYSICAL_SYNTHESIS_ALGO_END" "register unpacking 0 " "Info: Physical synthesis algorithm register unpacking complete: estimated performance improvement of up to 0 percent" {  } {  } 0 0 "Physical synthesis algorithm %1!s! complete: estimated performance improvement of up to %2!d! percent" 0 0}
{ "Info" "IFSYN_PHYSICAL_SYNTHESIS_END" "00:01:22 " "Info: Physical synthesis optimizations complete: elapsed time is 00:01:22" {  } {  } 0 0 "Physical synthesis optimizations complete: elapsed time is %1!s!" 0 0}
{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Info: Fitter placement was successful" {  } {  } 0 0 "Fitter placement was successful" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:02:35 " "Info: Fitter placement operations ending: elapsed time is 00:02:35" {  } {  } 0 0 "Fitter placement operations ending: elapsed time is %1!s!" 0 0}
{ "Info" "ITDB_FULL_ESTIMATED_DATA_PATH_RESULT" "15.301 ns register register " "Info: Estimated most critical path is register to register delay of 15.301 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns std_1c20:inst\|cpu:the_cpu\|M_alu_result\[18\]~736 1 REG LAB_X32_Y18 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X32_Y18; Fanout = 1; REG Node = 'std_1c20:inst\|cpu:the_cpu\|M_alu_result\[18\]~736'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { std_1c20:inst|cpu:the_cpu|M_alu_result[18]~736 } "NODE_NAME" } } { "cpu.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/cpu.vhd" 7300 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.927 ns) + CELL(0.258 ns) 1.185 ns std_1c20:inst\|cpu:the_cpu\|A_WE_StdLogicVector~27996 2 COMB LAB_X28_Y18 1 " "Info: 2: + IC(0.927 ns) + CELL(0.258 ns) = 1.185 ns; Loc. = LAB_X28_Y18; Fanout = 1; COMB Node = 'std_1c20:inst\|cpu:the_cpu\|A_WE_StdLogicVector~27996'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.185 ns" { std_1c20:inst|cpu:the_cpu|M_alu_result[18]~736 std_1c20:inst|cpu:the_cpu|A_WE_StdLogicVector~27996 } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.055 ns) + CELL(0.522 ns) 1.762 ns std_1c20:inst\|cpu:the_cpu\|M_alu_result\[18\]~301 3 COMB LAB_X28_Y18 3 " "Info: 3: + IC(0.055 ns) + CELL(0.522 ns) = 1.762 ns; Loc. = LAB_X28_Y18; Fanout = 3; COMB Node = 'std_1c20:inst\|cpu:the_cpu\|M_alu_result\[18\]~301'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.577 ns" { std_1c20:inst|cpu:the_cpu|A_WE_StdLogicVector~27996 std_1c20:inst|cpu:the_cpu|M_alu_result[18]~301 } "NODE_NAME" } } { "cpu.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/cpu.vhd" 7300 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.319 ns) + CELL(0.258 ns) 2.339 ns std_1c20:inst\|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave\|cpu_data_master_requests_lan91c111_s1~352_BDD545 4 COMB LAB_X28_Y18 1 " "Info: 4: + IC(0.319 ns) + CELL(0.258 ns) = 2.339 ns; Loc. = LAB_X28_Y18; Fanout = 1; COMB Node = 'std_1c20:inst\|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave\|cpu_data_master_requests_lan91c111_s1~352_BDD545'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.577 ns" { std_1c20:inst|cpu:the_cpu|M_alu_result[18]~301 std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|cpu_data_master_requests_lan91c111_s1~352_BDD545 } "NODE_NAME" } } { "std_1c20.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/std_1c20.vhd" 2962 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.476 ns) + CELL(0.101 ns) 2.916 ns std_1c20:inst\|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave\|cpu_data_master_requests_lan91c111_s1~349 5 COMB LAB_X28_Y18 5 " "Info: 5: + IC(0.476 ns) + CELL(0.101 ns) = 2.916 ns; Loc. = LAB_X28_Y18; Fanout = 5; COMB Node = 'std_1c20:inst\|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave\|cpu_data_master_requests_lan91c111_s1~349'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.577 ns" { std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|cpu_data_master_requests_lan91c111_s1~352_BDD545 std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|cpu_data_master_requests_lan91c111_s1~349 } "NODE_NAME" } } { "std_1c20.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/std_1c20.vhd" 2962 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.101 ns) + CELL(0.101 ns) 4.118 ns std_1c20:inst\|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave\|last_cycle_cpu_data_master_granted_slave_lan91c111_s1~5_DUP_COMB 6 COMB LAB_X28_Y20 35 " "Info: 6: + IC(1.101 ns) + CELL(0.101 ns) = 4.118 ns; Loc. = LAB_X28_Y20; Fanout = 35; COMB Node = 'std_1c20:inst\|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave\|last_cycle_cpu_data_master_granted_slave_lan91c111_s1~5_DUP_COMB'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.202 ns" { std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|cpu_data_master_requests_lan91c111_s1~349 std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|last_cycle_cpu_data_master_granted_slave_lan91c111_s1~5_DUP_COMB } "NODE_NAME" } } { "std_1c20.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/std_1c20.vhd" 3113 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.695 ns) + CELL(0.522 ns) 5.335 ns std_1c20:inst\|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave\|cpu_data_master_qualified_request_lan91c111_s1~128 7 COMB LAB_X29_Y24 22 " "Info: 7: + IC(0.695 ns) + CELL(0.522 ns) = 5.335 ns; Loc. = LAB_X29_Y24; Fanout = 22; COMB Node = 'std_1c20:inst\|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave\|cpu_data_master_qualified_request_lan91c111_s1~128'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.217 ns" { std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|last_cycle_cpu_data_master_granted_slave_lan91c111_s1~5_DUP_COMB std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|cpu_data_master_qualified_request_lan91c111_s1~128 } "NODE_NAME" } } { "std_1c20.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/std_1c20.vhd" 2956 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.947 ns) + CELL(0.509 ns) 6.791 ns std_1c20:inst\|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave\|Add2~313COUT1_478 8 COMB LAB_X28_Y23 2 " "Info: 8: + IC(0.947 ns) + CELL(0.509 ns) = 6.791 ns; Loc. = LAB_X28_Y23; Fanout = 2; COMB Node = 'std_1c20:inst\|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave\|Add2~313COUT1_478'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.456 ns" { std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|cpu_data_master_qualified_request_lan91c111_s1~128 std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|Add2~313COUT1_478 } "NODE_NAME" } } { "d:/altera/quartus60/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "d:/altera/quartus60/libraries/vhdl/synopsys/syn_arit.vhd" 836 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.071 ns) 6.862 ns std_1c20:inst\|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave\|Add2~321COUT1_480 9 COMB LAB_X28_Y23 2 " "Info: 9: + IC(0.000 ns) + CELL(0.071 ns) = 6.862 ns; Loc. = LAB_X28_Y23; Fanout = 2; COMB Node = 'std_1c20:inst\|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave\|Add2~321COUT1_480'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.071 ns" { std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|Add2~313COUT1_478 std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|Add2~321COUT1_480 } "NODE_NAME" } } { "d:/altera/quartus60/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "d:/altera/quartus60/libraries/vhdl/synopsys/syn_arit.vhd" 836 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.071 ns) 6.933 ns std_1c20:inst\|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave\|Add2~317COUT1_482 10 COMB LAB_X28_Y23 2 " "Info: 10: + IC(0.000 ns) + CELL(0.071 ns) = 6.933 ns; Loc. = LAB_X28_Y23; Fanout = 2; COMB Node = 'std_1c20:inst\|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave\|Add2~317COUT1_482'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.071 ns" { std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|Add2~321COUT1_480 std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|Add2~317COUT1_482 } "NODE_NAME" } } { "d:/altera/quartus60/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "d:/altera/quartus60/libraries/vhdl/synopsys/syn_arit.vhd" 836 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.228 ns) 7.161 ns std_1c20:inst\|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave\|Add2~325 11 COMB LAB_X28_Y23 1 " "Info: 11: + IC(0.000 ns) + CELL(0.228 ns) = 7.161 ns; Loc. = LAB_X28_Y23; Fanout = 1; COMB Node = 'std_1c20:inst\|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave\|Add2~325'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.228 ns" { std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|Add2~317COUT1_482 std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|Add2~325 } "NODE_NAME" } } { "d:/altera/quartus60/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "d:/altera/quartus60/libraries/vhdl/synopsys/syn_arit.vhd" 836 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.601 ns) 7.762 ns std_1c20:inst\|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave\|Add2~328 12 COMB LAB_X28_Y23 12 " "Info: 12: + IC(0.000 ns) + CELL(0.601 ns) = 7.762 ns; Loc. = LAB_X28_Y23; Fanout = 12; COMB Node = 'std_1c20:inst\|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave\|Add2~328'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.601 ns" { std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|Add2~325 std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|Add2~328 } "NODE_NAME" } } { "d:/altera/quartus60/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "d:/altera/quartus60/libraries/vhdl/synopsys/syn_arit.vhd" 836 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.687 ns) + CELL(0.101 ns) 8.550 ns std_1c20:inst\|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave\|read_n_to_the_ext_ram~2_BDD44 13 COMB LAB_X27_Y23 1 " "Info: 13: + IC(0.687 ns) + CELL(0.101 ns) = 8.550 ns; Loc. = LAB_X27_Y23; Fanout = 1; COMB Node = 'std_1c20:inst\|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave\|read_n_to_the_ext_ram~2_BDD44'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.788 ns" { std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|Add2~328 std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|read_n_to_the_ext_ram~2_BDD44 } "NODE_NAME" } } { "std_1c20.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/std_1c20.vhd" 2988 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.476 ns) + CELL(0.101 ns) 9.127 ns std_1c20:inst\|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave\|read_n_to_the_ext_ram~COMB_OUT 14 COMB LAB_X27_Y23 1 " "Info: 14: + IC(0.476 ns) + CELL(0.101 ns) = 9.127 ns; Loc. = LAB_X27_Y23; Fanout = 1; COMB Node = 'std_1c20:inst\|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave\|read_n_to_the_ext_ram~COMB_OUT'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.577 ns" { std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|read_n_to_the_ext_ram~2_BDD44 std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|read_n_to_the_ext_ram~COMB_OUT } "NODE_NAME" } } { "std_1c20.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/std_1c20.vhd" 2988 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(5.997 ns) + CELL(0.177 ns) 15.301 ns std_1c20:inst\|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave\|read_n_to_the_ext_ram 15 REG IOC_X68_Y0_N1 1 " "Info: 15: + IC(5.997 ns) + CELL(0.177 ns) = 15.301 ns; Loc. = IOC_X68_Y0_N1; Fanout = 1; REG Node = 'std_1c20:inst\|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave\|read_n_to_the_ext_ram'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "6.174 ns" { std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|read_n_to_the_ext_ram~COMB_OUT std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|read_n_to_the_ext_ram } "NODE_NAME" } } { "std_1c20.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/std_1c20.vhd" 2988 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.621 ns ( 23.67 % ) " "Info: Total cell delay = 3.621 ns ( 23.67 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "11.680 ns ( 76.33 % ) " "Info: Total interconnect delay = 11.680 ns ( 76.33 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "15.301 ns" { std_1c20:inst|cpu:the_cpu|M_alu_result[18]~736 std_1c20:inst|cpu:the_cpu|A_WE_StdLogicVector~27996 std_1c20:inst|cpu:the_cpu|M_alu_result[18]~301 std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|cpu_data_master_requests_lan91c111_s1~352_BDD545 std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|cpu_data_master_requests_lan91c111_s1~349 std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|last_cycle_cpu_data_master_granted_slave_lan91c111_s1~5_DUP_COMB std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|cpu_data_master_qualified_request_lan91c111_s1~128 std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|Add2~313COUT1_478 std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|Add2~321COUT1_480 std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|Add2~317COUT1_482 std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|Add2~325 std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|Add2~328 std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|read_n_to_the_ext_ram~2_BDD44 std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|read_n_to_the_ext_ram~COMB_OUT std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|read_n_to_the_ext_ram } "NODE_NAME" } }  } 0 0 "Estimated most critical path is %2!s! to %3!s! delay of %1!s!" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Info: Fitter routing operations beginning" {  } {  } 0 0 "Fitter routing operations beginning" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "13 46 " "Info: Average interconnect usage is 13% of the available device resources. Peak interconnect usage is 46%" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "x23_y11 x34_y21 " "Info: The peak interconnect region extends from location x23_y11 to location x34_y21" {  } {  } 0 0 "The peak interconnect region extends from location %1!s! to location %2!s!" 0 0}  } {  } 0 0 "Average interconnect usage is %1!d!%% of the available device resources. Peak interconnect usage is %2!d!%%" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:26 " "Info: Fitter routing operations ending: elapsed time is 00:00:26" {  } {  } 0 0 "Fitter routing operations ending: elapsed time is %1!s!" 0 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Fixed Delay Chain Operation " "Info: Completed Fixed Delay Chain Operation" {  } {  } 0 0 "Completed %1!s!" 0 0}
{ "Info" "IDAT_DAT_STARTED" "" "Info: Started post-fitting delay annotation" {  } {  } 0 0 "Started post-fitting delay annotation" 0 0}
{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0 0 "Delay annotation completed successfully" 0 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Auto Delay Chain Operation " "Info: Completed Auto Delay Chain Operation" {  } {  } 0 0 "Completed %1!s!" 0 0}
{ "Info" "IFSAC_FSAC_RAM_METASTABILITY_INFO" "" "Info: Design uses memory blocks. Violating setup or hold times of memory block address registers could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements." {  } {  } 0 0 "Design uses memory blocks. Violating setup or hold times of memory block address registers could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements." 0 0}
{ "Info" "IFSAC_FSAC_GLOBAL_CLK_USES_LAB_LINE_TOP_MSG" "std_1c20:inst\|std_1c20_reset_sysclk2_domain_synch_module:std_1c20_reset_sysclk2_domain_synch\|data_out " "Info: Node std_1c20:inst\|std_1c20_reset_sysclk2_domain_synch_module:std_1c20_reset_sysclk2_domain_synch\|data_out uses non-global routing resources to route signals to global destination nodes" { { "Info" "IFSAC_FSAC_GLOBAL_CLK_USES_LAB_LINE" "clear std_1c20:inst\|clock_0:the_clock_0\|slave_writedata_d1\[0\] " "Info: Port clear -- assigned as a global for destination node std_1c20:inst\|clock_0:the_clock_0\|slave_writedata_d1\[0\] -- routed using non-global resources" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { std_1c20:inst|clock_0:the_clock_0|slave_writedata_d1[0] } "NODE_NAME" } } { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "std_1c20:inst\|clock_0:the_clock_0\|slave_writedata_d1\[0\]" } } } } { "clock_0.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/clock_0.vhd" 1039 -1 0 } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { std_1c20:inst|clock_0:the_clock_0|slave_writedata_d1[0] } "NODE_NAME" } }  } 0 0 "Port %1!s! -- assigned as a global for destination node %2!s! -- routed using non-global resources" 0 0} { "Info" "IFSAC_FSAC_GLOBAL_CLK_USES_LAB_LINE" "clear std_1c20:inst\|clock_1:the_clock_1\|slave_writedata_d1\[0\] " "Info: Port clear -- assigned as a global for destination node std_1c20:inst\|clock_1:the_clock_1\|slave_writedata_d1\[0\] -- routed using non-global resources" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { std_1c20:inst|clock_1:the_clock_1|slave_writedata_d1[0] } "NODE_NAME" } } { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "std_1c20:inst\|clock_1:the_clock_1\|slave_writedata_d1\[0\]" } } } } { "clock_1.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/clock_1.vhd" 1039 -1 0 } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { std_1c20:inst|clock_1:the_clock_1|slave_writedata_d1[0] } "NODE_NAME" } }  } 0 0 "Port %1!s! -- assigned as a global for destination node %2!s! -- routed using non-global resources" 0 0} { "Info" "IFSAC_FSAC_GLOBAL_CLK_USES_LAB_LINE" "clear std_1c20:inst\|clock_1:the_clock_1\|slave_writedata_d1\[8\] " "Info: Port clear -- assigned as a global for destination node std_1c20:inst\|clock_1:the_clock_1\|slave_writedata_d1\[8\] -- routed using non-global resources" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { std_1c20:inst|clock_1:the_clock_1|slave_writedata_d1[8] } "NODE_NAME" } } { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "std_1c20:inst\|clock_1:the_clock_1\|slave_writedata_d1\[8\]" } } } } { "clock_1.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/clock_1.vhd" 1039 -1 0 } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { std_1c20:inst|clock_1:the_clock_1|slave_writedata_d1[8] } "NODE_NAME" } }  } 0 0 "Port %1!s! -- assigned as a global for destination node %2!s! -- routed using non-global resources" 0 0} { "Info" "IFSAC_FSAC_GLOBAL_CLK_USES_LAB_LINE" "clear std_1c20:inst\|clock_0:the_clock_0\|slave_writedata_d1\[8\] " "Info: Port clear -- assigned as a global for destination node std_1c20:inst\|clock_0:the_clock_0\|slave_writedata_d1\[8\] -- routed using non-global resources" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { std_1c20:inst|clock_0:the_clock_0|slave_writedata_d1[8] } "NODE_NAME" } } { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "std_1c20:inst\|clock_0:the_clock_0\|slave_writedata_d1\[8\]" } } } } { "clock_0.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/clock_0.vhd" 1039 -1 0 } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { std_1c20:inst|clock_0:the_clock_0|slave_writedata_d1[8] } "NODE_NAME" } }  } 0 0 "Port %1!s! -- assigned as a global for destination node %2!s! -- routed using non-global resources" 0 0} { "Info" "IFSAC_FSAC_GLOBAL_CLK_USES_LAB_LINE" "clear std_1c20:inst\|clock_0:the_clock_0\|slave_writedata_d1\[3\] " "Info: Port clear -- assigned as a global for destination node std_1c20:inst\|clock_0:the_clock_0\|slave_writedata_d1\[3\] -- routed using non-global resources" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { std_1c20:inst|clock_0:the_clock_0|slave_writedata_d1[3] } "NODE_NAME" } } { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "std_1c20:inst\|clock_0:the_clock_0\|slave_writedata_d1\[3\]" } } } } { "clock_0.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/clock_0.vhd" 1039 -1 0 } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { std_1c20:inst|clock_0:the_clock_0|slave_writedata_d1[3] } "NODE_NAME" } }  } 0 0 "Port %1!s! -- assigned as a global for destination node %2!s! -- routed using non-global resources" 0 0} { "Info" "IFSAC_FSAC_GLOBAL_CLK_USES_LAB_LINE" "clear std_1c20:inst\|clock_1:the_clock_1\|clock_1_master_read_done_sync_module:clock_1_master_read_done_sync\|data_in_d1 " "Info: Port clear -- assigned as a global for destination node std_1c20:inst\|clock_1:the_clock_1\|clock_1_master_read_done_sync_module:clock_1_master_read_done_sync\|data_in_d1 -- routed using non-global resources" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { std_1c20:inst|clock_1:the_clock_1|clock_1_master_read_done_sync_module:clock_1_master_read_done_sync|data_in_d1 } "NODE_NAME" } } { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "std_1c20:inst\|clock_1:the_clock_1\|clock_1_master_read_done_sync_module:clock_1_master_read_done_sync\|data_in_d1" } } } } { "clock_1.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/clock_1.vhd" 40 -1 0 } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { std_1c20:inst|clock_1:the_clock_1|clock_1_master_read_done_sync_module:clock_1_master_read_done_sync|data_in_d1 } "NODE_NAME" } }  } 0 0 "Port %1!s! -- assigned as a global for destination node %2!s! -- routed using non-global resources" 0 0} { "Info" "IFSAC_FSAC_GLOBAL_CLK_USES_LAB_LINE" "clear std_1c20:inst\|clock_1:the_clock_1\|slave_readdata\[8\] " "Info: Port clear -- assigned as a global for destination node std_1c20:inst\|clock_1:the_clock_1\|slave_readdata\[8\] -- routed using non-global resources" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { std_1c20:inst|clock_1:the_clock_1|slave_readdata[8] } "NODE_NAME" } } { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "std_1c20:inst\|clock_1:the_clock_1\|slave_readdata\[8\]" } } } } { "clock_1.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/clock_1.vhd" 1027 -1 0 } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { std_1c20:inst|clock_1:the_clock_1|slave_readdata[8] } "NODE_NAME" } }  } 0 0 "Port %1!s! -- assigned as a global for destination node %2!s! -- routed using non-global resources" 0 0} { "Info" "IFSAC_FSAC_GLOBAL_CLK_USES_LAB_LINE" "clear std_1c20:inst\|clock_0:the_clock_0\|slave_readdata\[14\] " "Info: Port clear -- assigned as a global for destination node std_1c20:inst\|clock_0:the_clock_0\|slave_readdata\[14\] -- routed using non-global resources" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { std_1c20:inst|clock_0:the_clock_0|slave_readdata[14] } "NODE_NAME" } } { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "std_1c20:inst\|clock_0:the_clock_0\|slave_readdata\[14\]" } } } } { "clock_0.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/clock_0.vhd" 1027 -1 0 } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { std_1c20:inst|clock_0:the_clock_0|slave_readdata[14] } "NODE_NAME" } }  } 0 0 "Port %1!s! -- assigned as a global for destination node %2!s! -- routed using non-global resources" 0 0} { "Info" "IFSAC_FSAC_GLOBAL_CLK_USES_LAB_LINE" "clear std_1c20:inst\|clock_1:the_clock_1\|slave_readdata\[14\] " "Info: Port clear -- assigned as a global for destination node std_1c20:inst\|clock_1:the_clock_1\|slave_readdata\[14\] -- routed using non-global resources" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { std_1c20:inst|clock_1:the_clock_1|slave_readdata[14] } "NODE_NAME" } } { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "std_1c20:inst\|clock_1:the_clock_1\|slave_readdata\[14\]" } } } } { "clock_1.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/clock_1.vhd" 1027 -1 0 } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { std_1c20:inst|clock_1:the_clock_1|slave_readdata[14] } "NODE_NAME" } }  } 0 0 "Port %1!s! -- assigned as a global for destination node %2!s! -- routed using non-global resources" 0 0} { "Info" "IFSAC_FSAC_GLOBAL_CLK_USES_LAB_LINE" "clear std_1c20:inst\|clock_0:the_clock_0\|slave_readdata\[2\] " "Info: Port clear -- assigned as a global for destination node std_1c20:inst\|clock_0:the_clock_0\|slave_readdata\[2\] -- routed using non-global resources" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { std_1c20:inst|clock_0:the_clock_0|slave_readdata[2] } "NODE_NAME" } } { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "std_1c20:inst\|clock_0:the_clock_0\|slave_readdata\[2\]" } } } } { "clock_0.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/clock_0.vhd" 1027 -1 0 } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { std_1c20:inst|clock_0:the_clock_0|slave_readdata[2] } "NODE_NAME" } }  } 0 0 "Port %1!s! -- assigned as a global for destination node %2!s! -- routed using non-global resources" 0 0} { "Info" "IFSAC_FSAC_GLOBAL_CLK_USES_LAB_LINE" "clear std_1c20:inst\|clock_1:the_clock_1\|slave_readdata\[2\] " "Info: Port clear -- assigned as a global for destination node std_1c20:inst\|clock_1:the_clock_1\|slave_readdata\[2\] -- routed using non-global resources" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { std_1c20:inst|clock_1:the_clock_1|slave_readdata[2] } "NODE_NAME" } } { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "std_1c20:inst\|clock_1:the_clock_1\|slave_readdata\[2\]" } } } } { "clock_1.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/clock_1.vhd" 1027 -1 0 } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { std_1c20:inst|clock_1:the_clock_1|slave_readdata[2] } "NODE_NAME" } }  } 0 0 "Port %1!s! -- assigned as a global for destination node %2!s! -- routed using non-global resources" 0 0} { "Info" "IFSAC_FSAC_GLOBAL_CLK_USES_LAB_LINE" "clear std_1c20:inst\|cpu_data_master_arbitrator:the_cpu_data_master\|registered_cpu_data_master_readdata\[2\] " "Info: Port clear -- assigned as a global for destination node std_1c20:inst\|cpu_data_master_arbitrator:the_cpu_data_master\|registered_cpu_data_master_readdata\[2\] -- routed using non-global resources" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|registered_cpu_data_master_readdata[2] } "NODE_NAME" } } { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "std_1c20:inst\|cpu_data_master_arbitrator:the_cpu_data_master\|registered_cpu_data_master_readdata\[2\]" } } } } { "std_1c20.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/std_1c20.vhd" 1927 -1 0 } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|registered_cpu_data_master_readdata[2] } "NODE_NAME" } }  } 0 0 "Port %1!s! -- assigned as a global for destination node %2!s! -- routed using non-global resources" 0 0} { "Info" "IFSAC_FSAC_GLOBAL_CLK_USES_LAB_LINE" "clear std_1c20:inst\|clock_1:the_clock_1\|slave_writedata_d1\[4\] " "Info: Port clear -- assigned as a global for destination node std_1c20:inst\|clock_1:the_clock_1\|slave_writedata_d1\[4\] -- routed using non-global resources" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { std_1c20:inst|clock_1:the_clock_1|slave_writedata_d1[4] } "NODE_NAME" } } { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "std_1c20:inst\|clock_1:the_clock_1\|slave_writedata_d1\[4\]" } } } } { "clock_1.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/clock_1.vhd" 1039 -1 0 } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { std_1c20:inst|clock_1:the_clock_1|slave_writedata_d1[4] } "NODE_NAME" } }  } 0 0 "Port %1!s! -- assigned as a global for destination node %2!s! -- routed using non-global resources" 0 0} { "Info" "IFSAC_FSAC_GLOBAL_CLK_USES_LAB_LINE" "clear std_1c20:inst\|cpu_data_master_arbitrator:the_cpu_data_master\|dbs_8_reg_segment_2\[5\]~769 " "Info: Port clear -- assigned as a global for destination node std_1c20:inst\|cpu_data_master_arbitrator:the_cpu_data_master\|dbs_8_reg_segment_2\[5\]~769 -- routed using non-global resources" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|dbs_8_reg_segment_2[5]~769 } "NODE_NAME" } } { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "std_1c20:inst\|cpu_data_master_arbitrator:the_cpu_data_master\|dbs_8_reg_segment_2\[5\]~769" } } } } { "std_1c20.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/std_1c20.vhd" 1991 -1 0 } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|dbs_8_reg_segment_2[5]~769 } "NODE_NAME" } }  } 0 0 "Port %1!s! -- assigned as a global for destination node %2!s! -- routed using non-global resources" 0 0} { "Info" "IFSAC_FSAC_GLOBAL_CLK_USES_LAB_LINE" "clear std_1c20:inst\|clock_0:the_clock_0\|slave_nativeaddress_d1\[2\] " "Info: Port clear -- assigned as a global for destination node std_1c20:inst\|clock_0:the_clock_0\|slave_nativeaddress_d1\[2\] -- routed using non-global resources" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { std_1c20:inst|clock_0:the_clock_0|slave_nativeaddress_d1[2] } "NODE_NAME" } } { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "std_1c20:inst\|clock_0:the_clock_0\|slave_nativeaddress_d1\[2\]" } } } } { "clock_0.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/clock_0.vhd" 1087 -1 0 } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { std_1c20:inst|clock_0:the_clock_0|slave_nativeaddress_d1[2] } "NODE_NAME" } }  } 0 0 "Port %1!s! -- assigned as a global for destination node %2!s! -- routed using non-global resources" 0 0} { "Info" "IFSAC_FSAC_GLOBAL_CLK_USES_LAB_LINE" "clear std_1c20:inst\|clock_1:the_clock_1\|slave_nativeaddress_d1\[2\] " "Info: Port clear -- assigned as a global for destination node std_1c20:inst\|clock_1:the_clock_1\|slave_nativeaddress_d1\[2\] -- routed using non-global resources" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { std_1c20:inst|clock_1:the_clock_1|slave_nativeaddress_d1[2] } "NODE_NAME" } } { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "std_1c20:inst\|clock_1:the_clock_1\|slave_nativeaddress_d1\[2\]" } } } } { "clock_1.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/clock_1.vhd" 1087 -1 0 } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { std_1c20:inst|clock_1:the_clock_1|slave_nativeaddress_d1[2] } "NODE_NAME" } }  } 0 0 "Port %1!s! -- assigned as a global for destination node %2!s! -- routed using non-global resources" 0 0} { "Info" "IFSAC_FSAC_GLOBAL_CLK_USES_LAB_LINE" "clear std_1c20:inst\|clock_1:the_clock_1\|slave_nativeaddress_d1\[0\] " "Info: Port clear -- assigned as a global for destination node std_1c20:inst\|clock_1:the_clock_1\|slave_nativeaddress_d1\[0\] -- routed using non-global resources" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { std_1c20:inst|clock_1:the_clock_1|slave_nativeaddress_d1[0] } "NODE_NAME" } } { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "std_1c20:inst\|clock_1:the_clock_1\|slave_nativeaddress_d1\[0\]" } } } } { "clock_1.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/clock_1.vhd" 1087 -1 0 } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { std_1c20:inst|clock_1:the_clock_1|slave_nativeaddress_d1[0] } "NODE_NAME" } }  } 0 0 "Port %1!s! -- assigned as a global for destination node %2!s! -- routed using non-global resources" 0 0} { "Info" "IFSAC_FSAC_GLOBAL_CLK_USES_LAB_LINE" "clear std_1c20:inst\|clock_0:the_clock_0\|slave_readdata\[7\] " "Info: Port clear -- assigned as a global for destination node std_1c20:inst\|clock_0:the_clock_0\|slave_readdata\[7\] -- routed using non-global resources" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { std_1c20:inst|clock_0:the_clock_0|slave_readdata[7] } "NODE_NAME" } } { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "std_1c20:inst\|clock_0:the_clock_0\|slave_readdata\[7\]" } } } } { "clock_0.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/clock_0.vhd" 1027 -1 0 } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { std_1c20:inst|clock_0:the_clock_0|slave_readdata[7] } "NODE_NAME" } }  } 0 0 "Port %1!s! -- assigned as a global for destination node %2!s! -- routed using non-global resources" 0 0} { "Info" "IFSAC_FSAC_GLOBAL_CLK_USES_LAB_LINE" "clear std_1c20:inst\|clock_1:the_clock_1\|slave_readdata\[9\] " "Info: Port clear -- assigned as a global for destination node std_1c20:inst\|clock_1:the_clock_1\|slave_readdata\[9\] -- routed using non-global resources" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { std_1c20:inst|clock_1:the_clock_1|slave_readdata[9] } "NODE_NAME" } } { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "std_1c20:inst\|clock_1:the_clock_1\|slave_readdata\[9\]" } } } } { "clock_1.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/clock_1.vhd" 1027 -1 0 } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { std_1c20:inst|clock_1:the_clock_1|slave_readdata[9] } "NODE_NAME" } }  } 0 0 "Port %1!s! -- assigned as a global for destination node %2!s! -- routed using non-global resources" 0 0} { "Info" "IFSAC_FSAC_GLOBAL_CLK_USES_LAB_LINE" "clear std_1c20:inst\|clock_0:the_clock_0\|slave_readdata\[10\] " "Info: Port clear -- assigned as a global for destination node std_1c20:inst\|clock_0:the_clock_0\|slave_readdata\[10\] -- routed using non-global resources" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { std_1c20:inst|clock_0:the_clock_0|slave_readdata[10] } "NODE_NAME" } } { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "std_1c20:inst\|clock_0:the_clock_0\|slave_readdata\[10\]" } } } } { "clock_0.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/clock_0.vhd" 1027 -1 0 } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { std_1c20:inst|clock_0:the_clock_0|slave_readdata[10] } "NODE_NAME" } }  } 0 0 "Port %1!s! -- assigned as a global for destination node %2!s! -- routed using non-global resources" 0 0} { "Info" "IFSAC_FSAC_GLOBAL_CLK_USES_LAB_LINE" "clear std_1c20:inst\|jtag_uart:the_jtag_uart\|alt_jtag_atlantic:jtag_uart_alt_jtag_atlantic\|t_pause~reg0 " "Info: Port clear -- assigned as a global for destination node std_1c20:inst\|jtag_uart:the_jtag_uart\|alt_jtag_atlantic:jtag_uart_alt_jtag_atlantic\|t_pause~reg0 -- routed using non-global resources" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { std_1c20:inst|jtag_uart:the_jtag_uart|alt_jtag_atlantic:jtag_uart_alt_jtag_atlantic|t_pause~reg0 } "NODE_NAME" } } { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "std_1c20:inst\|jtag_uart:the_jtag_uart\|alt_jtag_atlantic:jtag_uart_alt_jtag_atlantic\|t_pause~reg0" } } } } { "../../../../quartus60/libraries/megafunctions/alt_jtag_atlantic.v" "" { Text "D:/ALTERA/quartus60/libraries/megafunctions/alt_jtag_atlantic.v" 420 -1 0 } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { std_1c20:inst|jtag_uart:the_jtag_uart|alt_jtag_atlantic:jtag_uart_alt_jtag_atlantic|t_pause~reg0 } "NODE_NAME" } }  } 0 0 "Port %1!s! -- assigned as a global for destination node %2!s! -- routed using non-global resources" 0 0} { "Info" "IFSAC_FSAC_GLOBAL_CLK_USES_LAB_LINE" "clear std_1c20:inst\|clock_1:the_clock_1\|slave_readdata\[1\] " "Info: Port clear -- assigned as a global for destination node std_1c20:inst\|clock_1:the_clock_1\|slave_readdata\[1\] -- routed using non-global resources" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { std_1c20:inst|clock_1:the_clock_1|slave_readdata[1] } "NODE_NAME" } } { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "std_1c20:inst\|clock_1:the_clock_1\|slave_readdata\[1\]" } } } } { "clock_1.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/clock_1.vhd" 1027 -1 0 } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { std_1c20:inst|clock_1:the_clock_1|slave_readdata[1] } "NODE_NAME" } }  } 0 0 "Port %1!s! -- assigned as a global for destination node %2!s! -- routed using non-global resources" 0 0} { "Info" "IFSAC_FSAC_GLOBAL_CLK_USES_LAB_LINE" "clear std_1c20:inst\|jtag_uart:the_jtag_uart\|alt_jtag_atlantic:jtag_uart_alt_jtag_atlantic\|jupdate2 " "Info: Port clear -- assigned as a global for destination node std_1c20:inst\|jtag_uart:the_jtag_uart\|alt_jtag_atlantic:jtag_uart_alt_jtag_atlantic\|jupdate2 -- routed using non-global resources" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { std_1c20:inst|jtag_uart:the_jtag_uart|alt_jtag_atlantic:jtag_uart_alt_jtag_atlantic|jupdate2 } "NODE_NAME" } } { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "std_1c20:inst\|jtag_uart:the_jtag_uart\|alt_jtag_atlantic:jtag_uart_alt_jtag_atlantic\|jupdate2" } } } } { "../../../../quartus60/libraries/megafunctions/alt_jtag_atlantic.v" "" { Text "D:/ALTERA/quartus60/libraries/megafunctions/alt_jtag_atlantic.v" 213 -1 0 } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { std_1c20:inst|jtag_uart:the_jtag_uart|alt_jtag_atlantic:jtag_uart_alt_jtag_atlantic|jupdate2 } "NODE_NAME" } }  } 0 0 "Port %1!s! -- assigned as a global for destination node %2!s! -- routed using non-global resources" 0 0} { "Info" "IFSAC_FSAC_GLOBAL_CLK_USES_LAB_LINE" "clear std_1c20:inst\|clock_0:the_clock_0\|slave_readdata\[9\] " "Info: Port clear -- assigned as a global for destination node std_1c20:inst\|clock_0:the_clock_0\|slave_readdata\[9\] -- routed using non-global resources" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { std_1c20:inst|clock_0:the_clock_0|slave_readdata[9] } "NODE_NAME" } } { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "std_1c20:inst\|clock_0:the_clock_0\|slave_readdata\[9\]" } } } } { "clock_0.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/clock_0.vhd" 1027 -1 0 } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { std_1c20:inst|clock_0:the_clock_0|slave_readdata[9] } "NODE_NAME" } }  } 0 0 "Port %1!s! -- assigned as a global for destination node %2!s! -- routed using non-global resources" 0 0} { "Info" "IFSAC_FSAC_GLOBAL_CLK_USES_LAB_LINE" "clear std_1c20:inst\|clock_0:the_clock_0\|slave_readdata\[1\] " "Info: Port clear -- assigned as a global for destination node std_1c20:inst\|clock_0:the_clock_0\|slave_readdata\[1\] -- routed using non-global resources" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { std_1c20:inst|clock_0:the_clock_0|slave_readdata[1] } "NODE_NAME" } } { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "std_1c20:inst\|clock_0:the_clock_0\|slave_readdata\[1\]" } } } } { "clock_0.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/clock_0.vhd" 1027 -1 0 } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { std_1c20:inst|clock_0:the_clock_0|slave_readdata[1] } "NODE_NAME" } }  } 0 0 "Port %1!s! -- assigned as a global for destination node %2!s! -- routed using non-global resources" 0 0} { "Info" "IFSAC_FSAC_GLOBAL_CLK_USES_LAB_LINE" "clear std_1c20:inst\|clock_1:the_clock_1\|slave_readdata\[10\] " "Info: Port clear -- assigned as a global for destination node std_1c20:inst\|clock_1:the_clock_1\|slave_readdata\[10\] -- routed using non-global resources" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { std_1c20:inst|clock_1:the_clock_1|slave_readdata[10] } "NODE_NAME" } } { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "std_1c20:inst\|clock_1:the_clock_1\|slave_readdata\[10\]" } } } } { "clock_1.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/clock_1.vhd" 1027 -1 0 } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { std_1c20:inst|clock_1:the_clock_1|slave_readdata[10] } "NODE_NAME" } }  } 0 0 "Port %1!s! -- assigned as a global for destination node %2!s! -- routed using non-global resources" 0 0} { "Info" "IFSAC_FSAC_GLOBAL_CLK_USES_LAB_LINE" "clear std_1c20:inst\|jtag_uart:the_jtag_uart\|fifo_wr " "Info: Port clear -- assigned as a global for destination node std_1c20:inst\|jtag_uart:the_jtag_uart\|fifo_wr -- routed using non-global resources" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { std_1c20:inst|jtag_uart:the_jtag_uart|fifo_wr } "NODE_NAME" } } { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "std_1c20:inst\|jtag_uart:the_jtag_uart\|fifo_wr" } } } } { "jtag_uart.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/jtag_uart.vhd" 1162 -1 0 } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { std_1c20:inst|jtag_uart:the_jtag_uart|fifo_wr } "NODE_NAME" } }  } 0 0 "Port %1!s! -- assigned as a global for destination node %2!s! -- routed using non-global resources" 0 0} { "Info" "IFSAC_FSAC_GLOBAL_CLK_USES_LAB_LINE" "clear std_1c20:inst\|clock_0:the_clock_0\|slave_readdata\[13\] " "Info: Port clear -- assigned as a global for destination node std_1c20:inst\|clock_0:the_clock_0\|slave_readdata\[13\] -- routed using non-global resources" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { std_1c20:inst|clock_0:the_clock_0|slave_readdata[13] } "NODE_NAME" } } { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "std_1c20:inst\|clock_0:the_clock_0\|slave_readdata\[13\]" } } } } { "clock_0.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/clock_0.vhd" 1027 -1 0 } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { std_1c20:inst|clock_0:the_clock_0|slave_readdata[13] } "NODE_NAME" } }  } 0 0 "Port %1!s! -- assigned as a global for destination node %2!s! -- routed using non-global resources" 0 0} { "Info" "IFSAC_FSAC_GLOBAL_CLK_USES_LAB_LINE" "clear std_1c20:inst\|cpu_data_master_arbitrator:the_cpu_data_master\|registered_cpu_data_master_readdata\[13\] " "Info: Port clear -- assigned as a global for destination node std_1c20:inst\|cpu_data_master_arbitrator:the_cpu_data_master\|registered_cpu_data_master_readdata\[13\] -- routed using non-global resources" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|registered_cpu_data_master_readdata[13] } "NODE_NAME" } } { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "std_1c20:inst\|cpu_data_master_arbitrator:the_cpu_data_master\|registered_cpu_data_master_readdata\[13\]" } } } } { "std_1c20.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/std_1c20.vhd" 1927 -1 0 } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|registered_cpu_data_master_readdata[13] } "NODE_NAME" } }  } 0 0 "Port %1!s! -- assigned as a global for destination node %2!s! -- routed using non-global resources" 0 0} { "Info" "IFSAC_FSAC_GLOBAL_CLK_USES_LAB_LINE" "clear std_1c20:inst\|clock_1:the_clock_1\|slave_readdata\[13\] " "Info: Port clear -- assigned as a global for destination node std_1c20:inst\|clock_1:the_clock_1\|slave_readdata\[13\] -- routed using non-global resources" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { std_1c20:inst|clock_1:the_clock_1|slave_readdata[13] } "NODE_NAME" } } { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "std_1c20:inst\|clock_1:the_clock_1\|slave_readdata\[13\]" } } } } { "clock_1.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/clock_1.vhd" 1027 -1 0 } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { std_1c20:inst|clock_1:the_clock_1|slave_readdata[13] } "NODE_NAME" } }  } 0 0 "Port %1!s! -- assigned as a global for destination node %2!s! -- routed using non-global resources" 0 0} { "Info" "IFSAC_FSAC_GLOBAL_CLK_USES_LAB_LINE" "clear std_1c20:inst\|clock_1:the_clock_1\|slave_readdata\[7\] " "Info: Port clear -- assigned as a global for destination node std_1c20:inst\|clock_1:the_clock_1\|slave_readdata\[7\] -- routed using non-global resources" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { std_1c20:inst|clock_1:the_clock_1|slave_readdata[7] } "NODE_NAME" } } { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "std_1c20:inst\|clock_1:the_clock_1\|slave_readdata\[7\]" } } } } { "clock_1.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/clock_1.vhd" 1027 -1 0 } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { std_1c20:inst|clock_1:the_clock_1|slave_readdata[7] } "NODE_NAME" } }  } 0 0 "Port %1!s! -- assigned as a global for destination node %2!s! -- routed using non-global resources" 0 0} { "Info" "IFSAC_FSAC_GLOBAL_CLK_USES_LAB_LINE" "clear std_1c20:inst\|clock_0:the_clock_0\|slave_nativeaddress_d1\[0\] " "Info: Port clear -- assigned as a global for destination node std_1c20:inst\|clock_0:the_clock_0\|slave_nativeaddress_d1\[0\] -- routed using non-global resources" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { std_1c20:inst|clock_0:the_clock_0|slave_nativeaddress_d1[0] } "NODE_NAME" } } { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "std_1c20:inst\|clock_0:the_clock_0\|slave_nativeaddress_d1\[0\]" } } } } { "clock_0.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/clock_0.vhd" 1087 -1 0 } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { std_1c20:inst|clock_0:the_clock_0|slave_nativeaddress_d1[0] } "NODE_NAME" } }  } 0 0 "Port %1!s! -- assigned as a global for destination node %2!s! -- routed using non-global resources" 0 0} { "Info" "IFSAC_FSAC_GLOBAL_CLK_USES_LAB_LINE" "clear std_1c20:inst\|jtag_uart:the_jtag_uart\|woverflow " "Info: Port clear -- assigned as a global for destination node std_1c20:inst\|jtag_uart:the_jtag_uart\|woverflow -- routed using non-global resources" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { std_1c20:inst|jtag_uart:the_jtag_uart|woverflow } "NODE_NAME" } } { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "std_1c20:inst\|jtag_uart:the_jtag_uart\|woverflow" } } } } { "jtag_uart.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/jtag_uart.vhd" 1187 -1 0 } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { std_1c20:inst|jtag_uart:the_jtag_uart|woverflow } "NODE_NAME" } }  } 0 0 "Port %1!s! -- assigned as a global for destination node %2!s! -- routed using non-global resources" 0 0} { "Info" "IFSAC_FSAC_GLOBAL_CLK_USES_LAB_LINE" "clear std_1c20:inst\|high_res_timer:the_high_res_timer\|readdata\[5\] " "Info: Port clear -- assigned as a global for destination node std_1c20:inst\|high_res_timer:the_high_res_timer\|readdata\[5\] -- routed using non-global resources" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { std_1c20:inst|high_res_timer:the_high_res_timer|readdata[5] } "NODE_NAME" } } { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "std_1c20:inst\|high_res_timer:the_high_res_timer\|readdata\[5\]" } } } } { "high_res_timer.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/high_res_timer.vhd" 159 -1 0 } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { std_1c20:inst|high_res_timer:the_high_res_timer|readdata[5] } "NODE_NAME" } }  } 0 0 "Port %1!s! -- assigned as a global for destination node %2!s! -- routed using non-global resources" 0 0} { "Info" "IFSAC_FSAC_GLOBAL_CLK_USES_LAB_LINE" "clear std_1c20:inst\|high_res_timer:the_high_res_timer\|period_h_register\[6\]~2503 " "Info: Port clear -- assigned as a global for destination node std_1c20:inst\|high_res_timer:the_high_res_timer\|period_h_register\[6\]~2503 -- routed using non-global resources" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { std_1c20:inst|high_res_timer:the_high_res_timer|period_h_register[6]~2503 } "NODE_NAME" } } { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "std_1c20:inst\|high_res_timer:the_high_res_timer\|period_h_register\[6\]~2503" } } } } { "high_res_timer.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/high_res_timer.vhd" 185 -1 0 } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { std_1c20:inst|high_res_timer:the_high_res_timer|period_h_register[6]~2503 } "NODE_NAME" } }  } 0 0 "Port %1!s! -- assigned as a global for destination node %2!s! -- routed using non-global resources" 0 0} { "Info" "IFSAC_FSAC_GLOBAL_CLK_USES_LAB_LINE" "clear std_1c20:inst\|high_res_timer:the_high_res_timer\|period_l_register\[6\]~2508 " "Info: Port clear -- assigned as a global for destination node std_1c20:inst\|high_res_timer:the_high_res_timer\|period_l_register\[6\]~2508 -- routed using non-global resources" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { std_1c20:inst|high_res_timer:the_high_res_timer|period_l_register[6]~2508 } "NODE_NAME" } } { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "std_1c20:inst\|high_res_timer:the_high_res_timer\|period_l_register\[6\]~2508" } } } } { "high_res_timer.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/high_res_timer.vhd" 173 -1 0 } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { std_1c20:inst|high_res_timer:the_high_res_timer|period_l_register[6]~2508 } "NODE_NAME" } }  } 0 0 "Port %1!s! -- assigned as a global for destination node %2!s! -- routed using non-global resources" 0 0} { "Info" "IFSAC_FSAC_GLOBAL_CLK_USES_LAB_LINE" "clear std_1c20:inst\|high_res_timer:the_high_res_timer\|period_l_register\[5\]~2512 " "Info: Port clear -- assigned as a global for destination node std_1c20:inst\|high_res_timer:the_high_res_timer\|period_l_register\[5\]~2512 -- routed using non-global resources" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { std_1c20:inst|high_res_timer:the_high_res_timer|period_l_register[5]~2512 } "NODE_NAME" } } { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "std_1c20:inst\|high_res_timer:the_high_res_timer\|period_l_register\[5\]~2512" } } } } { "high_res_timer.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/high_res_timer.vhd" 173 -1 0 } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { std_1c20:inst|high_res_timer:the_high_res_timer|period_l_register[5]~2512 } "NODE_NAME" } }  } 0 0 "Port %1!s! -- assigned as a global for destination node %2!s! -- routed using non-global resources" 0 0} { "Info" "IFSAC_FSAC_GLOBAL_CLK_USES_LAB_LINE" "clear std_1c20:inst\|high_res_timer:the_high_res_timer\|period_h_register\[5\]~2504 " "Info: Port clear -- assigned as a global for destination node std_1c20:inst\|high_res_timer:the_high_res_timer\|period_h_register\[5\]~2504 -- routed using non-global resources" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { std_1c20:inst|high_res_timer:the_high_res_timer|period_h_register[5]~2504 } "NODE_NAME" } } { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "std_1c20:inst\|high_res_timer:the_high_res_timer\|period_h_register\[5\]~2504" } } } } { "high_res_timer.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/high_res_timer.vhd" 185 -1 0 } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { std_1c20:inst|high_res_timer:the_high_res_timer|period_h_register[5]~2504 } "NODE_NAME" } }  } 0 0 "Port %1!s! -- assigned as a global for destination node %2!s! -- routed using non-global resources" 0 0} { "Info" "IFSAC_FSAC_GLOBAL_CLK_USES_LAB_LINE" "clear std_1c20:inst\|high_res_timer:the_high_res_timer\|readdata\[6\] " "Info: Port clear -- assigned as a global for destination node std_1c20:inst\|high_res_timer:the_high_res_timer\|readdata\[6\] -- routed using non-global resources" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { std_1c20:inst|high_res_timer:the_high_res_timer|readdata[6] } "NODE_NAME" } } { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "std_1c20:inst\|high_res_timer:the_high_res_timer\|readdata\[6\]" } } } } { "high_res_timer.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/high_res_timer.vhd" 159 -1 0 } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { std_1c20:inst|high_res_timer:the_high_res_timer|readdata[6] } "NODE_NAME" } }  } 0 0 "Port %1!s! -- assigned as a global for destination node %2!s! -- routed using non-global resources" 0 0} { "Info" "IFSAC_FSAC_GLOBAL_CLK_USES_LAB_LINE" "clear std_1c20:inst\|clock_1:the_clock_1\|slave_writedata_d1\[5\] " "Info: Port clear -- assigned as a global for destination node std_1c20:inst\|clock_1:the_clock_1\|slave_writedata_d1\[5\] -- routed using non-global resources" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { std_1c20:inst|clock_1:the_clock_1|slave_writedata_d1[5] } "NODE_NAME" } } { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "std_1c20:inst\|clock_1:the_clock_1\|slave_writedata_d1\[5\]" } } } } { "clock_1.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/clock_1.vhd" 1039 -1 0 } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { std_1c20:inst|clock_1:the_clock_1|slave_writedata_d1[5] } "NODE_NAME" } }  } 0 0 "Port %1!s! -- assigned as a global for destination node %2!s! -- routed using non-global resources" 0 0} { "Info" "IFSAC_FSAC_GLOBAL_CLK_USES_LAB_LINE" "clear std_1c20:inst\|clock_1:the_clock_1\|clock_1_master_write_done_sync_module:clock_1_master_write_done_sync\|data_in_d1 " "Info: Port clear -- assigned as a global for destination node std_1c20:inst\|clock_1:the_clock_1\|clock_1_master_write_done_sync_module:clock_1_master_write_done_sync\|data_in_d1 -- routed using non-global resources" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { std_1c20:inst|clock_1:the_clock_1|clock_1_master_write_done_sync_module:clock_1_master_write_done_sync|data_in_d1 } "NODE_NAME" } } { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "std_1c20:inst\|clock_1:the_clock_1\|clock_1_master_write_done_sync_module:clock_1_master_write_done_sync\|data_in_d1" } } } } { "clock_1.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/clock_1.vhd" 102 -1 0 } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { std_1c20:inst|clock_1:the_clock_1|clock_1_master_write_done_sync_module:clock_1_master_write_done_sync|data_in_d1 } "NODE_NAME" } }  } 0 0 "Port %1!s! -- assigned as a global for destination node %2!s! -- routed using non-global resources" 0 0} { "Info" "IFSAC_FSAC_GLOBAL_CLK_USES_LAB_LINE" "clear std_1c20:inst\|clock_0:the_clock_0\|slave_writedata_d1\[5\] " "Info: Port clear -- assigned as a global for destination node std_1c20:inst\|clock_0:the_clock_0\|slave_writedata_d1\[5\] -- routed using non-global resources" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { std_1c20:inst|clock_0:the_clock_0|slave_writedata_d1[5] } "NODE_NAME" } } { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "std_1c20:inst\|clock_0:the_clock_0\|slave_writedata_d1\[5\]" } } } } { "clock_0.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/clock_0.vhd" 1039 -1 0 } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { std_1c20:inst|clock_0:the_clock_0|slave_writedata_d1[5] } "NODE_NAME" } }  } 0 0 "Port %1!s! -- assigned as a global for destination node %2!s! -- routed using non-global resources" 0 0} { "Info" "IFSAC_FSAC_GLOBAL_CLK_USES_LAB_LINE" "clear std_1c20:inst\|clock_0:the_clock_0\|slave_writedata_d1\[6\] " "Info: Port clear -- assigned as a global for destination node std_1c20:inst\|clock_0:the_clock_0\|slave_writedata_d1\[6\] -- routed using non-global resources" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { std_1c20:inst|clock_0:the_clock_0|slave_writedata_d1[6] } "NODE_NAME" } } { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "std_1c20:inst\|clock_0:the_clock_0\|slave_writedata_d1\[6\]" } } } } { "clock_0.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/clock_0.vhd" 1039 -1 0 } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { std_1c20:inst|clock_0:the_clock_0|slave_writedata_d1[6] } "NODE_NAME" } }  } 0 0 "Port %1!s! -- assigned as a global for destination node %2!s! -- routed using non-global resources" 0 0} { "Info" "IFSAC_FSAC_GLOBAL_CLK_USES_LAB_LINE" "clear std_1c20:inst\|clock_1:the_clock_1\|slave_writedata_d1\[6\] " "Info: Port clear -- assigned as a global for destination node std_1c20:inst\|clock_1:the_clock_1\|slave_writedata_d1\[6\] -- routed using non-global resources" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { std_1c20:inst|clock_1:the_clock_1|slave_writedata_d1[6] } "NODE_NAME" } } { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "std_1c20:inst\|clock_1:the_clock_1\|slave_writedata_d1\[6\]" } } } } { "clock_1.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/clock_1.vhd" 1039 -1 0 } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { std_1c20:inst|clock_1:the_clock_1|slave_writedata_d1[6] } "NODE_NAME" } }  } 0 0 "Port %1!s! -- assigned as a global for destination node %2!s! -- routed using non-global resources" 0 0} { "Info" "IFSAC_FSAC_GLOBAL_CLK_USES_LAB_LINE" "clear std_1c20:inst\|clock_0:the_clock_0\|clock_0_master_read_done_sync_module:clock_0_master_read_done_sync\|data_in_d1 " "Info: Port clear -- assigned as a global for destination node std_1c20:inst\|clock_0:the_clock_0\|clock_0_master_read_done_sync_module:clock_0_master_read_done_sync\|data_in_d1 -- routed using non-global resources" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { std_1c20:inst|clock_0:the_clock_0|clock_0_master_read_done_sync_module:clock_0_master_read_done_sync|data_in_d1 } "NODE_NAME" } } { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "std_1c20:inst\|clock_0:the_clock_0\|clock_0_master_read_done_sync_module:clock_0_master_read_done_sync\|data_in_d1" } } } } { "clock_0.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/clock_0.vhd" 40 -1 0 } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { std_1c20:inst|clock_0:the_clock_0|clock_0_master_read_done_sync_module:clock_0_master_read_done_sync|data_in_d1 } "NODE_NAME" } }  } 0 0 "Port %1!s! -- assigned as a global for destination node %2!s! -- routed using non-global resources" 0 0} { "Info" "IFSAC_FSAC_GLOBAL_CLK_USES_LAB_LINE" "clear std_1c20:inst\|clock_0:the_clock_0\|clock_0_master_write_done_sync_module:clock_0_master_write_done_sync\|data_in_d1 " "Info: Port clear -- assigned as a global for destination node std_1c20:inst\|clock_0:the_clock_0\|clock_0_master_write_done_sync_module:clock_0_master_write_done_sync\|data_in_d1 -- routed using non-global resources" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { std_1c20:inst|clock_0:the_clock_0|clock_0_master_write_done_sync_module:clock_0_master_write_done_sync|data_in_d1 } "NODE_NAME" } } { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "std_1c20:inst\|clock_0:the_clock_0\|clock_0_master_write_done_sync_module:clock_0_master_write_done_sync\|data_in_d1" } } } } { "clock_0.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/clock_0.vhd" 102 -1 0 } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { std_1c20:inst|clock_0:the_clock_0|clock_0_master_write_done_sync_module:clock_0_master_write_done_sync|data_in_d1 } "NODE_NAME" } }  } 0 0 "Port %1!s! -- assigned as a global for destination node %2!s! -- routed using non-global resources" 0 0} { "Info" "IFSAC_FSAC_GLOBAL_CLK_USES_LAB_LINE" "clear std_1c20:inst\|clock_0:the_clock_0\|slave_writedata_d1\[7\] " "Info: Port clear -- assigned as a global for destination node std_1c20:inst\|clock_0:the_clock_0\|slave_writedata_d1\[7\] -- routed using non-global resources" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { std_1c20:inst|clock_0:the_clock_0|slave_writedata_d1[7] } "NODE_NAME" } } { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "std_1c20:inst\|clock_0:the_clock_0\|slave_writedata_d1\[7\]" } } } } { "clock_0.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/clock_0.vhd" 1039 -1 0 } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { std_1c20:inst|clock_0:the_clock_0|slave_writedata_d1[7] } "NODE_NAME" } }  } 0 0 "Port %1!s! -- assigned as a global for destination node %2!s! -- routed using non-global resources" 0 0} { "Info" "IFSAC_FSAC_GLOBAL_CLK_USES_LAB_LINE" "clear std_1c20:inst\|clock_0:the_clock_0\|slave_writedata_d1\[12\] " "Info: Port clear -- assigned as a global for destination node std_1c20:inst\|clock_0:the_clock_0\|slave_writedata_d1\[12\] -- routed using non-global resources" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { std_1c20:inst|clock_0:the_clock_0|slave_writedata_d1[12] } "NODE_NAME" } } { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "std_1c20:inst\|clock_0:the_clock_0\|slave_writedata_d1\[12\]" } } } } { "clock_0.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/clock_0.vhd" 1039 -1 0 } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { std_1c20:inst|clock_0:the_clock_0|slave_writedata_d1[12] } "NODE_NAME" } }  } 0 0 "Port %1!s! -- assigned as a global for destination node %2!s! -- routed using non-global resources" 0 0} { "Info" "IFSAC_FSAC_GLOBAL_CLK_USES_LAB_LINE" "clear std_1c20:inst\|clock_1:the_clock_1\|slave_writedata_d1\[12\] " "Info: Port clear -- assigned as a global for destination node std_1c20:inst\|clock_1:the_clock_1\|slave_writedata_d1\[12\] -- routed using non-global resources" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { std_1c20:inst|clock_1:the_clock_1|slave_writedata_d1[12] } "NODE_NAME" } } { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "std_1c20:inst\|clock_1:the_clock_1\|slave_writedata_d1\[12\]" } } } } { "clock_1.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/clock_1.vhd" 1039 -1 0 } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { std_1c20:inst|clock_1:the_clock_1|slave_writedata_d1[12] } "NODE_NAME" } }  } 0 0 "Port %1!s! -- assigned as a global for destination node %2!s! -- routed using non-global resources" 0 0} { "Info" "IFSAC_FSAC_GLOBAL_CLK_USES_LAB_LINE" "clear std_1c20:inst\|clock_0:the_clock_0\|clock_0_slave_FSM:slave_FSM\|internal_slave_read_request " "Info: Port clear -- assigned as a global for destination node std_1c20:inst\|clock_0:the_clock_0\|clock_0_slave_FSM:slave_FSM\|internal_slave_read_request -- routed using non-global resources" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { std_1c20:inst|clock_0:the_clock_0|clock_0_slave_FSM:slave_FSM|internal_slave_read_request } "NODE_NAME" } } { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "std_1c20:inst\|clock_0:the_clock_0\|clock_0_slave_FSM:slave_FSM\|internal_slave_read_request" } } } } { "clock_0.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/clock_0.vhd" 228 -1 0 } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { std_1c20:inst|clock_0:the_clock_0|clock_0_slave_FSM:slave_FSM|internal_slave_read_request } "NODE_NAME" } }  } 0 0 "Port %1!s! -- assigned as a global for destination node %2!s! -- routed using non-global resources" 0 0} { "Info" "IFSAC_FSAC_GLOBAL_CLK_USES_LAB_LINE_EXCEEDS_OUTPUT_LIMIT" "86 50 " "Info: Total of 86 global destination nodes routed using non-global resources -- displayed first 50" {  } {  } 0 0 "Total of %1!d! global destination nodes routed using non-global resources -- displayed first %2!d!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { std_1c20:inst|std_1c20_reset_sysclk2_domain_synch_module:std_1c20_reset_sysclk2_domain_synch|data_out } "NODE_NAME" } } { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "std_1c20:inst\|std_1c20_reset_sysclk2_domain_synch_module:std_1c20_reset_sysclk2_domain_synch\|data_out" } } } } { "std_1c20.vhd" "" { Text "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/std_1c20.vhd" 7300 -1 0 } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { std_1c20:inst|std_1c20_reset_sysclk2_domain_synch_module:std_1c20_reset_sysclk2_domain_synch|data_out } "NODE_NAME" } }  } 0 0 "Node %1!s! uses non-global routing resources to route signals to global destination nodes" 0 0}
{ "Warning" "WFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN" "3 " "Warning: Following 3 pins have nothing, GND, or VCC driving datain port -- changes to this connectivity may change fitting results" { { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "ENET_ADS_N GND " "Info: Pin ENET_ADS_N has GND driving its datain port" {  } { { "standard.bdf" "" { Schematic "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/standard.bdf" { { 504 1392 1568 520 "ENET_ADS_N" "" } } } } { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "ENET_ADS_N" } } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { ENET_ADS_N } "NODE_NAME" } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { ENET_ADS_N } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "ENET_AEN GND " "Info: Pin ENET_AEN has GND driving its datain port" {  } { { "standard.bdf" "" { Schematic "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/standard.bdf" { { 520 1392 1568 536 "ENET_AEN" "" } } } } { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "ENET_AEN" } } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { ENET_AEN } "NODE_NAME" } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { ENET_AEN } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "zs_cke_from_the_sdram VCC " "Info: Pin zs_cke_from_the_sdram has VCC driving its datain port" {  } { { "standard.bdf" "" { Schematic "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/standard.bdf" { { 1112 1312 1488 1128 "zs_cke_from_the_sdram" "" } } } } { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "zs_cke_from_the_sdram" } } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { zs_cke_from_the_sdram } "NODE_NAME" } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { zs_cke_from_the_sdram } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0}  } {  } 0 0 "Following %1!d! pins have nothing, GND, or VCC driving datain port -- changes to this connectivity may change fitting results" 0 0}
{ "Info" "IFIOMGR_ALL_OUTPUT_ENABLE_GROUPS" "" "Info: Following groups of pins have the same output enable" { { "Info" "IFIOMGR_SAME_OUTPUT_ENABLE_GROUP" "std_1c20:inst\|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave\|d1_in_a_write_cycle~COMB_OUT " "Info: Following pins have the same output enable: std_1c20:inst\|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave\|d1_in_a_write_cycle~COMB_OUT" { { "Info" "IFIOMGR_SAME_OUTPUT_ENABLE_GROUP_SUB" "bidirectional ext_ram_bus_data\[31\] LVTTL " "Info: Type bidirectional pin ext_ram_bus_data\[31\] uses the LVTTL I/O standard" {  } { { "standard.bdf" "" { Schematic "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/standard.bdf" { { 744 1312 1488 760 "ext_ram_bus_data\[31..0\]" "" } } } } { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "ext_ram_bus_data\[31\]" } } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { ext_ram_bus_data[31] } "NODE_NAME" } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { ext_ram_bus_data[31] } "NODE_NAME" } }  } 0 0 "Type %1!s! pin %2!s! uses the %3!s! I/O standard" 0 0} { "Info" "IFIOMGR_SAME_OUTPUT_ENABLE_GROUP_SUB" "bidirectional ext_ram_bus_data\[8\] LVTTL " "Info: Type bidirectional pin ext_ram_bus_data\[8\] uses the LVTTL I/O standard" {  } { { "standard.bdf" "" { Schematic "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/standard.bdf" { { 744 1312 1488 760 "ext_ram_bus_data\[31..0\]" "" } } } } { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "ext_ram_bus_data\[8\]" } } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { ext_ram_bus_data[8] } "NODE_NAME" } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { ext_ram_bus_data[8] } "NODE_NAME" } }  } 0 0 "Type %1!s! pin %2!s! uses the %3!s! I/O standard" 0 0} { "Info" "IFIOMGR_SAME_OUTPUT_ENABLE_GROUP_SUB" "bidirectional ext_ram_bus_data\[17\] LVTTL " "Info: Type bidirectional pin ext_ram_bus_data\[17\] uses the LVTTL I/O standard" {  } { { "standard.bdf" "" { Schematic "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/standard.bdf" { { 744 1312 1488 760 "ext_ram_bus_data\[31..0\]" "" } } } } { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "ext_ram_bus_data\[17\]" } } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { ext_ram_bus_data[17] } "NODE_NAME" } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { ext_ram_bus_data[17] } "NODE_NAME" } }  } 0 0 "Type %1!s! pin %2!s! uses the %3!s! I/O standard" 0 0} { "Info" "IFIOMGR_SAME_OUTPUT_ENABLE_GROUP_SUB" "bidirectional ext_ram_bus_data\[26\] LVTTL " "Info: Type bidirectional pin ext_ram_bus_data\[26\] uses the LVTTL I/O standard" {  } { { "standard.bdf" "" { Schematic "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/standard.bdf" { { 744 1312 1488 760 "ext_ram_bus_data\[31..0\]" "" } } } } { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "ext_ram_bus_data\[26\]" } } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { ext_ram_bus_data[26] } "NODE_NAME" } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { ext_ram_bus_data[26] } "NODE_NAME" } }  } 0 0 "Type %1!s! pin %2!s! uses the %3!s! I/O standard" 0 0} { "Info" "IFIOMGR_SAME_OUTPUT_ENABLE_GROUP_SUB" "bidirectional ext_ram_bus_data\[10\] LVTTL " "Info: Type bidirectional pin ext_ram_bus_data\[10\] uses the LVTTL I/O standard" {  } { { "standard.bdf" "" { Schematic "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/standard.bdf" { { 744 1312 1488 760 "ext_ram_bus_data\[31..0\]" "" } } } } { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "ext_ram_bus_data\[10\]" } } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { ext_ram_bus_data[10] } "NODE_NAME" } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { ext_ram_bus_data[10] } "NODE_NAME" } }  } 0 0 "Type %1!s! pin %2!s! uses the %3!s! I/O standard" 0 0} { "Info" "IFIOMGR_SAME_OUTPUT_ENABLE_GROUP_SUB" "bidirectional ext_ram_bus_data\[19\] LVTTL " "Info: Type bidirectional pin ext_ram_bus_data\[19\] uses the LVTTL I/O standard" {  } { { "standard.bdf" "" { Schematic "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/standard.bdf" { { 744 1312 1488 760 "ext_ram_bus_data\[31..0\]" "" } } } } { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "ext_ram_bus_data\[19\]" } } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { ext_ram_bus_data[19] } "NODE_NAME" } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { ext_ram_bus_data[19] } "NODE_NAME" } }  } 0 0 "Type %1!s! pin %2!s! uses the %3!s! I/O standard" 0 0} { "Info" "IFIOMGR_SAME_OUTPUT_ENABLE_GROUP_SUB" "bidirectional ext_ram_bus_data\[3\] LVTTL " "Info: Type bidirectional pin ext_ram_bus_data\[3\] uses the LVTTL I/O standard" {  } { { "standard.bdf" "" { Schematic "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/standard.bdf" { { 744 1312 1488 760 "ext_ram_bus_data\[31..0\]" "" } } } } { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "ext_ram_bus_data\[3\]" } } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { ext_ram_bus_data[3] } "NODE_NAME" } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { ext_ram_bus_data[3] } "NODE_NAME" } }  } 0 0 "Type %1!s! pin %2!s! uses the %3!s! I/O standard" 0 0} { "Info" "IFIOMGR_SAME_OUTPUT_ENABLE_GROUP_SUB" "bidirectional ext_ram_bus_data\[28\] LVTTL " "Info: Type bidirectional pin ext_ram_bus_data\[28\] uses the LVTTL I/O standard" {  } { { "standard.bdf" "" { Schematic "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/standard.bdf" { { 744 1312 1488 760 "ext_ram_bus_data\[31..0\]" "" } } } } { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "ext_ram_bus_data\[28\]" } } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { ext_ram_bus_data[28] } "NODE_NAME" } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { ext_ram_bus_data[28] } "NODE_NAME" } }  } 0 0 "Type %1!s! pin %2!s! uses the %3!s! I/O standard" 0 0} { "Info" "IFIOMGR_SAME_OUTPUT_ENABLE_GROUP_SUB" "bidirectional ext_ram_bus_data\[12\] LVTTL " "Info: Type bidirectional pin ext_ram_bus_data\[12\] uses the LVTTL I/O standard" {  } { { "standard.bdf" "" { Schematic "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/standard.bdf" { { 744 1312 1488 760 "ext_ram_bus_data\[31..0\]" "" } } } } { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "ext_ram_bus_data\[12\]" } } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { ext_ram_bus_data[12] } "NODE_NAME" } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { ext_ram_bus_data[12] } "NODE_NAME" } }  } 0 0 "Type %1!s! pin %2!s! uses the %3!s! I/O standard" 0 0} { "Info" "IFIOMGR_SAME_OUTPUT_ENABLE_GROUP_SUB" "bidirectional ext_ram_bus_data\[21\] LVTTL " "Info: Type bidirectional pin ext_ram_bus_data\[21\] uses the LVTTL I/O standard" {  } { { "standard.bdf" "" { Schematic "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/standard.bdf" { { 744 1312 1488 760 "ext_ram_bus_data\[31..0\]" "" } } } } { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "ext_ram_bus_data\[21\]" } } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { ext_ram_bus_data[21] } "NODE_NAME" } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { ext_ram_bus_data[21] } "NODE_NAME" } }  } 0 0 "Type %1!s! pin %2!s! uses the %3!s! I/O standard" 0 0} { "Info" "IFIOMGR_SAME_OUTPUT_ENABLE_GROUP_SUB" "bidirectional ext_ram_bus_data\[5\] LVTTL " "Info: Type bidirectional pin ext_ram_bus_data\[5\] uses the LVTTL I/O standard" {  } { { "standard.bdf" "" { Schematic "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/standard.bdf" { { 744 1312 1488 760 "ext_ram_bus_data\[31..0\]" "" } } } } { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "ext_ram_bus_data\[5\]" } } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { ext_ram_bus_data[5] } "NODE_NAME" } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { ext_ram_bus_data[5] } "NODE_NAME" } }  } 0 0 "Type %1!s! pin %2!s! uses the %3!s! I/O standard" 0 0} { "Info" "IFIOMGR_SAME_OUTPUT_ENABLE_GROUP_SUB" "bidirectional ext_ram_bus_data\[30\] LVTTL " "Info: Type bidirectional pin ext_ram_bus_data\[30\] uses the LVTTL I/O standard" {  } { { "standard.bdf" "" { Schematic "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/standard.bdf" { { 744 1312 1488 760 "ext_ram_bus_data\[31..0\]" "" } } } } { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "ext_ram_bus_data\[30\]" } } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { ext_ram_bus_data[30] } "NODE_NAME" } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { ext_ram_bus_data[30] } "NODE_NAME" } }  } 0 0 "Type %1!s! pin %2!s! uses the %3!s! I/O standard" 0 0} { "Info" "IFIOMGR_SAME_OUTPUT_ENABLE_GROUP_SUB" "bidirectional ext_ram_bus_data\[14\] LVTTL " "Info: Type bidirectional pin ext_ram_bus_data\[14\] uses the LVTTL I/O standard" {  } { { "standard.bdf" "" { Schematic "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/standard.bdf" { { 744 1312 1488 760 "ext_ram_bus_data\[31..0\]" "" } } } } { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "ext_ram_bus_data\[14\]" } } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { ext_ram_bus_data[14] } "NODE_NAME" } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { ext_ram_bus_data[14] } "NODE_NAME" } }  } 0 0 "Type %1!s! pin %2!s! uses the %3!s! I/O standard" 0 0} { "Info" "IFIOMGR_SAME_OUTPUT_ENABLE_GROUP_SUB" "bidirectional ext_ram_bus_data\[23\] LVTTL " "Info: Type bidirectional pin ext_ram_bus_data\[23\] uses the LVTTL I/O standard" {  } { { "standard.bdf" "" { Schematic "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/standard.bdf" { { 744 1312 1488 760 "ext_ram_bus_data\[31..0\]" "" } } } } { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "ext_ram_bus_data\[23\]" } } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { ext_ram_bus_data[23] } "NODE_NAME" } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { ext_ram_bus_data[23] } "NODE_NAME" } }  } 0 0 "Type %1!s! pin %2!s! uses the %3!s! I/O standard" 0 0} { "Info" "IFIOMGR_SAME_OUTPUT_ENABLE_GROUP_SUB" "bidirectional ext_ram_bus_data\[7\] LVTTL " "Info: Type bidirectional pin ext_ram_bus_data\[7\] uses the LVTTL I/O standard" {  } { { "standard.bdf" "" { Schematic "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/standard.bdf" { { 744 1312 1488 760 "ext_ram_bus_data\[31..0\]" "" } } } } { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "ext_ram_bus_data\[7\]" } } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { ext_ram_bus_data[7] } "NODE_NAME" } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { ext_ram_bus_data[7] } "NODE_NAME" } }  } 0 0 "Type %1!s! pin %2!s! uses the %3!s! I/O standard" 0 0} { "Info" "IFIOMGR_SAME_OUTPUT_ENABLE_GROUP_SUB" "bidirectional ext_ram_bus_data\[16\] LVTTL " "Info: Type bidirectional pin ext_ram_bus_data\[16\] uses the LVTTL I/O standard" {  } { { "standard.bdf" "" { Schematic "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/standard.bdf" { { 744 1312 1488 760 "ext_ram_bus_data\[31..0\]" "" } } } } { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "ext_ram_bus_data\[16\]" } } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { ext_ram_bus_data[16] } "NODE_NAME" } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { ext_ram_bus_data[16] } "NODE_NAME" } }  } 0 0 "Type %1!s! pin %2!s! uses the %3!s! I/O standard" 0 0} { "Info" "IFIOMGR_SAME_OUTPUT_ENABLE_GROUP_SUB" "bidirectional ext_ram_bus_data\[0\] LVTTL " "Info: Type bidirectional pin ext_ram_bus_data\[0\] uses the LVTTL I/O standard" {  } { { "standard.bdf" "" { Schematic "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/standard.bdf" { { 744 1312 1488 760 "ext_ram_bus_data\[31..0\]" "" } } } } { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "ext_ram_bus_data\[0\]" } } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { ext_ram_bus_data[0] } "NODE_NAME" } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { ext_ram_bus_data[0] } "NODE_NAME" } }  } 0 0 "Type %1!s! pin %2!s! uses the %3!s! I/O standard" 0 0} { "Info" "IFIOMGR_SAME_OUTPUT_ENABLE_GROUP_SUB" "bidirectional ext_ram_bus_data\[25\] LVTTL " "Info: Type bidirectional pin ext_ram_bus_data\[25\] uses the LVTTL I/O standard" {  } { { "standard.bdf" "" { Schematic "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/standard.bdf" { { 744 1312 1488 760 "ext_ram_bus_data\[31..0\]" "" } } } } { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "ext_ram_bus_data\[25\]" } } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { ext_ram_bus_data[25] } "NODE_NAME" } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { ext_ram_bus_data[25] } "NODE_NAME" } }  } 0 0 "Type %1!s! pin %2!s! uses the %3!s! I/O standard" 0 0} { "Info" "IFIOMGR_SAME_OUTPUT_ENABLE_GROUP_SUB" "bidirectional ext_ram_bus_data\[9\] LVTTL " "Info: Type bidirectional pin ext_ram_bus_data\[9\] uses the LVTTL I/O standard" {  } { { "standard.bdf" "" { Schematic "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/standard.bdf" { { 744 1312 1488 760 "ext_ram_bus_data\[31..0\]" "" } } } } { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "ext_ram_bus_data\[9\]" } } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { ext_ram_bus_data[9] } "NODE_NAME" } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { ext_ram_bus_data[9] } "NODE_NAME" } }  } 0 0 "Type %1!s! pin %2!s! uses the %3!s! I/O standard" 0 0} { "Info" "IFIOMGR_SAME_OUTPUT_ENABLE_GROUP_SUB" "bidirectional ext_ram_bus_data\[18\] LVTTL " "Info: Type bidirectional pin ext_ram_bus_data\[18\] uses the LVTTL I/O standard" {  } { { "standard.bdf" "" { Schematic "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/standard.bdf" { { 744 1312 1488 760 "ext_ram_bus_data\[31..0\]" "" } } } } { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "ext_ram_bus_data\[18\]" } } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { ext_ram_bus_data[18] } "NODE_NAME" } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { ext_ram_bus_data[18] } "NODE_NAME" } }  } 0 0 "Type %1!s! pin %2!s! uses the %3!s! I/O standard" 0 0} { "Info" "IFIOMGR_SAME_OUTPUT_ENABLE_GROUP_SUB" "bidirectional ext_ram_bus_data\[2\] LVTTL " "Info: Type bidirectional pin ext_ram_bus_data\[2\] uses the LVTTL I/O standard" {  } { { "standard.bdf" "" { Schematic "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/standard.bdf" { { 744 1312 1488 760 "ext_ram_bus_data\[31..0\]" "" } } } } { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "ext_ram_bus_data\[2\]" } } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { ext_ram_bus_data[2] } "NODE_NAME" } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { ext_ram_bus_data[2] } "NODE_NAME" } }  } 0 0 "Type %1!s! pin %2!s! uses the %3!s! I/O standard" 0 0} { "Info" "IFIOMGR_SAME_OUTPUT_ENABLE_GROUP_SUB" "bidirectional ext_ram_bus_data\[27\] LVTTL " "Info: Type bidirectional pin ext_ram_bus_data\[27\] uses the LVTTL I/O standard" {  } { { "standard.bdf" "" { Schematic "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/standard.bdf" { { 744 1312 1488 760 "ext_ram_bus_data\[31..0\]" "" } } } } { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "ext_ram_bus_data\[27\]" } } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { ext_ram_bus_data[27] } "NODE_NAME" } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { ext_ram_bus_data[27] } "NODE_NAME" } }  } 0 0 "Type %1!s! pin %2!s! uses the %3!s! I/O standard" 0 0} { "Info" "IFIOMGR_SAME_OUTPUT_ENABLE_GROUP_SUB" "bidirectional ext_ram_bus_data\[11\] LVTTL " "Info: Type bidirectional pin ext_ram_bus_data\[11\] uses the LVTTL I/O standard" {  } { { "standard.bdf" "" { Schematic "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/standard.bdf" { { 744 1312 1488 760 "ext_ram_bus_data\[31..0\]" "" } } } } { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "ext_ram_bus_data\[11\]" } } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { ext_ram_bus_data[11] } "NODE_NAME" } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { ext_ram_bus_data[11] } "NODE_NAME" } }  } 0 0 "Type %1!s! pin %2!s! uses the %3!s! I/O standard" 0 0} { "Info" "IFIOMGR_SAME_OUTPUT_ENABLE_GROUP_SUB" "bidirectional ext_ram_bus_data\[20\] LVTTL " "Info: Type bidirectional pin ext_ram_bus_data\[20\] uses the LVTTL I/O standard" {  } { { "standard.bdf" "" { Schematic "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/standard.bdf" { { 744 1312 1488 760 "ext_ram_bus_data\[31..0\]" "" } } } } { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "ext_ram_bus_data\[20\]" } } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { ext_ram_bus_data[20] } "NODE_NAME" } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { ext_ram_bus_data[20] } "NODE_NAME" } }  } 0 0 "Type %1!s! pin %2!s! uses the %3!s! I/O standard" 0 0} { "Info" "IFIOMGR_SAME_OUTPUT_ENABLE_GROUP_SUB" "bidirectional ext_ram_bus_data\[4\] LVTTL " "Info: Type bidirectional pin ext_ram_bus_data\[4\] uses the LVTTL I/O standard" {  } { { "standard.bdf" "" { Schematic "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/standard.bdf" { { 744 1312 1488 760 "ext_ram_bus_data\[31..0\]" "" } } } } { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "ext_ram_bus_data\[4\]" } } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { ext_ram_bus_data[4] } "NODE_NAME" } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { ext_ram_bus_data[4] } "NODE_NAME" } }  } 0 0 "Type %1!s! pin %2!s! uses the %3!s! I/O standard" 0 0} { "Info" "IFIOMGR_SAME_OUTPUT_ENABLE_GROUP_SUB" "bidirectional ext_ram_bus_data\[29\] LVTTL " "Info: Type bidirectional pin ext_ram_bus_data\[29\] uses the LVTTL I/O standard" {  } { { "standard.bdf" "" { Schematic "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/standard.bdf" { { 744 1312 1488 760 "ext_ram_bus_data\[31..0\]" "" } } } } { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "ext_ram_bus_data\[29\]" } } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { ext_ram_bus_data[29] } "NODE_NAME" } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { ext_ram_bus_data[29] } "NODE_NAME" } }  } 0 0 "Type %1!s! pin %2!s! uses the %3!s! I/O standard" 0 0} { "Info" "IFIOMGR_SAME_OUTPUT_ENABLE_GROUP_SUB" "bidirectional ext_ram_bus_data\[13\] LVTTL " "Info: Type bidirectional pin ext_ram_bus_data\[13\] uses the LVTTL I/O standard" {  } { { "standard.bdf" "" { Schematic "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/standard.bdf" { { 744 1312 1488 760 "ext_ram_bus_data\[31..0\]" "" } } } } { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "ext_ram_bus_data\[13\]" } } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { ext_ram_bus_data[13] } "NODE_NAME" } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { ext_ram_bus_data[13] } "NODE_NAME" } }  } 0 0 "Type %1!s! pin %2!s! uses the %3!s! I/O standard" 0 0} { "Info" "IFIOMGR_SAME_OUTPUT_ENABLE_GROUP_SUB" "bidirectional ext_ram_bus_data\[22\] LVTTL " "Info: Type bidirectional pin ext_ram_bus_data\[22\] uses the LVTTL I/O standard" {  } { { "standard.bdf" "" { Schematic "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/standard.bdf" { { 744 1312 1488 760 "ext_ram_bus_data\[31..0\]" "" } } } } { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "ext_ram_bus_data\[22\]" } } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { ext_ram_bus_data[22] } "NODE_NAME" } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { ext_ram_bus_data[22] } "NODE_NAME" } }  } 0 0 "Type %1!s! pin %2!s! uses the %3!s! I/O standard" 0 0} { "Info" "IFIOMGR_SAME_OUTPUT_ENABLE_GROUP_SUB" "bidirectional ext_ram_bus_data\[6\] LVTTL " "Info: Type bidirectional pin ext_ram_bus_data\[6\] uses the LVTTL I/O standard" {  } { { "standard.bdf" "" { Schematic "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/standard.bdf" { { 744 1312 1488 760 "ext_ram_bus_data\[31..0\]" "" } } } } { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "ext_ram_bus_data\[6\]" } } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { ext_ram_bus_data[6] } "NODE_NAME" } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { ext_ram_bus_data[6] } "NODE_NAME" } }  } 0 0 "Type %1!s! pin %2!s! uses the %3!s! I/O standard" 0 0} { "Info" "IFIOMGR_SAME_OUTPUT_ENABLE_GROUP_SUB" "bidirectional ext_ram_bus_data\[15\] LVTTL " "Info: Type bidirectional pin ext_ram_bus_data\[15\] uses the LVTTL I/O standard" {  } { { "standard.bdf" "" { Schematic "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/standard.bdf" { { 744 1312 1488 760 "ext_ram_bus_data\[31..0\]" "" } } } } { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "ext_ram_bus_data\[15\]" } } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { ext_ram_bus_data[15] } "NODE_NAME" } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { ext_ram_bus_data[15] } "NODE_NAME" } }  } 0 0 "Type %1!s! pin %2!s! uses the %3!s! I/O standard" 0 0} { "Info" "IFIOMGR_SAME_OUTPUT_ENABLE_GROUP_SUB" "bidirectional ext_ram_bus_data\[24\] LVTTL " "Info: Type bidirectional pin ext_ram_bus_data\[24\] uses the LVTTL I/O standard" {  } { { "standard.bdf" "" { Schematic "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/standard.bdf" { { 744 1312 1488 760 "ext_ram_bus_data\[31..0\]" "" } } } } { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "ext_ram_bus_data\[24\]" } } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { ext_ram_bus_data[24] } "NODE_NAME" } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { ext_ram_bus_data[24] } "NODE_NAME" } }  } 0 0 "Type %1!s! pin %2!s! uses the %3!s! I/O standard" 0 0} { "Info" "IFIOMGR_SAME_OUTPUT_ENABLE_GROUP_SUB" "bidirectional ext_ram_bus_data\[1\] LVTTL " "Info: Type bidirectional pin ext_ram_bus_data\[1\] uses the LVTTL I/O standard" {  } { { "standard.bdf" "" { Schematic "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/standard.bdf" { { 744 1312 1488 760 "ext_ram_bus_data\[31..0\]" "" } } } } { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "ext_ram_bus_data\[1\]" } } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { ext_ram_bus_data[1] } "NODE_NAME" } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { ext_ram_bus_data[1] } "NODE_NAME" } }  } 0 0 "Type %1!s! pin %2!s! uses the %3!s! I/O standard" 0 0}  } {  } 0 0 "Following pins have the same output enable: %1!s!" 0 0} { "Info" "IFIOMGR_SAME_OUTPUT_ENABLE_GROUP" "std_1c20:inst\|cpu:the_cpu\|M_alu_result\[2\] (inverted) " "Info: Following pins have the same output enable: std_1c20:inst\|cpu:the_cpu\|M_alu_result\[2\] (inverted)" { { "Info" "IFIOMGR_SAME_OUTPUT_ENABLE_GROUP_SUB" "bidirectional LCD_data_to_and_from_the_lcd_display\[7\] LVTTL " "Info: Type bidirectional pin LCD_data_to_and_from_the_lcd_display\[7\] uses the LVTTL I/O standard" {  } { { "standard.bdf" "" { Schematic "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/standard.bdf" { { 968 1312 1488 984 "LCD_data_to_and_from_the_lcd_display\[7..0\]" "" } } } } { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "LCD_data_to_and_from_the_lcd_display\[7\]" } } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { LCD_data_to_and_from_the_lcd_display[7] } "NODE_NAME" } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { LCD_data_to_and_from_the_lcd_display[7] } "NODE_NAME" } }  } 0 0 "Type %1!s! pin %2!s! uses the %3!s! I/O standard" 0 0} { "Info" "IFIOMGR_SAME_OUTPUT_ENABLE_GROUP_SUB" "bidirectional LCD_data_to_and_from_the_lcd_display\[2\] LVTTL " "Info: Type bidirectional pin LCD_data_to_and_from_the_lcd_display\[2\] uses the LVTTL I/O standard" {  } { { "standard.bdf" "" { Schematic "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/standard.bdf" { { 968 1312 1488 984 "LCD_data_to_and_from_the_lcd_display\[7..0\]" "" } } } } { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "LCD_data_to_and_from_the_lcd_display\[2\]" } } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { LCD_data_to_and_from_the_lcd_display[2] } "NODE_NAME" } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { LCD_data_to_and_from_the_lcd_display[2] } "NODE_NAME" } }  } 0 0 "Type %1!s! pin %2!s! uses the %3!s! I/O standard" 0 0} { "Info" "IFIOMGR_SAME_OUTPUT_ENABLE_GROUP_SUB" "bidirectional LCD_data_to_and_from_the_lcd_display\[4\] LVTTL " "Info: Type bidirectional pin LCD_data_to_and_from_the_lcd_display\[4\] uses the LVTTL I/O standard" {  } { { "standard.bdf" "" { Schematic "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/standard.bdf" { { 968 1312 1488 984 "LCD_data_to_and_from_the_lcd_display\[7..0\]" "" } } } } { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "LCD_data_to_and_from_the_lcd_display\[4\]" } } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { LCD_data_to_and_from_the_lcd_display[4] } "NODE_NAME" } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { LCD_data_to_and_from_the_lcd_display[4] } "NODE_NAME" } }  } 0 0 "Type %1!s! pin %2!s! uses the %3!s! I/O standard" 0 0} { "Info" "IFIOMGR_SAME_OUTPUT_ENABLE_GROUP_SUB" "bidirectional LCD_data_to_and_from_the_lcd_display\[6\] LVTTL " "Info: Type bidirectional pin LCD_data_to_and_from_the_lcd_display\[6\] uses the LVTTL I/O standard" {  } { { "standard.bdf" "" { Schematic "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/standard.bdf" { { 968 1312 1488 984 "LCD_data_to_and_from_the_lcd_display\[7..0\]" "" } } } } { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "LCD_data_to_and_from_the_lcd_display\[6\]" } } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { LCD_data_to_and_from_the_lcd_display[6] } "NODE_NAME" } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { LCD_data_to_and_from_the_lcd_display[6] } "NODE_NAME" } }  } 0 0 "Type %1!s! pin %2!s! uses the %3!s! I/O standard" 0 0} { "Info" "IFIOMGR_SAME_OUTPUT_ENABLE_GROUP_SUB" "bidirectional LCD_data_to_and_from_the_lcd_display\[1\] LVTTL " "Info: Type bidirectional pin LCD_data_to_and_from_the_lcd_display\[1\] uses the LVTTL I/O standard" {  } { { "standard.bdf" "" { Schematic "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/standard.bdf" { { 968 1312 1488 984 "LCD_data_to_and_from_the_lcd_display\[7..0\]" "" } } } } { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "LCD_data_to_and_from_the_lcd_display\[1\]" } } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { LCD_data_to_and_from_the_lcd_display[1] } "NODE_NAME" } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { LCD_data_to_and_from_the_lcd_display[1] } "NODE_NAME" } }  } 0 0 "Type %1!s! pin %2!s! uses the %3!s! I/O standard" 0 0} { "Info" "IFIOMGR_SAME_OUTPUT_ENABLE_GROUP_SUB" "bidirectional LCD_data_to_and_from_the_lcd_display\[3\] LVTTL " "Info: Type bidirectional pin LCD_data_to_and_from_the_lcd_display\[3\] uses the LVTTL I/O standard" {  } { { "standard.bdf" "" { Schematic "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/standard.bdf" { { 968 1312 1488 984 "LCD_data_to_and_from_the_lcd_display\[7..0\]" "" } } } } { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "LCD_data_to_and_from_the_lcd_display\[3\]" } } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { LCD_data_to_and_from_the_lcd_display[3] } "NODE_NAME" } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { LCD_data_to_and_from_the_lcd_display[3] } "NODE_NAME" } }  } 0 0 "Type %1!s! pin %2!s! uses the %3!s! I/O standard" 0 0} { "Info" "IFIOMGR_SAME_OUTPUT_ENABLE_GROUP_SUB" "bidirectional LCD_data_to_and_from_the_lcd_display\[5\] LVTTL " "Info: Type bidirectional pin LCD_data_to_and_from_the_lcd_display\[5\] uses the LVTTL I/O standard" {  } { { "standard.bdf" "" { Schematic "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/standard.bdf" { { 968 1312 1488 984 "LCD_data_to_and_from_the_lcd_display\[7..0\]" "" } } } } { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "LCD_data_to_and_from_the_lcd_display\[5\]" } } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { LCD_data_to_and_from_the_lcd_display[5] } "NODE_NAME" } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { LCD_data_to_and_from_the_lcd_display[5] } "NODE_NAME" } }  } 0 0 "Type %1!s! pin %2!s! uses the %3!s! I/O standard" 0 0} { "Info" "IFIOMGR_SAME_OUTPUT_ENABLE_GROUP_SUB" "bidirectional LCD_data_to_and_from_the_lcd_display\[0\] LVTTL " "Info: Type bidirectional pin LCD_data_to_and_from_the_lcd_display\[0\] uses the LVTTL I/O standard" {  } { { "standard.bdf" "" { Schematic "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/standard.bdf" { { 968 1312 1488 984 "LCD_data_to_and_from_the_lcd_display\[7..0\]" "" } } } } { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "LCD_data_to_and_from_the_lcd_display\[0\]" } } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { LCD_data_to_and_from_the_lcd_display[0] } "NODE_NAME" } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { LCD_data_to_and_from_the_lcd_display[0] } "NODE_NAME" } }  } 0 0 "Type %1!s! pin %2!s! uses the %3!s! I/O standard" 0 0}  } {  } 0 0 "Following pins have the same output enable: %1!s!" 0 0} { "Info" "IFIOMGR_SAME_OUTPUT_ENABLE_GROUP" "std_1c20:inst\|sdram:the_sdram\|oe " "Info: Following pins have the same output enable: std_1c20:inst\|sdram:the_sdram\|oe" { { "Info" "IFIOMGR_SAME_OUTPUT_ENABLE_GROUP_SUB" "bidirectional zs_dq_to_and_from_the_sdram\[7\] LVTTL " "Info: Type bidirectional pin zs_dq_to_and_from_the_sdram\[7\] uses the LVTTL I/O standard" {  } { { "standard.bdf" "" { Schematic "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/standard.bdf" { { 1144 1312 1488 1160 "zs_dq_to_and_from_the_sdram\[31..0\]" "" } } } } { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "zs_dq_to_and_from_the_sdram\[7\]" } } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { zs_dq_to_and_from_the_sdram[7] } "NODE_NAME" } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { zs_dq_to_and_from_the_sdram[7] } "NODE_NAME" } }  } 0 0 "Type %1!s! pin %2!s! uses the %3!s! I/O standard" 0 0} { "Info" "IFIOMGR_SAME_OUTPUT_ENABLE_GROUP_SUB" "bidirectional zs_dq_to_and_from_the_sdram\[16\] LVTTL " "Info: Type bidirectional pin zs_dq_to_and_from_the_sdram\[16\] uses the LVTTL I/O standard" {  } { { "standard.bdf" "" { Schematic "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/standard.bdf" { { 1144 1312 1488 1160 "zs_dq_to_and_from_the_sdram\[31..0\]" "" } } } } { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "zs_dq_to_and_from_the_sdram\[16\]" } } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { zs_dq_to_and_from_the_sdram[16] } "NODE_NAME" } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { zs_dq_to_and_from_the_sdram[16] } "NODE_NAME" } }  } 0 0 "Type %1!s! pin %2!s! uses the %3!s! I/O standard" 0 0} { "Info" "IFIOMGR_SAME_OUTPUT_ENABLE_GROUP_SUB" "bidirectional zs_dq_to_and_from_the_sdram\[25\] LVTTL " "Info: Type bidirectional pin zs_dq_to_and_from_the_sdram\[25\] uses the LVTTL I/O standard" {  } { { "standard.bdf" "" { Schematic "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/standard.bdf" { { 1144 1312 1488 1160 "zs_dq_to_and_from_the_sdram\[31..0\]" "" } } } } { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "zs_dq_to_and_from_the_sdram\[25\]" } } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { zs_dq_to_and_from_the_sdram[25] } "NODE_NAME" } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { zs_dq_to_and_from_the_sdram[25] } "NODE_NAME" } }  } 0 0 "Type %1!s! pin %2!s! uses the %3!s! I/O standard" 0 0} { "Info" "IFIOMGR_SAME_OUTPUT_ENABLE_GROUP_SUB" "bidirectional zs_dq_to_and_from_the_sdram\[18\] LVTTL " "Info: Type bidirectional pin zs_dq_to_and_from_the_sdram\[18\] uses the LVTTL I/O standard" {  } { { "standard.bdf" "" { Schematic "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/standard.bdf" { { 1144 1312 1488 1160 "zs_dq_to_and_from_the_sdram\[31..0\]" "" } } } } { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "zs_dq_to_and_from_the_sdram\[18\]" } } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { zs_dq_to_and_from_the_sdram[18] } "NODE_NAME" } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { zs_dq_to_and_from_the_sdram[18] } "NODE_NAME" } }  } 0 0 "Type %1!s! pin %2!s! uses the %3!s! I/O standard" 0 0} { "Info" "IFIOMGR_SAME_OUTPUT_ENABLE_GROUP_SUB" "bidirectional zs_dq_to_and_from_the_sdram\[2\] LVTTL " "Info: Type bidirectional pin zs_dq_to_and_from_the_sdram\[2\] uses the LVTTL I/O standard" {  } { { "standard.bdf" "" { Schematic "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/standard.bdf" { { 1144 1312 1488 1160 "zs_dq_to_and_from_the_sdram\[31..0\]" "" } } } } { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "zs_dq_to_and_from_the_sdram\[2\]" } } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { zs_dq_to_and_from_the_sdram[2] } "NODE_NAME" } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { zs_dq_to_and_from_the_sdram[2] } "NODE_NAME" } }  } 0 0 "Type %1!s! pin %2!s! uses the %3!s! I/O standard" 0 0} { "Info" "IFIOMGR_SAME_OUTPUT_ENABLE_GROUP_SUB" "bidirectional zs_dq_to_and_from_the_sdram\[27\] LVTTL " "Info: Type bidirectional pin zs_dq_to_and_from_the_sdram\[27\] uses the LVTTL I/O standard" {  } { { "standard.bdf" "" { Schematic "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/standard.bdf" { { 1144 1312 1488 1160 "zs_dq_to_and_from_the_sdram\[31..0\]" "" } } } } { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "zs_dq_to_and_from_the_sdram\[27\]" } } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { zs_dq_to_and_from_the_sdram[27] } "NODE_NAME" } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { zs_dq_to_and_from_the_sdram[27] } "NODE_NAME" } }  } 0 0 "Type %1!s! pin %2!s! uses the %3!s! I/O standard" 0 0} { "Info" "IFIOMGR_SAME_OUTPUT_ENABLE_GROUP_SUB" "bidirectional zs_dq_to_and_from_the_sdram\[11\] LVTTL " "Info: Type bidirectional pin zs_dq_to_and_from_the_sdram\[11\] uses the LVTTL I/O standard" {  } { { "standard.bdf" "" { Schematic "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/standard.bdf" { { 1144 1312 1488 1160 "zs_dq_to_and_from_the_sdram\[31..0\]" "" } } } } { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "zs_dq_to_and_from_the_sdram\[11\]" } } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { zs_dq_to_and_from_the_sdram[11] } "NODE_NAME" } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { zs_dq_to_and_from_the_sdram[11] } "NODE_NAME" } }  } 0 0 "Type %1!s! pin %2!s! uses the %3!s! I/O standard" 0 0} { "Info" "IFIOMGR_SAME_OUTPUT_ENABLE_GROUP_SUB" "bidirectional zs_dq_to_and_from_the_sdram\[20\] LVTTL " "Info: Type bidirectional pin zs_dq_to_and_from_the_sdram\[20\] uses the LVTTL I/O standard" {  } { { "standard.bdf" "" { Schematic "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/standard.bdf" { { 1144 1312 1488 1160 "zs_dq_to_and_from_the_sdram\[31..0\]" "" } } } } { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "zs_dq_to_and_from_the_sdram\[20\]" } } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { zs_dq_to_and_from_the_sdram[20] } "NODE_NAME" } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { zs_dq_to_and_from_the_sdram[20] } "NODE_NAME" } }  } 0 0 "Type %1!s! pin %2!s! uses the %3!s! I/O standard" 0 0} { "Info" "IFIOMGR_SAME_OUTPUT_ENABLE_GROUP_SUB" "bidirectional zs_dq_to_and_from_the_sdram\[4\] LVTTL " "Info: Type bidirectional pin zs_dq_to_and_from_the_sdram\[4\] uses the LVTTL I/O standard" {  } { { "standard.bdf" "" { Schematic "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/standard.bdf" { { 1144 1312 1488 1160 "zs_dq_to_and_from_the_sdram\[31..0\]" "" } } } } { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "zs_dq_to_and_from_the_sdram\[4\]" } } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { zs_dq_to_and_from_the_sdram[4] } "NODE_NAME" } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { zs_dq_to_and_from_the_sdram[4] } "NODE_NAME" } }  } 0 0 "Type %1!s! pin %2!s! uses the %3!s! I/O standard" 0 0} { "Info" "IFIOMGR_SAME_OUTPUT_ENABLE_GROUP_SUB" "bidirectional zs_dq_to_and_from_the_sdram\[29\] LVTTL " "Info: Type bidirectional pin zs_dq_to_and_from_the_sdram\[29\] uses the LVTTL I/O standard" {  } { { "standard.bdf" "" { Schematic "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/standard.bdf" { { 1144 1312 1488 1160 "zs_dq_to_and_from_the_sdram\[31..0\]" "" } } } } { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "zs_dq_to_and_from_the_sdram\[29\]" } } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { zs_dq_to_and_from_the_sdram[29] } "NODE_NAME" } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { zs_dq_to_and_from_the_sdram[29] } "NODE_NAME" } }  } 0 0 "Type %1!s! pin %2!s! uses the %3!s! I/O standard" 0 0} { "Info" "IFIOMGR_SAME_OUTPUT_ENABLE_GROUP_SUB" "bidirectional zs_dq_to_and_from_the_sdram\[13\] LVTTL " "Info: Type bidirectional pin zs_dq_to_and_from_the_sdram\[13\] uses the LVTTL I/O standard" {  } { { "standard.bdf" "" { Schematic "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/standard.bdf" { { 1144 1312 1488 1160 "zs_dq_to_and_from_the_sdram\[31..0\]" "" } } } } { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "zs_dq_to_and_from_the_sdram\[13\]" } } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { zs_dq_to_and_from_the_sdram[13] } "NODE_NAME" } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { zs_dq_to_and_from_the_sdram[13] } "NODE_NAME" } }  } 0 0 "Type %1!s! pin %2!s! uses the %3!s! I/O standard" 0 0} { "Info" "IFIOMGR_SAME_OUTPUT_ENABLE_GROUP_SUB" "bidirectional zs_dq_to_and_from_the_sdram\[22\] LVTTL " "Info: Type bidirectional pin zs_dq_to_and_from_the_sdram\[22\] uses the LVTTL I/O standard" {  } { { "standard.bdf" "" { Schematic "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/standard.bdf" { { 1144 1312 1488 1160 "zs_dq_to_and_from_the_sdram\[31..0\]" "" } } } } { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "zs_dq_to_and_from_the_sdram\[22\]" } } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { zs_dq_to_and_from_the_sdram[22] } "NODE_NAME" } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { zs_dq_to_and_from_the_sdram[22] } "NODE_NAME" } }  } 0 0 "Type %1!s! pin %2!s! uses the %3!s! I/O standard" 0 0} { "Info" "IFIOMGR_SAME_OUTPUT_ENABLE_GROUP_SUB" "bidirectional zs_dq_to_and_from_the_sdram\[6\] LVTTL " "Info: Type bidirectional pin zs_dq_to_and_from_the_sdram\[6\] uses the LVTTL I/O standard" {  } { { "standard.bdf" "" { Schematic "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/standard.bdf" { { 1144 1312 1488 1160 "zs_dq_to_and_from_the_sdram\[31..0\]" "" } } } } { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "zs_dq_to_and_from_the_sdram\[6\]" } } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { zs_dq_to_and_from_the_sdram[6] } "NODE_NAME" } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { zs_dq_to_and_from_the_sdram[6] } "NODE_NAME" } }  } 0 0 "Type %1!s! pin %2!s! uses the %3!s! I/O standard" 0 0} { "Info" "IFIOMGR_SAME_OUTPUT_ENABLE_GROUP_SUB" "bidirectional zs_dq_to_and_from_the_sdram\[31\] LVTTL " "Info: Type bidirectional pin zs_dq_to_and_from_the_sdram\[31\] uses the LVTTL I/O standard" {  } { { "standard.bdf" "" { Schematic "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/standard.bdf" { { 1144 1312 1488 1160 "zs_dq_to_and_from_the_sdram\[31..0\]" "" } } } } { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "zs_dq_to_and_from_the_sdram\[31\]" } } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { zs_dq_to_and_from_the_sdram[31] } "NODE_NAME" } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { zs_dq_to_and_from_the_sdram[31] } "NODE_NAME" } }  } 0 0 "Type %1!s! pin %2!s! uses the %3!s! I/O standard" 0 0} { "Info" "IFIOMGR_SAME_OUTPUT_ENABLE_GROUP_SUB" "bidirectional zs_dq_to_and_from_the_sdram\[15\] LVTTL " "Info: Type bidirectional pin zs_dq_to_and_from_the_sdram\[15\] uses the LVTTL I/O standard" {  } { { "standard.bdf" "" { Schematic "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/standard.bdf" { { 1144 1312 1488 1160 "zs_dq_to_and_from_the_sdram\[31..0\]" "" } } } } { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "zs_dq_to_and_from_the_sdram\[15\]" } } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { zs_dq_to_and_from_the_sdram[15] } "NODE_NAME" } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { zs_dq_to_and_from_the_sdram[15] } "NODE_NAME" } }  } 0 0 "Type %1!s! pin %2!s! uses the %3!s! I/O standard" 0 0} { "Info" "IFIOMGR_SAME_OUTPUT_ENABLE_GROUP_SUB" "bidirectional zs_dq_to_and_from_the_sdram\[24\] LVTTL " "Info: Type bidirectional pin zs_dq_to_and_from_the_sdram\[24\] uses the LVTTL I/O standard" {  } { { "standard.bdf" "" { Schematic "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/standard.bdf" { { 1144 1312 1488 1160 "zs_dq_to_and_from_the_sdram\[31..0\]" "" } } } } { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "zs_dq_to_and_from_the_sdram\[24\]" } } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { zs_dq_to_and_from_the_sdram[24] } "NODE_NAME" } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { zs_dq_to_and_from_the_sdram[24] } "NODE_NAME" } }  } 0 0 "Type %1!s! pin %2!s! uses the %3!s! I/O standard" 0 0} { "Info" "IFIOMGR_SAME_OUTPUT_ENABLE_GROUP_SUB" "bidirectional zs_dq_to_and_from_the_sdram\[8\] LVTTL " "Info: Type bidirectional pin zs_dq_to_and_from_the_sdram\[8\] uses the LVTTL I/O standard" {  } { { "standard.bdf" "" { Schematic "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/standard.bdf" { { 1144 1312 1488 1160 "zs_dq_to_and_from_the_sdram\[31..0\]" "" } } } } { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "zs_dq_to_and_from_the_sdram\[8\]" } } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { zs_dq_to_and_from_the_sdram[8] } "NODE_NAME" } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { zs_dq_to_and_from_the_sdram[8] } "NODE_NAME" } }  } 0 0 "Type %1!s! pin %2!s! uses the %3!s! I/O standard" 0 0} { "Info" "IFIOMGR_SAME_OUTPUT_ENABLE_GROUP_SUB" "bidirectional zs_dq_to_and_from_the_sdram\[17\] LVTTL " "Info: Type bidirectional pin zs_dq_to_and_from_the_sdram\[17\] uses the LVTTL I/O standard" {  } { { "standard.bdf" "" { Schematic "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/standard.bdf" { { 1144 1312 1488 1160 "zs_dq_to_and_from_the_sdram\[31..0\]" "" } } } } { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "zs_dq_to_and_from_the_sdram\[17\]" } } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { zs_dq_to_and_from_the_sdram[17] } "NODE_NAME" } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { zs_dq_to_and_from_the_sdram[17] } "NODE_NAME" } }  } 0 0 "Type %1!s! pin %2!s! uses the %3!s! I/O standard" 0 0} { "Info" "IFIOMGR_SAME_OUTPUT_ENABLE_GROUP_SUB" "bidirectional zs_dq_to_and_from_the_sdram\[1\] LVTTL " "Info: Type bidirectional pin zs_dq_to_and_from_the_sdram\[1\] uses the LVTTL I/O standard" {  } { { "standard.bdf" "" { Schematic "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/standard.bdf" { { 1144 1312 1488 1160 "zs_dq_to_and_from_the_sdram\[31..0\]" "" } } } } { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "zs_dq_to_and_from_the_sdram\[1\]" } } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { zs_dq_to_and_from_the_sdram[1] } "NODE_NAME" } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { zs_dq_to_and_from_the_sdram[1] } "NODE_NAME" } }  } 0 0 "Type %1!s! pin %2!s! uses the %3!s! I/O standard" 0 0} { "Info" "IFIOMGR_SAME_OUTPUT_ENABLE_GROUP_SUB" "bidirectional zs_dq_to_and_from_the_sdram\[26\] LVTTL " "Info: Type bidirectional pin zs_dq_to_and_from_the_sdram\[26\] uses the LVTTL I/O standard" {  } { { "standard.bdf" "" { Schematic "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/standard.bdf" { { 1144 1312 1488 1160 "zs_dq_to_and_from_the_sdram\[31..0\]" "" } } } } { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "zs_dq_to_and_from_the_sdram\[26\]" } } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { zs_dq_to_and_from_the_sdram[26] } "NODE_NAME" } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { zs_dq_to_and_from_the_sdram[26] } "NODE_NAME" } }  } 0 0 "Type %1!s! pin %2!s! uses the %3!s! I/O standard" 0 0} { "Info" "IFIOMGR_SAME_OUTPUT_ENABLE_GROUP_SUB" "bidirectional zs_dq_to_and_from_the_sdram\[10\] LVTTL " "Info: Type bidirectional pin zs_dq_to_and_from_the_sdram\[10\] uses the LVTTL I/O standard" {  } { { "standard.bdf" "" { Schematic "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/standard.bdf" { { 1144 1312 1488 1160 "zs_dq_to_and_from_the_sdram\[31..0\]" "" } } } } { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "zs_dq_to_and_from_the_sdram\[10\]" } } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { zs_dq_to_and_from_the_sdram[10] } "NODE_NAME" } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { zs_dq_to_and_from_the_sdram[10] } "NODE_NAME" } }  } 0 0 "Type %1!s! pin %2!s! uses the %3!s! I/O standard" 0 0} { "Info" "IFIOMGR_SAME_OUTPUT_ENABLE_GROUP_SUB" "bidirectional zs_dq_to_and_from_the_sdram\[19\] LVTTL " "Info: Type bidirectional pin zs_dq_to_and_from_the_sdram\[19\] uses the LVTTL I/O standard" {  } { { "standard.bdf" "" { Schematic "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/standard.bdf" { { 1144 1312 1488 1160 "zs_dq_to_and_from_the_sdram\[31..0\]" "" } } } } { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "zs_dq_to_and_from_the_sdram\[19\]" } } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { zs_dq_to_and_from_the_sdram[19] } "NODE_NAME" } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { zs_dq_to_and_from_the_sdram[19] } "NODE_NAME" } }  } 0 0 "Type %1!s! pin %2!s! uses the %3!s! I/O standard" 0 0} { "Info" "IFIOMGR_SAME_OUTPUT_ENABLE_GROUP_SUB" "bidirectional zs_dq_to_and_from_the_sdram\[3\] LVTTL " "Info: Type bidirectional pin zs_dq_to_and_from_the_sdram\[3\] uses the LVTTL I/O standard" {  } { { "standard.bdf" "" { Schematic "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/standard.bdf" { { 1144 1312 1488 1160 "zs_dq_to_and_from_the_sdram\[31..0\]" "" } } } } { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "zs_dq_to_and_from_the_sdram\[3\]" } } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { zs_dq_to_and_from_the_sdram[3] } "NODE_NAME" } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { zs_dq_to_and_from_the_sdram[3] } "NODE_NAME" } }  } 0 0 "Type %1!s! pin %2!s! uses the %3!s! I/O standard" 0 0} { "Info" "IFIOMGR_SAME_OUTPUT_ENABLE_GROUP_SUB" "bidirectional zs_dq_to_and_from_the_sdram\[28\] LVTTL " "Info: Type bidirectional pin zs_dq_to_and_from_the_sdram\[28\] uses the LVTTL I/O standard" {  } { { "standard.bdf" "" { Schematic "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/standard.bdf" { { 1144 1312 1488 1160 "zs_dq_to_and_from_the_sdram\[31..0\]" "" } } } } { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "zs_dq_to_and_from_the_sdram\[28\]" } } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { zs_dq_to_and_from_the_sdram[28] } "NODE_NAME" } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { zs_dq_to_and_from_the_sdram[28] } "NODE_NAME" } }  } 0 0 "Type %1!s! pin %2!s! uses the %3!s! I/O standard" 0 0} { "Info" "IFIOMGR_SAME_OUTPUT_ENABLE_GROUP_SUB" "bidirectional zs_dq_to_and_from_the_sdram\[12\] LVTTL " "Info: Type bidirectional pin zs_dq_to_and_from_the_sdram\[12\] uses the LVTTL I/O standard" {  } { { "standard.bdf" "" { Schematic "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/standard.bdf" { { 1144 1312 1488 1160 "zs_dq_to_and_from_the_sdram\[31..0\]" "" } } } } { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "zs_dq_to_and_from_the_sdram\[12\]" } } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { zs_dq_to_and_from_the_sdram[12] } "NODE_NAME" } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { zs_dq_to_and_from_the_sdram[12] } "NODE_NAME" } }  } 0 0 "Type %1!s! pin %2!s! uses the %3!s! I/O standard" 0 0} { "Info" "IFIOMGR_SAME_OUTPUT_ENABLE_GROUP_SUB" "bidirectional zs_dq_to_and_from_the_sdram\[21\] LVTTL " "Info: Type bidirectional pin zs_dq_to_and_from_the_sdram\[21\] uses the LVTTL I/O standard" {  } { { "standard.bdf" "" { Schematic "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/standard.bdf" { { 1144 1312 1488 1160 "zs_dq_to_and_from_the_sdram\[31..0\]" "" } } } } { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "zs_dq_to_and_from_the_sdram\[21\]" } } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { zs_dq_to_and_from_the_sdram[21] } "NODE_NAME" } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { zs_dq_to_and_from_the_sdram[21] } "NODE_NAME" } }  } 0 0 "Type %1!s! pin %2!s! uses the %3!s! I/O standard" 0 0} { "Info" "IFIOMGR_SAME_OUTPUT_ENABLE_GROUP_SUB" "bidirectional zs_dq_to_and_from_the_sdram\[5\] LVTTL " "Info: Type bidirectional pin zs_dq_to_and_from_the_sdram\[5\] uses the LVTTL I/O standard" {  } { { "standard.bdf" "" { Schematic "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/standard.bdf" { { 1144 1312 1488 1160 "zs_dq_to_and_from_the_sdram\[31..0\]" "" } } } } { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "zs_dq_to_and_from_the_sdram\[5\]" } } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { zs_dq_to_and_from_the_sdram[5] } "NODE_NAME" } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { zs_dq_to_and_from_the_sdram[5] } "NODE_NAME" } }  } 0 0 "Type %1!s! pin %2!s! uses the %3!s! I/O standard" 0 0} { "Info" "IFIOMGR_SAME_OUTPUT_ENABLE_GROUP_SUB" "bidirectional zs_dq_to_and_from_the_sdram\[30\] LVTTL " "Info: Type bidirectional pin zs_dq_to_and_from_the_sdram\[30\] uses the LVTTL I/O standard" {  } { { "standard.bdf" "" { Schematic "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/standard.bdf" { { 1144 1312 1488 1160 "zs_dq_to_and_from_the_sdram\[31..0\]" "" } } } } { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "zs_dq_to_and_from_the_sdram\[30\]" } } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { zs_dq_to_and_from_the_sdram[30] } "NODE_NAME" } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { zs_dq_to_and_from_the_sdram[30] } "NODE_NAME" } }  } 0 0 "Type %1!s! pin %2!s! uses the %3!s! I/O standard" 0 0} { "Info" "IFIOMGR_SAME_OUTPUT_ENABLE_GROUP_SUB" "bidirectional zs_dq_to_and_from_the_sdram\[14\] LVTTL " "Info: Type bidirectional pin zs_dq_to_and_from_the_sdram\[14\] uses the LVTTL I/O standard" {  } { { "standard.bdf" "" { Schematic "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/standard.bdf" { { 1144 1312 1488 1160 "zs_dq_to_and_from_the_sdram\[31..0\]" "" } } } } { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "zs_dq_to_and_from_the_sdram\[14\]" } } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { zs_dq_to_and_from_the_sdram[14] } "NODE_NAME" } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { zs_dq_to_and_from_the_sdram[14] } "NODE_NAME" } }  } 0 0 "Type %1!s! pin %2!s! uses the %3!s! I/O standard" 0 0} { "Info" "IFIOMGR_SAME_OUTPUT_ENABLE_GROUP_SUB" "bidirectional zs_dq_to_and_from_the_sdram\[23\] LVTTL " "Info: Type bidirectional pin zs_dq_to_and_from_the_sdram\[23\] uses the LVTTL I/O standard" {  } { { "standard.bdf" "" { Schematic "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/standard.bdf" { { 1144 1312 1488 1160 "zs_dq_to_and_from_the_sdram\[31..0\]" "" } } } } { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "zs_dq_to_and_from_the_sdram\[23\]" } } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { zs_dq_to_and_from_the_sdram[23] } "NODE_NAME" } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { zs_dq_to_and_from_the_sdram[23] } "NODE_NAME" } }  } 0 0 "Type %1!s! pin %2!s! uses the %3!s! I/O standard" 0 0} { "Info" "IFIOMGR_SAME_OUTPUT_ENABLE_GROUP_SUB" "bidirectional zs_dq_to_and_from_the_sdram\[0\] LVTTL " "Info: Type bidirectional pin zs_dq_to_and_from_the_sdram\[0\] uses the LVTTL I/O standard" {  } { { "standard.bdf" "" { Schematic "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/standard.bdf" { { 1144 1312 1488 1160 "zs_dq_to_and_from_the_sdram\[31..0\]" "" } } } } { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "zs_dq_to_and_from_the_sdram\[0\]" } } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { zs_dq_to_and_from_the_sdram[0] } "NODE_NAME" } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { zs_dq_to_and_from_the_sdram[0] } "NODE_NAME" } }  } 0 0 "Type %1!s! pin %2!s! uses the %3!s! I/O standard" 0 0} { "Info" "IFIOMGR_SAME_OUTPUT_ENABLE_GROUP_SUB" "bidirectional zs_dq_to_and_from_the_sdram\[9\] LVTTL " "Info: Type bidirectional pin zs_dq_to_and_from_the_sdram\[9\] uses the LVTTL I/O standard" {  } { { "standard.bdf" "" { Schematic "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/standard.bdf" { { 1144 1312 1488 1160 "zs_dq_to_and_from_the_sdram\[31..0\]" "" } } } } { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "zs_dq_to_and_from_the_sdram\[9\]" } } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { zs_dq_to_and_from_the_sdram[9] } "NODE_NAME" } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { zs_dq_to_and_from_the_sdram[9] } "NODE_NAME" } }  } 0 0 "Type %1!s! pin %2!s! uses the %3!s! I/O standard" 0 0}  } {  } 0 0 "Following pins have the same output enable: %1!s!" 0 0} { "Info" "IFIOMGR_SAME_OUTPUT_ENABLE_GROUP" "std_1c20:inst\|reconfig_request_pio:the_reconfig_request_pio\|data_dir " "Info: Following pins have the same output enable: std_1c20:inst\|reconfig_request_pio:the_reconfig_request_pio\|data_dir" { { "Info" "IFIOMGR_SAME_OUTPUT_ENABLE_GROUP_SUB" "bidirectional bidir_port_to_and_from_the_reconfig_request_pio LVTTL " "Info: Type bidirectional pin bidir_port_to_and_from_the_reconfig_request_pio uses the LVTTL I/O standard" {  } { { "standard.bdf" "" { Schematic "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/standard.bdf" { { 1032 1312 1488 1048 "bidir_port_to_and_from_the_reconfig_request_pio" "" } } } } { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "bidir_port_to_and_from_the_reconfig_request_pio" } } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { bidir_port_to_and_from_the_reconfig_request_pio } "NODE_NAME" } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { bidir_port_to_and_from_the_reconfig_request_pio } "NODE_NAME" } }  } 0 0 "Type %1!s! pin %2!s! uses the %3!s! I/O standard" 0 0}  } {  } 0 0 "Following pins have the same output enable: %1!s!" 0 0}  } {  } 0 0 "Following groups of pins have the same output enable" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 137 s Quartus II " "Info: Quartus II Fitter was successful. 0 errors, 137 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Thu Oct 06 16:12:53 2011 " "Info: Processing ended: Thu Oct 06 16:12:53 2011" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:09:38 " "Info: Elapsed time: 00:09:38" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}
{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/standard.fit.smsg " "Info: Generated suppressed messages file D:/ALTERA/examples/vhdl/niosII_cyclone_1c20/standard/standard.fit.smsg" {  } {  } 0 0 "Generated suppressed messages file %1!s!" 0 0}
