--------------------------------------------------------------------------------------
Timing Analyzer Summary
--------------------------------------------------------------------------------------

Type           : Worst-case tsu
Slack          : N/A
Required Time  : None
Actual Time    : 11.615 ns
From           : LCD_data_to_and_from_the_lcd_display[6]
To             : std_1c20:inst|cpu:the_cpu|d_readdata_d1[6]~135
From Clock     : --
To Clock       : PLD_CLKFB
Failed Paths   : 0

Type           : Worst-case tco
Slack          : N/A
Required Time  : None
Actual Time    : 17.787 ns
From           : std_1c20:inst|cpu:the_cpu|M_alu_result[8]~681
To             : LCD_E_from_the_lcd_display
From Clock     : PLD_CLKFB
To Clock       : --
Failed Paths   : 0

Type           : Worst-case tpd
Slack          : N/A
Required Time  : None
Actual Time    : 1.879 ns
From           : altera_internal_jtag~TDO
To             : altera_reserved_tdo
From Clock     : --
To Clock       : --
Failed Paths   : 0

Type           : Worst-case th
Slack          : N/A
Required Time  : None
Actual Time    : 3.205 ns
From           : altera_internal_jtag~TMSUTAP
To             : sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state[9]
From Clock     : --
To Clock       : altera_internal_jtag~TCKUTAP
Failed Paths   : 0

Type           : Clock Setup: 'std_1c20:inst|sdram_pll:the_sdram_pll|altpllsdram_pll:the_pll|altpll:altpll_component|_clk0'
Slack          : 3.378 ns
Required Time  : 50.00 MHz ( period = 20.000 ns )
Actual Time    : 60.16 MHz ( period = 16.622 ns )
From           : std_1c20:inst|cpu:the_cpu|M_alu_result[22]~424
To             : std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|read_n_to_the_ext_ram
From Clock     : std_1c20:inst|sdram_pll:the_sdram_pll|altpllsdram_pll:the_pll|altpll:altpll_component|_clk0
To Clock       : std_1c20:inst|sdram_pll:the_sdram_pll|altpllsdram_pll:the_pll|altpll:altpll_component|_clk0
Failed Paths   : 0

Type           : Clock Setup: 'PLD_CLKFB'
Slack          : 15.862 ns
Required Time  : 50.00 MHz ( period = 20.000 ns )
Actual Time    : 241.66 MHz ( period = 4.138 ns )
From           : std_1c20:inst|clock_0:the_clock_0|clock_0_master_FSM:master_FSM|master_state[2]
To             : std_1c20:inst|sdram_pll:the_sdram_pll|control_reg_out[14]
From Clock     : PLD_CLKFB
To Clock       : PLD_CLKFB
Failed Paths   : 0

Type           : Clock Setup: 'PLD_CLOCKINPUT[1]'
Slack          : 16.088 ns
Required Time  : 50.00 MHz ( period = 20.000 ns )
Actual Time    : 255.62 MHz ( period = 3.912 ns )
From           : std_1c20:inst|clock_1:the_clock_1|clock_1_master_FSM:master_FSM|master_state[2]
To             : std_1c20:inst|connector_pll:the_connector_pll|control_reg_out[13]
From Clock     : PLD_CLOCKINPUT[1]
To Clock       : PLD_CLOCKINPUT[1]
Failed Paths   : 0

Type           : Clock Setup: 'altera_internal_jtag~TCKUTAP'
Slack          : N/A
Required Time  : None
Actual Time    : 76.65 MHz ( period = 13.046 ns )
From           : sld_hub:sld_hub_inst|jtag_debug_mode_usr1
To             : std_1c20:inst|jtag_uart:the_jtag_uart|alt_jtag_atlantic:jtag_uart_alt_jtag_atlantic|jupdate
From Clock     : altera_internal_jtag~TCKUTAP
To Clock       : altera_internal_jtag~TCKUTAP
Failed Paths   : 0

Type           : Clock Hold: 'std_1c20:inst|sdram_pll:the_sdram_pll|altpllsdram_pll:the_pll|altpll:altpll_component|_clk0'
Slack          : 0.727 ns
Required Time  : 50.00 MHz ( period = 20.000 ns )
Actual Time    : N/A
From           : std_1c20:inst|jtag_uart:the_jtag_uart|r_val
To             : std_1c20:inst|jtag_uart:the_jtag_uart|r_val
From Clock     : std_1c20:inst|sdram_pll:the_sdram_pll|altpllsdram_pll:the_pll|altpll:altpll_component|_clk0
To Clock       : std_1c20:inst|sdram_pll:the_sdram_pll|altpllsdram_pll:the_pll|altpll:altpll_component|_clk0
Failed Paths   : 0

Type           : Clock Hold: 'PLD_CLKFB'
Slack          : 0.762 ns
Required Time  : 50.00 MHz ( period = 20.000 ns )
Actual Time    : N/A
From           : std_1c20:inst|clock_0:the_clock_0|master_writedata[0]
To             : std_1c20:inst|sdram_pll:the_sdram_pll|control_reg_out[0]
From Clock     : PLD_CLKFB
To Clock       : PLD_CLKFB
Failed Paths   : 0

Type           : Clock Hold: 'PLD_CLOCKINPUT[1]'
Slack          : 0.768 ns
Required Time  : 50.00 MHz ( period = 20.000 ns )
Actual Time    : N/A
From           : std_1c20:inst|clock_1:the_clock_1|master_writedata[15]
To             : std_1c20:inst|connector_pll:the_connector_pll|control_reg_out[15]
From Clock     : PLD_CLOCKINPUT[1]
To Clock       : PLD_CLOCKINPUT[1]
Failed Paths   : 0

Type           : Total number of failed paths
Slack          : 
Required Time  : 
Actual Time    : 
From           : 
To             : 
From Clock     : 
To Clock       : 
Failed Paths   : 0

--------------------------------------------------------------------------------------

