# Flow report for standard

### Fri Apr 21 03:23:57 2006
Version 6.0 Build 176 04/19/2006 SJ Full Version

## Table of Contents

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1. Legal Notice
2. Flow Summary
3. Flow Settings
4. Flow Non-Default Global Settings
5. Flow Elapsed Time
6. Flow Log

## Legal Notice

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    Copyright (C) 1991-2006 Altera Corporation
    Your use of Altera Corporation's design tools, logic functions
    and other software and tools, and its AMPP partner logic
    functions, and any output files any of the foregoing
    (including device programming or simulation files), and any
    associated documentation or information are expressly subject
    to the terms and conditions of the Altera Program License
    Subscription Agreement, Altera MegaCore Function License
    Agreement, or other applicable license agreement, including,
    without limitation, that your use is for the sole purpose of
    programming logic devices manufactured by Altera and sold by
    Altera or its authorized distributors.  Please refer to the
    applicable agreement for further details.

## Flow Summary

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Flow Status | Successful - Fri Apr 21 03:23:56 2006
Quartus II Version | 6.0 Build 176 04/19/2006 SJ Full Version
Revision Name | standard
Top-level Entity Name | standard
Family | Cyclone
Device | EP1C20F400C7
Timing Models | Final
Met timing requirements | Yes
Total logic elements | 4,930 / 20,060 ( 25 % )
Total pins | 180 / 301 ( 60 % )
Total virtual pins | 0
Total memory bits | 50,944 / 294,912 ( 17 % )
Total PLLs | 2 / 2 ( 100 % )

## Flow Settings

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Option | Setting
--- | ---
Start date & time | 04/21/2006 02:56:21
Main task | Compilation
Revision Name | standard

## Flow Non-Default Global Settings

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Assignment Name | Value | Default Value | Entity Name | Section Id
--- | --- | --- | --- | ---
ADV_NETLIST_OPT_SYNTH_GATE_RETIME | On | Off | -- | --
ADV_NETLIST_OPT_SYNTH_WYSIWYG_REMAP | On | Off | -- | --
CYCLONE_OPTIMIZATION_TECHNIQUE | Speed | Balanced | -- | --
FITTER_EFFORT | Standard Fit | Auto Fit | -- | --
PHYSICAL_SYNTHESIS_COMBO_LOGIC | On | Off | -- | --
PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION | On | Off | -- | --
PHYSICAL_SYNTHESIS_REGISTER_RETIMING | On | Off | -- | --
RESERVE_PIN | As input tri-stated | -- | -- | --

## Flow Elapsed Time

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Module Name | Elapsed Time
--- | ---
Analysis & Synthesis | 00:04:50
Fitter | 00:22:19
Assembler | 00:00:06
Timing Analyzer | 00:00:09
Total | 00:27:24

## Flow Log

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    quartus_map --read_settings_files=on --write_settings_files=off standard -c standard
    quartus_fit --read_settings_files=off --write_settings_files=off standard -c standard
    quartus_asm --read_settings_files=off --write_settings_files=off standard -c standard
    quartus_tan --read_settings_files=off --write_settings_files=off standard -c standard --timing_analysis_only

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