readme - Standard Design



Overview:

This design is provided for all Nios development boards and highlights many of the standard features of the Nios II processor.

Contents of the System:

 - Nios II/s Core
 - JTAG Debug Module (Level 1)
 - SDRAM Controller (32MB)
 - SRAM Controller (1MB)
 - CFI Flash Memory Interface (16MB)
 - EPCS Controller (with bootloader)
 - JTAG UART
 - UART (RS-232)
 - Two Timers
 - Ethernet Interface
 - LED PIO
 - Seven Segment Display PIO
 - Push Button PIO
 - LCD Display Interface
 - System ID Peripheral



Hardware Specs:

 - Fmax > 85MHz
 - Resource Usage < 4500 LEs
 - Onchip Memory Usage < 7KB
 - Two PLLs 



Supported Software Examples:

 - Blank Project
 - Hello World
 - Board Diagnostic
 - Count Binary
 - Dhrystone
 - Hello Free-Standing
 - Hello LED
 - Hello MicroC/OS II
 - Hello World Small
 - Host File System
 - MicroC/OS-II Message Box
 - Memory Test
 - MicroC/OS-II Tutorial
 - Simple Sockets Server
 - Web Server
 - Zip File System

