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-- Copyright (C) 1991-2006 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions
-- and other software and tools, and its AMPP partner logic
-- functions, and any output files any of the foregoing
-- (including device programming or simulation files), and any
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-- Agreement, or other applicable license agreement, including,
-- without limitation, that your use is for the sole purpose of
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-- applicable agreement for further details.

--QC2__clk0 is std_1c20:inst|sdram_pll:the_sdram_pll|altpllsdram_pll:the_pll|altpll:altpll_component|_clk0

QC2__clk0 = PLL.CLK0(.FBIN(), .ENA(), .CLKSWITCH(), .ARESET(), .PFDENA(), .SCANCLK(), .SCANACLR(), .SCANDATA(), .COMPARATOR(), .INCLK(PLD_CLKFB), .INCLK(), .CLKENA(), .CLKENA(), .CLKENA(), .CLKENA(), .CLKENA(), .CLKENA(), .EXTCLKENA(), .EXTCLKENA(), .EXTCLKENA(), .EXTCLKENA());

--QC2__extclk0 is std_1c20:inst|sdram_pll:the_sdram_pll|altpllsdram_pll:the_pll|altpll:altpll_component|_extclk0

QC2__extclk0 = PLL.EXTCLK0(.FBIN(), .ENA(), .CLKSWITCH(), .ARESET(), .PFDENA(), .SCANCLK(), .SCANACLR(), .SCANDATA(), .COMPARATOR(), .INCLK(PLD_CLKFB), .INCLK(), .CLKENA(), .CLKENA(), .CLKENA(), .CLKENA(), .CLKENA(), .CLKENA(), .EXTCLKENA(), .EXTCLKENA(), .EXTCLKENA(), .EXTCLKENA());

--QC1__extclk0 is std_1c20:inst|connector_pll:the_connector_pll|altpllconnector_pll:the_pll|altpll:altpll_component|_extclk0

QC1__extclk0 = PLL.EXTCLK0(.FBIN(), .ENA(), .CLKSWITCH(), .ARESET(), .PFDENA(), .SCANCLK(), .SCANACLR(), .SCANDATA(), .COMPARATOR(), .INCLK(PLD_CLOCKINPUT[1]), .INCLK(), .CLKENA(), .CLKENA(), .CLKENA(), .CLKENA(), .CLKENA(), .CLKENA(), .EXTCLKENA(), .EXTCLKENA(), .EXTCLKENA(), .EXTCLKENA());

--Y1_ior_n_to_the_lan91c111 is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ior_n_to_the_lan91c111

--operation mode is normal

Y1_ior_n_to_the_lan91c111_lut_out = !Y1_ext_ram_bus_avalon_slave_begins_xfer & (Y1L84 # S1_internal_d_read & Y1L52);

Y1_ior_n_to_the_lan91c111 = DFFEAS(Y1_ior_n_to_the_lan91c111_lut_out, QC2__clk0, F1_data_out, , , , , , );

--Y1_write_n_to_the_ext_flash is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|write_n_to_the_ext_flash

--operation mode is normal

Y1_write_n_to_the_ext_flash_lut_out = Y1L139 & !Y1_ext_ram_bus_avalon_slave_begins_xfer & (Y1_ext_flash_s1_wait_counter[3] $ !Y1L290);

Y1_write_n_to_the_ext_flash = DFFEAS(Y1_write_n_to_the_ext_flash_lut_out, QC2__clk0, F1_data_out, , , , , , );

--Y1_iow_n_to_the_lan91c111 is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|iow_n_to_the_lan91c111

--operation mode is normal

Y1_iow_n_to_the_lan91c111_lut_out = S1_internal_d_write & Y1L52 & Y1L260 & !Y1_ext_ram_bus_avalon_slave_begins_xfer;

Y1_iow_n_to_the_lan91c111 = DFFEAS(Y1_iow_n_to_the_lan91c111_lut_out, QC2__clk0, F1_data_out, , , , , , );

--Y1_read_n_to_the_ext_flash is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|read_n_to_the_ext_flash

--operation mode is normal

Y1_read_n_to_the_ext_flash_lut_out = !Y1_ext_ram_bus_avalon_slave_begins_xfer & !Y1_ext_flash_s1_wait_counter[3] & (Y1L66 # Y1L82);

Y1_read_n_to_the_ext_flash = DFFEAS(Y1_read_n_to_the_ext_flash_lut_out, QC2__clk0, F1_data_out, , , , , , );

--Y1_read_n_to_the_ext_ram is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|read_n_to_the_ext_ram

--operation mode is normal

Y1_read_n_to_the_ext_ram_lut_out = Y1L83 # S1_internal_d_read & Y1L51;

Y1_read_n_to_the_ext_ram = DFFEAS(Y1_read_n_to_the_ext_ram_lut_out, QC2__clk0, F1_data_out, , , , , , );

--Y1_select_n_to_the_ext_flash is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|select_n_to_the_ext_flash

--operation mode is normal

Y1_select_n_to_the_ext_flash_lut_out = !Y1L281;

Y1_select_n_to_the_ext_flash = DFFEAS(Y1_select_n_to_the_ext_flash_lut_out, QC2__clk0, F1_data_out, , , , , , );

--Y1_select_n_to_the_ext_ram is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|select_n_to_the_ext_ram

--operation mode is normal

Y1_select_n_to_the_ext_ram_lut_out = Y1L83 # Y1L59 & (Y1L29 # Y1L31);

Y1_select_n_to_the_ext_ram = DFFEAS(Y1_select_n_to_the_ext_ram_lut_out, QC2__clk0, F1_data_out, , , , , , );

--Y1_write_n_to_the_ext_ram_local is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|write_n_to_the_ext_ram_local

--operation mode is normal

Y1_write_n_to_the_ext_ram_local_lut_out = S1_internal_d_write & Y1L59 & (Y1L29 # Y1L31);

Y1_write_n_to_the_ext_ram_local = DFFEAS(Y1_write_n_to_the_ext_ram_local_lut_out, QC2__clk0, F1_data_out, , , , , , );

--Y1_write_n_to_the_ext_ram_mask is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|write_n_to_the_ext_ram_mask

--operation mode is normal

Y1_write_n_to_the_ext_ram_mask_lut_out = Y1_write_n_to_the_ext_ram_local;

Y1_write_n_to_the_ext_ram_mask = DFFEAS(Y1_write_n_to_the_ext_ram_mask_lut_out, !QC2__clk0, F1_data_out, , , , , , );

--Y1L304 is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|write_n_to_the_ext_ram~0

--operation mode is normal

Y1L304 = Y1_write_n_to_the_ext_ram_local & (!Y1_write_n_to_the_ext_ram_mask);

--KB1_m_cmd[1] is std_1c20:inst|sdram:the_sdram|m_cmd[1]

--operation mode is normal

KB1_m_cmd[1]_lut_out = !KB1L262 & (KB1_m_state[7] & KB1L263 # !KB1_m_state[7] & (KB1L265));

KB1_m_cmd[1] = DFFEAS(KB1_m_cmd[1]_lut_out, QC2__clk0, F1_data_out, , , , , , );

--KB1_m_cmd[3] is std_1c20:inst|sdram:the_sdram|m_cmd[3]

--operation mode is normal

KB1_m_cmd[3]_lut_out = KB1_m_state[7] & (KB1L256 & KB1L257) # !KB1_m_state[7] & !KB1L255;

KB1_m_cmd[3] = DFFEAS(KB1_m_cmd[3]_lut_out, QC2__clk0, F1_data_out, , , , , , );

--KB1_m_cmd[2] is std_1c20:inst|sdram:the_sdram|m_cmd[2]

--operation mode is normal

KB1_m_cmd[2]_lut_out = !KB1L258 & !KB1L259 & (KB1L261 # !KB1L260);

KB1_m_cmd[2] = DFFEAS(KB1_m_cmd[2]_lut_out, QC2__clk0, F1_data_out, , , , , , );

--KB1_m_cmd[0] is std_1c20:inst|sdram:the_sdram|m_cmd[0]

--operation mode is normal

KB1_m_cmd[0]_lut_out = KB1L267 & KB1L269 & (!KB1L268 # !KB1L171);

KB1_m_cmd[0] = DFFEAS(KB1_m_cmd[0]_lut_out, QC2__clk0, F1_data_out, , , , , , );

--ZE1_txd is std_1c20:inst|uart1:the_uart1|uart1_tx:the_uart1_tx|txd

--operation mode is normal

ZE1_txd_lut_out = XE1_control_reg[9] # ZE1_pre_txd;

ZE1_txd = DFFEAS(ZE1_txd_lut_out, QC2__clk0, F1_data_out, , , , , , );

--S1_M_alu_result[2] is std_1c20:inst|cpu:the_cpu|M_alu_result[2]

--operation mode is normal

S1_M_alu_result[2] = AMPP_FUNCTION(QC2__clk0, S1L408, F1_data_out, S1_W_stall);

--S1_M_alu_result[3] is std_1c20:inst|cpu:the_cpu|M_alu_result[3]

--operation mode is normal

S1_M_alu_result[3] = AMPP_FUNCTION(QC2__clk0, S1L409, F1_data_out, S1_W_stall);

--S1_internal_d_read is std_1c20:inst|cpu:the_cpu|internal_d_read

--operation mode is normal

S1_internal_d_read = AMPP_FUNCTION(QC2__clk0, S1L336, S1L752, S1_E_ctrl_ld, S1_W_stall, F1_data_out);

--S1_M_alu_result[22] is std_1c20:inst|cpu:the_cpu|M_alu_result[22]

--operation mode is normal

S1_M_alu_result[22] = AMPP_FUNCTION(QC2__clk0, S1L7, S1L530, A1L276, S1_E_ctrl_dst_data_sel_logic_result, F1_data_out, S1_E_ctrl_dst_data_sel_cmp, S1_E_ctrl_rdctl_inst, S1_W_stall);

--S1_M_alu_result[21] is std_1c20:inst|cpu:the_cpu|M_alu_result[21]

--operation mode is normal

S1_M_alu_result[21] = AMPP_FUNCTION(QC2__clk0, S1L8, S1L529, A1L276, S1_E_ctrl_dst_data_sel_logic_result, F1_data_out, S1_E_ctrl_dst_data_sel_cmp, S1_E_ctrl_rdctl_inst, S1_W_stall);

--S1_M_alu_result[19] is std_1c20:inst|cpu:the_cpu|M_alu_result[19]

--operation mode is normal

S1_M_alu_result[19] = AMPP_FUNCTION(QC2__clk0, S1L9, S1L527, A1L276, S1_E_ctrl_dst_data_sel_logic_result, F1_data_out, S1_E_ctrl_dst_data_sel_cmp, S1_E_ctrl_rdctl_inst, S1_W_stall);

--S1_M_alu_result[18] is std_1c20:inst|cpu:the_cpu|M_alu_result[18]

--operation mode is normal

S1_M_alu_result[18] = AMPP_FUNCTION(QC2__clk0, S1L10, S1L526, A1L276, S1_E_ctrl_dst_data_sel_logic_result, F1_data_out, S1_E_ctrl_dst_data_sel_cmp, S1_E_ctrl_rdctl_inst, S1_W_stall);

--UB1L2 is std_1c20:inst|sysid_control_slave_arbitrator:the_sysid_control_slave|cpu_data_master_granted_sysid_control_slave~150

--operation mode is normal

UB1L2 = !S1_M_alu_result[22] & !S1_M_alu_result[21] & !S1_M_alu_result[19] & !S1_M_alu_result[18];

--S1_M_alu_result[24] is std_1c20:inst|cpu:the_cpu|M_alu_result[24]

--operation mode is normal

S1_M_alu_result[24] = AMPP_FUNCTION(QC2__clk0, S1L11, S1L532, A1L276, S1_E_ctrl_dst_data_sel_logic_result, F1_data_out, S1_E_ctrl_dst_data_sel_cmp, S1_E_ctrl_rdctl_inst, S1_W_stall);

--S1_M_alu_result[16] is std_1c20:inst|cpu:the_cpu|M_alu_result[16]

--operation mode is normal

S1_M_alu_result[16] = AMPP_FUNCTION(QC2__clk0, S1L12, S1L524, A1L276, S1_E_ctrl_dst_data_sel_logic_result, F1_data_out, S1_E_ctrl_dst_data_sel_cmp, S1_E_ctrl_rdctl_inst, S1_W_stall);

--S1_M_alu_result[15] is std_1c20:inst|cpu:the_cpu|M_alu_result[15]

--operation mode is normal

S1_M_alu_result[15] = AMPP_FUNCTION(QC2__clk0, S1L13, S1L523, A1L276, S1_E_ctrl_dst_data_sel_logic_result, F1_data_out, S1_E_ctrl_dst_data_sel_cmp, S1_E_ctrl_rdctl_inst, S1_W_stall);

--S1_M_alu_result[14] is std_1c20:inst|cpu:the_cpu|M_alu_result[14]

--operation mode is normal

S1_M_alu_result[14] = AMPP_FUNCTION(QC2__clk0, S1L14, S1L522, A1L276, S1_E_ctrl_dst_data_sel_logic_result, F1_data_out, S1_E_ctrl_dst_data_sel_cmp, S1_E_ctrl_rdctl_inst, S1_W_stall);

--UB1L3 is std_1c20:inst|sysid_control_slave_arbitrator:the_sysid_control_slave|cpu_data_master_granted_sysid_control_slave~151

--operation mode is normal

UB1L3 = !S1_M_alu_result[24] & !S1_M_alu_result[16] & !S1_M_alu_result[15] & !S1_M_alu_result[14];

--S1_M_alu_result[13] is std_1c20:inst|cpu:the_cpu|M_alu_result[13]

--operation mode is normal

S1_M_alu_result[13] = AMPP_FUNCTION(QC2__clk0, S1L15, S1L521, A1L276, S1_E_ctrl_dst_data_sel_logic_result, F1_data_out, S1_E_ctrl_dst_data_sel_cmp, S1_E_ctrl_rdctl_inst, S1_W_stall);

--S1_M_alu_result[12] is std_1c20:inst|cpu:the_cpu|M_alu_result[12]

--operation mode is normal

S1_M_alu_result[12] = AMPP_FUNCTION(QC2__clk0, S1L16, S1L520, A1L276, S1_E_ctrl_dst_data_sel_logic_result, F1_data_out, S1_E_ctrl_dst_data_sel_cmp, S1_E_ctrl_rdctl_inst, S1_W_stall);

--UB1L4 is std_1c20:inst|sysid_control_slave_arbitrator:the_sysid_control_slave|cpu_data_master_granted_sysid_control_slave~152

--operation mode is normal

UB1L4 = !S1_M_alu_result[13] & !S1_M_alu_result[12];

--S1_M_alu_result[17] is std_1c20:inst|cpu:the_cpu|M_alu_result[17]

--operation mode is normal

S1_M_alu_result[17] = AMPP_FUNCTION(QC2__clk0, S1L17, S1L525, A1L276, S1_E_ctrl_dst_data_sel_logic_result, F1_data_out, S1_E_ctrl_dst_data_sel_cmp, S1_E_ctrl_rdctl_inst, S1_W_stall);

--S1_M_alu_result[25] is std_1c20:inst|cpu:the_cpu|M_alu_result[25]

--operation mode is normal

S1_M_alu_result[25] = AMPP_FUNCTION(QC2__clk0, S1L18, S1L533, A1L276, S1_E_ctrl_dst_data_sel_logic_result, F1_data_out, S1_E_ctrl_dst_data_sel_cmp, S1_E_ctrl_rdctl_inst, S1_W_stall);

--S1_M_alu_result[20] is std_1c20:inst|cpu:the_cpu|M_alu_result[20]

--operation mode is normal

S1_M_alu_result[20] = AMPP_FUNCTION(QC2__clk0, S1L19, S1L528, A1L276, S1_E_ctrl_dst_data_sel_logic_result, F1_data_out, S1_E_ctrl_dst_data_sel_cmp, S1_E_ctrl_rdctl_inst, S1_W_stall);

--S1_M_alu_result[23] is std_1c20:inst|cpu:the_cpu|M_alu_result[23]

--operation mode is normal

S1_M_alu_result[23] = AMPP_FUNCTION(QC2__clk0, S1L20, S1L531, A1L276, S1_E_ctrl_dst_data_sel_logic_result, F1_data_out, S1_E_ctrl_dst_data_sel_cmp, S1_E_ctrl_rdctl_inst, S1_W_stall);

--V1L6 is std_1c20:inst|cpu_jtag_debug_module_arbitrator:the_cpu_jtag_debug_module|cpu_data_master_requests_cpu_jtag_debug_module~274

--operation mode is normal

V1L6 = S1_M_alu_result[17] & S1_M_alu_result[25] & S1_M_alu_result[20] & !S1_M_alu_result[23];

--UB1L5 is std_1c20:inst|sysid_control_slave_arbitrator:the_sysid_control_slave|cpu_data_master_granted_sysid_control_slave~153

--operation mode is normal

UB1L5 = UB1L2 & UB1L3 & UB1L4 & V1L6;

--S1_M_alu_result[11] is std_1c20:inst|cpu:the_cpu|M_alu_result[11]

--operation mode is normal

S1_M_alu_result[11] = AMPP_FUNCTION(QC2__clk0, S1L21, S1L519, A1L276, S1_E_ctrl_dst_data_sel_logic_result, F1_data_out, S1_E_ctrl_dst_data_sel_cmp, S1_E_ctrl_rdctl_inst, S1_W_stall);

--S1_M_alu_result[10] is std_1c20:inst|cpu:the_cpu|M_alu_result[10]

--operation mode is normal

S1_M_alu_result[10] = AMPP_FUNCTION(QC2__clk0, S1L22, S1L518, A1L276, S1_E_ctrl_dst_data_sel_logic_result, F1_data_out, S1_E_ctrl_dst_data_sel_cmp, S1_E_ctrl_rdctl_inst, S1_W_stall);

--S1_M_alu_result[9] is std_1c20:inst|cpu:the_cpu|M_alu_result[9]

--operation mode is normal

S1_M_alu_result[9] = AMPP_FUNCTION(QC2__clk0, S1L23, S1L517, A1L276, S1_E_ctrl_dst_data_sel_logic_result, F1_data_out, S1_E_ctrl_dst_data_sel_cmp, S1_E_ctrl_rdctl_inst, S1_W_stall);

--S1_M_alu_result[8] is std_1c20:inst|cpu:the_cpu|M_alu_result[8]

--operation mode is normal

S1_M_alu_result[8] = AMPP_FUNCTION(QC2__clk0, S1L24, S1L516, A1L276, S1_E_ctrl_dst_data_sel_logic_result, F1_data_out, S1_E_ctrl_dst_data_sel_cmp, S1_E_ctrl_rdctl_inst, S1_W_stall);

--UB1L6 is std_1c20:inst|sysid_control_slave_arbitrator:the_sysid_control_slave|cpu_data_master_granted_sysid_control_slave~154

--operation mode is normal

UB1L6 = S1_M_alu_result[11] & !S1_M_alu_result[10] & !S1_M_alu_result[9] & !S1_M_alu_result[8];

--S1_M_alu_result[7] is std_1c20:inst|cpu:the_cpu|M_alu_result[7]

--operation mode is normal

S1_M_alu_result[7] = AMPP_FUNCTION(QC2__clk0, S1L25, S1L515, A1L276, S1_E_ctrl_dst_data_sel_logic_result, F1_data_out, S1_E_ctrl_dst_data_sel_cmp, S1_E_ctrl_rdctl_inst, S1_W_stall);

--S1_M_alu_result[6] is std_1c20:inst|cpu:the_cpu|M_alu_result[6]

--operation mode is normal

S1_M_alu_result[6] = AMPP_FUNCTION(QC2__clk0, S1L412, F1_data_out, S1_W_stall);

--UB1L7 is std_1c20:inst|sysid_control_slave_arbitrator:the_sysid_control_slave|cpu_data_master_granted_sysid_control_slave~155

--operation mode is normal

UB1L7 = S1_M_alu_result[7] & (!S1_M_alu_result[6]);

--S1_internal_d_write is std_1c20:inst|cpu:the_cpu|internal_d_write

--operation mode is normal

S1_internal_d_write = AMPP_FUNCTION(QC2__clk0, RB1L7, S1_E_ctrl_st, S1L752, S1L1385, F1_data_out);

--S1_M_alu_result[4] is std_1c20:inst|cpu:the_cpu|M_alu_result[4]

--operation mode is normal

S1_M_alu_result[4] = AMPP_FUNCTION(QC2__clk0, S1L410, F1_data_out, S1_W_stall);

--JB1L2 is std_1c20:inst|reconfig_request_pio_s1_arbitrator:the_reconfig_request_pio_s1|cpu_data_master_requests_reconfig_request_pio_s1~48

--operation mode is normal

JB1L2 = !S1_M_alu_result[4] & (S1_internal_d_write # S1_internal_d_read);

--JB1L3 is std_1c20:inst|reconfig_request_pio_s1_arbitrator:the_reconfig_request_pio_s1|cpu_data_master_requests_reconfig_request_pio_s1~49

--operation mode is normal

JB1L3 = UB1L5 & UB1L6 & UB1L7 & JB1L2;

--EB1_lcd_display_control_slave_wait_counter[1] is std_1c20:inst|lcd_display_control_slave_arbitrator:the_lcd_display_control_slave|lcd_display_control_slave_wait_counter[1]

--operation mode is normal

EB1_lcd_display_control_slave_wait_counter[1]_lut_out = EB1L1 & !EB1L15 & (!EB1L16 # !QB1L1);

EB1_lcd_display_control_slave_wait_counter[1] = DFFEAS(EB1_lcd_display_control_slave_wait_counter[1]_lut_out, QC2__clk0, F1_data_out, , , , , , );

--EB1_lcd_display_control_slave_wait_counter[0] is std_1c20:inst|lcd_display_control_slave_arbitrator:the_lcd_display_control_slave|lcd_display_control_slave_wait_counter[0]

--operation mode is normal

EB1_lcd_display_control_slave_wait_counter[0]_lut_out = EB1L19 # EB1L3 & EB1L17 & !EB1L15;

EB1_lcd_display_control_slave_wait_counter[0] = DFFEAS(EB1_lcd_display_control_slave_wait_counter[0]_lut_out, QC2__clk0, F1_data_out, , , , , , );

--EB1_lcd_display_control_slave_wait_counter[3] is std_1c20:inst|lcd_display_control_slave_arbitrator:the_lcd_display_control_slave|lcd_display_control_slave_wait_counter[3]

--operation mode is normal

EB1_lcd_display_control_slave_wait_counter[3]_lut_out = !EB1L19 & (EB1L5 & !EB1L15 # !EB1L17);

EB1_lcd_display_control_slave_wait_counter[3] = DFFEAS(EB1_lcd_display_control_slave_wait_counter[3]_lut_out, QC2__clk0, F1_data_out, , , , , , );

--EB1_lcd_display_control_slave_wait_counter[2] is std_1c20:inst|lcd_display_control_slave_arbitrator:the_lcd_display_control_slave|lcd_display_control_slave_wait_counter[2]

--operation mode is normal

EB1_lcd_display_control_slave_wait_counter[2]_lut_out = EB1L19 # EB1L7 & EB1L17 & !EB1L15;

EB1_lcd_display_control_slave_wait_counter[2] = DFFEAS(EB1_lcd_display_control_slave_wait_counter[2]_lut_out, QC2__clk0, F1_data_out, , , , , , );

--EB1L28 is std_1c20:inst|lcd_display_control_slave_arbitrator:the_lcd_display_control_slave|LessThan0~92

--operation mode is normal

EB1L28 = !EB1_lcd_display_control_slave_wait_counter[1] & !EB1_lcd_display_control_slave_wait_counter[0] # !EB1_lcd_display_control_slave_wait_counter[2] # !EB1_lcd_display_control_slave_wait_counter[3];

--EB1_lcd_display_control_slave_wait_counter[5] is std_1c20:inst|lcd_display_control_slave_arbitrator:the_lcd_display_control_slave|lcd_display_control_slave_wait_counter[5]

--operation mode is normal

EB1_lcd_display_control_slave_wait_counter[5]_lut_out = EB1L19 # EB1L9 & EB1L17 & !EB1L15;

EB1_lcd_display_control_slave_wait_counter[5] = DFFEAS(EB1_lcd_display_control_slave_wait_counter[5]_lut_out, QC2__clk0, F1_data_out, , , , , , );

--EB1_lcd_display_control_slave_wait_counter[4] is std_1c20:inst|lcd_display_control_slave_arbitrator:the_lcd_display_control_slave|lcd_display_control_slave_wait_counter[4]

--operation mode is normal

EB1_lcd_display_control_slave_wait_counter[4]_lut_out = !EB1L19 & (EB1L10 & !EB1L15 # !EB1L17);

EB1_lcd_display_control_slave_wait_counter[4] = DFFEAS(EB1_lcd_display_control_slave_wait_counter[4]_lut_out, QC2__clk0, F1_data_out, , , , , , );

--EB1L29 is std_1c20:inst|lcd_display_control_slave_arbitrator:the_lcd_display_control_slave|LessThan0~93

--operation mode is normal

EB1L29 = !EB1_lcd_display_control_slave_wait_counter[5] & !EB1_lcd_display_control_slave_wait_counter[4];

--S1_M_alu_result[5] is std_1c20:inst|cpu:the_cpu|M_alu_result[5]

--operation mode is normal

S1_M_alu_result[5] = AMPP_FUNCTION(QC2__clk0, S1L411, F1_data_out, S1_W_stall);

--DB1L1 is std_1c20:inst|lcd_display:the_lcd_display|LCD_E~447

--operation mode is normal

DB1L1 = S1_internal_d_read & JB1L3 & EB1L30 & !S1_M_alu_result[5];

--EB1L18 is std_1c20:inst|lcd_display_control_slave_arbitrator:the_lcd_display_control_slave|lcd_display_control_slave_in_a_write_cycle~48

--operation mode is normal

EB1L18 = S1_internal_d_write & JB1L3 & (!S1_M_alu_result[5]);

--S1_M_mem_byte_en[0] is std_1c20:inst|cpu:the_cpu|M_mem_byte_en[0]

--operation mode is normal

S1_M_mem_byte_en[0] = AMPP_FUNCTION(QC2__clk0, S1_E_iw[4], S1_E_iw[3], YC1_result[0], YC1_result[1], F1_data_out, S1_W_stall);

--DB1L2 is std_1c20:inst|lcd_display:the_lcd_display|LCD_E~448

--operation mode is normal

DB1L2 = EB1_lcd_display_control_slave_wait_counter[1] & (EB1_lcd_display_control_slave_wait_counter[2] # EB1_lcd_display_control_slave_wait_counter[4]) # !EB1_lcd_display_control_slave_wait_counter[1] & EB1_lcd_display_control_slave_wait_counter[2] & (EB1_lcd_display_control_slave_wait_counter[4] # EB1_lcd_display_control_slave_wait_counter[0]);

--DB1L3 is std_1c20:inst|lcd_display:the_lcd_display|LCD_E~449

--operation mode is normal

DB1L3 = S1_M_mem_byte_en[0] & !EB1_lcd_display_control_slave_wait_counter[5] & !DB1L5;

--EB1_d1_reasons_to_wait is std_1c20:inst|lcd_display_control_slave_arbitrator:the_lcd_display_control_slave|d1_reasons_to_wait

--operation mode is normal

EB1_d1_reasons_to_wait_lut_out = JB1L3 & !S1_M_alu_result[5] & (!EB1L15 # !EB1_d1_reasons_to_wait);

EB1_d1_reasons_to_wait = DFFEAS(EB1_d1_reasons_to_wait_lut_out, QC2__clk0, F1_data_out, , , , , , );

--EB1L16 is std_1c20:inst|lcd_display_control_slave_arbitrator:the_lcd_display_control_slave|lcd_display_control_slave_begintransfer~46

--operation mode is normal

EB1L16 = JB1L3 & (!S1_M_alu_result[5] & !EB1_d1_reasons_to_wait);

--DB1L4 is std_1c20:inst|lcd_display:the_lcd_display|LCD_E~450

--operation mode is normal

DB1L4 = !EB1L16 & (DB1L1 # EB1L18 & DB1L3);

--Y1_be_n_to_the_ext_ram[3] is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|be_n_to_the_ext_ram[3]

--operation mode is normal

Y1_be_n_to_the_ext_ram[3]_lut_out = S1_M_mem_byte_en[3] # !Y1L29 & !Y1L31 # !Y1L59;

Y1_be_n_to_the_ext_ram[3] = DFFEAS(Y1_be_n_to_the_ext_ram[3]_lut_out, QC2__clk0, F1_data_out, , , , , , );

--Y1_be_n_to_the_ext_ram[2] is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|be_n_to_the_ext_ram[2]

--operation mode is normal

Y1_be_n_to_the_ext_ram[2]_lut_out = S1_M_mem_byte_en[2] # !Y1L29 & !Y1L31 # !Y1L59;

Y1_be_n_to_the_ext_ram[2] = DFFEAS(Y1_be_n_to_the_ext_ram[2]_lut_out, QC2__clk0, F1_data_out, , , , , , );

--Y1_be_n_to_the_ext_ram[1] is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|be_n_to_the_ext_ram[1]

--operation mode is normal

Y1_be_n_to_the_ext_ram[1]_lut_out = S1_M_mem_byte_en[1] # !Y1L29 & !Y1L31 # !Y1L59;

Y1_be_n_to_the_ext_ram[1] = DFFEAS(Y1_be_n_to_the_ext_ram[1]_lut_out, QC2__clk0, F1_data_out, , , , , , );

--Y1_be_n_to_the_ext_ram[0] is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|be_n_to_the_ext_ram[0]

--operation mode is normal

Y1_be_n_to_the_ext_ram[0]_lut_out = S1_M_mem_byte_en[0] # !Y1L29 & !Y1L31 # !Y1L59;

Y1_be_n_to_the_ext_ram[0] = DFFEAS(Y1_be_n_to_the_ext_ram[0]_lut_out, QC2__clk0, F1_data_out, , , , , , );

--Y1_byteenablen_to_the_lan91c111[3] is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|byteenablen_to_the_lan91c111[3]

--operation mode is normal

Y1_byteenablen_to_the_lan91c111[3]_lut_out = S1_M_mem_byte_en[3] # !Y1L13 & !Y1L15 # !Y1L61;

Y1_byteenablen_to_the_lan91c111[3] = DFFEAS(Y1_byteenablen_to_the_lan91c111[3]_lut_out, QC2__clk0, F1_data_out, , , , , , );

--Y1_byteenablen_to_the_lan91c111[2] is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|byteenablen_to_the_lan91c111[2]

--operation mode is normal

Y1_byteenablen_to_the_lan91c111[2]_lut_out = S1_M_mem_byte_en[2] # !Y1L13 & !Y1L15 # !Y1L61;

Y1_byteenablen_to_the_lan91c111[2] = DFFEAS(Y1_byteenablen_to_the_lan91c111[2]_lut_out, QC2__clk0, F1_data_out, , , , , , );

--Y1_byteenablen_to_the_lan91c111[1] is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|byteenablen_to_the_lan91c111[1]

--operation mode is normal

Y1_byteenablen_to_the_lan91c111[1]_lut_out = S1_M_mem_byte_en[1] # !Y1L13 & !Y1L15 # !Y1L61;

Y1_byteenablen_to_the_lan91c111[1] = DFFEAS(Y1_byteenablen_to_the_lan91c111[1]_lut_out, QC2__clk0, F1_data_out, , , , , , );

--Y1_byteenablen_to_the_lan91c111[0] is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|byteenablen_to_the_lan91c111[0]

--operation mode is normal

Y1_byteenablen_to_the_lan91c111[0]_lut_out = S1_M_mem_byte_en[0] # !Y1L13 & !Y1L15 # !Y1L61;

Y1_byteenablen_to_the_lan91c111[0] = DFFEAS(Y1_byteenablen_to_the_lan91c111[0]_lut_out, QC2__clk0, F1_data_out, , , , , , );

--Y1_ext_ram_bus_address[22] is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_address[22]

--operation mode is normal

Y1_ext_ram_bus_address[22]_lut_out = Y1L284 & (Y1L285 # S1_M_alu_result[22] & Y1L50);

Y1_ext_ram_bus_address[22] = DFFEAS(Y1_ext_ram_bus_address[22]_lut_out, QC2__clk0, F1_data_out, , , , , , );

--Y1_ext_ram_bus_address[21] is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_address[21]

--operation mode is normal

Y1_ext_ram_bus_address[21]_lut_out = Y1L284 & (Y1L283 # S1_M_alu_result[21] & Y1L50);

Y1_ext_ram_bus_address[21] = DFFEAS(Y1_ext_ram_bus_address[21]_lut_out, QC2__clk0, F1_data_out, , , , , , );

--Y1_ext_ram_bus_address[20] is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_address[20]

--operation mode is normal

Y1_ext_ram_bus_address[20]_lut_out = Y1L52 # Y1L1 # S1_ic_fill_tag[8] & !Y1L2;

Y1_ext_ram_bus_address[20] = DFFEAS(Y1_ext_ram_bus_address[20]_lut_out, QC2__clk0, F1_data_out, , , , , , );

--Y1_ext_ram_bus_address[19] is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_address[19]

--operation mode is normal

Y1_ext_ram_bus_address[19]_lut_out = Y1L284 & (Y1L286 & S1_ic_fill_tag[7] # !Y1L286 & (S1_M_alu_result[19]));

Y1_ext_ram_bus_address[19] = DFFEAS(Y1_ext_ram_bus_address[19]_lut_out, QC2__clk0, F1_data_out, , , , , , );

--Y1_ext_ram_bus_address[18] is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_address[18]

--operation mode is normal

Y1_ext_ram_bus_address[18]_lut_out = Y1L284 & (Y1L286 & S1_ic_fill_tag[6] # !Y1L286 & (S1_M_alu_result[18]));

Y1_ext_ram_bus_address[18] = DFFEAS(Y1_ext_ram_bus_address[18]_lut_out, QC2__clk0, F1_data_out, , , , , , );

--Y1_ext_ram_bus_address[17] is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_address[17]

--operation mode is normal

Y1_ext_ram_bus_address[17]_lut_out = Y1L284 & (Y1L286 & S1_ic_fill_tag[5] # !Y1L286 & (S1_M_alu_result[17]));

Y1_ext_ram_bus_address[17] = DFFEAS(Y1_ext_ram_bus_address[17]_lut_out, QC2__clk0, F1_data_out, , , , , , );

--Y1_ext_ram_bus_address[16] is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_address[16]

--operation mode is normal

Y1_ext_ram_bus_address[16]_lut_out = Y1L52 # Y1L2 & S1_M_alu_result[16] # !Y1L2 & (S1_ic_fill_tag[4]);

Y1_ext_ram_bus_address[16] = DFFEAS(Y1_ext_ram_bus_address[16]_lut_out, QC2__clk0, F1_data_out, , , , , , );

--Y1_ext_ram_bus_address[15] is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_address[15]

--operation mode is normal

Y1_ext_ram_bus_address[15]_lut_out = Y1L52 & S1_M_alu_result[15] # !Y1L52 & (Y1L2 & S1_M_alu_result[15] # !Y1L2 & (S1_ic_fill_tag[3]));

Y1_ext_ram_bus_address[15] = DFFEAS(Y1_ext_ram_bus_address[15]_lut_out, QC2__clk0, F1_data_out, , , , , , );

--Y1_ext_ram_bus_address[14] is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_address[14]

--operation mode is normal

Y1_ext_ram_bus_address[14]_lut_out = Y1L52 & S1_M_alu_result[14] # !Y1L52 & (Y1L2 & S1_M_alu_result[14] # !Y1L2 & (S1_ic_fill_tag[2]));

Y1_ext_ram_bus_address[14] = DFFEAS(Y1_ext_ram_bus_address[14]_lut_out, QC2__clk0, F1_data_out, , , , , , );

--Y1_ext_ram_bus_address[13] is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_address[13]

--operation mode is normal

Y1_ext_ram_bus_address[13]_lut_out = Y1L52 & S1_M_alu_result[13] # !Y1L52 & (Y1L2 & S1_M_alu_result[13] # !Y1L2 & (S1_ic_fill_tag[1]));

Y1_ext_ram_bus_address[13] = DFFEAS(Y1_ext_ram_bus_address[13]_lut_out, QC2__clk0, F1_data_out, , , , , , );

--Y1_ext_ram_bus_address[12] is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_address[12]

--operation mode is normal

Y1_ext_ram_bus_address[12]_lut_out = Y1L52 & S1_M_alu_result[12] # !Y1L52 & (Y1L2 & S1_M_alu_result[12] # !Y1L2 & (S1_ic_fill_tag[0]));

Y1_ext_ram_bus_address[12] = DFFEAS(Y1_ext_ram_bus_address[12]_lut_out, QC2__clk0, F1_data_out, , , , , , );

--Y1_ext_ram_bus_address[11] is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_address[11]

--operation mode is normal

Y1_ext_ram_bus_address[11]_lut_out = Y1L52 & S1_M_alu_result[11] # !Y1L52 & (Y1L2 & S1_M_alu_result[11] # !Y1L2 & (S1_ic_fill_line[6]));

Y1_ext_ram_bus_address[11] = DFFEAS(Y1_ext_ram_bus_address[11]_lut_out, QC2__clk0, F1_data_out, , , , , , );

--Y1_ext_ram_bus_address[10] is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_address[10]

--operation mode is normal

Y1_ext_ram_bus_address[10]_lut_out = Y1L52 & S1_M_alu_result[10] # !Y1L52 & (Y1L2 & S1_M_alu_result[10] # !Y1L2 & (S1_ic_fill_line[5]));

Y1_ext_ram_bus_address[10] = DFFEAS(Y1_ext_ram_bus_address[10]_lut_out, QC2__clk0, F1_data_out, , , , , , );

--Y1_ext_ram_bus_address[9] is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_address[9]

--operation mode is normal

Y1_ext_ram_bus_address[9]_lut_out = Y1L52 & S1_M_alu_result[9] # !Y1L52 & (Y1L2 & S1_M_alu_result[9] # !Y1L2 & (S1_ic_fill_line[4]));

Y1_ext_ram_bus_address[9] = DFFEAS(Y1_ext_ram_bus_address[9]_lut_out, QC2__clk0, F1_data_out, , , , , , );

--Y1_ext_ram_bus_address[8] is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_address[8]

--operation mode is normal

Y1_ext_ram_bus_address[8]_lut_out = Y1L52 & S1_M_alu_result[8] # !Y1L52 & (Y1L2 & S1_M_alu_result[8] # !Y1L2 & (S1_ic_fill_line[3]));

Y1_ext_ram_bus_address[8] = DFFEAS(Y1_ext_ram_bus_address[8]_lut_out, QC2__clk0, F1_data_out, , , , , , );

--Y1_ext_ram_bus_address[7] is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_address[7]

--operation mode is normal

Y1_ext_ram_bus_address[7]_lut_out = Y1L52 & S1_M_alu_result[7] # !Y1L52 & (Y1L2 & S1_M_alu_result[7] # !Y1L2 & (S1_ic_fill_line[2]));

Y1_ext_ram_bus_address[7] = DFFEAS(Y1_ext_ram_bus_address[7]_lut_out, QC2__clk0, F1_data_out, , , , , , );

--Y1_ext_ram_bus_address[6] is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_address[6]

--operation mode is normal

Y1_ext_ram_bus_address[6]_lut_out = Y1L52 & S1_M_alu_result[6] # !Y1L52 & (Y1L2 & S1_M_alu_result[6] # !Y1L2 & (S1_ic_fill_line[1]));

Y1_ext_ram_bus_address[6] = DFFEAS(Y1_ext_ram_bus_address[6]_lut_out, QC2__clk0, F1_data_out, , , , , , );

--Y1_ext_ram_bus_address[5] is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_address[5]

--operation mode is normal

Y1_ext_ram_bus_address[5]_lut_out = Y1L52 & S1_M_alu_result[5] # !Y1L52 & (Y1L2 & S1_M_alu_result[5] # !Y1L2 & (S1_ic_fill_line[0]));

Y1_ext_ram_bus_address[5] = DFFEAS(Y1_ext_ram_bus_address[5]_lut_out, QC2__clk0, F1_data_out, , , , , , );

--Y1_ext_ram_bus_address[4] is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_address[4]

--operation mode is normal

Y1_ext_ram_bus_address[4]_lut_out = Y1L52 & S1_M_alu_result[4] # !Y1L52 & (Y1L2 & S1_M_alu_result[4] # !Y1L2 & (S1_ic_fill_ap_offset[2]));

Y1_ext_ram_bus_address[4] = DFFEAS(Y1_ext_ram_bus_address[4]_lut_out, QC2__clk0, F1_data_out, , , , , , );

--Y1_ext_ram_bus_address[3] is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_address[3]

--operation mode is normal

Y1_ext_ram_bus_address[3]_lut_out = Y1L52 & S1_M_alu_result[3] # !Y1L52 & (Y1L2 & S1_M_alu_result[3] # !Y1L2 & (S1_ic_fill_ap_offset[1]));

Y1_ext_ram_bus_address[3] = DFFEAS(Y1_ext_ram_bus_address[3]_lut_out, QC2__clk0, F1_data_out, , , , , , );

--Y1_ext_ram_bus_address[2] is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_address[2]

--operation mode is normal

Y1_ext_ram_bus_address[2]_lut_out = Y1L52 & S1_M_alu_result[2] # !Y1L52 & (Y1L2 & S1_M_alu_result[2] # !Y1L2 & (S1_ic_fill_ap_offset[0]));

Y1_ext_ram_bus_address[2] = DFFEAS(Y1_ext_ram_bus_address[2]_lut_out, QC2__clk0, F1_data_out, , , , , , );

--Y1_ext_ram_bus_address[1] is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_address[1]

--operation mode is normal

Y1_ext_ram_bus_address[1]_lut_out = Y1L284 & (Y1L282 # S1_M_alu_result[1] & Y1L279) # !Y1L284 & S1_M_alu_result[1] & Y1L279;

Y1_ext_ram_bus_address[1] = DFFEAS(Y1_ext_ram_bus_address[1]_lut_out, QC2__clk0, F1_data_out, , , , , , );

--Y1_ext_ram_bus_address[0] is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_address[0]

--operation mode is normal

Y1_ext_ram_bus_address[0]_lut_out = Y1L284 & (Y1L280 # Y1L279 & S1_M_alu_result[0]) # !Y1L284 & Y1L279 & S1_M_alu_result[0];

Y1_ext_ram_bus_address[0] = DFFEAS(Y1_ext_ram_bus_address[0]_lut_out, QC2__clk0, F1_data_out, , , , , , );

--FB1_data_out[7] is std_1c20:inst|led_pio:the_led_pio|data_out[7]

--operation mode is normal

FB1_data_out[7]_lut_out = S1_M_st_data[7];

FB1_data_out[7] = DFFEAS(FB1_data_out[7]_lut_out, QC2__clk0, F1_data_out, , FB1L10, , , , );

--FB1_data_out[6] is std_1c20:inst|led_pio:the_led_pio|data_out[6]

--operation mode is normal

FB1_data_out[6]_lut_out = S1_M_st_data[6];

FB1_data_out[6] = DFFEAS(FB1_data_out[6]_lut_out, QC2__clk0, F1_data_out, , FB1L10, , , , );

--FB1_data_out[5] is std_1c20:inst|led_pio:the_led_pio|data_out[5]

--operation mode is normal

FB1_data_out[5]_lut_out = S1_M_st_data[5];

FB1_data_out[5] = DFFEAS(FB1_data_out[5]_lut_out, QC2__clk0, F1_data_out, , FB1L10, , , , );

--FB1_data_out[4] is std_1c20:inst|led_pio:the_led_pio|data_out[4]

--operation mode is normal

FB1_data_out[4]_lut_out = S1_M_st_data[4];

FB1_data_out[4] = DFFEAS(FB1_data_out[4]_lut_out, QC2__clk0, F1_data_out, , FB1L10, , , , );

--FB1_data_out[3] is std_1c20:inst|led_pio:the_led_pio|data_out[3]

--operation mode is normal

FB1_data_out[3]_lut_out = S1_M_st_data[3];

FB1_data_out[3] = DFFEAS(FB1_data_out[3]_lut_out, QC2__clk0, F1_data_out, , FB1L10, , , , );

--FB1_data_out[2] is std_1c20:inst|led_pio:the_led_pio|data_out[2]

--operation mode is normal

FB1_data_out[2]_lut_out = S1_M_st_data[2];

FB1_data_out[2] = DFFEAS(FB1_data_out[2]_lut_out, QC2__clk0, F1_data_out, , FB1L10, , , , );

--FB1_data_out[1] is std_1c20:inst|led_pio:the_led_pio|data_out[1]

--operation mode is normal

FB1_data_out[1]_lut_out = S1_M_st_data[1];

FB1_data_out[1] = DFFEAS(FB1_data_out[1]_lut_out, QC2__clk0, F1_data_out, , FB1L10, , , , );

--FB1_data_out[0] is std_1c20:inst|led_pio:the_led_pio|data_out[0]

--operation mode is normal

FB1_data_out[0]_lut_out = S1_M_st_data[0];

FB1_data_out[0] = DFFEAS(FB1_data_out[0]_lut_out, QC2__clk0, F1_data_out, , FB1L10, , , , );

--PB1_data_out[15] is std_1c20:inst|seven_seg_pio:the_seven_seg_pio|data_out[15]

--operation mode is normal

PB1_data_out[15]_lut_out = S1_M_st_data[15];

PB1_data_out[15] = DFFEAS(PB1_data_out[15]_lut_out, QC2__clk0, F1_data_out, , PB1L18, , , , );

--PB1_data_out[14] is std_1c20:inst|seven_seg_pio:the_seven_seg_pio|data_out[14]

--operation mode is normal

PB1_data_out[14]_lut_out = S1_M_st_data[14];

PB1_data_out[14] = DFFEAS(PB1_data_out[14]_lut_out, QC2__clk0, F1_data_out, , PB1L18, , , , );

--PB1_data_out[13] is std_1c20:inst|seven_seg_pio:the_seven_seg_pio|data_out[13]

--operation mode is normal

PB1_data_out[13]_lut_out = S1_M_st_data[13];

PB1_data_out[13] = DFFEAS(PB1_data_out[13]_lut_out, QC2__clk0, F1_data_out, , PB1L18, , , , );

--PB1_data_out[12] is std_1c20:inst|seven_seg_pio:the_seven_seg_pio|data_out[12]

--operation mode is normal

PB1_data_out[12]_lut_out = S1_M_st_data[12];

PB1_data_out[12] = DFFEAS(PB1_data_out[12]_lut_out, QC2__clk0, F1_data_out, , PB1L18, , , , );

--PB1_data_out[11] is std_1c20:inst|seven_seg_pio:the_seven_seg_pio|data_out[11]

--operation mode is normal

PB1_data_out[11]_lut_out = S1_M_st_data[11];

PB1_data_out[11] = DFFEAS(PB1_data_out[11]_lut_out, QC2__clk0, F1_data_out, , PB1L18, , , , );

--PB1_data_out[10] is std_1c20:inst|seven_seg_pio:the_seven_seg_pio|data_out[10]

--operation mode is normal

PB1_data_out[10]_lut_out = S1_M_st_data[10];

PB1_data_out[10] = DFFEAS(PB1_data_out[10]_lut_out, QC2__clk0, F1_data_out, , PB1L18, , , , );

--PB1_data_out[9] is std_1c20:inst|seven_seg_pio:the_seven_seg_pio|data_out[9]

--operation mode is normal

PB1_data_out[9]_lut_out = S1_M_st_data[9];

PB1_data_out[9] = DFFEAS(PB1_data_out[9]_lut_out, QC2__clk0, F1_data_out, , PB1L18, , , , );

--PB1_data_out[8] is std_1c20:inst|seven_seg_pio:the_seven_seg_pio|data_out[8]

--operation mode is normal

PB1_data_out[8]_lut_out = S1_M_st_data[8];

PB1_data_out[8] = DFFEAS(PB1_data_out[8]_lut_out, QC2__clk0, F1_data_out, , PB1L18, , , , );

--PB1_data_out[7] is std_1c20:inst|seven_seg_pio:the_seven_seg_pio|data_out[7]

--operation mode is normal

PB1_data_out[7]_lut_out = S1_M_st_data[7];

PB1_data_out[7] = DFFEAS(PB1_data_out[7]_lut_out, QC2__clk0, F1_data_out, , PB1L18, , , , );

--PB1_data_out[6] is std_1c20:inst|seven_seg_pio:the_seven_seg_pio|data_out[6]

--operation mode is normal

PB1_data_out[6]_lut_out = S1_M_st_data[6];

PB1_data_out[6] = DFFEAS(PB1_data_out[6]_lut_out, QC2__clk0, F1_data_out, , PB1L18, , , , );

--PB1_data_out[5] is std_1c20:inst|seven_seg_pio:the_seven_seg_pio|data_out[5]

--operation mode is normal

PB1_data_out[5]_lut_out = S1_M_st_data[5];

PB1_data_out[5] = DFFEAS(PB1_data_out[5]_lut_out, QC2__clk0, F1_data_out, , PB1L18, , , , );

--PB1_data_out[4] is std_1c20:inst|seven_seg_pio:the_seven_seg_pio|data_out[4]

--operation mode is normal

PB1_data_out[4]_lut_out = S1_M_st_data[4];

PB1_data_out[4] = DFFEAS(PB1_data_out[4]_lut_out, QC2__clk0, F1_data_out, , PB1L18, , , , );

--PB1_data_out[3] is std_1c20:inst|seven_seg_pio:the_seven_seg_pio|data_out[3]

--operation mode is normal

PB1_data_out[3]_lut_out = S1_M_st_data[3];

PB1_data_out[3] = DFFEAS(PB1_data_out[3]_lut_out, QC2__clk0, F1_data_out, , PB1L18, , , , );

--PB1_data_out[2] is std_1c20:inst|seven_seg_pio:the_seven_seg_pio|data_out[2]

--operation mode is normal

PB1_data_out[2]_lut_out = S1_M_st_data[2];

PB1_data_out[2] = DFFEAS(PB1_data_out[2]_lut_out, QC2__clk0, F1_data_out, , PB1L18, , , , );

--PB1_data_out[1] is std_1c20:inst|seven_seg_pio:the_seven_seg_pio|data_out[1]

--operation mode is normal

PB1_data_out[1]_lut_out = S1_M_st_data[1];

PB1_data_out[1] = DFFEAS(PB1_data_out[1]_lut_out, QC2__clk0, F1_data_out, , PB1L18, , , , );

--PB1_data_out[0] is std_1c20:inst|seven_seg_pio:the_seven_seg_pio|data_out[0]

--operation mode is normal

PB1_data_out[0]_lut_out = S1_M_st_data[0];

PB1_data_out[0] = DFFEAS(PB1_data_out[0]_lut_out, QC2__clk0, F1_data_out, , PB1L18, , , , );

--KB1_m_addr[11] is std_1c20:inst|sdram:the_sdram|m_addr[11]

--operation mode is normal

KB1_m_addr[11]_lut_out = KB1L432 & KB1_m_addr[11] # !KB1L432 & (KB1L430 # KB1_m_addr[11] & KB1L431);

KB1_m_addr[11] = DFFEAS(KB1_m_addr[11]_lut_out, QC2__clk0, F1_data_out, , , , , , );

--KB1_m_addr[10] is std_1c20:inst|sdram:the_sdram|m_addr[10]

--operation mode is normal

KB1_m_addr[10]_lut_out = KB1L432 & KB1_m_addr[10] # !KB1L432 & (KB1L437 # KB1_m_addr[10] & KB1L431);

KB1_m_addr[10] = DFFEAS(KB1_m_addr[10]_lut_out, QC2__clk0, F1_data_out, , , , , , );

--KB1_m_addr[9] is std_1c20:inst|sdram:the_sdram|m_addr[9]

--operation mode is normal

KB1_m_addr[9]_lut_out = KB1L432 & KB1_m_addr[9] # !KB1L432 & (KB1L442 # KB1_m_addr[9] & KB1L431);

KB1_m_addr[9] = DFFEAS(KB1_m_addr[9]_lut_out, QC2__clk0, F1_data_out, , , , , , );

--KB1_m_addr[8] is std_1c20:inst|sdram:the_sdram|m_addr[8]

--operation mode is normal

KB1_m_addr[8]_lut_out = KB1L432 & KB1_m_addr[8] # !KB1L432 & (KB1L447 # KB1_m_addr[8] & KB1L431);

KB1_m_addr[8] = DFFEAS(KB1_m_addr[8]_lut_out, QC2__clk0, F1_data_out, , , , , , );

--KB1_m_addr[7] is std_1c20:inst|sdram:the_sdram|m_addr[7]

--operation mode is normal

KB1_m_addr[7]_lut_out = KB1L432 & KB1_m_addr[7] # !KB1L432 & (KB1L454 # KB1_m_addr[7] & KB1_m_state[6]);

KB1_m_addr[7] = DFFEAS(KB1_m_addr[7]_lut_out, QC2__clk0, F1_data_out, , , , , , );

--KB1_m_addr[6] is std_1c20:inst|sdram:the_sdram|m_addr[6]

--operation mode is normal

KB1_m_addr[6]_lut_out = KB1L456 # KB1L461 & !KB1_m_state[6] & !KB1L432;

KB1_m_addr[6] = DFFEAS(KB1_m_addr[6]_lut_out, QC2__clk0, F1_data_out, , , , , , );

--KB1_m_addr[5] is std_1c20:inst|sdram:the_sdram|m_addr[5]

--operation mode is normal

KB1_m_addr[5]_lut_out = KB1L463 # KB1L468 & !KB1_m_state[6] & !KB1L432;

KB1_m_addr[5] = DFFEAS(KB1_m_addr[5]_lut_out, QC2__clk0, F1_data_out, , , , , , );

--KB1_m_addr[4] is std_1c20:inst|sdram:the_sdram|m_addr[4]

--operation mode is normal

KB1_m_addr[4]_lut_out = KB1L470 # KB1L475 & !KB1_m_state[6] & !KB1L432;

KB1_m_addr[4] = DFFEAS(KB1_m_addr[4]_lut_out, QC2__clk0, F1_data_out, , , , , , );

--KB1_m_addr[3] is std_1c20:inst|sdram:the_sdram|m_addr[3]

--operation mode is normal

KB1_m_addr[3]_lut_out = KB1L477 # KB1L482 & !KB1_m_state[6] & !KB1L432;

KB1_m_addr[3] = DFFEAS(KB1_m_addr[3]_lut_out, QC2__clk0, F1_data_out, , , , , , );

--KB1_m_addr[2] is std_1c20:inst|sdram:the_sdram|m_addr[2]

--operation mode is normal

KB1_m_addr[2]_lut_out = KB1L484 # KB1L489 & !KB1_m_state[6] & !KB1L432;

KB1_m_addr[2] = DFFEAS(KB1_m_addr[2]_lut_out, QC2__clk0, F1_data_out, , , , , , );

--KB1_m_addr[1] is std_1c20:inst|sdram:the_sdram|m_addr[1]

--operation mode is normal

KB1_m_addr[1]_lut_out = KB1L491 # KB1L496 & !KB1_m_state[6] & !KB1L432;

KB1_m_addr[1] = DFFEAS(KB1_m_addr[1]_lut_out, QC2__clk0, F1_data_out, , , , , , );

--KB1_m_addr[0] is std_1c20:inst|sdram:the_sdram|m_addr[0]

--operation mode is normal

KB1_m_addr[0]_lut_out = KB1L498 # KB1L503 & !KB1_m_state[6] & !KB1L432;

KB1_m_addr[0] = DFFEAS(KB1_m_addr[0]_lut_out, QC2__clk0, F1_data_out, , , , , , );

--KB1_m_bank[1] is std_1c20:inst|sdram:the_sdram|m_bank[1]

--operation mode is normal

KB1_m_bank[1]_lut_out = KB1L506 & (KB1L511 & KB1L505 # !KB1L511 & (KB1_m_bank[1])) # !KB1L506 & (KB1_m_bank[1]);

KB1_m_bank[1] = DFFEAS(KB1_m_bank[1]_lut_out, QC2__clk0, F1_data_out, , , , , , );

--KB1_m_bank[0] is std_1c20:inst|sdram:the_sdram|m_bank[0]

--operation mode is normal

KB1_m_bank[0]_lut_out = KB1L506 & (KB1L511 & KB1L507 # !KB1L511 & (KB1_m_bank[0])) # !KB1L506 & (KB1_m_bank[0]);

KB1_m_bank[0] = DFFEAS(KB1_m_bank[0]_lut_out, QC2__clk0, F1_data_out, , , , , , );

--KB1_m_dqm[3] is std_1c20:inst|sdram:the_sdram|m_dqm[3]

--operation mode is normal

KB1_m_dqm[3]_lut_out = KB1L506 & (KB1L511 & KB1L543 # !KB1L511 & (KB1_m_dqm[3])) # !KB1L506 & (KB1_m_dqm[3]);

KB1_m_dqm[3] = DFFEAS(KB1_m_dqm[3]_lut_out, QC2__clk0, F1_data_out, , , , , , );

--KB1_m_dqm[2] is std_1c20:inst|sdram:the_sdram|m_dqm[2]

--operation mode is normal

KB1_m_dqm[2]_lut_out = KB1L506 & (KB1L511 & KB1L544 # !KB1L511 & (KB1_m_dqm[2])) # !KB1L506 & (KB1_m_dqm[2]);

KB1_m_dqm[2] = DFFEAS(KB1_m_dqm[2]_lut_out, QC2__clk0, F1_data_out, , , , , , );

--KB1_m_dqm[1] is std_1c20:inst|sdram:the_sdram|m_dqm[1]

--operation mode is normal

KB1_m_dqm[1]_lut_out = KB1L506 & (KB1L511 & KB1L545 # !KB1L511 & (KB1_m_dqm[1])) # !KB1L506 & (KB1_m_dqm[1]);

KB1_m_dqm[1] = DFFEAS(KB1_m_dqm[1]_lut_out, QC2__clk0, F1_data_out, , , , , , );

--KB1_m_dqm[0] is std_1c20:inst|sdram:the_sdram|m_dqm[0]

--operation mode is normal

KB1_m_dqm[0]_lut_out = KB1L506 & (KB1L511 & KB1L546 # !KB1L511 & (KB1_m_dqm[0])) # !KB1L506 & (KB1_m_dqm[0]);

KB1_m_dqm[0] = DFFEAS(KB1_m_dqm[0]_lut_out, QC2__clk0, F1_data_out, , , , , , );

--A1L6 is altera_internal_jtag~TDO

A1L6 = STRATIX_ELA(altera_reserved_tms, altera_reserved_tck, altera_reserved_tdi, , , C1L19);

--A1L7 is altera_internal_jtag~TMSUTAP

A1L7 = STRATIX_ELA(altera_reserved_tms, altera_reserved_tck, altera_reserved_tdi, , , C1L19);

--A1L5 is altera_internal_jtag~TCKUTAP

A1L5 = STRATIX_ELA(altera_reserved_tms, altera_reserved_tck, altera_reserved_tdi, , , C1L19);

--altera_internal_jtag is altera_internal_jtag

altera_internal_jtag = STRATIX_ELA(altera_reserved_tms, altera_reserved_tck, altera_reserved_tdi, , , C1L19);

--A1L4 is altera_internal_jtag~SHIFTUSER

A1L4 = STRATIX_ELA(altera_reserved_tms, altera_reserved_tck, altera_reserved_tdi, , , C1L19);

--A1L8 is altera_internal_jtag~UPDATEUSER

A1L8 = STRATIX_ELA(altera_reserved_tms, altera_reserved_tck, altera_reserved_tdi, , , C1L19);

--A1L3 is altera_internal_jtag~RUNIDLEUSER

A1L3 = STRATIX_ELA(altera_reserved_tms, altera_reserved_tck, altera_reserved_tdi, , , C1L19);

--S1_internal_i_read is std_1c20:inst|cpu:the_cpu|internal_i_read

--operation mode is normal

S1_internal_i_read = AMPP_FUNCTION(QC2__clk0, S1_internal_i_read, S1_ic_fill_ap_cnt[3], U1L132, S1_D_ic_fill_starting, F1_data_out);

--S1_ic_fill_tag[8] is std_1c20:inst|cpu:the_cpu|ic_fill_tag[8]

--operation mode is normal

S1_ic_fill_tag[8] = AMPP_FUNCTION(QC2__clk0, S1_D_pc[18], F1_data_out, S1_D_ic_fill_starting);

--S1_ic_fill_tag[13] is std_1c20:inst|cpu:the_cpu|ic_fill_tag[13]

--operation mode is normal

S1_ic_fill_tag[13] = AMPP_FUNCTION(QC2__clk0, S1_D_pc[23], F1_data_out, S1_D_ic_fill_starting);

--S1_ic_fill_tag[9] is std_1c20:inst|cpu:the_cpu|ic_fill_tag[9]

--operation mode is normal

S1_ic_fill_tag[9] = AMPP_FUNCTION(QC2__clk0, S1_D_pc[19], F1_data_out, S1_D_ic_fill_starting);

--S1_ic_fill_tag[10] is std_1c20:inst|cpu:the_cpu|ic_fill_tag[10]

--operation mode is normal

S1_ic_fill_tag[10] = AMPP_FUNCTION(QC2__clk0, S1_D_pc[20], F1_data_out, S1_D_ic_fill_starting);

--Y1L134 is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|Equal3~105

--operation mode is normal

Y1L134 = S1_ic_fill_tag[8] & S1_ic_fill_tag[13] & !S1_ic_fill_tag[9] & !S1_ic_fill_tag[10];

--S1_ic_fill_tag[11] is std_1c20:inst|cpu:the_cpu|ic_fill_tag[11]

--operation mode is normal

S1_ic_fill_tag[11] = AMPP_FUNCTION(QC2__clk0, S1_D_pc[21], F1_data_out, S1_D_ic_fill_starting);

--S1_ic_fill_tag[12] is std_1c20:inst|cpu:the_cpu|ic_fill_tag[12]

--operation mode is normal

S1_ic_fill_tag[12] = AMPP_FUNCTION(QC2__clk0, S1_D_pc[22], F1_data_out, S1_D_ic_fill_starting);

--S1_ic_fill_tag[6] is std_1c20:inst|cpu:the_cpu|ic_fill_tag[6]

--operation mode is normal

S1_ic_fill_tag[6] = AMPP_FUNCTION(QC2__clk0, S1_D_pc[16], F1_data_out, S1_D_ic_fill_starting);

--S1_ic_fill_tag[7] is std_1c20:inst|cpu:the_cpu|ic_fill_tag[7]

--operation mode is normal

S1_ic_fill_tag[7] = AMPP_FUNCTION(QC2__clk0, S1_D_pc[17], F1_data_out, S1_D_ic_fill_starting);

--Y1L135 is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|Equal3~106

--operation mode is normal

Y1L135 = !S1_ic_fill_tag[11] & !S1_ic_fill_tag[12] & !S1_ic_fill_tag[6] & !S1_ic_fill_tag[7];

--S1_ic_fill_tag[4] is std_1c20:inst|cpu:the_cpu|ic_fill_tag[4]

--operation mode is normal

S1_ic_fill_tag[4] = AMPP_FUNCTION(QC2__clk0, S1_D_pc[14], F1_data_out, S1_D_ic_fill_starting);

--S1_ic_fill_tag[5] is std_1c20:inst|cpu:the_cpu|ic_fill_tag[5]

--operation mode is normal

S1_ic_fill_tag[5] = AMPP_FUNCTION(QC2__clk0, S1_D_pc[15], F1_data_out, S1_D_ic_fill_starting);

--Y1L136 is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|Equal3~107

--operation mode is normal

Y1L136 = S1_ic_fill_tag[4] & (!S1_ic_fill_tag[5]);

--Y1L247 is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|lan91c111_s1_in_a_read_cycle~60

--operation mode is normal

Y1L247 = S1_internal_i_read & Y1L134 & Y1L135 & Y1L136;

--Y1_ext_ram_bus_avalon_slave_slavearbiterlockenable is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_avalon_slave_slavearbiterlockenable

--operation mode is normal

Y1_ext_ram_bus_avalon_slave_slavearbiterlockenable_lut_out = Y1L294 & (Y1L196 & Y1_ext_ram_bus_avalon_slave_slavearbiterlockenable # !Y1L196 & (Y1L207)) # !Y1L294 & Y1_ext_ram_bus_avalon_slave_slavearbiterlockenable;

Y1_ext_ram_bus_avalon_slave_slavearbiterlockenable = DFFEAS(Y1_ext_ram_bus_avalon_slave_slavearbiterlockenable_lut_out, QC2__clk0, F1_data_out, , , , , , );

--QB1L1 is std_1c20:inst|seven_seg_pio_s1_arbitrator:the_seven_seg_pio_s1|internal_cpu_data_master_requests_seven_seg_pio_s1~0

--operation mode is normal

QB1L1 = S1_internal_d_write # S1_internal_d_read;

--Y1L76 is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|cpu_data_master_requests_ext_ram_s1~338

--operation mode is normal

Y1L76 = S1_M_alu_result[25] & (!S1_M_alu_result[22] & !S1_M_alu_result[21]);

--Y1_last_cycle_cpu_data_master_granted_slave_ext_ram_s1 is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|last_cycle_cpu_data_master_granted_slave_ext_ram_s1

--operation mode is normal

Y1_last_cycle_cpu_data_master_granted_slave_ext_ram_s1_lut_out = Y1L74 & Y1L76 & !S1_M_alu_result[20] & Y1L4;

Y1_last_cycle_cpu_data_master_granted_slave_ext_ram_s1 = DFFEAS(Y1_last_cycle_cpu_data_master_granted_slave_ext_ram_s1_lut_out, QC2__clk0, F1_data_out, , , , , , );

--Y1L48 is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|cpu_data_master_continuerequest~3

--operation mode is normal

Y1L48 = Y1L74 & Y1L76 & Y1_last_cycle_cpu_data_master_granted_slave_ext_ram_s1 & !S1_M_alu_result[20];

--Y1_last_cycle_cpu_data_master_granted_slave_ext_flash_s1 is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|last_cycle_cpu_data_master_granted_slave_ext_flash_s1

--operation mode is normal

Y1_last_cycle_cpu_data_master_granted_slave_ext_flash_s1_lut_out = Y1_cpu_data_master_requests_ext_flash_s1 & (Y1L182 # Y1_last_cycle_cpu_data_master_granted_slave_ext_flash_s1 & !Y1_ext_ram_bus_avalon_slave_arbitration_holdoff_internal);

Y1_last_cycle_cpu_data_master_granted_slave_ext_flash_s1 = DFFEAS(Y1_last_cycle_cpu_data_master_granted_slave_ext_flash_s1_lut_out, QC2__clk0, F1_data_out, , , , , , );

--Y1_cpu_data_master_requests_ext_flash_s1 is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|cpu_data_master_requests_ext_flash_s1

--operation mode is normal

Y1_cpu_data_master_requests_ext_flash_s1 = QB1L1 & !S1_M_alu_result[24] & !S1_M_alu_result[25] & !S1_M_alu_result[23];

--Y1L47 is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|cpu_data_master_continuerequest~1

--operation mode is normal

Y1L47 = Y1_last_cycle_cpu_data_master_granted_slave_ext_flash_s1 & Y1_cpu_data_master_requests_ext_flash_s1;

--Y1_last_cycle_cpu_data_master_granted_slave_lan91c111_s1 is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|last_cycle_cpu_data_master_granted_slave_lan91c111_s1

--operation mode is normal

Y1_last_cycle_cpu_data_master_granted_slave_lan91c111_s1_lut_out = Y1L78 & (Y1L178 # Y1_last_cycle_cpu_data_master_granted_slave_lan91c111_s1 & !Y1_ext_ram_bus_avalon_slave_arbitration_holdoff_internal);

Y1_last_cycle_cpu_data_master_granted_slave_lan91c111_s1 = DFFEAS(Y1_last_cycle_cpu_data_master_granted_slave_lan91c111_s1_lut_out, QC2__clk0, F1_data_out, , , , , , );

--Y1L77 is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|cpu_data_master_requests_lan91c111_s1~349

--operation mode is normal

Y1L77 = S1_M_alu_result[16] & !S1_M_alu_result[19] & !S1_M_alu_result[18] & !S1_M_alu_result[17];

--Y1L78 is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|cpu_data_master_requests_lan91c111_s1~350

--operation mode is normal

Y1L78 = S1_M_alu_result[20] & Y1L74 & Y1L76 & Y1L77;

--Y1L49 is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|cpu_data_master_continuerequest~103

--operation mode is normal

Y1L49 = Y1L48 # Y1L47 # Y1_last_cycle_cpu_data_master_granted_slave_lan91c111_s1 & Y1L78;

--WE1_fifo_contains_ones_n is std_1c20:inst|sdram_s1_arbitrator:the_sdram_s1|rdv_fifo_for_cpu_instruction_master_to_sdram_s1_module:rdv_fifo_for_cpu_instruction_master_to_sdram_s1|fifo_contains_ones_n

--operation mode is normal

WE1_fifo_contains_ones_n_lut_out = WE1L2 # WE1L3 # WE1L4 # WE1L6;

WE1_fifo_contains_ones_n = DFFEAS(WE1_fifo_contains_ones_n_lut_out, QC2__clk0, F1_data_out, , WE1L27, , , , );

--U1_internal_cpu_instruction_master_latency_counter[0] is std_1c20:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|internal_cpu_instruction_master_latency_counter[0]

--operation mode is normal

U1_internal_cpu_instruction_master_latency_counter[0]_lut_out = U1L170 & (!U1L131 # !U1L133 # !S1_internal_i_read);

U1_internal_cpu_instruction_master_latency_counter[0] = DFFEAS(U1_internal_cpu_instruction_master_latency_counter[0]_lut_out, QC2__clk0, F1_data_out, , , , , , );

--U1_internal_cpu_instruction_master_latency_counter[1] is std_1c20:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|internal_cpu_instruction_master_latency_counter[1]

--operation mode is normal

U1_internal_cpu_instruction_master_latency_counter[1]_lut_out = S1_internal_i_read & (U1L132 & U1L173 # !U1L132 & (U1L174)) # !S1_internal_i_read & (U1L174);

U1_internal_cpu_instruction_master_latency_counter[1] = DFFEAS(U1_internal_cpu_instruction_master_latency_counter[1]_lut_out, QC2__clk0, F1_data_out, , , , , , );

--Y1L208 is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|internal_cpu_instruction_master_qualified_request_ext_ram_s1~95

--operation mode is normal

Y1L208 = S1_internal_i_read & (WE1_fifo_contains_ones_n # U1_internal_cpu_instruction_master_latency_counter[0] & U1_internal_cpu_instruction_master_latency_counter[1]);

--Y1L248 is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|lan91c111_s1_in_a_read_cycle~61

--operation mode is normal

Y1L248 = Y1L247 & !Y1L208 & (!Y1L49 # !Y1_ext_ram_bus_avalon_slave_slavearbiterlockenable);

--Y1L9 is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|Add2~306

--operation mode is arithmetic

Y1L9 = Y1L5 $ !Y1L248;

--Y1L10 is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|Add2~307

--operation mode is arithmetic

Y1L10 = CARRY(Y1L5 & !Y1L248);

--Y1L11 is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|Add2~308

--operation mode is arithmetic

Y1L11_carry_eqn = Y1L30;

Y1L11 = Y1L11_carry_eqn $ (!Y1L209 & Y1L247);

--Y1L12 is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|Add2~309

--operation mode is arithmetic

Y1L12 = CARRY(!Y1L30 & (Y1L209 # !Y1L247));

--Y1L84 is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|cpu_instruction_master_granted_lan91c111_s1~80

--operation mode is normal

Y1L84 = Y1L248 & (Y1L9 # Y1L11);

--Y1_cpu_data_master_read_data_valid_lan91c111_s1_shift_register[0] is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|cpu_data_master_read_data_valid_lan91c111_s1_shift_register[0]

--operation mode is normal

Y1_cpu_data_master_read_data_valid_lan91c111_s1_shift_register[0]_lut_out = S1_internal_d_read & Y1L52 & Y1L95;

Y1_cpu_data_master_read_data_valid_lan91c111_s1_shift_register[0] = DFFEAS(Y1_cpu_data_master_read_data_valid_lan91c111_s1_shift_register[0]_lut_out, QC2__clk0, F1_data_out, , , , , , );

--Y1_cpu_data_master_read_data_valid_lan91c111_s1_shift_register[1] is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|cpu_data_master_read_data_valid_lan91c111_s1_shift_register[1]

--operation mode is normal

Y1_cpu_data_master_read_data_valid_lan91c111_s1_shift_register[1]_lut_out = Y1_cpu_data_master_read_data_valid_lan91c111_s1_shift_register[0];

Y1_cpu_data_master_read_data_valid_lan91c111_s1_shift_register[1] = DFFEAS(Y1_cpu_data_master_read_data_valid_lan91c111_s1_shift_register[1]_lut_out, QC2__clk0, F1_data_out, , , , , , );

--Y1L60 is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|cpu_data_master_qualified_request_lan91c111_s1~127

--operation mode is normal

Y1L60 = !Y1_cpu_data_master_read_data_valid_lan91c111_s1_shift_register[0] & !Y1_cpu_data_master_read_data_valid_lan91c111_s1_shift_register[1] # !S1_internal_d_read;

--Y1L287 is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|p1_read_n_to_the_ext_ram~60

--operation mode is normal

Y1L287 = S1_ic_fill_tag[13] & (!S1_ic_fill_tag[9] & !S1_ic_fill_tag[10]);

--Y1_last_cycle_cpu_instruction_master_granted_slave_ext_ram_s1 is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|last_cycle_cpu_instruction_master_granted_slave_ext_ram_s1

--operation mode is normal

Y1_last_cycle_cpu_instruction_master_granted_slave_ext_ram_s1_lut_out = Y1L288 & (Y1L184 # Y1_last_cycle_cpu_instruction_master_granted_slave_ext_ram_s1 & !Y1_ext_ram_bus_avalon_slave_arbitration_holdoff_internal);

Y1_last_cycle_cpu_instruction_master_granted_slave_ext_ram_s1 = DFFEAS(Y1_last_cycle_cpu_instruction_master_granted_slave_ext_ram_s1_lut_out, QC2__clk0, F1_data_out, , , , , , );

--Y1L96 is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|cpu_instruction_master_requests_ext_flash_s1~35

--operation mode is normal

Y1L96 = S1_internal_i_read & (!S1_ic_fill_tag[11] & !S1_ic_fill_tag[12]);

--Y1L80 is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|cpu_instruction_master_continuerequest~3

--operation mode is normal

Y1L80 = Y1L287 & Y1_last_cycle_cpu_instruction_master_granted_slave_ext_ram_s1 & Y1L96 & !S1_ic_fill_tag[8];

--Y1_last_cycle_cpu_instruction_master_granted_slave_ext_flash_s1 is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|last_cycle_cpu_instruction_master_granted_slave_ext_flash_s1

--operation mode is normal

Y1_last_cycle_cpu_instruction_master_granted_slave_ext_flash_s1_lut_out = Y1L97 & (Y1L180 # Y1_last_cycle_cpu_instruction_master_granted_slave_ext_flash_s1 & !Y1_ext_ram_bus_avalon_slave_arbitration_holdoff_internal);

Y1_last_cycle_cpu_instruction_master_granted_slave_ext_flash_s1 = DFFEAS(Y1_last_cycle_cpu_instruction_master_granted_slave_ext_flash_s1_lut_out, QC2__clk0, F1_data_out, , , , , , );

--Y1L97 is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|cpu_instruction_master_requests_ext_flash_s1~36

--operation mode is normal

Y1L97 = S1_internal_i_read & !S1_ic_fill_tag[13] & !S1_ic_fill_tag[11] & !S1_ic_fill_tag[12];

--Y1L79 is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|cpu_instruction_master_continuerequest~1

--operation mode is normal

Y1L79 = Y1_last_cycle_cpu_instruction_master_granted_slave_ext_flash_s1 & Y1L97;

--Y1_last_cycle_cpu_instruction_master_granted_slave_lan91c111_s1 is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|last_cycle_cpu_instruction_master_granted_slave_lan91c111_s1

--operation mode is normal

Y1_last_cycle_cpu_instruction_master_granted_slave_lan91c111_s1_lut_out = Y1L247 & (Y1L176 # Y1_last_cycle_cpu_instruction_master_granted_slave_lan91c111_s1 & !Y1_ext_ram_bus_avalon_slave_arbitration_holdoff_internal);

Y1_last_cycle_cpu_instruction_master_granted_slave_lan91c111_s1 = DFFEAS(Y1_last_cycle_cpu_instruction_master_granted_slave_lan91c111_s1_lut_out, QC2__clk0, F1_data_out, , , , , , );

--Y1L81 is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|cpu_instruction_master_continuerequest~57

--operation mode is normal

Y1L81 = Y1L80 # Y1L79 # Y1L247 & Y1_last_cycle_cpu_instruction_master_granted_slave_lan91c111_s1;

--Y1L61 is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|cpu_data_master_qualified_request_lan91c111_s1~128

--operation mode is normal

Y1L61 = Y1L78 & Y1L60 & (!Y1L81 # !Y1_ext_ram_bus_avalon_slave_slavearbiterlockenable);

--Y1L13 is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|Add2~310

--operation mode is arithmetic

Y1L13_carry_eqn = Y1L10;

Y1L13 = Y1_ext_ram_bus_avalon_slave_arb_addend[1] $ Y1L61 $ !Y1L13_carry_eqn;

--Y1L14 is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|Add2~311

--operation mode is arithmetic

Y1L14 = CARRY(Y1_ext_ram_bus_avalon_slave_arb_addend[1] & Y1L61 & !Y1L10 # !Y1_ext_ram_bus_avalon_slave_arb_addend[1] & (Y1L61 # !Y1L10));

--Y1L15 is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|Add2~312

--operation mode is arithmetic

Y1L15_carry_eqn = Y1L12;

Y1L15 = Y1L61 $ (!Y1L15_carry_eqn);

--Y1L16 is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|Add2~313

--operation mode is arithmetic

Y1L16 = CARRY(Y1L61 # !Y1L12);

--Y1L52 is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|cpu_data_master_granted_lan91c111_s1~149

--operation mode is normal

Y1L52 = Y1L61 & (Y1L13 # Y1L15);

--Y1_d1_ext_ram_bus_avalon_slave_end_xfer is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_ext_ram_bus_avalon_slave_end_xfer

--operation mode is normal

Y1_d1_ext_ram_bus_avalon_slave_end_xfer_lut_out = Y1L196;

Y1_d1_ext_ram_bus_avalon_slave_end_xfer = DFFEAS(Y1_d1_ext_ram_bus_avalon_slave_end_xfer_lut_out, QC2__clk0, F1_data_out, , , , , , );

--T1_internal_cpu_data_master_dbs_address[1] is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|internal_cpu_data_master_dbs_address[1]

--operation mode is normal

T1_internal_cpu_data_master_dbs_address[1]_lut_out = T1_internal_cpu_data_master_dbs_address[1] $ (Y1_cpu_data_master_requests_ext_flash_s1 & T1_internal_cpu_data_master_dbs_address[0] & T1L293);

T1_internal_cpu_data_master_dbs_address[1] = DFFEAS(T1_internal_cpu_data_master_dbs_address[1]_lut_out, QC2__clk0, F1_data_out, , , , , , );

--S1_M_mem_byte_en[3] is std_1c20:inst|cpu:the_cpu|M_mem_byte_en[3]

--operation mode is normal

S1_M_mem_byte_en[3] = AMPP_FUNCTION(QC2__clk0, S1_E_iw[4], YC1_result[1], YC1_result[0], S1_E_iw[3], F1_data_out, S1_W_stall);

--S1_M_mem_byte_en[2] is std_1c20:inst|cpu:the_cpu|M_mem_byte_en[2]

--operation mode is normal

S1_M_mem_byte_en[2] = AMPP_FUNCTION(QC2__clk0, S1_E_iw[4], YC1_result[1], S1_E_iw[3], YC1_result[0], F1_data_out, S1_W_stall);

--T1_internal_cpu_data_master_dbs_address[0] is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|internal_cpu_data_master_dbs_address[0]

--operation mode is normal

T1_internal_cpu_data_master_dbs_address[0]_lut_out = T1_internal_cpu_data_master_dbs_address[0] $ (Y1_cpu_data_master_requests_ext_flash_s1 & T1L293);

T1_internal_cpu_data_master_dbs_address[0] = DFFEAS(T1_internal_cpu_data_master_dbs_address[0]_lut_out, QC2__clk0, F1_data_out, , , , , , );

--Y1L45 is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|cpu_data_master_byteenable_ext_flash_s1~310

--operation mode is normal

Y1L45 = T1_internal_cpu_data_master_dbs_address[1] & (T1_internal_cpu_data_master_dbs_address[0] & S1_M_mem_byte_en[3] # !T1_internal_cpu_data_master_dbs_address[0] & (S1_M_mem_byte_en[2]));

--S1_M_mem_byte_en[1] is std_1c20:inst|cpu:the_cpu|M_mem_byte_en[1]

--operation mode is normal

S1_M_mem_byte_en[1] = AMPP_FUNCTION(QC2__clk0, S1_E_iw[4], YC1_result[0], S1_E_iw[3], YC1_result[1], F1_data_out, S1_W_stall);

--Y1L46 is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|cpu_data_master_byteenable_ext_flash_s1~311

--operation mode is normal

Y1L46 = !T1_internal_cpu_data_master_dbs_address[1] & (T1_internal_cpu_data_master_dbs_address[0] & S1_M_mem_byte_en[1] # !T1_internal_cpu_data_master_dbs_address[0] & (S1_M_mem_byte_en[0]));

--T1_internal_cpu_data_master_no_byte_enables_and_last_term is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|internal_cpu_data_master_no_byte_enables_and_last_term

--operation mode is normal

T1_internal_cpu_data_master_no_byte_enables_and_last_term_lut_out = S1_internal_d_write & T1_internal_cpu_data_master_dbs_address[1] & T1_internal_cpu_data_master_dbs_address[0] & !S1_M_mem_byte_en[3];

T1_internal_cpu_data_master_no_byte_enables_and_last_term = DFFEAS(T1_internal_cpu_data_master_no_byte_enables_and_last_term_lut_out, QC2__clk0, F1_data_out, , , , , , );

--Y1L53 is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|cpu_data_master_qualified_request_ext_flash_s1~149

--operation mode is normal

Y1L53 = !T1_internal_cpu_data_master_no_byte_enables_and_last_term & (Y1L45 # Y1L46) # !S1_internal_d_write;

--Y1_cpu_data_master_read_data_valid_ext_flash_s1_shift_register[1] is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|cpu_data_master_read_data_valid_ext_flash_s1_shift_register[1]

--operation mode is normal

Y1_cpu_data_master_read_data_valid_ext_flash_s1_shift_register[1]_lut_out = Y1_cpu_data_master_read_data_valid_ext_flash_s1_shift_register[0];

Y1_cpu_data_master_read_data_valid_ext_flash_s1_shift_register[1] = DFFEAS(Y1_cpu_data_master_read_data_valid_ext_flash_s1_shift_register[1]_lut_out, QC2__clk0, F1_data_out, , , , , , );

--Y1_cpu_data_master_read_data_valid_ext_flash_s1_shift_register[0] is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|cpu_data_master_read_data_valid_ext_flash_s1_shift_register[0]

--operation mode is normal

Y1_cpu_data_master_read_data_valid_ext_flash_s1_shift_register[0]_lut_out = Y1L137 & Y1L66 & (Y1_d1_ext_ram_bus_avalon_slave_end_xfer # Y1L194);

Y1_cpu_data_master_read_data_valid_ext_flash_s1_shift_register[0] = DFFEAS(Y1_cpu_data_master_read_data_valid_ext_flash_s1_shift_register[0]_lut_out, QC2__clk0, F1_data_out, , , , , , );

--Y1L54 is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|cpu_data_master_qualified_request_ext_flash_s1~150

--operation mode is normal

Y1L54 = Y1_cpu_data_master_requests_ext_flash_s1 & (!Y1_cpu_data_master_read_data_valid_ext_flash_s1_shift_register[1] & !Y1_cpu_data_master_read_data_valid_ext_flash_s1_shift_register[0] # !S1_internal_d_read);

--Y1L55 is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|cpu_data_master_qualified_request_ext_flash_s1~151

--operation mode is normal

Y1L55 = Y1L53 & Y1L54 & (!Y1L81 # !Y1_ext_ram_bus_avalon_slave_slavearbiterlockenable);

--Y1_cpu_data_master_read_data_valid_ext_ram_s1_shift_register[1] is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|cpu_data_master_read_data_valid_ext_ram_s1_shift_register[1]

--operation mode is normal

Y1_cpu_data_master_read_data_valid_ext_ram_s1_shift_register[1]_lut_out = Y1_cpu_data_master_read_data_valid_ext_ram_s1_shift_register[0];

Y1_cpu_data_master_read_data_valid_ext_ram_s1_shift_register[1] = DFFEAS(Y1_cpu_data_master_read_data_valid_ext_ram_s1_shift_register[1]_lut_out, QC2__clk0, F1_data_out, , , , , , );

--Y1_cpu_data_master_read_data_valid_ext_ram_s1_shift_register[0] is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|cpu_data_master_read_data_valid_ext_ram_s1_shift_register[0]

--operation mode is normal

Y1_cpu_data_master_read_data_valid_ext_ram_s1_shift_register[0]_lut_out = S1_internal_d_read & Y1L51 & !Y1_cpu_data_master_read_data_valid_ext_ram_s1_shift_register[1] & !Y1_cpu_data_master_read_data_valid_ext_ram_s1_shift_register[0];

Y1_cpu_data_master_read_data_valid_ext_ram_s1_shift_register[0] = DFFEAS(Y1_cpu_data_master_read_data_valid_ext_ram_s1_shift_register[0]_lut_out, QC2__clk0, F1_data_out, , , , , , );

--Y1L56 is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|cpu_data_master_qualified_request_ext_ram_s1~139

--operation mode is normal

Y1L56 = !Y1_cpu_data_master_read_data_valid_ext_ram_s1_shift_register[1] & !Y1_cpu_data_master_read_data_valid_ext_ram_s1_shift_register[0] # !S1_internal_d_read;

--Y1L57 is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|cpu_data_master_qualified_request_ext_ram_s1~140

--operation mode is normal

Y1L57 = Y1L74 & Y1L76 & Y1L56 & !S1_M_alu_result[20];

--T1_internal_cpu_data_master_waitrequest is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|internal_cpu_data_master_waitrequest

--operation mode is normal

T1_internal_cpu_data_master_waitrequest_lut_out = !T1L3 & !T1L4 & !T1L5 & !T1L20;

T1_internal_cpu_data_master_waitrequest = DFFEAS(T1_internal_cpu_data_master_waitrequest_lut_out, QC2__clk0, F1_data_out, , , , , , );

--Y1L58 is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|cpu_data_master_qualified_request_ext_ram_s1~141

--operation mode is normal

Y1L58 = !Y1_write_n_to_the_ext_ram_local & !T1_internal_cpu_data_master_waitrequest # !S1_internal_d_write;

--Y1L59 is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|cpu_data_master_qualified_request_ext_ram_s1~142

--operation mode is normal

Y1L59 = Y1L57 & Y1L58 & (!Y1L81 # !Y1_ext_ram_bus_avalon_slave_slavearbiterlockenable);

--T1L1 is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|A_WE_StdLogicVector~1427

--operation mode is normal

T1L1 = !Y1L61 & !Y1L55 & !Y1L59;

--Y1L288 is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|p1_read_n_to_the_ext_ram~61

--operation mode is normal

Y1L288 = Y1L287 & Y1L96 & (!S1_ic_fill_tag[8]);

--Y1L289 is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|p1_read_n_to_the_ext_ram~62

--operation mode is normal

Y1L289 = Y1L288 & !Y1L208 & (!Y1L49 # !Y1_ext_ram_bus_avalon_slave_slavearbiterlockenable);

--U1L165 is std_1c20:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|internal_cpu_instruction_master_dbs_address[1]~49

--operation mode is normal

U1L165 = Y1L97 & !Y1L208 & (!Y1L49 # !Y1_ext_ram_bus_avalon_slave_slavearbiterlockenable);

--Y1L194 is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_avalon_slave_begins_xfer~61

--operation mode is normal

Y1L194 = T1L1 & !Y1L248 & !Y1L289 & !U1L165;

--Y1_ext_ram_bus_avalon_slave_begins_xfer is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_avalon_slave_begins_xfer

--operation mode is normal

Y1_ext_ram_bus_avalon_slave_begins_xfer = !Y1_d1_ext_ram_bus_avalon_slave_end_xfer & !Y1L194;

--F1_data_out is std_1c20:inst|std_1c20_reset_sysclk2_domain_synch_module:std_1c20_reset_sysclk2_domain_synch|data_out

--operation mode is normal

F1_data_out_lut_out = F1_data_in_d1;

F1_data_out = DFFEAS(F1_data_out_lut_out, QC2__clk0, !B1L1, , , , , , );

--Y1L17 is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|Add2~314

--operation mode is arithmetic

Y1L17_carry_eqn = Y1L22;

Y1L17 = Y1_ext_ram_bus_avalon_slave_arb_addend[3] $ Y1L55 $ !Y1L17_carry_eqn;

--Y1L18 is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|Add2~315

--operation mode is arithmetic

Y1L18 = CARRY(Y1_ext_ram_bus_avalon_slave_arb_addend[3] & Y1L55 & !Y1L22 # !Y1_ext_ram_bus_avalon_slave_arb_addend[3] & (Y1L55 # !Y1L22));

--Y1L19 is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|Add2~316

--operation mode is arithmetic

Y1L19_carry_eqn = Y1L24;

Y1L19 = Y1L55 $ (!Y1L19_carry_eqn);

--Y1L20 is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|Add2~317

--operation mode is arithmetic

Y1L20 = CARRY(Y1L55 # !Y1L24);

--Y1L139 is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_flash_s1_counter_load_value[1]~166

--operation mode is normal

Y1L139 = S1_internal_d_write & Y1L55 & (Y1L17 # Y1L19);

--Y1_ext_flash_s1_wait_counter[3] is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_flash_s1_wait_counter[3]

--operation mode is normal

Y1_ext_flash_s1_wait_counter[3]_lut_out = Y1L141 # Y1_ext_flash_s1_wait_counter[3] & (Y1_ext_flash_s1_wait_counter[0] # !Y1L290);

Y1_ext_flash_s1_wait_counter[3] = DFFEAS(Y1_ext_flash_s1_wait_counter[3]_lut_out, QC2__clk0, F1_data_out, , , , , , );

--Y1_ext_flash_s1_wait_counter[2] is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_flash_s1_wait_counter[2]

--operation mode is normal

Y1_ext_flash_s1_wait_counter[2]_lut_out = !Y1L137 & !Y1L141 & (Y1_ext_flash_s1_wait_counter[2] $ !Y1L34);

Y1_ext_flash_s1_wait_counter[2] = DFFEAS(Y1_ext_flash_s1_wait_counter[2]_lut_out, QC2__clk0, F1_data_out, , , , , , );

--Y1_ext_flash_s1_wait_counter[1] is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_flash_s1_wait_counter[1]

--operation mode is normal

Y1_ext_flash_s1_wait_counter[1]_lut_out = Y1_ext_ram_bus_avalon_slave_begins_xfer & !Y1_ext_flash_s1_in_a_read_cycle & (Y1L140 # Y1L139) # !Y1_ext_ram_bus_avalon_slave_begins_xfer & Y1L140;

Y1_ext_flash_s1_wait_counter[1] = DFFEAS(Y1_ext_flash_s1_wait_counter[1]_lut_out, QC2__clk0, F1_data_out, , , , , , );

--Y1L290 is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|p1_write_n_to_the_ext_flash~116

--operation mode is normal

Y1L290 = !Y1_ext_flash_s1_wait_counter[2] & !Y1_ext_flash_s1_wait_counter[1];

--Y1_lan91c111_s1_wait_counter[0] is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|lan91c111_s1_wait_counter[0]

--operation mode is normal

Y1_lan91c111_s1_wait_counter[0]_lut_out = Y1L246 # !Y1_lan91c111_s1_wait_counter[0] & !Y1L261 & !Y1L6;

Y1_lan91c111_s1_wait_counter[0] = DFFEAS(Y1_lan91c111_s1_wait_counter[0]_lut_out, QC2__clk0, F1_data_out, , , , , , );

--Y1_lan91c111_s1_wait_counter[3] is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|lan91c111_s1_wait_counter[3]

--operation mode is normal

Y1_lan91c111_s1_wait_counter[3]_lut_out = Y1L32 # Y1_ext_ram_bus_avalon_slave_begins_xfer & (Y1L84 # Y1L197);

Y1_lan91c111_s1_wait_counter[3] = DFFEAS(Y1_lan91c111_s1_wait_counter[3]_lut_out, QC2__clk0, F1_data_out, , , , , , );

--Y1_lan91c111_s1_wait_counter[2] is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|lan91c111_s1_wait_counter[2]

--operation mode is normal

Y1_lan91c111_s1_wait_counter[2]_lut_out = !Y1L245 & Y1L260 & (Y1_lan91c111_s1_wait_counter[2] $ Y1L33);

Y1_lan91c111_s1_wait_counter[2] = DFFEAS(Y1_lan91c111_s1_wait_counter[2]_lut_out, QC2__clk0, F1_data_out, , , , , , );

--Y1_lan91c111_s1_wait_counter[1] is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|lan91c111_s1_wait_counter[1]

--operation mode is normal

Y1_lan91c111_s1_wait_counter[1]_lut_out = !Y1L245 & (Y1_lan91c111_s1_wait_counter[0] & (Y1_lan91c111_s1_wait_counter[1]) # !Y1_lan91c111_s1_wait_counter[0] & !Y1L261 & !Y1_lan91c111_s1_wait_counter[1]);

Y1_lan91c111_s1_wait_counter[1] = DFFEAS(Y1_lan91c111_s1_wait_counter[1]_lut_out, QC2__clk0, F1_data_out, , , , , , );

--Y1L260 is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|LessThan1~90

--operation mode is normal

Y1L260 = Y1_lan91c111_s1_wait_counter[0] # Y1_lan91c111_s1_wait_counter[3] # Y1_lan91c111_s1_wait_counter[2] # Y1_lan91c111_s1_wait_counter[1];

--Y1L66 is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|cpu_data_master_read_data_valid_ext_flash_s1_shift_register_in~19

--operation mode is normal

Y1L66 = S1_internal_d_read & Y1L55 & (Y1L17 # Y1L19);

--Y1L21 is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|Add2~318

--operation mode is arithmetic

Y1L21_carry_eqn = Y1L14;

Y1L21 = Y1_ext_ram_bus_avalon_slave_arb_addend[2] $ U1L165 $ Y1L21_carry_eqn;

--Y1L22 is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|Add2~319

--operation mode is arithmetic

Y1L22 = CARRY(Y1_ext_ram_bus_avalon_slave_arb_addend[2] & (!Y1L14 # !U1L165) # !Y1_ext_ram_bus_avalon_slave_arb_addend[2] & !U1L165 & !Y1L14);

--Y1L23 is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|Add2~320

--operation mode is arithmetic

Y1L23_carry_eqn = Y1L16;

Y1L23 = Y1L23_carry_eqn $ (!Y1L209 & Y1L97);

--Y1L24 is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|Add2~321

--operation mode is arithmetic

Y1L24 = CARRY(!Y1L16 & (Y1L209 # !Y1L97));

--Y1L82 is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|cpu_instruction_master_granted_ext_flash_s1~46

--operation mode is normal

Y1L82 = U1L165 & (Y1L21 # Y1L23);

--Y1L25 is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|Add2~322

--operation mode is arithmetic

Y1L25_carry_eqn = Y1L18;

Y1L25 = Y1_ext_ram_bus_avalon_slave_arb_addend[4] $ Y1L289 $ Y1L25_carry_eqn;

--Y1L26 is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|Add2~323

--operation mode is arithmetic

Y1L26 = CARRY(Y1_ext_ram_bus_avalon_slave_arb_addend[4] & (!Y1L18 # !Y1L289) # !Y1_ext_ram_bus_avalon_slave_arb_addend[4] & !Y1L289 & !Y1L18);

--Y1L27 is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|Add2~324

--operation mode is arithmetic

Y1L27_carry_eqn = Y1L20;

Y1L27 = Y1L27_carry_eqn $ (Y1L288 & !Y1L209);

--Y1L28 is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|Add2~325

--operation mode is arithmetic

Y1L28 = CARRY(!Y1L20 & (Y1L209 # !Y1L288));

--Y1L83 is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|cpu_instruction_master_granted_ext_ram_s1~39

--operation mode is normal

Y1L83 = Y1L289 & (Y1L25 # Y1L27);

--Y1L29 is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|Add2~326

--operation mode is arithmetic

Y1L29_carry_eqn = Y1L26;

Y1L29 = Y1_ext_ram_bus_avalon_slave_arb_addend[5] $ Y1L59 $ !Y1L29_carry_eqn;

--Y1L30 is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|Add2~327

--operation mode is arithmetic

Y1L30 = CARRY(Y1_ext_ram_bus_avalon_slave_arb_addend[5] & Y1L59 & !Y1L26 # !Y1_ext_ram_bus_avalon_slave_arb_addend[5] & (Y1L59 # !Y1L26));

--Y1L31 is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|Add2~328

--operation mode is normal

Y1L31_carry_eqn = Y1L28;

Y1L31 = Y1L59 $ (!Y1L31_carry_eqn);

--Y1L51 is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|cpu_data_master_granted_ext_ram_s1~90

--operation mode is normal

Y1L51 = Y1L59 & (Y1L29 # Y1L31);

--Y1L281 is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|p1_ext_ram_bus_address[1]~3405

--operation mode is normal

Y1L281 = !Y1L82 & (!Y1L17 & !Y1L19 # !Y1L55);

--KB1_m_state[6] is std_1c20:inst|sdram:the_sdram|m_state[6]

--operation mode is normal

KB1_m_state[6]_lut_out = KB1L279 # KB1L299 & (KB1L280 # KB1L283);

KB1_m_state[6] = DFFEAS(KB1_m_state[6]_lut_out, QC2__clk0, F1_data_out, , , , , , );

--KB1_m_state[1] is std_1c20:inst|sdram:the_sdram|m_state[1]

--operation mode is normal

KB1_m_state[1]_lut_out = KB1L311 # KB1L312 & (KB1L285 # KB1L314);

KB1_m_state[1] = DFFEAS(KB1_m_state[1]_lut_out, QC2__clk0, F1_data_out, , , , , , );

--KB1_m_state[8] is std_1c20:inst|sdram:the_sdram|m_state[8]

--operation mode is normal

KB1_m_state[8]_lut_out = KB1_m_state[8] $ (KB1L547 & KB1L275 & KB1L274);

KB1_m_state[8] = DFFEAS(KB1_m_state[8]_lut_out, QC2__clk0, F1_data_out, , , , , , );

--KB1_m_state[5] is std_1c20:inst|sdram:the_sdram|m_state[5]

--operation mode is normal

KB1_m_state[5]_lut_out = KB1L287 # KB1L284 & (KB1L285 # KB1L288);

KB1_m_state[5] = DFFEAS(KB1_m_state[5]_lut_out, QC2__clk0, F1_data_out, , , , , , );

--KB1_m_state[2] is std_1c20:inst|sdram:the_sdram|m_state[2]

--operation mode is normal

KB1_m_state[2]_lut_out = KB1L300 # KB1L301 & (KB1L305 # KB1L308);

KB1_m_state[2] = DFFEAS(KB1_m_state[2]_lut_out, QC2__clk0, F1_data_out, , , , , , );

--KB1L424 is std_1c20:inst|sdram:the_sdram|Mux104~1605

--operation mode is normal

KB1L424 = !KB1_m_state[8] & !KB1_m_state[5] & !KB1_m_state[2];

--KB1L262 is std_1c20:inst|sdram:the_sdram|Mux19~1736

--operation mode is normal

KB1L262 = KB1_m_state[6] # KB1_m_state[1] # !KB1L424;

--KB1_m_state[7] is std_1c20:inst|sdram:the_sdram|m_state[7]

--operation mode is normal

KB1_m_state[7]_lut_out = KB1L277 # KB1_m_state[7] & (!KB1L257 # !KB1L256);

KB1_m_state[7] = DFFEAS(KB1_m_state[7]_lut_out, QC2__clk0, F1_data_out, , , , , , );

--KB1_m_state[4] is std_1c20:inst|sdram:the_sdram|m_state[4]

--operation mode is normal

KB1_m_state[4]_lut_out = KB1L289 # KB1L547 & KB1L293 & KB1L365;

KB1_m_state[4] = DFFEAS(KB1_m_state[4]_lut_out, QC2__clk0, F1_data_out, , , , , , );

--KB1_m_state[3] is std_1c20:inst|sdram:the_sdram|m_state[3]

--operation mode is normal

KB1_m_state[3]_lut_out = KB1L295 # KB1L547 & KB1L296 & KB1L297;

KB1_m_state[3] = DFFEAS(KB1_m_state[3]_lut_out, QC2__clk0, F1_data_out, , , , , , );

--KB1_m_state[0] is std_1c20:inst|sdram:the_sdram|m_state[0]

--operation mode is normal

KB1_m_state[0]_lut_out = !KB1L315 & (KB1_m_state[0] # !KB1L574 & KB1L30);

KB1_m_state[0] = DFFEAS(KB1_m_state[0]_lut_out, QC2__clk0, F1_data_out, , , , , , );

--KB1L263 is std_1c20:inst|sdram:the_sdram|Mux19~1737

--operation mode is normal

KB1L263 = KB1_m_state[0] & (!KB1_m_state[4] & !KB1_m_state[3] # !KB1_m_state[7]);

--KB1_f_pop is std_1c20:inst|sdram:the_sdram|f_pop

--operation mode is normal

KB1_f_pop_lut_out = KB1L392 & (KB1L394 # KB1L304 & KB1_m_state[0]);

KB1_f_pop = DFFEAS(KB1_f_pop_lut_out, QC2__clk0, F1_data_out, , , , , , );

--TE1_rd_address is std_1c20:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|rd_address

--operation mode is normal

TE1_rd_address_lut_out = TE1_rd_address $ (!KB1L554 & KB1_f_pop & TE1L127);

TE1_rd_address = DFFEAS(TE1_rd_address_lut_out, QC2__clk0, F1_data_out, , , , , , );

--TE1_entry_0[45] is std_1c20:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_0[45]

--operation mode is normal

TE1_entry_0[45]_lut_out = NB1L38;

TE1_entry_0[45] = DFFEAS(TE1_entry_0[45]_lut_out, QC2__clk0, VCC, , TE1L62, , , , );

--TE1_entry_1[45] is std_1c20:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_1[45]

--operation mode is normal

TE1_entry_1[45]_lut_out = NB1L38;

TE1_entry_1[45] = DFFEAS(TE1_entry_1[45]_lut_out, QC2__clk0, VCC, , TE1L123, , , , );

--KB1_active_addr[9] is std_1c20:inst|sdram:the_sdram|active_addr[9]

--operation mode is normal

KB1_active_addr[9]_lut_out = F1_data_out & (KB1L395 & KB1L422 # !KB1L395 & (KB1_active_addr[9])) # !F1_data_out & (KB1_active_addr[9]);

KB1_active_addr[9] = DFFEAS(KB1_active_addr[9]_lut_out, QC2__clk0, VCC, , , , , , );

--KB1L106 is std_1c20:inst|sdram:the_sdram|Equal4~471

--operation mode is normal

KB1L106 = KB1_active_addr[9] $ (TE1_rd_address & (TE1_entry_1[45]) # !TE1_rd_address & TE1_entry_0[45]);

--TE1_entry_0[44] is std_1c20:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_0[44]

--operation mode is normal

TE1_entry_0[44]_lut_out = NB1L37;

TE1_entry_0[44] = DFFEAS(TE1_entry_0[44]_lut_out, QC2__clk0, VCC, , TE1L62, , , , );

--TE1_entry_1[44] is std_1c20:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_1[44]

--operation mode is normal

TE1_entry_1[44]_lut_out = NB1L37;

TE1_entry_1[44] = DFFEAS(TE1_entry_1[44]_lut_out, QC2__clk0, VCC, , TE1L123, , , , );

--KB1_active_addr[8] is std_1c20:inst|sdram:the_sdram|active_addr[8]

--operation mode is normal

KB1_active_addr[8]_lut_out = KB1L12 & (KB1L14 & (TE1L173) # !KB1L14 & KB1_active_addr[8]) # !KB1L12 & KB1_active_addr[8];

KB1_active_addr[8] = DFFEAS(KB1_active_addr[8]_lut_out, QC2__clk0, VCC, , , , , , );

--KB1L104 is std_1c20:inst|sdram:the_sdram|Equal3~78

--operation mode is normal

KB1L104 = KB1_active_addr[8] $ (TE1_rd_address & (TE1_entry_1[44]) # !TE1_rd_address & TE1_entry_0[44]);

--TE1_entry_0[50] is std_1c20:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_0[50]

--operation mode is normal

TE1_entry_0[50]_lut_out = NB1L43;

TE1_entry_0[50] = DFFEAS(TE1_entry_0[50]_lut_out, QC2__clk0, VCC, , TE1L62, , , , );

--TE1_entry_1[50] is std_1c20:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_1[50]

--operation mode is normal

TE1_entry_1[50]_lut_out = NB1L43;

TE1_entry_1[50] = DFFEAS(TE1_entry_1[50]_lut_out, QC2__clk0, VCC, , TE1L123, , , , );

--KB1_active_addr[14] is std_1c20:inst|sdram:the_sdram|active_addr[14]

--operation mode is normal

KB1_active_addr[14]_lut_out = F1_data_out & (KB1L395 & KB1L410 # !KB1L395 & (KB1_active_addr[14])) # !F1_data_out & (KB1_active_addr[14]);

KB1_active_addr[14] = DFFEAS(KB1_active_addr[14]_lut_out, QC2__clk0, VCC, , , , , , );

--KB1L107 is std_1c20:inst|sdram:the_sdram|Equal4~472

--operation mode is normal

KB1L107 = KB1_active_addr[14] $ (TE1_rd_address & (TE1_entry_1[50]) # !TE1_rd_address & TE1_entry_0[50]);

--TE1_entry_0[49] is std_1c20:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_0[49]

--operation mode is normal

TE1_entry_0[49]_lut_out = NB1L42;

TE1_entry_0[49] = DFFEAS(TE1_entry_0[49]_lut_out, QC2__clk0, VCC, , TE1L62, , , , );

--TE1_entry_1[49] is std_1c20:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_1[49]

--operation mode is normal

TE1_entry_1[49]_lut_out = NB1L42;

TE1_entry_1[49] = DFFEAS(TE1_entry_1[49]_lut_out, QC2__clk0, VCC, , TE1L123, , , , );

--KB1_active_addr[13] is std_1c20:inst|sdram:the_sdram|active_addr[13]

--operation mode is normal

KB1_active_addr[13]_lut_out = F1_data_out & (KB1L395 & KB1L412 # !KB1L395 & (KB1_active_addr[13])) # !F1_data_out & (KB1_active_addr[13]);

KB1_active_addr[13] = DFFEAS(KB1_active_addr[13]_lut_out, QC2__clk0, VCC, , , , , , );

--KB1L108 is std_1c20:inst|sdram:the_sdram|Equal4~473

--operation mode is normal

KB1L108 = KB1_active_addr[13] $ (TE1_rd_address & (TE1_entry_1[49]) # !TE1_rd_address & TE1_entry_0[49]);

--KB1L550 is std_1c20:inst|sdram:the_sdram|pending~245

--operation mode is normal

KB1L550 = KB1L106 # KB1L104 # KB1L107 # KB1L108;

--TE1_entry_0[47] is std_1c20:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_0[47]

--operation mode is normal

TE1_entry_0[47]_lut_out = NB1L40;

TE1_entry_0[47] = DFFEAS(TE1_entry_0[47]_lut_out, QC2__clk0, VCC, , TE1L62, , , , );

--TE1_entry_1[47] is std_1c20:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_1[47]

--operation mode is normal

TE1_entry_1[47]_lut_out = NB1L40;

TE1_entry_1[47] = DFFEAS(TE1_entry_1[47]_lut_out, QC2__clk0, VCC, , TE1L123, , , , );

--KB1_active_addr[11] is std_1c20:inst|sdram:the_sdram|active_addr[11]

--operation mode is normal

KB1_active_addr[11]_lut_out = F1_data_out & (KB1L395 & KB1L416 # !KB1L395 & (KB1_active_addr[11])) # !F1_data_out & (KB1_active_addr[11]);

KB1_active_addr[11] = DFFEAS(KB1_active_addr[11]_lut_out, QC2__clk0, VCC, , , , , , );

--KB1L109 is std_1c20:inst|sdram:the_sdram|Equal4~474

--operation mode is normal

KB1L109 = KB1_active_addr[11] $ (TE1_rd_address & (TE1_entry_1[47]) # !TE1_rd_address & TE1_entry_0[47]);

--TE1_entry_0[57] is std_1c20:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_0[57]

--operation mode is normal

TE1_entry_0[57]_lut_out = NB1L50;

TE1_entry_0[57] = DFFEAS(TE1_entry_0[57]_lut_out, QC2__clk0, VCC, , TE1L62, , , , );

--TE1_entry_1[57] is std_1c20:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_1[57]

--operation mode is normal

TE1_entry_1[57]_lut_out = NB1L50;

TE1_entry_1[57] = DFFEAS(TE1_entry_1[57]_lut_out, QC2__clk0, VCC, , TE1L123, , , , );

--KB1_active_addr[21] is std_1c20:inst|sdram:the_sdram|active_addr[21]

--operation mode is normal

KB1_active_addr[21]_lut_out = KB1L12 & (KB1L14 & (TE1L174) # !KB1L14 & KB1_active_addr[21]) # !KB1L12 & KB1_active_addr[21];

KB1_active_addr[21] = DFFEAS(KB1_active_addr[21]_lut_out, QC2__clk0, VCC, , , , , , );

--KB1L105 is std_1c20:inst|sdram:the_sdram|Equal3~79

--operation mode is normal

KB1L105 = KB1_active_addr[21] $ (TE1_rd_address & (TE1_entry_1[57]) # !TE1_rd_address & TE1_entry_0[57]);

--TE1_entry_0[52] is std_1c20:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_0[52]

--operation mode is normal

TE1_entry_0[52]_lut_out = NB1L45;

TE1_entry_0[52] = DFFEAS(TE1_entry_0[52]_lut_out, QC2__clk0, VCC, , TE1L62, , , , );

--TE1_entry_1[52] is std_1c20:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_1[52]

--operation mode is normal

TE1_entry_1[52]_lut_out = NB1L45;

TE1_entry_1[52] = DFFEAS(TE1_entry_1[52]_lut_out, QC2__clk0, VCC, , TE1L123, , , , );

--KB1_active_addr[16] is std_1c20:inst|sdram:the_sdram|active_addr[16]

--operation mode is normal

KB1_active_addr[16]_lut_out = F1_data_out & (KB1L395 & KB1L406 # !KB1L395 & (KB1_active_addr[16])) # !F1_data_out & (KB1_active_addr[16]);

KB1_active_addr[16] = DFFEAS(KB1_active_addr[16]_lut_out, QC2__clk0, VCC, , , , , , );

--KB1L110 is std_1c20:inst|sdram:the_sdram|Equal4~475

--operation mode is normal

KB1L110 = KB1_active_addr[16] $ (TE1_rd_address & (TE1_entry_1[52]) # !TE1_rd_address & TE1_entry_0[52]);

--TE1_entry_0[51] is std_1c20:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_0[51]

--operation mode is normal

TE1_entry_0[51]_lut_out = NB1L44;

TE1_entry_0[51] = DFFEAS(TE1_entry_0[51]_lut_out, QC2__clk0, VCC, , TE1L62, , , , );

--TE1_entry_1[51] is std_1c20:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_1[51]

--operation mode is normal

TE1_entry_1[51]_lut_out = NB1L44;

TE1_entry_1[51] = DFFEAS(TE1_entry_1[51]_lut_out, QC2__clk0, VCC, , TE1L123, , , , );

--KB1_active_addr[15] is std_1c20:inst|sdram:the_sdram|active_addr[15]

--operation mode is normal

KB1_active_addr[15]_lut_out = F1_data_out & (KB1L395 & KB1L408 # !KB1L395 & (KB1_active_addr[15])) # !F1_data_out & (KB1_active_addr[15]);

KB1_active_addr[15] = DFFEAS(KB1_active_addr[15]_lut_out, QC2__clk0, VCC, , , , , , );

--KB1L111 is std_1c20:inst|sdram:the_sdram|Equal4~476

--operation mode is normal

KB1L111 = KB1_active_addr[15] $ (TE1_rd_address & (TE1_entry_1[51]) # !TE1_rd_address & TE1_entry_0[51]);

--KB1L551 is std_1c20:inst|sdram:the_sdram|pending~246

--operation mode is normal

KB1L551 = KB1L109 # KB1L105 # KB1L110 # KB1L111;

--TE1_entry_0[53] is std_1c20:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_0[53]

--operation mode is normal

TE1_entry_0[53]_lut_out = NB1L46;

TE1_entry_0[53] = DFFEAS(TE1_entry_0[53]_lut_out, QC2__clk0, VCC, , TE1L62, , , , );

--TE1_entry_1[53] is std_1c20:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_1[53]

--operation mode is normal

TE1_entry_1[53]_lut_out = NB1L46;

TE1_entry_1[53] = DFFEAS(TE1_entry_1[53]_lut_out, QC2__clk0, VCC, , TE1L123, , , , );

--KB1_active_addr[17] is std_1c20:inst|sdram:the_sdram|active_addr[17]

--operation mode is normal

KB1_active_addr[17]_lut_out = F1_data_out & (KB1L395 & KB1L404 # !KB1L395 & (KB1_active_addr[17])) # !F1_data_out & (KB1_active_addr[17]);

KB1_active_addr[17] = DFFEAS(KB1_active_addr[17]_lut_out, QC2__clk0, VCC, , , , , , );

--KB1L112 is std_1c20:inst|sdram:the_sdram|Equal4~477

--operation mode is normal

KB1L112 = KB1_active_addr[17] $ (TE1_rd_address & (TE1_entry_1[53]) # !TE1_rd_address & TE1_entry_0[53]);

--TE1_entry_0[46] is std_1c20:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_0[46]

--operation mode is normal

TE1_entry_0[46]_lut_out = NB1L39;

TE1_entry_0[46] = DFFEAS(TE1_entry_0[46]_lut_out, QC2__clk0, VCC, , TE1L62, , , , );

--TE1_entry_1[46] is std_1c20:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_1[46]

--operation mode is normal

TE1_entry_1[46]_lut_out = NB1L39;

TE1_entry_1[46] = DFFEAS(TE1_entry_1[46]_lut_out, QC2__clk0, VCC, , TE1L123, , , , );

--KB1_active_addr[10] is std_1c20:inst|sdram:the_sdram|active_addr[10]

--operation mode is normal

KB1_active_addr[10]_lut_out = F1_data_out & (KB1L395 & KB1L418 # !KB1L395 & (KB1_active_addr[10])) # !F1_data_out & (KB1_active_addr[10]);

KB1_active_addr[10] = DFFEAS(KB1_active_addr[10]_lut_out, QC2__clk0, VCC, , , , , , );

--KB1L113 is std_1c20:inst|sdram:the_sdram|Equal4~478

--operation mode is normal

KB1L113 = KB1_active_addr[10] $ (TE1_rd_address & (TE1_entry_1[46]) # !TE1_rd_address & TE1_entry_0[46]);

--TE1_entry_0[58] is std_1c20:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_0[58]

--operation mode is normal

TE1_entry_0[58]_lut_out = !NB1_sdram_s1_in_a_write_cycle;

TE1_entry_0[58] = DFFEAS(TE1_entry_0[58]_lut_out, QC2__clk0, VCC, , TE1L62, , , , );

--TE1_entry_1[58] is std_1c20:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_1[58]

--operation mode is normal

TE1_entry_1[58]_lut_out = !NB1_sdram_s1_in_a_write_cycle;

TE1_entry_1[58] = DFFEAS(TE1_entry_1[58]_lut_out, QC2__clk0, VCC, , TE1L123, , , , );

--KB1_active_rnw is std_1c20:inst|sdram:the_sdram|active_rnw

--operation mode is normal

KB1_active_rnw_lut_out = KB1L12 & (KB1L14 & (TE1L175) # !KB1L14 & KB1_active_rnw) # !KB1L12 & KB1_active_rnw;

KB1_active_rnw = DFFEAS(KB1_active_rnw_lut_out, QC2__clk0, VCC, , , , , , );

--KB1L575 is std_1c20:inst|sdram:the_sdram|rnw_match~0

--operation mode is normal

KB1L575 = KB1_active_rnw $ (TE1_rd_address & (TE1_entry_1[58]) # !TE1_rd_address & TE1_entry_0[58]);

--TE1_entry_0[56] is std_1c20:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_0[56]

--operation mode is normal

TE1_entry_0[56]_lut_out = NB1L49;

TE1_entry_0[56] = DFFEAS(TE1_entry_0[56]_lut_out, QC2__clk0, VCC, , TE1L62, , , , );

--TE1_entry_1[56] is std_1c20:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_1[56]

--operation mode is normal

TE1_entry_1[56]_lut_out = NB1L49;

TE1_entry_1[56] = DFFEAS(TE1_entry_1[56]_lut_out, QC2__clk0, VCC, , TE1L123, , , , );

--KB1_active_addr[20] is std_1c20:inst|sdram:the_sdram|active_addr[20]

--operation mode is normal

KB1_active_addr[20]_lut_out = F1_data_out & (KB1L395 & KB1L398 # !KB1L395 & (KB1_active_addr[20])) # !F1_data_out & (KB1_active_addr[20]);

KB1_active_addr[20] = DFFEAS(KB1_active_addr[20]_lut_out, QC2__clk0, VCC, , , , , , );

--KB1L114 is std_1c20:inst|sdram:the_sdram|Equal4~479

--operation mode is normal

KB1L114 = KB1_active_addr[20] $ (TE1_rd_address & (TE1_entry_1[56]) # !TE1_rd_address & TE1_entry_0[56]);

--KB1L552 is std_1c20:inst|sdram:the_sdram|pending~247

--operation mode is normal

KB1L552 = KB1L112 # KB1L113 # KB1L575 # KB1L114;

--TE1_entry_0[54] is std_1c20:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_0[54]

--operation mode is normal

TE1_entry_0[54]_lut_out = NB1L47;

TE1_entry_0[54] = DFFEAS(TE1_entry_0[54]_lut_out, QC2__clk0, VCC, , TE1L62, , , , );

--TE1_entry_1[54] is std_1c20:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_1[54]

--operation mode is normal

TE1_entry_1[54]_lut_out = NB1L47;

TE1_entry_1[54] = DFFEAS(TE1_entry_1[54]_lut_out, QC2__clk0, VCC, , TE1L123, , , , );

--KB1_active_addr[18] is std_1c20:inst|sdram:the_sdram|active_addr[18]

--operation mode is normal

KB1_active_addr[18]_lut_out = F1_data_out & (KB1L395 & KB1L402 # !KB1L395 & (KB1_active_addr[18])) # !F1_data_out & (KB1_active_addr[18]);

KB1_active_addr[18] = DFFEAS(KB1_active_addr[18]_lut_out, QC2__clk0, VCC, , , , , , );

--KB1L115 is std_1c20:inst|sdram:the_sdram|Equal4~480

--operation mode is normal

KB1L115 = KB1_active_addr[18] $ (TE1_rd_address & (TE1_entry_1[54]) # !TE1_rd_address & TE1_entry_0[54]);

--TE1_entry_0[48] is std_1c20:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_0[48]

--operation mode is normal

TE1_entry_0[48]_lut_out = NB1L41;

TE1_entry_0[48] = DFFEAS(TE1_entry_0[48]_lut_out, QC2__clk0, VCC, , TE1L62, , , , );

--TE1_entry_1[48] is std_1c20:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_1[48]

--operation mode is normal

TE1_entry_1[48]_lut_out = NB1L41;

TE1_entry_1[48] = DFFEAS(TE1_entry_1[48]_lut_out, QC2__clk0, VCC, , TE1L123, , , , );

--KB1_active_addr[12] is std_1c20:inst|sdram:the_sdram|active_addr[12]

--operation mode is normal

KB1_active_addr[12]_lut_out = F1_data_out & (KB1L395 & KB1L414 # !KB1L395 & (KB1_active_addr[12])) # !F1_data_out & (KB1_active_addr[12]);

KB1_active_addr[12] = DFFEAS(KB1_active_addr[12]_lut_out, QC2__clk0, VCC, , , , , , );

--KB1L116 is std_1c20:inst|sdram:the_sdram|Equal4~481

--operation mode is normal

KB1L116 = KB1_active_addr[12] $ (TE1_rd_address & (TE1_entry_1[48]) # !TE1_rd_address & TE1_entry_0[48]);

--KB1_active_cs_n is std_1c20:inst|sdram:the_sdram|active_cs_n

--operation mode is normal

KB1_active_cs_n_lut_out = KB1L32 & (KB1_refresh_request # KB1_active_cs_n & !TE1L127) # !KB1L32 & (KB1_active_cs_n);

KB1_active_cs_n = DFFEAS(KB1_active_cs_n_lut_out, QC2__clk0, VCC, , , , , , );

--TE1_entry_0[55] is std_1c20:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_0[55]

--operation mode is normal

TE1_entry_0[55]_lut_out = NB1L48;

TE1_entry_0[55] = DFFEAS(TE1_entry_0[55]_lut_out, QC2__clk0, VCC, , TE1L62, , , , );

--TE1_entry_1[55] is std_1c20:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_1[55]

--operation mode is normal

TE1_entry_1[55]_lut_out = NB1L48;

TE1_entry_1[55] = DFFEAS(TE1_entry_1[55]_lut_out, QC2__clk0, VCC, , TE1L123, , , , );

--KB1_active_addr[19] is std_1c20:inst|sdram:the_sdram|active_addr[19]

--operation mode is normal

KB1_active_addr[19]_lut_out = F1_data_out & (KB1L395 & KB1L400 # !KB1L395 & (KB1_active_addr[19])) # !F1_data_out & (KB1_active_addr[19]);

KB1_active_addr[19] = DFFEAS(KB1_active_addr[19]_lut_out, QC2__clk0, VCC, , , , , , );

--KB1L117 is std_1c20:inst|sdram:the_sdram|Equal4~482

--operation mode is normal

KB1L117 = KB1_active_addr[19] $ (TE1_rd_address & (TE1_entry_1[55]) # !TE1_rd_address & TE1_entry_0[55]);

--KB1L553 is std_1c20:inst|sdram:the_sdram|pending~248

--operation mode is normal

KB1L553 = KB1L115 # KB1L116 # KB1_active_cs_n # KB1L117;

--KB1L554 is std_1c20:inst|sdram:the_sdram|pending~249

--operation mode is normal

KB1L554 = KB1L550 # KB1L551 # KB1L552 # KB1L553;

--TE1_entries[0] is std_1c20:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entries[0]

--operation mode is normal

TE1_entries[0]_lut_out = KB1_f_select $ (KB1L237 & !TE1_entries[1] & !TE1_entries[0] # !KB1L237 & (TE1_entries[0]));

TE1_entries[0] = DFFEAS(TE1_entries[0]_lut_out, QC2__clk0, F1_data_out, , , , , , );

--TE1_entries[1] is std_1c20:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entries[1]

--operation mode is normal

TE1_entries[1]_lut_out = TE1_entries[0] & (TE1_entries[1] $ (!KB1_f_select & KB1L237)) # !TE1_entries[0] & (TE1_entries[1] & !KB1_f_select # !TE1_entries[1] & KB1_f_select & !KB1L237);

TE1_entries[1] = DFFEAS(TE1_entries[1]_lut_out, QC2__clk0, F1_data_out, , , , , , );

--TE1L127 is std_1c20:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|Equal1~96

--operation mode is normal

TE1L127 = TE1_entries[0] # TE1_entries[1];

--KB1L264 is std_1c20:inst|sdram:the_sdram|Mux19~1738

--operation mode is normal

KB1L264 = KB1_m_state[4] $ KB1_m_state[3];

--KB1_init_done is std_1c20:inst|sdram:the_sdram|init_done

--operation mode is normal

KB1_init_done_lut_out = KB1_init_done # KB1_i_state[0] & KB1_i_state[2] & !KB1_i_state[1];

KB1_init_done = DFFEAS(KB1_init_done_lut_out, QC2__clk0, F1_data_out, , , , , , );

--KB1_i_cmd[1] is std_1c20:inst|sdram:the_sdram|i_cmd[1]

--operation mode is normal

KB1_i_cmd[1]_lut_out = KB1_i_state[2] # KB1_i_state[1] & (!KB1_i_state[0]);

KB1_i_cmd[1] = DFFEAS(KB1_i_cmd[1]_lut_out, QC2__clk0, F1_data_out, , KB1L125, , , , );

--KB1L348 is std_1c20:inst|sdram:the_sdram|Mux40~1465

--operation mode is normal

KB1L348 = !KB1_m_state[4] & !KB1_m_state[3];

--KB1L265 is std_1c20:inst|sdram:the_sdram|Mux19~1739

--operation mode is normal

KB1L265 = KB1L263 & !KB1L171 & KB1L264 # !KB1L263 & (KB1L266);

--KB1_i_cmd[3] is std_1c20:inst|sdram:the_sdram|i_cmd[3]

--operation mode is normal

KB1_i_cmd[3]_lut_out = KB1_i_state[0] # KB1_i_state[2] # KB1_i_state[1];

KB1_i_cmd[3] = DFFEAS(KB1_i_cmd[3]_lut_out, QC2__clk0, F1_data_out, , KB1L125, , , , );

--KB1_refresh_request is std_1c20:inst|sdram:the_sdram|refresh_request

--operation mode is normal

KB1_refresh_request_lut_out = KB1_init_done & !KB1_ack_refresh_request & (KB1_refresh_request # KB1L103);

KB1_refresh_request = DFFEAS(KB1_refresh_request_lut_out, QC2__clk0, F1_data_out, , , , , , );

--KB1L245 is std_1c20:inst|sdram:the_sdram|Mux17~1836

--operation mode is normal

KB1L245 = KB1_init_done & (!KB1_refresh_request) # !KB1_init_done & !KB1_i_cmd[3];

--KB1L246 is std_1c20:inst|sdram:the_sdram|Mux17~1837

--operation mode is normal

KB1L246 = !KB1_m_state[3] & !KB1_m_state[8] & !KB1_m_state[5] & !KB1_m_state[1];

--KB1L247 is std_1c20:inst|sdram:the_sdram|Mux17~1838

--operation mode is normal

KB1L247 = KB1_m_state[4] & (!KB1_m_state[0] # !KB1L246) # !KB1_m_state[4] & !KB1_m_state[0] & (KB1L245 # !KB1L246);

--KB1L248 is std_1c20:inst|sdram:the_sdram|Mux17~1839

--operation mode is normal

KB1L248 = KB1_m_state[5] & !KB1_m_state[1] & !KB1_m_state[8] & !KB1_m_state[3] # !KB1_m_state[5] & (KB1_m_state[1] & !KB1_m_state[8] & !KB1_m_state[3] # !KB1_m_state[1] & (KB1_m_state[8] $ KB1_m_state[3]));

--KB1L249 is std_1c20:inst|sdram:the_sdram|Mux17~1840

--operation mode is normal

KB1L249 = KB1_m_state[0] & (KB1_active_cs_n # !KB1_m_state[4] & !KB1L248);

--KB1L250 is std_1c20:inst|sdram:the_sdram|Mux17~1841

--operation mode is normal

KB1L250 = !KB1_m_state[2] & !KB1_m_state[6] & (KB1L247 # KB1L249);

--KB1L251 is std_1c20:inst|sdram:the_sdram|Mux17~1842

--operation mode is normal

KB1L251 = KB1_m_state[0] & !KB1_m_state[2] & (KB1_refresh_request # !KB1_active_cs_n);

--KB1L252 is std_1c20:inst|sdram:the_sdram|Mux17~1843

--operation mode is normal

KB1L252 = KB1_m_state[6] & (KB1_m_state[4] # !KB1L251 # !KB1L246);

--KB1_m_next[7] is std_1c20:inst|sdram:the_sdram|m_next[7]

--operation mode is normal

KB1_m_next[7]_lut_out = KB1_m_state[8] & KB1_m_next[7] & (KB1L321 # !KB1L341) # !KB1_m_state[8] & (KB1L321);

KB1_m_next[7] = DFFEAS(KB1_m_next[7]_lut_out, QC2__clk0, F1_data_out, , KB1L342, , , , );

--KB1_m_next[0] is std_1c20:inst|sdram:the_sdram|m_next[0]

--operation mode is normal

KB1_m_next[0]_lut_out = KB1_m_state[8] & KB1_m_next[0] & (KB1L347 # !KB1L341) # !KB1_m_state[8] & (!KB1L347);

KB1_m_next[0] = DFFEAS(KB1_m_next[0]_lut_out, QC2__clk0, F1_data_out, , KB1L342, , , , );

--KB1_m_next[1] is std_1c20:inst|sdram:the_sdram|m_next[1]

--operation mode is normal

KB1_m_next[1]_lut_out = KB1_m_state[8] & KB1_m_next[1] & (KB1L340 # !KB1L341) # !KB1_m_state[8] & (KB1L340);

KB1_m_next[1] = DFFEAS(KB1_m_next[1]_lut_out, QC2__clk0, F1_data_out, , KB1L342, , , , );

--KB1_m_next[3] is std_1c20:inst|sdram:the_sdram|m_next[3]

--operation mode is normal

KB1_m_next[3]_lut_out = KB1_m_state[7] & KB1_m_next[3] & (KB1L334 # !KB1L448) # !KB1_m_state[7] & (KB1L334);

KB1_m_next[3] = DFFEAS(KB1_m_next[3]_lut_out, QC2__clk0, F1_data_out, , KB1L342, , , , );

--KB1_m_next[4] is std_1c20:inst|sdram:the_sdram|m_next[4]

--operation mode is normal

KB1_m_next[4]_lut_out = KB1_m_state[7] & KB1_m_next[4] & (KB1L327 # !KB1L448) # !KB1_m_state[7] & (KB1L327);

KB1_m_next[4] = DFFEAS(KB1_m_next[4]_lut_out, QC2__clk0, F1_data_out, , KB1L342, , , , );

--KB1L118 is std_1c20:inst|sdram:the_sdram|Equal5~52

--operation mode is normal

KB1L118 = KB1_m_next[0] & !KB1_m_next[1] & !KB1_m_next[3] & !KB1_m_next[4];

--KB1L253 is std_1c20:inst|sdram:the_sdram|Mux17~1844

--operation mode is normal

KB1L253 = KB1_m_state[0] & KB1L246 & (!KB1_m_state[4]);

--KB1L254 is std_1c20:inst|sdram:the_sdram|Mux17~1845

--operation mode is normal

KB1L254 = KB1_active_cs_n & (!KB1L118 # !KB1_m_next[7]) # !KB1L253;

--KB1L255 is std_1c20:inst|sdram:the_sdram|Mux17~1846

--operation mode is normal

KB1L255 = KB1L250 # KB1L252 # KB1_m_state[2] & KB1L254;

--KB1L256 is std_1c20:inst|sdram:the_sdram|Mux17~1847

--operation mode is normal

KB1L256 = KB1_m_state[0] & (!KB1_m_state[2]);

--KB1L257 is std_1c20:inst|sdram:the_sdram|Mux17~1848

--operation mode is normal

KB1L257 = KB1L246 & (!KB1_m_state[4] & !KB1_m_state[6]);

--KB1_i_cmd[2] is std_1c20:inst|sdram:the_sdram|i_cmd[2]

--operation mode is normal

KB1_i_cmd[2]_lut_out = KB1_i_state[2] # KB1_i_state[0] $ KB1_i_state[1];

KB1_i_cmd[2] = DFFEAS(KB1_i_cmd[2]_lut_out, QC2__clk0, F1_data_out, , KB1L125, , , , );

--KB1L284 is std_1c20:inst|sdram:the_sdram|Mux25~1259

--operation mode is normal

KB1L284 = !KB1_m_state[7] & !KB1_m_state[6] & !KB1_m_state[1];

--KB1L258 is std_1c20:inst|sdram:the_sdram|Mux18~1364

--operation mode is normal

KB1L258 = !KB1_m_state[0] & (KB1_init_done # !KB1L284 # !KB1_i_cmd[2]);

--KB1L299 is std_1c20:inst|sdram:the_sdram|Mux28~1625

--operation mode is normal

KB1L299 = !KB1_m_state[7] & !KB1_m_state[1];

--KB1L259 is std_1c20:inst|sdram:the_sdram|Mux18~1365

--operation mode is normal

KB1L259 = KB1_m_state[6] & !KB1L299 # !KB1L424 # !KB1L348;

--KB1L260 is std_1c20:inst|sdram:the_sdram|Mux18~1366

--operation mode is normal

KB1L260 = KB1_m_state[0] & (!KB1_m_state[6]);

--KB1L261 is std_1c20:inst|sdram:the_sdram|Mux18~1367

--operation mode is normal

KB1L261 = KB1_m_state[7] $ KB1_m_state[1];

--KB1L267 is std_1c20:inst|sdram:the_sdram|Mux20~1315

--operation mode is normal

KB1L267 = !KB1_m_state[7] & KB1L246 & !KB1_m_state[2];

--KB1L268 is std_1c20:inst|sdram:the_sdram|Mux20~1316

--operation mode is normal

KB1L268 = KB1_m_state[4] # KB1_init_done & !KB1_m_state[0];

--KB1_i_cmd[0] is std_1c20:inst|sdram:the_sdram|i_cmd[0]

--operation mode is normal

KB1_i_cmd[0]_lut_out = KB1_i_state[2] # KB1_i_state[0] & (!KB1_i_state[1]);

KB1_i_cmd[0] = DFFEAS(KB1_i_cmd[0]_lut_out, QC2__clk0, F1_data_out, , KB1L125, , , , );

--KB1L269 is std_1c20:inst|sdram:the_sdram|Mux20~1317

--operation mode is normal

KB1L269 = KB1_m_state[0] & (KB1_m_state[6] $ (KB1L268)) # !KB1_m_state[0] & !KB1_m_state[6] & KB1_i_cmd[0] & !KB1L268;

--XE1_control_reg[9] is std_1c20:inst|uart1:the_uart1|uart1_regs:the_uart1_regs|control_reg[9]

--operation mode is normal

XE1_control_reg[9]_lut_out = S1_M_st_data[9];

XE1_control_reg[9] = DFFEAS(XE1_control_reg[9]_lut_out, QC2__clk0, F1_data_out, , XE1L14, , , , );

--ZE1_pre_txd is std_1c20:inst|uart1:the_uart1|uart1_tx:the_uart1_tx|pre_txd

--operation mode is normal

ZE1_pre_txd_lut_out = !ZE1_unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out[0] & (ZE1_pre_txd # !ZE1L28);

ZE1_pre_txd = DFFEAS(ZE1_pre_txd_lut_out, QC2__clk0, F1_data_out, , , , , , );

--S1_E_control_rd_data_without_mmu_regs[2] is std_1c20:inst|cpu:the_cpu|E_control_rd_data_without_mmu_regs[2]

--operation mode is normal

S1_E_control_rd_data_without_mmu_regs[2] = AMPP_FUNCTION(QC2__clk0, S1_M_ipending_reg[2], S1_M_ienable_reg[2], S1_D_iw[8], S1L200, F1_data_out, S1_W_stall);

--S1_E_logic_op[1] is std_1c20:inst|cpu:the_cpu|E_logic_op[1]

--operation mode is normal

S1_E_logic_op[1] = AMPP_FUNCTION(QC2__clk0, S1_D_iw[4], S1_D_iw[15], S1L760, S1_D_iw[5], F1_data_out, S1_W_stall);

--S1_E_src1_prelim[2] is std_1c20:inst|cpu:the_cpu|E_src1_prelim[2]

--operation mode is normal

S1_E_src1_prelim[2] = AMPP_FUNCTION(QC2__clk0, CD1_q_b[2], S1_W_wr_data[2], S1L1288, S1_D_src1_hazard_W, F1_data_out, S1_D_src1_hazard_M, S1_W_stall);

--S1_E_src1_hazard_M is std_1c20:inst|cpu:the_cpu|E_src1_hazard_M

--operation mode is normal

S1_E_src1_hazard_M = AMPP_FUNCTION(QC2__clk0, S1L755, S1L202, S1L376, S1L377, F1_data_out, S1_W_stall);

--S1_M_shift_rot_result[2] is std_1c20:inst|cpu:the_cpu|M_shift_rot_result[2]

--operation mode is normal

S1_M_shift_rot_result[2] = AMPP_FUNCTION(QC2__clk0, S1_M_shift_rot_result[1], S1_M_shift_rot_result[3], S1L571, S1_M_ctrl_shift_rot_right, F1_data_out, !S1_M_shift_rot_stall);

--S1_M_ctrl_shift_rot is std_1c20:inst|cpu:the_cpu|M_ctrl_shift_rot

--operation mode is normal

S1_M_ctrl_shift_rot = AMPP_FUNCTION(QC2__clk0, S1_E_ctrl_shift_rot, F1_data_out, S1_W_stall);

--S1L1286 is std_1c20:inst|cpu:the_cpu|M_wr_data_unfiltered[2]~3645

--operation mode is normal

S1L1286 = AMPP_FUNCTION(S1_M_shift_rot_result[2], S1_M_ctrl_shift_rot);

--S1_av_ld_data_aligned_or_div[2] is std_1c20:inst|cpu:the_cpu|av_ld_data_aligned_or_div[2]

--operation mode is normal

S1_av_ld_data_aligned_or_div[2] = AMPP_FUNCTION(QC2__clk0, T1_cpu_data_master_readdata[2], S1_d_readdata_d1[18], S1L144, S1_M_ld_align_sh16, F1_data_out, S1_M_ld_align_sh8);

--S1_av_ld_or_div_done is std_1c20:inst|cpu:the_cpu|av_ld_or_div_done

--operation mode is normal

S1_av_ld_or_div_done = AMPP_FUNCTION(QC2__clk0, S1_av_ld_aligning_data, F1_data_out);

--S1L1287 is std_1c20:inst|cpu:the_cpu|M_wr_data_unfiltered[2]~3646

--operation mode is normal

S1L1287 = AMPP_FUNCTION(S1_av_ld_data_aligned_or_div[2], S1_M_alu_result[2], S1_av_ld_or_div_done, S1_M_ctrl_shift_rot);

--S1L571 is std_1c20:inst|cpu:the_cpu|E_src1[2]~2015

--operation mode is normal

S1L571 = AMPP_FUNCTION(S1_E_src1_prelim[2], S1_E_src1_hazard_M, S1L1286, S1L1287);

--S1_E_src2_imm[2] is std_1c20:inst|cpu:the_cpu|E_src2_imm[2]

--operation mode is normal

S1_E_src2_imm[2] = AMPP_FUNCTION(QC2__clk0, S1_D_iw[8], S1_D_iw[2], S1_D_iw[5], S1L227, F1_data_out, S1_W_stall);

--S1L1235 is std_1c20:inst|cpu:the_cpu|M_st_data[10]~COMBOUT

--operation mode is normal

S1L1235 = AMPP_FUNCTION(S1_E_src2_prelim[2], S1L1288, S1_E_src2_hazard_M);

--S1_M_st_data[10] is std_1c20:inst|cpu:the_cpu|M_st_data[10]

--operation mode is normal

S1_M_st_data[10] = AMPP_FUNCTION(QC2__clk0, S1_E_src2_prelim[2], S1L1288, S1L744, S1_E_src2_hazard_M, F1_data_out, S1L777, S1_W_stall);

--S1_E_ctrl_src2_is_imm is std_1c20:inst|cpu:the_cpu|E_ctrl_src2_is_imm

--operation mode is normal

S1_E_ctrl_src2_is_imm = AMPP_FUNCTION(QC2__clk0, S1L235, S1L234, S1_D_iw[11], F1_data_out, S1_W_stall);

--S1L637 is std_1c20:inst|cpu:the_cpu|E_src2[2]~1503

--operation mode is normal

S1L637 = AMPP_FUNCTION(S1_E_src2_imm[2], S1L1235, S1_E_ctrl_src2_is_imm);

--S1_E_logic_op[0] is std_1c20:inst|cpu:the_cpu|E_logic_op[0]

--operation mode is normal

S1_E_logic_op[0] = AMPP_FUNCTION(QC2__clk0, S1_D_iw[14], S1_D_iw[3], S1L760, S1L763, F1_data_out, S1_W_stall);

--S1L1 is std_1c20:inst|cpu:the_cpu|A_WE_StdLogicVector~14080

--operation mode is normal

S1L1 = AMPP_FUNCTION(S1_E_logic_op[1], S1L571, S1L637, S1_E_logic_op[0]);

--S1_E_extra_pc[0] is std_1c20:inst|cpu:the_cpu|E_extra_pc[0]

--operation mode is normal

S1_E_extra_pc[0] = AMPP_FUNCTION(QC2__clk0, S1_D_pc_plus_one[0], S1_D_br_taken_waddr_partial[0], S1L214, S1_D_iw[21], F1_data_out, S1_W_stall);

--YC1_result[2] is std_1c20:inst|cpu:the_cpu|lpm_add_sub:Add8|alt_stratix_add_sub:stratix_adder|result[2]

--operation mode is arithmetic

YC1_result[2] = AMPP_FUNCTION(S1L637, S1L571, YC1L5, S1_E_ctrl_alu_subtract);

--YC1L7 is std_1c20:inst|cpu:the_cpu|lpm_add_sub:Add8|alt_stratix_add_sub:stratix_adder|add_sub_cell[2]~COUT

--operation mode is arithmetic

YC1L7 = AMPP_FUNCTION(S1L637, S1L571, YC1L5, S1_E_ctrl_alu_subtract);

--S1_E_ctrl_dst_data_sel_pc_plus_one is std_1c20:inst|cpu:the_cpu|E_ctrl_dst_data_sel_pc_plus_one

--operation mode is normal

S1_E_ctrl_dst_data_sel_pc_plus_one = AMPP_FUNCTION(QC2__clk0, S1L765, S1L218, S1L202, S1L773, F1_data_out, S1_W_stall);

--S1L2 is std_1c20:inst|cpu:the_cpu|A_WE_StdLogicVector~14081

--operation mode is normal

S1L2 = AMPP_FUNCTION(S1_E_extra_pc[0], YC1_result[2], S1_E_ctrl_dst_data_sel_pc_plus_one);

--S1_E_ctrl_dst_data_sel_logic_result is std_1c20:inst|cpu:the_cpu|E_ctrl_dst_data_sel_logic_result

--operation mode is normal

S1_E_ctrl_dst_data_sel_logic_result = AMPP_FUNCTION(QC2__clk0, S1L217, S1L772, S1_D_iw[11], S1_D_iw[16], F1_data_out, S1_W_stall);

--S1L3 is std_1c20:inst|cpu:the_cpu|A_WE_StdLogicVector~14082

--operation mode is normal

S1L3 = AMPP_FUNCTION(S1L1, S1L2, S1_E_ctrl_dst_data_sel_logic_result);

--S1_E_ctrl_rdctl_inst is std_1c20:inst|cpu:the_cpu|E_ctrl_rdctl_inst

--operation mode is normal

S1_E_ctrl_rdctl_inst = AMPP_FUNCTION(QC2__clk0, S1L774, S1L772, S1_D_iw[11], S1_D_iw[15], F1_data_out, S1_W_stall);

--S1_E_ctrl_dst_data_sel_cmp is std_1c20:inst|cpu:the_cpu|E_ctrl_dst_data_sel_cmp

--operation mode is normal

S1_E_ctrl_dst_data_sel_cmp = AMPP_FUNCTION(QC2__clk0, S1L216, S1L206, S1L763, S1_D_iw[11], F1_data_out, S1_W_stall);

--S1L408 is std_1c20:inst|cpu:the_cpu|E_alu_result[2]~2392

--operation mode is normal

S1L408 = AMPP_FUNCTION(S1_E_control_rd_data_without_mmu_regs[2], S1L3, S1_E_ctrl_rdctl_inst, S1_E_ctrl_dst_data_sel_cmp);

--S1_M_shift_rot_stall is std_1c20:inst|cpu:the_cpu|M_shift_rot_stall

--operation mode is normal

S1_M_shift_rot_stall = AMPP_FUNCTION(QC2__clk0, S1L1220, S1L120, S1L784, S1L787, F1_data_out);

--S1_M_valid_from_E is std_1c20:inst|cpu:the_cpu|M_valid_from_E

--operation mode is normal

S1_M_valid_from_E = AMPP_FUNCTION(QC2__clk0, S1L752, F1_data_out, S1_W_stall);

--S1_M_ctrl_ld is std_1c20:inst|cpu:the_cpu|M_ctrl_ld

--operation mode is normal

S1_M_ctrl_ld = AMPP_FUNCTION(QC2__clk0, S1_E_ctrl_ld, F1_data_out, S1_W_stall);

--S1L1385 is std_1c20:inst|cpu:the_cpu|W_stall~21

--operation mode is normal

S1L1385 = AMPP_FUNCTION(S1_M_shift_rot_stall, S1_M_valid_from_E, S1_M_ctrl_ld, S1_av_ld_or_div_done);

--RB1L7 is std_1c20:inst|sys_clk_timer:the_sys_clk_timer|control_wr_strobe~42

--operation mode is normal

RB1L7 = S1_internal_d_write & (!T1_internal_cpu_data_master_waitrequest);

--S1_E_control_rd_data_without_mmu_regs[3] is std_1c20:inst|cpu:the_cpu|E_control_rd_data_without_mmu_regs[3]

--operation mode is normal

S1_E_control_rd_data_without_mmu_regs[3] = AMPP_FUNCTION(QC2__clk0, S1_M_ipending_reg[3], S1_M_ienable_reg[3], S1_D_iw[8], S1L200, F1_data_out, S1_W_stall);

--S1_E_src1_prelim[3] is std_1c20:inst|cpu:the_cpu|E_src1_prelim[3]

--operation mode is normal

S1_E_src1_prelim[3] = AMPP_FUNCTION(QC2__clk0, CD1_q_b[3], S1_W_wr_data[3], S1L1291, S1_D_src1_hazard_W, F1_data_out, S1_D_src1_hazard_M, S1_W_stall);

--S1_M_shift_rot_result[3] is std_1c20:inst|cpu:the_cpu|M_shift_rot_result[3]

--operation mode is normal

S1_M_shift_rot_result[3] = AMPP_FUNCTION(QC2__clk0, S1_M_shift_rot_result[2], S1_M_shift_rot_result[4], S1L572, S1_M_ctrl_shift_rot_right, F1_data_out, !S1_M_shift_rot_stall);

--S1L1289 is std_1c20:inst|cpu:the_cpu|M_wr_data_unfiltered[3]~3647

--operation mode is normal

S1L1289 = AMPP_FUNCTION(S1_M_shift_rot_result[3], S1_M_ctrl_shift_rot);

--S1_av_ld_data_aligned_or_div[3] is std_1c20:inst|cpu:the_cpu|av_ld_data_aligned_or_div[3]

--operation mode is normal

S1_av_ld_data_aligned_or_div[3] = AMPP_FUNCTION(QC2__clk0, T1_cpu_data_master_readdata[3], S1_d_readdata_d1[19], S1L146, S1_M_ld_align_sh16, F1_data_out, S1_M_ld_align_sh8);

--S1L1290 is std_1c20:inst|cpu:the_cpu|M_wr_data_unfiltered[3]~3648

--operation mode is normal

S1L1290 = AMPP_FUNCTION(S1_av_ld_data_aligned_or_div[3], S1_M_alu_result[3], S1_av_ld_or_div_done, S1_M_ctrl_shift_rot);

--S1L572 is std_1c20:inst|cpu:the_cpu|E_src1[3]~2016

--operation mode is normal

S1L572 = AMPP_FUNCTION(S1_E_src1_prelim[3], S1_E_src1_hazard_M, S1L1289, S1L1290);

--S1_E_src2_imm[3] is std_1c20:inst|cpu:the_cpu|E_src2_imm[3]

--operation mode is normal

S1_E_src2_imm[3] = AMPP_FUNCTION(QC2__clk0, S1_D_iw[9], S1_D_iw[2], S1_D_iw[5], S1L227, F1_data_out, S1_W_stall);

--S1L1237 is std_1c20:inst|cpu:the_cpu|M_st_data[11]~COMBOUT

--operation mode is normal

S1L1237 = AMPP_FUNCTION(S1_E_src2_prelim[3], S1L1291, S1_E_src2_hazard_M);

--S1_M_st_data[11] is std_1c20:inst|cpu:the_cpu|M_st_data[11]

--operation mode is normal

S1_M_st_data[11] = AMPP_FUNCTION(QC2__clk0, S1_E_src2_prelim[3], S1L1291, S1L745, S1_E_src2_hazard_M, F1_data_out, S1L777, S1_W_stall);

--S1L638 is std_1c20:inst|cpu:the_cpu|E_src2[3]~1504

--operation mode is normal

S1L638 = AMPP_FUNCTION(S1_E_src2_imm[3], S1L1237, S1_E_ctrl_src2_is_imm);

--S1L4 is std_1c20:inst|cpu:the_cpu|A_WE_StdLogicVector~14083

--operation mode is normal

S1L4 = AMPP_FUNCTION(S1_E_logic_op[1], S1L572, S1L638, S1_E_logic_op[0]);

--S1_E_extra_pc[1] is std_1c20:inst|cpu:the_cpu|E_extra_pc[1]

--operation mode is normal

S1_E_extra_pc[1] = AMPP_FUNCTION(QC2__clk0, S1_D_pc_plus_one[1], S1_D_br_taken_waddr_partial[1], S1L214, S1_D_iw[21], F1_data_out, S1_W_stall);

--YC1_result[3] is std_1c20:inst|cpu:the_cpu|lpm_add_sub:Add8|alt_stratix_add_sub:stratix_adder|result[3]

--operation mode is arithmetic

YC1_result[3] = AMPP_FUNCTION(S1L638, S1L572, YC1L7, S1_E_ctrl_alu_subtract);

--YC1L9 is std_1c20:inst|cpu:the_cpu|lpm_add_sub:Add8|alt_stratix_add_sub:stratix_adder|add_sub_cell[3]~COUT

--operation mode is arithmetic

YC1L9 = AMPP_FUNCTION(S1L638, S1L572, YC1L7, S1_E_ctrl_alu_subtract);

--S1L5 is std_1c20:inst|cpu:the_cpu|A_WE_StdLogicVector~14084

--operation mode is normal

S1L5 = AMPP_FUNCTION(S1_E_extra_pc[1], YC1_result[3], S1_E_ctrl_dst_data_sel_pc_plus_one);

--S1L6 is std_1c20:inst|cpu:the_cpu|A_WE_StdLogicVector~14085

--operation mode is normal

S1L6 = AMPP_FUNCTION(S1L4, S1L5, S1_E_ctrl_dst_data_sel_logic_result);

--S1L409 is std_1c20:inst|cpu:the_cpu|E_alu_result[3]~2393

--operation mode is normal

S1L409 = AMPP_FUNCTION(S1_E_control_rd_data_without_mmu_regs[3], S1L6, S1_E_ctrl_rdctl_inst, S1_E_ctrl_dst_data_sel_cmp);

--S1L336 is std_1c20:inst|cpu:the_cpu|d_read_nxt~0

--operation mode is normal

S1L336 = AMPP_FUNCTION(S1_internal_d_read, T1_internal_cpu_data_master_waitrequest);

--S1_E_valid_from_D is std_1c20:inst|cpu:the_cpu|E_valid_from_D

--operation mode is normal

S1_E_valid_from_D = AMPP_FUNCTION(QC2__clk0, S1_M_pipe_flush, S1_D_issue, F1_data_out, S1_W_stall);

--S1_M_pipe_flush is std_1c20:inst|cpu:the_cpu|M_pipe_flush

--operation mode is normal

S1_M_pipe_flush = AMPP_FUNCTION(QC2__clk0, S1L751, S1_E_hbreak_req, S1_E_ctrl_flush_pipe_always, S1L1153, F1_data_out, S1_W_stall);

--S1L751 is std_1c20:inst|cpu:the_cpu|E_valid~34

--operation mode is normal

S1L751 = AMPP_FUNCTION(S1_E_valid_from_D, S1_M_pipe_flush);

--S1_E_iw[11] is std_1c20:inst|cpu:the_cpu|E_iw[11]

--operation mode is normal

S1_E_iw[11] = AMPP_FUNCTION(QC2__clk0, S1_D_iw[11], F1_data_out, S1_W_stall);

--S1_E_iw[4] is std_1c20:inst|cpu:the_cpu|E_iw[4]

--operation mode is normal

S1_E_iw[4] = AMPP_FUNCTION(QC2__clk0, S1_D_iw[4], F1_data_out, S1_W_stall);

--S1_E_iw[3] is std_1c20:inst|cpu:the_cpu|E_iw[3]

--operation mode is normal

S1_E_iw[3] = AMPP_FUNCTION(QC2__clk0, S1_D_iw[3], F1_data_out, S1_W_stall);

--S1_E_iw[5] is std_1c20:inst|cpu:the_cpu|E_iw[5]

--operation mode is normal

S1_E_iw[5] = AMPP_FUNCTION(QC2__clk0, S1_D_iw[5], F1_data_out, S1_W_stall);

--S1_E_iw[12] is std_1c20:inst|cpu:the_cpu|E_iw[12]

--operation mode is normal

S1_E_iw[12] = AMPP_FUNCTION(QC2__clk0, S1_D_iw[12], F1_data_out, S1_W_stall);

--S1L540 is std_1c20:inst|cpu:the_cpu|E_op_eret~72

--operation mode is normal

S1L540 = AMPP_FUNCTION(S1_E_iw[4], S1_E_iw[3], S1_E_iw[5], S1_E_iw[12]);

--S1_E_iw[1] is std_1c20:inst|cpu:the_cpu|E_iw[1]

--operation mode is normal

S1_E_iw[1] = AMPP_FUNCTION(QC2__clk0, S1_D_iw[1], F1_data_out, S1_W_stall);

--S1_E_iw[2] is std_1c20:inst|cpu:the_cpu|E_iw[2]

--operation mode is normal

S1_E_iw[2] = AMPP_FUNCTION(QC2__clk0, S1_D_iw[2], F1_data_out, S1_W_stall);

--S1_E_iw[0] is std_1c20:inst|cpu:the_cpu|E_iw[0]

--operation mode is normal

S1_E_iw[0] = AMPP_FUNCTION(QC2__clk0, S1_D_iw[0], F1_data_out, S1_W_stall);

--S1L541 is std_1c20:inst|cpu:the_cpu|E_op_eret~73

--operation mode is normal

S1L541 = AMPP_FUNCTION(S1_E_iw[1], S1_E_iw[2], S1_E_iw[0]);

--S1_E_iw[16] is std_1c20:inst|cpu:the_cpu|E_iw[16]

--operation mode is normal

S1_E_iw[16] = AMPP_FUNCTION(QC2__clk0, S1_D_iw[16], F1_data_out, S1_W_stall);

--S1_E_iw[15] is std_1c20:inst|cpu:the_cpu|E_iw[15]

--operation mode is normal

S1_E_iw[15] = AMPP_FUNCTION(QC2__clk0, S1_D_iw[15], F1_data_out, S1_W_stall);

--S1L478 is std_1c20:inst|cpu:the_cpu|E_hbreak_req~68

--operation mode is normal

S1L478 = AMPP_FUNCTION(S1_E_valid_from_D, S1_M_pipe_flush, S1_E_iw[16], S1_E_iw[15]);

--S1L479 is std_1c20:inst|cpu:the_cpu|E_hbreak_req~69

--operation mode is normal

S1L479 = AMPP_FUNCTION(S1_E_iw[11], S1L540, S1L541, S1L478);

--S1_E_iw[13] is std_1c20:inst|cpu:the_cpu|E_iw[13]

--operation mode is normal

S1_E_iw[13] = AMPP_FUNCTION(QC2__clk0, S1_D_iw[13], F1_data_out, S1_W_stall);

--S1_E_iw[14] is std_1c20:inst|cpu:the_cpu|E_iw[14]

--operation mode is normal

S1_E_iw[14] = AMPP_FUNCTION(QC2__clk0, S1_D_iw[14], F1_data_out, S1_W_stall);

--S1L480 is std_1c20:inst|cpu:the_cpu|E_hbreak_req~70

--operation mode is normal

S1L480 = AMPP_FUNCTION(S1_E_iw[13], S1_E_iw[14]);

--JD1_jtag_break is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_debug:the_cpu_nios2_oci_debug|jtag_break

--operation mode is normal

JD1_jtag_break = AMPP_FUNCTION(QC2__clk0, JD1_probepresent, JD1_jtag_break, JD1L1, F1_data_out, !C1_CLR_SIGNAL, SD1L191);

--S1_latched_oci_tb_hbreak_req is std_1c20:inst|cpu:the_cpu|latched_oci_tb_hbreak_req

--operation mode is normal

S1_latched_oci_tb_hbreak_req = AMPP_FUNCTION(QC2__clk0, S1L751, S1L926, S1_latched_oci_tb_hbreak_req, S1_hbreak_enabled, F1_data_out);

--S1_hbreak_enabled is std_1c20:inst|cpu:the_cpu|hbreak_enabled

--operation mode is normal

S1_hbreak_enabled = AMPP_FUNCTION(QC2__clk0, S1L921, S1L924, S1L925, S1_hbreak_enabled, F1_data_out);

--S1_wait_for_one_post_bret_inst is std_1c20:inst|cpu:the_cpu|wait_for_one_post_bret_inst

--operation mode is normal

S1_wait_for_one_post_bret_inst = AMPP_FUNCTION(QC2__clk0, FD1_internal_oci_single_step_mode1, S1_hbreak_enabled, S1_wait_for_one_post_bret_inst, S1L83, F1_data_out);

--S1L926 is std_1c20:inst|cpu:the_cpu|hbreak_req~32

--operation mode is normal

S1L926 = AMPP_FUNCTION(JD1_jtag_break, S1_latched_oci_tb_hbreak_req, S1_hbreak_enabled, S1_wait_for_one_post_bret_inst);

--S1L752 is std_1c20:inst|cpu:the_cpu|E_valid~35

--operation mode is normal

S1L752 = AMPP_FUNCTION(S1L751, S1L479, S1L480, S1L926);

--S1_E_ctrl_ld is std_1c20:inst|cpu:the_cpu|E_ctrl_ld

--operation mode is normal

S1_E_ctrl_ld = AMPP_FUNCTION(QC2__clk0, S1_D_iw[4], S1_D_iw[2], S1_D_iw[1], S1_D_iw[0], F1_data_out, S1_W_stall);

--S1_E_extra_pc[20] is std_1c20:inst|cpu:the_cpu|E_extra_pc[20]

--operation mode is normal

S1_E_extra_pc[20] = AMPP_FUNCTION(QC2__clk0, S1_D_pc_plus_one[20], S1L84, S1L214, S1_D_iw[21], F1_data_out, S1_W_stall);

--YC1_result[22] is std_1c20:inst|cpu:the_cpu|lpm_add_sub:Add8|alt_stratix_add_sub:stratix_adder|result[22]

--operation mode is arithmetic

YC1_result[22] = AMPP_FUNCTION(S1L657, S1L591, YC1L45, S1_E_ctrl_alu_subtract);

--YC1L47 is std_1c20:inst|cpu:the_cpu|lpm_add_sub:Add8|alt_stratix_add_sub:stratix_adder|add_sub_cell[22]~COUT

--operation mode is arithmetic

YC1L47 = AMPP_FUNCTION(S1L657, S1L591, YC1L45, S1_E_ctrl_alu_subtract);

--S1L7 is std_1c20:inst|cpu:the_cpu|A_WE_StdLogicVector~14086

--operation mode is normal

S1L7 = AMPP_FUNCTION(S1_E_extra_pc[20], YC1_result[22], S1_E_ctrl_dst_data_sel_pc_plus_one);

--S1_E_src1_prelim[22] is std_1c20:inst|cpu:the_cpu|E_src1_prelim[22]

--operation mode is normal

S1_E_src1_prelim[22] = AMPP_FUNCTION(QC2__clk0, CD1_q_b[22], S1_W_wr_data[22], S1L1348, S1_D_src1_hazard_W, F1_data_out, S1_D_src1_hazard_M, S1_W_stall);

--S1_M_shift_rot_result[22] is std_1c20:inst|cpu:the_cpu|M_shift_rot_result[22]

--operation mode is normal

S1_M_shift_rot_result[22] = AMPP_FUNCTION(QC2__clk0, S1_M_shift_rot_result[21], S1_M_shift_rot_result[23], S1L591, S1_M_ctrl_shift_rot_right, F1_data_out, !S1_M_shift_rot_stall);

--S1L1346 is std_1c20:inst|cpu:the_cpu|M_wr_data_unfiltered[22]~3649

--operation mode is normal

S1L1346 = AMPP_FUNCTION(S1_M_shift_rot_result[22], S1_M_ctrl_shift_rot);

--S1_av_ld_data_aligned_or_div[22] is std_1c20:inst|cpu:the_cpu|av_ld_data_aligned_or_div[22]

--operation mode is normal

S1_av_ld_data_aligned_or_div[22] = AMPP_FUNCTION(QC2__clk0, S1_d_readdata_d1[22], S1_M_ctrl_ld_signed, S1L174, S1_M_iw[4], F1_data_out);

--S1L1347 is std_1c20:inst|cpu:the_cpu|M_wr_data_unfiltered[22]~3650

--operation mode is normal

S1L1347 = AMPP_FUNCTION(S1_av_ld_data_aligned_or_div[22], S1_M_alu_result[22], S1_av_ld_or_div_done, S1_M_ctrl_shift_rot);

--S1L591 is std_1c20:inst|cpu:the_cpu|E_src1[22]~2017

--operation mode is normal

S1L591 = AMPP_FUNCTION(S1_E_src1_prelim[22], S1_E_src1_hazard_M, S1L1346, S1L1347);

--S1_E_src2_imm[22] is std_1c20:inst|cpu:the_cpu|E_src2_imm[22]

--operation mode is normal

S1_E_src2_imm[22] = AMPP_FUNCTION(QC2__clk0, S1_D_iw[12], S1_D_iw[21], S1L228, S1L238, F1_data_out, S1_W_stall);

--S1L1259 is std_1c20:inst|cpu:the_cpu|M_st_data[22]~COMBOUT

--operation mode is normal

S1L1259 = AMPP_FUNCTION(S1_E_src2_prelim[22], S1L1348, S1_E_src2_hazard_M);

--S1_M_st_data[22] is std_1c20:inst|cpu:the_cpu|M_st_data[22]

--operation mode is normal

S1_M_st_data[22] = AMPP_FUNCTION(QC2__clk0, S1_E_src2_prelim[22], S1L1348, S1L1243, S1_E_src2_hazard_M, F1_data_out, !S1_E_iw[4], S1_W_stall);

--S1L657 is std_1c20:inst|cpu:the_cpu|E_src2[22]~1505

--operation mode is normal

S1L657 = AMPP_FUNCTION(S1_E_src2_imm[22], S1L1259, S1_E_ctrl_src2_is_imm);

--S1L530 is std_1c20:inst|cpu:the_cpu|E_logic_result[22]~15595

--operation mode is normal

S1L530 = AMPP_FUNCTION(S1_E_logic_op[1], S1L591, S1L657, S1_E_logic_op[0]);

--S1_E_extra_pc[19] is std_1c20:inst|cpu:the_cpu|E_extra_pc[19]

--operation mode is normal

S1_E_extra_pc[19] = AMPP_FUNCTION(QC2__clk0, S1_D_pc_plus_one[19], S1L86, S1L214, S1_D_iw[21], F1_data_out, S1_W_stall);

--YC1_result[21] is std_1c20:inst|cpu:the_cpu|lpm_add_sub:Add8|alt_stratix_add_sub:stratix_adder|result[21]

--operation mode is arithmetic

YC1_result[21] = AMPP_FUNCTION(S1L656, S1L590, YC1L43, S1_E_ctrl_alu_subtract);

--YC1L45 is std_1c20:inst|cpu:the_cpu|lpm_add_sub:Add8|alt_stratix_add_sub:stratix_adder|add_sub_cell[21]~COUT

--operation mode is arithmetic

YC1L45 = AMPP_FUNCTION(S1L656, S1L590, YC1L43, S1_E_ctrl_alu_subtract);

--S1L8 is std_1c20:inst|cpu:the_cpu|A_WE_StdLogicVector~14087

--operation mode is normal

S1L8 = AMPP_FUNCTION(S1_E_extra_pc[19], YC1_result[21], S1_E_ctrl_dst_data_sel_pc_plus_one);

--S1_E_src1_prelim[21] is std_1c20:inst|cpu:the_cpu|E_src1_prelim[21]

--operation mode is normal

S1_E_src1_prelim[21] = AMPP_FUNCTION(QC2__clk0, CD1_q_b[21], S1_W_wr_data[21], S1L1345, S1_D_src1_hazard_W, F1_data_out, S1_D_src1_hazard_M, S1_W_stall);

--S1_M_shift_rot_result[21] is std_1c20:inst|cpu:the_cpu|M_shift_rot_result[21]

--operation mode is normal

S1_M_shift_rot_result[21] = AMPP_FUNCTION(QC2__clk0, S1_M_shift_rot_result[20], S1_M_shift_rot_result[22], S1L590, S1_M_ctrl_shift_rot_right, F1_data_out, !S1_M_shift_rot_stall);

--S1L1343 is std_1c20:inst|cpu:the_cpu|M_wr_data_unfiltered[21]~3651

--operation mode is normal

S1L1343 = AMPP_FUNCTION(S1_M_shift_rot_result[21], S1_M_ctrl_shift_rot);

--S1_av_ld_data_aligned_or_div[21] is std_1c20:inst|cpu:the_cpu|av_ld_data_aligned_or_div[21]

--operation mode is normal

S1_av_ld_data_aligned_or_div[21] = AMPP_FUNCTION(QC2__clk0, S1_d_readdata_d1[21], S1_M_ctrl_ld_signed, S1L174, S1_M_iw[4], F1_data_out);

--S1L1344 is std_1c20:inst|cpu:the_cpu|M_wr_data_unfiltered[21]~3652

--operation mode is normal

S1L1344 = AMPP_FUNCTION(S1_av_ld_data_aligned_or_div[21], S1_M_alu_result[21], S1_av_ld_or_div_done, S1_M_ctrl_shift_rot);

--S1L590 is std_1c20:inst|cpu:the_cpu|E_src1[21]~2018

--operation mode is normal

S1L590 = AMPP_FUNCTION(S1_E_src1_prelim[21], S1_E_src1_hazard_M, S1L1343, S1L1344);

--S1_E_src2_imm[21] is std_1c20:inst|cpu:the_cpu|E_src2_imm[21]

--operation mode is normal

S1_E_src2_imm[21] = AMPP_FUNCTION(QC2__clk0, S1_D_iw[11], S1_D_iw[21], S1L228, S1L238, F1_data_out, S1_W_stall);

--S1L1257 is std_1c20:inst|cpu:the_cpu|M_st_data[21]~COMBOUT

--operation mode is normal

S1L1257 = AMPP_FUNCTION(S1_E_src2_prelim[21], S1L1345, S1_E_src2_hazard_M);

--S1_M_st_data[21] is std_1c20:inst|cpu:the_cpu|M_st_data[21]

--operation mode is normal

S1_M_st_data[21] = AMPP_FUNCTION(QC2__clk0, S1_E_src2_prelim[21], S1L1345, S1L1241, S1_E_src2_hazard_M, F1_data_out, !S1_E_iw[4], S1_W_stall);

--S1L656 is std_1c20:inst|cpu:the_cpu|E_src2[21]~1506

--operation mode is normal

S1L656 = AMPP_FUNCTION(S1_E_src2_imm[21], S1L1257, S1_E_ctrl_src2_is_imm);

--S1L529 is std_1c20:inst|cpu:the_cpu|E_logic_result[21]~15596

--operation mode is normal

S1L529 = AMPP_FUNCTION(S1_E_logic_op[1], S1L590, S1L656, S1_E_logic_op[0]);

--S1_E_extra_pc[17] is std_1c20:inst|cpu:the_cpu|E_extra_pc[17]

--operation mode is normal

S1_E_extra_pc[17] = AMPP_FUNCTION(QC2__clk0, S1_D_pc_plus_one[17], S1L88, S1L214, S1_D_iw[21], F1_data_out, S1_W_stall);

--YC1_result[19] is std_1c20:inst|cpu:the_cpu|lpm_add_sub:Add8|alt_stratix_add_sub:stratix_adder|result[19]

--operation mode is arithmetic

YC1_result[19] = AMPP_FUNCTION(S1L654, S1L588, YC1L39, S1_E_ctrl_alu_subtract);

--YC1L41 is std_1c20:inst|cpu:the_cpu|lpm_add_sub:Add8|alt_stratix_add_sub:stratix_adder|add_sub_cell[19]~COUT

--operation mode is arithmetic

YC1L41 = AMPP_FUNCTION(S1L654, S1L588, YC1L39, S1_E_ctrl_alu_subtract);

--S1L9 is std_1c20:inst|cpu:the_cpu|A_WE_StdLogicVector~14088

--operation mode is normal

S1L9 = AMPP_FUNCTION(S1_E_extra_pc[17], YC1_result[19], S1_E_ctrl_dst_data_sel_pc_plus_one);

--S1_E_src1_prelim[19] is std_1c20:inst|cpu:the_cpu|E_src1_prelim[19]

--operation mode is normal

S1_E_src1_prelim[19] = AMPP_FUNCTION(QC2__clk0, CD1_q_b[19], S1_W_wr_data[19], S1L1339, S1_D_src1_hazard_W, F1_data_out, S1_D_src1_hazard_M, S1_W_stall);

--S1_M_shift_rot_result[19] is std_1c20:inst|cpu:the_cpu|M_shift_rot_result[19]

--operation mode is normal

S1_M_shift_rot_result[19] = AMPP_FUNCTION(QC2__clk0, S1_M_shift_rot_result[18], S1_M_shift_rot_result[20], S1L588, S1_M_ctrl_shift_rot_right, F1_data_out, !S1_M_shift_rot_stall);

--S1L1337 is std_1c20:inst|cpu:the_cpu|M_wr_data_unfiltered[19]~3653

--operation mode is normal

S1L1337 = AMPP_FUNCTION(S1_M_shift_rot_result[19], S1_M_ctrl_shift_rot);

--S1_av_ld_data_aligned_or_div[19] is std_1c20:inst|cpu:the_cpu|av_ld_data_aligned_or_div[19]

--operation mode is normal

S1_av_ld_data_aligned_or_div[19] = AMPP_FUNCTION(QC2__clk0, S1_d_readdata_d1[19], S1_M_ctrl_ld_signed, S1L174, S1_M_iw[4], F1_data_out);

--S1L1338 is std_1c20:inst|cpu:the_cpu|M_wr_data_unfiltered[19]~3654

--operation mode is normal

S1L1338 = AMPP_FUNCTION(S1_av_ld_data_aligned_or_div[19], S1_M_alu_result[19], S1_av_ld_or_div_done, S1_M_ctrl_shift_rot);

--S1L588 is std_1c20:inst|cpu:the_cpu|E_src1[19]~2019

--operation mode is normal

S1L588 = AMPP_FUNCTION(S1_E_src1_prelim[19], S1_E_src1_hazard_M, S1L1337, S1L1338);

--S1_E_src2_imm[19] is std_1c20:inst|cpu:the_cpu|E_src2_imm[19]

--operation mode is normal

S1_E_src2_imm[19] = AMPP_FUNCTION(QC2__clk0, S1_D_iw[9], S1_D_iw[21], S1L228, S1L238, F1_data_out, S1_W_stall);

--S1L1253 is std_1c20:inst|cpu:the_cpu|M_st_data[19]~COMBOUT

--operation mode is normal

S1L1253 = AMPP_FUNCTION(S1_E_src2_prelim[19], S1L1339, S1_E_src2_hazard_M);

--S1_M_st_data[19] is std_1c20:inst|cpu:the_cpu|M_st_data[19]

--operation mode is normal

S1_M_st_data[19] = AMPP_FUNCTION(QC2__clk0, S1_E_src2_prelim[19], S1L1339, S1L1237, S1_E_src2_hazard_M, F1_data_out, !S1_E_iw[4], S1_W_stall);

--S1L654 is std_1c20:inst|cpu:the_cpu|E_src2[19]~1507

--operation mode is normal

S1L654 = AMPP_FUNCTION(S1_E_src2_imm[19], S1L1253, S1_E_ctrl_src2_is_imm);

--S1L527 is std_1c20:inst|cpu:the_cpu|E_logic_result[19]~15597

--operation mode is normal

S1L527 = AMPP_FUNCTION(S1_E_logic_op[1], S1L588, S1L654, S1_E_logic_op[0]);

--S1_E_extra_pc[16] is std_1c20:inst|cpu:the_cpu|E_extra_pc[16]

--operation mode is normal

S1_E_extra_pc[16] = AMPP_FUNCTION(QC2__clk0, S1_D_pc_plus_one[16], S1L90, S1L214, S1_D_iw[21], F1_data_out, S1_W_stall);

--YC1_result[18] is std_1c20:inst|cpu:the_cpu|lpm_add_sub:Add8|alt_stratix_add_sub:stratix_adder|result[18]

--operation mode is arithmetic

YC1_result[18] = AMPP_FUNCTION(S1L653, S1L587, YC1L37, S1_E_ctrl_alu_subtract);

--YC1L39 is std_1c20:inst|cpu:the_cpu|lpm_add_sub:Add8|alt_stratix_add_sub:stratix_adder|add_sub_cell[18]~COUT

--operation mode is arithmetic

YC1L39 = AMPP_FUNCTION(S1L653, S1L587, YC1L37, S1_E_ctrl_alu_subtract);

--S1L10 is std_1c20:inst|cpu:the_cpu|A_WE_StdLogicVector~14089

--operation mode is normal

S1L10 = AMPP_FUNCTION(S1_E_extra_pc[16], YC1_result[18], S1_E_ctrl_dst_data_sel_pc_plus_one);

--S1_E_src1_prelim[18] is std_1c20:inst|cpu:the_cpu|E_src1_prelim[18]

--operation mode is normal

S1_E_src1_prelim[18] = AMPP_FUNCTION(QC2__clk0, CD1_q_b[18], S1_W_wr_data[18], S1L1336, S1_D_src1_hazard_W, F1_data_out, S1_D_src1_hazard_M, S1_W_stall);

--S1_M_shift_rot_result[18] is std_1c20:inst|cpu:the_cpu|M_shift_rot_result[18]

--operation mode is normal

S1_M_shift_rot_result[18] = AMPP_FUNCTION(QC2__clk0, S1_M_shift_rot_result[17], S1_M_shift_rot_result[19], S1L587, S1_M_ctrl_shift_rot_right, F1_data_out, !S1_M_shift_rot_stall);

--S1L1334 is std_1c20:inst|cpu:the_cpu|M_wr_data_unfiltered[18]~3655

--operation mode is normal

S1L1334 = AMPP_FUNCTION(S1_M_shift_rot_result[18], S1_M_ctrl_shift_rot);

--S1_av_ld_data_aligned_or_div[18] is std_1c20:inst|cpu:the_cpu|av_ld_data_aligned_or_div[18]

--operation mode is normal

S1_av_ld_data_aligned_or_div[18] = AMPP_FUNCTION(QC2__clk0, S1_d_readdata_d1[18], S1_M_ctrl_ld_signed, S1L174, S1_M_iw[4], F1_data_out);

--S1L1335 is std_1c20:inst|cpu:the_cpu|M_wr_data_unfiltered[18]~3656

--operation mode is normal

S1L1335 = AMPP_FUNCTION(S1_av_ld_data_aligned_or_div[18], S1_M_alu_result[18], S1_av_ld_or_div_done, S1_M_ctrl_shift_rot);

--S1L587 is std_1c20:inst|cpu:the_cpu|E_src1[18]~2020

--operation mode is normal

S1L587 = AMPP_FUNCTION(S1_E_src1_prelim[18], S1_E_src1_hazard_M, S1L1334, S1L1335);

--S1_E_src2_imm[18] is std_1c20:inst|cpu:the_cpu|E_src2_imm[18]

--operation mode is normal

S1_E_src2_imm[18] = AMPP_FUNCTION(QC2__clk0, S1_D_iw[8], S1_D_iw[21], S1L228, S1L238, F1_data_out, S1_W_stall);

--S1L1251 is std_1c20:inst|cpu:the_cpu|M_st_data[18]~COMBOUT

--operation mode is normal

S1L1251 = AMPP_FUNCTION(S1_E_src2_prelim[18], S1L1336, S1_E_src2_hazard_M);

--S1_M_st_data[18] is std_1c20:inst|cpu:the_cpu|M_st_data[18]

--operation mode is normal

S1_M_st_data[18] = AMPP_FUNCTION(QC2__clk0, S1_E_src2_prelim[18], S1L1336, S1L1235, S1_E_src2_hazard_M, F1_data_out, !S1_E_iw[4], S1_W_stall);

--S1L653 is std_1c20:inst|cpu:the_cpu|E_src2[18]~1508

--operation mode is normal

S1L653 = AMPP_FUNCTION(S1_E_src2_imm[18], S1L1251, S1_E_ctrl_src2_is_imm);

--S1L526 is std_1c20:inst|cpu:the_cpu|E_logic_result[18]~15598

--operation mode is normal

S1L526 = AMPP_FUNCTION(S1_E_logic_op[1], S1L587, S1L653, S1_E_logic_op[0]);

--S1_E_extra_pc[22] is std_1c20:inst|cpu:the_cpu|E_extra_pc[22]

--operation mode is normal

S1_E_extra_pc[22] = AMPP_FUNCTION(QC2__clk0, S1_D_pc_plus_one[22], S1L92, S1L214, S1_D_iw[21], F1_data_out, S1_W_stall);

--YC1_result[24] is std_1c20:inst|cpu:the_cpu|lpm_add_sub:Add8|alt_stratix_add_sub:stratix_adder|result[24]

--operation mode is arithmetic

YC1_result[24] = AMPP_FUNCTION(S1L659, S1L593, YC1L49, S1_E_ctrl_alu_subtract);

--YC1L51 is std_1c20:inst|cpu:the_cpu|lpm_add_sub:Add8|alt_stratix_add_sub:stratix_adder|add_sub_cell[24]~COUT

--operation mode is arithmetic

YC1L51 = AMPP_FUNCTION(S1L659, S1L593, YC1L49, S1_E_ctrl_alu_subtract);

--S1L11 is std_1c20:inst|cpu:the_cpu|A_WE_StdLogicVector~14090

--operation mode is normal

S1L11 = AMPP_FUNCTION(S1_E_extra_pc[22], YC1_result[24], S1_E_ctrl_dst_data_sel_pc_plus_one);

--S1_E_src2_imm[24] is std_1c20:inst|cpu:the_cpu|E_src2_imm[24]

--operation mode is normal

S1_E_src2_imm[24] = AMPP_FUNCTION(QC2__clk0, S1_D_iw[14], S1_D_iw[21], S1L228, S1L238, F1_data_out, S1_W_stall);

--S1_E_src2_prelim[24] is std_1c20:inst|cpu:the_cpu|E_src2_prelim[24]

--operation mode is normal

S1_E_src2_prelim[24] = AMPP_FUNCTION(QC2__clk0, DD1_q_b[24], S1_W_wr_data[24], S1L1354, S1L396, F1_data_out, S1L392, S1_W_stall);

--S1_E_src2_hazard_M is std_1c20:inst|cpu:the_cpu|E_src2_hazard_M

--operation mode is normal

S1_E_src2_hazard_M = AMPP_FUNCTION(QC2__clk0, S1L755, S1L388, S1_E_dst_regnum[2], S1_D_iw[24], F1_data_out, S1_W_stall);

--S1_M_shift_rot_result[24] is std_1c20:inst|cpu:the_cpu|M_shift_rot_result[24]

--operation mode is normal

S1_M_shift_rot_result[24] = AMPP_FUNCTION(QC2__clk0, S1_M_shift_rot_result[23], S1_M_shift_rot_result[25], S1L593, S1_M_ctrl_shift_rot_right, F1_data_out, !S1_M_shift_rot_stall);

--S1L1352 is std_1c20:inst|cpu:the_cpu|M_wr_data_unfiltered[24]~3657

--operation mode is normal

S1L1352 = AMPP_FUNCTION(S1_M_shift_rot_result[24], S1_M_ctrl_shift_rot);

--S1_av_ld_data_aligned_or_div[24] is std_1c20:inst|cpu:the_cpu|av_ld_data_aligned_or_div[24]

--operation mode is normal

S1_av_ld_data_aligned_or_div[24] = AMPP_FUNCTION(QC2__clk0, S1_d_readdata_d1[24], S1_M_ctrl_ld_signed, S1L174, S1_M_iw[4], F1_data_out);

--S1L1353 is std_1c20:inst|cpu:the_cpu|M_wr_data_unfiltered[24]~3658

--operation mode is normal

S1L1353 = AMPP_FUNCTION(S1_av_ld_data_aligned_or_div[24], S1_M_alu_result[24], S1_av_ld_or_div_done, S1_M_ctrl_shift_rot);

--S1L734 is std_1c20:inst|cpu:the_cpu|E_src2_reg[24]~472

--operation mode is normal

S1L734 = AMPP_FUNCTION(S1_E_src2_prelim[24], S1_E_src2_hazard_M, S1L1352, S1L1353);

--S1L659 is std_1c20:inst|cpu:the_cpu|E_src2[24]~1509

--operation mode is normal

S1L659 = AMPP_FUNCTION(S1_E_src2_imm[24], S1L734, S1_E_ctrl_src2_is_imm);

--S1_E_src1_prelim[24] is std_1c20:inst|cpu:the_cpu|E_src1_prelim[24]

--operation mode is normal

S1_E_src1_prelim[24] = AMPP_FUNCTION(QC2__clk0, CD1_q_b[24], S1_W_wr_data[24], S1L1354, S1_D_src1_hazard_W, F1_data_out, S1_D_src1_hazard_M, S1_W_stall);

--S1L593 is std_1c20:inst|cpu:the_cpu|E_src1[24]~2021

--operation mode is normal

S1L593 = AMPP_FUNCTION(S1_E_src1_prelim[24], S1_E_src1_hazard_M, S1L1352, S1L1353);

--S1L532 is std_1c20:inst|cpu:the_cpu|E_logic_result[24]~15599

--operation mode is normal

S1L532 = AMPP_FUNCTION(S1_E_logic_op[1], S1L659, S1L593, S1_E_logic_op[0]);

--S1_E_extra_pc[14] is std_1c20:inst|cpu:the_cpu|E_extra_pc[14]

--operation mode is normal

S1_E_extra_pc[14] = AMPP_FUNCTION(QC2__clk0, S1_D_pc_plus_one[14], S1L94, S1L214, S1_D_iw[21], F1_data_out, S1_W_stall);

--YC1_result[16] is std_1c20:inst|cpu:the_cpu|lpm_add_sub:Add8|alt_stratix_add_sub:stratix_adder|result[16]

--operation mode is arithmetic

YC1_result[16] = AMPP_FUNCTION(S1L651, S1L585, YC1L33, S1_E_ctrl_alu_subtract);

--YC1L35 is std_1c20:inst|cpu:the_cpu|lpm_add_sub:Add8|alt_stratix_add_sub:stratix_adder|add_sub_cell[16]~COUT

--operation mode is arithmetic

YC1L35 = AMPP_FUNCTION(S1L651, S1L585, YC1L33, S1_E_ctrl_alu_subtract);

--S1L12 is std_1c20:inst|cpu:the_cpu|A_WE_StdLogicVector~14091

--operation mode is normal

S1L12 = AMPP_FUNCTION(S1_E_extra_pc[14], YC1_result[16], S1_E_ctrl_dst_data_sel_pc_plus_one);

--S1_E_src1_prelim[16] is std_1c20:inst|cpu:the_cpu|E_src1_prelim[16]

--operation mode is normal

S1_E_src1_prelim[16] = AMPP_FUNCTION(QC2__clk0, CD1_q_b[16], S1_W_wr_data[16], S1L1330, S1_D_src1_hazard_W, F1_data_out, S1_D_src1_hazard_M, S1_W_stall);

--S1_M_shift_rot_result[16] is std_1c20:inst|cpu:the_cpu|M_shift_rot_result[16]

--operation mode is normal

S1_M_shift_rot_result[16] = AMPP_FUNCTION(QC2__clk0, S1_M_shift_rot_result[15], S1_M_shift_rot_result[17], S1L585, S1_M_ctrl_shift_rot_right, F1_data_out, !S1_M_shift_rot_stall);

--S1L1328 is std_1c20:inst|cpu:the_cpu|M_wr_data_unfiltered[16]~3659

--operation mode is normal

S1L1328 = AMPP_FUNCTION(S1_M_shift_rot_result[16], S1_M_ctrl_shift_rot);

--S1_av_ld_data_aligned_or_div[16] is std_1c20:inst|cpu:the_cpu|av_ld_data_aligned_or_div[16]

--operation mode is normal

S1_av_ld_data_aligned_or_div[16] = AMPP_FUNCTION(QC2__clk0, S1_d_readdata_d1[16], S1_M_ctrl_ld_signed, S1L174, S1_M_iw[4], F1_data_out);

--S1L1329 is std_1c20:inst|cpu:the_cpu|M_wr_data_unfiltered[16]~3660

--operation mode is normal

S1L1329 = AMPP_FUNCTION(S1_av_ld_data_aligned_or_div[16], S1_M_alu_result[16], S1_av_ld_or_div_done, S1_M_ctrl_shift_rot);

--S1L585 is std_1c20:inst|cpu:the_cpu|E_src1[16]~2022

--operation mode is normal

S1L585 = AMPP_FUNCTION(S1_E_src1_prelim[16], S1_E_src1_hazard_M, S1L1328, S1L1329);

--S1_E_src2_imm[16] is std_1c20:inst|cpu:the_cpu|E_src2_imm[16]

--operation mode is normal

S1_E_src2_imm[16] = AMPP_FUNCTION(QC2__clk0, S1_D_iw[6], S1_D_iw[21], S1L228, S1L238, F1_data_out, S1_W_stall);

--S1L1247 is std_1c20:inst|cpu:the_cpu|M_st_data[16]~COMBOUT

--operation mode is normal

S1L1247 = AMPP_FUNCTION(S1_E_src2_prelim[16], S1L1330, S1_E_src2_hazard_M);

--S1_M_st_data[16] is std_1c20:inst|cpu:the_cpu|M_st_data[16]

--operation mode is normal

S1_M_st_data[16] = AMPP_FUNCTION(QC2__clk0, S1_E_src2_prelim[16], S1L1330, S1L1231, S1_E_src2_hazard_M, F1_data_out, !S1_E_iw[4], S1_W_stall);

--S1L651 is std_1c20:inst|cpu:the_cpu|E_src2[16]~1510

--operation mode is normal

S1L651 = AMPP_FUNCTION(S1_E_src2_imm[16], S1L1247, S1_E_ctrl_src2_is_imm);

--S1L524 is std_1c20:inst|cpu:the_cpu|E_logic_result[16]~15600

--operation mode is normal

S1L524 = AMPP_FUNCTION(S1_E_logic_op[1], S1L585, S1L651, S1_E_logic_op[0]);

--S1_E_extra_pc[13] is std_1c20:inst|cpu:the_cpu|E_extra_pc[13]

--operation mode is normal

S1_E_extra_pc[13] = AMPP_FUNCTION(QC2__clk0, S1_D_pc_plus_one[13], S1L96, S1L214, S1_D_iw[21], F1_data_out, S1_W_stall);

--YC1_result[15] is std_1c20:inst|cpu:the_cpu|lpm_add_sub:Add8|alt_stratix_add_sub:stratix_adder|result[15]

--operation mode is arithmetic

YC1_result[15] = AMPP_FUNCTION(S1L650, S1L584, YC1L31, S1_E_ctrl_alu_subtract);

--YC1L33 is std_1c20:inst|cpu:the_cpu|lpm_add_sub:Add8|alt_stratix_add_sub:stratix_adder|add_sub_cell[15]~COUT

--operation mode is arithmetic

YC1L33 = AMPP_FUNCTION(S1L650, S1L584, YC1L31, S1_E_ctrl_alu_subtract);

--S1L13 is std_1c20:inst|cpu:the_cpu|A_WE_StdLogicVector~14092

--operation mode is normal

S1L13 = AMPP_FUNCTION(S1_E_extra_pc[13], YC1_result[15], S1_E_ctrl_dst_data_sel_pc_plus_one);

--S1_E_src2_imm[15] is std_1c20:inst|cpu:the_cpu|E_src2_imm[15]

--operation mode is normal

S1_E_src2_imm[15] = AMPP_FUNCTION(QC2__clk0, S1_D_iw[21], S1_D_iw[2], S1_D_iw[5], S1L227, F1_data_out, S1_W_stall);

--S1_E_src2_prelim[15] is std_1c20:inst|cpu:the_cpu|E_src2_prelim[15]

--operation mode is normal

S1_E_src2_prelim[15] = AMPP_FUNCTION(QC2__clk0, DD1_q_b[15], S1_W_wr_data[15], S1L1327, S1L396, F1_data_out, S1L392, S1_W_stall);

--S1_M_shift_rot_result[15] is std_1c20:inst|cpu:the_cpu|M_shift_rot_result[15]

--operation mode is normal

S1_M_shift_rot_result[15] = AMPP_FUNCTION(QC2__clk0, S1_M_shift_rot_result[14], S1_M_shift_rot_result[16], S1L584, S1_M_ctrl_shift_rot_right, F1_data_out, !S1_M_shift_rot_stall);

--S1L1325 is std_1c20:inst|cpu:the_cpu|M_wr_data_unfiltered[15]~3661

--operation mode is normal

S1L1325 = AMPP_FUNCTION(S1_M_shift_rot_result[15], S1_M_ctrl_shift_rot);

--S1L154 is std_1c20:inst|cpu:the_cpu|av_ld_data_aligned_or_div[15]~COMBOUT

--operation mode is normal

S1L154 = AMPP_FUNCTION(S1_d_readdata_d1[15], S1_d_readdata_d1[31], S1_M_ld_align_sh16);

--S1_av_ld_data_aligned_or_div[15] is std_1c20:inst|cpu:the_cpu|av_ld_data_aligned_or_div[15]

--operation mode is normal

S1_av_ld_data_aligned_or_div[15] = AMPP_FUNCTION(QC2__clk0, S1_d_readdata_d1[15], S1_d_readdata_d1[31], S1_av_fill_bit, S1_M_ld_align_sh16, F1_data_out, S1L778);

--S1L1326 is std_1c20:inst|cpu:the_cpu|M_wr_data_unfiltered[15]~3662

--operation mode is normal

S1L1326 = AMPP_FUNCTION(S1_av_ld_data_aligned_or_div[15], S1_M_alu_result[15], S1_av_ld_or_div_done, S1_M_ctrl_shift_rot);

--S1L749 is std_1c20:inst|cpu:the_cpu|E_sth_data[15]~472

--operation mode is normal

S1L749 = AMPP_FUNCTION(S1_E_src2_prelim[15], S1_E_src2_hazard_M, S1L1325, S1L1326);

--S1L650 is std_1c20:inst|cpu:the_cpu|E_src2[15]~1511

--operation mode is normal

S1L650 = AMPP_FUNCTION(S1_E_src2_imm[15], S1L749, S1_E_ctrl_src2_is_imm);

--S1_E_src1_prelim[15] is std_1c20:inst|cpu:the_cpu|E_src1_prelim[15]

--operation mode is normal

S1_E_src1_prelim[15] = AMPP_FUNCTION(QC2__clk0, CD1_q_b[15], S1_W_wr_data[15], S1L1327, S1_D_src1_hazard_W, F1_data_out, S1_D_src1_hazard_M, S1_W_stall);

--S1L584 is std_1c20:inst|cpu:the_cpu|E_src1[15]~2023

--operation mode is normal

S1L584 = AMPP_FUNCTION(S1_E_src1_prelim[15], S1_E_src1_hazard_M, S1L1325, S1L1326);

--S1L523 is std_1c20:inst|cpu:the_cpu|E_logic_result[15]~15601

--operation mode is normal

S1L523 = AMPP_FUNCTION(S1_E_logic_op[1], S1L650, S1L584, S1_E_logic_op[0]);

--S1_E_extra_pc[12] is std_1c20:inst|cpu:the_cpu|E_extra_pc[12]

--operation mode is normal

S1_E_extra_pc[12] = AMPP_FUNCTION(QC2__clk0, S1_D_pc_plus_one[12], S1L98, S1L214, S1_D_iw[21], F1_data_out, S1_W_stall);

--YC1_result[14] is std_1c20:inst|cpu:the_cpu|lpm_add_sub:Add8|alt_stratix_add_sub:stratix_adder|result[14]

--operation mode is arithmetic

YC1_result[14] = AMPP_FUNCTION(S1L649, S1L583, YC1L29, S1_E_ctrl_alu_subtract);

--YC1L31 is std_1c20:inst|cpu:the_cpu|lpm_add_sub:Add8|alt_stratix_add_sub:stratix_adder|add_sub_cell[14]~COUT

--operation mode is arithmetic

YC1L31 = AMPP_FUNCTION(S1L649, S1L583, YC1L29, S1_E_ctrl_alu_subtract);

--S1L14 is std_1c20:inst|cpu:the_cpu|A_WE_StdLogicVector~14093

--operation mode is normal

S1L14 = AMPP_FUNCTION(S1_E_extra_pc[12], YC1_result[14], S1_E_ctrl_dst_data_sel_pc_plus_one);

--S1_E_src2_imm[14] is std_1c20:inst|cpu:the_cpu|E_src2_imm[14]

--operation mode is normal

S1_E_src2_imm[14] = AMPP_FUNCTION(QC2__clk0, S1_D_iw[20], S1_D_iw[2], S1_D_iw[5], S1L227, F1_data_out, S1_W_stall);

--S1_E_src2_prelim[14] is std_1c20:inst|cpu:the_cpu|E_src2_prelim[14]

--operation mode is normal

S1_E_src2_prelim[14] = AMPP_FUNCTION(QC2__clk0, DD1_q_b[14], S1_W_wr_data[14], S1L1324, S1L396, F1_data_out, S1L392, S1_W_stall);

--S1_M_shift_rot_result[14] is std_1c20:inst|cpu:the_cpu|M_shift_rot_result[14]

--operation mode is normal

S1_M_shift_rot_result[14] = AMPP_FUNCTION(QC2__clk0, S1_M_shift_rot_result[13], S1_M_shift_rot_result[15], S1L583, S1_M_ctrl_shift_rot_right, F1_data_out, !S1_M_shift_rot_stall);

--S1L1322 is std_1c20:inst|cpu:the_cpu|M_wr_data_unfiltered[14]~3663

--operation mode is normal

S1L1322 = AMPP_FUNCTION(S1_M_shift_rot_result[14], S1_M_ctrl_shift_rot);

--S1L152 is std_1c20:inst|cpu:the_cpu|av_ld_data_aligned_or_div[14]~COMBOUT

--operation mode is normal

S1L152 = AMPP_FUNCTION(S1_d_readdata_d1[14], S1_d_readdata_d1[30], S1_M_ld_align_sh16);

--S1_av_ld_data_aligned_or_div[14] is std_1c20:inst|cpu:the_cpu|av_ld_data_aligned_or_div[14]

--operation mode is normal

S1_av_ld_data_aligned_or_div[14] = AMPP_FUNCTION(QC2__clk0, S1_d_readdata_d1[14], S1_d_readdata_d1[30], S1_av_fill_bit, S1_M_ld_align_sh16, F1_data_out, S1L778);

--S1L1323 is std_1c20:inst|cpu:the_cpu|M_wr_data_unfiltered[14]~3664

--operation mode is normal

S1L1323 = AMPP_FUNCTION(S1_av_ld_data_aligned_or_div[14], S1_M_alu_result[14], S1_av_ld_or_div_done, S1_M_ctrl_shift_rot);

--S1L748 is std_1c20:inst|cpu:the_cpu|E_sth_data[14]~473

--operation mode is normal

S1L748 = AMPP_FUNCTION(S1_E_src2_prelim[14], S1_E_src2_hazard_M, S1L1322, S1L1323);

--S1L649 is std_1c20:inst|cpu:the_cpu|E_src2[14]~1512

--operation mode is normal

S1L649 = AMPP_FUNCTION(S1_E_src2_imm[14], S1L748, S1_E_ctrl_src2_is_imm);

--S1_E_src1_prelim[14] is std_1c20:inst|cpu:the_cpu|E_src1_prelim[14]

--operation mode is normal

S1_E_src1_prelim[14] = AMPP_FUNCTION(QC2__clk0, CD1_q_b[14], S1_W_wr_data[14], S1L1324, S1_D_src1_hazard_W, F1_data_out, S1_D_src1_hazard_M, S1_W_stall);

--S1L583 is std_1c20:inst|cpu:the_cpu|E_src1[14]~2024

--operation mode is normal

S1L583 = AMPP_FUNCTION(S1_E_src1_prelim[14], S1_E_src1_hazard_M, S1L1322, S1L1323);

--S1L522 is std_1c20:inst|cpu:the_cpu|E_logic_result[14]~15602

--operation mode is normal

S1L522 = AMPP_FUNCTION(S1_E_logic_op[1], S1L649, S1L583, S1_E_logic_op[0]);

--S1_E_extra_pc[11] is std_1c20:inst|cpu:the_cpu|E_extra_pc[11]

--operation mode is normal

S1_E_extra_pc[11] = AMPP_FUNCTION(QC2__clk0, S1_D_pc_plus_one[11], S1L100, S1L214, S1_D_iw[21], F1_data_out, S1_W_stall);

--YC1_result[13] is std_1c20:inst|cpu:the_cpu|lpm_add_sub:Add8|alt_stratix_add_sub:stratix_adder|result[13]

--operation mode is arithmetic

YC1_result[13] = AMPP_FUNCTION(S1L648, S1L582, YC1L27, S1_E_ctrl_alu_subtract);

--YC1L29 is std_1c20:inst|cpu:the_cpu|lpm_add_sub:Add8|alt_stratix_add_sub:stratix_adder|add_sub_cell[13]~COUT

--operation mode is arithmetic

YC1L29 = AMPP_FUNCTION(S1L648, S1L582, YC1L27, S1_E_ctrl_alu_subtract);

--S1L15 is std_1c20:inst|cpu:the_cpu|A_WE_StdLogicVector~14094

--operation mode is normal

S1L15 = AMPP_FUNCTION(S1_E_extra_pc[11], YC1_result[13], S1_E_ctrl_dst_data_sel_pc_plus_one);

--S1_E_src2_imm[13] is std_1c20:inst|cpu:the_cpu|E_src2_imm[13]

--operation mode is normal

S1_E_src2_imm[13] = AMPP_FUNCTION(QC2__clk0, S1_D_iw[19], S1_D_iw[2], S1_D_iw[5], S1L227, F1_data_out, S1_W_stall);

--S1_E_src2_prelim[13] is std_1c20:inst|cpu:the_cpu|E_src2_prelim[13]

--operation mode is normal

S1_E_src2_prelim[13] = AMPP_FUNCTION(QC2__clk0, DD1_q_b[13], S1_W_wr_data[13], S1L1321, S1L396, F1_data_out, S1L392, S1_W_stall);

--S1_M_shift_rot_result[13] is std_1c20:inst|cpu:the_cpu|M_shift_rot_result[13]

--operation mode is normal

S1_M_shift_rot_result[13] = AMPP_FUNCTION(QC2__clk0, S1_M_shift_rot_result[12], S1_M_shift_rot_result[14], S1L582, S1_M_ctrl_shift_rot_right, F1_data_out, !S1_M_shift_rot_stall);

--S1L1319 is std_1c20:inst|cpu:the_cpu|M_wr_data_unfiltered[13]~3665

--operation mode is normal

S1L1319 = AMPP_FUNCTION(S1_M_shift_rot_result[13], S1_M_ctrl_shift_rot);

--S1L150 is std_1c20:inst|cpu:the_cpu|av_ld_data_aligned_or_div[13]~COMBOUT

--operation mode is normal

S1L150 = AMPP_FUNCTION(S1_d_readdata_d1[13], S1_d_readdata_d1[29], S1_M_ld_align_sh16);

--S1_av_ld_data_aligned_or_div[13] is std_1c20:inst|cpu:the_cpu|av_ld_data_aligned_or_div[13]

--operation mode is normal

S1_av_ld_data_aligned_or_div[13] = AMPP_FUNCTION(QC2__clk0, S1_d_readdata_d1[13], S1_d_readdata_d1[29], S1_av_fill_bit, S1_M_ld_align_sh16, F1_data_out, S1L778);

--S1L1320 is std_1c20:inst|cpu:the_cpu|M_wr_data_unfiltered[13]~3666

--operation mode is normal

S1L1320 = AMPP_FUNCTION(S1_av_ld_data_aligned_or_div[13], S1_M_alu_result[13], S1_av_ld_or_div_done, S1_M_ctrl_shift_rot);

--S1L747 is std_1c20:inst|cpu:the_cpu|E_sth_data[13]~474

--operation mode is normal

S1L747 = AMPP_FUNCTION(S1_E_src2_prelim[13], S1_E_src2_hazard_M, S1L1319, S1L1320);

--S1L648 is std_1c20:inst|cpu:the_cpu|E_src2[13]~1513

--operation mode is normal

S1L648 = AMPP_FUNCTION(S1_E_src2_imm[13], S1L747, S1_E_ctrl_src2_is_imm);

--S1_E_src1_prelim[13] is std_1c20:inst|cpu:the_cpu|E_src1_prelim[13]

--operation mode is normal

S1_E_src1_prelim[13] = AMPP_FUNCTION(QC2__clk0, CD1_q_b[13], S1_W_wr_data[13], S1L1321, S1_D_src1_hazard_W, F1_data_out, S1_D_src1_hazard_M, S1_W_stall);

--S1L582 is std_1c20:inst|cpu:the_cpu|E_src1[13]~2025

--operation mode is normal

S1L582 = AMPP_FUNCTION(S1_E_src1_prelim[13], S1_E_src1_hazard_M, S1L1319, S1L1320);

--S1L521 is std_1c20:inst|cpu:the_cpu|E_logic_result[13]~15603

--operation mode is normal

S1L521 = AMPP_FUNCTION(S1_E_logic_op[1], S1L648, S1L582, S1_E_logic_op[0]);

--S1_E_extra_pc[10] is std_1c20:inst|cpu:the_cpu|E_extra_pc[10]

--operation mode is normal

S1_E_extra_pc[10] = AMPP_FUNCTION(QC2__clk0, S1_D_pc_plus_one[10], S1L102, S1L214, S1_D_iw[21], F1_data_out, S1_W_stall);

--YC1_result[12] is std_1c20:inst|cpu:the_cpu|lpm_add_sub:Add8|alt_stratix_add_sub:stratix_adder|result[12]

--operation mode is arithmetic

YC1_result[12] = AMPP_FUNCTION(S1L647, S1L581, YC1L25, S1_E_ctrl_alu_subtract);

--YC1L27 is std_1c20:inst|cpu:the_cpu|lpm_add_sub:Add8|alt_stratix_add_sub:stratix_adder|add_sub_cell[12]~COUT

--operation mode is arithmetic

YC1L27 = AMPP_FUNCTION(S1L647, S1L581, YC1L25, S1_E_ctrl_alu_subtract);

--S1L16 is std_1c20:inst|cpu:the_cpu|A_WE_StdLogicVector~14095

--operation mode is normal

S1L16 = AMPP_FUNCTION(S1_E_extra_pc[10], YC1_result[12], S1_E_ctrl_dst_data_sel_pc_plus_one);

--S1_E_src2_imm[12] is std_1c20:inst|cpu:the_cpu|E_src2_imm[12]

--operation mode is normal

S1_E_src2_imm[12] = AMPP_FUNCTION(QC2__clk0, S1_D_iw[18], S1_D_iw[2], S1_D_iw[5], S1L227, F1_data_out, S1_W_stall);

--S1_E_src2_prelim[12] is std_1c20:inst|cpu:the_cpu|E_src2_prelim[12]

--operation mode is normal

S1_E_src2_prelim[12] = AMPP_FUNCTION(QC2__clk0, DD1_q_b[12], S1_W_wr_data[12], S1L1318, S1L396, F1_data_out, S1L392, S1_W_stall);

--S1_M_shift_rot_result[12] is std_1c20:inst|cpu:the_cpu|M_shift_rot_result[12]

--operation mode is normal

S1_M_shift_rot_result[12] = AMPP_FUNCTION(QC2__clk0, S1_M_shift_rot_result[11], S1_M_shift_rot_result[13], S1L581, S1_M_ctrl_shift_rot_right, F1_data_out, !S1_M_shift_rot_stall);

--S1L1316 is std_1c20:inst|cpu:the_cpu|M_wr_data_unfiltered[12]~3667

--operation mode is normal

S1L1316 = AMPP_FUNCTION(S1_M_shift_rot_result[12], S1_M_ctrl_shift_rot);

--S1L148 is std_1c20:inst|cpu:the_cpu|av_ld_data_aligned_or_div[12]~COMBOUT

--operation mode is normal

S1L148 = AMPP_FUNCTION(S1_d_readdata_d1[12], S1_d_readdata_d1[28], S1_M_ld_align_sh16);

--S1_av_ld_data_aligned_or_div[12] is std_1c20:inst|cpu:the_cpu|av_ld_data_aligned_or_div[12]

--operation mode is normal

S1_av_ld_data_aligned_or_div[12] = AMPP_FUNCTION(QC2__clk0, S1_d_readdata_d1[12], S1_d_readdata_d1[28], S1_av_fill_bit, S1_M_ld_align_sh16, F1_data_out, S1L778);

--S1L1317 is std_1c20:inst|cpu:the_cpu|M_wr_data_unfiltered[12]~3668

--operation mode is normal

S1L1317 = AMPP_FUNCTION(S1_av_ld_data_aligned_or_div[12], S1_M_alu_result[12], S1_av_ld_or_div_done, S1_M_ctrl_shift_rot);

--S1L746 is std_1c20:inst|cpu:the_cpu|E_sth_data[12]~475

--operation mode is normal

S1L746 = AMPP_FUNCTION(S1_E_src2_prelim[12], S1_E_src2_hazard_M, S1L1316, S1L1317);

--S1L647 is std_1c20:inst|cpu:the_cpu|E_src2[12]~1514

--operation mode is normal

S1L647 = AMPP_FUNCTION(S1_E_src2_imm[12], S1L746, S1_E_ctrl_src2_is_imm);

--S1_E_src1_prelim[12] is std_1c20:inst|cpu:the_cpu|E_src1_prelim[12]

--operation mode is normal

S1_E_src1_prelim[12] = AMPP_FUNCTION(QC2__clk0, CD1_q_b[12], S1_W_wr_data[12], S1L1318, S1_D_src1_hazard_W, F1_data_out, S1_D_src1_hazard_M, S1_W_stall);

--S1L581 is std_1c20:inst|cpu:the_cpu|E_src1[12]~2026

--operation mode is normal

S1L581 = AMPP_FUNCTION(S1_E_src1_prelim[12], S1_E_src1_hazard_M, S1L1316, S1L1317);

--S1L520 is std_1c20:inst|cpu:the_cpu|E_logic_result[12]~15604

--operation mode is normal

S1L520 = AMPP_FUNCTION(S1_E_logic_op[1], S1L647, S1L581, S1_E_logic_op[0]);

--S1_E_extra_pc[15] is std_1c20:inst|cpu:the_cpu|E_extra_pc[15]

--operation mode is normal

S1_E_extra_pc[15] = AMPP_FUNCTION(QC2__clk0, S1_D_pc_plus_one[15], S1L104, S1L214, S1_D_iw[21], F1_data_out, S1_W_stall);

--YC1_result[17] is std_1c20:inst|cpu:the_cpu|lpm_add_sub:Add8|alt_stratix_add_sub:stratix_adder|result[17]

--operation mode is arithmetic

YC1_result[17] = AMPP_FUNCTION(S1L652, S1L586, YC1L35, S1_E_ctrl_alu_subtract);

--YC1L37 is std_1c20:inst|cpu:the_cpu|lpm_add_sub:Add8|alt_stratix_add_sub:stratix_adder|add_sub_cell[17]~COUT

--operation mode is arithmetic

YC1L37 = AMPP_FUNCTION(S1L652, S1L586, YC1L35, S1_E_ctrl_alu_subtract);

--S1L17 is std_1c20:inst|cpu:the_cpu|A_WE_StdLogicVector~14096

--operation mode is normal

S1L17 = AMPP_FUNCTION(S1_E_extra_pc[15], YC1_result[17], S1_E_ctrl_dst_data_sel_pc_plus_one);

--S1_E_src1_prelim[17] is std_1c20:inst|cpu:the_cpu|E_src1_prelim[17]

--operation mode is normal

S1_E_src1_prelim[17] = AMPP_FUNCTION(QC2__clk0, CD1_q_b[17], S1_W_wr_data[17], S1L1333, S1_D_src1_hazard_W, F1_data_out, S1_D_src1_hazard_M, S1_W_stall);

--S1_M_shift_rot_result[17] is std_1c20:inst|cpu:the_cpu|M_shift_rot_result[17]

--operation mode is normal

S1_M_shift_rot_result[17] = AMPP_FUNCTION(QC2__clk0, S1_M_shift_rot_result[16], S1_M_shift_rot_result[18], S1L586, S1_M_ctrl_shift_rot_right, F1_data_out, !S1_M_shift_rot_stall);

--S1L1331 is std_1c20:inst|cpu:the_cpu|M_wr_data_unfiltered[17]~3669

--operation mode is normal

S1L1331 = AMPP_FUNCTION(S1_M_shift_rot_result[17], S1_M_ctrl_shift_rot);

--S1_av_ld_data_aligned_or_div[17] is std_1c20:inst|cpu:the_cpu|av_ld_data_aligned_or_div[17]

--operation mode is normal

S1_av_ld_data_aligned_or_div[17] = AMPP_FUNCTION(QC2__clk0, S1_d_readdata_d1[17], S1_M_ctrl_ld_signed, S1L174, S1_M_iw[4], F1_data_out);

--S1L1332 is std_1c20:inst|cpu:the_cpu|M_wr_data_unfiltered[17]~3670

--operation mode is normal

S1L1332 = AMPP_FUNCTION(S1_av_ld_data_aligned_or_div[17], S1_M_alu_result[17], S1_av_ld_or_div_done, S1_M_ctrl_shift_rot);

--S1L586 is std_1c20:inst|cpu:the_cpu|E_src1[17]~2027

--operation mode is normal

S1L586 = AMPP_FUNCTION(S1_E_src1_prelim[17], S1_E_src1_hazard_M, S1L1331, S1L1332);

--S1_E_src2_imm[17] is std_1c20:inst|cpu:the_cpu|E_src2_imm[17]

--operation mode is normal

S1_E_src2_imm[17] = AMPP_FUNCTION(QC2__clk0, S1_D_iw[7], S1_D_iw[21], S1L228, S1L238, F1_data_out, S1_W_stall);

--S1L1249 is std_1c20:inst|cpu:the_cpu|M_st_data[17]~COMBOUT

--operation mode is normal

S1L1249 = AMPP_FUNCTION(S1_E_src2_prelim[17], S1L1333, S1_E_src2_hazard_M);

--S1_M_st_data[17] is std_1c20:inst|cpu:the_cpu|M_st_data[17]

--operation mode is normal

S1_M_st_data[17] = AMPP_FUNCTION(QC2__clk0, S1_E_src2_prelim[17], S1L1333, S1L1233, S1_E_src2_hazard_M, F1_data_out, !S1_E_iw[4], S1_W_stall);

--S1L652 is std_1c20:inst|cpu:the_cpu|E_src2[17]~1515

--operation mode is normal

S1L652 = AMPP_FUNCTION(S1_E_src2_imm[17], S1L1249, S1_E_ctrl_src2_is_imm);

--S1L525 is std_1c20:inst|cpu:the_cpu|E_logic_result[17]~15605

--operation mode is normal

S1L525 = AMPP_FUNCTION(S1_E_logic_op[1], S1L586, S1L652, S1_E_logic_op[0]);

--S1_E_extra_pc[23] is std_1c20:inst|cpu:the_cpu|E_extra_pc[23]

--operation mode is normal

S1_E_extra_pc[23] = AMPP_FUNCTION(QC2__clk0, S1_D_pc_plus_one[23], S1L106, S1L214, S1_D_iw[21], F1_data_out, S1_W_stall);

--YC1_result[25] is std_1c20:inst|cpu:the_cpu|lpm_add_sub:Add8|alt_stratix_add_sub:stratix_adder|result[25]

--operation mode is arithmetic

YC1_result[25] = AMPP_FUNCTION(S1L660, S1L594, YC1L51, S1_E_ctrl_alu_subtract);

--YC1L53 is std_1c20:inst|cpu:the_cpu|lpm_add_sub:Add8|alt_stratix_add_sub:stratix_adder|add_sub_cell[25]~COUT

--operation mode is arithmetic

YC1L53 = AMPP_FUNCTION(S1L660, S1L594, YC1L51, S1_E_ctrl_alu_subtract);

--S1L18 is std_1c20:inst|cpu:the_cpu|A_WE_StdLogicVector~14097

--operation mode is normal

S1L18 = AMPP_FUNCTION(S1_E_extra_pc[23], YC1_result[25], S1_E_ctrl_dst_data_sel_pc_plus_one);

--S1_E_src2_imm[25] is std_1c20:inst|cpu:the_cpu|E_src2_imm[25]

--operation mode is normal

S1_E_src2_imm[25] = AMPP_FUNCTION(QC2__clk0, S1_D_iw[15], S1_D_iw[21], S1L228, S1L238, F1_data_out, S1_W_stall);

--S1_E_src2_prelim[25] is std_1c20:inst|cpu:the_cpu|E_src2_prelim[25]

--operation mode is normal

S1_E_src2_prelim[25] = AMPP_FUNCTION(QC2__clk0, DD1_q_b[25], S1_W_wr_data[25], S1L1357, S1L396, F1_data_out, S1L392, S1_W_stall);

--S1_M_shift_rot_result[25] is std_1c20:inst|cpu:the_cpu|M_shift_rot_result[25]

--operation mode is normal

S1_M_shift_rot_result[25] = AMPP_FUNCTION(QC2__clk0, S1_M_shift_rot_result[24], S1_M_shift_rot_result[26], S1L594, S1_M_ctrl_shift_rot_right, F1_data_out, !S1_M_shift_rot_stall);

--S1L1355 is std_1c20:inst|cpu:the_cpu|M_wr_data_unfiltered[25]~3671

--operation mode is normal

S1L1355 = AMPP_FUNCTION(S1_M_shift_rot_result[25], S1_M_ctrl_shift_rot);

--S1_av_ld_data_aligned_or_div[25] is std_1c20:inst|cpu:the_cpu|av_ld_data_aligned_or_div[25]

--operation mode is normal

S1_av_ld_data_aligned_or_div[25] = AMPP_FUNCTION(QC2__clk0, S1_d_readdata_d1[25], S1_M_ctrl_ld_signed, S1L174, S1_M_iw[4], F1_data_out);

--S1L1356 is std_1c20:inst|cpu:the_cpu|M_wr_data_unfiltered[25]~3672

--operation mode is normal

S1L1356 = AMPP_FUNCTION(S1_av_ld_data_aligned_or_div[25], S1_M_alu_result[25], S1_av_ld_or_div_done, S1_M_ctrl_shift_rot);

--S1L735 is std_1c20:inst|cpu:the_cpu|E_src2_reg[25]~473

--operation mode is normal

S1L735 = AMPP_FUNCTION(S1_E_src2_prelim[25], S1_E_src2_hazard_M, S1L1355, S1L1356);

--S1L660 is std_1c20:inst|cpu:the_cpu|E_src2[25]~1516

--operation mode is normal

S1L660 = AMPP_FUNCTION(S1_E_src2_imm[25], S1L735, S1_E_ctrl_src2_is_imm);

--S1_E_src1_prelim[25] is std_1c20:inst|cpu:the_cpu|E_src1_prelim[25]

--operation mode is normal

S1_E_src1_prelim[25] = AMPP_FUNCTION(QC2__clk0, CD1_q_b[25], S1_W_wr_data[25], S1L1357, S1_D_src1_hazard_W, F1_data_out, S1_D_src1_hazard_M, S1_W_stall);

--S1L594 is std_1c20:inst|cpu:the_cpu|E_src1[25]~2028

--operation mode is normal

S1L594 = AMPP_FUNCTION(S1_E_src1_prelim[25], S1_E_src1_hazard_M, S1L1355, S1L1356);

--S1L533 is std_1c20:inst|cpu:the_cpu|E_logic_result[25]~15606

--operation mode is normal

S1L533 = AMPP_FUNCTION(S1_E_logic_op[1], S1L660, S1L594, S1_E_logic_op[0]);

--S1_E_extra_pc[18] is std_1c20:inst|cpu:the_cpu|E_extra_pc[18]

--operation mode is normal

S1_E_extra_pc[18] = AMPP_FUNCTION(QC2__clk0, S1_D_pc_plus_one[18], S1L107, S1L214, S1_D_iw[21], F1_data_out, S1_W_stall);

--YC1_result[20] is std_1c20:inst|cpu:the_cpu|lpm_add_sub:Add8|alt_stratix_add_sub:stratix_adder|result[20]

--operation mode is arithmetic

YC1_result[20] = AMPP_FUNCTION(S1L655, S1L589, YC1L41, S1_E_ctrl_alu_subtract);

--YC1L43 is std_1c20:inst|cpu:the_cpu|lpm_add_sub:Add8|alt_stratix_add_sub:stratix_adder|add_sub_cell[20]~COUT

--operation mode is arithmetic

YC1L43 = AMPP_FUNCTION(S1L655, S1L589, YC1L41, S1_E_ctrl_alu_subtract);

--S1L19 is std_1c20:inst|cpu:the_cpu|A_WE_StdLogicVector~14098

--operation mode is normal

S1L19 = AMPP_FUNCTION(S1_E_extra_pc[18], YC1_result[20], S1_E_ctrl_dst_data_sel_pc_plus_one);

--S1_E_src1_prelim[20] is std_1c20:inst|cpu:the_cpu|E_src1_prelim[20]

--operation mode is normal

S1_E_src1_prelim[20] = AMPP_FUNCTION(QC2__clk0, CD1_q_b[20], S1_W_wr_data[20], S1L1342, S1_D_src1_hazard_W, F1_data_out, S1_D_src1_hazard_M, S1_W_stall);

--S1_M_shift_rot_result[20] is std_1c20:inst|cpu:the_cpu|M_shift_rot_result[20]

--operation mode is normal

S1_M_shift_rot_result[20] = AMPP_FUNCTION(QC2__clk0, S1_M_shift_rot_result[19], S1_M_shift_rot_result[21], S1L589, S1_M_ctrl_shift_rot_right, F1_data_out, !S1_M_shift_rot_stall);

--S1L1340 is std_1c20:inst|cpu:the_cpu|M_wr_data_unfiltered[20]~3673

--operation mode is normal

S1L1340 = AMPP_FUNCTION(S1_M_shift_rot_result[20], S1_M_ctrl_shift_rot);

--S1_av_ld_data_aligned_or_div[20] is std_1c20:inst|cpu:the_cpu|av_ld_data_aligned_or_div[20]

--operation mode is normal

S1_av_ld_data_aligned_or_div[20] = AMPP_FUNCTION(QC2__clk0, S1_d_readdata_d1[20], S1_M_ctrl_ld_signed, S1L174, S1_M_iw[4], F1_data_out);

--S1L1341 is std_1c20:inst|cpu:the_cpu|M_wr_data_unfiltered[20]~3674

--operation mode is normal

S1L1341 = AMPP_FUNCTION(S1_av_ld_data_aligned_or_div[20], S1_M_alu_result[20], S1_av_ld_or_div_done, S1_M_ctrl_shift_rot);

--S1L589 is std_1c20:inst|cpu:the_cpu|E_src1[20]~2029

--operation mode is normal

S1L589 = AMPP_FUNCTION(S1_E_src1_prelim[20], S1_E_src1_hazard_M, S1L1340, S1L1341);

--S1_E_src2_imm[20] is std_1c20:inst|cpu:the_cpu|E_src2_imm[20]

--operation mode is normal

S1_E_src2_imm[20] = AMPP_FUNCTION(QC2__clk0, S1_D_iw[10], S1_D_iw[21], S1L228, S1L238, F1_data_out, S1_W_stall);

--S1L1255 is std_1c20:inst|cpu:the_cpu|M_st_data[20]~COMBOUT

--operation mode is normal

S1L1255 = AMPP_FUNCTION(S1_E_src2_prelim[20], S1L1342, S1_E_src2_hazard_M);

--S1_M_st_data[20] is std_1c20:inst|cpu:the_cpu|M_st_data[20]

--operation mode is normal

S1_M_st_data[20] = AMPP_FUNCTION(QC2__clk0, S1_E_src2_prelim[20], S1L1342, S1L1239, S1_E_src2_hazard_M, F1_data_out, !S1_E_iw[4], S1_W_stall);

--S1L655 is std_1c20:inst|cpu:the_cpu|E_src2[20]~1517

--operation mode is normal

S1L655 = AMPP_FUNCTION(S1_E_src2_imm[20], S1L1255, S1_E_ctrl_src2_is_imm);

--S1L528 is std_1c20:inst|cpu:the_cpu|E_logic_result[20]~15607

--operation mode is normal

S1L528 = AMPP_FUNCTION(S1_E_logic_op[1], S1L589, S1L655, S1_E_logic_op[0]);

--S1_E_extra_pc[21] is std_1c20:inst|cpu:the_cpu|E_extra_pc[21]

--operation mode is normal

S1_E_extra_pc[21] = AMPP_FUNCTION(QC2__clk0, S1_D_pc_plus_one[21], S1L109, S1L214, S1_D_iw[21], F1_data_out, S1_W_stall);

--YC1_result[23] is std_1c20:inst|cpu:the_cpu|lpm_add_sub:Add8|alt_stratix_add_sub:stratix_adder|result[23]

--operation mode is arithmetic

YC1_result[23] = AMPP_FUNCTION(S1L658, S1L592, YC1L47, S1_E_ctrl_alu_subtract);

--YC1L49 is std_1c20:inst|cpu:the_cpu|lpm_add_sub:Add8|alt_stratix_add_sub:stratix_adder|add_sub_cell[23]~COUT

--operation mode is arithmetic

YC1L49 = AMPP_FUNCTION(S1L658, S1L592, YC1L47, S1_E_ctrl_alu_subtract);

--S1L20 is std_1c20:inst|cpu:the_cpu|A_WE_StdLogicVector~14099

--operation mode is normal

S1L20 = AMPP_FUNCTION(S1_E_extra_pc[21], YC1_result[23], S1_E_ctrl_dst_data_sel_pc_plus_one);

--S1_E_src1_prelim[23] is std_1c20:inst|cpu:the_cpu|E_src1_prelim[23]

--operation mode is normal

S1_E_src1_prelim[23] = AMPP_FUNCTION(QC2__clk0, CD1_q_b[23], S1_W_wr_data[23], S1L1351, S1_D_src1_hazard_W, F1_data_out, S1_D_src1_hazard_M, S1_W_stall);

--S1_M_shift_rot_result[23] is std_1c20:inst|cpu:the_cpu|M_shift_rot_result[23]

--operation mode is normal

S1_M_shift_rot_result[23] = AMPP_FUNCTION(QC2__clk0, S1_M_shift_rot_result[22], S1_M_shift_rot_result[24], S1L592, S1_M_ctrl_shift_rot_right, F1_data_out, !S1_M_shift_rot_stall);

--S1L1349 is std_1c20:inst|cpu:the_cpu|M_wr_data_unfiltered[23]~3675

--operation mode is normal

S1L1349 = AMPP_FUNCTION(S1_M_shift_rot_result[23], S1_M_ctrl_shift_rot);

--S1_av_ld_data_aligned_or_div[23] is std_1c20:inst|cpu:the_cpu|av_ld_data_aligned_or_div[23]

--operation mode is normal

S1_av_ld_data_aligned_or_div[23] = AMPP_FUNCTION(QC2__clk0, S1_d_readdata_d1[23], S1_M_ctrl_ld_signed, S1L174, S1_M_iw[4], F1_data_out);

--S1L1350 is std_1c20:inst|cpu:the_cpu|M_wr_data_unfiltered[23]~3676

--operation mode is normal

S1L1350 = AMPP_FUNCTION(S1_av_ld_data_aligned_or_div[23], S1_M_alu_result[23], S1_av_ld_or_div_done, S1_M_ctrl_shift_rot);

--S1L592 is std_1c20:inst|cpu:the_cpu|E_src1[23]~2030

--operation mode is normal

S1L592 = AMPP_FUNCTION(S1_E_src1_prelim[23], S1_E_src1_hazard_M, S1L1349, S1L1350);

--S1_E_src2_imm[23] is std_1c20:inst|cpu:the_cpu|E_src2_imm[23]

--operation mode is normal

S1_E_src2_imm[23] = AMPP_FUNCTION(QC2__clk0, S1_D_iw[13], S1_D_iw[21], S1L228, S1L238, F1_data_out, S1_W_stall);

--S1L1261 is std_1c20:inst|cpu:the_cpu|M_st_data[23]~COMBOUT

--operation mode is normal

S1L1261 = AMPP_FUNCTION(S1_E_src2_prelim[23], S1L1351, S1_E_src2_hazard_M);

--S1_M_st_data[23] is std_1c20:inst|cpu:the_cpu|M_st_data[23]

--operation mode is normal

S1_M_st_data[23] = AMPP_FUNCTION(QC2__clk0, S1_E_src2_prelim[23], S1L1351, S1L1245, S1_E_src2_hazard_M, F1_data_out, !S1_E_iw[4], S1_W_stall);

--S1L658 is std_1c20:inst|cpu:the_cpu|E_src2[23]~1518

--operation mode is normal

S1L658 = AMPP_FUNCTION(S1_E_src2_imm[23], S1L1261, S1_E_ctrl_src2_is_imm);

--S1L531 is std_1c20:inst|cpu:the_cpu|E_logic_result[23]~15608

--operation mode is normal

S1L531 = AMPP_FUNCTION(S1_E_logic_op[1], S1L592, S1L658, S1_E_logic_op[0]);

--S1_E_extra_pc[9] is std_1c20:inst|cpu:the_cpu|E_extra_pc[9]

--operation mode is normal

S1_E_extra_pc[9] = AMPP_FUNCTION(QC2__clk0, S1_D_pc_plus_one[9], S1_D_br_taken_waddr_partial[9], S1L214, S1_D_iw[21], F1_data_out, S1_W_stall);

--YC1_result[11] is std_1c20:inst|cpu:the_cpu|lpm_add_sub:Add8|alt_stratix_add_sub:stratix_adder|result[11]

--operation mode is arithmetic

YC1_result[11] = AMPP_FUNCTION(S1L646, S1L580, YC1L23, S1_E_ctrl_alu_subtract);

--YC1L25 is std_1c20:inst|cpu:the_cpu|lpm_add_sub:Add8|alt_stratix_add_sub:stratix_adder|add_sub_cell[11]~COUT

--operation mode is arithmetic

YC1L25 = AMPP_FUNCTION(S1L646, S1L580, YC1L23, S1_E_ctrl_alu_subtract);

--S1L21 is std_1c20:inst|cpu:the_cpu|A_WE_StdLogicVector~14100

--operation mode is normal

S1L21 = AMPP_FUNCTION(S1_E_extra_pc[9], YC1_result[11], S1_E_ctrl_dst_data_sel_pc_plus_one);

--S1_E_src2_imm[11] is std_1c20:inst|cpu:the_cpu|E_src2_imm[11]

--operation mode is normal

S1_E_src2_imm[11] = AMPP_FUNCTION(QC2__clk0, S1_D_iw[17], S1_D_iw[2], S1_D_iw[5], S1L227, F1_data_out, S1_W_stall);

--S1_E_src2_prelim[11] is std_1c20:inst|cpu:the_cpu|E_src2_prelim[11]

--operation mode is normal

S1_E_src2_prelim[11] = AMPP_FUNCTION(QC2__clk0, DD1_q_b[11], S1_W_wr_data[11], S1L1315, S1L396, F1_data_out, S1L392, S1_W_stall);

--S1_M_shift_rot_result[11] is std_1c20:inst|cpu:the_cpu|M_shift_rot_result[11]

--operation mode is normal

S1_M_shift_rot_result[11] = AMPP_FUNCTION(QC2__clk0, S1_M_shift_rot_result[10], S1_M_shift_rot_result[12], S1L580, S1_M_ctrl_shift_rot_right, F1_data_out, !S1_M_shift_rot_stall);

--S1L1313 is std_1c20:inst|cpu:the_cpu|M_wr_data_unfiltered[11]~3677

--operation mode is normal

S1L1313 = AMPP_FUNCTION(S1_M_shift_rot_result[11], S1_M_ctrl_shift_rot);

--S1L146 is std_1c20:inst|cpu:the_cpu|av_ld_data_aligned_or_div[11]~COMBOUT

--operation mode is normal

S1L146 = AMPP_FUNCTION(S1_d_readdata_d1[11], S1_d_readdata_d1[27], S1_M_ld_align_sh16);

--S1_av_ld_data_aligned_or_div[11] is std_1c20:inst|cpu:the_cpu|av_ld_data_aligned_or_div[11]

--operation mode is normal

S1_av_ld_data_aligned_or_div[11] = AMPP_FUNCTION(QC2__clk0, S1_d_readdata_d1[11], S1_d_readdata_d1[27], S1_av_fill_bit, S1_M_ld_align_sh16, F1_data_out, S1L778);

--S1L1314 is std_1c20:inst|cpu:the_cpu|M_wr_data_unfiltered[11]~3678

--operation mode is normal

S1L1314 = AMPP_FUNCTION(S1_av_ld_data_aligned_or_div[11], S1_M_alu_result[11], S1_av_ld_or_div_done, S1_M_ctrl_shift_rot);

--S1L745 is std_1c20:inst|cpu:the_cpu|E_sth_data[11]~476

--operation mode is normal

S1L745 = AMPP_FUNCTION(S1_E_src2_prelim[11], S1_E_src2_hazard_M, S1L1313, S1L1314);

--S1L646 is std_1c20:inst|cpu:the_cpu|E_src2[11]~1519

--operation mode is normal

S1L646 = AMPP_FUNCTION(S1_E_src2_imm[11], S1L745, S1_E_ctrl_src2_is_imm);

--S1_E_src1_prelim[11] is std_1c20:inst|cpu:the_cpu|E_src1_prelim[11]

--operation mode is normal

S1_E_src1_prelim[11] = AMPP_FUNCTION(QC2__clk0, CD1_q_b[11], S1_W_wr_data[11], S1L1315, S1_D_src1_hazard_W, F1_data_out, S1_D_src1_hazard_M, S1_W_stall);

--S1L580 is std_1c20:inst|cpu:the_cpu|E_src1[11]~2031

--operation mode is normal

S1L580 = AMPP_FUNCTION(S1_E_src1_prelim[11], S1_E_src1_hazard_M, S1L1313, S1L1314);

--S1L519 is std_1c20:inst|cpu:the_cpu|E_logic_result[11]~15609

--operation mode is normal

S1L519 = AMPP_FUNCTION(S1_E_logic_op[1], S1L646, S1L580, S1_E_logic_op[0]);

--S1_E_extra_pc[8] is std_1c20:inst|cpu:the_cpu|E_extra_pc[8]

--operation mode is normal

S1_E_extra_pc[8] = AMPP_FUNCTION(QC2__clk0, S1_D_pc_plus_one[8], S1_D_br_taken_waddr_partial[8], S1L214, S1_D_iw[21], F1_data_out, S1_W_stall);

--YC1_result[10] is std_1c20:inst|cpu:the_cpu|lpm_add_sub:Add8|alt_stratix_add_sub:stratix_adder|result[10]

--operation mode is arithmetic

YC1_result[10] = AMPP_FUNCTION(S1L645, S1L579, YC1L21, S1_E_ctrl_alu_subtract);

--YC1L23 is std_1c20:inst|cpu:the_cpu|lpm_add_sub:Add8|alt_stratix_add_sub:stratix_adder|add_sub_cell[10]~COUT

--operation mode is arithmetic

YC1L23 = AMPP_FUNCTION(S1L645, S1L579, YC1L21, S1_E_ctrl_alu_subtract);

--S1L22 is std_1c20:inst|cpu:the_cpu|A_WE_StdLogicVector~14101

--operation mode is normal

S1L22 = AMPP_FUNCTION(S1_E_extra_pc[8], YC1_result[10], S1_E_ctrl_dst_data_sel_pc_plus_one);

--S1_E_src2_imm[10] is std_1c20:inst|cpu:the_cpu|E_src2_imm[10]

--operation mode is normal

S1_E_src2_imm[10] = AMPP_FUNCTION(QC2__clk0, S1_D_iw[16], S1_D_iw[2], S1_D_iw[5], S1L227, F1_data_out, S1_W_stall);

--S1_E_src2_prelim[10] is std_1c20:inst|cpu:the_cpu|E_src2_prelim[10]

--operation mode is normal

S1_E_src2_prelim[10] = AMPP_FUNCTION(QC2__clk0, DD1_q_b[10], S1_W_wr_data[10], S1L1312, S1L396, F1_data_out, S1L392, S1_W_stall);

--S1_M_shift_rot_result[10] is std_1c20:inst|cpu:the_cpu|M_shift_rot_result[10]

--operation mode is normal

S1_M_shift_rot_result[10] = AMPP_FUNCTION(QC2__clk0, S1_M_shift_rot_result[9], S1_M_shift_rot_result[11], S1L579, S1_M_ctrl_shift_rot_right, F1_data_out, !S1_M_shift_rot_stall);

--S1L1310 is std_1c20:inst|cpu:the_cpu|M_wr_data_unfiltered[10]~3679

--operation mode is normal

S1L1310 = AMPP_FUNCTION(S1_M_shift_rot_result[10], S1_M_ctrl_shift_rot);

--S1L144 is std_1c20:inst|cpu:the_cpu|av_ld_data_aligned_or_div[10]~COMBOUT

--operation mode is normal

S1L144 = AMPP_FUNCTION(S1_d_readdata_d1[10], S1_d_readdata_d1[26], S1_M_ld_align_sh16);

--S1_av_ld_data_aligned_or_div[10] is std_1c20:inst|cpu:the_cpu|av_ld_data_aligned_or_div[10]

--operation mode is normal

S1_av_ld_data_aligned_or_div[10] = AMPP_FUNCTION(QC2__clk0, S1_d_readdata_d1[10], S1_d_readdata_d1[26], S1_av_fill_bit, S1_M_ld_align_sh16, F1_data_out, S1L778);

--S1L1311 is std_1c20:inst|cpu:the_cpu|M_wr_data_unfiltered[10]~3680

--operation mode is normal

S1L1311 = AMPP_FUNCTION(S1_av_ld_data_aligned_or_div[10], S1_M_alu_result[10], S1_av_ld_or_div_done, S1_M_ctrl_shift_rot);

--S1L744 is std_1c20:inst|cpu:the_cpu|E_sth_data[10]~477

--operation mode is normal

S1L744 = AMPP_FUNCTION(S1_E_src2_prelim[10], S1_E_src2_hazard_M, S1L1310, S1L1311);

--S1L645 is std_1c20:inst|cpu:the_cpu|E_src2[10]~1520

--operation mode is normal

S1L645 = AMPP_FUNCTION(S1_E_src2_imm[10], S1L744, S1_E_ctrl_src2_is_imm);

--S1_E_src1_prelim[10] is std_1c20:inst|cpu:the_cpu|E_src1_prelim[10]

--operation mode is normal

S1_E_src1_prelim[10] = AMPP_FUNCTION(QC2__clk0, CD1_q_b[10], S1_W_wr_data[10], S1L1312, S1_D_src1_hazard_W, F1_data_out, S1_D_src1_hazard_M, S1_W_stall);

--S1L579 is std_1c20:inst|cpu:the_cpu|E_src1[10]~2032

--operation mode is normal

S1L579 = AMPP_FUNCTION(S1_E_src1_prelim[10], S1_E_src1_hazard_M, S1L1310, S1L1311);

--S1L518 is std_1c20:inst|cpu:the_cpu|E_logic_result[10]~15610

--operation mode is normal

S1L518 = AMPP_FUNCTION(S1_E_logic_op[1], S1L645, S1L579, S1_E_logic_op[0]);

--S1_E_extra_pc[7] is std_1c20:inst|cpu:the_cpu|E_extra_pc[7]

--operation mode is normal

S1_E_extra_pc[7] = AMPP_FUNCTION(QC2__clk0, S1_D_pc_plus_one[7], S1_D_br_taken_waddr_partial[7], S1L214, S1_D_iw[21], F1_data_out, S1_W_stall);

--YC1_result[9] is std_1c20:inst|cpu:the_cpu|lpm_add_sub:Add8|alt_stratix_add_sub:stratix_adder|result[9]

--operation mode is arithmetic

YC1_result[9] = AMPP_FUNCTION(S1L644, S1L578, YC1L19, S1_E_ctrl_alu_subtract);

--YC1L21 is std_1c20:inst|cpu:the_cpu|lpm_add_sub:Add8|alt_stratix_add_sub:stratix_adder|add_sub_cell[9]~COUT

--operation mode is arithmetic

YC1L21 = AMPP_FUNCTION(S1L644, S1L578, YC1L19, S1_E_ctrl_alu_subtract);

--S1L23 is std_1c20:inst|cpu:the_cpu|A_WE_StdLogicVector~14102

--operation mode is normal

S1L23 = AMPP_FUNCTION(S1_E_extra_pc[7], YC1_result[9], S1_E_ctrl_dst_data_sel_pc_plus_one);

--S1_E_src2_imm[9] is std_1c20:inst|cpu:the_cpu|E_src2_imm[9]

--operation mode is normal

S1_E_src2_imm[9] = AMPP_FUNCTION(QC2__clk0, S1_D_iw[15], S1_D_iw[2], S1_D_iw[5], S1L227, F1_data_out, S1_W_stall);

--S1_E_src2_prelim[9] is std_1c20:inst|cpu:the_cpu|E_src2_prelim[9]

--operation mode is normal

S1_E_src2_prelim[9] = AMPP_FUNCTION(QC2__clk0, DD1_q_b[9], S1_W_wr_data[9], S1L1309, S1L396, F1_data_out, S1L392, S1_W_stall);

--S1_M_shift_rot_result[9] is std_1c20:inst|cpu:the_cpu|M_shift_rot_result[9]

--operation mode is normal

S1_M_shift_rot_result[9] = AMPP_FUNCTION(QC2__clk0, S1_M_shift_rot_result[8], S1_M_shift_rot_result[10], S1L578, S1_M_ctrl_shift_rot_right, F1_data_out, !S1_M_shift_rot_stall);

--S1L1307 is std_1c20:inst|cpu:the_cpu|M_wr_data_unfiltered[9]~3681

--operation mode is normal

S1L1307 = AMPP_FUNCTION(S1_M_shift_rot_result[9], S1_M_ctrl_shift_rot);

--S1L142 is std_1c20:inst|cpu:the_cpu|av_ld_data_aligned_or_div[9]~COMBOUT

--operation mode is normal

S1L142 = AMPP_FUNCTION(S1_d_readdata_d1[9], S1_d_readdata_d1[25], S1_M_ld_align_sh16);

--S1_av_ld_data_aligned_or_div[9] is std_1c20:inst|cpu:the_cpu|av_ld_data_aligned_or_div[9]

--operation mode is normal

S1_av_ld_data_aligned_or_div[9] = AMPP_FUNCTION(QC2__clk0, S1_d_readdata_d1[9], S1_d_readdata_d1[25], S1_av_fill_bit, S1_M_ld_align_sh16, F1_data_out, S1L778);

--S1L1308 is std_1c20:inst|cpu:the_cpu|M_wr_data_unfiltered[9]~3682

--operation mode is normal

S1L1308 = AMPP_FUNCTION(S1_av_ld_data_aligned_or_div[9], S1_M_alu_result[9], S1_av_ld_or_div_done, S1_M_ctrl_shift_rot);

--S1L743 is std_1c20:inst|cpu:the_cpu|E_sth_data[9]~478

--operation mode is normal

S1L743 = AMPP_FUNCTION(S1_E_src2_prelim[9], S1_E_src2_hazard_M, S1L1307, S1L1308);

--S1L644 is std_1c20:inst|cpu:the_cpu|E_src2[9]~1521

--operation mode is normal

S1L644 = AMPP_FUNCTION(S1_E_src2_imm[9], S1L743, S1_E_ctrl_src2_is_imm);

--S1_E_src1_prelim[9] is std_1c20:inst|cpu:the_cpu|E_src1_prelim[9]

--operation mode is normal

S1_E_src1_prelim[9] = AMPP_FUNCTION(QC2__clk0, CD1_q_b[9], S1_W_wr_data[9], S1L1309, S1_D_src1_hazard_W, F1_data_out, S1_D_src1_hazard_M, S1_W_stall);

--S1L578 is std_1c20:inst|cpu:the_cpu|E_src1[9]~2033

--operation mode is normal

S1L578 = AMPP_FUNCTION(S1_E_src1_prelim[9], S1_E_src1_hazard_M, S1L1307, S1L1308);

--S1L517 is std_1c20:inst|cpu:the_cpu|E_logic_result[9]~15611

--operation mode is normal

S1L517 = AMPP_FUNCTION(S1_E_logic_op[1], S1L644, S1L578, S1_E_logic_op[0]);

--S1_E_extra_pc[6] is std_1c20:inst|cpu:the_cpu|E_extra_pc[6]

--operation mode is normal

S1_E_extra_pc[6] = AMPP_FUNCTION(QC2__clk0, S1_D_pc_plus_one[6], S1_D_br_taken_waddr_partial[6], S1L214, S1_D_iw[21], F1_data_out, S1_W_stall);

--YC1_result[8] is std_1c20:inst|cpu:the_cpu|lpm_add_sub:Add8|alt_stratix_add_sub:stratix_adder|result[8]

--operation mode is arithmetic

YC1_result[8] = AMPP_FUNCTION(S1L643, S1L577, YC1L17, S1_E_ctrl_alu_subtract);

--YC1L19 is std_1c20:inst|cpu:the_cpu|lpm_add_sub:Add8|alt_stratix_add_sub:stratix_adder|add_sub_cell[8]~COUT

--operation mode is arithmetic

YC1L19 = AMPP_FUNCTION(S1L643, S1L577, YC1L17, S1_E_ctrl_alu_subtract);

--S1L24 is std_1c20:inst|cpu:the_cpu|A_WE_StdLogicVector~14103

--operation mode is normal

S1L24 = AMPP_FUNCTION(S1_E_extra_pc[6], YC1_result[8], S1_E_ctrl_dst_data_sel_pc_plus_one);

--S1_E_src2_imm[8] is std_1c20:inst|cpu:the_cpu|E_src2_imm[8]

--operation mode is normal

S1_E_src2_imm[8] = AMPP_FUNCTION(QC2__clk0, S1_D_iw[14], S1_D_iw[2], S1_D_iw[5], S1L227, F1_data_out, S1_W_stall);

--S1_E_src2_prelim[8] is std_1c20:inst|cpu:the_cpu|E_src2_prelim[8]

--operation mode is normal

S1_E_src2_prelim[8] = AMPP_FUNCTION(QC2__clk0, DD1_q_b[8], S1_W_wr_data[8], S1L1306, S1L396, F1_data_out, S1L392, S1_W_stall);

--S1_M_shift_rot_result[8] is std_1c20:inst|cpu:the_cpu|M_shift_rot_result[8]

--operation mode is normal

S1_M_shift_rot_result[8] = AMPP_FUNCTION(QC2__clk0, S1_M_shift_rot_result[7], S1_M_shift_rot_result[9], S1L577, S1_M_ctrl_shift_rot_right, F1_data_out, !S1_M_shift_rot_stall);

--S1L1304 is std_1c20:inst|cpu:the_cpu|M_wr_data_unfiltered[8]~3683

--operation mode is normal

S1L1304 = AMPP_FUNCTION(S1_M_shift_rot_result[8], S1_M_ctrl_shift_rot);

--S1L140 is std_1c20:inst|cpu:the_cpu|av_ld_data_aligned_or_div[8]~COMBOUT

--operation mode is normal

S1L140 = AMPP_FUNCTION(S1_d_readdata_d1[8], S1_d_readdata_d1[24], S1_M_ld_align_sh16);

--S1_av_ld_data_aligned_or_div[8] is std_1c20:inst|cpu:the_cpu|av_ld_data_aligned_or_div[8]

--operation mode is normal

S1_av_ld_data_aligned_or_div[8] = AMPP_FUNCTION(QC2__clk0, S1_d_readdata_d1[8], S1_d_readdata_d1[24], S1_av_fill_bit, S1_M_ld_align_sh16, F1_data_out, S1L778);

--S1L1305 is std_1c20:inst|cpu:the_cpu|M_wr_data_unfiltered[8]~3684

--operation mode is normal

S1L1305 = AMPP_FUNCTION(S1_av_ld_data_aligned_or_div[8], S1_M_alu_result[8], S1_av_ld_or_div_done, S1_M_ctrl_shift_rot);

--S1L742 is std_1c20:inst|cpu:the_cpu|E_sth_data[8]~479

--operation mode is normal

S1L742 = AMPP_FUNCTION(S1_E_src2_prelim[8], S1_E_src2_hazard_M, S1L1304, S1L1305);

--S1L643 is std_1c20:inst|cpu:the_cpu|E_src2[8]~1522

--operation mode is normal

S1L643 = AMPP_FUNCTION(S1_E_src2_imm[8], S1L742, S1_E_ctrl_src2_is_imm);

--S1_E_src1_prelim[8] is std_1c20:inst|cpu:the_cpu|E_src1_prelim[8]

--operation mode is normal

S1_E_src1_prelim[8] = AMPP_FUNCTION(QC2__clk0, CD1_q_b[8], S1_W_wr_data[8], S1L1306, S1_D_src1_hazard_W, F1_data_out, S1_D_src1_hazard_M, S1_W_stall);

--S1L577 is std_1c20:inst|cpu:the_cpu|E_src1[8]~2034

--operation mode is normal

S1L577 = AMPP_FUNCTION(S1_E_src1_prelim[8], S1_E_src1_hazard_M, S1L1304, S1L1305);

--S1L516 is std_1c20:inst|cpu:the_cpu|E_logic_result[8]~15612

--operation mode is normal

S1L516 = AMPP_FUNCTION(S1_E_logic_op[1], S1L643, S1L577, S1_E_logic_op[0]);

--S1_E_extra_pc[5] is std_1c20:inst|cpu:the_cpu|E_extra_pc[5]

--operation mode is normal

S1_E_extra_pc[5] = AMPP_FUNCTION(QC2__clk0, S1_D_pc_plus_one[5], S1_D_br_taken_waddr_partial[5], S1L214, S1_D_iw[21], F1_data_out, S1_W_stall);

--YC1_result[7] is std_1c20:inst|cpu:the_cpu|lpm_add_sub:Add8|alt_stratix_add_sub:stratix_adder|result[7]

--operation mode is arithmetic

YC1_result[7] = AMPP_FUNCTION(S1L642, S1L576, YC1L15, S1_E_ctrl_alu_subtract);

--YC1L17 is std_1c20:inst|cpu:the_cpu|lpm_add_sub:Add8|alt_stratix_add_sub:stratix_adder|add_sub_cell[7]~COUT

--operation mode is arithmetic

YC1L17 = AMPP_FUNCTION(S1L642, S1L576, YC1L15, S1_E_ctrl_alu_subtract);

--S1L25 is std_1c20:inst|cpu:the_cpu|A_WE_StdLogicVector~14104

--operation mode is normal

S1L25 = AMPP_FUNCTION(S1_E_extra_pc[5], YC1_result[7], S1_E_ctrl_dst_data_sel_pc_plus_one);

--S1_E_src1_prelim[7] is std_1c20:inst|cpu:the_cpu|E_src1_prelim[7]

--operation mode is normal

S1_E_src1_prelim[7] = AMPP_FUNCTION(QC2__clk0, CD1_q_b[7], S1_W_wr_data[7], S1L1303, S1_D_src1_hazard_W, F1_data_out, S1_D_src1_hazard_M, S1_W_stall);

--S1_M_shift_rot_result[7] is std_1c20:inst|cpu:the_cpu|M_shift_rot_result[7]

--operation mode is normal

S1_M_shift_rot_result[7] = AMPP_FUNCTION(QC2__clk0, S1_M_shift_rot_result[6], S1_M_shift_rot_result[8], S1L576, S1_M_ctrl_shift_rot_right, F1_data_out, !S1_M_shift_rot_stall);

--S1L1301 is std_1c20:inst|cpu:the_cpu|M_wr_data_unfiltered[7]~3685

--operation mode is normal

S1L1301 = AMPP_FUNCTION(S1_M_shift_rot_result[7], S1_M_ctrl_shift_rot);

--S1_av_ld_data_aligned_or_div[7] is std_1c20:inst|cpu:the_cpu|av_ld_data_aligned_or_div[7]

--operation mode is normal

S1_av_ld_data_aligned_or_div[7] = AMPP_FUNCTION(QC2__clk0, S1_d_readdata_d1[7], S1_d_readdata_d1[23], S1L154, S1_M_ld_align_sh16, F1_data_out, S1_M_ld_align_sh8);

--S1L1302 is std_1c20:inst|cpu:the_cpu|M_wr_data_unfiltered[7]~3686

--operation mode is normal

S1L1302 = AMPP_FUNCTION(S1_av_ld_data_aligned_or_div[7], S1_M_alu_result[7], S1_av_ld_or_div_done, S1_M_ctrl_shift_rot);

--S1L576 is std_1c20:inst|cpu:the_cpu|E_src1[7]~2035

--operation mode is normal

S1L576 = AMPP_FUNCTION(S1_E_src1_prelim[7], S1_E_src1_hazard_M, S1L1301, S1L1302);

--S1_E_src2_imm[7] is std_1c20:inst|cpu:the_cpu|E_src2_imm[7]

--operation mode is normal

S1_E_src2_imm[7] = AMPP_FUNCTION(QC2__clk0, S1_D_iw[13], S1_D_iw[2], S1_D_iw[5], S1L227, F1_data_out, S1_W_stall);

--S1L1245 is std_1c20:inst|cpu:the_cpu|M_st_data[15]~COMBOUT

--operation mode is normal

S1L1245 = AMPP_FUNCTION(S1_E_src2_prelim[7], S1L1303, S1_E_src2_hazard_M);

--S1_M_st_data[15] is std_1c20:inst|cpu:the_cpu|M_st_data[15]

--operation mode is normal

S1_M_st_data[15] = AMPP_FUNCTION(QC2__clk0, S1_E_src2_prelim[7], S1L1303, S1L749, S1_E_src2_hazard_M, F1_data_out, S1L777, S1_W_stall);

--S1L642 is std_1c20:inst|cpu:the_cpu|E_src2[7]~1523

--operation mode is normal

S1L642 = AMPP_FUNCTION(S1_E_src2_imm[7], S1L1245, S1_E_ctrl_src2_is_imm);

--S1L515 is std_1c20:inst|cpu:the_cpu|E_logic_result[7]~15613

--operation mode is normal

S1L515 = AMPP_FUNCTION(S1_E_logic_op[1], S1L576, S1L642, S1_E_logic_op[0]);

--S1_E_control_rd_data_without_mmu_regs[6] is std_1c20:inst|cpu:the_cpu|E_control_rd_data_without_mmu_regs[6]

--operation mode is normal

S1_E_control_rd_data_without_mmu_regs[6] = AMPP_FUNCTION(QC2__clk0, S1_M_ipending_reg[6], S1_M_ienable_reg[6], S1_D_iw[8], S1L200, F1_data_out, S1_W_stall);

--S1_E_src1_prelim[6] is std_1c20:inst|cpu:the_cpu|E_src1_prelim[6]

--operation mode is normal

S1_E_src1_prelim[6] = AMPP_FUNCTION(QC2__clk0, CD1_q_b[6], S1_W_wr_data[6], S1L1300, S1_D_src1_hazard_W, F1_data_out, S1_D_src1_hazard_M, S1_W_stall);

--S1_M_shift_rot_result[6] is std_1c20:inst|cpu:the_cpu|M_shift_rot_result[6]

--operation mode is normal

S1_M_shift_rot_result[6] = AMPP_FUNCTION(QC2__clk0, S1_M_shift_rot_result[5], S1_M_shift_rot_result[7], S1L575, S1_M_ctrl_shift_rot_right, F1_data_out, !S1_M_shift_rot_stall);

--S1L1298 is std_1c20:inst|cpu:the_cpu|M_wr_data_unfiltered[6]~3687

--operation mode is normal

S1L1298 = AMPP_FUNCTION(S1_M_shift_rot_result[6], S1_M_ctrl_shift_rot);

--S1_av_ld_data_aligned_or_div[6] is std_1c20:inst|cpu:the_cpu|av_ld_data_aligned_or_div[6]

--operation mode is normal

S1_av_ld_data_aligned_or_div[6] = AMPP_FUNCTION(QC2__clk0, T1_cpu_data_master_readdata[6], S1_d_readdata_d1[22], S1L152, S1_M_ld_align_sh16, F1_data_out, S1_M_ld_align_sh8);

--S1L1299 is std_1c20:inst|cpu:the_cpu|M_wr_data_unfiltered[6]~3688

--operation mode is normal

S1L1299 = AMPP_FUNCTION(S1_av_ld_data_aligned_or_div[6], S1_M_alu_result[6], S1_av_ld_or_div_done, S1_M_ctrl_shift_rot);

--S1L575 is std_1c20:inst|cpu:the_cpu|E_src1[6]~2036

--operation mode is normal

S1L575 = AMPP_FUNCTION(S1_E_src1_prelim[6], S1_E_src1_hazard_M, S1L1298, S1L1299);

--S1_E_src2_imm[6] is std_1c20:inst|cpu:the_cpu|E_src2_imm[6]

--operation mode is normal

S1_E_src2_imm[6] = AMPP_FUNCTION(QC2__clk0, S1_D_iw[12], S1_D_iw[2], S1_D_iw[5], S1L227, F1_data_out, S1_W_stall);

--S1L1243 is std_1c20:inst|cpu:the_cpu|M_st_data[14]~COMBOUT

--operation mode is normal

S1L1243 = AMPP_FUNCTION(S1_E_src2_prelim[6], S1L1300, S1_E_src2_hazard_M);

--S1_M_st_data[14] is std_1c20:inst|cpu:the_cpu|M_st_data[14]

--operation mode is normal

S1_M_st_data[14] = AMPP_FUNCTION(QC2__clk0, S1_E_src2_prelim[6], S1L1300, S1L748, S1_E_src2_hazard_M, F1_data_out, S1L777, S1_W_stall);

--S1L641 is std_1c20:inst|cpu:the_cpu|E_src2[6]~1524

--operation mode is normal

S1L641 = AMPP_FUNCTION(S1_E_src2_imm[6], S1L1243, S1_E_ctrl_src2_is_imm);

--S1L26 is std_1c20:inst|cpu:the_cpu|A_WE_StdLogicVector~14105

--operation mode is normal

S1L26 = AMPP_FUNCTION(S1_E_logic_op[1], S1L575, S1L641, S1_E_logic_op[0]);

--S1_E_extra_pc[4] is std_1c20:inst|cpu:the_cpu|E_extra_pc[4]

--operation mode is normal

S1_E_extra_pc[4] = AMPP_FUNCTION(QC2__clk0, S1_D_pc_plus_one[4], S1_D_br_taken_waddr_partial[4], S1L214, S1_D_iw[21], F1_data_out, S1_W_stall);

--YC1_result[6] is std_1c20:inst|cpu:the_cpu|lpm_add_sub:Add8|alt_stratix_add_sub:stratix_adder|result[6]

--operation mode is arithmetic

YC1_result[6] = AMPP_FUNCTION(S1L641, S1L575, YC1L13, S1_E_ctrl_alu_subtract);

--YC1L15 is std_1c20:inst|cpu:the_cpu|lpm_add_sub:Add8|alt_stratix_add_sub:stratix_adder|add_sub_cell[6]~COUT

--operation mode is arithmetic

YC1L15 = AMPP_FUNCTION(S1L641, S1L575, YC1L13, S1_E_ctrl_alu_subtract);

--S1L27 is std_1c20:inst|cpu:the_cpu|A_WE_StdLogicVector~14106

--operation mode is normal

S1L27 = AMPP_FUNCTION(S1_E_extra_pc[4], YC1_result[6], S1_E_ctrl_dst_data_sel_pc_plus_one);

--S1L28 is std_1c20:inst|cpu:the_cpu|A_WE_StdLogicVector~14107

--operation mode is normal

S1L28 = AMPP_FUNCTION(S1L26, S1L27, S1_E_ctrl_dst_data_sel_logic_result);

--S1L412 is std_1c20:inst|cpu:the_cpu|E_alu_result[6]~2394

--operation mode is normal

S1L412 = AMPP_FUNCTION(S1_E_control_rd_data_without_mmu_regs[6], S1L28, S1_E_ctrl_rdctl_inst, S1_E_ctrl_dst_data_sel_cmp);

--S1_E_ctrl_st is std_1c20:inst|cpu:the_cpu|E_ctrl_st

--operation mode is normal

S1_E_ctrl_st = AMPP_FUNCTION(QC2__clk0, S1_D_iw[0], S1_D_iw[1], F1_data_out, S1_W_stall);

--S1_E_control_rd_data_without_mmu_regs[4] is std_1c20:inst|cpu:the_cpu|E_control_rd_data_without_mmu_regs[4]

--operation mode is normal

S1_E_control_rd_data_without_mmu_regs[4] = AMPP_FUNCTION(QC2__clk0, S1_M_ipending_reg[4], S1_M_ienable_reg[4], S1_D_iw[8], S1L200, F1_data_out, S1_W_stall);

--S1_E_src1_prelim[4] is std_1c20:inst|cpu:the_cpu|E_src1_prelim[4]

--operation mode is normal

S1_E_src1_prelim[4] = AMPP_FUNCTION(QC2__clk0, CD1_q_b[4], S1_W_wr_data[4], S1L1294, S1_D_src1_hazard_W, F1_data_out, S1_D_src1_hazard_M, S1_W_stall);

--S1_M_shift_rot_result[4] is std_1c20:inst|cpu:the_cpu|M_shift_rot_result[4]

--operation mode is normal

S1_M_shift_rot_result[4] = AMPP_FUNCTION(QC2__clk0, S1_M_shift_rot_result[3], S1_M_shift_rot_result[5], S1L573, S1_M_ctrl_shift_rot_right, F1_data_out, !S1_M_shift_rot_stall);

--S1L1292 is std_1c20:inst|cpu:the_cpu|M_wr_data_unfiltered[4]~3689

--operation mode is normal

S1L1292 = AMPP_FUNCTION(S1_M_shift_rot_result[4], S1_M_ctrl_shift_rot);

--S1_av_ld_data_aligned_or_div[4] is std_1c20:inst|cpu:the_cpu|av_ld_data_aligned_or_div[4]

--operation mode is normal

S1_av_ld_data_aligned_or_div[4] = AMPP_FUNCTION(QC2__clk0, T1_cpu_data_master_readdata[4], S1_d_readdata_d1[20], S1L148, S1_M_ld_align_sh16, F1_data_out, S1_M_ld_align_sh8);

--S1L1293 is std_1c20:inst|cpu:the_cpu|M_wr_data_unfiltered[4]~3690

--operation mode is normal

S1L1293 = AMPP_FUNCTION(S1_av_ld_data_aligned_or_div[4], S1_M_alu_result[4], S1_av_ld_or_div_done, S1_M_ctrl_shift_rot);

--S1L573 is std_1c20:inst|cpu:the_cpu|E_src1[4]~2037

--operation mode is normal

S1L573 = AMPP_FUNCTION(S1_E_src1_prelim[4], S1_E_src1_hazard_M, S1L1292, S1L1293);

--S1_E_src2_imm[4] is std_1c20:inst|cpu:the_cpu|E_src2_imm[4]

--operation mode is normal

S1_E_src2_imm[4] = AMPP_FUNCTION(QC2__clk0, S1_D_iw[10], S1_D_iw[2], S1_D_iw[5], S1L227, F1_data_out, S1_W_stall);

--S1L1239 is std_1c20:inst|cpu:the_cpu|M_st_data[12]~COMBOUT

--operation mode is normal

S1L1239 = AMPP_FUNCTION(S1_E_src2_prelim[4], S1L1294, S1_E_src2_hazard_M);

--S1_M_st_data[12] is std_1c20:inst|cpu:the_cpu|M_st_data[12]

--operation mode is normal

S1_M_st_data[12] = AMPP_FUNCTION(QC2__clk0, S1_E_src2_prelim[4], S1L1294, S1L746, S1_E_src2_hazard_M, F1_data_out, S1L777, S1_W_stall);

--S1L639 is std_1c20:inst|cpu:the_cpu|E_src2[4]~1525

--operation mode is normal

S1L639 = AMPP_FUNCTION(S1_E_src2_imm[4], S1L1239, S1_E_ctrl_src2_is_imm);

--S1L29 is std_1c20:inst|cpu:the_cpu|A_WE_StdLogicVector~14108

--operation mode is normal

S1L29 = AMPP_FUNCTION(S1_E_logic_op[1], S1L573, S1L639, S1_E_logic_op[0]);

--S1_E_extra_pc[2] is std_1c20:inst|cpu:the_cpu|E_extra_pc[2]

--operation mode is normal

S1_E_extra_pc[2] = AMPP_FUNCTION(QC2__clk0, S1_D_pc_plus_one[2], S1_D_br_taken_waddr_partial[2], S1L214, S1_D_iw[21], F1_data_out, S1_W_stall);

--YC1_result[4] is std_1c20:inst|cpu:the_cpu|lpm_add_sub:Add8|alt_stratix_add_sub:stratix_adder|result[4]

--operation mode is arithmetic

YC1_result[4] = AMPP_FUNCTION(S1L639, S1L573, YC1L9, S1_E_ctrl_alu_subtract);

--YC1L11 is std_1c20:inst|cpu:the_cpu|lpm_add_sub:Add8|alt_stratix_add_sub:stratix_adder|add_sub_cell[4]~COUT

--operation mode is arithmetic

YC1L11 = AMPP_FUNCTION(S1L639, S1L573, YC1L9, S1_E_ctrl_alu_subtract);

--S1L30 is std_1c20:inst|cpu:the_cpu|A_WE_StdLogicVector~14109

--operation mode is normal

S1L30 = AMPP_FUNCTION(S1_E_extra_pc[2], YC1_result[4], S1_E_ctrl_dst_data_sel_pc_plus_one);

--S1L31 is std_1c20:inst|cpu:the_cpu|A_WE_StdLogicVector~14110

--operation mode is normal

S1L31 = AMPP_FUNCTION(S1L29, S1L30, S1_E_ctrl_dst_data_sel_logic_result);

--S1L410 is std_1c20:inst|cpu:the_cpu|E_alu_result[4]~2395

--operation mode is normal

S1L410 = AMPP_FUNCTION(S1_E_control_rd_data_without_mmu_regs[4], S1L31, S1_E_ctrl_rdctl_inst, S1_E_ctrl_dst_data_sel_cmp);

--EB1L1 is std_1c20:inst|lcd_display_control_slave_arbitrator:the_lcd_display_control_slave|Add0~99

--operation mode is arithmetic

EB1L1_carry_eqn = EB1L4;

EB1L1 = EB1_lcd_display_control_slave_wait_counter[1] $ (!EB1L1_carry_eqn);

--EB1L2 is std_1c20:inst|lcd_display_control_slave_arbitrator:the_lcd_display_control_slave|Add0~100

--operation mode is arithmetic

EB1L2 = CARRY(!EB1_lcd_display_control_slave_wait_counter[1] & (!EB1L4));

--EB1L23 is std_1c20:inst|lcd_display_control_slave_arbitrator:the_lcd_display_control_slave|lcd_display_control_slave_wait_counter[1]~72

--operation mode is normal

EB1L23 = !EB1_lcd_display_control_slave_wait_counter[1] & !EB1_lcd_display_control_slave_wait_counter[2];

--EB1L15 is std_1c20:inst|lcd_display_control_slave_arbitrator:the_lcd_display_control_slave|Equal2~97

--operation mode is normal

EB1L15 = EB1L29 & EB1L23 & !EB1_lcd_display_control_slave_wait_counter[0] & !EB1_lcd_display_control_slave_wait_counter[3];

--EB1L19 is std_1c20:inst|lcd_display_control_slave_arbitrator:the_lcd_display_control_slave|lcd_display_control_slave_in_a_write_cycle~49

--operation mode is normal

EB1L19 = S1_internal_d_write & JB1L3 & !S1_M_alu_result[5] & !EB1_d1_reasons_to_wait;

--EB1L3 is std_1c20:inst|lcd_display_control_slave_arbitrator:the_lcd_display_control_slave|Add0~101

--operation mode is arithmetic

EB1L3 = !EB1_lcd_display_control_slave_wait_counter[0];

--EB1L4 is std_1c20:inst|lcd_display_control_slave_arbitrator:the_lcd_display_control_slave|Add0~102

--operation mode is arithmetic

EB1L4 = CARRY(EB1_lcd_display_control_slave_wait_counter[0]);

--EB1L17 is std_1c20:inst|lcd_display_control_slave_arbitrator:the_lcd_display_control_slave|lcd_display_control_slave_counter_load_value~1

--operation mode is normal

EB1L17 = S1_M_alu_result[5] # EB1_d1_reasons_to_wait # !JB1L3 # !S1_internal_d_read;

--EB1L5 is std_1c20:inst|lcd_display_control_slave_arbitrator:the_lcd_display_control_slave|Add0~103

--operation mode is arithmetic

EB1L5_carry_eqn = EB1L8;

EB1L5 = EB1_lcd_display_control_slave_wait_counter[3] $ (!EB1L5_carry_eqn);

--EB1L6 is std_1c20:inst|lcd_display_control_slave_arbitrator:the_lcd_display_control_slave|Add0~104

--operation mode is arithmetic

EB1L6 = CARRY(!EB1_lcd_display_control_slave_wait_counter[3] & (!EB1L8));

--EB1L7 is std_1c20:inst|lcd_display_control_slave_arbitrator:the_lcd_display_control_slave|Add0~105

--operation mode is arithmetic

EB1L7_carry_eqn = EB1L2;

EB1L7 = EB1_lcd_display_control_slave_wait_counter[2] $ (EB1L7_carry_eqn);

--EB1L8 is std_1c20:inst|lcd_display_control_slave_arbitrator:the_lcd_display_control_slave|Add0~106

--operation mode is arithmetic

EB1L8 = CARRY(EB1_lcd_display_control_slave_wait_counter[2] # !EB1L2);

--EB1L9 is std_1c20:inst|lcd_display_control_slave_arbitrator:the_lcd_display_control_slave|Add0~107

--operation mode is normal

EB1L9_carry_eqn = EB1L11;

EB1L9 = EB1_lcd_display_control_slave_wait_counter[5] $ (!EB1L9_carry_eqn);

--EB1L10 is std_1c20:inst|lcd_display_control_slave_arbitrator:the_lcd_display_control_slave|Add0~109

--operation mode is arithmetic

EB1L10_carry_eqn = EB1L6;

EB1L10 = EB1_lcd_display_control_slave_wait_counter[4] $ (EB1L10_carry_eqn);

--EB1L11 is std_1c20:inst|lcd_display_control_slave_arbitrator:the_lcd_display_control_slave|Add0~110

--operation mode is arithmetic

EB1L11 = CARRY(EB1_lcd_display_control_slave_wait_counter[4] # !EB1L6);

--S1_E_control_rd_data_without_mmu_regs[5] is std_1c20:inst|cpu:the_cpu|E_control_rd_data_without_mmu_regs[5]

--operation mode is normal

S1_E_control_rd_data_without_mmu_regs[5] = AMPP_FUNCTION(QC2__clk0, S1_M_ipending_reg[5], S1_M_ienable_reg[5], S1_D_iw[8], S1L200, F1_data_out, S1_W_stall);

--S1_E_src1_prelim[5] is std_1c20:inst|cpu:the_cpu|E_src1_prelim[5]

--operation mode is normal

S1_E_src1_prelim[5] = AMPP_FUNCTION(QC2__clk0, CD1_q_b[5], S1_W_wr_data[5], S1L1297, S1_D_src1_hazard_W, F1_data_out, S1_D_src1_hazard_M, S1_W_stall);

--S1_M_shift_rot_result[5] is std_1c20:inst|cpu:the_cpu|M_shift_rot_result[5]

--operation mode is normal

S1_M_shift_rot_result[5] = AMPP_FUNCTION(QC2__clk0, S1_M_shift_rot_result[4], S1_M_shift_rot_result[6], S1L574, S1_M_ctrl_shift_rot_right, F1_data_out, !S1_M_shift_rot_stall);

--S1L1295 is std_1c20:inst|cpu:the_cpu|M_wr_data_unfiltered[5]~3691

--operation mode is normal

S1L1295 = AMPP_FUNCTION(S1_M_shift_rot_result[5], S1_M_ctrl_shift_rot);

--S1_av_ld_data_aligned_or_div[5] is std_1c20:inst|cpu:the_cpu|av_ld_data_aligned_or_div[5]

--operation mode is normal

S1_av_ld_data_aligned_or_div[5] = AMPP_FUNCTION(QC2__clk0, T1_cpu_data_master_readdata[5], S1_d_readdata_d1[21], S1L150, S1_M_ld_align_sh16, F1_data_out, S1_M_ld_align_sh8);

--S1L1296 is std_1c20:inst|cpu:the_cpu|M_wr_data_unfiltered[5]~3692

--operation mode is normal

S1L1296 = AMPP_FUNCTION(S1_av_ld_data_aligned_or_div[5], S1_M_alu_result[5], S1_av_ld_or_div_done, S1_M_ctrl_shift_rot);

--S1L574 is std_1c20:inst|cpu:the_cpu|E_src1[5]~2038

--operation mode is normal

S1L574 = AMPP_FUNCTION(S1_E_src1_prelim[5], S1_E_src1_hazard_M, S1L1295, S1L1296);

--S1_E_src2_imm[5] is std_1c20:inst|cpu:the_cpu|E_src2_imm[5]

--operation mode is normal

S1_E_src2_imm[5] = AMPP_FUNCTION(QC2__clk0, S1_D_iw[11], S1_D_iw[2], S1_D_iw[5], S1L227, F1_data_out, S1_W_stall);

--S1L1241 is std_1c20:inst|cpu:the_cpu|M_st_data[13]~COMBOUT

--operation mode is normal

S1L1241 = AMPP_FUNCTION(S1_E_src2_prelim[5], S1L1297, S1_E_src2_hazard_M);

--S1_M_st_data[13] is std_1c20:inst|cpu:the_cpu|M_st_data[13]

--operation mode is normal

S1_M_st_data[13] = AMPP_FUNCTION(QC2__clk0, S1_E_src2_prelim[5], S1L1297, S1L747, S1_E_src2_hazard_M, F1_data_out, S1L777, S1_W_stall);

--S1L640 is std_1c20:inst|cpu:the_cpu|E_src2[5]~1526

--operation mode is normal

S1L640 = AMPP_FUNCTION(S1_E_src2_imm[5], S1L1241, S1_E_ctrl_src2_is_imm);

--S1L32 is std_1c20:inst|cpu:the_cpu|A_WE_StdLogicVector~14111

--operation mode is normal

S1L32 = AMPP_FUNCTION(S1_E_logic_op[1], S1L574, S1L640, S1_E_logic_op[0]);

--S1_E_extra_pc[3] is std_1c20:inst|cpu:the_cpu|E_extra_pc[3]

--operation mode is normal

S1_E_extra_pc[3] = AMPP_FUNCTION(QC2__clk0, S1_D_pc_plus_one[3], S1_D_br_taken_waddr_partial[3], S1L214, S1_D_iw[21], F1_data_out, S1_W_stall);

--YC1_result[5] is std_1c20:inst|cpu:the_cpu|lpm_add_sub:Add8|alt_stratix_add_sub:stratix_adder|result[5]

--operation mode is arithmetic

YC1_result[5] = AMPP_FUNCTION(S1L640, S1L574, YC1L11, S1_E_ctrl_alu_subtract);

--YC1L13 is std_1c20:inst|cpu:the_cpu|lpm_add_sub:Add8|alt_stratix_add_sub:stratix_adder|add_sub_cell[5]~COUT

--operation mode is arithmetic

YC1L13 = AMPP_FUNCTION(S1L640, S1L574, YC1L11, S1_E_ctrl_alu_subtract);

--S1L33 is std_1c20:inst|cpu:the_cpu|A_WE_StdLogicVector~14112

--operation mode is normal

S1L33 = AMPP_FUNCTION(S1_E_extra_pc[3], YC1_result[5], S1_E_ctrl_dst_data_sel_pc_plus_one);

--S1L34 is std_1c20:inst|cpu:the_cpu|A_WE_StdLogicVector~14113

--operation mode is normal

S1L34 = AMPP_FUNCTION(S1L32, S1L33, S1_E_ctrl_dst_data_sel_logic_result);

--S1L411 is std_1c20:inst|cpu:the_cpu|E_alu_result[5]~2396

--operation mode is normal

S1L411 = AMPP_FUNCTION(S1_E_control_rd_data_without_mmu_regs[5], S1L34, S1_E_ctrl_rdctl_inst, S1_E_ctrl_dst_data_sel_cmp);

--YC1_result[0] is std_1c20:inst|cpu:the_cpu|lpm_add_sub:Add8|alt_stratix_add_sub:stratix_adder|result[0]

--operation mode is arithmetic

YC1_result[0] = AMPP_FUNCTION(S1L635, S1L569);

--YC1L3 is std_1c20:inst|cpu:the_cpu|lpm_add_sub:Add8|alt_stratix_add_sub:stratix_adder|add_sub_cell[0]~COUT

--operation mode is arithmetic

YC1L3 = AMPP_FUNCTION(S1L635, S1L569, S1_E_ctrl_alu_subtract);

--YC1_result[1] is std_1c20:inst|cpu:the_cpu|lpm_add_sub:Add8|alt_stratix_add_sub:stratix_adder|result[1]

--operation mode is arithmetic

YC1_result[1] = AMPP_FUNCTION(S1L636, S1L570, YC1L3, S1_E_ctrl_alu_subtract);

--YC1L5 is std_1c20:inst|cpu:the_cpu|lpm_add_sub:Add8|alt_stratix_add_sub:stratix_adder|add_sub_cell[1]~COUT

--operation mode is arithmetic

YC1L5 = AMPP_FUNCTION(S1L636, S1L570, YC1L3, S1_E_ctrl_alu_subtract);

--Y1L284 is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|p1_ext_ram_bus_address[22]~3406

--operation mode is normal

Y1L284 = !Y1L84 & (!Y1L13 & !Y1L15 # !Y1L61);

--Y1L50 is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|cpu_data_master_granted_ext_flash_s1~57

--operation mode is normal

Y1L50 = Y1L55 & (Y1L17 # Y1L19);

--Y1L285 is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|p1_ext_ram_bus_address[22]~3407

--operation mode is normal

Y1L285 = S1_ic_fill_tag[10] & !Y1L50 & (Y1L82 # !Y1L51);

--Y1L283 is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|p1_ext_ram_bus_address[21]~3409

--operation mode is normal

Y1L283 = S1_ic_fill_tag[9] & !Y1L50 & (Y1L82 # !Y1L51);

--Y1L1 is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|A_WE_StdLogicVector~4277

--operation mode is normal

Y1L1 = S1_M_alu_result[20] & Y1L50 & (!Y1L84);

--Y1L2 is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|A_WE_StdLogicVector~4278

--operation mode is normal

Y1L2 = !Y1L84 & (Y1L50 # Y1L51 & !Y1L82);

--Y1L286 is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|p1_ext_ram_bus_address[22]~3412

--operation mode is normal

Y1L286 = !Y1L50 & (Y1L82 # !Y1L51);

--S1_ic_fill_tag[3] is std_1c20:inst|cpu:the_cpu|ic_fill_tag[3]

--operation mode is normal

S1_ic_fill_tag[3] = AMPP_FUNCTION(QC2__clk0, S1_D_pc[13], F1_data_out, S1_D_ic_fill_starting);

--S1_ic_fill_tag[2] is std_1c20:inst|cpu:the_cpu|ic_fill_tag[2]

--operation mode is normal

S1_ic_fill_tag[2] = AMPP_FUNCTION(QC2__clk0, S1_D_pc[12], F1_data_out, S1_D_ic_fill_starting);

--S1_ic_fill_tag[1] is std_1c20:inst|cpu:the_cpu|ic_fill_tag[1]

--operation mode is normal

S1_ic_fill_tag[1] = AMPP_FUNCTION(QC2__clk0, S1_D_pc[11], F1_data_out, S1_D_ic_fill_starting);

--S1_ic_fill_tag[0] is std_1c20:inst|cpu:the_cpu|ic_fill_tag[0]

--operation mode is normal

S1_ic_fill_tag[0] = AMPP_FUNCTION(QC2__clk0, S1_D_pc[10], F1_data_out, S1_D_ic_fill_starting);

--S1_ic_fill_line[6] is std_1c20:inst|cpu:the_cpu|ic_fill_line[6]

--operation mode is normal

S1_ic_fill_line[6] = AMPP_FUNCTION(QC2__clk0, S1L1056, F1_data_out);

--S1_ic_fill_line[5] is std_1c20:inst|cpu:the_cpu|ic_fill_line[5]

--operation mode is normal

S1_ic_fill_line[5] = AMPP_FUNCTION(QC2__clk0, S1L1054, F1_data_out);

--S1_ic_fill_line[4] is std_1c20:inst|cpu:the_cpu|ic_fill_line[4]

--operation mode is normal

S1_ic_fill_line[4] = AMPP_FUNCTION(QC2__clk0, S1L1052, F1_data_out);

--S1_ic_fill_line[3] is std_1c20:inst|cpu:the_cpu|ic_fill_line[3]

--operation mode is normal

S1_ic_fill_line[3] = AMPP_FUNCTION(QC2__clk0, S1L1050, F1_data_out);

--S1_ic_fill_line[2] is std_1c20:inst|cpu:the_cpu|ic_fill_line[2]

--operation mode is normal

S1_ic_fill_line[2] = AMPP_FUNCTION(QC2__clk0, S1L1048, F1_data_out);

--S1_ic_fill_line[1] is std_1c20:inst|cpu:the_cpu|ic_fill_line[1]

--operation mode is normal

S1_ic_fill_line[1] = AMPP_FUNCTION(QC2__clk0, S1L1046, F1_data_out);

--S1_ic_fill_line[0] is std_1c20:inst|cpu:the_cpu|ic_fill_line[0]

--operation mode is normal

S1_ic_fill_line[0] = AMPP_FUNCTION(QC2__clk0, S1L1004, F1_data_out);

--S1_ic_fill_ap_offset[2] is std_1c20:inst|cpu:the_cpu|ic_fill_ap_offset[2]

--operation mode is normal

S1_ic_fill_ap_offset[2] = AMPP_FUNCTION(QC2__clk0, S1_D_pc[2], S1_ic_fill_ap_offset[2], S1L113, S1_D_ic_fill_starting, F1_data_out, S1_ic_fill_req_accepted);

--S1_ic_fill_ap_offset[1] is std_1c20:inst|cpu:the_cpu|ic_fill_ap_offset[1]

--operation mode is normal

S1_ic_fill_ap_offset[1] = AMPP_FUNCTION(QC2__clk0, S1_D_pc[1], S1_ic_fill_ap_offset[1], S1L114, S1_D_ic_fill_starting, F1_data_out, S1_ic_fill_req_accepted);

--S1_ic_fill_ap_offset[0] is std_1c20:inst|cpu:the_cpu|ic_fill_ap_offset[0]

--operation mode is normal

S1_ic_fill_ap_offset[0] = AMPP_FUNCTION(QC2__clk0, S1_D_pc[0], S1_ic_fill_ap_offset[0], S1L979, S1_D_ic_fill_starting, F1_data_out, S1_ic_fill_req_accepted);

--S1_M_alu_result[1] is std_1c20:inst|cpu:the_cpu|M_alu_result[1]

--operation mode is normal

S1_M_alu_result[1] = AMPP_FUNCTION(QC2__clk0, S1L407, F1_data_out, S1_W_stall);

--Y1L279 is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|p1_ext_ram_bus_address[0]~3431

--operation mode is normal

Y1L279 = Y1L52 # Y1L51 & Y1L281 & !Y1L84;

--U1_internal_cpu_instruction_master_dbs_address[1] is std_1c20:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|internal_cpu_instruction_master_dbs_address[1]

--operation mode is normal

U1_internal_cpu_instruction_master_dbs_address[1]_lut_out = U1_internal_cpu_instruction_master_dbs_address[1] $ (Y1L82 & U1_internal_cpu_instruction_master_dbs_address[0] & U1L166);

U1_internal_cpu_instruction_master_dbs_address[1] = DFFEAS(U1_internal_cpu_instruction_master_dbs_address[1]_lut_out, QC2__clk0, F1_data_out, , , , , , );

--Y1L282 is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|p1_ext_ram_bus_address[1]~3432

--operation mode is normal

Y1L282 = Y1L50 & T1_internal_cpu_data_master_dbs_address[1] # !Y1L50 & (Y1L82 & U1_internal_cpu_instruction_master_dbs_address[1]);

--S1_M_alu_result[0] is std_1c20:inst|cpu:the_cpu|M_alu_result[0]

--operation mode is normal

S1_M_alu_result[0] = AMPP_FUNCTION(QC2__clk0, S1L404, F1_data_out, S1_W_stall);

--U1_internal_cpu_instruction_master_dbs_address[0] is std_1c20:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|internal_cpu_instruction_master_dbs_address[0]

--operation mode is normal

U1_internal_cpu_instruction_master_dbs_address[0]_lut_out = U1_internal_cpu_instruction_master_dbs_address[0] $ (Y1_d1_ext_ram_bus_avalon_slave_end_xfer & Y1L137 & Y1L82);

U1_internal_cpu_instruction_master_dbs_address[0] = DFFEAS(U1_internal_cpu_instruction_master_dbs_address[0]_lut_out, QC2__clk0, F1_data_out, , , , , , );

--Y1L280 is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|p1_ext_ram_bus_address[0]~3434

--operation mode is normal

Y1L280 = Y1L50 & T1_internal_cpu_data_master_dbs_address[0] # !Y1L50 & (Y1L82 & U1_internal_cpu_instruction_master_dbs_address[0]);

--S1_M_st_data[7] is std_1c20:inst|cpu:the_cpu|M_st_data[7]

--operation mode is normal

S1_M_st_data[7] = AMPP_FUNCTION(QC2__clk0, S1L1245, F1_data_out, S1_W_stall);

--ZE1L33 is std_1c20:inst|uart1:the_uart1|uart1_tx:the_uart1_tx|tx_wr_strobe_onset~34

--operation mode is normal

ZE1L33 = UB1L5 & UB1L6 & S1_M_alu_result[6] & !S1_M_alu_result[7];

--PB1L19 is std_1c20:inst|seven_seg_pio:the_seven_seg_pio|process0~29

--operation mode is normal

PB1L19 = !S1_M_alu_result[2] & !S1_M_alu_result[3] & (!T1_internal_cpu_data_master_waitrequest # !S1_internal_d_write);

--PB1L20 is std_1c20:inst|seven_seg_pio:the_seven_seg_pio|process0~30

--operation mode is normal

PB1L20 = S1_internal_d_write & S1_M_alu_result[4] & PB1L19;

--FB1L10 is std_1c20:inst|led_pio:the_led_pio|process0~1

--operation mode is normal

FB1L10 = S1_M_alu_result[5] & S1_M_mem_byte_en[0] & ZE1L33 & PB1L20;

--S1_M_st_data[6] is std_1c20:inst|cpu:the_cpu|M_st_data[6]

--operation mode is normal

S1_M_st_data[6] = AMPP_FUNCTION(QC2__clk0, S1L1243, F1_data_out, S1_W_stall);

--S1_M_st_data[5] is std_1c20:inst|cpu:the_cpu|M_st_data[5]

--operation mode is normal

S1_M_st_data[5] = AMPP_FUNCTION(QC2__clk0, S1L1241, F1_data_out, S1_W_stall);

--S1_M_st_data[4] is std_1c20:inst|cpu:the_cpu|M_st_data[4]

--operation mode is normal

S1_M_st_data[4] = AMPP_FUNCTION(QC2__clk0, S1L1239, F1_data_out, S1_W_stall);

--S1_M_st_data[3] is std_1c20:inst|cpu:the_cpu|M_st_data[3]

--operation mode is normal

S1_M_st_data[3] = AMPP_FUNCTION(QC2__clk0, S1L1237, F1_data_out, S1_W_stall);

--S1_M_st_data[2] is std_1c20:inst|cpu:the_cpu|M_st_data[2]

--operation mode is normal

S1_M_st_data[2] = AMPP_FUNCTION(QC2__clk0, S1L1235, F1_data_out, S1_W_stall);

--S1_M_st_data[1] is std_1c20:inst|cpu:the_cpu|M_st_data[1]

--operation mode is normal

S1_M_st_data[1] = AMPP_FUNCTION(QC2__clk0, S1L1233, F1_data_out, S1_W_stall);

--S1_M_st_data[0] is std_1c20:inst|cpu:the_cpu|M_st_data[0]

--operation mode is normal

S1_M_st_data[0] = AMPP_FUNCTION(QC2__clk0, S1L1231, F1_data_out, S1_W_stall);

--PB1L21 is std_1c20:inst|seven_seg_pio:the_seven_seg_pio|process0~31

--operation mode is normal

PB1L21 = S1_M_alu_result[5] # !PB1L19 # !S1_M_alu_result[4] # !S1_internal_d_write;

--PB1L18 is std_1c20:inst|seven_seg_pio:the_seven_seg_pio|process0~1

--operation mode is normal

PB1L18 = !PB1L21 & UB1L5 & UB1L6 & UB1L7;

--S1L1233 is std_1c20:inst|cpu:the_cpu|M_st_data[9]~COMBOUT

--operation mode is normal

S1L1233 = AMPP_FUNCTION(S1_E_src2_prelim[1], S1L1285, S1_E_src2_hazard_M);

--S1_M_st_data[9] is std_1c20:inst|cpu:the_cpu|M_st_data[9]

--operation mode is normal

S1_M_st_data[9] = AMPP_FUNCTION(QC2__clk0, S1_E_src2_prelim[1], S1L1285, S1L743, S1_E_src2_hazard_M, F1_data_out, S1L777, S1_W_stall);

--S1L1231 is std_1c20:inst|cpu:the_cpu|M_st_data[8]~COMBOUT

--operation mode is normal

S1L1231 = AMPP_FUNCTION(S1_E_src2_prelim[0], S1L1282, S1_E_src2_hazard_M);

--S1_M_st_data[8] is std_1c20:inst|cpu:the_cpu|M_st_data[8]

--operation mode is normal

S1_M_st_data[8] = AMPP_FUNCTION(QC2__clk0, S1_E_src2_prelim[0], S1L1282, S1L742, S1_E_src2_hazard_M, F1_data_out, S1L777, S1_W_stall);

--KB1L425 is std_1c20:inst|sdram:the_sdram|Mux104~1606

--operation mode is normal

KB1L425 = KB1_m_state[0] & !KB1_m_state[4] & !KB1_m_state[3] & !KB1_m_state[6];

--KB1_i_addr[0] is std_1c20:inst|sdram:the_sdram|i_addr[0]

--operation mode is normal

KB1_i_addr[0]_lut_out = KB1_i_state[0] & KB1_i_state[2] & KB1_i_state[1];

KB1_i_addr[0] = DFFEAS(KB1_i_addr[0]_lut_out, QC2__clk0, F1_data_out, , , , , , );

--KB1L426 is std_1c20:inst|sdram:the_sdram|Mux104~1607

--operation mode is normal

KB1L426 = KB1_init_done & KB1_m_addr[11] # !KB1_init_done & (KB1L348 & (!KB1_i_addr[0]) # !KB1L348 & KB1_m_addr[11]);

--KB1L427 is std_1c20:inst|sdram:the_sdram|Mux104~1608

--operation mode is normal

KB1L427 = KB1_m_addr[11] & (KB1_m_state[4] $ !KB1_m_state[3]);

--KB1L428 is std_1c20:inst|sdram:the_sdram|Mux104~1609

--operation mode is normal

KB1L428 = KB1_m_state[6] & (!KB1_m_state[0]) # !KB1_m_state[6] & (KB1_m_state[0] & (KB1L427) # !KB1_m_state[0] & KB1L426);

--KB1L429 is std_1c20:inst|sdram:the_sdram|Mux104~1610

--operation mode is normal

KB1L429 = KB1_m_state[6] & (KB1_m_addr[11] # KB1L348 & !KB1L428) # !KB1_m_state[6] & (KB1L428);

--KB1L430 is std_1c20:inst|sdram:the_sdram|Mux104~1611

--operation mode is normal

KB1L430 = KB1_m_state[1] & KB1_active_addr[20] & KB1L425 # !KB1_m_state[1] & (KB1L429);

--KB1L431 is std_1c20:inst|sdram:the_sdram|Mux104~1612

--operation mode is normal

KB1L431 = KB1_m_state[1] & (!KB1L425);

--KB1L432 is std_1c20:inst|sdram:the_sdram|Mux104~1613

--operation mode is normal

KB1L432 = KB1_m_state[7] # KB1_m_state[8] # KB1_m_state[5] # KB1_m_state[2];

--KB1L433 is std_1c20:inst|sdram:the_sdram|Mux105~1397

--operation mode is normal

KB1L433 = KB1_init_done & KB1_m_addr[10] # !KB1_init_done & (KB1L348 & (!KB1_i_addr[0]) # !KB1L348 & KB1_m_addr[10]);

--KB1L434 is std_1c20:inst|sdram:the_sdram|Mux105~1398

--operation mode is normal

KB1L434 = KB1_m_addr[10] & (KB1_m_state[4] $ !KB1_m_state[3]);

--KB1L435 is std_1c20:inst|sdram:the_sdram|Mux105~1399

--operation mode is normal

KB1L435 = KB1_m_state[6] & (!KB1_m_state[0]) # !KB1_m_state[6] & (KB1_m_state[0] & (KB1L434) # !KB1_m_state[0] & KB1L433);

--KB1L436 is std_1c20:inst|sdram:the_sdram|Mux105~1400

--operation mode is normal

KB1L436 = KB1_m_state[6] & (KB1_m_addr[10] # KB1L348 & !KB1L435) # !KB1_m_state[6] & (KB1L435);

--KB1L437 is std_1c20:inst|sdram:the_sdram|Mux105~1401

--operation mode is normal

KB1L437 = KB1_m_state[1] & KB1_active_addr[19] & KB1L425 # !KB1_m_state[1] & (KB1L436);

--KB1L438 is std_1c20:inst|sdram:the_sdram|Mux106~1397

--operation mode is normal

KB1L438 = KB1_init_done & KB1_m_addr[9] # !KB1_init_done & (KB1L348 & (!KB1_i_addr[0]) # !KB1L348 & KB1_m_addr[9]);

--KB1L439 is std_1c20:inst|sdram:the_sdram|Mux106~1398

--operation mode is normal

KB1L439 = KB1_m_addr[9] & (KB1_m_state[4] $ !KB1_m_state[3]);

--KB1L440 is std_1c20:inst|sdram:the_sdram|Mux106~1399

--operation mode is normal

KB1L440 = KB1_m_state[6] & (!KB1_m_state[0]) # !KB1_m_state[6] & (KB1_m_state[0] & (KB1L439) # !KB1_m_state[0] & KB1L438);

--KB1L441 is std_1c20:inst|sdram:the_sdram|Mux106~1400

--operation mode is normal

KB1L441 = KB1_m_state[6] & (KB1_m_addr[9] # KB1L348 & !KB1L440) # !KB1_m_state[6] & (KB1L440);

--KB1L442 is std_1c20:inst|sdram:the_sdram|Mux106~1401

--operation mode is normal

KB1L442 = KB1_m_state[1] & KB1_active_addr[18] & KB1L425 # !KB1_m_state[1] & (KB1L441);

--KB1L443 is std_1c20:inst|sdram:the_sdram|Mux107~1397

--operation mode is normal

KB1L443 = KB1_init_done & KB1_m_addr[8] # !KB1_init_done & (KB1L348 & (!KB1_i_addr[0]) # !KB1L348 & KB1_m_addr[8]);

--KB1L444 is std_1c20:inst|sdram:the_sdram|Mux107~1398

--operation mode is normal

KB1L444 = KB1_m_addr[8] & (KB1_m_state[4] $ !KB1_m_state[3]);

--KB1L445 is std_1c20:inst|sdram:the_sdram|Mux107~1399

--operation mode is normal

KB1L445 = KB1_m_state[6] & (!KB1_m_state[0]) # !KB1_m_state[6] & (KB1_m_state[0] & (KB1L444) # !KB1_m_state[0] & KB1L443);

--KB1L446 is std_1c20:inst|sdram:the_sdram|Mux107~1400

--operation mode is normal

KB1L446 = KB1_m_state[6] & (KB1_m_addr[8] # KB1L348 & !KB1L445) # !KB1_m_state[6] & (KB1L445);

--KB1L447 is std_1c20:inst|sdram:the_sdram|Mux107~1401

--operation mode is normal

KB1L447 = KB1_m_state[1] & KB1_active_addr[17] & KB1L425 # !KB1_m_state[1] & (KB1L446);

--KB1L448 is std_1c20:inst|sdram:the_sdram|Mux108~1491

--operation mode is normal

KB1L448 = KB1_m_state[0] & !KB1_m_state[4] & !KB1_m_state[3] & !KB1_m_state[1];

--KB1L449 is std_1c20:inst|sdram:the_sdram|Mux108~1492

--operation mode is normal

KB1L449 = KB1_m_state[4] & KB1_m_addr[7] # !KB1_m_state[4] & (KB1_m_state[3] & KB1_m_addr[7] # !KB1_m_state[3] & (KB1_active_addr[16]));

--KB1L450 is std_1c20:inst|sdram:the_sdram|Mux108~1493

--operation mode is normal

KB1L450 = KB1_init_done & KB1_m_addr[7] # !KB1_init_done & (KB1L348 & (!KB1_i_addr[0]) # !KB1L348 & KB1_m_addr[7]);

--TE1_entry_1[43] is std_1c20:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_1[43]

--operation mode is normal

TE1_entry_1[43]_lut_out = NB1L36;

TE1_entry_1[43] = DFFEAS(TE1_entry_1[43]_lut_out, QC2__clk0, VCC, , TE1L123, , , , );

--TE1_entry_0[43] is std_1c20:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_0[43]

--operation mode is normal

TE1_entry_0[43]_lut_out = NB1L36;

TE1_entry_0[43] = DFFEAS(TE1_entry_0[43]_lut_out, QC2__clk0, VCC, , TE1L62, , , , );

--TE1L172 is std_1c20:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|rd_data[43]~495

--operation mode is normal

TE1L172 = TE1_rd_address & TE1_entry_1[43] # !TE1_rd_address & (TE1_entry_0[43]);

--KB1_active_addr[7] is std_1c20:inst|sdram:the_sdram|active_addr[7]

--operation mode is normal

KB1_active_addr[7]_lut_out = KB1L12 & (KB1L14 & (TE1L172) # !KB1L14 & KB1_active_addr[7]) # !KB1L12 & KB1_active_addr[7];

KB1_active_addr[7] = DFFEAS(KB1_active_addr[7]_lut_out, QC2__clk0, VCC, , , , , , );

--KB1L451 is std_1c20:inst|sdram:the_sdram|Mux108~1494

--operation mode is normal

KB1L451 = KB1L264 & (KB1_f_select & TE1L172 # !KB1_f_select & (KB1_active_addr[7]));

--KB1L452 is std_1c20:inst|sdram:the_sdram|Mux108~1495

--operation mode is normal

KB1L452 = KB1_m_state[1] & (!KB1_m_state[0]) # !KB1_m_state[1] & (KB1_m_state[0] & (KB1L455) # !KB1_m_state[0] & KB1L450);

--KB1L453 is std_1c20:inst|sdram:the_sdram|Mux108~1496

--operation mode is normal

KB1L453 = KB1_m_state[1] & (KB1L452 & (KB1_m_addr[7]) # !KB1L452 & KB1L449) # !KB1_m_state[1] & (KB1L452);

--KB1L454 is std_1c20:inst|sdram:the_sdram|Mux108~1497

--operation mode is normal

KB1L454 = KB1_m_state[6] & KB1L448 # !KB1_m_state[6] & (KB1L453);

--KB1L456 is std_1c20:inst|sdram:the_sdram|Mux109~1364

--operation mode is normal

KB1L456 = KB1L432 & KB1_m_addr[6] # !KB1L432 & KB1_m_state[6] & (KB1_m_addr[6] # KB1L448);

--KB1L457 is std_1c20:inst|sdram:the_sdram|Mux109~1365

--operation mode is normal

KB1L457 = KB1_m_state[4] & KB1_m_addr[6] # !KB1_m_state[4] & (KB1_m_state[3] & KB1_m_addr[6] # !KB1_m_state[3] & (KB1_active_addr[15]));

--KB1L458 is std_1c20:inst|sdram:the_sdram|Mux109~1366

--operation mode is normal

KB1L458 = KB1_init_done & KB1_m_addr[6] # !KB1_init_done & (KB1L348 & (!KB1_i_addr[0]) # !KB1L348 & KB1_m_addr[6]);

--TE1_entry_1[42] is std_1c20:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_1[42]

--operation mode is normal

TE1_entry_1[42]_lut_out = NB1L35;

TE1_entry_1[42] = DFFEAS(TE1_entry_1[42]_lut_out, QC2__clk0, VCC, , TE1L123, , , , );

--TE1_entry_0[42] is std_1c20:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_0[42]

--operation mode is normal

TE1_entry_0[42]_lut_out = NB1L35;

TE1_entry_0[42] = DFFEAS(TE1_entry_0[42]_lut_out, QC2__clk0, VCC, , TE1L62, , , , );

--TE1L171 is std_1c20:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|rd_data[42]~496

--operation mode is normal

TE1L171 = TE1_rd_address & TE1_entry_1[42] # !TE1_rd_address & (TE1_entry_0[42]);

--KB1_active_addr[6] is std_1c20:inst|sdram:the_sdram|active_addr[6]

--operation mode is normal

KB1_active_addr[6]_lut_out = KB1L12 & (KB1L14 & (TE1L171) # !KB1L14 & KB1_active_addr[6]) # !KB1L12 & KB1_active_addr[6];

KB1_active_addr[6] = DFFEAS(KB1_active_addr[6]_lut_out, QC2__clk0, VCC, , , , , , );

--KB1L459 is std_1c20:inst|sdram:the_sdram|Mux109~1367

--operation mode is normal

KB1L459 = KB1L264 & (KB1_f_select & TE1L171 # !KB1_f_select & (KB1_active_addr[6]));

--KB1L460 is std_1c20:inst|sdram:the_sdram|Mux109~1368

--operation mode is normal

KB1L460 = KB1_m_state[1] & (!KB1_m_state[0]) # !KB1_m_state[1] & (KB1_m_state[0] & (KB1L462) # !KB1_m_state[0] & KB1L458);

--KB1L461 is std_1c20:inst|sdram:the_sdram|Mux109~1369

--operation mode is normal

KB1L461 = KB1_m_state[1] & (KB1L460 & (KB1_m_addr[6]) # !KB1L460 & KB1L457) # !KB1_m_state[1] & (KB1L460);

--KB1L463 is std_1c20:inst|sdram:the_sdram|Mux110~1388

--operation mode is normal

KB1L463 = KB1L432 & KB1_m_addr[5] # !KB1L432 & KB1_m_state[6] & (KB1_m_addr[5] # KB1L448);

--KB1L464 is std_1c20:inst|sdram:the_sdram|Mux110~1389

--operation mode is normal

KB1L464 = KB1_m_state[4] & KB1_m_addr[5] # !KB1_m_state[4] & (KB1_m_state[3] & KB1_m_addr[5] # !KB1_m_state[3] & (KB1_active_addr[14]));

--KB1L465 is std_1c20:inst|sdram:the_sdram|Mux110~1390

--operation mode is normal

KB1L465 = KB1_m_addr[5] # !KB1_m_state[4] & !KB1_m_state[3] & !KB1_init_done;

--TE1_entry_1[41] is std_1c20:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_1[41]

--operation mode is normal

TE1_entry_1[41]_lut_out = NB1L34;

TE1_entry_1[41] = DFFEAS(TE1_entry_1[41]_lut_out, QC2__clk0, VCC, , TE1L123, , , , );

--TE1_entry_0[41] is std_1c20:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_0[41]

--operation mode is normal

TE1_entry_0[41]_lut_out = NB1L34;

TE1_entry_0[41] = DFFEAS(TE1_entry_0[41]_lut_out, QC2__clk0, VCC, , TE1L62, , , , );

--TE1L170 is std_1c20:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|rd_data[41]~497

--operation mode is normal

TE1L170 = TE1_rd_address & TE1_entry_1[41] # !TE1_rd_address & (TE1_entry_0[41]);

--KB1_active_addr[5] is std_1c20:inst|sdram:the_sdram|active_addr[5]

--operation mode is normal

KB1_active_addr[5]_lut_out = KB1L12 & (KB1L14 & (TE1L170) # !KB1L14 & KB1_active_addr[5]) # !KB1L12 & KB1_active_addr[5];

KB1_active_addr[5] = DFFEAS(KB1_active_addr[5]_lut_out, QC2__clk0, VCC, , , , , , );

--KB1L466 is std_1c20:inst|sdram:the_sdram|Mux110~1391

--operation mode is normal

KB1L466 = KB1L264 & (KB1_f_select & TE1L170 # !KB1_f_select & (KB1_active_addr[5]));

--KB1L467 is std_1c20:inst|sdram:the_sdram|Mux110~1392

--operation mode is normal

KB1L467 = KB1_m_state[1] & (!KB1_m_state[0]) # !KB1_m_state[1] & (KB1_m_state[0] & (KB1L469) # !KB1_m_state[0] & KB1L465);

--KB1L468 is std_1c20:inst|sdram:the_sdram|Mux110~1393

--operation mode is normal

KB1L468 = KB1_m_state[1] & (KB1L467 & (KB1_m_addr[5]) # !KB1L467 & KB1L464) # !KB1_m_state[1] & (KB1L467);

--KB1L470 is std_1c20:inst|sdram:the_sdram|Mux111~1315

--operation mode is normal

KB1L470 = KB1L432 & KB1_m_addr[4] # !KB1L432 & KB1_m_state[6] & (KB1_m_addr[4] # KB1L448);

--KB1L471 is std_1c20:inst|sdram:the_sdram|Mux111~1316

--operation mode is normal

KB1L471 = KB1_m_state[4] & KB1_m_addr[4] # !KB1_m_state[4] & (KB1_m_state[3] & KB1_m_addr[4] # !KB1_m_state[3] & (KB1_active_addr[13]));

--KB1L472 is std_1c20:inst|sdram:the_sdram|Mux111~1317

--operation mode is normal

KB1L472 = KB1_m_addr[4] # !KB1_m_state[4] & !KB1_m_state[3] & !KB1_init_done;

--TE1_entry_1[40] is std_1c20:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_1[40]

--operation mode is normal

TE1_entry_1[40]_lut_out = NB1L33;

TE1_entry_1[40] = DFFEAS(TE1_entry_1[40]_lut_out, QC2__clk0, VCC, , TE1L123, , , , );

--TE1_entry_0[40] is std_1c20:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_0[40]

--operation mode is normal

TE1_entry_0[40]_lut_out = NB1L33;

TE1_entry_0[40] = DFFEAS(TE1_entry_0[40]_lut_out, QC2__clk0, VCC, , TE1L62, , , , );

--TE1L169 is std_1c20:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|rd_data[40]~498

--operation mode is normal

TE1L169 = TE1_rd_address & TE1_entry_1[40] # !TE1_rd_address & (TE1_entry_0[40]);

--KB1_active_addr[4] is std_1c20:inst|sdram:the_sdram|active_addr[4]

--operation mode is normal

KB1_active_addr[4]_lut_out = KB1L12 & (KB1L14 & (TE1L169) # !KB1L14 & KB1_active_addr[4]) # !KB1L12 & KB1_active_addr[4];

KB1_active_addr[4] = DFFEAS(KB1_active_addr[4]_lut_out, QC2__clk0, VCC, , , , , , );

--KB1L473 is std_1c20:inst|sdram:the_sdram|Mux111~1318

--operation mode is normal

KB1L473 = KB1L264 & (KB1_f_select & TE1L169 # !KB1_f_select & (KB1_active_addr[4]));

--KB1L474 is std_1c20:inst|sdram:the_sdram|Mux111~1319

--operation mode is normal

KB1L474 = KB1_m_state[1] & (!KB1_m_state[0]) # !KB1_m_state[1] & (KB1_m_state[0] & (KB1L476) # !KB1_m_state[0] & KB1L472);

--KB1L475 is std_1c20:inst|sdram:the_sdram|Mux111~1320

--operation mode is normal

KB1L475 = KB1_m_state[1] & (KB1L474 & (KB1_m_addr[4]) # !KB1L474 & KB1L471) # !KB1_m_state[1] & (KB1L474);

--KB1L477 is std_1c20:inst|sdram:the_sdram|Mux112~1347

--operation mode is normal

KB1L477 = KB1L432 & KB1_m_addr[3] # !KB1L432 & KB1_m_state[6] & (KB1_m_addr[3] # KB1L448);

--KB1L478 is std_1c20:inst|sdram:the_sdram|Mux112~1348

--operation mode is normal

KB1L478 = KB1_m_state[4] & KB1_m_addr[3] # !KB1_m_state[4] & (KB1_m_state[3] & KB1_m_addr[3] # !KB1_m_state[3] & (KB1_active_addr[12]));

--KB1L479 is std_1c20:inst|sdram:the_sdram|Mux112~1349

--operation mode is normal

KB1L479 = KB1_init_done & KB1_m_addr[3] # !KB1_init_done & (KB1L348 & (!KB1_i_addr[0]) # !KB1L348 & KB1_m_addr[3]);

--TE1_entry_1[39] is std_1c20:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_1[39]

--operation mode is normal

TE1_entry_1[39]_lut_out = NB1L32;

TE1_entry_1[39] = DFFEAS(TE1_entry_1[39]_lut_out, QC2__clk0, VCC, , TE1L123, , , , );

--TE1_entry_0[39] is std_1c20:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_0[39]

--operation mode is normal

TE1_entry_0[39]_lut_out = NB1L32;

TE1_entry_0[39] = DFFEAS(TE1_entry_0[39]_lut_out, QC2__clk0, VCC, , TE1L62, , , , );

--TE1L168 is std_1c20:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|rd_data[39]~499

--operation mode is normal

TE1L168 = TE1_rd_address & TE1_entry_1[39] # !TE1_rd_address & (TE1_entry_0[39]);

--KB1_active_addr[3] is std_1c20:inst|sdram:the_sdram|active_addr[3]

--operation mode is normal

KB1_active_addr[3]_lut_out = KB1L12 & (KB1L14 & (TE1L168) # !KB1L14 & KB1_active_addr[3]) # !KB1L12 & KB1_active_addr[3];

KB1_active_addr[3] = DFFEAS(KB1_active_addr[3]_lut_out, QC2__clk0, VCC, , , , , , );

--KB1L480 is std_1c20:inst|sdram:the_sdram|Mux112~1350

--operation mode is normal

KB1L480 = KB1L264 & (KB1_f_select & TE1L168 # !KB1_f_select & (KB1_active_addr[3]));

--KB1L481 is std_1c20:inst|sdram:the_sdram|Mux112~1351

--operation mode is normal

KB1L481 = KB1_m_state[1] & (!KB1_m_state[0]) # !KB1_m_state[1] & (KB1_m_state[0] & (KB1L483) # !KB1_m_state[0] & KB1L479);

--KB1L482 is std_1c20:inst|sdram:the_sdram|Mux112~1352

--operation mode is normal

KB1L482 = KB1_m_state[1] & (KB1L481 & (KB1_m_addr[3]) # !KB1L481 & KB1L478) # !KB1_m_state[1] & (KB1L481);

--KB1L484 is std_1c20:inst|sdram:the_sdram|Mux113~1347

--operation mode is normal

KB1L484 = KB1L432 & KB1_m_addr[2] # !KB1L432 & KB1_m_state[6] & (KB1_m_addr[2] # KB1L448);

--KB1L485 is std_1c20:inst|sdram:the_sdram|Mux113~1348

--operation mode is normal

KB1L485 = KB1_m_state[4] & KB1_m_addr[2] # !KB1_m_state[4] & (KB1_m_state[3] & KB1_m_addr[2] # !KB1_m_state[3] & (KB1_active_addr[11]));

--KB1L486 is std_1c20:inst|sdram:the_sdram|Mux113~1349

--operation mode is normal

KB1L486 = KB1_init_done & KB1_m_addr[2] # !KB1_init_done & (KB1L348 & (!KB1_i_addr[0]) # !KB1L348 & KB1_m_addr[2]);

--TE1_entry_1[38] is std_1c20:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_1[38]

--operation mode is normal

TE1_entry_1[38]_lut_out = NB1L31;

TE1_entry_1[38] = DFFEAS(TE1_entry_1[38]_lut_out, QC2__clk0, VCC, , TE1L123, , , , );

--TE1_entry_0[38] is std_1c20:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_0[38]

--operation mode is normal

TE1_entry_0[38]_lut_out = NB1L31;

TE1_entry_0[38] = DFFEAS(TE1_entry_0[38]_lut_out, QC2__clk0, VCC, , TE1L62, , , , );

--TE1L167 is std_1c20:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|rd_data[38]~500

--operation mode is normal

TE1L167 = TE1_rd_address & TE1_entry_1[38] # !TE1_rd_address & (TE1_entry_0[38]);

--KB1_active_addr[2] is std_1c20:inst|sdram:the_sdram|active_addr[2]

--operation mode is normal

KB1_active_addr[2]_lut_out = KB1L12 & (KB1L14 & (TE1L167) # !KB1L14 & KB1_active_addr[2]) # !KB1L12 & KB1_active_addr[2];

KB1_active_addr[2] = DFFEAS(KB1_active_addr[2]_lut_out, QC2__clk0, VCC, , , , , , );

--KB1L487 is std_1c20:inst|sdram:the_sdram|Mux113~1350

--operation mode is normal

KB1L487 = KB1L264 & (KB1_f_select & TE1L167 # !KB1_f_select & (KB1_active_addr[2]));

--KB1L488 is std_1c20:inst|sdram:the_sdram|Mux113~1351

--operation mode is normal

KB1L488 = KB1_m_state[1] & (!KB1_m_state[0]) # !KB1_m_state[1] & (KB1_m_state[0] & (KB1L490) # !KB1_m_state[0] & KB1L486);

--KB1L489 is std_1c20:inst|sdram:the_sdram|Mux113~1352

--operation mode is normal

KB1L489 = KB1_m_state[1] & (KB1L488 & (KB1_m_addr[2]) # !KB1L488 & KB1L485) # !KB1_m_state[1] & (KB1L488);

--KB1L491 is std_1c20:inst|sdram:the_sdram|Mux114~1347

--operation mode is normal

KB1L491 = KB1L432 & KB1_m_addr[1] # !KB1L432 & KB1_m_state[6] & (KB1_m_addr[1] # KB1L448);

--KB1L492 is std_1c20:inst|sdram:the_sdram|Mux114~1348

--operation mode is normal

KB1L492 = KB1_m_state[4] & KB1_m_addr[1] # !KB1_m_state[4] & (KB1_m_state[3] & KB1_m_addr[1] # !KB1_m_state[3] & (KB1_active_addr[10]));

--KB1L493 is std_1c20:inst|sdram:the_sdram|Mux114~1349

--operation mode is normal

KB1L493 = KB1_init_done & KB1_m_addr[1] # !KB1_init_done & (KB1L348 & (!KB1_i_addr[0]) # !KB1L348 & KB1_m_addr[1]);

--TE1_entry_1[37] is std_1c20:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_1[37]

--operation mode is normal

TE1_entry_1[37]_lut_out = NB1L30;

TE1_entry_1[37] = DFFEAS(TE1_entry_1[37]_lut_out, QC2__clk0, VCC, , TE1L123, , , , );

--TE1_entry_0[37] is std_1c20:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_0[37]

--operation mode is normal

TE1_entry_0[37]_lut_out = NB1L30;

TE1_entry_0[37] = DFFEAS(TE1_entry_0[37]_lut_out, QC2__clk0, VCC, , TE1L62, , , , );

--TE1L166 is std_1c20:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|rd_data[37]~501

--operation mode is normal

TE1L166 = TE1_rd_address & TE1_entry_1[37] # !TE1_rd_address & (TE1_entry_0[37]);

--KB1_active_addr[1] is std_1c20:inst|sdram:the_sdram|active_addr[1]

--operation mode is normal

KB1_active_addr[1]_lut_out = KB1L12 & (KB1L14 & (TE1L166) # !KB1L14 & KB1_active_addr[1]) # !KB1L12 & KB1_active_addr[1];

KB1_active_addr[1] = DFFEAS(KB1_active_addr[1]_lut_out, QC2__clk0, VCC, , , , , , );

--KB1L494 is std_1c20:inst|sdram:the_sdram|Mux114~1350

--operation mode is normal

KB1L494 = KB1L264 & (KB1_f_select & TE1L166 # !KB1_f_select & (KB1_active_addr[1]));

--KB1L495 is std_1c20:inst|sdram:the_sdram|Mux114~1351

--operation mode is normal

KB1L495 = KB1_m_state[1] & (!KB1_m_state[0]) # !KB1_m_state[1] & (KB1_m_state[0] & (KB1L497) # !KB1_m_state[0] & KB1L493);

--KB1L496 is std_1c20:inst|sdram:the_sdram|Mux114~1352

--operation mode is normal

KB1L496 = KB1_m_state[1] & (KB1L495 & (KB1_m_addr[1]) # !KB1L495 & KB1L492) # !KB1_m_state[1] & (KB1L495);

--KB1L498 is std_1c20:inst|sdram:the_sdram|Mux115~1347

--operation mode is normal

KB1L498 = KB1L432 & KB1_m_addr[0] # !KB1L432 & KB1_m_state[6] & (KB1_m_addr[0] # KB1L448);

--KB1L499 is std_1c20:inst|sdram:the_sdram|Mux115~1348

--operation mode is normal

KB1L499 = KB1_m_state[4] & KB1_m_addr[0] # !KB1_m_state[4] & (KB1_m_state[3] & KB1_m_addr[0] # !KB1_m_state[3] & (KB1_active_addr[9]));

--KB1L500 is std_1c20:inst|sdram:the_sdram|Mux115~1349

--operation mode is normal

KB1L500 = KB1_init_done & KB1_m_addr[0] # !KB1_init_done & (KB1L348 & (!KB1_i_addr[0]) # !KB1L348 & KB1_m_addr[0]);

--TE1_entry_1[36] is std_1c20:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_1[36]

--operation mode is normal

TE1_entry_1[36]_lut_out = NB1L29;

TE1_entry_1[36] = DFFEAS(TE1_entry_1[36]_lut_out, QC2__clk0, VCC, , TE1L123, , , , );

--TE1_entry_0[36] is std_1c20:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_0[36]

--operation mode is normal

TE1_entry_0[36]_lut_out = NB1L29;

TE1_entry_0[36] = DFFEAS(TE1_entry_0[36]_lut_out, QC2__clk0, VCC, , TE1L62, , , , );

--TE1L165 is std_1c20:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|rd_data[36]~502

--operation mode is normal

TE1L165 = TE1_rd_address & TE1_entry_1[36] # !TE1_rd_address & (TE1_entry_0[36]);

--KB1_active_addr[0] is std_1c20:inst|sdram:the_sdram|active_addr[0]

--operation mode is normal

KB1_active_addr[0]_lut_out = KB1L12 & (KB1L14 & (TE1L165) # !KB1L14 & KB1_active_addr[0]) # !KB1L12 & KB1_active_addr[0];

KB1_active_addr[0] = DFFEAS(KB1_active_addr[0]_lut_out, QC2__clk0, VCC, , , , , , );

--KB1L501 is std_1c20:inst|sdram:the_sdram|Mux115~1350

--operation mode is normal

KB1L501 = KB1L264 & (KB1_f_select & TE1L165 # !KB1_f_select & (KB1_active_addr[0]));

--KB1L502 is std_1c20:inst|sdram:the_sdram|Mux115~1351

--operation mode is normal

KB1L502 = KB1_m_state[1] & (!KB1_m_state[0]) # !KB1_m_state[1] & (KB1_m_state[0] & (KB1L504) # !KB1_m_state[0] & KB1L500);

--KB1L503 is std_1c20:inst|sdram:the_sdram|Mux115~1352

--operation mode is normal

KB1L503 = KB1_m_state[1] & (KB1L502 & (KB1_m_addr[0]) # !KB1L502 & KB1L499) # !KB1_m_state[1] & (KB1L502);

--TE1L174 is std_1c20:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|rd_data[57]~503

--operation mode is normal

TE1L174 = TE1_rd_address & TE1_entry_1[57] # !TE1_rd_address & (TE1_entry_0[57]);

--KB1L505 is std_1c20:inst|sdram:the_sdram|Mux116~1304

--operation mode is normal

KB1L505 = KB1_f_select & (KB1_m_state[1] & KB1_active_addr[21] # !KB1_m_state[1] & (TE1L174)) # !KB1_f_select & KB1_active_addr[21];

--KB1L506 is std_1c20:inst|sdram:the_sdram|Mux116~1305

--operation mode is normal

KB1L506 = KB1_m_state[4] & !KB1_m_state[3] & !KB1_m_state[1] # !KB1_m_state[4] & (KB1_m_state[3] $ KB1_m_state[1]);

--KB1L278 is std_1c20:inst|sdram:the_sdram|Mux24~1464

--operation mode is normal

KB1L278 = KB1_m_state[0] & (!KB1_m_state[7] & !KB1_m_state[2]);

--KB1L310 is std_1c20:inst|sdram:the_sdram|Mux29~1324

--operation mode is normal

KB1L310 = !KB1_m_state[5] & !KB1_m_state[6];

--TE1L173 is std_1c20:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|rd_data[44]~504

--operation mode is normal

TE1L173 = TE1_rd_address & TE1_entry_1[44] # !TE1_rd_address & (TE1_entry_0[44]);

--KB1L507 is std_1c20:inst|sdram:the_sdram|Mux117~1184

--operation mode is normal

KB1L507 = KB1_f_select & (KB1_m_state[1] & KB1_active_addr[8] # !KB1_m_state[1] & (TE1L173)) # !KB1_f_select & KB1_active_addr[8];

--KB1_active_dqm[3] is std_1c20:inst|sdram:the_sdram|active_dqm[3]

--operation mode is normal

KB1_active_dqm[3]_lut_out = KB1L12 & (KB1L14 & (TE1L164) # !KB1L14 & KB1_active_dqm[3]) # !KB1L12 & KB1_active_dqm[3];

KB1_active_dqm[3] = DFFEAS(KB1_active_dqm[3]_lut_out, QC2__clk0, VCC, , , , , , );

--TE1_entry_1[35] is std_1c20:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_1[35]

--operation mode is normal

TE1_entry_1[35]_lut_out = KB1L236;

TE1_entry_1[35] = DFFEAS(TE1_entry_1[35]_lut_out, QC2__clk0, VCC, , TE1L123, , , , );

--TE1_entry_0[35] is std_1c20:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_0[35]

--operation mode is normal

TE1_entry_0[35]_lut_out = KB1L236;

TE1_entry_0[35] = DFFEAS(TE1_entry_0[35]_lut_out, QC2__clk0, VCC, , TE1L62, , , , );

--TE1L164 is std_1c20:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|rd_data[35]~505

--operation mode is normal

TE1L164 = TE1_rd_address & TE1_entry_1[35] # !TE1_rd_address & (TE1_entry_0[35]);

--KB1L543 is std_1c20:inst|sdram:the_sdram|Mux150~1184

--operation mode is normal

KB1L543 = KB1_f_select & (KB1_m_state[1] & KB1_active_dqm[3] # !KB1_m_state[1] & (TE1L164)) # !KB1_f_select & KB1_active_dqm[3];

--KB1_active_dqm[2] is std_1c20:inst|sdram:the_sdram|active_dqm[2]

--operation mode is normal

KB1_active_dqm[2]_lut_out = KB1L12 & (KB1L14 & (TE1L163) # !KB1L14 & KB1_active_dqm[2]) # !KB1L12 & KB1_active_dqm[2];

KB1_active_dqm[2] = DFFEAS(KB1_active_dqm[2]_lut_out, QC2__clk0, VCC, , , , , , );

--TE1_entry_1[34] is std_1c20:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_1[34]

--operation mode is normal

TE1_entry_1[34]_lut_out = KB1L235;

TE1_entry_1[34] = DFFEAS(TE1_entry_1[34]_lut_out, QC2__clk0, VCC, , TE1L123, , , , );

--TE1_entry_0[34] is std_1c20:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_0[34]

--operation mode is normal

TE1_entry_0[34]_lut_out = KB1L235;

TE1_entry_0[34] = DFFEAS(TE1_entry_0[34]_lut_out, QC2__clk0, VCC, , TE1L62, , , , );

--TE1L163 is std_1c20:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|rd_data[34]~506

--operation mode is normal

TE1L163 = TE1_rd_address & TE1_entry_1[34] # !TE1_rd_address & (TE1_entry_0[34]);

--KB1L544 is std_1c20:inst|sdram:the_sdram|Mux151~1184

--operation mode is normal

KB1L544 = KB1_f_select & (KB1_m_state[1] & KB1_active_dqm[2] # !KB1_m_state[1] & (TE1L163)) # !KB1_f_select & KB1_active_dqm[2];

--KB1_active_dqm[1] is std_1c20:inst|sdram:the_sdram|active_dqm[1]

--operation mode is normal

KB1_active_dqm[1]_lut_out = KB1L12 & (KB1L14 & (TE1L162) # !KB1L14 & KB1_active_dqm[1]) # !KB1L12 & KB1_active_dqm[1];

KB1_active_dqm[1] = DFFEAS(KB1_active_dqm[1]_lut_out, QC2__clk0, VCC, , , , , , );

--TE1_entry_1[33] is std_1c20:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_1[33]

--operation mode is normal

TE1_entry_1[33]_lut_out = KB1L234;

TE1_entry_1[33] = DFFEAS(TE1_entry_1[33]_lut_out, QC2__clk0, VCC, , TE1L123, , , , );

--TE1_entry_0[33] is std_1c20:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_0[33]

--operation mode is normal

TE1_entry_0[33]_lut_out = KB1L234;

TE1_entry_0[33] = DFFEAS(TE1_entry_0[33]_lut_out, QC2__clk0, VCC, , TE1L62, , , , );

--TE1L162 is std_1c20:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|rd_data[33]~507

--operation mode is normal

TE1L162 = TE1_rd_address & TE1_entry_1[33] # !TE1_rd_address & (TE1_entry_0[33]);

--KB1L545 is std_1c20:inst|sdram:the_sdram|Mux152~1184

--operation mode is normal

KB1L545 = KB1_f_select & (KB1_m_state[1] & KB1_active_dqm[1] # !KB1_m_state[1] & (TE1L162)) # !KB1_f_select & KB1_active_dqm[1];

--KB1_active_dqm[0] is std_1c20:inst|sdram:the_sdram|active_dqm[0]

--operation mode is normal

KB1_active_dqm[0]_lut_out = KB1L12 & (KB1L14 & (TE1L161) # !KB1L14 & KB1_active_dqm[0]) # !KB1L12 & KB1_active_dqm[0];

KB1_active_dqm[0] = DFFEAS(KB1_active_dqm[0]_lut_out, QC2__clk0, VCC, , , , , , );

--TE1_entry_1[32] is std_1c20:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_1[32]

--operation mode is normal

TE1_entry_1[32]_lut_out = KB1L233;

TE1_entry_1[32] = DFFEAS(TE1_entry_1[32]_lut_out, QC2__clk0, VCC, , TE1L123, , , , );

--TE1_entry_0[32] is std_1c20:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_0[32]

--operation mode is normal

TE1_entry_0[32]_lut_out = KB1L233;

TE1_entry_0[32] = DFFEAS(TE1_entry_0[32]_lut_out, QC2__clk0, VCC, , TE1L62, , , , );

--TE1L161 is std_1c20:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|rd_data[32]~508

--operation mode is normal

TE1L161 = TE1_rd_address & TE1_entry_1[32] # !TE1_rd_address & (TE1_entry_0[32]);

--KB1L546 is std_1c20:inst|sdram:the_sdram|Mux153~1184

--operation mode is normal

KB1L546 = KB1_f_select & (KB1_m_state[1] & KB1_active_dqm[0] # !KB1_m_state[1] & (TE1L161)) # !KB1_f_select & KB1_active_dqm[0];

--C1L14Q is sld_hub:sld_hub_inst|hub_tdo~548

--operation mode is normal

C1L14Q = AMPP_FUNCTION(!A1L5, C1_jtag_debug_mode_usr1, !FF1_state[8]);

--C1L15Q is sld_hub:sld_hub_inst|hub_tdo~549

--operation mode is normal

C1L15Q = AMPP_FUNCTION(!A1L5, C1L20, C1L21, GE1_td_shift[0], BF8_Q[1], !FF1_state[8]);

--C1L13Q is sld_hub:sld_hub_inst|hub_tdo~547

--operation mode is normal

C1L13Q = AMPP_FUNCTION(!A1L5, BF3_Q[0], C1_jtag_debug_mode_usr1, !FF1_state[8]);

--C1L18 is sld_hub:sld_hub_inst|hub_tdo~563

--operation mode is normal

C1L18 = AMPP_FUNCTION(C1L14Q, C1L15Q, C1L13Q);

--C1L16Q is sld_hub:sld_hub_inst|hub_tdo~550

--operation mode is normal

C1L16Q = AMPP_FUNCTION(!A1L5, C1L19, !FF1_state[8]);

--C1L17Q is sld_hub:sld_hub_inst|hub_tdo~551

--operation mode is normal

C1L17Q = AMPP_FUNCTION(!A1L5, FF1L18, !FF1_state[8]);

--C1L12Q is sld_hub:sld_hub_inst|hub_tdo~546

--operation mode is normal

C1L12Q = AMPP_FUNCTION(!A1L5, FF1L18, !FF1_state[8]);

--C1L19 is sld_hub:sld_hub_inst|hub_tdo~564

--operation mode is normal

C1L19 = AMPP_FUNCTION(C1L18, C1L16Q, C1L17Q, C1L12Q);

--S1_ic_fill_ap_cnt[3] is std_1c20:inst|cpu:the_cpu|ic_fill_ap_cnt[3]

--operation mode is normal

S1_ic_fill_ap_cnt[3] = AMPP_FUNCTION(QC2__clk0, S1_internal_i_read, U1L133, U1L131, S1L115, F1_data_out, S1L993);

--U1L179 is std_1c20:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|r_1~13

--operation mode is normal

U1L179 = Y1L21 # Y1L23 # !U1L165;

--U1L180 is std_1c20:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|r_1~15

--operation mode is normal

U1L180 = Y1L25 # Y1L27 # !Y1L289;

--V1_cpu_jtag_debug_module_arb_addend[1] is std_1c20:inst|cpu_jtag_debug_module_arbitrator:the_cpu_jtag_debug_module|cpu_jtag_debug_module_arb_addend[1]

--operation mode is normal

V1_cpu_jtag_debug_module_arb_addend[1]_lut_out = V1L23 # V1L24 # V1L7 & !V1L32;

V1_cpu_jtag_debug_module_arb_addend[1] = DFFEAS(V1_cpu_jtag_debug_module_arb_addend[1]_lut_out, QC2__clk0, F1_data_out, , , , , , );

--V1L36 is std_1c20:inst|cpu_jtag_debug_module_arbitrator:the_cpu_jtag_debug_module|internal_cpu_instruction_master_qualified_request_cpu_jtag_debug_module~44

--operation mode is normal

V1L36 = S1_internal_i_read & (WE1_fifo_contains_ones_n # U1_internal_cpu_instruction_master_latency_counter[0] # U1_internal_cpu_instruction_master_latency_counter[1]);

--X1L10 is std_1c20:inst|epcs_controller_epcs_control_port_arbitrator:the_epcs_controller_epcs_control_port|cpu_instruction_master_requests_epcs_controller_epcs_control_port~65

--operation mode is normal

X1L10 = S1_internal_i_read & !S1_ic_fill_tag[4] & !S1_ic_fill_tag[3] & !S1_ic_fill_tag[2];

--X1L11 is std_1c20:inst|epcs_controller_epcs_control_port_arbitrator:the_epcs_controller_epcs_control_port|cpu_instruction_master_requests_epcs_controller_epcs_control_port~66

--operation mode is normal

X1L11 = !S1_ic_fill_tag[1] & !S1_ic_fill_tag[0] & !S1_ic_fill_line[6];

--X1L12 is std_1c20:inst|epcs_controller_epcs_control_port_arbitrator:the_epcs_controller_epcs_control_port|cpu_instruction_master_requests_epcs_controller_epcs_control_port~67

--operation mode is normal

X1L12 = Y1L134 & Y1L135 & X1L10 & X1L11;

--V1_cpu_jtag_debug_module_arb_addend[0] is std_1c20:inst|cpu_jtag_debug_module_arbitrator:the_cpu_jtag_debug_module|cpu_jtag_debug_module_arb_addend[0]

--operation mode is normal

V1_cpu_jtag_debug_module_arb_addend[0]_lut_out = !V1L20 & !V1L21 & (!V1L7 # !V1L32);

V1_cpu_jtag_debug_module_arb_addend[0] = DFFEAS(V1_cpu_jtag_debug_module_arb_addend[0]_lut_out, QC2__clk0, F1_data_out, , , , , , );

--V1L1 is std_1c20:inst|cpu_jtag_debug_module_arbitrator:the_cpu_jtag_debug_module|Add2~344

--operation mode is normal

V1L1 = !V1_cpu_jtag_debug_module_arb_addend[0] & (V1L36 # !X1L12 # !S1_ic_fill_tag[5]);

--K1L3 is std_1c20:inst|clock_0_in_arbitrator:the_clock_0_in|cpu_data_master_requests_clock_0_in~534

--operation mode is normal

K1L3 = UB1L2 & UB1L3 & UB1L4 & K1L7;

--V1L2 is std_1c20:inst|cpu_jtag_debug_module_arbitrator:the_cpu_jtag_debug_module|Add2~345

--operation mode is normal

V1L2 = V1_cpu_jtag_debug_module_arb_addend[1] & (V1L1 # !K1L3 # !V1L6) # !V1_cpu_jtag_debug_module_arb_addend[1] & V1L1 & (!K1L3 # !V1L6);

--V1_cpu_instruction_master_qualified_request_cpu_jtag_debug_module is std_1c20:inst|cpu_jtag_debug_module_arbitrator:the_cpu_jtag_debug_module|cpu_instruction_master_qualified_request_cpu_jtag_debug_module

--operation mode is normal

V1_cpu_instruction_master_qualified_request_cpu_jtag_debug_module = S1_ic_fill_tag[5] & X1L12 & (!V1L36);

--U1L178 is std_1c20:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|r_0~1

--operation mode is normal

U1L178 = V1L2 # !V1_cpu_jtag_debug_module_arb_addend[0] # !V1_cpu_instruction_master_qualified_request_cpu_jtag_debug_module;

--U1L125 is std_1c20:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_run~165

--operation mode is normal

U1L125 = U1L178 & (Y1L9 # Y1L11 # !Y1L248);

--U1L126 is std_1c20:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_run~166

--operation mode is normal

U1L126 = U1L125 & (Y1_d1_ext_ram_bus_avalon_slave_end_xfer & !Y1L260 # !Y1L248);

--Y1L209 is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|internal_cpu_instruction_master_qualified_request_ext_ram_s1~96

--operation mode is normal

Y1L209 = Y1L208 # Y1_ext_ram_bus_avalon_slave_slavearbiterlockenable & Y1L49;

--Y1_ext_flash_s1_wait_counter[0] is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_flash_s1_wait_counter[0]

--operation mode is normal

Y1_ext_flash_s1_wait_counter[0]_lut_out = !Y1L138 & !Y1_ext_flash_s1_wait_counter[0] & !Y1L141;

Y1_ext_flash_s1_wait_counter[0] = DFFEAS(Y1_ext_flash_s1_wait_counter[0]_lut_out, QC2__clk0, F1_data_out, , , , , , );

--Y1L137 is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|Equal10~114

--operation mode is normal

Y1L137 = !Y1_ext_flash_s1_wait_counter[3] & !Y1_ext_flash_s1_wait_counter[2] & !Y1_ext_flash_s1_wait_counter[1] & !Y1_ext_flash_s1_wait_counter[0];

--U1L182 is std_1c20:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|r_1~293

--operation mode is normal

U1L182 = Y1_d1_ext_ram_bus_avalon_slave_end_xfer & U1_internal_cpu_instruction_master_dbs_address[1] & U1_internal_cpu_instruction_master_dbs_address[0] & Y1L137;

--U1L127 is std_1c20:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_run~167

--operation mode is normal

U1L127 = Y1L97 & U1L182 & (!Y1L209) # !Y1L97 & (!Y1L209 # !Y1L288);

--X1_epcs_controller_epcs_control_port_arb_addend[1] is std_1c20:inst|epcs_controller_epcs_control_port_arbitrator:the_epcs_controller_epcs_control_port|epcs_controller_epcs_control_port_arb_addend[1]

--operation mode is normal

X1_epcs_controller_epcs_control_port_arb_addend[1]_lut_out = X1L2 & X1L25 # !X1L2 & (X1L6 & X1L25 # !X1L6 & (X1_epcs_controller_epcs_control_port_arb_addend[1]));

X1_epcs_controller_epcs_control_port_arb_addend[1] = DFFEAS(X1_epcs_controller_epcs_control_port_arb_addend[1]_lut_out, QC2__clk0, F1_data_out, , , , , , );

--X1L4 is std_1c20:inst|epcs_controller_epcs_control_port_arbitrator:the_epcs_controller_epcs_control_port|cpu_data_master_requests_epcs_controller_epcs_control_port~349

--operation mode is normal

X1L4 = S1_M_alu_result[20] & (!S1_M_alu_result[23]);

--X1_cpu_data_master_requests_epcs_controller_epcs_control_port is std_1c20:inst|epcs_controller_epcs_control_port_arbitrator:the_epcs_controller_epcs_control_port|cpu_data_master_requests_epcs_controller_epcs_control_port

--operation mode is normal

X1_cpu_data_master_requests_epcs_controller_epcs_control_port = S1_M_alu_result[25] & X1L4 & K1L3 & !S1_M_alu_result[17];

--X1_cpu_instruction_master_qualified_request_epcs_controller_epcs_control_port is std_1c20:inst|epcs_controller_epcs_control_port_arbitrator:the_epcs_controller_epcs_control_port|cpu_instruction_master_qualified_request_epcs_controller_epcs_control_port

--operation mode is normal

X1_cpu_instruction_master_qualified_request_epcs_controller_epcs_control_port = X1L12 & (!S1_ic_fill_tag[5] & !V1L36);

--X1_epcs_controller_epcs_control_port_arb_addend[0] is std_1c20:inst|epcs_controller_epcs_control_port_arbitrator:the_epcs_controller_epcs_control_port|epcs_controller_epcs_control_port_arb_addend[0]

--operation mode is normal

X1_epcs_controller_epcs_control_port_arb_addend[0]_lut_out = X1L2 & !X1L23 # !X1L2 & (X1L6 & !X1L23 # !X1L6 & (X1_epcs_controller_epcs_control_port_arb_addend[0]));

X1_epcs_controller_epcs_control_port_arb_addend[0] = DFFEAS(X1_epcs_controller_epcs_control_port_arb_addend[0]_lut_out, QC2__clk0, F1_data_out, , , , , , );

--X1_cpu_instruction_master_granted_epcs_controller_epcs_control_port is std_1c20:inst|epcs_controller_epcs_control_port_arbitrator:the_epcs_controller_epcs_control_port|cpu_instruction_master_granted_epcs_controller_epcs_control_port

--operation mode is normal

X1_cpu_instruction_master_granted_epcs_controller_epcs_control_port = X1_cpu_instruction_master_qualified_request_epcs_controller_epcs_control_port & (X1_epcs_controller_epcs_control_port_arb_addend[1] & !X1_cpu_data_master_requests_epcs_controller_epcs_control_port # !X1_epcs_controller_epcs_control_port_arb_addend[0]) # !X1_cpu_instruction_master_qualified_request_epcs_controller_epcs_control_port & (X1_epcs_controller_epcs_control_port_arb_addend[0] # !X1_epcs_controller_epcs_control_port_arb_addend[1] & X1_cpu_data_master_requests_epcs_controller_epcs_control_port);

--X1_d1_reasons_to_wait is std_1c20:inst|epcs_controller_epcs_control_port_arbitrator:the_epcs_controller_epcs_control_port|d1_reasons_to_wait

--operation mode is normal

X1_d1_reasons_to_wait_lut_out = X1L27;

X1_d1_reasons_to_wait = DFFEAS(X1_d1_reasons_to_wait_lut_out, QC2__clk0, F1_data_out, , , , , , );

--NB1_sdram_s1_arb_addend[1] is std_1c20:inst|sdram_s1_arbitrator:the_sdram_s1|sdram_s1_arb_addend[1]

--operation mode is normal

NB1_sdram_s1_arb_addend[1]_lut_out = NB1_WideOr1 & NB1L55 # !NB1_WideOr1 & (NB1_sdram_s1_arb_addend[1]);

NB1_sdram_s1_arb_addend[1] = DFFEAS(NB1_sdram_s1_arb_addend[1]_lut_out, QC2__clk0, F1_data_out, , , , , , );

--VE1_fifo_contains_ones_n is std_1c20:inst|sdram_s1_arbitrator:the_sdram_s1|rdv_fifo_for_cpu_data_master_to_sdram_s1_module:rdv_fifo_for_cpu_data_master_to_sdram_s1|fifo_contains_ones_n

--operation mode is normal

VE1_fifo_contains_ones_n_lut_out = VE1L2 # VE1L3 # VE1L4 # VE1L6;

VE1_fifo_contains_ones_n = DFFEAS(VE1_fifo_contains_ones_n_lut_out, QC2__clk0, F1_data_out, , WE1L27, , , , );

--NB1L15 is std_1c20:inst|sdram_s1_arbitrator:the_sdram_s1|cpu_data_master_qualified_request_sdram_s1~114

--operation mode is normal

NB1L15 = T1_internal_cpu_data_master_waitrequest & !S1_internal_d_write & (!S1_internal_d_read) # !T1_internal_cpu_data_master_waitrequest & (!S1_internal_d_read # !VE1_fifo_contains_ones_n);

--NB1_sdram_s1_slavearbiterlockenable is std_1c20:inst|sdram_s1_arbitrator:the_sdram_s1|sdram_s1_slavearbiterlockenable

--operation mode is normal

NB1_sdram_s1_slavearbiterlockenable_lut_out = NB1L28 & (NB1L74 & NB1_sdram_s1_slavearbiterlockenable # !NB1L74 & (NB1L81)) # !NB1L28 & NB1_sdram_s1_slavearbiterlockenable;

NB1_sdram_s1_slavearbiterlockenable = DFFEAS(NB1_sdram_s1_slavearbiterlockenable_lut_out, QC2__clk0, F1_data_out, , , , , , );

--NB1_last_cycle_cpu_instruction_master_granted_slave_sdram_s1 is std_1c20:inst|sdram_s1_arbitrator:the_sdram_s1|last_cycle_cpu_instruction_master_granted_slave_sdram_s1

--operation mode is normal

NB1_last_cycle_cpu_instruction_master_granted_slave_sdram_s1_lut_out = NB1L21 & (NB1L71 # NB1_last_cycle_cpu_instruction_master_granted_slave_sdram_s1 & !NB1L73);

NB1_last_cycle_cpu_instruction_master_granted_slave_sdram_s1 = DFFEAS(NB1_last_cycle_cpu_instruction_master_granted_slave_sdram_s1_lut_out, QC2__clk0, F1_data_out, , , , , , );

--NB1L69 is std_1c20:inst|sdram_s1_arbitrator:the_sdram_s1|sdram_s1_arb_share_counter_next_value[5]~576

--operation mode is normal

NB1L69 = S1_internal_i_read & S1_ic_fill_tag[12] & NB1_last_cycle_cpu_instruction_master_granted_slave_sdram_s1 & !S1_ic_fill_tag[13];

--NB1L16 is std_1c20:inst|sdram_s1_arbitrator:the_sdram_s1|cpu_data_master_qualified_request_sdram_s1~115

--operation mode is normal

NB1L16 = NB1L17 & NB1L15 & (!NB1L69 # !NB1_sdram_s1_slavearbiterlockenable);

--NB1L21 is std_1c20:inst|sdram_s1_arbitrator:the_sdram_s1|cpu_instruction_master_requests_sdram_s1~41

--operation mode is normal

NB1L21 = S1_internal_i_read & S1_ic_fill_tag[12] & (!S1_ic_fill_tag[13]);

--NB1_last_cycle_cpu_data_master_granted_slave_sdram_s1 is std_1c20:inst|sdram_s1_arbitrator:the_sdram_s1|last_cycle_cpu_data_master_granted_slave_sdram_s1

--operation mode is normal

NB1_last_cycle_cpu_data_master_granted_slave_sdram_s1_lut_out = NB1L17 & (NB1L1 # NB1_last_cycle_cpu_data_master_granted_slave_sdram_s1 & !NB1L73);

NB1_last_cycle_cpu_data_master_granted_slave_sdram_s1 = DFFEAS(NB1_last_cycle_cpu_data_master_granted_slave_sdram_s1_lut_out, QC2__clk0, F1_data_out, , , , , , );

--NB1L13 is std_1c20:inst|sdram_s1_arbitrator:the_sdram_s1|cpu_data_master_arbiterlock~23

--operation mode is normal

NB1L13 = S1_M_alu_result[24] & QB1L1 & NB1_last_cycle_cpu_data_master_granted_slave_sdram_s1 & !S1_M_alu_result[25];

--NB1L23 is std_1c20:inst|sdram_s1_arbitrator:the_sdram_s1|internal_cpu_instruction_master_qualified_request_sdram_s1~59

--operation mode is normal

NB1L23 = S1_internal_i_read & (U1_internal_cpu_instruction_master_latency_counter[0] # U1_internal_cpu_instruction_master_latency_counter[1]);

--NB1L19 is std_1c20:inst|sdram_s1_arbitrator:the_sdram_s1|cpu_instruction_master_qualified_request_sdram_s1~58

--operation mode is normal

NB1L19 = NB1L21 & !NB1L23 & (!NB1L13 # !NB1_sdram_s1_slavearbiterlockenable);

--NB1_sdram_s1_arb_addend[0] is std_1c20:inst|sdram_s1_arbitrator:the_sdram_s1|sdram_s1_arb_addend[0]

--operation mode is normal

NB1_sdram_s1_arb_addend[0]_lut_out = NB1_WideOr1 & !NB1L53 # !NB1_WideOr1 & (NB1_sdram_s1_arb_addend[0]);

NB1_sdram_s1_arb_addend[0] = DFFEAS(NB1_sdram_s1_arb_addend[0]_lut_out, QC2__clk0, F1_data_out, , , , , , );

--U1L183 is std_1c20:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|r_2~1

--operation mode is normal

U1L183 = NB1_sdram_s1_arb_addend[1] & !NB1L16 # !NB1_sdram_s1_arb_addend[0] # !NB1L19;

--V1_d1_reasons_to_wait is std_1c20:inst|cpu_jtag_debug_module_arbitrator:the_cpu_jtag_debug_module|d1_reasons_to_wait

--operation mode is normal

V1_d1_reasons_to_wait_lut_out = V1L32;

V1_d1_reasons_to_wait = DFFEAS(V1_d1_reasons_to_wait_lut_out, QC2__clk0, F1_data_out, , , , , , );

--U1L128 is std_1c20:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_run~168

--operation mode is normal

U1L128 = !V1L36 & (V1_d1_reasons_to_wait # !S1_ic_fill_tag[5]) # !X1L12;

--NB1L24 is std_1c20:inst|sdram_s1_arbitrator:the_sdram_s1|internal_cpu_instruction_master_qualified_request_sdram_s1~60

--operation mode is normal

NB1L24 = NB1L23 # NB1_sdram_s1_slavearbiterlockenable & NB1L13;

--TE1L126 is std_1c20:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|Equal0~93

--operation mode is normal

TE1L126 = TE1_entries[1] & (!TE1_entries[0]);

--U1L129 is std_1c20:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_run~169

--operation mode is normal

U1L129 = U1L183 & U1L128 & U1L134;

--U1L130 is std_1c20:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_run~170

--operation mode is normal

U1L130 = U1L129 & (X1_cpu_instruction_master_granted_epcs_controller_epcs_control_port & X1_d1_reasons_to_wait # !X1_cpu_instruction_master_qualified_request_epcs_controller_epcs_control_port);

--U1L131 is std_1c20:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_run~171

--operation mode is normal

U1L131 = U1L127 & U1L130 & (!Y1L247 # !Y1L209);

--U1L132 is std_1c20:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_run~172

--operation mode is normal

U1L132 = U1L179 & U1L180 & U1L126 & U1L131;

--S1_D_kill is std_1c20:inst|cpu:the_cpu|D_kill

--operation mode is normal

S1_D_kill = AMPP_FUNCTION(QC2__clk0, S1_F_kill, F1_data_out, S1_W_stall);

--S1_D_inst_ram_hit is std_1c20:inst|cpu:the_cpu|D_inst_ram_hit

--operation mode is normal

S1_D_inst_ram_hit = AMPP_FUNCTION(QC2__clk0, S1L814, S1L815, S1L816, S1L818, F1_data_out, S1_W_stall);

--S1_ic_fill_prevent_refill is std_1c20:inst|cpu:the_cpu|ic_fill_prevent_refill

--operation mode is normal

S1_ic_fill_prevent_refill = AMPP_FUNCTION(QC2__clk0, S1_ic_fill_prevent_refill, S1L248, S1L249, S1L1006, F1_data_out);

--S1_D_ic_fill_same_tag_line is std_1c20:inst|cpu:the_cpu|D_ic_fill_same_tag_line

--operation mode is normal

S1_D_ic_fill_same_tag_line = AMPP_FUNCTION(QC2__clk0, S1L801, S1L806, S1L807, S1L809, F1_data_out, S1_W_stall);

--S1L248 is std_1c20:inst|cpu:the_cpu|D_ic_fill_starting~75

--operation mode is normal

S1L248 = AMPP_FUNCTION(S1_D_kill, S1_D_inst_ram_hit, S1_ic_fill_prevent_refill, S1_D_ic_fill_same_tag_line);

--S1_ic_fill_active is std_1c20:inst|cpu:the_cpu|ic_fill_active

--operation mode is normal

S1_ic_fill_active = AMPP_FUNCTION(QC2__clk0, S1_i_readdatavalid_d1, S1_ic_fill_active, S1_D_ic_fill_starting, S1L971, F1_data_out);

--S1L249 is std_1c20:inst|cpu:the_cpu|D_ic_fill_starting~76

--operation mode is normal

S1L249 = AMPP_FUNCTION(S1_ic_fill_active, S1_M_pipe_flush);

--S1_D_pc[18] is std_1c20:inst|cpu:the_cpu|D_pc[18]

--operation mode is normal

S1_D_pc[18] = AMPP_FUNCTION(QC2__clk0, S1_F_pc[18], F1_data_out, S1_W_stall);

--S1_D_pc[23] is std_1c20:inst|cpu:the_cpu|D_pc[23]

--operation mode is normal

S1_D_pc[23] = AMPP_FUNCTION(QC2__clk0, S1_F_pc[23], F1_data_out, S1_W_stall);

--S1_D_pc[19] is std_1c20:inst|cpu:the_cpu|D_pc[19]

--operation mode is normal

S1_D_pc[19] = AMPP_FUNCTION(QC2__clk0, S1_F_pc[19], F1_data_out, S1_W_stall);

--S1_D_pc[20] is std_1c20:inst|cpu:the_cpu|D_pc[20]

--operation mode is normal

S1_D_pc[20] = AMPP_FUNCTION(QC2__clk0, S1_F_pc[20], F1_data_out, S1_W_stall);

--S1_D_pc[21] is std_1c20:inst|cpu:the_cpu|D_pc[21]

--operation mode is normal

S1_D_pc[21] = AMPP_FUNCTION(QC2__clk0, S1_F_pc[21], F1_data_out, S1_W_stall);

--S1_D_pc[22] is std_1c20:inst|cpu:the_cpu|D_pc[22]

--operation mode is normal

S1_D_pc[22] = AMPP_FUNCTION(QC2__clk0, S1_F_pc[22], F1_data_out, S1_W_stall);

--S1_D_pc[16] is std_1c20:inst|cpu:the_cpu|D_pc[16]

--operation mode is normal

S1_D_pc[16] = AMPP_FUNCTION(QC2__clk0, S1_F_pc[16], F1_data_out, S1_W_stall);

--S1_D_pc[17] is std_1c20:inst|cpu:the_cpu|D_pc[17]

--operation mode is normal

S1_D_pc[17] = AMPP_FUNCTION(QC2__clk0, S1_F_pc[17], F1_data_out, S1_W_stall);

--S1_D_pc[14] is std_1c20:inst|cpu:the_cpu|D_pc[14]

--operation mode is normal

S1_D_pc[14] = AMPP_FUNCTION(QC2__clk0, S1_F_pc[14], F1_data_out, S1_W_stall);

--S1_D_pc[15] is std_1c20:inst|cpu:the_cpu|D_pc[15]

--operation mode is normal

S1_D_pc[15] = AMPP_FUNCTION(QC2__clk0, S1_F_pc[15], F1_data_out, S1_W_stall);

--Y1_ext_ram_bus_avalon_slave_arb_share_counter[1] is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_avalon_slave_arb_share_counter[1]

--operation mode is normal

Y1_ext_ram_bus_avalon_slave_arb_share_counter[1]_lut_out = Y1L190 # !Y1L198 & (Y1L50 # Y1L82);

Y1_ext_ram_bus_avalon_slave_arb_share_counter[1] = DFFEAS(Y1_ext_ram_bus_avalon_slave_arb_share_counter[1]_lut_out, QC2__clk0, F1_data_out, , Y1L185, , , , );

--Y1L198 is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_avalon_slave_firsttransfer~139

--operation mode is normal

Y1L198 = Y1_ext_ram_bus_avalon_slave_slavearbiterlockenable & (Y1L49 # Y1L81);

--Y1L207 is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_avalon_slave_slavearbiterlockenable~192

--operation mode is normal

Y1L207 = Y1L198 & Y1_ext_ram_bus_avalon_slave_arb_share_counter[1] # !Y1L198 & (!Y1L281);

--Y1L291 is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|process4~73

--operation mode is normal

Y1L291 = S1_M_alu_result[25] & (S1_M_alu_result[20] # !Y1L76) # !Y1L74;

--Y1L292 is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|process4~74

--operation mode is normal

Y1L292 = S1_ic_fill_tag[13] & (S1_ic_fill_tag[8] # !Y1L287) # !Y1L96;

--Y1L293 is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|process4~75

--operation mode is normal

Y1L293 = Y1L291 & Y1L292 & !Y1L78 & !Y1L247;

--Y1L294 is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|process4~76

--operation mode is normal

Y1L294 = Y1L293 # !Y1L194;

--Y1L95 is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|cpu_instruction_master_read_data_valid_lan91c111_s1_shift_register_in~15

--operation mode is normal

Y1L95 = !Y1L260 & (Y1_d1_ext_ram_bus_avalon_slave_end_xfer # Y1L194);

--Y1L195 is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_avalon_slave_end_xfer~79

--operation mode is normal

Y1L195 = !Y1L95 & (Y1L84 # QB1L1 & Y1L52);

--Y1L88 is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|cpu_instruction_master_read_data_valid_ext_flash_s1_shift_register_in~16

--operation mode is normal

Y1L88 = Y1L137 & (Y1_d1_ext_ram_bus_avalon_slave_end_xfer # Y1L194);

--Y1L196 is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_avalon_slave_end_xfer~80

--operation mode is normal

Y1L196 = Y1L195 # !Y1L88 & (Y1L139 # Y1_ext_flash_s1_in_a_read_cycle);

--Y1_cpu_data_master_requests_ext_ram_s1 is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|cpu_data_master_requests_ext_ram_s1

--operation mode is normal

Y1_cpu_data_master_requests_ext_ram_s1 = Y1L74 & Y1L76 & (!S1_M_alu_result[20]);

--Y1L3 is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|A_WE_StdLogicVector~4279

--operation mode is normal

Y1L3 = Y1_last_cycle_cpu_data_master_granted_slave_ext_ram_s1 & (Y1_d1_ext_ram_bus_avalon_slave_end_xfer # Y1L194 # Y1L198);

--Y1_ext_ram_bus_avalon_slave_saved_chosen_master_vector[5] is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_avalon_slave_saved_chosen_master_vector[5]

--operation mode is normal

Y1_ext_ram_bus_avalon_slave_saved_chosen_master_vector[5]_lut_out = Y1L51;

Y1_ext_ram_bus_avalon_slave_saved_chosen_master_vector[5] = DFFEAS(Y1_ext_ram_bus_avalon_slave_saved_chosen_master_vector[5]_lut_out, QC2__clk0, F1_data_out, , Y1L191, , , , );

--Y1L300 is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|WideOr6~30

--operation mode is normal

Y1L300 = !Y1L52 & !Y1L50 & !Y1L51;

--U1L5 is std_1c20:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_read_but_no_slave_selected~55

--operation mode is normal

U1L5 = !Y1L84 & !Y1L82 & !Y1L83;

--Y1L191 is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_avalon_slave_arb_winner~0

--operation mode is normal

Y1L191 = !Y1L198 & (!U1L5 # !Y1L300);

--Y1L4 is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|A_WE_StdLogicVector~4280

--operation mode is normal

Y1L4 = Y1L3 # Y1L191 & Y1L51 # !Y1L191 & (Y1_ext_ram_bus_avalon_slave_saved_chosen_master_vector[5]);

--Y1L182 is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_avalon_slave_arb_addend[4]~COMBOUT

--operation mode is normal

Y1L182 = Y1L191 & (Y1L50) # !Y1L191 & Y1_ext_ram_bus_avalon_slave_saved_chosen_master_vector[3];

--Y1_ext_ram_bus_avalon_slave_arb_addend[4] is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_avalon_slave_arb_addend[4]

--operation mode is normal

Y1_ext_ram_bus_avalon_slave_arb_addend[4] = DFFEAS(Y1L182, QC2__clk0, F1_data_out, , Y1_WideOr6, Y1L83, , , Y1L196);

--Y1_ext_ram_bus_avalon_slave_arbitration_holdoff_internal is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_avalon_slave_arbitration_holdoff_internal

--operation mode is normal

Y1_ext_ram_bus_avalon_slave_arbitration_holdoff_internal = !Y1_d1_ext_ram_bus_avalon_slave_end_xfer & !Y1L194 & !Y1L198;

--Y1L178 is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_avalon_slave_arb_addend[2]~COMBOUT

--operation mode is normal

Y1L178 = Y1L191 & (Y1L52) # !Y1L191 & Y1_ext_ram_bus_avalon_slave_saved_chosen_master_vector[1];

--Y1_ext_ram_bus_avalon_slave_arb_addend[2] is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_avalon_slave_arb_addend[2]

--operation mode is normal

Y1_ext_ram_bus_avalon_slave_arb_addend[2] = DFFEAS(Y1L178, QC2__clk0, F1_data_out, , Y1_WideOr6, Y1L82, , , Y1L196);

--WE1_how_many_ones[3] is std_1c20:inst|sdram_s1_arbitrator:the_sdram_s1|rdv_fifo_for_cpu_instruction_master_to_sdram_s1_module:rdv_fifo_for_cpu_instruction_master_to_sdram_s1|how_many_ones[3]

--operation mode is normal

WE1_how_many_ones[3]_lut_out = WE1L2;

WE1_how_many_ones[3] = DFFEAS(WE1_how_many_ones[3]_lut_out, QC2__clk0, F1_data_out, , WE1L27, , , , );

--NB1L18 is std_1c20:inst|sdram_s1_arbitrator:the_sdram_s1|cpu_instruction_master_granted_sdram_s1~85

--operation mode is normal

NB1L18 = NB1L19 & (NB1_sdram_s1_arb_addend[1] & !NB1L16 # !NB1_sdram_s1_arb_addend[0]);

--WE1_how_many_ones[2] is std_1c20:inst|sdram_s1_arbitrator:the_sdram_s1|rdv_fifo_for_cpu_instruction_master_to_sdram_s1_module:rdv_fifo_for_cpu_instruction_master_to_sdram_s1|how_many_ones[2]

--operation mode is normal

WE1_how_many_ones[2]_lut_out = WE1L3;

WE1_how_many_ones[2] = DFFEAS(WE1_how_many_ones[2]_lut_out, QC2__clk0, F1_data_out, , WE1L27, , , , );

--WE1_how_many_ones[1] is std_1c20:inst|sdram_s1_arbitrator:the_sdram_s1|rdv_fifo_for_cpu_instruction_master_to_sdram_s1_module:rdv_fifo_for_cpu_instruction_master_to_sdram_s1|how_many_ones[1]

--operation mode is normal

WE1_how_many_ones[1]_lut_out = WE1L4;

WE1_how_many_ones[1] = DFFEAS(WE1_how_many_ones[1]_lut_out, QC2__clk0, F1_data_out, , WE1L27, , , , );

--WE1_how_many_ones[0] is std_1c20:inst|sdram_s1_arbitrator:the_sdram_s1|rdv_fifo_for_cpu_instruction_master_to_sdram_s1_module:rdv_fifo_for_cpu_instruction_master_to_sdram_s1|how_many_ones[0]

--operation mode is normal

WE1_how_many_ones[0]_lut_out = WE1L6;

WE1_how_many_ones[0] = DFFEAS(WE1_how_many_ones[0]_lut_out, QC2__clk0, F1_data_out, , WE1L27, , , , );

--KB1_za_valid is std_1c20:inst|sdram:the_sdram|za_valid

--operation mode is normal

KB1_za_valid_lut_out = KB1_rd_valid[2];

KB1_za_valid = DFFEAS(KB1_za_valid_lut_out, QC2__clk0, F1_data_out, , , , , , );

--WE1_stage_0 is std_1c20:inst|sdram_s1_arbitrator:the_sdram_s1|rdv_fifo_for_cpu_instruction_master_to_sdram_s1_module:rdv_fifo_for_cpu_instruction_master_to_sdram_s1|stage_0

--operation mode is normal

WE1_stage_0_lut_out = WE1_full_1 & WE1_stage_1 # !WE1_full_1 & (NB1L18);

WE1_stage_0 = DFFEAS(WE1_stage_0_lut_out, QC2__clk0, VCC, , WE1L26, , , , );

--WE1L35 is std_1c20:inst|sdram_s1_arbitrator:the_sdram_s1|rdv_fifo_for_cpu_instruction_master_to_sdram_s1_module:rdv_fifo_for_cpu_instruction_master_to_sdram_s1|updated_one_count~70

--operation mode is normal

WE1L35 = KB1_za_valid & WE1_stage_0;

--WE1L1 is std_1c20:inst|sdram_s1_arbitrator:the_sdram_s1|rdv_fifo_for_cpu_instruction_master_to_sdram_s1_module:rdv_fifo_for_cpu_instruction_master_to_sdram_s1|A_WE_StdLogicVector~1213

--operation mode is normal

WE1L1 = WE1_how_many_ones[2] & WE1_how_many_ones[1] & WE1_how_many_ones[0] & !WE1L35 # !WE1_how_many_ones[2] & !WE1_how_many_ones[1] & !WE1_how_many_ones[0] & WE1L35;

--WE1L2 is std_1c20:inst|sdram_s1_arbitrator:the_sdram_s1|rdv_fifo_for_cpu_instruction_master_to_sdram_s1_module:rdv_fifo_for_cpu_instruction_master_to_sdram_s1|A_WE_StdLogicVector~1214

--operation mode is normal

WE1L2 = WE1_how_many_ones[3] $ (WE1L1 & (WE1L36 $ !WE1_how_many_ones[2]));

--WE1L3 is std_1c20:inst|sdram_s1_arbitrator:the_sdram_s1|rdv_fifo_for_cpu_instruction_master_to_sdram_s1_module:rdv_fifo_for_cpu_instruction_master_to_sdram_s1|A_WE_StdLogicVector~1215

--operation mode is normal

WE1L3 = WE1_how_many_ones[2] $ (WE1L5 & (WE1L36 $ !WE1_how_many_ones[1]));

--WE1L4 is std_1c20:inst|sdram_s1_arbitrator:the_sdram_s1|rdv_fifo_for_cpu_instruction_master_to_sdram_s1_module:rdv_fifo_for_cpu_instruction_master_to_sdram_s1|A_WE_StdLogicVector~1216

--operation mode is normal

WE1L4 = WE1_how_many_ones[1] $ (WE1L35 & !WE1L36 & !WE1_how_many_ones[0] # !WE1L35 & WE1L36 & WE1_how_many_ones[0]);

--NB1L14 is std_1c20:inst|sdram_s1_arbitrator:the_sdram_s1|cpu_data_master_granted_sdram_s1~36

--operation mode is normal

NB1L14 = NB1L16 & (NB1_sdram_s1_arb_addend[1] # !NB1L19 & !NB1_sdram_s1_arb_addend[0]);

--NB1L27 is std_1c20:inst|sdram_s1_arbitrator:the_sdram_s1|module_input5~34

--operation mode is normal

NB1L27 = !TE1L126 & (NB1L18 # S1_internal_d_read & NB1L14);

--WE1L27 is std_1c20:inst|sdram_s1_arbitrator:the_sdram_s1|rdv_fifo_for_cpu_instruction_master_to_sdram_s1_module:rdv_fifo_for_cpu_instruction_master_to_sdram_s1|process15~0

--operation mode is normal

WE1L27 = KB1_za_valid # NB1L27;

--U1L170 is std_1c20:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|p1_cpu_instruction_master_latency_counter[0]~149

--operation mode is normal

U1L170 = U1_internal_cpu_instruction_master_latency_counter[1] & (!U1_internal_cpu_instruction_master_latency_counter[0]);

--U1L181 is std_1c20:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|r_1~20

--operation mode is normal

U1L181 = Y1_d1_ext_ram_bus_avalon_slave_end_xfer & !Y1L260 # !Y1L248;

--U1L133 is std_1c20:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_run~173

--operation mode is normal

U1L133 = U1L179 & U1L180 & U1L181 & U1L125;

--U1L171 is std_1c20:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|p1_cpu_instruction_master_latency_counter[1]~151

--operation mode is normal

U1L171 = !S1_ic_fill_tag[8] & !S1_ic_fill_tag[9] & !S1_ic_fill_tag[10];

--U1L172 is std_1c20:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|p1_cpu_instruction_master_latency_counter[1]~152

--operation mode is normal

U1L172 = !S1_ic_fill_tag[11] & !S1_ic_fill_tag[12] & (U1L171 # !S1_ic_fill_tag[13]);

--U1L173 is std_1c20:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|p1_cpu_instruction_master_latency_counter[1]~153

--operation mode is normal

U1L173 = U1L172 # Y1L134 & Y1L135 & Y1L136;

--U1L174 is std_1c20:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|p1_cpu_instruction_master_latency_counter[1]~154

--operation mode is normal

U1L174 = U1_internal_cpu_instruction_master_latency_counter[0] & U1_internal_cpu_instruction_master_latency_counter[1];

--Y1L173Q is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_avalon_slave_arb_addend[0]~663

--operation mode is normal

Y1L173Q_lut_out = !Y1L195 & (Y1L88 # !Y1L7) # !Y1L84;

Y1L173Q = DFFEAS(Y1L173Q_lut_out, QC2__clk0, F1_data_out, , Y1_WideOr6, , , , );

--Y1L174Q is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_avalon_slave_arb_addend[0]~664

--operation mode is normal

Y1L174Q_lut_out = Y1L184 # Y1L196 # !Y1L8;

Y1L174Q = DFFEAS(Y1L174Q_lut_out, QC2__clk0, F1_data_out, , Y1_WideOr6, , , , );

--Y1L5 is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|A_WE_StdLogicVector~4283

--operation mode is normal

Y1L5 = !Y1L174Q # !Y1L173Q;

--Y1L184 is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_avalon_slave_arb_addend[5]~COMBOUT

--operation mode is normal

Y1L184 = Y1L191 & (Y1L83) # !Y1L191 & Y1_ext_ram_bus_avalon_slave_saved_chosen_master_vector[4];

--Y1_ext_ram_bus_avalon_slave_arb_addend[5] is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_avalon_slave_arb_addend[5]

--operation mode is normal

Y1_ext_ram_bus_avalon_slave_arb_addend[5] = DFFEAS(Y1L184, QC2__clk0, F1_data_out, , Y1_WideOr6, Y1L51, , , Y1L196);

--Y1L180 is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_avalon_slave_arb_addend[3]~COMBOUT

--operation mode is normal

Y1L180 = Y1L191 & (Y1L82) # !Y1L191 & Y1_ext_ram_bus_avalon_slave_saved_chosen_master_vector[2];

--Y1_ext_ram_bus_avalon_slave_arb_addend[3] is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_avalon_slave_arb_addend[3]

--operation mode is normal

Y1_ext_ram_bus_avalon_slave_arb_addend[3] = DFFEAS(Y1L180, QC2__clk0, F1_data_out, , Y1_WideOr6, Y1L50, , , Y1L196);

--Y1L176 is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_avalon_slave_arb_addend[1]~COMBOUT

--operation mode is normal

Y1L176 = Y1L191 & (Y1L84) # !Y1L191 & Y1_ext_ram_bus_avalon_slave_saved_chosen_master_vector[0];

--Y1_ext_ram_bus_avalon_slave_arb_addend[1] is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_avalon_slave_arb_addend[1]

--operation mode is normal

Y1_ext_ram_bus_avalon_slave_arb_addend[1] = DFFEAS(Y1L176, QC2__clk0, F1_data_out, , Y1_WideOr6, Y1L52, , , Y1L196);

--T1L291 is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|pre_dbs_count_enable~74

--operation mode is normal

T1L291 = Y1_cpu_data_master_requests_ext_flash_s1 & !T1_internal_cpu_data_master_no_byte_enables_and_last_term & !Y1L45 & !Y1L46;

--U1L166 is std_1c20:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|internal_cpu_instruction_master_dbs_address[1]~50

--operation mode is normal

U1L166 = Y1_d1_ext_ram_bus_avalon_slave_end_xfer & Y1L137;

--T1L292 is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|pre_dbs_count_enable~75

--operation mode is normal

T1L292 = Y1L55 & U1L166 & (Y1L17 # Y1L19);

--T1L293 is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|pre_dbs_count_enable~76

--operation mode is normal

T1L293 = Y1_cpu_data_master_read_data_valid_ext_flash_s1_shift_register[1] # S1_internal_d_write & (T1L291 # T1L292);

--T1L2 is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|A_WE_StdLogicVector~1428

--operation mode is normal

T1L2 = TE1L126 # !NB1_sdram_s1_arb_addend[1] & (NB1L19 # NB1_sdram_s1_arb_addend[0]);

--T1L3 is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|A_WE_StdLogicVector~1429

--operation mode is normal

T1L3 = NB1L16 & (S1_internal_d_read # T1L2) # !NB1L16 & S1_internal_d_read & !T1L1;

--X1L1 is std_1c20:inst|epcs_controller_epcs_control_port_arbitrator:the_epcs_controller_epcs_control_port|Add2~344

--operation mode is normal

X1L1 = X1_cpu_data_master_requests_epcs_controller_epcs_control_port & !X1_epcs_controller_epcs_control_port_arb_addend[1] & (X1_cpu_instruction_master_qualified_request_epcs_controller_epcs_control_port # X1_epcs_controller_epcs_control_port_arb_addend[0]);

--T1L4 is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|A_WE_StdLogicVector~1430

--operation mode is normal

T1L4 = X1L1 # Y1L59 & !Y1L29 & !Y1L31;

--V1_cpu_data_master_requests_cpu_jtag_debug_module is std_1c20:inst|cpu_jtag_debug_module_arbitrator:the_cpu_jtag_debug_module|cpu_data_master_requests_cpu_jtag_debug_module

--operation mode is normal

V1_cpu_data_master_requests_cpu_jtag_debug_module = V1L6 & K1L3;

--V1L3 is std_1c20:inst|cpu_jtag_debug_module_arbitrator:the_cpu_jtag_debug_module|Add2~346

--operation mode is normal

V1L3 = V1_cpu_data_master_requests_cpu_jtag_debug_module & !V1_cpu_jtag_debug_module_arb_addend[1] & (V1_cpu_instruction_master_qualified_request_cpu_jtag_debug_module # V1_cpu_jtag_debug_module_arb_addend[0]);

--T1L297 is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|r_1~238

--operation mode is normal

T1L297 = T1_internal_cpu_data_master_dbs_address[1] & T1_internal_cpu_data_master_dbs_address[0];

--T1L298 is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|r_1~239

--operation mode is normal

T1L298 = T1L297 & (Y1_cpu_data_master_read_data_valid_ext_flash_s1_shift_register[0] # S1_internal_d_write & !S1_M_mem_byte_en[3]);

--T1L5 is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|A_WE_StdLogicVector~1431

--operation mode is normal

T1L5 = V1L3 # Y1_cpu_data_master_requests_ext_flash_s1 & !Y1L55 & !T1L298;

--Y1L138 is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|Equal10~115

--operation mode is normal

Y1L138 = !Y1_ext_flash_s1_wait_counter[3] & !Y1_ext_flash_s1_wait_counter[2] & !Y1_ext_flash_s1_wait_counter[1];

--T1L299 is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|r_1~240

--operation mode is normal

T1L299 = Y1L138 & Y1_ext_flash_s1_wait_counter[0] & T1L297 # !S1_internal_d_write;

--T1L6 is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|A_WE_StdLogicVector~1432

--operation mode is normal

T1L6 = Y1L55 & (!Y1L17 & !Y1L19 # !T1L299);

--EB1L14 is std_1c20:inst|lcd_display_control_slave_arbitrator:the_lcd_display_control_slave|Equal1~75

--operation mode is normal

EB1L14 = EB1_lcd_display_control_slave_wait_counter[0] & EB1L29 & EB1L23 & !EB1_lcd_display_control_slave_wait_counter[3];

--T1L300 is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|r_2~102

--operation mode is normal

T1L300 = S1_internal_d_read & JB1L3 & !S1_M_alu_result[5] & !EB1L14;

--Y1L261 is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|LessThan1~91

--operation mode is normal

Y1L261 = !Y1_lan91c111_s1_wait_counter[3] & !Y1_lan91c111_s1_wait_counter[2] & !Y1_lan91c111_s1_wait_counter[1];

--T1L7 is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|A_WE_StdLogicVector~1433

--operation mode is normal

T1L7 = S1_internal_d_write & (!Y1L261 # !Y1_lan91c111_s1_wait_counter[0]);

--T1L8 is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|A_WE_StdLogicVector~1434

--operation mode is normal

T1L8 = Y1L61 & (T1L7 # !Y1L13 & !Y1L15);

--Y1L62 is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|cpu_data_master_qualified_request_lan91c111_s1~129

--operation mode is normal

Y1L62 = Y1L78 & (!Y1_cpu_data_master_read_data_valid_lan91c111_s1_shift_register[0]);

--T1L9 is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|A_WE_StdLogicVector~1435

--operation mode is normal

T1L9 = EB1L18 & (Y1L62 & !Y1L61 # !EB1L14) # !EB1L18 & Y1L62 & (!Y1L61);

--UB1L8 is std_1c20:inst|sysid_control_slave_arbitrator:the_sysid_control_slave|cpu_data_master_granted_sysid_control_slave~156

--operation mode is normal

UB1L8 = !S1_M_alu_result[9] & !S1_M_alu_result[8];

--K1L4 is std_1c20:inst|clock_0_in_arbitrator:the_clock_0_in|cpu_data_master_requests_clock_0_in~535

--operation mode is normal

K1L4 = S1_M_alu_result[23] & !S1_M_alu_result[25] & !S1_M_alu_result[20] & !S1_M_alu_result[7];

--K1L5 is std_1c20:inst|clock_0_in_arbitrator:the_clock_0_in|cpu_data_master_requests_clock_0_in~536

--operation mode is normal

K1L5 = UB1L8 & K1L4 & !S1_M_alu_result[10] & !S1_M_alu_result[6];

--K1L6 is std_1c20:inst|clock_0_in_arbitrator:the_clock_0_in|cpu_data_master_requests_clock_0_in~537

--operation mode is normal

K1L6 = K1L3 & K1L5 & (!S1_M_alu_result[17]);

--NC1_slave_state[0] is std_1c20:inst|clock_1:the_clock_1|clock_1_slave_FSM:slave_FSM|slave_state[0]

--operation mode is normal

NC1_slave_state[0]_lut_out = !NC1L8 & (NC1_slave_state[2] # !NC1L9 & NC1L10);

NC1_slave_state[0] = DFFEAS(NC1_slave_state[0]_lut_out, QC2__clk0, F1_data_out, , , , , , );

--MC2_data_in_d1 is std_1c20:inst|clock_1:the_clock_1|clock_1_edge_to_pulse:write_done_edge_to_pulse|data_in_d1

--operation mode is normal

MC2_data_in_d1_lut_out = GC1_data_out;

MC2_data_in_d1 = DFFEAS(MC2_data_in_d1_lut_out, QC2__clk0, F1_data_out, , , , , , );

--GC1_data_out is std_1c20:inst|clock_1:the_clock_1|clock_1_master_write_done_sync_module:clock_1_master_write_done_sync|data_out

--operation mode is normal

GC1_data_out_lut_out = GC1_data_in_d1;

GC1_data_out = DFFEAS(GC1_data_out_lut_out, QC2__clk0, F1_data_out, , , , , , );

--NC1_slave_state[1] is std_1c20:inst|clock_1:the_clock_1|clock_1_slave_FSM:slave_FSM|slave_state[1]

--operation mode is normal

NC1_slave_state[1]_lut_out = !NC1L6 & (NC1_slave_state[1] & (NC1_slave_state[0]) # !NC1_slave_state[1] & N1L1 & !NC1_slave_state[0]);

NC1_slave_state[1] = DFFEAS(NC1_slave_state[1]_lut_out, QC2__clk0, F1_data_out, , , , , , );

--T1L10 is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|A_WE_StdLogicVector~1436

--operation mode is normal

T1L10 = NC1_slave_state[0] & !NC1_slave_state[1] & (MC2_data_in_d1 $ !GC1_data_out);

--NC1_slave_state[2] is std_1c20:inst|clock_1:the_clock_1|clock_1_slave_FSM:slave_FSM|slave_state[2]

--operation mode is normal

NC1_slave_state[2]_lut_out = !NC1_slave_state[1] & !NC1L5 & (NC1_slave_state[2] # NC1L4);

NC1_slave_state[2] = DFFEAS(NC1_slave_state[2]_lut_out, QC2__clk0, F1_data_out, , , , , , );

--NC1L10 is std_1c20:inst|clock_1:the_clock_1|clock_1_slave_FSM:slave_FSM|Mux3~68

--operation mode is normal

NC1L10 = NC1_slave_state[1] $ !NC1_slave_state[0];

--MC1_data_in_d1 is std_1c20:inst|clock_1:the_clock_1|clock_1_edge_to_pulse:read_done_edge_to_pulse|data_in_d1

--operation mode is normal

MC1_data_in_d1_lut_out = FC1_data_out;

MC1_data_in_d1 = DFFEAS(MC1_data_in_d1_lut_out, QC2__clk0, F1_data_out, , , , , , );

--FC1_data_out is std_1c20:inst|clock_1:the_clock_1|clock_1_master_read_done_sync_module:clock_1_master_read_done_sync|data_out

--operation mode is normal

FC1_data_out_lut_out = FC1_data_in_d1;

FC1_data_out = DFFEAS(FC1_data_out_lut_out, QC2__clk0, F1_data_out, , , , , , );

--NC1L7 is std_1c20:inst|clock_1:the_clock_1|clock_1_slave_FSM:slave_FSM|Mux2~232

--operation mode is normal

NC1L7 = NC1_slave_state[1] & (MC1_data_in_d1 $ FC1_data_out);

--T1L11 is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|A_WE_StdLogicVector~1437

--operation mode is normal

T1L11 = NC1_slave_state[2] & T1L10 # !NC1_slave_state[2] & (NC1L10 & !NC1L7);

--EC1_slave_state[0] is std_1c20:inst|clock_0:the_clock_0|clock_0_slave_FSM:slave_FSM|slave_state[0]

--operation mode is normal

EC1_slave_state[0]_lut_out = !EC1L8 & (EC1_slave_state[2] # !EC1L9 & EC1L10);

EC1_slave_state[0] = DFFEAS(EC1_slave_state[0]_lut_out, QC2__clk0, F1_data_out, , , , , , );

--DC2_data_in_d1 is std_1c20:inst|clock_0:the_clock_0|clock_0_edge_to_pulse:write_done_edge_to_pulse|data_in_d1

--operation mode is normal

DC2_data_in_d1_lut_out = YB1_data_out;

DC2_data_in_d1 = DFFEAS(DC2_data_in_d1_lut_out, QC2__clk0, F1_data_out, , , , , , );

--YB1_data_out is std_1c20:inst|clock_0:the_clock_0|clock_0_master_write_done_sync_module:clock_0_master_write_done_sync|data_out

--operation mode is normal

YB1_data_out_lut_out = YB1_data_in_d1;

YB1_data_out = DFFEAS(YB1_data_out_lut_out, QC2__clk0, F1_data_out, , , , , , );

--EC1_slave_state[1] is std_1c20:inst|clock_0:the_clock_0|clock_0_slave_FSM:slave_FSM|slave_state[1]

--operation mode is normal

EC1_slave_state[1]_lut_out = !EC1L6 & (EC1_slave_state[1] & (EC1_slave_state[0]) # !EC1_slave_state[1] & K1L1 & !EC1_slave_state[0]);

EC1_slave_state[1] = DFFEAS(EC1_slave_state[1]_lut_out, QC2__clk0, F1_data_out, , , , , , );

--T1L12 is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|A_WE_StdLogicVector~1438

--operation mode is normal

T1L12 = EC1_slave_state[0] & !EC1_slave_state[1] & (DC2_data_in_d1 $ !YB1_data_out);

--EC1_slave_state[2] is std_1c20:inst|clock_0:the_clock_0|clock_0_slave_FSM:slave_FSM|slave_state[2]

--operation mode is normal

EC1_slave_state[2]_lut_out = !EC1_slave_state[1] & !EC1L5 & (EC1_slave_state[2] # EC1L4);

EC1_slave_state[2] = DFFEAS(EC1_slave_state[2]_lut_out, QC2__clk0, F1_data_out, , , , , , );

--EC1L10 is std_1c20:inst|clock_0:the_clock_0|clock_0_slave_FSM:slave_FSM|Mux3~68

--operation mode is normal

EC1L10 = EC1_slave_state[1] $ !EC1_slave_state[0];

--DC1_data_in_d1 is std_1c20:inst|clock_0:the_clock_0|clock_0_edge_to_pulse:read_done_edge_to_pulse|data_in_d1

--operation mode is normal

DC1_data_in_d1_lut_out = XB1_data_out;

DC1_data_in_d1 = DFFEAS(DC1_data_in_d1_lut_out, QC2__clk0, F1_data_out, , , , , , );

--XB1_data_out is std_1c20:inst|clock_0:the_clock_0|clock_0_master_read_done_sync_module:clock_0_master_read_done_sync|data_out

--operation mode is normal

XB1_data_out_lut_out = XB1_data_in_d1;

XB1_data_out = DFFEAS(XB1_data_out_lut_out, QC2__clk0, F1_data_out, , , , , , );

--EC1L7 is std_1c20:inst|clock_0:the_clock_0|clock_0_slave_FSM:slave_FSM|Mux2~232

--operation mode is normal

EC1L7 = EC1_slave_state[1] & (DC1_data_in_d1 $ XB1_data_out);

--T1L13 is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|A_WE_StdLogicVector~1439

--operation mode is normal

T1L13 = EC1_slave_state[2] & T1L12 # !EC1_slave_state[2] & (EC1L10 & !EC1L7);

--T1L14 is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|A_WE_StdLogicVector~1440

--operation mode is normal

T1L14 = K1L6 & (S1_M_alu_result[5] & T1L11 # !S1_M_alu_result[5] & (T1L13));

--T1L15 is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|A_WE_StdLogicVector~1441

--operation mode is normal

T1L15 = T1L14 # Y1_cpu_data_master_requests_ext_ram_s1 & !Y1_cpu_data_master_read_data_valid_ext_ram_s1_shift_register[0] & !Y1L59;

--UB1L9 is std_1c20:inst|sysid_control_slave_arbitrator:the_sysid_control_slave|cpu_data_master_granted_sysid_control_slave~157

--operation mode is normal

UB1L9 = S1_M_alu_result[5] & UB1L5 & UB1L6 & UB1L7;

--CB1L2 is std_1c20:inst|jtag_uart_avalon_jtag_slave_arbitrator:the_jtag_uart_avalon_jtag_slave|cpu_data_master_requests_jtag_uart_avalon_jtag_slave~554

--operation mode is normal

CB1L2 = S1_M_alu_result[4] & !S1_M_alu_result[3] & (S1_internal_d_write # S1_internal_d_read);

--BB1_internal_av_waitrequest is std_1c20:inst|jtag_uart:the_jtag_uart|internal_av_waitrequest

--operation mode is normal

BB1_internal_av_waitrequest_lut_out = BB1L55;

BB1_internal_av_waitrequest = DFFEAS(BB1_internal_av_waitrequest_lut_out, QC2__clk0, F1_data_out, , , , , , );

--BB1L54 is std_1c20:inst|jtag_uart:the_jtag_uart|process2~46

--operation mode is normal

BB1L54 = !BB1_internal_av_waitrequest & (!S1_internal_d_write & !S1_internal_d_read # !T1_internal_cpu_data_master_waitrequest);

--BB1L55 is std_1c20:inst|jtag_uart:the_jtag_uart|process2~47

--operation mode is normal

BB1L55 = UB1L9 & CB1L2 & BB1L54;

--T1L16 is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|A_WE_StdLogicVector~1442

--operation mode is normal

T1L16 = T1_internal_cpu_data_master_waitrequest # !S1_internal_d_write & !S1_internal_d_read;

--VE1_stage_0 is std_1c20:inst|sdram_s1_arbitrator:the_sdram_s1|rdv_fifo_for_cpu_data_master_to_sdram_s1_module:rdv_fifo_for_cpu_data_master_to_sdram_s1|stage_0

--operation mode is normal

VE1_stage_0_lut_out = WE1_full_1 & VE1_stage_1 # !WE1_full_1 & (NB1L14);

VE1_stage_0 = DFFEAS(VE1_stage_0_lut_out, QC2__clk0, VCC, , WE1L26, , , , );

--T1L17 is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|A_WE_StdLogicVector~1443

--operation mode is normal

T1L17 = !VE1_stage_0 # !KB1_za_valid # !VE1_fifo_contains_ones_n;

--T1L18 is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|A_WE_StdLogicVector~1444

--operation mode is normal

T1L18 = T1L16 # NB1L17 & T1L17 & !NB1L16;

--T1L19 is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|A_WE_StdLogicVector~1445

--operation mode is normal

T1L19 = T1L9 # T1L15 # BB1L55 # T1L18;

--T1L20 is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|A_WE_StdLogicVector~1446

--operation mode is normal

T1L20 = T1L6 # T1L300 # T1L8 # T1L19;

--F1_data_in_d1 is std_1c20:inst|std_1c20_reset_sysclk2_domain_synch_module:std_1c20_reset_sysclk2_domain_synch|data_in_d1

--operation mode is normal

F1_data_in_d1_lut_out = VCC;

F1_data_in_d1 = DFFEAS(F1_data_in_d1_lut_out, QC2__clk0, !B1L1, , , , , , );

--JD1_resetrequest is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_debug:the_cpu_nios2_oci_debug|resetrequest

--operation mode is normal

JD1_resetrequest = AMPP_FUNCTION(QC2__clk0, SD1_internal_jdo1[22], !C1_CLR_SIGNAL, SD1L191);

--LB1_count_done is std_1c20:inst|sdram_pll:the_sdram_pll|count_done

--operation mode is normal

LB1_count_done_lut_out = LB1_count_done # LB1_countup[4] & LB1_countup[5] & LB1L31;

LB1_count_done = DFFEAS(LB1_count_done_lut_out, PLD_CLKFB, LB1_not_areset, , , , , , );

--Q1_count_done is std_1c20:inst|connector_pll:the_connector_pll|count_done

--operation mode is normal

Q1_count_done_lut_out = Q1_count_done # Q1_countup[4] & Q1_countup[5] & Q1L31;

Q1_count_done = DFFEAS(Q1_count_done_lut_out, PLD_CLOCKINPUT[1], Q1_not_areset, , , , , , );

--B1L1 is std_1c20:inst|reset_n_sources~23

--operation mode is normal

B1L1 = JD1_resetrequest # !PLD_CLEAR_N # !Q1_count_done # !LB1_count_done;

--Y1L141 is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_flash_s1_counter_load_value[3]~167

--operation mode is normal

Y1L141 = Y1_ext_ram_bus_avalon_slave_begins_xfer & (Y1L139 # Y1L66 # Y1L82);

--Y1L34 is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|Add4~126

--operation mode is normal

Y1L34 = Y1_ext_flash_s1_wait_counter[1] # Y1_ext_flash_s1_wait_counter[0];

--Y1L140 is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_flash_s1_counter_load_value[1]~170

--operation mode is normal

Y1L140 = Y1_ext_flash_s1_wait_counter[1] & Y1_ext_flash_s1_wait_counter[0] # !Y1_ext_flash_s1_wait_counter[1] & !Y1_ext_flash_s1_wait_counter[0] & (Y1_ext_flash_s1_wait_counter[3] # Y1_ext_flash_s1_wait_counter[2]);

--Y1L6 is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|A_WE_StdLogicVector~4287

--operation mode is normal

Y1L6 = Y1_ext_ram_bus_avalon_slave_begins_xfer & (Y1L84 # S1_internal_d_read & Y1L52);

--Y1L32 is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|Add3~133

--operation mode is normal

Y1L32 = Y1_lan91c111_s1_wait_counter[3] & (Y1_lan91c111_s1_wait_counter[0] # Y1_lan91c111_s1_wait_counter[2] # Y1_lan91c111_s1_wait_counter[1]);

--Y1L197 is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_avalon_slave_end_xfer~81

--operation mode is normal

Y1L197 = QB1L1 & Y1L61 & (Y1L13 # Y1L15);

--Y1L245 is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|lan91c111_s1_counter_load_value[3]~113

--operation mode is normal

Y1L245 = Y1_ext_ram_bus_avalon_slave_begins_xfer & (Y1L84 # QB1L1 & Y1L52);

--Y1L33 is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|Add3~134

--operation mode is normal

Y1L33 = !Y1_lan91c111_s1_wait_counter[0] & !Y1_lan91c111_s1_wait_counter[1];

--KB1L279 is std_1c20:inst|sdram:the_sdram|Mux24~1465

--operation mode is normal

KB1L279 = KB1_m_state[6] & (KB1_m_state[4] # !KB1L278 # !KB1L246);

--KB1L176 is std_1c20:inst|sdram:the_sdram|m_count~775

--operation mode is normal

KB1L176 = KB1_init_done & KB1_refresh_request;

--KB1L280 is std_1c20:inst|sdram:the_sdram|Mux24~1466

--operation mode is normal

KB1L280 = KB1L348 & KB1L424 & KB1L176 & !KB1_m_state[0];

--KB1L281 is std_1c20:inst|sdram:the_sdram|Mux24~1467

--operation mode is normal

KB1L281 = KB1_m_state[0] & !KB1_m_state[4] & !KB1_m_state[3] & !KB1_m_state[8];

--KB1L282 is std_1c20:inst|sdram:the_sdram|Mux24~1468

--operation mode is normal

KB1L282 = KB1_m_state[5] & (!KB1_m_state[2]) # !KB1_m_state[5] & KB1_m_next[1] & KB1_m_state[2];

--KB1_m_count[2] is std_1c20:inst|sdram:the_sdram|m_count[2]

--operation mode is normal

KB1_m_count[2]_lut_out = KB1_m_state[8] & KB1_m_count[2] & (KB1L351 # KB1L363) # !KB1_m_state[8] & (KB1L363);

KB1_m_count[2] = DFFEAS(KB1_m_count[2]_lut_out, QC2__clk0, F1_data_out, , !KB1_m_state[6], , , , );

--KB1_m_count[1] is std_1c20:inst|sdram:the_sdram|m_count[1]

--operation mode is normal

KB1_m_count[1]_lut_out = KB1_m_state[4] & KB1_m_count[1] & (KB1L366 # KB1L376) # !KB1_m_state[4] & (KB1L376);

KB1_m_count[1] = DFFEAS(KB1_m_count[1]_lut_out, QC2__clk0, F1_data_out, , !KB1_m_state[6], , , , );

--KB1L149 is std_1c20:inst|sdram:the_sdram|LessThan1~56

--operation mode is normal

KB1L149 = KB1_m_count[2] # KB1_m_count[1];

--KB1L508 is std_1c20:inst|sdram:the_sdram|Mux118~1217

--operation mode is normal

KB1L508 = KB1_m_state[0] & !KB1_m_state[7] & !KB1_m_state[8] & !KB1_m_state[2];

--KB1L311 is std_1c20:inst|sdram:the_sdram|Mux29~1325

--operation mode is normal

KB1L311 = KB1_m_state[1] & (!KB1L310 # !KB1L508 # !KB1L348);

--KB1L312 is std_1c20:inst|sdram:the_sdram|Mux29~1326

--operation mode is normal

KB1L312 = !KB1_m_state[7] & !KB1_m_state[5] & !KB1_m_state[6];

--KB1L272 is std_1c20:inst|sdram:the_sdram|Mux22~1322

--operation mode is normal

KB1L272 = KB1_m_state[2] & (!KB1_m_count[2] & !KB1_m_count[1]);

--KB1L285 is std_1c20:inst|sdram:the_sdram|Mux25~1260

--operation mode is normal

KB1L285 = KB1_m_next[1] & KB1L272 & KB1L281;

--KB1L391 is std_1c20:inst|sdram:the_sdram|Mux44~1259

--operation mode is normal

KB1L391 = !KB1_m_state[4] & !KB1_m_state[3] & (TE1_entries[0] # TE1_entries[1]);

--KB1L313 is std_1c20:inst|sdram:the_sdram|Mux29~1327

--operation mode is normal

KB1L313 = !KB1_m_state[0] & !KB1_m_state[8] & !KB1_m_state[2];

--KB1L314 is std_1c20:inst|sdram:the_sdram|Mux29~1328

--operation mode is normal

KB1L314 = KB1_init_done & KB1L391 & KB1L313 & !KB1_refresh_request;

--KB1L547 is std_1c20:inst|sdram:the_sdram|Mux154~548

--operation mode is normal

KB1L547 = !KB1_m_state[7] & !KB1_m_state[5] & !KB1_m_state[6] & !KB1_m_state[1];

--KB1L574 is std_1c20:inst|sdram:the_sdram|refresh_request~105

--operation mode is normal

KB1L574 = !TE1_entries[0] & !TE1_entries[1] & !KB1_refresh_request;

--KB1L273 is std_1c20:inst|sdram:the_sdram|Mux22~1323

--operation mode is normal

KB1L273 = KB1L264 & !KB1_m_state[2] & (KB1L554 # !TE1L127);

--KB1L274 is std_1c20:inst|sdram:the_sdram|Mux22~1324

--operation mode is normal

KB1L274 = KB1_m_state[8] & KB1L348 # !KB1_m_state[8] & (KB1L273 # KB1L348 & KB1L276);

--KB1L286 is std_1c20:inst|sdram:the_sdram|Mux25~1261

--operation mode is normal

KB1L286 = KB1_m_state[8] # KB1_m_state[6] # KB1_m_count[2] # KB1_m_count[1];

--KB1L379 is std_1c20:inst|sdram:the_sdram|Mux42~1480

--operation mode is normal

KB1L379 = KB1_m_state[0] & (!KB1_m_state[4] & !KB1_m_state[3]);

--KB1L349 is std_1c20:inst|sdram:the_sdram|Mux40~1466

--operation mode is normal

KB1L349 = !KB1_m_state[7] & !KB1_m_state[2] & !KB1_m_state[1];

--KB1L287 is std_1c20:inst|sdram:the_sdram|Mux25~1262

--operation mode is normal

KB1L287 = KB1_m_state[5] & (KB1L286 # !KB1L349 # !KB1L379);

--KB1L423 is std_1c20:inst|sdram:the_sdram|Mux59~1280

--operation mode is normal

KB1L423 = KB1L391 & (!KB1_refresh_request);

--KB1L288 is std_1c20:inst|sdram:the_sdram|Mux25~1263

--operation mode is normal

KB1L288 = KB1L554 & KB1_m_state[8] & KB1L256 & KB1L423;

--KB1L300 is std_1c20:inst|sdram:the_sdram|Mux28~1626

--operation mode is normal

KB1L300 = KB1_m_state[2] & (KB1_m_state[8] # KB1L309 # !KB1L547);

--KB1L301 is std_1c20:inst|sdram:the_sdram|Mux28~1627

--operation mode is normal

KB1L301 = KB1_m_state[0] & (!KB1_m_state[5] & !KB1_m_state[2]);

--KB1L302 is std_1c20:inst|sdram:the_sdram|Mux28~1628

--operation mode is normal

KB1L302 = KB1_refresh_request & (!KB1_m_state[6] & !KB1_m_state[1]);

--KB1L303 is std_1c20:inst|sdram:the_sdram|Mux28~1629

--operation mode is normal

KB1L303 = KB1_m_state[8] & !KB1_m_state[4] & !KB1_m_state[3] & !KB1_m_state[7];

--KB1L304 is std_1c20:inst|sdram:the_sdram|Mux28~1630

--operation mode is normal

KB1L304 = KB1L264 & TE1L127 & !KB1L554 & !KB1_m_state[8];

--KB1L305 is std_1c20:inst|sdram:the_sdram|Mux28~1631

--operation mode is normal

KB1L305 = KB1L302 & (KB1L303 # KB1L304 & !KB1L261);

--KB1L306 is std_1c20:inst|sdram:the_sdram|Mux28~1632

--operation mode is normal

KB1L306 = !KB1_m_state[4] & !KB1_m_state[3] & !KB1_m_state[7] & !KB1_m_state[1];

--KB1L307 is std_1c20:inst|sdram:the_sdram|Mux28~1633

--operation mode is normal

KB1L307 = !KB1_m_state[4] & !KB1_m_state[3] & (KB1_m_state[7] $ KB1_m_state[1]);

--KB1L308 is std_1c20:inst|sdram:the_sdram|Mux28~1634

--operation mode is normal

KB1L308 = !KB1_m_state[8] & (KB1_m_state[6] & KB1L306 # !KB1_m_state[6] & (KB1L307));

--KB1L277 is std_1c20:inst|sdram:the_sdram|Mux23~1127

--operation mode is normal

KB1L277 = KB1_m_next[7] & KB1L547 & KB1L272 & KB1L281;

--KB1L289 is std_1c20:inst|sdram:the_sdram|Mux26~1231

--operation mode is normal

KB1L289 = KB1_m_state[4] & (KB1_m_state[3] # KB1L294 # !KB1L298);

--KB1L290 is std_1c20:inst|sdram:the_sdram|Mux26~1232

--operation mode is normal

KB1L290 = KB1_m_state[2] & !KB1_m_state[8] & !KB1_m_count[2] & !KB1_m_count[1];

--KB1L291 is std_1c20:inst|sdram:the_sdram|Mux26~1233

--operation mode is normal

KB1L291 = KB1_m_state[8] & (!KB1_m_state[2]);

--KB1L292 is std_1c20:inst|sdram:the_sdram|Mux26~1234

--operation mode is normal

KB1L292 = TE1L127 & KB1L291 & !KB1L554 & !KB1_refresh_request;

--TE1L175 is std_1c20:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|rd_data[58]~509

--operation mode is normal

TE1L175 = TE1_rd_address & TE1_entry_1[58] # !TE1_rd_address & (TE1_entry_0[58]);

--KB1L293 is std_1c20:inst|sdram:the_sdram|Mux26~1235

--operation mode is normal

KB1L293 = KB1_m_next[4] & (KB1L290 # KB1L292 & !TE1L175) # !KB1_m_next[4] & (KB1L292 & !TE1L175);

--KB1L365 is std_1c20:inst|sdram:the_sdram|Mux41~1466

--operation mode is normal

KB1L365 = KB1_m_state[0] & (!KB1_m_state[3]);

--KB1L295 is std_1c20:inst|sdram:the_sdram|Mux27~1230

--operation mode is normal

KB1L295 = KB1_m_state[3] & (KB1_m_state[4] # KB1L294 # !KB1L298);

--KB1L296 is std_1c20:inst|sdram:the_sdram|Mux27~1231

--operation mode is normal

KB1L296 = TE1L175 & (KB1L292 # KB1_m_next[3] & KB1L290) # !TE1L175 & KB1_m_next[3] & KB1L290;

--KB1L297 is std_1c20:inst|sdram:the_sdram|Mux27~1232

--operation mode is normal

KB1L297 = KB1_m_state[0] & (!KB1_m_state[4]);

--KB1L315 is std_1c20:inst|sdram:the_sdram|Mux30~1231

--operation mode is normal

KB1L315 = KB1L348 & KB1L547 & KB1L290 & !KB1_m_next[0];

--KB1L29 is std_1c20:inst|sdram:the_sdram|active_cs_n~289

--operation mode is normal

KB1L29 = KB1_init_done & !KB1_m_state[4] & !KB1_m_state[3] & !KB1_m_state[8];

--KB1L30 is std_1c20:inst|sdram:the_sdram|active_cs_n~290

--operation mode is normal

KB1L30 = KB1L547 & KB1L29 & (!KB1_m_state[2]);

--KB1L392 is std_1c20:inst|sdram:the_sdram|Mux44~1260

--operation mode is normal

KB1L392 = KB1L547 & !KB1_m_state[2] & !KB1_refresh_request;

--KB1L393 is std_1c20:inst|sdram:the_sdram|Mux44~1261

--operation mode is normal

KB1L393 = KB1_m_state[0] & (KB1_m_state[8]) # !KB1_m_state[0] & KB1_init_done & !KB1_m_state[8];

--KB1L394 is std_1c20:inst|sdram:the_sdram|Mux44~1262

--operation mode is normal

KB1L394 = KB1L391 & KB1L393 & (!KB1_m_state[0] # !KB1L554);

--NB1L38 is std_1c20:inst|sdram_s1_arbitrator:the_sdram_s1|sdram_s1_address[9]~154

--operation mode is normal

NB1L38 = NB1L14 & S1_M_alu_result[11] # !NB1L14 & (S1_ic_fill_line[6]);

--KB1L237 is std_1c20:inst|sdram:the_sdram|module_input~21

--operation mode is normal

KB1L237 = NB1L18 # NB1L14 & (S1_internal_d_write # S1_internal_d_read);

--TE1_wr_address is std_1c20:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|wr_address

--operation mode is normal

TE1_wr_address_lut_out = TE1_wr_address $ (KB1L237 & (TE1_entries[0] # !TE1_entries[1]));

TE1_wr_address = DFFEAS(TE1_wr_address_lut_out, QC2__clk0, F1_data_out, , , , , , );

--KB1L419 is std_1c20:inst|sdram:the_sdram|Mux58~1328

--operation mode is normal

KB1L419 = TE1_rd_address & TE1_entry_1[45] # !TE1_rd_address & (TE1_entry_0[45]);

--KB1L396 is std_1c20:inst|sdram:the_sdram|Mux47~1291

--operation mode is normal

KB1L396 = KB1L264 & TE1L127 & !KB1L554 & !KB1_refresh_request;

--KB1L420 is std_1c20:inst|sdram:the_sdram|Mux58~1329

--operation mode is normal

KB1L420 = KB1L423 & (KB1_m_state[0] & !KB1L554 # !KB1_m_state[0] & (KB1_init_done));

--KB1L421 is std_1c20:inst|sdram:the_sdram|Mux58~1330

--operation mode is normal

KB1L421 = KB1_m_state[8] & (KB1_m_state[0] & KB1L420) # !KB1_m_state[8] & (KB1_m_state[0] & KB1L396 # !KB1_m_state[0] & (KB1L420));

--KB1L422 is std_1c20:inst|sdram:the_sdram|Mux58~1331

--operation mode is normal

KB1L422 = KB1L421 & (KB1L419) # !KB1L421 & KB1_active_addr[9];

--KB1L395 is std_1c20:inst|sdram:the_sdram|Mux44~1264

--operation mode is normal

KB1L395 = KB1L547 & (!KB1_m_state[2]);

--NB1L37 is std_1c20:inst|sdram_s1_arbitrator:the_sdram_s1|sdram_s1_address[8]~155

--operation mode is normal

NB1L37 = NB1L14 & S1_M_alu_result[10] # !NB1L14 & (S1_ic_fill_line[5]);

--KB1L12 is std_1c20:inst|sdram:the_sdram|active_addr[8]~4929

--operation mode is normal

KB1L12 = F1_data_out & KB1L395 & (KB1_init_done # KB1_m_state[0]);

--KB1L13 is std_1c20:inst|sdram:the_sdram|active_addr[8]~4930

--operation mode is normal

KB1L13 = KB1_m_state[0] & (!KB1_m_state[8] # !KB1L554);

--KB1L14 is std_1c20:inst|sdram:the_sdram|active_addr[8]~4931

--operation mode is normal

KB1L14 = KB1_m_state[8] & KB1L423 & (KB1L13) # !KB1_m_state[8] & (KB1L13 & (KB1L396) # !KB1L13 & KB1L423);

--NB1L43 is std_1c20:inst|sdram_s1_arbitrator:the_sdram_s1|sdram_s1_address[14]~156

--operation mode is normal

NB1L43 = NB1L14 & S1_M_alu_result[16] # !NB1L14 & (S1_ic_fill_tag[4]);

--KB1L409 is std_1c20:inst|sdram:the_sdram|Mux53~1277

--operation mode is normal

KB1L409 = TE1_rd_address & TE1_entry_1[50] # !TE1_rd_address & (TE1_entry_0[50]);

--KB1L410 is std_1c20:inst|sdram:the_sdram|Mux53~1278

--operation mode is normal

KB1L410 = KB1L421 & (KB1L409) # !KB1L421 & KB1_active_addr[14];

--NB1L42 is std_1c20:inst|sdram_s1_arbitrator:the_sdram_s1|sdram_s1_address[13]~157

--operation mode is normal

NB1L42 = NB1L14 & S1_M_alu_result[15] # !NB1L14 & (S1_ic_fill_tag[3]);

--KB1L411 is std_1c20:inst|sdram:the_sdram|Mux54~1277

--operation mode is normal

KB1L411 = TE1_rd_address & TE1_entry_1[49] # !TE1_rd_address & (TE1_entry_0[49]);

--KB1L412 is std_1c20:inst|sdram:the_sdram|Mux54~1278

--operation mode is normal

KB1L412 = KB1L421 & (KB1L411) # !KB1L421 & KB1_active_addr[13];

--NB1L40 is std_1c20:inst|sdram_s1_arbitrator:the_sdram_s1|sdram_s1_address[11]~158

--operation mode is normal

NB1L40 = NB1L14 & S1_M_alu_result[13] # !NB1L14 & (S1_ic_fill_tag[1]);

--KB1L415 is std_1c20:inst|sdram:the_sdram|Mux56~1277

--operation mode is normal

KB1L415 = TE1_rd_address & TE1_entry_1[47] # !TE1_rd_address & (TE1_entry_0[47]);

--KB1L416 is std_1c20:inst|sdram:the_sdram|Mux56~1278

--operation mode is normal

KB1L416 = KB1L421 & (KB1L415) # !KB1L421 & KB1_active_addr[11];

--NB1L50 is std_1c20:inst|sdram_s1_arbitrator:the_sdram_s1|sdram_s1_address[21]~159

--operation mode is normal

NB1L50 = NB1L14 & S1_M_alu_result[23] # !NB1L14 & (S1_ic_fill_tag[11]);

--NB1L45 is std_1c20:inst|sdram_s1_arbitrator:the_sdram_s1|sdram_s1_address[16]~160

--operation mode is normal

NB1L45 = NB1L14 & S1_M_alu_result[18] # !NB1L14 & (S1_ic_fill_tag[6]);

--KB1L405 is std_1c20:inst|sdram:the_sdram|Mux51~1277

--operation mode is normal

KB1L405 = TE1_rd_address & TE1_entry_1[52] # !TE1_rd_address & (TE1_entry_0[52]);

--KB1L406 is std_1c20:inst|sdram:the_sdram|Mux51~1278

--operation mode is normal

KB1L406 = KB1L421 & (KB1L405) # !KB1L421 & KB1_active_addr[16];

--NB1L44 is std_1c20:inst|sdram_s1_arbitrator:the_sdram_s1|sdram_s1_address[15]~161

--operation mode is normal

NB1L44 = NB1L14 & S1_M_alu_result[17] # !NB1L14 & (S1_ic_fill_tag[5]);

--KB1L407 is std_1c20:inst|sdram:the_sdram|Mux52~1277

--operation mode is normal

KB1L407 = TE1_rd_address & TE1_entry_1[51] # !TE1_rd_address & (TE1_entry_0[51]);

--KB1L408 is std_1c20:inst|sdram:the_sdram|Mux52~1278

--operation mode is normal

KB1L408 = KB1L421 & (KB1L407) # !KB1L421 & KB1_active_addr[15];

--NB1L46 is std_1c20:inst|sdram_s1_arbitrator:the_sdram_s1|sdram_s1_address[17]~162

--operation mode is normal

NB1L46 = NB1L14 & S1_M_alu_result[19] # !NB1L14 & (S1_ic_fill_tag[7]);

--KB1L403 is std_1c20:inst|sdram:the_sdram|Mux50~1277

--operation mode is normal

KB1L403 = TE1_rd_address & TE1_entry_1[53] # !TE1_rd_address & (TE1_entry_0[53]);

--KB1L404 is std_1c20:inst|sdram:the_sdram|Mux50~1278

--operation mode is normal

KB1L404 = KB1L421 & (KB1L403) # !KB1L421 & KB1_active_addr[17];

--NB1L39 is std_1c20:inst|sdram_s1_arbitrator:the_sdram_s1|sdram_s1_address[10]~163

--operation mode is normal

NB1L39 = NB1L14 & S1_M_alu_result[12] # !NB1L14 & (S1_ic_fill_tag[0]);

--KB1L417 is std_1c20:inst|sdram:the_sdram|Mux57~1277

--operation mode is normal

KB1L417 = TE1_rd_address & TE1_entry_1[46] # !TE1_rd_address & (TE1_entry_0[46]);

--KB1L418 is std_1c20:inst|sdram:the_sdram|Mux57~1278

--operation mode is normal

KB1L418 = KB1L421 & (KB1L417) # !KB1L421 & KB1_active_addr[10];

--NB1_sdram_s1_in_a_write_cycle is std_1c20:inst|sdram_s1_arbitrator:the_sdram_s1|sdram_s1_in_a_write_cycle

--operation mode is normal

NB1_sdram_s1_in_a_write_cycle = S1_internal_d_write & NB1L14;

--NB1L49 is std_1c20:inst|sdram_s1_arbitrator:the_sdram_s1|sdram_s1_address[20]~164

--operation mode is normal

NB1L49 = NB1L14 & S1_M_alu_result[22] # !NB1L14 & (S1_ic_fill_tag[10]);

--KB1L397 is std_1c20:inst|sdram:the_sdram|Mux47~1292

--operation mode is normal

KB1L397 = TE1_rd_address & TE1_entry_1[56] # !TE1_rd_address & (TE1_entry_0[56]);

--KB1L398 is std_1c20:inst|sdram:the_sdram|Mux47~1293

--operation mode is normal

KB1L398 = KB1L421 & (KB1L397) # !KB1L421 & KB1_active_addr[20];

--NB1L47 is std_1c20:inst|sdram_s1_arbitrator:the_sdram_s1|sdram_s1_address[18]~165

--operation mode is normal

NB1L47 = NB1L14 & S1_M_alu_result[20] # !NB1L14 & (S1_ic_fill_tag[8]);

--KB1L401 is std_1c20:inst|sdram:the_sdram|Mux49~1277

--operation mode is normal

KB1L401 = TE1_rd_address & TE1_entry_1[54] # !TE1_rd_address & (TE1_entry_0[54]);

--KB1L402 is std_1c20:inst|sdram:the_sdram|Mux49~1278

--operation mode is normal

KB1L402 = KB1L421 & (KB1L401) # !KB1L421 & KB1_active_addr[18];

--NB1L41 is std_1c20:inst|sdram_s1_arbitrator:the_sdram_s1|sdram_s1_address[12]~166

--operation mode is normal

NB1L41 = NB1L14 & S1_M_alu_result[14] # !NB1L14 & (S1_ic_fill_tag[2]);

--KB1L413 is std_1c20:inst|sdram:the_sdram|Mux55~1277

--operation mode is normal

KB1L413 = TE1_rd_address & TE1_entry_1[48] # !TE1_rd_address & (TE1_entry_0[48]);

--KB1L414 is std_1c20:inst|sdram:the_sdram|Mux55~1278

--operation mode is normal

KB1L414 = KB1L421 & (KB1L413) # !KB1L421 & KB1_active_addr[12];

--KB1L31 is std_1c20:inst|sdram:the_sdram|active_cs_n~291

--operation mode is normal

KB1L31 = F1_data_out & (!KB1_m_state[0]);

--KB1L32 is std_1c20:inst|sdram:the_sdram|active_cs_n~292

--operation mode is normal

KB1L32 = KB1L547 & KB1L29 & KB1L31 & !KB1_m_state[2];

--NB1L48 is std_1c20:inst|sdram_s1_arbitrator:the_sdram_s1|sdram_s1_address[19]~167

--operation mode is normal

NB1L48 = NB1L14 & S1_M_alu_result[21] # !NB1L14 & (S1_ic_fill_tag[9]);

--KB1L399 is std_1c20:inst|sdram:the_sdram|Mux48~1277

--operation mode is normal

KB1L399 = TE1_rd_address & TE1_entry_1[55] # !TE1_rd_address & (TE1_entry_0[55]);

--KB1L400 is std_1c20:inst|sdram:the_sdram|Mux48~1278

--operation mode is normal

KB1L400 = KB1L421 & (KB1L399) # !KB1L421 & KB1_active_addr[19];

--KB1_i_state[0] is std_1c20:inst|sdram:the_sdram|i_state[0]

--operation mode is normal

KB1_i_state[0]_lut_out = KB1L241 # KB1L138 & (KB1_i_state[1] # KB1L103);

KB1_i_state[0] = DFFEAS(KB1_i_state[0]_lut_out, QC2__clk0, F1_data_out, , , , , , );

--KB1_i_state[2] is std_1c20:inst|sdram:the_sdram|i_state[2]

--operation mode is normal

KB1_i_state[2]_lut_out = KB1_i_state[0] & (KB1_i_state[2] & (!KB1_i_state[1]) # !KB1_i_state[2] & KB1L238 & KB1_i_state[1]);

KB1_i_state[2] = DFFEAS(KB1_i_state[2]_lut_out, QC2__clk0, F1_data_out, , , , , , );

--KB1_i_state[1] is std_1c20:inst|sdram:the_sdram|i_state[1]

--operation mode is normal

KB1_i_state[1]_lut_out = KB1_i_state[0] & (KB1_i_state[1] & (KB1L239 # KB1_i_state[2]) # !KB1_i_state[1] & (!KB1_i_state[2])) # !KB1_i_state[0] & KB1_i_state[1] & (!KB1_i_state[2]);

KB1_i_state[1] = DFFEAS(KB1_i_state[1]_lut_out, QC2__clk0, F1_data_out, , , , , , );

--KB1L125 is std_1c20:inst|sdram:the_sdram|i_cmd[0]~642

--operation mode is normal

KB1L125 = KB1_i_state[0] & KB1_i_state[1] # !KB1_i_state[2];

--KB1_refresh_counter[3] is std_1c20:inst|sdram:the_sdram|refresh_counter[3]

--operation mode is normal

KB1_refresh_counter[3]_lut_out = !KB1L74;

KB1_refresh_counter[3] = DFFEAS(KB1_refresh_counter[3]_lut_out, QC2__clk0, F1_data_out, , , , , , );

--KB1_refresh_counter[0] is std_1c20:inst|sdram:the_sdram|refresh_counter[0]

--operation mode is normal

KB1_refresh_counter[0]_lut_out = KB1L76;

KB1_refresh_counter[0] = DFFEAS(KB1_refresh_counter[0]_lut_out, QC2__clk0, VCC, , , A1L276, !F1_data_out, , );

--KB1_refresh_counter[1] is std_1c20:inst|sdram:the_sdram|refresh_counter[1]

--operation mode is normal

KB1_refresh_counter[1]_lut_out = KB1L78 & (!KB1L103);

KB1_refresh_counter[1] = DFFEAS(KB1_refresh_counter[1]_lut_out, QC2__clk0, F1_data_out, , , , , , );

--KB1_refresh_counter[2] is std_1c20:inst|sdram:the_sdram|refresh_counter[2]

--operation mode is normal

KB1_refresh_counter[2]_lut_out = KB1L80;

KB1_refresh_counter[2] = DFFEAS(KB1_refresh_counter[2]_lut_out, QC2__clk0, VCC, , , A1L276, !F1_data_out, , );

--KB1L100 is std_1c20:inst|sdram:the_sdram|Equal1~172

--operation mode is normal

KB1L100 = KB1_refresh_counter[3] & !KB1_refresh_counter[0] & !KB1_refresh_counter[1] & !KB1_refresh_counter[2];

--KB1_refresh_counter[7] is std_1c20:inst|sdram:the_sdram|refresh_counter[7]

--operation mode is normal

KB1_refresh_counter[7]_lut_out = KB1L103 # !KB1L82;

KB1_refresh_counter[7] = DFFEAS(KB1_refresh_counter[7]_lut_out, QC2__clk0, F1_data_out, , , , , , );

--KB1_refresh_counter[4] is std_1c20:inst|sdram:the_sdram|refresh_counter[4]

--operation mode is normal

KB1_refresh_counter[4]_lut_out = KB1L84 & (!KB1L103);

KB1_refresh_counter[4] = DFFEAS(KB1_refresh_counter[4]_lut_out, QC2__clk0, F1_data_out, , , , , , );

--KB1_refresh_counter[5] is std_1c20:inst|sdram:the_sdram|refresh_counter[5]

--operation mode is normal

KB1_refresh_counter[5]_lut_out = KB1L86 & (!KB1L103);

KB1_refresh_counter[5] = DFFEAS(KB1_refresh_counter[5]_lut_out, QC2__clk0, F1_data_out, , , , , , );

--KB1_refresh_counter[6] is std_1c20:inst|sdram:the_sdram|refresh_counter[6]

--operation mode is normal

KB1_refresh_counter[6]_lut_out = KB1L88 & (!KB1L103);

KB1_refresh_counter[6] = DFFEAS(KB1_refresh_counter[6]_lut_out, QC2__clk0, F1_data_out, , , , , , );

--KB1L101 is std_1c20:inst|sdram:the_sdram|Equal1~173

--operation mode is normal

KB1L101 = KB1_refresh_counter[7] & !KB1_refresh_counter[4] & !KB1_refresh_counter[5] & !KB1_refresh_counter[6];

--KB1_refresh_counter[12] is std_1c20:inst|sdram:the_sdram|refresh_counter[12]

--operation mode is normal

KB1_refresh_counter[12]_lut_out = KB1L103 # !KB1L90;

KB1_refresh_counter[12] = DFFEAS(KB1_refresh_counter[12]_lut_out, QC2__clk0, F1_data_out, , , , , , );

--KB1_refresh_counter[8] is std_1c20:inst|sdram:the_sdram|refresh_counter[8]

--operation mode is normal

KB1_refresh_counter[8]_lut_out = !KB1L91;

KB1_refresh_counter[8] = DFFEAS(KB1_refresh_counter[8]_lut_out, QC2__clk0, F1_data_out, , , , , , );

--KB1_refresh_counter[9] is std_1c20:inst|sdram:the_sdram|refresh_counter[9]

--operation mode is normal

KB1_refresh_counter[9]_lut_out = !KB1L93;

KB1_refresh_counter[9] = DFFEAS(KB1_refresh_counter[9]_lut_out, QC2__clk0, F1_data_out, , , , , , );

--KB1_refresh_counter[10] is std_1c20:inst|sdram:the_sdram|refresh_counter[10]

--operation mode is normal

KB1_refresh_counter[10]_lut_out = KB1L95 & (!KB1L103);

KB1_refresh_counter[10] = DFFEAS(KB1_refresh_counter[10]_lut_out, QC2__clk0, F1_data_out, , , , , , );

--KB1_refresh_counter[11] is std_1c20:inst|sdram:the_sdram|refresh_counter[11]

--operation mode is normal

KB1_refresh_counter[11]_lut_out = KB1L97 & (!KB1L103);

KB1_refresh_counter[11] = DFFEAS(KB1_refresh_counter[11]_lut_out, QC2__clk0, F1_data_out, , , , , , );

--KB1L102 is std_1c20:inst|sdram:the_sdram|Equal1~174

--operation mode is normal

KB1L102 = KB1_refresh_counter[8] & KB1_refresh_counter[9] & !KB1_refresh_counter[10] & !KB1_refresh_counter[11];

--KB1L103 is std_1c20:inst|sdram:the_sdram|Equal1~175

--operation mode is normal

KB1L103 = KB1L100 & KB1L101 & KB1_refresh_counter[12] & KB1L102;

--KB1_ack_refresh_request is std_1c20:inst|sdram:the_sdram|ack_refresh_request

--operation mode is normal

KB1_ack_refresh_request_lut_out = KB1L271 & (KB1_m_state[7] # KB1_ack_refresh_request & !KB1_init_done) # !KB1L271 & (KB1_ack_refresh_request);

KB1_ack_refresh_request = DFFEAS(KB1_ack_refresh_request_lut_out, QC2__clk0, F1_data_out, , , , , , );

--KB1L341 is std_1c20:inst|sdram:the_sdram|Mux39~1239

--operation mode is normal

KB1L341 = KB1L306 & (KB1_refresh_request # TE1L127 & KB1L554);

--KB1L316 is std_1c20:inst|sdram:the_sdram|Mux32~1281

--operation mode is normal

KB1L316 = KB1L306 & KB1_init_done & (KB1_m_next[7] # KB1_refresh_request) # !KB1L306 & (KB1_m_next[7]);

--KB1L317 is std_1c20:inst|sdram:the_sdram|Mux32~1282

--operation mode is normal

KB1L317 = KB1_m_next[7] & (KB1_m_state[4] # KB1_m_state[1] # !KB1L221);

--KB1L318 is std_1c20:inst|sdram:the_sdram|Mux32~1283

--operation mode is normal

KB1L318 = KB1_m_state[4] & (KB1_m_state[7] # !KB1_m_state[1] & KB1L221) # !KB1_m_state[4] & KB1_m_state[1];

--KB1L319 is std_1c20:inst|sdram:the_sdram|Mux32~1284

--operation mode is normal

KB1L319 = KB1_m_state[3] & (KB1_m_state[7]) # !KB1_m_state[3] & KB1_m_next[7] & (KB1_m_state[7] $ !KB1L318);

--KB1L320 is std_1c20:inst|sdram:the_sdram|Mux32~1285

--operation mode is normal

KB1L320 = KB1_m_state[3] & (KB1L319 & (KB1_m_next[7]) # !KB1L319 & KB1L317) # !KB1_m_state[3] & (KB1L319);

--KB1L321 is std_1c20:inst|sdram:the_sdram|Mux32~1286

--operation mode is normal

KB1L321 = KB1_m_state[8] & (!KB1_m_state[0]) # !KB1_m_state[8] & (KB1_m_state[0] & (KB1L320) # !KB1_m_state[0] & KB1L316);

--KB1L342 is std_1c20:inst|sdram:the_sdram|Mux39~1240

--operation mode is normal

KB1L342 = !KB1_m_state[5] & !KB1_m_state[2] & !KB1_m_state[6];

--KB1L343 is std_1c20:inst|sdram:the_sdram|Mux39~1241

--operation mode is normal

KB1L343 = KB1L306 & (!KB1_refresh_request & !KB1_m_next[0] # !KB1_init_done) # !KB1L306 & (!KB1_m_next[0]);

--KB1L344 is std_1c20:inst|sdram:the_sdram|Mux39~1242

--operation mode is normal

KB1L344 = KB1_m_state[7] # KB1_m_state[1] & (KB1_m_state[4] # KB1_m_state[3]);

--KB1L345 is std_1c20:inst|sdram:the_sdram|Mux39~1243

--operation mode is normal

KB1L345 = KB1L344 & (KB1L348) # !KB1L344 & KB1L264 & KB1L221;

--KB1L346 is std_1c20:inst|sdram:the_sdram|Mux39~1244

--operation mode is normal

KB1L346 = KB1_m_next[0] & !KB1_m_state[1] & (KB1L345) # !KB1_m_next[0] & (KB1L344 # !KB1_m_state[1]);

--KB1L347 is std_1c20:inst|sdram:the_sdram|Mux39~1245

--operation mode is normal

KB1L347 = KB1_m_state[8] & (!KB1_m_state[0]) # !KB1_m_state[8] & (KB1_m_state[0] & (KB1L346) # !KB1_m_state[0] & KB1L343);

--KB1L336 is std_1c20:inst|sdram:the_sdram|Mux38~1211

--operation mode is normal

KB1L336 = KB1_m_next[1] & (KB1_init_done & !KB1_refresh_request # !KB1L306);

--KB1L337 is std_1c20:inst|sdram:the_sdram|Mux38~1212

--operation mode is normal

KB1L337 = KB1_m_next[1] & (KB1_m_state[4] # KB1_m_state[1] # !KB1L221);

--KB1L338 is std_1c20:inst|sdram:the_sdram|Mux38~1213

--operation mode is normal

KB1L338 = KB1_m_state[3] & (KB1_m_state[7]) # !KB1_m_state[3] & KB1_m_next[1] & (KB1_m_state[7] $ !KB1L318);

--KB1L339 is std_1c20:inst|sdram:the_sdram|Mux38~1214

--operation mode is normal

KB1L339 = KB1_m_state[3] & (KB1L338 & (KB1_m_next[1]) # !KB1L338 & KB1L337) # !KB1_m_state[3] & (KB1L338);

--KB1L340 is std_1c20:inst|sdram:the_sdram|Mux38~1215

--operation mode is normal

KB1L340 = KB1_m_state[8] & (!KB1_m_state[0]) # !KB1_m_state[8] & (KB1_m_state[0] & (KB1L339) # !KB1_m_state[0] & KB1L336);

--KB1L329 is std_1c20:inst|sdram:the_sdram|Mux36~1269

--operation mode is normal

KB1L329 = KB1_m_next[3] & (!KB1L222 # !KB1L448);

--KB1L330 is std_1c20:inst|sdram:the_sdram|Mux36~1270

--operation mode is normal

KB1L330 = KB1_m_state[4] & KB1_m_next[3] # !KB1_m_state[4] & (KB1_m_state[3] & KB1_m_next[3] # !KB1_m_state[3] & (KB1_active_rnw));

--KB1L331 is std_1c20:inst|sdram:the_sdram|Mux36~1271

--operation mode is normal

KB1L331 = KB1_m_next[3] & (KB1_init_done & !KB1_refresh_request # !KB1L348);

--KB1L332 is std_1c20:inst|sdram:the_sdram|Mux36~1272

--operation mode is normal

KB1L332 = KB1_m_state[1] & (!KB1_m_state[0]) # !KB1_m_state[1] & (KB1_m_state[0] & (KB1L335) # !KB1_m_state[0] & KB1L331);

--KB1L333 is std_1c20:inst|sdram:the_sdram|Mux36~1273

--operation mode is normal

KB1L333 = KB1_m_state[1] & (KB1L332 & (KB1_m_next[3]) # !KB1L332 & KB1L330) # !KB1_m_state[1] & (KB1L332);

--KB1L334 is std_1c20:inst|sdram:the_sdram|Mux36~1274

--operation mode is normal

KB1L334 = KB1_m_state[7] & (KB1_m_state[8]) # !KB1_m_state[7] & (KB1_m_state[8] & KB1L329 # !KB1_m_state[8] & (KB1L333));

--KB1L322 is std_1c20:inst|sdram:the_sdram|Mux35~1199

--operation mode is normal

KB1L322 = KB1_m_next[4] & (!KB1L222 # !KB1L448);

--KB1L323 is std_1c20:inst|sdram:the_sdram|Mux35~1200

--operation mode is normal

KB1L323 = KB1_m_state[4] & KB1_m_next[4] # !KB1_m_state[4] & (KB1_m_state[3] & KB1_m_next[4] # !KB1_m_state[3] & (!KB1_active_rnw));

--KB1L324 is std_1c20:inst|sdram:the_sdram|Mux35~1201

--operation mode is normal

KB1L324 = KB1_m_next[4] & (KB1_init_done & !KB1_refresh_request # !KB1L348);

--KB1L325 is std_1c20:inst|sdram:the_sdram|Mux35~1202

--operation mode is normal

KB1L325 = KB1_m_state[1] & (!KB1_m_state[0]) # !KB1_m_state[1] & (KB1_m_state[0] & (KB1L328) # !KB1_m_state[0] & KB1L324);

--KB1L326 is std_1c20:inst|sdram:the_sdram|Mux35~1203

--operation mode is normal

KB1L326 = KB1_m_state[1] & (KB1L325 & (KB1_m_next[4]) # !KB1L325 & KB1L323) # !KB1_m_state[1] & (KB1L325);

--KB1L327 is std_1c20:inst|sdram:the_sdram|Mux35~1204

--operation mode is normal

KB1L327 = KB1_m_state[7] & (KB1_m_state[8]) # !KB1_m_state[7] & (KB1_m_state[8] & KB1L322 # !KB1_m_state[8] & (KB1L326));

--XE1L15 is std_1c20:inst|uart1:the_uart1|uart1_regs:the_uart1_regs|Equal1~116

--operation mode is normal

XE1L15 = S1_M_alu_result[2] & S1_M_alu_result[3] & (!S1_M_alu_result[4]);

--SB1L2 is std_1c20:inst|sys_clk_timer_s1_arbitrator:the_sys_clk_timer_s1|cpu_data_master_requests_sys_clk_timer_s1~180

--operation mode is normal

SB1L2 = UB1L5 & UB1L6 & QB1L1 & !S1_M_alu_result[7];

--XE1L13 is std_1c20:inst|uart1:the_uart1|uart1_regs:the_uart1_regs|control_wr_strobe~26

--operation mode is normal

XE1L13 = S1_internal_d_write & S1_M_alu_result[6] & SB1L2 & !S1_M_alu_result[5];

--ZE1_unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out[0] is std_1c20:inst|uart1:the_uart1|uart1_tx:the_uart1_tx|unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out[0]

--operation mode is normal

ZE1_unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out[0]_lut_out = ZE1_unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out[1] & (!ZE1_do_load_shifter);

ZE1_unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out[0] = DFFEAS(ZE1_unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out[0]_lut_out, QC2__clk0, F1_data_out, , ZE1L42, , , , );

--ZE1_unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out[3] is std_1c20:inst|uart1:the_uart1|uart1_tx:the_uart1_tx|unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out[3]

--operation mode is normal

ZE1_unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out[3]_lut_out = ZE1_do_load_shifter & XE1_internal_tx_data[2] # !ZE1_do_load_shifter & (ZE1_unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out[4]);

ZE1_unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out[3] = DFFEAS(ZE1_unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out[3]_lut_out, QC2__clk0, F1_data_out, , ZE1L42, , , , );

--ZE1_unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out[2] is std_1c20:inst|uart1:the_uart1|uart1_tx:the_uart1_tx|unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out[2]

--operation mode is normal

ZE1_unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out[2]_lut_out = ZE1_do_load_shifter & XE1_internal_tx_data[1] # !ZE1_do_load_shifter & (ZE1_unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out[3]);

ZE1_unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out[2] = DFFEAS(ZE1_unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out[2]_lut_out, QC2__clk0, F1_data_out, , ZE1L42, , , , );

--ZE1_unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out[1] is std_1c20:inst|uart1:the_uart1|uart1_tx:the_uart1_tx|unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out[1]

--operation mode is normal

ZE1_unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out[1]_lut_out = ZE1_do_load_shifter & XE1_internal_tx_data[0] # !ZE1_do_load_shifter & (ZE1_unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out[2]);

ZE1_unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out[1] = DFFEAS(ZE1_unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out[1]_lut_out, QC2__clk0, F1_data_out, , ZE1L42, , , , );

--ZE1_unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out[4] is std_1c20:inst|uart1:the_uart1|uart1_tx:the_uart1_tx|unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out[4]

--operation mode is normal

ZE1_unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out[4]_lut_out = ZE1_do_load_shifter & XE1_internal_tx_data[3] # !ZE1_do_load_shifter & (ZE1_unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out[5]);

ZE1_unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out[4] = DFFEAS(ZE1_unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out[4]_lut_out, QC2__clk0, F1_data_out, , ZE1L42, , , , );

--ZE1L26 is std_1c20:inst|uart1:the_uart1|uart1_tx:the_uart1_tx|pre_txd~65

--operation mode is normal

ZE1L26 = !ZE1_unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out[3] & !ZE1_unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out[2] & !ZE1_unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out[1] & !ZE1_unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out[4];

--ZE1_unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out[5] is std_1c20:inst|uart1:the_uart1|uart1_tx:the_uart1_tx|unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out[5]

--operation mode is normal

ZE1_unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out[5]_lut_out = ZE1_do_load_shifter & XE1_internal_tx_data[4] # !ZE1_do_load_shifter & (ZE1_unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out[6]);

ZE1_unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out[5] = DFFEAS(ZE1_unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out[5]_lut_out, QC2__clk0, F1_data_out, , ZE1L42, , , , );

--ZE1_unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out[6] is std_1c20:inst|uart1:the_uart1|uart1_tx:the_uart1_tx|unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out[6]

--operation mode is normal

ZE1_unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out[6]_lut_out = ZE1_do_load_shifter & XE1_internal_tx_data[5] # !ZE1_do_load_shifter & (ZE1_unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out[7]);

ZE1_unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out[6] = DFFEAS(ZE1_unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out[6]_lut_out, QC2__clk0, F1_data_out, , ZE1L42, , , , );

--ZE1_unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out[7] is std_1c20:inst|uart1:the_uart1|uart1_tx:the_uart1_tx|unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out[7]

--operation mode is normal

ZE1_unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out[7]_lut_out = ZE1_do_load_shifter & XE1_internal_tx_data[6] # !ZE1_do_load_shifter & (ZE1_unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out[8]);

ZE1_unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out[7] = DFFEAS(ZE1_unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out[7]_lut_out, QC2__clk0, F1_data_out, , ZE1L42, , , , );

--ZE1_unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out[8] is std_1c20:inst|uart1:the_uart1|uart1_tx:the_uart1_tx|unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out[8]

--operation mode is normal

ZE1_unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out[8]_lut_out = ZE1_do_load_shifter & XE1_internal_tx_data[7] # !ZE1_do_load_shifter & (ZE1_unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out[9]);

ZE1_unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out[8] = DFFEAS(ZE1_unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out[8]_lut_out, QC2__clk0, F1_data_out, , ZE1L42, , , , );

--ZE1L27 is std_1c20:inst|uart1:the_uart1|uart1_tx:the_uart1_tx|pre_txd~66

--operation mode is normal

ZE1L27 = !ZE1_unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out[5] & !ZE1_unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out[6] & !ZE1_unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out[7] & !ZE1_unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out[8];

--ZE1_unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out[9] is std_1c20:inst|uart1:the_uart1|uart1_tx:the_uart1_tx|unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out[9]

--operation mode is normal

ZE1_unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out[9]_lut_out = ZE1_do_load_shifter;

ZE1_unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out[9] = DFFEAS(ZE1_unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out[9]_lut_out, QC2__clk0, F1_data_out, , ZE1L42, , , , );

--ZE1L28 is std_1c20:inst|uart1:the_uart1|uart1_tx:the_uart1_tx|pre_txd~67

--operation mode is normal

ZE1L28 = ZE1L26 & ZE1L27 & (!ZE1_unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out[9]);

--S1_M_ipending_reg[2] is std_1c20:inst|cpu:the_cpu|M_ipending_reg[2]

--operation mode is normal

S1_M_ipending_reg[2] = AMPP_FUNCTION(QC2__clk0, S1_M_ienable_reg[2], S1L1130, S1L1131, FD1_internal_oci_ienable1[2], F1_data_out);

--S1_M_ienable_reg[2] is std_1c20:inst|cpu:the_cpu|M_ienable_reg[2]

--operation mode is normal

S1_M_ienable_reg[2] = AMPP_FUNCTION(QC2__clk0, S1L408, F1_data_out, S1L1117);

--S1_D_iw[8] is std_1c20:inst|cpu:the_cpu|D_iw[8]

--operation mode is normal

S1_D_iw[8] = AMPP_FUNCTION(QC2__clk0, AD1_q_b[8], S1_M_status_reg_pie, S1L1062, S1L845, F1_data_out, S1_W_stall);

--S1_D_iw[7] is std_1c20:inst|cpu:the_cpu|D_iw[7]

--operation mode is normal

S1_D_iw[7] = AMPP_FUNCTION(QC2__clk0, AD1_q_b[7], S1_M_status_reg_pie, S1L1062, S1L845, F1_data_out, S1_W_stall);

--S1_D_iw[6] is std_1c20:inst|cpu:the_cpu|D_iw[6]

--operation mode is normal

S1_D_iw[6] = AMPP_FUNCTION(QC2__clk0, AD1_q_b[6], S1_M_status_reg_pie, S1L1062, S1L845, F1_data_out, S1_W_stall);

--S1L200 is std_1c20:inst|cpu:the_cpu|D_control_rd_data_without_mmu_regs[2]~497

--operation mode is normal

S1L200 = AMPP_FUNCTION(S1_D_iw[8], S1_D_iw[7], S1_D_iw[6]);

--S1_D_iw[4] is std_1c20:inst|cpu:the_cpu|D_iw[4]

--operation mode is normal

S1_D_iw[4] = AMPP_FUNCTION(QC2__clk0, AD1_q_b[4], S1L845, S1_M_status_reg_pie, S1L1062, F1_data_out, S1_W_stall);

--S1_D_iw[15] is std_1c20:inst|cpu:the_cpu|D_iw[15]

--operation mode is normal

S1_D_iw[15] = AMPP_FUNCTION(QC2__clk0, AD1_q_b[15], S1L845, S1_M_status_reg_pie, S1L1062, F1_data_out, S1_W_stall);

--S1_D_iw[0] is std_1c20:inst|cpu:the_cpu|D_iw[0]

--operation mode is normal

S1_D_iw[0] = AMPP_FUNCTION(QC2__clk0, AD1_q_b[0], S1_M_status_reg_pie, S1L1062, S1L845, F1_data_out, S1_W_stall);

--S1_D_iw[1] is std_1c20:inst|cpu:the_cpu|D_iw[1]

--operation mode is normal

S1_D_iw[1] = AMPP_FUNCTION(QC2__clk0, AD1_q_b[1], S1L845, S1_M_status_reg_pie, S1L1062, F1_data_out, S1_W_stall);

--S1_D_iw[2] is std_1c20:inst|cpu:the_cpu|D_iw[2]

--operation mode is normal

S1_D_iw[2] = AMPP_FUNCTION(QC2__clk0, AD1_q_b[2], S1_M_status_reg_pie, S1L1062, S1L845, F1_data_out, S1_W_stall);

--S1_D_iw[3] is std_1c20:inst|cpu:the_cpu|D_iw[3]

--operation mode is normal

S1_D_iw[3] = AMPP_FUNCTION(QC2__clk0, AD1_q_b[3], S1L845, S1_M_status_reg_pie, S1L1062, F1_data_out, S1_W_stall);

--S1L760 is std_1c20:inst|cpu:the_cpu|Equal53~851

--operation mode is normal

S1L760 = AMPP_FUNCTION(S1_D_iw[0], S1_D_iw[1], S1_D_iw[2], S1_D_iw[3]);

--S1_D_iw[5] is std_1c20:inst|cpu:the_cpu|D_iw[5]

--operation mode is normal

S1_D_iw[5] = AMPP_FUNCTION(QC2__clk0, AD1_q_b[5], S1L845, S1_M_status_reg_pie, S1L1062, F1_data_out, S1_W_stall);

--CD1_q_b[2] is std_1c20:inst|cpu:the_cpu|cpu_register_bank_a_module:cpu_register_bank_a|altsyncram:the_altsyncram|altsyncram_3vd1:auto_generated|q_b[2]

--RAM Block Operation Mode: Simple Dual-Port

--Port A Depth: 32, Port A Width: 1, Port B Depth: 32, Port B Width: 1

--Port A Logical Depth: 32, Port A Logical Width: 32, Port B Logical Depth: 32, Port B Logical Width: 32

--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered

CD1_q_b[2] = AMPP_FUNCTION(GND, GND, QC2__clk0, QC2__clk0, !S1_M_wr_dst_reg, S1_W_stall, S1L1288, S1_M_dst_regnum[0], S1_M_dst_regnum[1], S1_M_dst_regnum[2], S1_M_dst_regnum[3], S1_M_dst_regnum[4], AD1_q_b[27], AD1_q_b[28], AD1_q_b[29], AD1_q_b[30], AD1_q_b[31]);

--S1_W_wr_data[2] is std_1c20:inst|cpu:the_cpu|W_wr_data[2]

--operation mode is normal

S1_W_wr_data[2] = AMPP_FUNCTION(QC2__clk0, S1L1288, F1_data_out, S1_W_stall);

--S1_D_iw[29] is std_1c20:inst|cpu:the_cpu|D_iw[29]

--operation mode is normal

S1_D_iw[29] = AMPP_FUNCTION(QC2__clk0, AD1_q_b[29], S1_M_status_reg_pie, S1L1062, S1L845, F1_data_out, S1_W_stall);

--S1_D_iw[28] is std_1c20:inst|cpu:the_cpu|D_iw[28]

--operation mode is normal

S1_D_iw[28] = AMPP_FUNCTION(QC2__clk0, AD1_q_b[28], S1_M_status_reg_pie, S1L1062, S1L845, F1_data_out, S1_W_stall);

--S1_W_dst_regnum[1] is std_1c20:inst|cpu:the_cpu|W_dst_regnum[1]

--operation mode is normal

S1_W_dst_regnum[1] = AMPP_FUNCTION(QC2__clk0, S1_M_dst_regnum[1], F1_data_out, S1_W_stall);

--S1_W_dst_regnum[2] is std_1c20:inst|cpu:the_cpu|W_dst_regnum[2]

--operation mode is normal

S1_W_dst_regnum[2] = AMPP_FUNCTION(QC2__clk0, S1_M_dst_regnum[2], F1_data_out, S1_W_stall);

--S1L383 is std_1c20:inst|cpu:the_cpu|D_src1_hazard_W~39

--operation mode is normal

S1L383 = AMPP_FUNCTION(S1_D_iw[29], S1_D_iw[28], S1_W_dst_regnum[1], S1_W_dst_regnum[2]);

--S1_D_iw[30] is std_1c20:inst|cpu:the_cpu|D_iw[30]

--operation mode is normal

S1_D_iw[30] = AMPP_FUNCTION(QC2__clk0, AD1_q_b[30], S1_M_status_reg_pie, S1L1062, S1L845, F1_data_out, S1_W_stall);

--S1_D_iw[27] is std_1c20:inst|cpu:the_cpu|D_iw[27]

--operation mode is normal

S1_D_iw[27] = AMPP_FUNCTION(QC2__clk0, AD1_q_b[27], S1_M_status_reg_pie, S1L1062, S1L845, F1_data_out, S1_W_stall);

--S1_W_dst_regnum[0] is std_1c20:inst|cpu:the_cpu|W_dst_regnum[0]

--operation mode is normal

S1_W_dst_regnum[0] = AMPP_FUNCTION(QC2__clk0, S1_M_dst_regnum[0], F1_data_out, S1_W_stall);

--S1_W_dst_regnum[3] is std_1c20:inst|cpu:the_cpu|W_dst_regnum[3]

--operation mode is normal

S1_W_dst_regnum[3] = AMPP_FUNCTION(QC2__clk0, S1_M_dst_regnum[3], F1_data_out, S1_W_stall);

--S1L384 is std_1c20:inst|cpu:the_cpu|D_src1_hazard_W~40

--operation mode is normal

S1L384 = AMPP_FUNCTION(S1_D_iw[30], S1_D_iw[27], S1_W_dst_regnum[0], S1_W_dst_regnum[3]);

--S1_W_wr_dst_reg is std_1c20:inst|cpu:the_cpu|W_wr_dst_reg

--operation mode is normal

S1_W_wr_dst_reg = AMPP_FUNCTION(QC2__clk0, S1_M_wr_dst_reg, F1_data_out, S1_W_stall);

--S1_D_iw[31] is std_1c20:inst|cpu:the_cpu|D_iw[31]

--operation mode is normal

S1_D_iw[31] = AMPP_FUNCTION(QC2__clk0, AD1_q_b[31], S1_M_status_reg_pie, S1L1062, S1L845, F1_data_out, S1_W_stall);

--S1_W_dst_regnum[4] is std_1c20:inst|cpu:the_cpu|W_dst_regnum[4]

--operation mode is normal

S1_W_dst_regnum[4] = AMPP_FUNCTION(QC2__clk0, S1_M_dst_regnum[4], F1_data_out, S1_W_stall);

--S1L385 is std_1c20:inst|cpu:the_cpu|D_src1_hazard_W~41

--operation mode is normal

S1L385 = AMPP_FUNCTION(S1_W_wr_dst_reg, S1_D_iw[31], S1_W_dst_regnum[4]);

--S1L201 is std_1c20:inst|cpu:the_cpu|D_ctrl_a_not_src~78

--operation mode is normal

S1L201 = AMPP_FUNCTION(S1_D_iw[4], S1_D_iw[5]);

--S1L202 is std_1c20:inst|cpu:the_cpu|D_ctrl_a_not_src~79

--operation mode is normal

S1L202 = AMPP_FUNCTION(S1L201, S1_D_iw[1], S1_D_iw[2], S1_D_iw[3]);

--S1_D_src1_hazard_W is std_1c20:inst|cpu:the_cpu|D_src1_hazard_W

--operation mode is normal

S1_D_src1_hazard_W = AMPP_FUNCTION(S1L383, S1L384, S1L385, S1L202);

--S1_M_dst_regnum[1] is std_1c20:inst|cpu:the_cpu|M_dst_regnum[1]

--operation mode is normal

S1_M_dst_regnum[1] = AMPP_FUNCTION(QC2__clk0, S1_E_dst_regnum[1], F1_data_out, S1_W_stall);

--S1_M_dst_regnum[2] is std_1c20:inst|cpu:the_cpu|M_dst_regnum[2]

--operation mode is normal

S1_M_dst_regnum[2] = AMPP_FUNCTION(QC2__clk0, S1_E_dst_regnum[2], F1_data_out, S1_W_stall);

--S1L379 is std_1c20:inst|cpu:the_cpu|D_src1_hazard_M~39

--operation mode is normal

S1L379 = AMPP_FUNCTION(S1_D_iw[29], S1_D_iw[28], S1_M_dst_regnum[1], S1_M_dst_regnum[2]);

--S1_M_dst_regnum[0] is std_1c20:inst|cpu:the_cpu|M_dst_regnum[0]

--operation mode is normal

S1_M_dst_regnum[0] = AMPP_FUNCTION(QC2__clk0, S1_E_dst_regnum[0], F1_data_out, S1_W_stall);

--S1_M_dst_regnum[3] is std_1c20:inst|cpu:the_cpu|M_dst_regnum[3]

--operation mode is normal

S1_M_dst_regnum[3] = AMPP_FUNCTION(QC2__clk0, S1_E_dst_regnum[3], F1_data_out, S1_W_stall);

--S1L380 is std_1c20:inst|cpu:the_cpu|D_src1_hazard_M~40

--operation mode is normal

S1L380 = AMPP_FUNCTION(S1_D_iw[30], S1_D_iw[27], S1_M_dst_regnum[0], S1_M_dst_regnum[3]);

--S1_M_dst_regnum[4] is std_1c20:inst|cpu:the_cpu|M_dst_regnum[4]

--operation mode is normal

S1_M_dst_regnum[4] = AMPP_FUNCTION(QC2__clk0, S1_E_dst_regnum[4], F1_data_out, S1_W_stall);

--S1_M_wr_dst_reg is std_1c20:inst|cpu:the_cpu|M_wr_dst_reg

--operation mode is normal

S1_M_wr_dst_reg = AMPP_FUNCTION(QC2__clk0, S1L755, F1_data_out, S1_W_stall);

--S1L381 is std_1c20:inst|cpu:the_cpu|D_src1_hazard_M~41

--operation mode is normal

S1L381 = AMPP_FUNCTION(S1_D_iw[31], S1_M_dst_regnum[4], S1_M_wr_dst_reg);

--S1_D_src1_hazard_M is std_1c20:inst|cpu:the_cpu|D_src1_hazard_M

--operation mode is normal

S1_D_src1_hazard_M = AMPP_FUNCTION(S1L379, S1L380, S1L381, S1L202);

--S1_E_wr_dst_reg_from_D is std_1c20:inst|cpu:the_cpu|E_wr_dst_reg_from_D

--operation mode is normal

S1_E_wr_dst_reg_from_D = AMPP_FUNCTION(QC2__clk0, S1L400, S1L243, S1L780, S1L781, F1_data_out, S1_W_stall);

--S1L754 is std_1c20:inst|cpu:the_cpu|E_wr_dst_reg~37

--operation mode is normal

S1L754 = AMPP_FUNCTION(S1_M_pipe_flush, S1_E_wr_dst_reg_from_D);

--S1L755 is std_1c20:inst|cpu:the_cpu|E_wr_dst_reg~38

--operation mode is normal

S1L755 = AMPP_FUNCTION(S1L754, S1L479, S1L480, S1L926);

--S1_E_dst_regnum[4] is std_1c20:inst|cpu:the_cpu|E_dst_regnum[4]

--operation mode is normal

S1_E_dst_regnum[4] = AMPP_FUNCTION(QC2__clk0, S1L202, S1L231, S1L244, F1_data_out, S1_W_stall);

--S1_E_dst_regnum[1] is std_1c20:inst|cpu:the_cpu|E_dst_regnum[1]

--operation mode is normal

S1_E_dst_regnum[1] = AMPP_FUNCTION(QC2__clk0, S1L202, S1L240, S1L231, F1_data_out, S1_W_stall);

--S1L375 is std_1c20:inst|cpu:the_cpu|D_src1_hazard_E~54

--operation mode is normal

S1L375 = AMPP_FUNCTION(S1_D_iw[28], S1_D_iw[31], S1_E_dst_regnum[4], S1_E_dst_regnum[1]);

--S1_E_dst_regnum[2] is std_1c20:inst|cpu:the_cpu|E_dst_regnum[2]

--operation mode is normal

S1_E_dst_regnum[2] = AMPP_FUNCTION(QC2__clk0, S1L202, S1L231, S1L241, F1_data_out, S1_W_stall);

--S1L376 is std_1c20:inst|cpu:the_cpu|D_src1_hazard_E~55

--operation mode is normal

S1L376 = AMPP_FUNCTION(S1L375, S1_D_iw[29], S1_E_dst_regnum[2]);

--S1_E_dst_regnum[3] is std_1c20:inst|cpu:the_cpu|E_dst_regnum[3]

--operation mode is normal

S1_E_dst_regnum[3] = AMPP_FUNCTION(QC2__clk0, S1L243, F1_data_out, S1_W_stall);

--S1_E_dst_regnum[0] is std_1c20:inst|cpu:the_cpu|E_dst_regnum[0]

--operation mode is normal

S1_E_dst_regnum[0] = AMPP_FUNCTION(QC2__clk0, S1L202, S1L231, S1L239, F1_data_out, S1_W_stall);

--S1L377 is std_1c20:inst|cpu:the_cpu|D_src1_hazard_E~56

--operation mode is normal

S1L377 = AMPP_FUNCTION(S1_D_iw[30], S1_E_dst_regnum[3], S1_D_iw[27], S1_E_dst_regnum[0]);

--S1_M_shift_rot_result[1] is std_1c20:inst|cpu:the_cpu|M_shift_rot_result[1]

--operation mode is normal

S1_M_shift_rot_result[1] = AMPP_FUNCTION(QC2__clk0, S1_M_shift_rot_result[0], S1_M_shift_rot_result[2], S1L570, S1_M_ctrl_shift_rot_right, F1_data_out, !S1_M_shift_rot_stall);

--S1_M_ctrl_shift_rot_right is std_1c20:inst|cpu:the_cpu|M_ctrl_shift_rot_right

--operation mode is normal

S1_M_ctrl_shift_rot_right = AMPP_FUNCTION(QC2__clk0, S1_E_ctrl_shift_rot_right, F1_data_out, S1_W_stall);

--S1_E_ctrl_shift_rot is std_1c20:inst|cpu:the_cpu|E_ctrl_shift_rot

--operation mode is normal

S1_E_ctrl_shift_rot = AMPP_FUNCTION(QC2__clk0, S1L234, F1_data_out, S1_W_stall);

--S1L341Q is std_1c20:inst|cpu:the_cpu|d_readdata_d1[2]~86

--operation mode is normal

S1L341Q = AMPP_FUNCTION(QC2__clk0, T1L48, U1L112, X1_cpu_data_master_requests_epcs_controller_epcs_control_port, F1_data_out);

--S1L339Q is std_1c20:inst|cpu:the_cpu|d_readdata_d1[0]~96

--operation mode is normal

S1L339Q = AMPP_FUNCTION(QC2__clk0, V1_cpu_data_master_requests_cpu_jtag_debug_module, F1_data_out);

--S1L933Q is std_1c20:inst|cpu:the_cpu|i_readdata_d1[2]~95

--operation mode is normal

S1L933Q = AMPP_FUNCTION(QC2__clk0, WC1L3, WC1L19, FD1_internal_oci_ienable1[2], FD1L3, F1_data_out);

--T1_cpu_data_master_readdata[2] is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[2]

--operation mode is normal

T1_cpu_data_master_readdata[2] = S1L341Q & (S1L339Q # S1L933Q);

--S1_d_readdata_d1[18] is std_1c20:inst|cpu:the_cpu|d_readdata_d1[18]

--operation mode is normal

S1_d_readdata_d1[18] = AMPP_FUNCTION(QC2__clk0, T1L154, WC1L19, WC1L20, V1_cpu_data_master_requests_cpu_jtag_debug_module, F1_data_out);

--S1_M_iw[4] is std_1c20:inst|cpu:the_cpu|M_iw[4]

--operation mode is normal

S1_M_iw[4] = AMPP_FUNCTION(QC2__clk0, S1_E_iw[4], F1_data_out, S1_W_stall);

--S1_M_ld_align_sh16 is std_1c20:inst|cpu:the_cpu|M_ld_align_sh16

--operation mode is normal

S1_M_ld_align_sh16 = AMPP_FUNCTION(S1_M_alu_result[1], S1_M_iw[4]);

--S1_M_iw[3] is std_1c20:inst|cpu:the_cpu|M_iw[3]

--operation mode is normal

S1_M_iw[3] = AMPP_FUNCTION(QC2__clk0, S1_E_iw[3], F1_data_out, S1_W_stall);

--S1_M_ld_align_sh8 is std_1c20:inst|cpu:the_cpu|M_ld_align_sh8

--operation mode is normal

S1_M_ld_align_sh8 = AMPP_FUNCTION(S1_M_alu_result[0], S1_M_iw[4], S1_M_iw[3]);

--S1_av_ld_aligning_data is std_1c20:inst|cpu:the_cpu|av_ld_aligning_data

--operation mode is normal

S1_av_ld_aligning_data = AMPP_FUNCTION(QC2__clk0, S1_internal_d_read, T1_internal_cpu_data_master_waitrequest, F1_data_out);

--S1L227 is std_1c20:inst|cpu:the_cpu|D_ctrl_hi_imm~100

--operation mode is normal

S1L227 = AMPP_FUNCTION(S1_D_iw[0], S1_D_iw[1], S1_D_iw[4], S1_D_iw[3]);

--S1_E_src2_prelim[2] is std_1c20:inst|cpu:the_cpu|E_src2_prelim[2]

--operation mode is normal

S1_E_src2_prelim[2] = AMPP_FUNCTION(QC2__clk0, DD1_q_b[2], S1_W_wr_data[2], S1L1288, S1L396, F1_data_out, S1L392, S1_W_stall);

--S1L777 is std_1c20:inst|cpu:the_cpu|Equal143~6

--operation mode is normal

S1L777 = AMPP_FUNCTION(S1_E_iw[4], S1_E_iw[3]);

--S1L211 is std_1c20:inst|cpu:the_cpu|D_ctrl_b_is_dst~79

--operation mode is normal

S1L211 = AMPP_FUNCTION(S1_D_iw[4], S1_D_iw[5], S1_D_iw[0], S1_D_iw[1]);

--S1L212 is std_1c20:inst|cpu:the_cpu|D_ctrl_b_not_src~56

--operation mode is normal

S1L212 = AMPP_FUNCTION(S1_D_iw[2], S1_D_iw[0], S1_D_iw[1], S1L211);

--S1L761 is std_1c20:inst|cpu:the_cpu|Equal53~852

--operation mode is normal

S1L761 = AMPP_FUNCTION(S1_D_iw[0], S1_D_iw[1], S1_D_iw[2], S1_D_iw[3]);

--S1L762 is std_1c20:inst|cpu:the_cpu|Equal53~853

--operation mode is normal

S1L762 = AMPP_FUNCTION(S1_D_iw[4], S1L761, S1_D_iw[5]);

--S1L235 is std_1c20:inst|cpu:the_cpu|D_ctrl_src2_is_imm~49

--operation mode is normal

S1L235 = AMPP_FUNCTION(S1L212, S1L762, S1L398, S1L399);

--S1_D_iw[12] is std_1c20:inst|cpu:the_cpu|D_iw[12]

--operation mode is normal

S1_D_iw[12] = AMPP_FUNCTION(QC2__clk0, AD1_q_b[12], S1_M_status_reg_pie, S1L1062, S1L845, F1_data_out, S1_W_stall);

--S1L763 is std_1c20:inst|cpu:the_cpu|Equal53~854

--operation mode is normal

S1L763 = AMPP_FUNCTION(S1_D_iw[4], S1_D_iw[5]);

--S1_D_iw[13] is std_1c20:inst|cpu:the_cpu|D_iw[13]

--operation mode is normal

S1_D_iw[13] = AMPP_FUNCTION(QC2__clk0, AD1_q_b[13], S1L845, S1_M_status_reg_pie, S1L1062, F1_data_out, S1_W_stall);

--S1L234 is std_1c20:inst|cpu:the_cpu|D_ctrl_shift_rot~57

--operation mode is normal

S1L234 = AMPP_FUNCTION(S1_D_iw[12], S1L760, S1L763, S1_D_iw[13]);

--S1_D_iw[11] is std_1c20:inst|cpu:the_cpu|D_iw[11]

--operation mode is normal

S1_D_iw[11] = AMPP_FUNCTION(QC2__clk0, AD1_q_b[11], S1L845, S1_M_status_reg_pie, S1L1062, F1_data_out, S1_W_stall);

--S1_D_iw[14] is std_1c20:inst|cpu:the_cpu|D_iw[14]

--operation mode is normal

S1_D_iw[14] = AMPP_FUNCTION(QC2__clk0, AD1_q_b[14], S1_M_status_reg_pie, S1L1062, S1L845, F1_data_out, S1_W_stall);

--S1_D_pc_plus_one[0] is std_1c20:inst|cpu:the_cpu|D_pc_plus_one[0]

--operation mode is normal

S1_D_pc_plus_one[0] = AMPP_FUNCTION(QC2__clk0, S1L872, F1_data_out, S1_W_stall);

--S1_D_br_taken_waddr_partial[0] is std_1c20:inst|cpu:the_cpu|D_br_taken_waddr_partial[0]

--operation mode is arithmetic

S1_D_br_taken_waddr_partial[0] = AMPP_FUNCTION(QC2__clk0, AD1_q_b[8], S1L872, F1_data_out, S1_W_stall);

--S1L178 is std_1c20:inst|cpu:the_cpu|D_br_taken_waddr_partial[0]~55

--operation mode is arithmetic

S1L178 = AMPP_FUNCTION(AD1_q_b[8], S1L872);

--S1L213 is std_1c20:inst|cpu:the_cpu|D_ctrl_br_cond~94

--operation mode is normal

S1L213 = AMPP_FUNCTION(S1_D_iw[4], S1_D_iw[5], S1_D_iw[2], S1_D_iw[3]);

--S1L214 is std_1c20:inst|cpu:the_cpu|D_ctrl_br_cond~95

--operation mode is normal

S1L214 = AMPP_FUNCTION(S1_D_iw[1], S1L213, S1_D_iw[0]);

--S1_D_iw[21] is std_1c20:inst|cpu:the_cpu|D_iw[21]

--operation mode is normal

S1_D_iw[21] = AMPP_FUNCTION(QC2__clk0, AD1_q_b[21], S1L845, S1_M_status_reg_pie, S1L1062, F1_data_out, S1_W_stall);

--S1_E_ctrl_alu_subtract is std_1c20:inst|cpu:the_cpu|E_ctrl_alu_subtract

--operation mode is normal

S1_E_ctrl_alu_subtract = AMPP_FUNCTION(QC2__clk0, S1L207, S1L208, S1L209, S1L210, F1_data_out, S1_W_stall);

--S1L764 is std_1c20:inst|cpu:the_cpu|Equal53~855

--operation mode is normal

S1L764 = AMPP_FUNCTION(S1_D_iw[0], S1_D_iw[1], S1_D_iw[2], S1_D_iw[3]);

--S1L765 is std_1c20:inst|cpu:the_cpu|Equal53~856

--operation mode is normal

S1L765 = AMPP_FUNCTION(S1_D_iw[5], S1L764, S1_D_iw[4]);

--S1_D_iw[16] is std_1c20:inst|cpu:the_cpu|D_iw[16]

--operation mode is normal

S1_D_iw[16] = AMPP_FUNCTION(QC2__clk0, AD1_q_b[16], S1L845, S1_M_status_reg_pie, S1L1062, F1_data_out, S1_W_stall);

--S1L771 is std_1c20:inst|cpu:the_cpu|Equal77~1059

--operation mode is normal

S1L771 = AMPP_FUNCTION(S1_D_iw[14], S1_D_iw[15]);

--S1L218 is std_1c20:inst|cpu:the_cpu|D_ctrl_dst_data_sel_pc_plus_one~66

--operation mode is normal

S1L218 = AMPP_FUNCTION(S1_D_iw[13], S1L233, S1_D_iw[16], S1L771);

--S1L772 is std_1c20:inst|cpu:the_cpu|Equal77~1060

--operation mode is normal

S1L772 = AMPP_FUNCTION(S1_D_iw[12], S1_D_iw[13], S1L760, S1L763);

--S1L773 is std_1c20:inst|cpu:the_cpu|Equal77~1061

--operation mode is normal

S1L773 = AMPP_FUNCTION(S1_D_iw[11], S1L772);

--S1L766 is std_1c20:inst|cpu:the_cpu|Equal53~857

--operation mode is normal

S1L766 = AMPP_FUNCTION(S1_D_iw[0], S1_D_iw[1], S1_D_iw[2], S1_D_iw[3]);

--S1L217 is std_1c20:inst|cpu:the_cpu|D_ctrl_dst_data_sel_logic_result~51

--operation mode is normal

S1L217 = AMPP_FUNCTION(S1L766, S1_D_iw[4], S1L764);

--S1L774 is std_1c20:inst|cpu:the_cpu|Equal77~1062

--operation mode is normal

S1L774 = AMPP_FUNCTION(S1_D_iw[16], S1_D_iw[14]);

--S1L767 is std_1c20:inst|cpu:the_cpu|Equal53~858

--operation mode is normal

S1L767 = AMPP_FUNCTION(S1_D_iw[0], S1_D_iw[1], S1_D_iw[2], S1_D_iw[3]);

--S1L768 is std_1c20:inst|cpu:the_cpu|Equal53~859

--operation mode is normal

S1L768 = AMPP_FUNCTION(S1_D_iw[0], S1_D_iw[1], S1_D_iw[2], S1_D_iw[3]);

--S1L216 is std_1c20:inst|cpu:the_cpu|D_ctrl_dst_data_sel_cmp~174

--operation mode is normal

S1L216 = AMPP_FUNCTION(S1L767, S1L768, S1_D_iw[4], S1_D_iw[5]);

--S1L206 is std_1c20:inst|cpu:the_cpu|D_ctrl_alu_subtract~404

--operation mode is normal

S1L206 = AMPP_FUNCTION(S1L760, S1_D_iw[12], S1_D_iw[13]);

--S1L1220 is std_1c20:inst|cpu:the_cpu|M_shift_rot_stall_nxt~21

--operation mode is normal

S1L1220 = AMPP_FUNCTION(S1_M_shift_rot_stall, S1L752, S1_E_ctrl_shift_rot, S1_W_stall);

--S1L118 is std_1c20:inst|cpu:the_cpu|Add9~277

--operation mode is arithmetic

S1L118 = AMPP_FUNCTION(S1_M_shift_rot_cnt[1], S1L122);

--S1L119 is std_1c20:inst|cpu:the_cpu|Add9~278

--operation mode is arithmetic

S1L119 = AMPP_FUNCTION(S1_M_shift_rot_cnt[1], S1L122);

--S1_E_src2_imm[1] is std_1c20:inst|cpu:the_cpu|E_src2_imm[1]

--operation mode is normal

S1_E_src2_imm[1] = AMPP_FUNCTION(QC2__clk0, S1_D_iw[7], S1_D_iw[2], S1_D_iw[5], S1L227, F1_data_out, S1_W_stall);

--S1L636 is std_1c20:inst|cpu:the_cpu|E_src2[1]~1527

--operation mode is normal

S1L636 = AMPP_FUNCTION(S1_E_src2_imm[1], S1L1233, S1_E_ctrl_src2_is_imm);

--S1L120 is std_1c20:inst|cpu:the_cpu|Add9~279

--operation mode is normal

S1L120 = AMPP_FUNCTION(S1L118, S1L636, S1_M_shift_rot_stall);

--S1L121 is std_1c20:inst|cpu:the_cpu|Add9~280

--operation mode is arithmetic

S1L121 = AMPP_FUNCTION(S1_M_shift_rot_cnt[0]);

--S1L122 is std_1c20:inst|cpu:the_cpu|Add9~281

--operation mode is arithmetic

S1L122 = AMPP_FUNCTION(S1_M_shift_rot_cnt[0]);

--S1L123 is std_1c20:inst|cpu:the_cpu|Add9~282

--operation mode is arithmetic

S1L123 = AMPP_FUNCTION(S1_M_shift_rot_cnt[2], S1L119);

--S1L124 is std_1c20:inst|cpu:the_cpu|Add9~283

--operation mode is arithmetic

S1L124 = AMPP_FUNCTION(S1_M_shift_rot_cnt[2], S1L119);

--S1_E_src2_imm[0] is std_1c20:inst|cpu:the_cpu|E_src2_imm[0]

--operation mode is normal

S1_E_src2_imm[0] = AMPP_FUNCTION(QC2__clk0, S1_D_iw[6], S1_D_iw[2], S1_D_iw[5], S1L227, F1_data_out, S1_W_stall);

--S1L782 is std_1c20:inst|cpu:the_cpu|Equal199~132

--operation mode is normal

S1L782 = AMPP_FUNCTION(S1_E_src2_imm[0], S1_E_src2_imm[2]);

--S1L783 is std_1c20:inst|cpu:the_cpu|Equal199~133

--operation mode is normal

S1L783 = AMPP_FUNCTION(S1L1231, S1L1235, S1_E_ctrl_src2_is_imm, S1L782);

--S1L784 is std_1c20:inst|cpu:the_cpu|Equal199~134

--operation mode is normal

S1L784 = AMPP_FUNCTION(S1_M_shift_rot_stall, S1L121, S1L123, S1L783);

--S1L125 is std_1c20:inst|cpu:the_cpu|Add9~284

--operation mode is normal

S1L125 = AMPP_FUNCTION(S1_M_shift_rot_cnt[4], S1L127);

--S1L126 is std_1c20:inst|cpu:the_cpu|Add9~286

--operation mode is arithmetic

S1L126 = AMPP_FUNCTION(S1_M_shift_rot_cnt[3], S1L124);

--S1L127 is std_1c20:inst|cpu:the_cpu|Add9~287

--operation mode is arithmetic

S1L127 = AMPP_FUNCTION(S1_M_shift_rot_cnt[3], S1L124);

--S1L785 is std_1c20:inst|cpu:the_cpu|Equal199~135

--operation mode is normal

S1L785 = AMPP_FUNCTION(S1_E_src2_imm[4], S1_E_src2_imm[3]);

--S1L786 is std_1c20:inst|cpu:the_cpu|Equal199~136

--operation mode is normal

S1L786 = AMPP_FUNCTION(S1L1239, S1L1237, S1_E_ctrl_src2_is_imm, S1L785);

--S1L787 is std_1c20:inst|cpu:the_cpu|Equal199~137

--operation mode is normal

S1L787 = AMPP_FUNCTION(S1_M_shift_rot_stall, S1L125, S1L126, S1L786);

--S1_M_ipending_reg[3] is std_1c20:inst|cpu:the_cpu|M_ipending_reg[3]

--operation mode is normal

S1_M_ipending_reg[3] = AMPP_FUNCTION(QC2__clk0, S1_M_ienable_reg[3], Z1_control_register[0], Z1_timeout_occurred, FD1_internal_oci_ienable1[3], F1_data_out);

--S1_M_ienable_reg[3] is std_1c20:inst|cpu:the_cpu|M_ienable_reg[3]

--operation mode is normal

S1_M_ienable_reg[3] = AMPP_FUNCTION(QC2__clk0, S1L409, F1_data_out, S1L1117);

--CD1_q_b[3] is std_1c20:inst|cpu:the_cpu|cpu_register_bank_a_module:cpu_register_bank_a|altsyncram:the_altsyncram|altsyncram_3vd1:auto_generated|q_b[3]

--RAM Block Operation Mode: Simple Dual-Port

--Port A Depth: 32, Port A Width: 1, Port B Depth: 32, Port B Width: 1

--Port A Logical Depth: 32, Port A Logical Width: 32, Port B Logical Depth: 32, Port B Logical Width: 32

--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered

CD1_q_b[3] = AMPP_FUNCTION(GND, GND, QC2__clk0, QC2__clk0, !S1_M_wr_dst_reg, S1_W_stall, S1L1291, S1_M_dst_regnum[0], S1_M_dst_regnum[1], S1_M_dst_regnum[2], S1_M_dst_regnum[3], S1_M_dst_regnum[4], AD1_q_b[27], AD1_q_b[28], AD1_q_b[29], AD1_q_b[30], AD1_q_b[31]);

--S1_W_wr_data[3] is std_1c20:inst|cpu:the_cpu|W_wr_data[3]

--operation mode is normal

S1_W_wr_data[3] = AMPP_FUNCTION(QC2__clk0, S1L1291, F1_data_out, S1_W_stall);

--S1L342Q is std_1c20:inst|cpu:the_cpu|d_readdata_d1[3]~87

--operation mode is normal

S1L342Q = AMPP_FUNCTION(QC2__clk0, T1L57, U1L113, X1_cpu_data_master_requests_epcs_controller_epcs_control_port, F1_data_out);

--S1L936Q is std_1c20:inst|cpu:the_cpu|i_readdata_d1[3]~98

--operation mode is normal

S1L936Q = AMPP_FUNCTION(QC2__clk0, WC1L4, WC1L19, FD1L3, FD1_internal_oci_ienable1[3], F1_data_out);

--T1_cpu_data_master_readdata[3] is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[3]

--operation mode is normal

T1_cpu_data_master_readdata[3] = S1L342Q & (S1L339Q # S1L936Q);

--S1_d_readdata_d1[19] is std_1c20:inst|cpu:the_cpu|d_readdata_d1[19]

--operation mode is normal

S1_d_readdata_d1[19] = AMPP_FUNCTION(QC2__clk0, T1L157, WC1L19, WC1L21, V1_cpu_data_master_requests_cpu_jtag_debug_module, F1_data_out);

--S1_D_iw[9] is std_1c20:inst|cpu:the_cpu|D_iw[9]

--operation mode is normal

S1_D_iw[9] = AMPP_FUNCTION(QC2__clk0, AD1_q_b[9], S1_M_status_reg_pie, S1L1062, S1L845, F1_data_out, S1_W_stall);

--S1_E_src2_prelim[3] is std_1c20:inst|cpu:the_cpu|E_src2_prelim[3]

--operation mode is normal

S1_E_src2_prelim[3] = AMPP_FUNCTION(QC2__clk0, DD1_q_b[3], S1_W_wr_data[3], S1L1291, S1L396, F1_data_out, S1L392, S1_W_stall);

--S1_D_pc_plus_one[1] is std_1c20:inst|cpu:the_cpu|D_pc_plus_one[1]

--operation mode is normal

S1_D_pc_plus_one[1] = AMPP_FUNCTION(QC2__clk0, S1L874, F1_data_out, S1_W_stall);

--S1_D_br_taken_waddr_partial[1] is std_1c20:inst|cpu:the_cpu|D_br_taken_waddr_partial[1]

--operation mode is arithmetic

S1_D_br_taken_waddr_partial[1] = AMPP_FUNCTION(QC2__clk0, AD1_q_b[9], S1L874, F1_data_out, S1_W_stall, S1L178);

--S1L180 is std_1c20:inst|cpu:the_cpu|D_br_taken_waddr_partial[1]~56

--operation mode is arithmetic

S1L180 = AMPP_FUNCTION(AD1_q_b[9], S1L874, S1L178);

--S1_D_issue is std_1c20:inst|cpu:the_cpu|D_issue

--operation mode is normal

S1_D_issue = AMPP_FUNCTION(QC2__clk0, S1L814, S1L819, S1L818, S1_F_kill, F1_data_out, S1_W_stall);

--S1_E_ctrl_flush_pipe_always is std_1c20:inst|cpu:the_cpu|E_ctrl_flush_pipe_always

--operation mode is normal

S1_E_ctrl_flush_pipe_always = AMPP_FUNCTION(QC2__clk0, S1L776, S1L225, S1L226, S1L773, F1_data_out, S1_W_stall);

--S1_E_ctrl_br_cond is std_1c20:inst|cpu:the_cpu|E_ctrl_br_cond

--operation mode is normal

S1_E_ctrl_br_cond = AMPP_FUNCTION(QC2__clk0, S1L214, F1_data_out, S1_W_stall);

--S1_E_iw[21] is std_1c20:inst|cpu:the_cpu|E_iw[21]

--operation mode is normal

S1_E_iw[21] = AMPP_FUNCTION(QC2__clk0, S1_D_iw[21], F1_data_out, S1_W_stall);

--XC1L1 is std_1c20:inst|cpu:the_cpu|cpu_test_bench:the_cpu_test_bench|Add0~558

--operation mode is normal

XC1L1 = AMPP_FUNCTION(XC1L3);

--YC1_result[32] is std_1c20:inst|cpu:the_cpu|lpm_add_sub:Add8|alt_stratix_add_sub:stratix_adder|result[32]

--operation mode is normal

YC1_result[32] = AMPP_FUNCTION(GND, YC1L65, S1_E_ctrl_alu_subtract);

--S1L415 is std_1c20:inst|cpu:the_cpu|E_br_actually_taken~243

--operation mode is normal

S1L415 = AMPP_FUNCTION(XC1L1, S1_E_logic_op[1], YC1_result[32], S1_E_logic_op[0]);

--S1L1153 is std_1c20:inst|cpu:the_cpu|M_pipe_flush_nxt~107

--operation mode is normal

S1L1153 = AMPP_FUNCTION(S1_E_ctrl_br_cond, S1_E_iw[21], S1L415);

--JD1_probepresent is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_debug:the_cpu_nios2_oci_debug|probepresent

--operation mode is normal

JD1_probepresent = AMPP_FUNCTION(QC2__clk0, SD1_internal_jdo1[19], JD1_probepresent, SD1_internal_jdo1[18], !C1_CLR_SIGNAL, SD1L191);

--SD1_internal_jdo1[21] is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|internal_jdo1[21]

--operation mode is normal

SD1_internal_jdo1[21] = AMPP_FUNCTION(A1L8, SD1_sr[21], VCC, SD1L145);

--SD1_internal_jdo1[20] is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|internal_jdo1[20]

--operation mode is normal

SD1_internal_jdo1[20] = AMPP_FUNCTION(A1L8, SD1_sr[20], VCC, SD1L145);

--JD1L1 is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_debug:the_cpu_nios2_oci_debug|A_WE_StdLogicVector~9

--operation mode is normal

JD1L1 = AMPP_FUNCTION(SD1_internal_jdo1[21], JD1_jtag_break, SD1_internal_jdo1[20]);

--C1_CLR_SIGNAL is sld_hub:sld_hub_inst|CLR_SIGNAL

--operation mode is normal

C1_CLR_SIGNAL = AMPP_FUNCTION(A1L5, FF1_state[1], BF1_Q[0], VCC);

--SD1_internal_jdo1[34] is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|internal_jdo1[34]

--operation mode is normal

SD1_internal_jdo1[34] = AMPP_FUNCTION(A1L8, SD1_sr[34], VCC, SD1L145);

--SD1_jxdr is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|jxdr

--operation mode is normal

SD1_jxdr = AMPP_FUNCTION(QC2__clk0, SD1_dr_update2, SD1_dr_update1, VCC);

--SD1_internal_jdo1[35] is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|internal_jdo1[35]

--operation mode is normal

SD1_internal_jdo1[35] = AMPP_FUNCTION(A1L8, SD1_sr[35], VCC, SD1L145);

--SD1_ir[0] is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|ir[0]

--operation mode is normal

SD1_ir[0] = AMPP_FUNCTION(A1L5, BF5_Q[0], VCC, SD1L117);

--SD1_ir[1] is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|ir[1]

--operation mode is normal

SD1_ir[1] = AMPP_FUNCTION(A1L5, BF5_Q[1], VCC, SD1L117);

--SD1L190 is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|take_action_ocimem_a~54

--operation mode is normal

SD1L190 = AMPP_FUNCTION(SD1_jxdr, SD1_internal_jdo1[35], SD1_ir[0], SD1_ir[1]);

--SD1L191 is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|take_action_ocimem_a~55

--operation mode is normal

SD1L191 = AMPP_FUNCTION(SD1_internal_jdo1[34], SD1L190);

--S1_M_iw[5] is std_1c20:inst|cpu:the_cpu|M_iw[5]

--operation mode is normal

S1_M_iw[5] = AMPP_FUNCTION(QC2__clk0, S1_E_iw[5], F1_data_out, S1_W_stall);

--S1_M_ctrl_break is std_1c20:inst|cpu:the_cpu|M_ctrl_break

--operation mode is normal

S1_M_ctrl_break = AMPP_FUNCTION(QC2__clk0, S1_E_ctrl_break, F1_data_out, S1_W_stall);

--S1L920 is std_1c20:inst|cpu:the_cpu|hbreak_enabled~274

--operation mode is normal

S1L920 = AMPP_FUNCTION(S1_M_iw[4], S1_M_iw[3], S1_M_iw[5], S1_M_ctrl_break);

--S1L921 is std_1c20:inst|cpu:the_cpu|hbreak_enabled~275

--operation mode is normal

S1L921 = AMPP_FUNCTION(S1_M_valid_from_E, S1L920, S1L1385, RB1L7);

--S1_M_iw[1] is std_1c20:inst|cpu:the_cpu|M_iw[1]

--operation mode is normal

S1_M_iw[1] = AMPP_FUNCTION(QC2__clk0, S1_E_iw[1], F1_data_out, S1_W_stall);

--S1_M_iw[2] is std_1c20:inst|cpu:the_cpu|M_iw[2]

--operation mode is normal

S1_M_iw[2] = AMPP_FUNCTION(QC2__clk0, S1_E_iw[2], F1_data_out, S1_W_stall);

--S1_M_iw[0] is std_1c20:inst|cpu:the_cpu|M_iw[0]

--operation mode is normal

S1_M_iw[0] = AMPP_FUNCTION(QC2__clk0, S1_E_iw[0], F1_data_out, S1_W_stall);

--S1_M_iw[16] is std_1c20:inst|cpu:the_cpu|M_iw[16]

--operation mode is normal

S1_M_iw[16] = AMPP_FUNCTION(QC2__clk0, S1_E_iw[16], F1_data_out, S1_W_stall);

--S1L922 is std_1c20:inst|cpu:the_cpu|hbreak_enabled~276

--operation mode is normal

S1L922 = AMPP_FUNCTION(S1_M_iw[1], S1_M_iw[2], S1_M_iw[0], S1_M_iw[16]);

--S1_M_iw[11] is std_1c20:inst|cpu:the_cpu|M_iw[11]

--operation mode is normal

S1_M_iw[11] = AMPP_FUNCTION(QC2__clk0, S1_E_iw[11], F1_data_out, S1_W_stall);

--S1_M_iw[14] is std_1c20:inst|cpu:the_cpu|M_iw[14]

--operation mode is normal

S1_M_iw[14] = AMPP_FUNCTION(QC2__clk0, S1_E_iw[14], F1_data_out, S1_W_stall);

--S1_M_iw[15] is std_1c20:inst|cpu:the_cpu|M_iw[15]

--operation mode is normal

S1_M_iw[15] = AMPP_FUNCTION(QC2__clk0, S1_E_iw[15], F1_data_out, S1_W_stall);

--S1_M_iw[13] is std_1c20:inst|cpu:the_cpu|M_iw[13]

--operation mode is normal

S1_M_iw[13] = AMPP_FUNCTION(QC2__clk0, S1_E_iw[13], F1_data_out, S1_W_stall);

--S1_M_iw[12] is std_1c20:inst|cpu:the_cpu|M_iw[12]

--operation mode is normal

S1_M_iw[12] = AMPP_FUNCTION(QC2__clk0, S1_E_iw[12], F1_data_out, S1_W_stall);

--S1L923 is std_1c20:inst|cpu:the_cpu|hbreak_enabled~277

--operation mode is normal

S1L923 = AMPP_FUNCTION(S1_M_iw[14], S1_M_iw[15], S1_M_iw[13], S1_M_iw[12]);

--S1L924 is std_1c20:inst|cpu:the_cpu|hbreak_enabled~278

--operation mode is normal

S1L924 = AMPP_FUNCTION(S1L922, S1_M_iw[11], S1L923);

--S1L925 is std_1c20:inst|cpu:the_cpu|hbreak_enabled~279

--operation mode is normal

S1L925 = AMPP_FUNCTION(S1L1385, RB1L7, S1_M_valid_from_E, S1_M_ctrl_break);

--FD1_internal_oci_single_step_mode1 is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_avalon_reg:the_cpu_nios2_avalon_reg|internal_oci_single_step_mode1

--operation mode is normal

FD1_internal_oci_single_step_mode1 = AMPP_FUNCTION(QC2__clk0, S1_M_st_data[3], FD1_internal_oci_single_step_mode1, FD1L14, F1_data_out);

--S1_E_ctrl_ld_signed is std_1c20:inst|cpu:the_cpu|E_ctrl_ld_signed

--operation mode is normal

S1_E_ctrl_ld_signed = AMPP_FUNCTION(QC2__clk0, S1_D_iw[0], S1_D_iw[1], S1_D_iw[2], F1_data_out, S1_W_stall);

--S1_D_pc_plus_one[20] is std_1c20:inst|cpu:the_cpu|D_pc_plus_one[20]

--operation mode is normal

S1_D_pc_plus_one[20] = AMPP_FUNCTION(QC2__clk0, S1L912, F1_data_out, S1_W_stall);

--S1L84 is std_1c20:inst|cpu:the_cpu|Add1~250

--operation mode is arithmetic

S1L84 = AMPP_FUNCTION(S1_D_iw[21], S1_D_pc_plus_one[20], S1L87);

--S1L85 is std_1c20:inst|cpu:the_cpu|Add1~251

--operation mode is arithmetic

S1L85 = AMPP_FUNCTION(S1_D_iw[21], S1_D_pc_plus_one[20], S1L87);

--CD1_q_b[22] is std_1c20:inst|cpu:the_cpu|cpu_register_bank_a_module:cpu_register_bank_a|altsyncram:the_altsyncram|altsyncram_3vd1:auto_generated|q_b[22]

--RAM Block Operation Mode: Simple Dual-Port

--Port A Depth: 32, Port A Width: 1, Port B Depth: 32, Port B Width: 1

--Port A Logical Depth: 32, Port A Logical Width: 32, Port B Logical Depth: 32, Port B Logical Width: 32

--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered

CD1_q_b[22] = AMPP_FUNCTION(GND, GND, QC2__clk0, QC2__clk0, !S1_M_wr_dst_reg, S1_W_stall, S1L1348, S1_M_dst_regnum[0], S1_M_dst_regnum[1], S1_M_dst_regnum[2], S1_M_dst_regnum[3], S1_M_dst_regnum[4], AD1_q_b[27], AD1_q_b[28], AD1_q_b[29], AD1_q_b[30], AD1_q_b[31]);

--S1_W_wr_data[22] is std_1c20:inst|cpu:the_cpu|W_wr_data[22]

--operation mode is normal

S1_W_wr_data[22] = AMPP_FUNCTION(QC2__clk0, S1L1348, F1_data_out, S1_W_stall);

--S1_d_readdata_d1[22] is std_1c20:inst|cpu:the_cpu|d_readdata_d1[22]

--operation mode is normal

S1_d_readdata_d1[22] = AMPP_FUNCTION(QC2__clk0, T1L167, WC1L19, WC1L24, V1_cpu_data_master_requests_cpu_jtag_debug_module, F1_data_out);

--S1_M_ctrl_ld_signed is std_1c20:inst|cpu:the_cpu|M_ctrl_ld_signed

--operation mode is normal

S1_M_ctrl_ld_signed = AMPP_FUNCTION(QC2__clk0, S1_E_ctrl_ld_signed, F1_data_out, S1_W_stall);

--S1_d_readdata_d1[15] is std_1c20:inst|cpu:the_cpu|d_readdata_d1[15]

--operation mode is normal

S1_d_readdata_d1[15] = AMPP_FUNCTION(QC2__clk0, T1L142, WC1L19, WC1L16, V1_cpu_data_master_requests_cpu_jtag_debug_module, F1_data_out);

--S1L172 is std_1c20:inst|cpu:the_cpu|av_sign_bit~0

--operation mode is normal

S1L172 = AMPP_FUNCTION(S1_M_alu_result[0], S1_M_iw[3], S1_M_iw[4]);

--S1_d_readdata_d1[23] is std_1c20:inst|cpu:the_cpu|d_readdata_d1[23]

--operation mode is normal

S1_d_readdata_d1[23] = AMPP_FUNCTION(QC2__clk0, T1L171, WC1L19, WC1L25, V1_cpu_data_master_requests_cpu_jtag_debug_module, F1_data_out);

--S1_d_readdata_d1[7] is std_1c20:inst|cpu:the_cpu|d_readdata_d1[7]

--operation mode is normal

S1_d_readdata_d1[7] = AMPP_FUNCTION(QC2__clk0, T1L91, WC1L19, WC1L8, V1_cpu_data_master_requests_cpu_jtag_debug_module, F1_data_out);

--S1L173 is std_1c20:inst|cpu:the_cpu|av_sign_bit~9

--operation mode is normal

S1L173 = AMPP_FUNCTION(S1L172, S1_d_readdata_d1[23], S1_M_alu_result[1], S1_d_readdata_d1[7]);

--S1_d_readdata_d1[31] is std_1c20:inst|cpu:the_cpu|d_readdata_d1[31]

--operation mode is normal

S1_d_readdata_d1[31] = AMPP_FUNCTION(QC2__clk0, T1L198, WC1L19, WC1L33, V1_cpu_data_master_requests_cpu_jtag_debug_module, F1_data_out);

--S1L174 is std_1c20:inst|cpu:the_cpu|av_sign_bit~10

--operation mode is normal

S1L174 = AMPP_FUNCTION(S1_d_readdata_d1[15], S1L172, S1L173, S1_d_readdata_d1[31]);

--S1L228 is std_1c20:inst|cpu:the_cpu|D_ctrl_hi_imm~101

--operation mode is normal

S1L228 = AMPP_FUNCTION(S1_D_iw[2], S1_D_iw[5], S1L227);

--S1L236 is std_1c20:inst|cpu:the_cpu|D_ctrl_unsigned_lo_imm~163

--operation mode is normal

S1L236 = AMPP_FUNCTION(S1_D_iw[5], S1L767, S1L768, S1_D_iw[4]);

--S1L237 is std_1c20:inst|cpu:the_cpu|D_ctrl_unsigned_lo_imm~164

--operation mode is normal

S1L237 = AMPP_FUNCTION(S1L766, S1_D_iw[4], S1L764, S1_D_iw[5]);

--S1L238 is std_1c20:inst|cpu:the_cpu|D_ctrl_unsigned_lo_imm~165

--operation mode is normal

S1L238 = AMPP_FUNCTION(S1L236, S1L237, S1L234, S1_D_iw[11]);

--S1_E_src2_prelim[22] is std_1c20:inst|cpu:the_cpu|E_src2_prelim[22]

--operation mode is normal

S1_E_src2_prelim[22] = AMPP_FUNCTION(QC2__clk0, DD1_q_b[22], S1_W_wr_data[22], S1L1348, S1L396, F1_data_out, S1L392, S1_W_stall);

--S1_D_pc_plus_one[19] is std_1c20:inst|cpu:the_cpu|D_pc_plus_one[19]

--operation mode is normal

S1_D_pc_plus_one[19] = AMPP_FUNCTION(QC2__clk0, S1L910, F1_data_out, S1_W_stall);

--S1L86 is std_1c20:inst|cpu:the_cpu|Add1~252

--operation mode is arithmetic

S1L86 = AMPP_FUNCTION(S1_D_iw[21], S1_D_pc_plus_one[19], S1L108);

--S1L87 is std_1c20:inst|cpu:the_cpu|Add1~253

--operation mode is arithmetic

S1L87 = AMPP_FUNCTION(S1_D_iw[21], S1_D_pc_plus_one[19], S1L108);

--CD1_q_b[21] is std_1c20:inst|cpu:the_cpu|cpu_register_bank_a_module:cpu_register_bank_a|altsyncram:the_altsyncram|altsyncram_3vd1:auto_generated|q_b[21]

--RAM Block Operation Mode: Simple Dual-Port

--Port A Depth: 32, Port A Width: 1, Port B Depth: 32, Port B Width: 1

--Port A Logical Depth: 32, Port A Logical Width: 32, Port B Logical Depth: 32, Port B Logical Width: 32

--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered

CD1_q_b[21] = AMPP_FUNCTION(GND, GND, QC2__clk0, QC2__clk0, !S1_M_wr_dst_reg, S1_W_stall, S1L1345, S1_M_dst_regnum[0], S1_M_dst_regnum[1], S1_M_dst_regnum[2], S1_M_dst_regnum[3], S1_M_dst_regnum[4], AD1_q_b[27], AD1_q_b[28], AD1_q_b[29], AD1_q_b[30], AD1_q_b[31]);

--S1_W_wr_data[21] is std_1c20:inst|cpu:the_cpu|W_wr_data[21]

--operation mode is normal

S1_W_wr_data[21] = AMPP_FUNCTION(QC2__clk0, S1L1345, F1_data_out, S1_W_stall);

--S1_d_readdata_d1[21] is std_1c20:inst|cpu:the_cpu|d_readdata_d1[21]

--operation mode is normal

S1_d_readdata_d1[21] = AMPP_FUNCTION(QC2__clk0, T1L163, WC1L19, WC1L23, V1_cpu_data_master_requests_cpu_jtag_debug_module, F1_data_out);

--S1_E_src2_prelim[21] is std_1c20:inst|cpu:the_cpu|E_src2_prelim[21]

--operation mode is normal

S1_E_src2_prelim[21] = AMPP_FUNCTION(QC2__clk0, DD1_q_b[21], S1_W_wr_data[21], S1L1345, S1L396, F1_data_out, S1L392, S1_W_stall);

--S1_D_pc_plus_one[17] is std_1c20:inst|cpu:the_cpu|D_pc_plus_one[17]

--operation mode is normal

S1_D_pc_plus_one[17] = AMPP_FUNCTION(QC2__clk0, S1L906, F1_data_out, S1_W_stall);

--S1L88 is std_1c20:inst|cpu:the_cpu|Add1~254

--operation mode is arithmetic

S1L88 = AMPP_FUNCTION(S1_D_iw[21], S1_D_pc_plus_one[17], S1L91);

--S1L89 is std_1c20:inst|cpu:the_cpu|Add1~255

--operation mode is arithmetic

S1L89 = AMPP_FUNCTION(S1_D_iw[21], S1_D_pc_plus_one[17], S1L91);

--CD1_q_b[19] is std_1c20:inst|cpu:the_cpu|cpu_register_bank_a_module:cpu_register_bank_a|altsyncram:the_altsyncram|altsyncram_3vd1:auto_generated|q_b[19]

--RAM Block Operation Mode: Simple Dual-Port

--Port A Depth: 32, Port A Width: 1, Port B Depth: 32, Port B Width: 1

--Port A Logical Depth: 32, Port A Logical Width: 32, Port B Logical Depth: 32, Port B Logical Width: 32

--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered

CD1_q_b[19] = AMPP_FUNCTION(GND, GND, QC2__clk0, QC2__clk0, !S1_M_wr_dst_reg, S1_W_stall, S1L1339, S1_M_dst_regnum[0], S1_M_dst_regnum[1], S1_M_dst_regnum[2], S1_M_dst_regnum[3], S1_M_dst_regnum[4], AD1_q_b[27], AD1_q_b[28], AD1_q_b[29], AD1_q_b[30], AD1_q_b[31]);

--S1_W_wr_data[19] is std_1c20:inst|cpu:the_cpu|W_wr_data[19]

--operation mode is normal

S1_W_wr_data[19] = AMPP_FUNCTION(QC2__clk0, S1L1339, F1_data_out, S1_W_stall);

--S1_E_src2_prelim[19] is std_1c20:inst|cpu:the_cpu|E_src2_prelim[19]

--operation mode is normal

S1_E_src2_prelim[19] = AMPP_FUNCTION(QC2__clk0, DD1_q_b[19], S1_W_wr_data[19], S1L1339, S1L396, F1_data_out, S1L392, S1_W_stall);

--S1_D_pc_plus_one[16] is std_1c20:inst|cpu:the_cpu|D_pc_plus_one[16]

--operation mode is normal

S1_D_pc_plus_one[16] = AMPP_FUNCTION(QC2__clk0, S1L904, F1_data_out, S1_W_stall);

--S1L90 is std_1c20:inst|cpu:the_cpu|Add1~256

--operation mode is arithmetic

S1L90 = AMPP_FUNCTION(S1_D_iw[21], S1_D_pc_plus_one[16], S1L105);

--S1L91 is std_1c20:inst|cpu:the_cpu|Add1~257

--operation mode is arithmetic

S1L91 = AMPP_FUNCTION(S1_D_iw[21], S1_D_pc_plus_one[16], S1L105);

--CD1_q_b[18] is std_1c20:inst|cpu:the_cpu|cpu_register_bank_a_module:cpu_register_bank_a|altsyncram:the_altsyncram|altsyncram_3vd1:auto_generated|q_b[18]

--RAM Block Operation Mode: Simple Dual-Port

--Port A Depth: 32, Port A Width: 1, Port B Depth: 32, Port B Width: 1

--Port A Logical Depth: 32, Port A Logical Width: 32, Port B Logical Depth: 32, Port B Logical Width: 32

--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered

CD1_q_b[18] = AMPP_FUNCTION(GND, GND, QC2__clk0, QC2__clk0, !S1_M_wr_dst_reg, S1_W_stall, S1L1336, S1_M_dst_regnum[0], S1_M_dst_regnum[1], S1_M_dst_regnum[2], S1_M_dst_regnum[3], S1_M_dst_regnum[4], AD1_q_b[27], AD1_q_b[28], AD1_q_b[29], AD1_q_b[30], AD1_q_b[31]);

--S1_W_wr_data[18] is std_1c20:inst|cpu:the_cpu|W_wr_data[18]

--operation mode is normal

S1_W_wr_data[18] = AMPP_FUNCTION(QC2__clk0, S1L1336, F1_data_out, S1_W_stall);

--S1_E_src2_prelim[18] is std_1c20:inst|cpu:the_cpu|E_src2_prelim[18]

--operation mode is normal

S1_E_src2_prelim[18] = AMPP_FUNCTION(QC2__clk0, DD1_q_b[18], S1_W_wr_data[18], S1L1336, S1L396, F1_data_out, S1L392, S1_W_stall);

--S1_D_pc_plus_one[22] is std_1c20:inst|cpu:the_cpu|D_pc_plus_one[22]

--operation mode is normal

S1_D_pc_plus_one[22] = AMPP_FUNCTION(QC2__clk0, S1L916, F1_data_out, S1_W_stall);

--S1L92 is std_1c20:inst|cpu:the_cpu|Add1~258

--operation mode is arithmetic

S1L92 = AMPP_FUNCTION(S1_D_iw[21], S1_D_pc_plus_one[22], S1L110);

--S1L93 is std_1c20:inst|cpu:the_cpu|Add1~259

--operation mode is arithmetic

S1L93 = AMPP_FUNCTION(S1_D_iw[21], S1_D_pc_plus_one[22], S1L110);

--DD1_q_b[24] is std_1c20:inst|cpu:the_cpu|cpu_register_bank_b_module:cpu_register_bank_b|altsyncram:the_altsyncram|altsyncram_4vd1:auto_generated|q_b[24]

--RAM Block Operation Mode: Simple Dual-Port

--Port A Depth: 32, Port A Width: 1, Port B Depth: 32, Port B Width: 1

--Port A Logical Depth: 32, Port A Logical Width: 32, Port B Logical Depth: 32, Port B Logical Width: 32

--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered

DD1_q_b[24] = AMPP_FUNCTION(GND, GND, QC2__clk0, QC2__clk0, !S1_M_wr_dst_reg, S1_W_stall, S1L1354, S1_M_dst_regnum[0], S1_M_dst_regnum[1], S1_M_dst_regnum[2], S1_M_dst_regnum[3], S1_M_dst_regnum[4], AD1_q_b[22], AD1_q_b[23], AD1_q_b[24], AD1_q_b[25], AD1_q_b[26]);

--S1_W_wr_data[24] is std_1c20:inst|cpu:the_cpu|W_wr_data[24]

--operation mode is normal

S1_W_wr_data[24] = AMPP_FUNCTION(QC2__clk0, S1L1354, F1_data_out, S1_W_stall);

--S1_D_iw[25] is std_1c20:inst|cpu:the_cpu|D_iw[25]

--operation mode is normal

S1_D_iw[25] = AMPP_FUNCTION(QC2__clk0, AD1_q_b[25], S1_M_status_reg_pie, S1L1062, S1L845, F1_data_out, S1_W_stall);

--S1_D_iw[26] is std_1c20:inst|cpu:the_cpu|D_iw[26]

--operation mode is normal

S1_D_iw[26] = AMPP_FUNCTION(QC2__clk0, AD1_q_b[26], S1_M_status_reg_pie, S1L1062, S1L845, F1_data_out, S1_W_stall);

--S1_D_iw[24] is std_1c20:inst|cpu:the_cpu|D_iw[24]

--operation mode is normal

S1_D_iw[24] = AMPP_FUNCTION(QC2__clk0, AD1_q_b[24], S1_M_status_reg_pie, S1L1062, S1L845, F1_data_out, S1_W_stall);

--S1L393 is std_1c20:inst|cpu:the_cpu|D_src2_hazard_W~58

--operation mode is normal

S1L393 = AMPP_FUNCTION(S1_W_dst_regnum[2], S1_W_dst_regnum[4], S1_D_iw[26], S1_D_iw[24]);

--S1_D_iw[22] is std_1c20:inst|cpu:the_cpu|D_iw[22]

--operation mode is normal

S1_D_iw[22] = AMPP_FUNCTION(QC2__clk0, AD1_q_b[22], S1_M_status_reg_pie, S1L1062, S1L845, F1_data_out, S1_W_stall);

--S1_D_iw[23] is std_1c20:inst|cpu:the_cpu|D_iw[23]

--operation mode is normal

S1_D_iw[23] = AMPP_FUNCTION(QC2__clk0, AD1_q_b[23], S1_M_status_reg_pie, S1L1062, S1L845, F1_data_out, S1_W_stall);

--S1L394 is std_1c20:inst|cpu:the_cpu|D_src2_hazard_W~59

--operation mode is normal

S1L394 = AMPP_FUNCTION(S1_W_dst_regnum[0], S1_D_iw[22], S1_W_dst_regnum[1], S1_D_iw[23]);

--S1L395 is std_1c20:inst|cpu:the_cpu|D_src2_hazard_W~60

--operation mode is normal

S1L395 = AMPP_FUNCTION(S1_W_dst_regnum[3], S1_D_iw[25], S1L393, S1L394);

--S1L396 is std_1c20:inst|cpu:the_cpu|D_src2_hazard_W~61

--operation mode is normal

S1L396 = AMPP_FUNCTION(S1_W_wr_dst_reg, S1L212, S1L762, S1L395);

--S1L389 is std_1c20:inst|cpu:the_cpu|D_src2_hazard_M~42

--operation mode is normal

S1L389 = AMPP_FUNCTION(S1_M_dst_regnum[2], S1_M_dst_regnum[4], S1_D_iw[26], S1_D_iw[24]);

--S1L390 is std_1c20:inst|cpu:the_cpu|D_src2_hazard_M~43

--operation mode is normal

S1L390 = AMPP_FUNCTION(S1_M_dst_regnum[0], S1_D_iw[22], S1_M_dst_regnum[1], S1_D_iw[23]);

--S1L391 is std_1c20:inst|cpu:the_cpu|D_src2_hazard_M~44

--operation mode is normal

S1L391 = AMPP_FUNCTION(S1_M_dst_regnum[3], S1_D_iw[25], S1L389, S1L390);

--S1L392 is std_1c20:inst|cpu:the_cpu|D_src2_hazard_M~45

--operation mode is normal

S1L392 = AMPP_FUNCTION(S1_M_wr_dst_reg, S1L212, S1L762, S1L391);

--S1L386 is std_1c20:inst|cpu:the_cpu|D_src2_hazard_E~41

--operation mode is normal

S1L386 = AMPP_FUNCTION(S1_E_dst_regnum[1], S1_E_dst_regnum[4], S1_D_iw[26], S1_D_iw[23]);

--S1L387 is std_1c20:inst|cpu:the_cpu|D_src2_hazard_E~42

--operation mode is normal

S1L387 = AMPP_FUNCTION(S1_E_dst_regnum[3], S1_E_dst_regnum[0], S1_D_iw[22], S1_D_iw[25]);

--S1L388 is std_1c20:inst|cpu:the_cpu|D_src2_hazard_E~43

--operation mode is normal

S1L388 = AMPP_FUNCTION(S1L386, S1L387, S1L212, S1L762);

--S1_d_readdata_d1[24] is std_1c20:inst|cpu:the_cpu|d_readdata_d1[24]

--operation mode is normal

S1_d_readdata_d1[24] = AMPP_FUNCTION(QC2__clk0, T1L174, WC1L19, WC1L26, V1_cpu_data_master_requests_cpu_jtag_debug_module, F1_data_out);

--CD1_q_b[24] is std_1c20:inst|cpu:the_cpu|cpu_register_bank_a_module:cpu_register_bank_a|altsyncram:the_altsyncram|altsyncram_3vd1:auto_generated|q_b[24]

--RAM Block Operation Mode: Simple Dual-Port

--Port A Depth: 32, Port A Width: 1, Port B Depth: 32, Port B Width: 1

--Port A Logical Depth: 32, Port A Logical Width: 32, Port B Logical Depth: 32, Port B Logical Width: 32

--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered

CD1_q_b[24] = AMPP_FUNCTION(GND, GND, QC2__clk0, QC2__clk0, !S1_M_wr_dst_reg, S1_W_stall, S1L1354, S1_M_dst_regnum[0], S1_M_dst_regnum[1], S1_M_dst_regnum[2], S1_M_dst_regnum[3], S1_M_dst_regnum[4], AD1_q_b[27], AD1_q_b[28], AD1_q_b[29], AD1_q_b[30], AD1_q_b[31]);

--S1_D_pc_plus_one[14] is std_1c20:inst|cpu:the_cpu|D_pc_plus_one[14]

--operation mode is normal

S1_D_pc_plus_one[14] = AMPP_FUNCTION(QC2__clk0, S1L900, F1_data_out, S1_W_stall);

--S1L94 is std_1c20:inst|cpu:the_cpu|Add1~260

--operation mode is arithmetic

S1L94 = AMPP_FUNCTION(S1_D_iw[21], S1_D_pc_plus_one[14], S1L97);

--S1L95 is std_1c20:inst|cpu:the_cpu|Add1~261

--operation mode is arithmetic

S1L95 = AMPP_FUNCTION(S1_D_iw[21], S1_D_pc_plus_one[14], S1L97);

--CD1_q_b[16] is std_1c20:inst|cpu:the_cpu|cpu_register_bank_a_module:cpu_register_bank_a|altsyncram:the_altsyncram|altsyncram_3vd1:auto_generated|q_b[16]

--RAM Block Operation Mode: Simple Dual-Port

--Port A Depth: 32, Port A Width: 1, Port B Depth: 32, Port B Width: 1

--Port A Logical Depth: 32, Port A Logical Width: 32, Port B Logical Depth: 32, Port B Logical Width: 32

--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered

CD1_q_b[16] = AMPP_FUNCTION(GND, GND, QC2__clk0, QC2__clk0, !S1_M_wr_dst_reg, S1_W_stall, S1L1330, S1_M_dst_regnum[0], S1_M_dst_regnum[1], S1_M_dst_regnum[2], S1_M_dst_regnum[3], S1_M_dst_regnum[4], AD1_q_b[27], AD1_q_b[28], AD1_q_b[29], AD1_q_b[30], AD1_q_b[31]);

--S1_W_wr_data[16] is std_1c20:inst|cpu:the_cpu|W_wr_data[16]

--operation mode is normal

S1_W_wr_data[16] = AMPP_FUNCTION(QC2__clk0, S1L1330, F1_data_out, S1_W_stall);

--S1_d_readdata_d1[16] is std_1c20:inst|cpu:the_cpu|d_readdata_d1[16]

--operation mode is normal

S1_d_readdata_d1[16] = AMPP_FUNCTION(QC2__clk0, T1L146, WC1L19, WC1L17, V1_cpu_data_master_requests_cpu_jtag_debug_module, F1_data_out);

--S1_E_src2_prelim[16] is std_1c20:inst|cpu:the_cpu|E_src2_prelim[16]

--operation mode is normal

S1_E_src2_prelim[16] = AMPP_FUNCTION(QC2__clk0, DD1_q_b[16], S1_W_wr_data[16], S1L1330, S1L396, F1_data_out, S1L392, S1_W_stall);

--S1_D_pc_plus_one[13] is std_1c20:inst|cpu:the_cpu|D_pc_plus_one[13]

--operation mode is normal

S1_D_pc_plus_one[13] = AMPP_FUNCTION(QC2__clk0, S1L898, F1_data_out, S1_W_stall);

--S1L96 is std_1c20:inst|cpu:the_cpu|Add1~262

--operation mode is arithmetic

S1L96 = AMPP_FUNCTION(S1_D_iw[21], S1_D_pc_plus_one[13], S1L99);

--S1L97 is std_1c20:inst|cpu:the_cpu|Add1~263

--operation mode is arithmetic

S1L97 = AMPP_FUNCTION(S1_D_iw[21], S1_D_pc_plus_one[13], S1L99);

--DD1_q_b[15] is std_1c20:inst|cpu:the_cpu|cpu_register_bank_b_module:cpu_register_bank_b|altsyncram:the_altsyncram|altsyncram_4vd1:auto_generated|q_b[15]

--RAM Block Operation Mode: Simple Dual-Port

--Port A Depth: 32, Port A Width: 1, Port B Depth: 32, Port B Width: 1

--Port A Logical Depth: 32, Port A Logical Width: 32, Port B Logical Depth: 32, Port B Logical Width: 32

--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered

DD1_q_b[15] = AMPP_FUNCTION(GND, GND, QC2__clk0, QC2__clk0, !S1_M_wr_dst_reg, S1_W_stall, S1L1327, S1_M_dst_regnum[0], S1_M_dst_regnum[1], S1_M_dst_regnum[2], S1_M_dst_regnum[3], S1_M_dst_regnum[4], AD1_q_b[22], AD1_q_b[23], AD1_q_b[24], AD1_q_b[25], AD1_q_b[26]);

--S1_W_wr_data[15] is std_1c20:inst|cpu:the_cpu|W_wr_data[15]

--operation mode is normal

S1_W_wr_data[15] = AMPP_FUNCTION(QC2__clk0, S1L1327, F1_data_out, S1_W_stall);

--S1_av_fill_bit is std_1c20:inst|cpu:the_cpu|av_fill_bit

--operation mode is normal

S1_av_fill_bit = AMPP_FUNCTION(S1_M_ctrl_ld_signed, S1L174);

--S1L778 is std_1c20:inst|cpu:the_cpu|Equal145~6

--operation mode is normal

S1L778 = AMPP_FUNCTION(S1_M_iw[4], S1_M_iw[3]);

--CD1_q_b[15] is std_1c20:inst|cpu:the_cpu|cpu_register_bank_a_module:cpu_register_bank_a|altsyncram:the_altsyncram|altsyncram_3vd1:auto_generated|q_b[15]

--RAM Block Operation Mode: Simple Dual-Port

--Port A Depth: 32, Port A Width: 1, Port B Depth: 32, Port B Width: 1

--Port A Logical Depth: 32, Port A Logical Width: 32, Port B Logical Depth: 32, Port B Logical Width: 32

--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered

CD1_q_b[15] = AMPP_FUNCTION(GND, GND, QC2__clk0, QC2__clk0, !S1_M_wr_dst_reg, S1_W_stall, S1L1327, S1_M_dst_regnum[0], S1_M_dst_regnum[1], S1_M_dst_regnum[2], S1_M_dst_regnum[3], S1_M_dst_regnum[4], AD1_q_b[27], AD1_q_b[28], AD1_q_b[29], AD1_q_b[30], AD1_q_b[31]);

--S1_D_pc_plus_one[12] is std_1c20:inst|cpu:the_cpu|D_pc_plus_one[12]

--operation mode is normal

S1_D_pc_plus_one[12] = AMPP_FUNCTION(QC2__clk0, S1L896, F1_data_out, S1_W_stall);

--S1L98 is std_1c20:inst|cpu:the_cpu|Add1~264

--operation mode is arithmetic

S1L98 = AMPP_FUNCTION(S1_D_iw[20], S1_D_pc_plus_one[12], S1L101);

--S1L99 is std_1c20:inst|cpu:the_cpu|Add1~265

--operation mode is arithmetic

S1L99 = AMPP_FUNCTION(S1_D_iw[20], S1_D_pc_plus_one[12], S1L101);

--S1_D_iw[20] is std_1c20:inst|cpu:the_cpu|D_iw[20]

--operation mode is normal

S1_D_iw[20] = AMPP_FUNCTION(QC2__clk0, AD1_q_b[20], S1L845, S1_M_status_reg_pie, S1L1062, F1_data_out, S1_W_stall);

--DD1_q_b[14] is std_1c20:inst|cpu:the_cpu|cpu_register_bank_b_module:cpu_register_bank_b|altsyncram:the_altsyncram|altsyncram_4vd1:auto_generated|q_b[14]

--RAM Block Operation Mode: Simple Dual-Port

--Port A Depth: 32, Port A Width: 1, Port B Depth: 32, Port B Width: 1

--Port A Logical Depth: 32, Port A Logical Width: 32, Port B Logical Depth: 32, Port B Logical Width: 32

--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered

DD1_q_b[14] = AMPP_FUNCTION(GND, GND, QC2__clk0, QC2__clk0, !S1_M_wr_dst_reg, S1_W_stall, S1L1324, S1_M_dst_regnum[0], S1_M_dst_regnum[1], S1_M_dst_regnum[2], S1_M_dst_regnum[3], S1_M_dst_regnum[4], AD1_q_b[22], AD1_q_b[23], AD1_q_b[24], AD1_q_b[25], AD1_q_b[26]);

--S1_W_wr_data[14] is std_1c20:inst|cpu:the_cpu|W_wr_data[14]

--operation mode is normal

S1_W_wr_data[14] = AMPP_FUNCTION(QC2__clk0, S1L1324, F1_data_out, S1_W_stall);

--S1_d_readdata_d1[14] is std_1c20:inst|cpu:the_cpu|d_readdata_d1[14]

--operation mode is normal

S1_d_readdata_d1[14] = AMPP_FUNCTION(QC2__clk0, T1L138, WC1L19, WC1L15, V1_cpu_data_master_requests_cpu_jtag_debug_module, F1_data_out);

--S1_d_readdata_d1[30] is std_1c20:inst|cpu:the_cpu|d_readdata_d1[30]

--operation mode is normal

S1_d_readdata_d1[30] = AMPP_FUNCTION(QC2__clk0, T1L195, WC1L19, WC1L32, V1_cpu_data_master_requests_cpu_jtag_debug_module, F1_data_out);

--CD1_q_b[14] is std_1c20:inst|cpu:the_cpu|cpu_register_bank_a_module:cpu_register_bank_a|altsyncram:the_altsyncram|altsyncram_3vd1:auto_generated|q_b[14]

--RAM Block Operation Mode: Simple Dual-Port

--Port A Depth: 32, Port A Width: 1, Port B Depth: 32, Port B Width: 1

--Port A Logical Depth: 32, Port A Logical Width: 32, Port B Logical Depth: 32, Port B Logical Width: 32

--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered

CD1_q_b[14] = AMPP_FUNCTION(GND, GND, QC2__clk0, QC2__clk0, !S1_M_wr_dst_reg, S1_W_stall, S1L1324, S1_M_dst_regnum[0], S1_M_dst_regnum[1], S1_M_dst_regnum[2], S1_M_dst_regnum[3], S1_M_dst_regnum[4], AD1_q_b[27], AD1_q_b[28], AD1_q_b[29], AD1_q_b[30], AD1_q_b[31]);

--S1_D_pc_plus_one[11] is std_1c20:inst|cpu:the_cpu|D_pc_plus_one[11]

--operation mode is normal

S1_D_pc_plus_one[11] = AMPP_FUNCTION(QC2__clk0, S1L894, F1_data_out, S1_W_stall);

--S1L100 is std_1c20:inst|cpu:the_cpu|Add1~266

--operation mode is arithmetic

S1L100 = AMPP_FUNCTION(S1_D_iw[19], S1_D_pc_plus_one[11], S1L103);

--S1L101 is std_1c20:inst|cpu:the_cpu|Add1~267

--operation mode is arithmetic

S1L101 = AMPP_FUNCTION(S1_D_iw[19], S1_D_pc_plus_one[11], S1L103);

--S1_D_iw[19] is std_1c20:inst|cpu:the_cpu|D_iw[19]

--operation mode is normal

S1_D_iw[19] = AMPP_FUNCTION(QC2__clk0, AD1_q_b[19], S1L845, S1_M_status_reg_pie, S1L1062, F1_data_out, S1_W_stall);

--DD1_q_b[13] is std_1c20:inst|cpu:the_cpu|cpu_register_bank_b_module:cpu_register_bank_b|altsyncram:the_altsyncram|altsyncram_4vd1:auto_generated|q_b[13]

--RAM Block Operation Mode: Simple Dual-Port

--Port A Depth: 32, Port A Width: 1, Port B Depth: 32, Port B Width: 1

--Port A Logical Depth: 32, Port A Logical Width: 32, Port B Logical Depth: 32, Port B Logical Width: 32

--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered

DD1_q_b[13] = AMPP_FUNCTION(GND, GND, QC2__clk0, QC2__clk0, !S1_M_wr_dst_reg, S1_W_stall, S1L1321, S1_M_dst_regnum[0], S1_M_dst_regnum[1], S1_M_dst_regnum[2], S1_M_dst_regnum[3], S1_M_dst_regnum[4], AD1_q_b[22], AD1_q_b[23], AD1_q_b[24], AD1_q_b[25], AD1_q_b[26]);

--S1_W_wr_data[13] is std_1c20:inst|cpu:the_cpu|W_wr_data[13]

--operation mode is normal

S1_W_wr_data[13] = AMPP_FUNCTION(QC2__clk0, S1L1321, F1_data_out, S1_W_stall);

--S1_d_readdata_d1[13] is std_1c20:inst|cpu:the_cpu|d_readdata_d1[13]

--operation mode is normal

S1_d_readdata_d1[13] = AMPP_FUNCTION(QC2__clk0, T1L132, WC1L19, WC1L14, V1_cpu_data_master_requests_cpu_jtag_debug_module, F1_data_out);

--S1_d_readdata_d1[29] is std_1c20:inst|cpu:the_cpu|d_readdata_d1[29]

--operation mode is normal

S1_d_readdata_d1[29] = AMPP_FUNCTION(QC2__clk0, T1L190, WC1L19, WC1L31, V1_cpu_data_master_requests_cpu_jtag_debug_module, F1_data_out);

--CD1_q_b[13] is std_1c20:inst|cpu:the_cpu|cpu_register_bank_a_module:cpu_register_bank_a|altsyncram:the_altsyncram|altsyncram_3vd1:auto_generated|q_b[13]

--RAM Block Operation Mode: Simple Dual-Port

--Port A Depth: 32, Port A Width: 1, Port B Depth: 32, Port B Width: 1

--Port A Logical Depth: 32, Port A Logical Width: 32, Port B Logical Depth: 32, Port B Logical Width: 32

--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered

CD1_q_b[13] = AMPP_FUNCTION(GND, GND, QC2__clk0, QC2__clk0, !S1_M_wr_dst_reg, S1_W_stall, S1L1321, S1_M_dst_regnum[0], S1_M_dst_regnum[1], S1_M_dst_regnum[2], S1_M_dst_regnum[3], S1_M_dst_regnum[4], AD1_q_b[27], AD1_q_b[28], AD1_q_b[29], AD1_q_b[30], AD1_q_b[31]);

--S1_D_pc_plus_one[10] is std_1c20:inst|cpu:the_cpu|D_pc_plus_one[10]

--operation mode is normal

S1_D_pc_plus_one[10] = AMPP_FUNCTION(QC2__clk0, S1L892, F1_data_out, S1_W_stall);

--S1L102 is std_1c20:inst|cpu:the_cpu|Add1~268

--operation mode is arithmetic

S1L102 = AMPP_FUNCTION(S1_D_iw[18], S1_D_pc_plus_one[10], S1L112);

--S1L103 is std_1c20:inst|cpu:the_cpu|Add1~269

--operation mode is arithmetic

S1L103 = AMPP_FUNCTION(S1_D_iw[18], S1_D_pc_plus_one[10], S1L112);

--S1_D_iw[18] is std_1c20:inst|cpu:the_cpu|D_iw[18]

--operation mode is normal

S1_D_iw[18] = AMPP_FUNCTION(QC2__clk0, S1L845, AD1_q_b[18], S1_M_status_reg_pie, S1L1062, F1_data_out, S1_W_stall);

--DD1_q_b[12] is std_1c20:inst|cpu:the_cpu|cpu_register_bank_b_module:cpu_register_bank_b|altsyncram:the_altsyncram|altsyncram_4vd1:auto_generated|q_b[12]

--RAM Block Operation Mode: Simple Dual-Port

--Port A Depth: 32, Port A Width: 1, Port B Depth: 32, Port B Width: 1

--Port A Logical Depth: 32, Port A Logical Width: 32, Port B Logical Depth: 32, Port B Logical Width: 32

--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered

DD1_q_b[12] = AMPP_FUNCTION(GND, GND, QC2__clk0, QC2__clk0, !S1_M_wr_dst_reg, S1_W_stall, S1L1318, S1_M_dst_regnum[0], S1_M_dst_regnum[1], S1_M_dst_regnum[2], S1_M_dst_regnum[3], S1_M_dst_regnum[4], AD1_q_b[22], AD1_q_b[23], AD1_q_b[24], AD1_q_b[25], AD1_q_b[26]);

--S1_W_wr_data[12] is std_1c20:inst|cpu:the_cpu|W_wr_data[12]

--operation mode is normal

S1_W_wr_data[12] = AMPP_FUNCTION(QC2__clk0, S1L1318, F1_data_out, S1_W_stall);

--S1_d_readdata_d1[12] is std_1c20:inst|cpu:the_cpu|d_readdata_d1[12]

--operation mode is normal

S1_d_readdata_d1[12] = AMPP_FUNCTION(QC2__clk0, T1L126, WC1L19, WC1L13, V1_cpu_data_master_requests_cpu_jtag_debug_module, F1_data_out);

--S1_d_readdata_d1[28] is std_1c20:inst|cpu:the_cpu|d_readdata_d1[28]

--operation mode is normal

S1_d_readdata_d1[28] = AMPP_FUNCTION(QC2__clk0, T1L187, WC1L19, WC1L30, V1_cpu_data_master_requests_cpu_jtag_debug_module, F1_data_out);

--CD1_q_b[12] is std_1c20:inst|cpu:the_cpu|cpu_register_bank_a_module:cpu_register_bank_a|altsyncram:the_altsyncram|altsyncram_3vd1:auto_generated|q_b[12]

--RAM Block Operation Mode: Simple Dual-Port

--Port A Depth: 32, Port A Width: 1, Port B Depth: 32, Port B Width: 1

--Port A Logical Depth: 32, Port A Logical Width: 32, Port B Logical Depth: 32, Port B Logical Width: 32

--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered

CD1_q_b[12] = AMPP_FUNCTION(GND, GND, QC2__clk0, QC2__clk0, !S1_M_wr_dst_reg, S1_W_stall, S1L1318, S1_M_dst_regnum[0], S1_M_dst_regnum[1], S1_M_dst_regnum[2], S1_M_dst_regnum[3], S1_M_dst_regnum[4], AD1_q_b[27], AD1_q_b[28], AD1_q_b[29], AD1_q_b[30], AD1_q_b[31]);

--S1_D_pc_plus_one[15] is std_1c20:inst|cpu:the_cpu|D_pc_plus_one[15]

--operation mode is normal

S1_D_pc_plus_one[15] = AMPP_FUNCTION(QC2__clk0, S1L902, F1_data_out, S1_W_stall);

--S1L104 is std_1c20:inst|cpu:the_cpu|Add1~270

--operation mode is arithmetic

S1L104 = AMPP_FUNCTION(S1_D_iw[21], S1_D_pc_plus_one[15], S1L95);

--S1L105 is std_1c20:inst|cpu:the_cpu|Add1~271

--operation mode is arithmetic

S1L105 = AMPP_FUNCTION(S1_D_iw[21], S1_D_pc_plus_one[15], S1L95);

--CD1_q_b[17] is std_1c20:inst|cpu:the_cpu|cpu_register_bank_a_module:cpu_register_bank_a|altsyncram:the_altsyncram|altsyncram_3vd1:auto_generated|q_b[17]

--RAM Block Operation Mode: Simple Dual-Port

--Port A Depth: 32, Port A Width: 1, Port B Depth: 32, Port B Width: 1

--Port A Logical Depth: 32, Port A Logical Width: 32, Port B Logical Depth: 32, Port B Logical Width: 32

--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered

CD1_q_b[17] = AMPP_FUNCTION(GND, GND, QC2__clk0, QC2__clk0, !S1_M_wr_dst_reg, S1_W_stall, S1L1333, S1_M_dst_regnum[0], S1_M_dst_regnum[1], S1_M_dst_regnum[2], S1_M_dst_regnum[3], S1_M_dst_regnum[4], AD1_q_b[27], AD1_q_b[28], AD1_q_b[29], AD1_q_b[30], AD1_q_b[31]);

--S1_W_wr_data[17] is std_1c20:inst|cpu:the_cpu|W_wr_data[17]

--operation mode is normal

S1_W_wr_data[17] = AMPP_FUNCTION(QC2__clk0, S1L1333, F1_data_out, S1_W_stall);

--S1_d_readdata_d1[17] is std_1c20:inst|cpu:the_cpu|d_readdata_d1[17]

--operation mode is normal

S1_d_readdata_d1[17] = AMPP_FUNCTION(QC2__clk0, T1L149, WC1L19, WC1L18, V1_cpu_data_master_requests_cpu_jtag_debug_module, F1_data_out);

--S1_E_src2_prelim[17] is std_1c20:inst|cpu:the_cpu|E_src2_prelim[17]

--operation mode is normal

S1_E_src2_prelim[17] = AMPP_FUNCTION(QC2__clk0, DD1_q_b[17], S1_W_wr_data[17], S1L1333, S1L396, F1_data_out, S1L392, S1_W_stall);

--S1_D_pc_plus_one[23] is std_1c20:inst|cpu:the_cpu|D_pc_plus_one[23]

--operation mode is normal

S1_D_pc_plus_one[23] = AMPP_FUNCTION(QC2__clk0, S1L918, F1_data_out, S1_W_stall);

--S1L106 is std_1c20:inst|cpu:the_cpu|Add1~272

--operation mode is normal

S1L106 = AMPP_FUNCTION(S1_D_iw[21], S1_D_pc_plus_one[23], S1L93);

--DD1_q_b[25] is std_1c20:inst|cpu:the_cpu|cpu_register_bank_b_module:cpu_register_bank_b|altsyncram:the_altsyncram|altsyncram_4vd1:auto_generated|q_b[25]

--RAM Block Operation Mode: Simple Dual-Port

--Port A Depth: 32, Port A Width: 1, Port B Depth: 32, Port B Width: 1

--Port A Logical Depth: 32, Port A Logical Width: 32, Port B Logical Depth: 32, Port B Logical Width: 32

--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered

DD1_q_b[25] = AMPP_FUNCTION(GND, GND, QC2__clk0, QC2__clk0, !S1_M_wr_dst_reg, S1_W_stall, S1L1357, S1_M_dst_regnum[0], S1_M_dst_regnum[1], S1_M_dst_regnum[2], S1_M_dst_regnum[3], S1_M_dst_regnum[4], AD1_q_b[22], AD1_q_b[23], AD1_q_b[24], AD1_q_b[25], AD1_q_b[26]);

--S1_W_wr_data[25] is std_1c20:inst|cpu:the_cpu|W_wr_data[25]

--operation mode is normal

S1_W_wr_data[25] = AMPP_FUNCTION(QC2__clk0, S1L1357, F1_data_out, S1_W_stall);

--S1_M_shift_rot_result[26] is std_1c20:inst|cpu:the_cpu|M_shift_rot_result[26]

--operation mode is normal

S1_M_shift_rot_result[26] = AMPP_FUNCTION(QC2__clk0, S1_M_shift_rot_result[25], S1_M_shift_rot_result[27], S1L595, S1_M_ctrl_shift_rot_right, F1_data_out, !S1_M_shift_rot_stall);

--S1_d_readdata_d1[25] is std_1c20:inst|cpu:the_cpu|d_readdata_d1[25]

--operation mode is normal

S1_d_readdata_d1[25] = AMPP_FUNCTION(QC2__clk0, T1L177, WC1L19, WC1L27, V1_cpu_data_master_requests_cpu_jtag_debug_module, F1_data_out);

--CD1_q_b[25] is std_1c20:inst|cpu:the_cpu|cpu_register_bank_a_module:cpu_register_bank_a|altsyncram:the_altsyncram|altsyncram_3vd1:auto_generated|q_b[25]

--RAM Block Operation Mode: Simple Dual-Port

--Port A Depth: 32, Port A Width: 1, Port B Depth: 32, Port B Width: 1

--Port A Logical Depth: 32, Port A Logical Width: 32, Port B Logical Depth: 32, Port B Logical Width: 32

--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered

CD1_q_b[25] = AMPP_FUNCTION(GND, GND, QC2__clk0, QC2__clk0, !S1_M_wr_dst_reg, S1_W_stall, S1L1357, S1_M_dst_regnum[0], S1_M_dst_regnum[1], S1_M_dst_regnum[2], S1_M_dst_regnum[3], S1_M_dst_regnum[4], AD1_q_b[27], AD1_q_b[28], AD1_q_b[29], AD1_q_b[30], AD1_q_b[31]);

--S1_D_pc_plus_one[18] is std_1c20:inst|cpu:the_cpu|D_pc_plus_one[18]

--operation mode is normal

S1_D_pc_plus_one[18] = AMPP_FUNCTION(QC2__clk0, S1L908, F1_data_out, S1_W_stall);

--S1L107 is std_1c20:inst|cpu:the_cpu|Add1~274

--operation mode is arithmetic

S1L107 = AMPP_FUNCTION(S1_D_iw[21], S1_D_pc_plus_one[18], S1L89);

--S1L108 is std_1c20:inst|cpu:the_cpu|Add1~275

--operation mode is arithmetic

S1L108 = AMPP_FUNCTION(S1_D_iw[21], S1_D_pc_plus_one[18], S1L89);

--CD1_q_b[20] is std_1c20:inst|cpu:the_cpu|cpu_register_bank_a_module:cpu_register_bank_a|altsyncram:the_altsyncram|altsyncram_3vd1:auto_generated|q_b[20]

--RAM Block Operation Mode: Simple Dual-Port

--Port A Depth: 32, Port A Width: 1, Port B Depth: 32, Port B Width: 1

--Port A Logical Depth: 32, Port A Logical Width: 32, Port B Logical Depth: 32, Port B Logical Width: 32

--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered

CD1_q_b[20] = AMPP_FUNCTION(GND, GND, QC2__clk0, QC2__clk0, !S1_M_wr_dst_reg, S1_W_stall, S1L1342, S1_M_dst_regnum[0], S1_M_dst_regnum[1], S1_M_dst_regnum[2], S1_M_dst_regnum[3], S1_M_dst_regnum[4], AD1_q_b[27], AD1_q_b[28], AD1_q_b[29], AD1_q_b[30], AD1_q_b[31]);

--S1_W_wr_data[20] is std_1c20:inst|cpu:the_cpu|W_wr_data[20]

--operation mode is normal

S1_W_wr_data[20] = AMPP_FUNCTION(QC2__clk0, S1L1342, F1_data_out, S1_W_stall);

--S1_d_readdata_d1[20] is std_1c20:inst|cpu:the_cpu|d_readdata_d1[20]

--operation mode is normal

S1_d_readdata_d1[20] = AMPP_FUNCTION(QC2__clk0, T1L160, WC1L19, WC1L22, V1_cpu_data_master_requests_cpu_jtag_debug_module, F1_data_out);

--S1_D_iw[10] is std_1c20:inst|cpu:the_cpu|D_iw[10]

--operation mode is normal

S1_D_iw[10] = AMPP_FUNCTION(QC2__clk0, AD1_q_b[10], S1_M_status_reg_pie, S1L1062, S1L845, F1_data_out, S1_W_stall);

--S1_E_src2_prelim[20] is std_1c20:inst|cpu:the_cpu|E_src2_prelim[20]

--operation mode is normal

S1_E_src2_prelim[20] = AMPP_FUNCTION(QC2__clk0, DD1_q_b[20], S1_W_wr_data[20], S1L1342, S1L396, F1_data_out, S1L392, S1_W_stall);

--S1_D_pc_plus_one[21] is std_1c20:inst|cpu:the_cpu|D_pc_plus_one[21]

--operation mode is normal

S1_D_pc_plus_one[21] = AMPP_FUNCTION(QC2__clk0, S1L914, F1_data_out, S1_W_stall);

--S1L109 is std_1c20:inst|cpu:the_cpu|Add1~276

--operation mode is arithmetic

S1L109 = AMPP_FUNCTION(S1_D_iw[21], S1_D_pc_plus_one[21], S1L85);

--S1L110 is std_1c20:inst|cpu:the_cpu|Add1~277

--operation mode is arithmetic

S1L110 = AMPP_FUNCTION(S1_D_iw[21], S1_D_pc_plus_one[21], S1L85);

--CD1_q_b[23] is std_1c20:inst|cpu:the_cpu|cpu_register_bank_a_module:cpu_register_bank_a|altsyncram:the_altsyncram|altsyncram_3vd1:auto_generated|q_b[23]

--RAM Block Operation Mode: Simple Dual-Port

--Port A Depth: 32, Port A Width: 1, Port B Depth: 32, Port B Width: 1

--Port A Logical Depth: 32, Port A Logical Width: 32, Port B Logical Depth: 32, Port B Logical Width: 32

--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered

CD1_q_b[23] = AMPP_FUNCTION(GND, GND, QC2__clk0, QC2__clk0, !S1_M_wr_dst_reg, S1_W_stall, S1L1351, S1_M_dst_regnum[0], S1_M_dst_regnum[1], S1_M_dst_regnum[2], S1_M_dst_regnum[3], S1_M_dst_regnum[4], AD1_q_b[27], AD1_q_b[28], AD1_q_b[29], AD1_q_b[30], AD1_q_b[31]);

--S1_W_wr_data[23] is std_1c20:inst|cpu:the_cpu|W_wr_data[23]

--operation mode is normal

S1_W_wr_data[23] = AMPP_FUNCTION(QC2__clk0, S1L1351, F1_data_out, S1_W_stall);

--S1_E_src2_prelim[23] is std_1c20:inst|cpu:the_cpu|E_src2_prelim[23]

--operation mode is normal

S1_E_src2_prelim[23] = AMPP_FUNCTION(QC2__clk0, DD1_q_b[23], S1_W_wr_data[23], S1L1351, S1L396, F1_data_out, S1L392, S1_W_stall);

--S1_D_pc_plus_one[9] is std_1c20:inst|cpu:the_cpu|D_pc_plus_one[9]

--operation mode is normal

S1_D_pc_plus_one[9] = AMPP_FUNCTION(QC2__clk0, S1L890, F1_data_out, S1_W_stall);

--S1_D_br_taken_waddr_partial[9] is std_1c20:inst|cpu:the_cpu|D_br_taken_waddr_partial[9]

--operation mode is arithmetic

S1_D_br_taken_waddr_partial[9] = AMPP_FUNCTION(QC2__clk0, AD1_q_b[17], S1L890, F1_data_out, S1_W_stall, S1L194);

--S1L196 is std_1c20:inst|cpu:the_cpu|D_br_taken_waddr_partial[9]~57

--operation mode is arithmetic

S1L196 = AMPP_FUNCTION(AD1_q_b[17], S1L890, S1L194);

--S1_D_iw[17] is std_1c20:inst|cpu:the_cpu|D_iw[17]

--operation mode is normal

S1_D_iw[17] = AMPP_FUNCTION(QC2__clk0, AD1_q_b[17], S1_M_status_reg_pie, S1L1062, S1L845, F1_data_out, S1_W_stall);

--DD1_q_b[11] is std_1c20:inst|cpu:the_cpu|cpu_register_bank_b_module:cpu_register_bank_b|altsyncram:the_altsyncram|altsyncram_4vd1:auto_generated|q_b[11]

--RAM Block Operation Mode: Simple Dual-Port

--Port A Depth: 32, Port A Width: 1, Port B Depth: 32, Port B Width: 1

--Port A Logical Depth: 32, Port A Logical Width: 32, Port B Logical Depth: 32, Port B Logical Width: 32

--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered

DD1_q_b[11] = AMPP_FUNCTION(GND, GND, QC2__clk0, QC2__clk0, !S1_M_wr_dst_reg, S1_W_stall, S1L1315, S1_M_dst_regnum[0], S1_M_dst_regnum[1], S1_M_dst_regnum[2], S1_M_dst_regnum[3], S1_M_dst_regnum[4], AD1_q_b[22], AD1_q_b[23], AD1_q_b[24], AD1_q_b[25], AD1_q_b[26]);

--S1_W_wr_data[11] is std_1c20:inst|cpu:the_cpu|W_wr_data[11]

--operation mode is normal

S1_W_wr_data[11] = AMPP_FUNCTION(QC2__clk0, S1L1315, F1_data_out, S1_W_stall);

--S1_d_readdata_d1[11] is std_1c20:inst|cpu:the_cpu|d_readdata_d1[11]

--operation mode is normal

S1_d_readdata_d1[11] = AMPP_FUNCTION(QC2__clk0, T1L119, WC1L19, WC1L12, V1_cpu_data_master_requests_cpu_jtag_debug_module, F1_data_out);

--S1_d_readdata_d1[27] is std_1c20:inst|cpu:the_cpu|d_readdata_d1[27]

--operation mode is normal

S1_d_readdata_d1[27] = AMPP_FUNCTION(QC2__clk0, T1L184, WC1L19, WC1L29, V1_cpu_data_master_requests_cpu_jtag_debug_module, F1_data_out);

--CD1_q_b[11] is std_1c20:inst|cpu:the_cpu|cpu_register_bank_a_module:cpu_register_bank_a|altsyncram:the_altsyncram|altsyncram_3vd1:auto_generated|q_b[11]

--RAM Block Operation Mode: Simple Dual-Port

--Port A Depth: 32, Port A Width: 1, Port B Depth: 32, Port B Width: 1

--Port A Logical Depth: 32, Port A Logical Width: 32, Port B Logical Depth: 32, Port B Logical Width: 32

--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered

CD1_q_b[11] = AMPP_FUNCTION(GND, GND, QC2__clk0, QC2__clk0, !S1_M_wr_dst_reg, S1_W_stall, S1L1315, S1_M_dst_regnum[0], S1_M_dst_regnum[1], S1_M_dst_regnum[2], S1_M_dst_regnum[3], S1_M_dst_regnum[4], AD1_q_b[27], AD1_q_b[28], AD1_q_b[29], AD1_q_b[30], AD1_q_b[31]);

--S1_D_pc_plus_one[8] is std_1c20:inst|cpu:the_cpu|D_pc_plus_one[8]

--operation mode is normal

S1_D_pc_plus_one[8] = AMPP_FUNCTION(QC2__clk0, S1L888, F1_data_out, S1_W_stall);

--S1_D_br_taken_waddr_partial[8] is std_1c20:inst|cpu:the_cpu|D_br_taken_waddr_partial[8]

--operation mode is arithmetic

S1_D_br_taken_waddr_partial[8] = AMPP_FUNCTION(QC2__clk0, AD1_q_b[16], S1L888, F1_data_out, S1_W_stall, S1L192);

--S1L194 is std_1c20:inst|cpu:the_cpu|D_br_taken_waddr_partial[8]~58

--operation mode is arithmetic

S1L194 = AMPP_FUNCTION(AD1_q_b[16], S1L888, S1L192);

--DD1_q_b[10] is std_1c20:inst|cpu:the_cpu|cpu_register_bank_b_module:cpu_register_bank_b|altsyncram:the_altsyncram|altsyncram_4vd1:auto_generated|q_b[10]

--RAM Block Operation Mode: Simple Dual-Port

--Port A Depth: 32, Port A Width: 1, Port B Depth: 32, Port B Width: 1

--Port A Logical Depth: 32, Port A Logical Width: 32, Port B Logical Depth: 32, Port B Logical Width: 32

--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered

DD1_q_b[10] = AMPP_FUNCTION(GND, GND, QC2__clk0, QC2__clk0, !S1_M_wr_dst_reg, S1_W_stall, S1L1312, S1_M_dst_regnum[0], S1_M_dst_regnum[1], S1_M_dst_regnum[2], S1_M_dst_regnum[3], S1_M_dst_regnum[4], AD1_q_b[22], AD1_q_b[23], AD1_q_b[24], AD1_q_b[25], AD1_q_b[26]);

--S1_W_wr_data[10] is std_1c20:inst|cpu:the_cpu|W_wr_data[10]

--operation mode is normal

S1_W_wr_data[10] = AMPP_FUNCTION(QC2__clk0, S1L1312, F1_data_out, S1_W_stall);

--S1_d_readdata_d1[10] is std_1c20:inst|cpu:the_cpu|d_readdata_d1[10]

--operation mode is normal

S1_d_readdata_d1[10] = AMPP_FUNCTION(QC2__clk0, T1L111, WC1L19, WC1L11, V1_cpu_data_master_requests_cpu_jtag_debug_module, F1_data_out);

--S1_d_readdata_d1[26] is std_1c20:inst|cpu:the_cpu|d_readdata_d1[26]

--operation mode is normal

S1_d_readdata_d1[26] = AMPP_FUNCTION(QC2__clk0, T1L181, WC1L19, WC1L28, V1_cpu_data_master_requests_cpu_jtag_debug_module, F1_data_out);

--CD1_q_b[10] is std_1c20:inst|cpu:the_cpu|cpu_register_bank_a_module:cpu_register_bank_a|altsyncram:the_altsyncram|altsyncram_3vd1:auto_generated|q_b[10]

--RAM Block Operation Mode: Simple Dual-Port

--Port A Depth: 32, Port A Width: 1, Port B Depth: 32, Port B Width: 1

--Port A Logical Depth: 32, Port A Logical Width: 32, Port B Logical Depth: 32, Port B Logical Width: 32

--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered

CD1_q_b[10] = AMPP_FUNCTION(GND, GND, QC2__clk0, QC2__clk0, !S1_M_wr_dst_reg, S1_W_stall, S1L1312, S1_M_dst_regnum[0], S1_M_dst_regnum[1], S1_M_dst_regnum[2], S1_M_dst_regnum[3], S1_M_dst_regnum[4], AD1_q_b[27], AD1_q_b[28], AD1_q_b[29], AD1_q_b[30], AD1_q_b[31]);

--S1_D_pc_plus_one[7] is std_1c20:inst|cpu:the_cpu|D_pc_plus_one[7]

--operation mode is normal

S1_D_pc_plus_one[7] = AMPP_FUNCTION(QC2__clk0, S1L886, F1_data_out, S1_W_stall);

--S1_D_br_taken_waddr_partial[7] is std_1c20:inst|cpu:the_cpu|D_br_taken_waddr_partial[7]

--operation mode is arithmetic

S1_D_br_taken_waddr_partial[7] = AMPP_FUNCTION(QC2__clk0, AD1_q_b[15], S1L886, F1_data_out, S1_W_stall, S1L190);

--S1L192 is std_1c20:inst|cpu:the_cpu|D_br_taken_waddr_partial[7]~59

--operation mode is arithmetic

S1L192 = AMPP_FUNCTION(AD1_q_b[15], S1L886, S1L190);

--DD1_q_b[9] is std_1c20:inst|cpu:the_cpu|cpu_register_bank_b_module:cpu_register_bank_b|altsyncram:the_altsyncram|altsyncram_4vd1:auto_generated|q_b[9]

--RAM Block Operation Mode: Simple Dual-Port

--Port A Depth: 32, Port A Width: 1, Port B Depth: 32, Port B Width: 1

--Port A Logical Depth: 32, Port A Logical Width: 32, Port B Logical Depth: 32, Port B Logical Width: 32

--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered

DD1_q_b[9] = AMPP_FUNCTION(GND, GND, QC2__clk0, QC2__clk0, !S1_M_wr_dst_reg, S1_W_stall, S1L1309, S1_M_dst_regnum[0], S1_M_dst_regnum[1], S1_M_dst_regnum[2], S1_M_dst_regnum[3], S1_M_dst_regnum[4], AD1_q_b[22], AD1_q_b[23], AD1_q_b[24], AD1_q_b[25], AD1_q_b[26]);

--S1_W_wr_data[9] is std_1c20:inst|cpu:the_cpu|W_wr_data[9]

--operation mode is normal

S1_W_wr_data[9] = AMPP_FUNCTION(QC2__clk0, S1L1309, F1_data_out, S1_W_stall);

--S1_d_readdata_d1[9] is std_1c20:inst|cpu:the_cpu|d_readdata_d1[9]

--operation mode is normal

S1_d_readdata_d1[9] = AMPP_FUNCTION(QC2__clk0, T1L105, WC1L19, WC1L10, V1_cpu_data_master_requests_cpu_jtag_debug_module, F1_data_out);

--CD1_q_b[9] is std_1c20:inst|cpu:the_cpu|cpu_register_bank_a_module:cpu_register_bank_a|altsyncram:the_altsyncram|altsyncram_3vd1:auto_generated|q_b[9]

--RAM Block Operation Mode: Simple Dual-Port

--Port A Depth: 32, Port A Width: 1, Port B Depth: 32, Port B Width: 1

--Port A Logical Depth: 32, Port A Logical Width: 32, Port B Logical Depth: 32, Port B Logical Width: 32

--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered

CD1_q_b[9] = AMPP_FUNCTION(GND, GND, QC2__clk0, QC2__clk0, !S1_M_wr_dst_reg, S1_W_stall, S1L1309, S1_M_dst_regnum[0], S1_M_dst_regnum[1], S1_M_dst_regnum[2], S1_M_dst_regnum[3], S1_M_dst_regnum[4], AD1_q_b[27], AD1_q_b[28], AD1_q_b[29], AD1_q_b[30], AD1_q_b[31]);

--S1_D_pc_plus_one[6] is std_1c20:inst|cpu:the_cpu|D_pc_plus_one[6]

--operation mode is normal

S1_D_pc_plus_one[6] = AMPP_FUNCTION(QC2__clk0, S1L884, F1_data_out, S1_W_stall);

--S1_D_br_taken_waddr_partial[6] is std_1c20:inst|cpu:the_cpu|D_br_taken_waddr_partial[6]

--operation mode is arithmetic

S1_D_br_taken_waddr_partial[6] = AMPP_FUNCTION(QC2__clk0, AD1_q_b[14], S1L884, F1_data_out, S1_W_stall, S1L188);

--S1L190 is std_1c20:inst|cpu:the_cpu|D_br_taken_waddr_partial[6]~60

--operation mode is arithmetic

S1L190 = AMPP_FUNCTION(AD1_q_b[14], S1L884, S1L188);

--DD1_q_b[8] is std_1c20:inst|cpu:the_cpu|cpu_register_bank_b_module:cpu_register_bank_b|altsyncram:the_altsyncram|altsyncram_4vd1:auto_generated|q_b[8]

--RAM Block Operation Mode: Simple Dual-Port

--Port A Depth: 32, Port A Width: 1, Port B Depth: 32, Port B Width: 1

--Port A Logical Depth: 32, Port A Logical Width: 32, Port B Logical Depth: 32, Port B Logical Width: 32

--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered

DD1_q_b[8] = AMPP_FUNCTION(GND, GND, QC2__clk0, QC2__clk0, !S1_M_wr_dst_reg, S1_W_stall, S1L1306, S1_M_dst_regnum[0], S1_M_dst_regnum[1], S1_M_dst_regnum[2], S1_M_dst_regnum[3], S1_M_dst_regnum[4], AD1_q_b[22], AD1_q_b[23], AD1_q_b[24], AD1_q_b[25], AD1_q_b[26]);

--S1_W_wr_data[8] is std_1c20:inst|cpu:the_cpu|W_wr_data[8]

--operation mode is normal

S1_W_wr_data[8] = AMPP_FUNCTION(QC2__clk0, S1L1306, F1_data_out, S1_W_stall);

--S1_d_readdata_d1[8] is std_1c20:inst|cpu:the_cpu|d_readdata_d1[8]

--operation mode is normal

S1_d_readdata_d1[8] = AMPP_FUNCTION(QC2__clk0, T1L99, WC1L19, WC1L9, V1_cpu_data_master_requests_cpu_jtag_debug_module, F1_data_out);

--CD1_q_b[8] is std_1c20:inst|cpu:the_cpu|cpu_register_bank_a_module:cpu_register_bank_a|altsyncram:the_altsyncram|altsyncram_3vd1:auto_generated|q_b[8]

--RAM Block Operation Mode: Simple Dual-Port

--Port A Depth: 32, Port A Width: 1, Port B Depth: 32, Port B Width: 1

--Port A Logical Depth: 32, Port A Logical Width: 32, Port B Logical Depth: 32, Port B Logical Width: 32

--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered

CD1_q_b[8] = AMPP_FUNCTION(GND, GND, QC2__clk0, QC2__clk0, !S1_M_wr_dst_reg, S1_W_stall, S1L1306, S1_M_dst_regnum[0], S1_M_dst_regnum[1], S1_M_dst_regnum[2], S1_M_dst_regnum[3], S1_M_dst_regnum[4], AD1_q_b[27], AD1_q_b[28], AD1_q_b[29], AD1_q_b[30], AD1_q_b[31]);

--S1_D_pc_plus_one[5] is std_1c20:inst|cpu:the_cpu|D_pc_plus_one[5]

--operation mode is normal

S1_D_pc_plus_one[5] = AMPP_FUNCTION(QC2__clk0, S1L882, F1_data_out, S1_W_stall);

--S1_D_br_taken_waddr_partial[5] is std_1c20:inst|cpu:the_cpu|D_br_taken_waddr_partial[5]

--operation mode is arithmetic

S1_D_br_taken_waddr_partial[5] = AMPP_FUNCTION(QC2__clk0, AD1_q_b[13], S1L882, F1_data_out, S1_W_stall, S1L186);

--S1L188 is std_1c20:inst|cpu:the_cpu|D_br_taken_waddr_partial[5]~61

--operation mode is arithmetic

S1L188 = AMPP_FUNCTION(AD1_q_b[13], S1L882, S1L186);

--CD1_q_b[7] is std_1c20:inst|cpu:the_cpu|cpu_register_bank_a_module:cpu_register_bank_a|altsyncram:the_altsyncram|altsyncram_3vd1:auto_generated|q_b[7]

--RAM Block Operation Mode: Simple Dual-Port

--Port A Depth: 32, Port A Width: 1, Port B Depth: 32, Port B Width: 1

--Port A Logical Depth: 32, Port A Logical Width: 32, Port B Logical Depth: 32, Port B Logical Width: 32

--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered

CD1_q_b[7] = AMPP_FUNCTION(GND, GND, QC2__clk0, QC2__clk0, !S1_M_wr_dst_reg, S1_W_stall, S1L1303, S1_M_dst_regnum[0], S1_M_dst_regnum[1], S1_M_dst_regnum[2], S1_M_dst_regnum[3], S1_M_dst_regnum[4], AD1_q_b[27], AD1_q_b[28], AD1_q_b[29], AD1_q_b[30], AD1_q_b[31]);

--S1_W_wr_data[7] is std_1c20:inst|cpu:the_cpu|W_wr_data[7]

--operation mode is normal

S1_W_wr_data[7] = AMPP_FUNCTION(QC2__clk0, S1L1303, F1_data_out, S1_W_stall);

--S1_E_src2_prelim[7] is std_1c20:inst|cpu:the_cpu|E_src2_prelim[7]

--operation mode is normal

S1_E_src2_prelim[7] = AMPP_FUNCTION(QC2__clk0, DD1_q_b[7], S1_W_wr_data[7], S1L1303, S1L396, F1_data_out, S1L392, S1_W_stall);

--S1_M_ipending_reg[6] is std_1c20:inst|cpu:the_cpu|M_ipending_reg[6]

--operation mode is normal

S1_M_ipending_reg[6] = AMPP_FUNCTION(QC2__clk0, S1_M_ienable_reg[6], Y1_d1_irq_from_the_lan91c111, FD1_internal_oci_ienable1[6], F1_data_out);

--S1_M_ienable_reg[6] is std_1c20:inst|cpu:the_cpu|M_ienable_reg[6]

--operation mode is normal

S1_M_ienable_reg[6] = AMPP_FUNCTION(QC2__clk0, S1L412, F1_data_out, S1L1117);

--CD1_q_b[6] is std_1c20:inst|cpu:the_cpu|cpu_register_bank_a_module:cpu_register_bank_a|altsyncram:the_altsyncram|altsyncram_3vd1:auto_generated|q_b[6]

--RAM Block Operation Mode: Simple Dual-Port

--Port A Depth: 32, Port A Width: 1, Port B Depth: 32, Port B Width: 1

--Port A Logical Depth: 32, Port A Logical Width: 32, Port B Logical Depth: 32, Port B Logical Width: 32

--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered

CD1_q_b[6] = AMPP_FUNCTION(GND, GND, QC2__clk0, QC2__clk0, !S1_M_wr_dst_reg, S1_W_stall, S1L1300, S1_M_dst_regnum[0], S1_M_dst_regnum[1], S1_M_dst_regnum[2], S1_M_dst_regnum[3], S1_M_dst_regnum[4], AD1_q_b[27], AD1_q_b[28], AD1_q_b[29], AD1_q_b[30], AD1_q_b[31]);

--S1_W_wr_data[6] is std_1c20:inst|cpu:the_cpu|W_wr_data[6]

--operation mode is normal

S1_W_wr_data[6] = AMPP_FUNCTION(QC2__clk0, S1L1300, F1_data_out, S1_W_stall);

--S1L347Q is std_1c20:inst|cpu:the_cpu|d_readdata_d1[6]~88

--operation mode is normal

S1L347Q = AMPP_FUNCTION(QC2__clk0, T1L83, U1L120, X1_cpu_data_master_requests_epcs_controller_epcs_control_port, F1_data_out);

--S1L348Q is std_1c20:inst|cpu:the_cpu|d_readdata_d1[6]~89

--operation mode is normal

S1L348Q = AMPP_FUNCTION(QC2__clk0, WC1L7, WC1L19, FD1_internal_oci_ienable1[6], V1_cpu_data_master_requests_cpu_jtag_debug_module, F1_data_out);

--T1_cpu_data_master_readdata[6] is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[6]

--operation mode is normal

T1_cpu_data_master_readdata[6] = S1L347Q & S1L348Q;

--S1_E_src2_prelim[6] is std_1c20:inst|cpu:the_cpu|E_src2_prelim[6]

--operation mode is normal

S1_E_src2_prelim[6] = AMPP_FUNCTION(QC2__clk0, DD1_q_b[6], S1_W_wr_data[6], S1L1300, S1L396, F1_data_out, S1L392, S1_W_stall);

--S1_D_pc_plus_one[4] is std_1c20:inst|cpu:the_cpu|D_pc_plus_one[4]

--operation mode is normal

S1_D_pc_plus_one[4] = AMPP_FUNCTION(QC2__clk0, S1L880, F1_data_out, S1_W_stall);

--S1_D_br_taken_waddr_partial[4] is std_1c20:inst|cpu:the_cpu|D_br_taken_waddr_partial[4]

--operation mode is arithmetic

S1_D_br_taken_waddr_partial[4] = AMPP_FUNCTION(QC2__clk0, AD1_q_b[12], S1L880, F1_data_out, S1_W_stall, S1L184);

--S1L186 is std_1c20:inst|cpu:the_cpu|D_br_taken_waddr_partial[4]~62

--operation mode is arithmetic

S1L186 = AMPP_FUNCTION(AD1_q_b[12], S1L880, S1L184);

--S1_M_ipending_reg[4] is std_1c20:inst|cpu:the_cpu|M_ipending_reg[4]

--operation mode is normal

S1_M_ipending_reg[4] = AMPP_FUNCTION(QC2__clk0, S1_M_ienable_reg[4], XE1_irq, FD1_internal_oci_ienable1[4], F1_data_out);

--S1_M_ienable_reg[4] is std_1c20:inst|cpu:the_cpu|M_ienable_reg[4]

--operation mode is normal

S1_M_ienable_reg[4] = AMPP_FUNCTION(QC2__clk0, S1L410, F1_data_out, S1L1117);

--CD1_q_b[4] is std_1c20:inst|cpu:the_cpu|cpu_register_bank_a_module:cpu_register_bank_a|altsyncram:the_altsyncram|altsyncram_3vd1:auto_generated|q_b[4]

--RAM Block Operation Mode: Simple Dual-Port

--Port A Depth: 32, Port A Width: 1, Port B Depth: 32, Port B Width: 1

--Port A Logical Depth: 32, Port A Logical Width: 32, Port B Logical Depth: 32, Port B Logical Width: 32

--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered

CD1_q_b[4] = AMPP_FUNCTION(GND, GND, QC2__clk0, QC2__clk0, !S1_M_wr_dst_reg, S1_W_stall, S1L1294, S1_M_dst_regnum[0], S1_M_dst_regnum[1], S1_M_dst_regnum[2], S1_M_dst_regnum[3], S1_M_dst_regnum[4], AD1_q_b[27], AD1_q_b[28], AD1_q_b[29], AD1_q_b[30], AD1_q_b[31]);

--S1_W_wr_data[4] is std_1c20:inst|cpu:the_cpu|W_wr_data[4]

--operation mode is normal

S1_W_wr_data[4] = AMPP_FUNCTION(QC2__clk0, S1L1294, F1_data_out, S1_W_stall);

--S1L343Q is std_1c20:inst|cpu:the_cpu|d_readdata_d1[4]~92

--operation mode is normal

S1L343Q = AMPP_FUNCTION(QC2__clk0, T1L66, U1L121, X1_cpu_data_master_requests_epcs_controller_epcs_control_port, F1_data_out);

--S1L344Q is std_1c20:inst|cpu:the_cpu|d_readdata_d1[4]~93

--operation mode is normal

S1L344Q = AMPP_FUNCTION(QC2__clk0, WC1L5, WC1L19, FD1_internal_oci_ienable1[4], V1_cpu_data_master_requests_cpu_jtag_debug_module, F1_data_out);

--T1_cpu_data_master_readdata[4] is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[4]

--operation mode is normal

T1_cpu_data_master_readdata[4] = S1L343Q & S1L344Q;

--S1_E_src2_prelim[4] is std_1c20:inst|cpu:the_cpu|E_src2_prelim[4]

--operation mode is normal

S1_E_src2_prelim[4] = AMPP_FUNCTION(QC2__clk0, DD1_q_b[4], S1_W_wr_data[4], S1L1294, S1L396, F1_data_out, S1L392, S1_W_stall);

--S1_D_pc_plus_one[2] is std_1c20:inst|cpu:the_cpu|D_pc_plus_one[2]

--operation mode is normal

S1_D_pc_plus_one[2] = AMPP_FUNCTION(QC2__clk0, S1L876, F1_data_out, S1_W_stall);

--S1_D_br_taken_waddr_partial[2] is std_1c20:inst|cpu:the_cpu|D_br_taken_waddr_partial[2]

--operation mode is arithmetic

S1_D_br_taken_waddr_partial[2] = AMPP_FUNCTION(QC2__clk0, AD1_q_b[10], S1L876, F1_data_out, S1_W_stall, S1L180);

--S1L182 is std_1c20:inst|cpu:the_cpu|D_br_taken_waddr_partial[2]~63

--operation mode is arithmetic

S1L182 = AMPP_FUNCTION(AD1_q_b[10], S1L876, S1L180);

--S1_M_ipending_reg[5] is std_1c20:inst|cpu:the_cpu|M_ipending_reg[5]

--operation mode is normal

S1_M_ipending_reg[5] = AMPP_FUNCTION(QC2__clk0, S1_M_ienable_reg[5], DE1_irq_reg, FD1_internal_oci_ienable1[5], F1_data_out);

--S1_M_ienable_reg[5] is std_1c20:inst|cpu:the_cpu|M_ienable_reg[5]

--operation mode is normal

S1_M_ienable_reg[5] = AMPP_FUNCTION(QC2__clk0, S1L411, F1_data_out, S1L1117);

--CD1_q_b[5] is std_1c20:inst|cpu:the_cpu|cpu_register_bank_a_module:cpu_register_bank_a|altsyncram:the_altsyncram|altsyncram_3vd1:auto_generated|q_b[5]

--RAM Block Operation Mode: Simple Dual-Port

--Port A Depth: 32, Port A Width: 1, Port B Depth: 32, Port B Width: 1

--Port A Logical Depth: 32, Port A Logical Width: 32, Port B Logical Depth: 32, Port B Logical Width: 32

--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered

CD1_q_b[5] = AMPP_FUNCTION(GND, GND, QC2__clk0, QC2__clk0, !S1_M_wr_dst_reg, S1_W_stall, S1L1297, S1_M_dst_regnum[0], S1_M_dst_regnum[1], S1_M_dst_regnum[2], S1_M_dst_regnum[3], S1_M_dst_regnum[4], AD1_q_b[27], AD1_q_b[28], AD1_q_b[29], AD1_q_b[30], AD1_q_b[31]);

--S1_W_wr_data[5] is std_1c20:inst|cpu:the_cpu|W_wr_data[5]

--operation mode is normal

S1_W_wr_data[5] = AMPP_FUNCTION(QC2__clk0, S1L1297, F1_data_out, S1_W_stall);

--S1L345Q is std_1c20:inst|cpu:the_cpu|d_readdata_d1[5]~90

--operation mode is normal

S1L345Q = AMPP_FUNCTION(QC2__clk0, T1L74, U1L122, X1_cpu_data_master_requests_epcs_controller_epcs_control_port, F1_data_out);

--S1L346Q is std_1c20:inst|cpu:the_cpu|d_readdata_d1[5]~91

--operation mode is normal

S1L346Q = AMPP_FUNCTION(QC2__clk0, WC1L6, WC1L19, FD1_internal_oci_ienable1[5], V1_cpu_data_master_requests_cpu_jtag_debug_module, F1_data_out);

--T1_cpu_data_master_readdata[5] is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[5]

--operation mode is normal

T1_cpu_data_master_readdata[5] = S1L345Q & S1L346Q;

--S1_E_src2_prelim[5] is std_1c20:inst|cpu:the_cpu|E_src2_prelim[5]

--operation mode is normal

S1_E_src2_prelim[5] = AMPP_FUNCTION(QC2__clk0, DD1_q_b[5], S1_W_wr_data[5], S1L1297, S1L396, F1_data_out, S1L392, S1_W_stall);

--S1_D_pc_plus_one[3] is std_1c20:inst|cpu:the_cpu|D_pc_plus_one[3]

--operation mode is normal

S1_D_pc_plus_one[3] = AMPP_FUNCTION(QC2__clk0, S1L878, F1_data_out, S1_W_stall);

--S1_D_br_taken_waddr_partial[3] is std_1c20:inst|cpu:the_cpu|D_br_taken_waddr_partial[3]

--operation mode is arithmetic

S1_D_br_taken_waddr_partial[3] = AMPP_FUNCTION(QC2__clk0, AD1_q_b[11], S1L878, F1_data_out, S1_W_stall, S1L182);

--S1L184 is std_1c20:inst|cpu:the_cpu|D_br_taken_waddr_partial[3]~64

--operation mode is arithmetic

S1L184 = AMPP_FUNCTION(AD1_q_b[11], S1L878, S1L182);

--S1L635 is std_1c20:inst|cpu:the_cpu|E_src2[0]~1528

--operation mode is normal

S1L635 = AMPP_FUNCTION(S1_E_src2_imm[0], S1L1231, S1_E_ctrl_src2_is_imm);

--S1_E_src1_prelim[0] is std_1c20:inst|cpu:the_cpu|E_src1_prelim[0]

--operation mode is normal

S1_E_src1_prelim[0] = AMPP_FUNCTION(QC2__clk0, CD1_q_b[0], S1_W_wr_data[0], S1L1282, S1_D_src1_hazard_W, F1_data_out, S1_D_src1_hazard_M, S1_W_stall);

--S1_M_shift_rot_result[0] is std_1c20:inst|cpu:the_cpu|M_shift_rot_result[0]

--operation mode is normal

S1_M_shift_rot_result[0] = AMPP_FUNCTION(QC2__clk0, S1L1185, S1_M_shift_rot_result[1], S1L569, S1_M_ctrl_shift_rot_right, F1_data_out, !S1_M_shift_rot_stall);

--S1L1280 is std_1c20:inst|cpu:the_cpu|M_wr_data_unfiltered[0]~3693

--operation mode is normal

S1L1280 = AMPP_FUNCTION(S1_M_shift_rot_result[0], S1_M_ctrl_shift_rot);

--S1_av_ld_data_aligned_or_div[0] is std_1c20:inst|cpu:the_cpu|av_ld_data_aligned_or_div[0]

--operation mode is normal

S1_av_ld_data_aligned_or_div[0] = AMPP_FUNCTION(QC2__clk0, T1_cpu_data_master_readdata[0], S1_d_readdata_d1[16], S1L140, S1_M_ld_align_sh16, F1_data_out, S1_M_ld_align_sh8);

--S1L1281 is std_1c20:inst|cpu:the_cpu|M_wr_data_unfiltered[0]~3694

--operation mode is normal

S1L1281 = AMPP_FUNCTION(S1_av_ld_data_aligned_or_div[0], S1_M_alu_result[0], S1_av_ld_or_div_done, S1_M_ctrl_shift_rot);

--S1L569 is std_1c20:inst|cpu:the_cpu|E_src1[0]~2039

--operation mode is normal

S1L569 = AMPP_FUNCTION(S1_E_src1_prelim[0], S1_E_src1_hazard_M, S1L1280, S1L1281);

--S1_E_src1_prelim[1] is std_1c20:inst|cpu:the_cpu|E_src1_prelim[1]

--operation mode is normal

S1_E_src1_prelim[1] = AMPP_FUNCTION(QC2__clk0, CD1_q_b[1], S1_W_wr_data[1], S1L1285, S1_D_src1_hazard_W, F1_data_out, S1_D_src1_hazard_M, S1_W_stall);

--S1L1283 is std_1c20:inst|cpu:the_cpu|M_wr_data_unfiltered[1]~3695

--operation mode is normal

S1L1283 = AMPP_FUNCTION(S1_M_shift_rot_result[1], S1_M_ctrl_shift_rot);

--S1_av_ld_data_aligned_or_div[1] is std_1c20:inst|cpu:the_cpu|av_ld_data_aligned_or_div[1]

--operation mode is normal

S1_av_ld_data_aligned_or_div[1] = AMPP_FUNCTION(QC2__clk0, T1_cpu_data_master_readdata[1], S1_d_readdata_d1[17], S1L142, S1_M_ld_align_sh16, F1_data_out, S1_M_ld_align_sh8);

--S1L1284 is std_1c20:inst|cpu:the_cpu|M_wr_data_unfiltered[1]~3696

--operation mode is normal

S1L1284 = AMPP_FUNCTION(S1_av_ld_data_aligned_or_div[1], S1_M_alu_result[1], S1_av_ld_or_div_done, S1_M_ctrl_shift_rot);

--S1L570 is std_1c20:inst|cpu:the_cpu|E_src1[1]~2040

--operation mode is normal

S1L570 = AMPP_FUNCTION(S1_E_src1_prelim[1], S1_E_src1_hazard_M, S1L1283, S1L1284);

--S1_D_pc[13] is std_1c20:inst|cpu:the_cpu|D_pc[13]

--operation mode is normal

S1_D_pc[13] = AMPP_FUNCTION(QC2__clk0, S1_F_pc[13], F1_data_out, S1_W_stall);

--S1_D_pc[12] is std_1c20:inst|cpu:the_cpu|D_pc[12]

--operation mode is normal

S1_D_pc[12] = AMPP_FUNCTION(QC2__clk0, S1_F_pc[12], F1_data_out, S1_W_stall);

--S1_D_pc[11] is std_1c20:inst|cpu:the_cpu|D_pc[11]

--operation mode is normal

S1_D_pc[11] = AMPP_FUNCTION(QC2__clk0, S1_F_pc[11], F1_data_out, S1_W_stall);

--S1_D_pc[10] is std_1c20:inst|cpu:the_cpu|D_pc[10]

--operation mode is normal

S1_D_pc[10] = AMPP_FUNCTION(QC2__clk0, S1_F_pc[10], F1_data_out, S1_W_stall);

--S1L1056 is std_1c20:inst|cpu:the_cpu|ic_tag_wraddress[6]~COMBOUT

--operation mode is normal

S1L1056 = AMPP_FUNCTION(S1_D_pc[9], S1_ic_fill_line[6], S1_D_ic_fill_starting);

--S1_ic_tag_wraddress[6] is std_1c20:inst|cpu:the_cpu|ic_tag_wraddress[6]

--operation mode is normal

S1_ic_tag_wraddress[6] = AMPP_FUNCTION(QC2__clk0, S1_D_pc[9], S1_ic_fill_line[6], S1_M_alu_result[11], S1_D_ic_fill_starting, F1_data_out, !S1_reset_d1, S1L1006);

--S1L1054 is std_1c20:inst|cpu:the_cpu|ic_tag_wraddress[5]~COMBOUT

--operation mode is normal

S1L1054 = AMPP_FUNCTION(S1_D_pc[8], S1_ic_fill_line[5], S1_D_ic_fill_starting);

--S1_ic_tag_wraddress[5] is std_1c20:inst|cpu:the_cpu|ic_tag_wraddress[5]

--operation mode is normal

S1_ic_tag_wraddress[5] = AMPP_FUNCTION(QC2__clk0, S1_D_pc[8], S1_ic_fill_line[5], S1_M_alu_result[10], S1_D_ic_fill_starting, F1_data_out, !S1_reset_d1, S1L1006);

--S1L1052 is std_1c20:inst|cpu:the_cpu|ic_tag_wraddress[4]~COMBOUT

--operation mode is normal

S1L1052 = AMPP_FUNCTION(S1_D_pc[7], S1_ic_fill_line[4], S1_D_ic_fill_starting);

--S1_ic_tag_wraddress[4] is std_1c20:inst|cpu:the_cpu|ic_tag_wraddress[4]

--operation mode is normal

S1_ic_tag_wraddress[4] = AMPP_FUNCTION(QC2__clk0, S1_D_pc[7], S1_ic_fill_line[4], S1_M_alu_result[9], S1_D_ic_fill_starting, F1_data_out, !S1_reset_d1, S1L1006);

--S1L1050 is std_1c20:inst|cpu:the_cpu|ic_tag_wraddress[3]~COMBOUT

--operation mode is normal

S1L1050 = AMPP_FUNCTION(S1_D_pc[6], S1_ic_fill_line[3], S1_D_ic_fill_starting);

--S1_ic_tag_wraddress[3] is std_1c20:inst|cpu:the_cpu|ic_tag_wraddress[3]

--operation mode is normal

S1_ic_tag_wraddress[3] = AMPP_FUNCTION(QC2__clk0, S1_D_pc[6], S1_ic_fill_line[3], S1_M_alu_result[8], S1_D_ic_fill_starting, F1_data_out, !S1_reset_d1, S1L1006);

--S1L1048 is std_1c20:inst|cpu:the_cpu|ic_tag_wraddress[2]~COMBOUT

--operation mode is normal

S1L1048 = AMPP_FUNCTION(S1_D_pc[5], S1_ic_fill_line[2], S1_D_ic_fill_starting);

--S1_ic_tag_wraddress[2] is std_1c20:inst|cpu:the_cpu|ic_tag_wraddress[2]

--operation mode is normal

S1_ic_tag_wraddress[2] = AMPP_FUNCTION(QC2__clk0, S1_D_pc[5], S1_ic_fill_line[2], S1_M_alu_result[7], S1_D_ic_fill_starting, F1_data_out, !S1_reset_d1, S1L1006);

--S1L1046 is std_1c20:inst|cpu:the_cpu|ic_tag_wraddress[1]~COMBOUT

--operation mode is normal

S1L1046 = AMPP_FUNCTION(S1_D_pc[4], S1_ic_fill_line[1], S1_D_ic_fill_starting);

--S1_ic_tag_wraddress[1] is std_1c20:inst|cpu:the_cpu|ic_tag_wraddress[1]

--operation mode is normal

S1_ic_tag_wraddress[1] = AMPP_FUNCTION(QC2__clk0, S1_D_pc[4], S1_ic_fill_line[1], S1_M_alu_result[6], S1_D_ic_fill_starting, F1_data_out, !S1_reset_d1, S1L1006);

--S1_D_pc[3] is std_1c20:inst|cpu:the_cpu|D_pc[3]

--operation mode is normal

S1_D_pc[3] = AMPP_FUNCTION(QC2__clk0, S1_F_pc[3], F1_data_out, S1_W_stall);

--S1L1004 is std_1c20:inst|cpu:the_cpu|ic_fill_line~121

--operation mode is normal

S1L1004 = AMPP_FUNCTION(S1_ic_fill_line[0], S1_D_pc[3], S1L248, S1L249);

--S1_D_pc[2] is std_1c20:inst|cpu:the_cpu|D_pc[2]

--operation mode is normal

S1_D_pc[2] = AMPP_FUNCTION(QC2__clk0, S1_F_pc[2], F1_data_out, S1_W_stall);

--S1L113 is std_1c20:inst|cpu:the_cpu|Add5~39

--operation mode is normal

S1L113 = AMPP_FUNCTION(S1_ic_fill_ap_offset[2], S1_ic_fill_ap_offset[1], S1_ic_fill_ap_offset[0]);

--S1_ic_fill_req_accepted is std_1c20:inst|cpu:the_cpu|ic_fill_req_accepted

--operation mode is normal

S1_ic_fill_req_accepted = AMPP_FUNCTION(S1_internal_i_read, U1L133, U1L131);

--S1_D_pc[1] is std_1c20:inst|cpu:the_cpu|D_pc[1]

--operation mode is normal

S1_D_pc[1] = AMPP_FUNCTION(QC2__clk0, S1_F_pc[1], F1_data_out, S1_W_stall);

--S1L114 is std_1c20:inst|cpu:the_cpu|Add5~40

--operation mode is normal

S1L114 = AMPP_FUNCTION(S1_ic_fill_ap_offset[1], S1_ic_fill_ap_offset[0]);

--S1_D_pc[0] is std_1c20:inst|cpu:the_cpu|D_pc[0]

--operation mode is normal

S1_D_pc[0] = AMPP_FUNCTION(QC2__clk0, S1_F_pc[0], F1_data_out, S1_W_stall);

--S1_E_control_rd_data_without_mmu_regs[1] is std_1c20:inst|cpu:the_cpu|E_control_rd_data_without_mmu_regs[1]

--operation mode is normal

S1_E_control_rd_data_without_mmu_regs[1] = AMPP_FUNCTION(QC2__clk0, S1_M_ipending_reg[1], S1_M_ienable_reg[1], S1_D_iw[8], S1L200, F1_data_out, S1_W_stall);

--S1L405 is std_1c20:inst|cpu:the_cpu|E_alu_result[1]~2397

--operation mode is normal

S1L405 = AMPP_FUNCTION(S1_E_logic_op[1], S1L636, S1L570, S1_E_logic_op[0]);

--S1L406 is std_1c20:inst|cpu:the_cpu|E_alu_result[1]~2398

--operation mode is normal

S1L406 = AMPP_FUNCTION(S1L405, S1_E_ctrl_dst_data_sel_logic_result, YC1_result[1], S1_E_ctrl_dst_data_sel_pc_plus_one);

--S1L407 is std_1c20:inst|cpu:the_cpu|E_alu_result[1]~2399

--operation mode is normal

S1L407 = AMPP_FUNCTION(S1_E_control_rd_data_without_mmu_regs[1], S1L406, S1_E_ctrl_rdctl_inst, S1_E_ctrl_dst_data_sel_cmp);

--S1_E_control_rd_data_without_mmu_regs[0] is std_1c20:inst|cpu:the_cpu|E_control_rd_data_without_mmu_regs[0]

--operation mode is normal

S1_E_control_rd_data_without_mmu_regs[0] = AMPP_FUNCTION(QC2__clk0, S1_M_bstatus_reg, S1_D_iw[6], S1L198, S1L199, F1_data_out, S1_W_stall);

--S1L401 is std_1c20:inst|cpu:the_cpu|E_alu_result[0]~2400

--operation mode is normal

S1L401 = AMPP_FUNCTION(S1_E_logic_op[1], S1L635, S1L569, S1_E_logic_op[0]);

--S1L402 is std_1c20:inst|cpu:the_cpu|E_alu_result[0]~2401

--operation mode is normal

S1L402 = AMPP_FUNCTION(S1L401, S1_E_ctrl_dst_data_sel_logic_result, YC1_result[0], S1_E_ctrl_dst_data_sel_pc_plus_one);

--S1L403 is std_1c20:inst|cpu:the_cpu|E_alu_result[0]~2402

--operation mode is normal

S1L403 = AMPP_FUNCTION(S1_E_control_rd_data_without_mmu_regs[0], S1L402, S1_E_ctrl_rdctl_inst);

--S1L404 is std_1c20:inst|cpu:the_cpu|E_alu_result[0]~2403

--operation mode is normal

S1L404 = AMPP_FUNCTION(S1L415, S1L403, S1_E_ctrl_dst_data_sel_cmp);

--S1_E_src2_prelim[1] is std_1c20:inst|cpu:the_cpu|E_src2_prelim[1]

--operation mode is normal

S1_E_src2_prelim[1] = AMPP_FUNCTION(QC2__clk0, DD1_q_b[1], S1_W_wr_data[1], S1L1285, S1L396, F1_data_out, S1L392, S1_W_stall);

--S1_E_src2_prelim[0] is std_1c20:inst|cpu:the_cpu|E_src2_prelim[0]

--operation mode is normal

S1_E_src2_prelim[0] = AMPP_FUNCTION(QC2__clk0, DD1_q_b[0], S1_W_wr_data[0], S1L1282, S1L396, F1_data_out, S1L392, S1_W_stall);

--NB1L36 is std_1c20:inst|sdram_s1_arbitrator:the_sdram_s1|sdram_s1_address[7]~168

--operation mode is normal

NB1L36 = NB1L14 & S1_M_alu_result[9] # !NB1L14 & (S1_ic_fill_line[4]);

--NB1L35 is std_1c20:inst|sdram_s1_arbitrator:the_sdram_s1|sdram_s1_address[6]~169

--operation mode is normal

NB1L35 = NB1L14 & S1_M_alu_result[8] # !NB1L14 & (S1_ic_fill_line[3]);

--NB1L34 is std_1c20:inst|sdram_s1_arbitrator:the_sdram_s1|sdram_s1_address[5]~170

--operation mode is normal

NB1L34 = NB1L14 & S1_M_alu_result[7] # !NB1L14 & (S1_ic_fill_line[2]);

--NB1L33 is std_1c20:inst|sdram_s1_arbitrator:the_sdram_s1|sdram_s1_address[4]~171

--operation mode is normal

NB1L33 = NB1L14 & S1_M_alu_result[6] # !NB1L14 & (S1_ic_fill_line[1]);

--NB1L32 is std_1c20:inst|sdram_s1_arbitrator:the_sdram_s1|sdram_s1_address[3]~172

--operation mode is normal

NB1L32 = NB1L14 & S1_M_alu_result[5] # !NB1L14 & (S1_ic_fill_line[0]);

--NB1L31 is std_1c20:inst|sdram_s1_arbitrator:the_sdram_s1|sdram_s1_address[2]~173

--operation mode is normal

NB1L31 = NB1L14 & S1_M_alu_result[4] # !NB1L14 & (S1_ic_fill_ap_offset[2]);

--NB1L30 is std_1c20:inst|sdram_s1_arbitrator:the_sdram_s1|sdram_s1_address[1]~174

--operation mode is normal

NB1L30 = NB1L14 & S1_M_alu_result[3] # !NB1L14 & (S1_ic_fill_ap_offset[1]);

--NB1L29 is std_1c20:inst|sdram_s1_arbitrator:the_sdram_s1|sdram_s1_address[0]~175

--operation mode is normal

NB1L29 = NB1L14 & S1_M_alu_result[2] # !NB1L14 & (S1_ic_fill_ap_offset[0]);

--KB1L236 is std_1c20:inst|sdram:the_sdram|module_input1[35]~44

--operation mode is normal

KB1L236 = S1_internal_d_write & NB1L14 & (!S1_M_mem_byte_en[3]);

--KB1L235 is std_1c20:inst|sdram:the_sdram|module_input1[34]~45

--operation mode is normal

KB1L235 = S1_internal_d_write & NB1L14 & (!S1_M_mem_byte_en[2]);

--KB1L234 is std_1c20:inst|sdram:the_sdram|module_input1[33]~46

--operation mode is normal

KB1L234 = S1_internal_d_write & NB1L14 & (!S1_M_mem_byte_en[1]);

--KB1L233 is std_1c20:inst|sdram:the_sdram|module_input1[32]~47

--operation mode is normal

KB1L233 = S1_internal_d_write & NB1L14 & (!S1_M_mem_byte_en[0]);

--C1_jtag_debug_mode_usr1 is sld_hub:sld_hub_inst|jtag_debug_mode_usr1

--operation mode is normal

C1_jtag_debug_mode_usr1 = AMPP_FUNCTION(A1L5, EF1_dffs[1], C1L6, C1L7, EF1_dffs[0], FF1_state[0], FF1_state[12]);

--FF1_state[8] is sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state[8]

--operation mode is normal

FF1_state[8] = AMPP_FUNCTION(A1L5, FF1_state[5], FF1_state[7], VCC, !A1L7);

--BF9_Q[0] is sld_hub:sld_hub_inst|sld_dffex:IRF_ENA_0|Q[0]

--operation mode is normal

BF9_Q[0] = AMPP_FUNCTION(A1L5, altera_internal_jtag, BF3_Q[6], VCC, C1L24);

--CF1_WORD_SR[0] is sld_hub:sld_hub_inst|sld_rom_sr:HUB_INFO_REG|WORD_SR[0]

--operation mode is normal

CF1_WORD_SR[0] = AMPP_FUNCTION(A1L5, CF1_WORD_SR[1], CF1L19, FF1_state[4], CF1_clear_signal, VCC, CF1L21);

--C1_HUB_BYPASS_REG is sld_hub:sld_hub_inst|HUB_BYPASS_REG

--operation mode is normal

C1_HUB_BYPASS_REG = AMPP_FUNCTION(A1L5, C1L11, VCC);

--GF1_dffe1a[0] is sld_hub:sld_hub_inst|lpm_decode:instruction_decoder|decode_ogi:auto_generated|dffe1a[0]

--operation mode is normal

GF1_dffe1a[0] = AMPP_FUNCTION(A1L5, C1L32, BF3_Q[1], BF3_Q[3], BF3_Q[2], !C1_CLR_SIGNAL, C1L5);

--C1L20 is sld_hub:sld_hub_inst|hub_tdo~565

--operation mode is normal

C1L20 = AMPP_FUNCTION(BF9_Q[0], CF1_WORD_SR[0], C1_HUB_BYPASS_REG, GF1_dffe1a[0]);

--BF8_Q[0] is sld_hub:sld_hub_inst|sld_dffex:IRF_ENA|Q[0]

--operation mode is normal

BF8_Q[0] = AMPP_FUNCTION(A1L5, BF3_Q[6], altera_internal_jtag, !C1_CLR_SIGNAL, C1L24);

--SD1_sr[0] is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|sr[0]

--operation mode is normal

SD1_sr[0] = AMPP_FUNCTION(A1L5, SD1L141, SD1L5, SD1L142, SD1L144, !C1_CLR_SIGNAL, SD1L6);

--C1L21 is sld_hub:sld_hub_inst|hub_tdo~566

--operation mode is normal

C1L21 = AMPP_FUNCTION(BF8_Q[0], SD1_sr[0]);

--GE1_td_shift[0] is std_1c20:inst|jtag_uart:the_jtag_uart|alt_jtag_atlantic:jtag_uart_alt_jtag_atlantic|td_shift[0]

--operation mode is normal

GE1_td_shift[0] = AMPP_FUNCTION(A1L5, GE1L65, GE1L67, BF4_Q[0], !C1_CLR_SIGNAL, !FF1_state[4], GE1L52);

--BF8_Q[1] is sld_hub:sld_hub_inst|sld_dffex:IRF_ENA|Q[1]

--operation mode is normal

BF8_Q[1] = AMPP_FUNCTION(A1L5, altera_internal_jtag, BF3_Q[6], !C1_CLR_SIGNAL, C1L24);

--BF3_Q[0] is sld_hub:sld_hub_inst|sld_dffex:IRSR|Q[0]

--operation mode is normal

BF3_Q[0] = AMPP_FUNCTION(A1L5, SD1L119Q, C1L23, BF3_Q[1], BF3L3, !C1_CLR_SIGNAL, FF1_state[4], BF3L4);

--FF1_state[4] is sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state[4]

--operation mode is normal

FF1_state[4] = AMPP_FUNCTION(A1L5, FF1_state[7], FF1_state[3], FF1_state[4], VCC, A1L7);

--FF1_state[3] is sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state[3]

--operation mode is normal

FF1_state[3] = AMPP_FUNCTION(A1L5, FF1_state[2], A1L7, VCC);

--FF1L18 is sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state~13

--operation mode is normal

FF1L18 = AMPP_FUNCTION(FF1_state[4], FF1_state[3]);

--HB1_data_out is std_1c20:inst|reconfig_request_pio:the_reconfig_request_pio|data_out

--operation mode is normal

HB1_data_out_lut_out = XE1L16 & (HB1L3 & S1_M_st_data[0] # !HB1L3 & (HB1_data_out)) # !XE1L16 & (HB1_data_out);

HB1_data_out = DFFEAS(HB1_data_out_lut_out, QC2__clk0, F1_data_out, , , , , , );

--HB1_data_dir is std_1c20:inst|reconfig_request_pio:the_reconfig_request_pio|data_dir

--operation mode is normal

HB1_data_dir_lut_out = HB1L3 & (XE1L17 & S1_M_st_data[0] # !XE1L17 & (HB1_data_dir)) # !HB1L3 & (HB1_data_dir);

HB1_data_dir = DFFEAS(HB1_data_dir_lut_out, QC2__clk0, F1_data_out, , , , , , );

--Y1_d1_outgoing_ext_ram_bus_data[31] is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_outgoing_ext_ram_bus_data[31]

--operation mode is normal

Y1_d1_outgoing_ext_ram_bus_data[31]_lut_out = S1_M_st_data[31] & (Y1L52 # !Y1L50);

Y1_d1_outgoing_ext_ram_bus_data[31] = DFFEAS(Y1_d1_outgoing_ext_ram_bus_data[31]_lut_out, QC2__clk0, F1_data_out, , , , , , );

--Y1_d1_in_a_write_cycle is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_in_a_write_cycle

--operation mode is normal

Y1_d1_in_a_write_cycle_lut_out = S1_internal_d_write & (!Y1L194 & !Y1L300);

Y1_d1_in_a_write_cycle = DFFEAS(Y1_d1_in_a_write_cycle_lut_out, QC2__clk0, F1_data_out, , , , , , );

--Y1_d1_outgoing_ext_ram_bus_data[30] is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_outgoing_ext_ram_bus_data[30]

--operation mode is normal

Y1_d1_outgoing_ext_ram_bus_data[30]_lut_out = S1_M_st_data[30] & (Y1L52 # !Y1L50);

Y1_d1_outgoing_ext_ram_bus_data[30] = DFFEAS(Y1_d1_outgoing_ext_ram_bus_data[30]_lut_out, QC2__clk0, F1_data_out, , , , , , );

--Y1_d1_outgoing_ext_ram_bus_data[29] is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_outgoing_ext_ram_bus_data[29]

--operation mode is normal

Y1_d1_outgoing_ext_ram_bus_data[29]_lut_out = S1_M_st_data[29] & (Y1L52 # !Y1L50);

Y1_d1_outgoing_ext_ram_bus_data[29] = DFFEAS(Y1_d1_outgoing_ext_ram_bus_data[29]_lut_out, QC2__clk0, F1_data_out, , , , , , );

--Y1_d1_outgoing_ext_ram_bus_data[28] is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_outgoing_ext_ram_bus_data[28]

--operation mode is normal

Y1_d1_outgoing_ext_ram_bus_data[28]_lut_out = S1_M_st_data[28] & (Y1L52 # !Y1L50);

Y1_d1_outgoing_ext_ram_bus_data[28] = DFFEAS(Y1_d1_outgoing_ext_ram_bus_data[28]_lut_out, QC2__clk0, F1_data_out, , , , , , );

--Y1_d1_outgoing_ext_ram_bus_data[27] is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_outgoing_ext_ram_bus_data[27]

--operation mode is normal

Y1_d1_outgoing_ext_ram_bus_data[27]_lut_out = S1_M_st_data[27] & (Y1L52 # !Y1L50);

Y1_d1_outgoing_ext_ram_bus_data[27] = DFFEAS(Y1_d1_outgoing_ext_ram_bus_data[27]_lut_out, QC2__clk0, F1_data_out, , , , , , );

--Y1_d1_outgoing_ext_ram_bus_data[26] is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_outgoing_ext_ram_bus_data[26]

--operation mode is normal

Y1_d1_outgoing_ext_ram_bus_data[26]_lut_out = S1_M_st_data[26] & (Y1L52 # !Y1L50);

Y1_d1_outgoing_ext_ram_bus_data[26] = DFFEAS(Y1_d1_outgoing_ext_ram_bus_data[26]_lut_out, QC2__clk0, F1_data_out, , , , , , );

--Y1_d1_outgoing_ext_ram_bus_data[25] is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_outgoing_ext_ram_bus_data[25]

--operation mode is normal

Y1_d1_outgoing_ext_ram_bus_data[25]_lut_out = S1_M_st_data[25] & (Y1L52 # !Y1L50);

Y1_d1_outgoing_ext_ram_bus_data[25] = DFFEAS(Y1_d1_outgoing_ext_ram_bus_data[25]_lut_out, QC2__clk0, F1_data_out, , , , , , );

--Y1_d1_outgoing_ext_ram_bus_data[24] is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_outgoing_ext_ram_bus_data[24]

--operation mode is normal

Y1_d1_outgoing_ext_ram_bus_data[24]_lut_out = S1_M_st_data[24] & (Y1L52 # !Y1L50);

Y1_d1_outgoing_ext_ram_bus_data[24] = DFFEAS(Y1_d1_outgoing_ext_ram_bus_data[24]_lut_out, QC2__clk0, F1_data_out, , , , , , );

--Y1_d1_outgoing_ext_ram_bus_data[23] is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_outgoing_ext_ram_bus_data[23]

--operation mode is normal

Y1_d1_outgoing_ext_ram_bus_data[23]_lut_out = S1_M_st_data[23] & (Y1L52 # !Y1L50);

Y1_d1_outgoing_ext_ram_bus_data[23] = DFFEAS(Y1_d1_outgoing_ext_ram_bus_data[23]_lut_out, QC2__clk0, F1_data_out, , , , , , );

--Y1_d1_outgoing_ext_ram_bus_data[22] is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_outgoing_ext_ram_bus_data[22]

--operation mode is normal

Y1_d1_outgoing_ext_ram_bus_data[22]_lut_out = S1_M_st_data[22] & (Y1L52 # !Y1L50);

Y1_d1_outgoing_ext_ram_bus_data[22] = DFFEAS(Y1_d1_outgoing_ext_ram_bus_data[22]_lut_out, QC2__clk0, F1_data_out, , , , , , );

--Y1_d1_outgoing_ext_ram_bus_data[21] is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_outgoing_ext_ram_bus_data[21]

--operation mode is normal

Y1_d1_outgoing_ext_ram_bus_data[21]_lut_out = S1_M_st_data[21] & (Y1L52 # !Y1L50);

Y1_d1_outgoing_ext_ram_bus_data[21] = DFFEAS(Y1_d1_outgoing_ext_ram_bus_data[21]_lut_out, QC2__clk0, F1_data_out, , , , , , );

--Y1_d1_outgoing_ext_ram_bus_data[20] is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_outgoing_ext_ram_bus_data[20]

--operation mode is normal

Y1_d1_outgoing_ext_ram_bus_data[20]_lut_out = S1_M_st_data[20] & (Y1L52 # !Y1L50);

Y1_d1_outgoing_ext_ram_bus_data[20] = DFFEAS(Y1_d1_outgoing_ext_ram_bus_data[20]_lut_out, QC2__clk0, F1_data_out, , , , , , );

--Y1_d1_outgoing_ext_ram_bus_data[19] is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_outgoing_ext_ram_bus_data[19]

--operation mode is normal

Y1_d1_outgoing_ext_ram_bus_data[19]_lut_out = S1_M_st_data[19] & (Y1L52 # !Y1L50);

Y1_d1_outgoing_ext_ram_bus_data[19] = DFFEAS(Y1_d1_outgoing_ext_ram_bus_data[19]_lut_out, QC2__clk0, F1_data_out, , , , , , );

--Y1_d1_outgoing_ext_ram_bus_data[18] is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_outgoing_ext_ram_bus_data[18]

--operation mode is normal

Y1_d1_outgoing_ext_ram_bus_data[18]_lut_out = S1_M_st_data[18] & (Y1L52 # !Y1L50);

Y1_d1_outgoing_ext_ram_bus_data[18] = DFFEAS(Y1_d1_outgoing_ext_ram_bus_data[18]_lut_out, QC2__clk0, F1_data_out, , , , , , );

--Y1_d1_outgoing_ext_ram_bus_data[17] is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_outgoing_ext_ram_bus_data[17]

--operation mode is normal

Y1_d1_outgoing_ext_ram_bus_data[17]_lut_out = S1_M_st_data[17] & (Y1L52 # !Y1L50);

Y1_d1_outgoing_ext_ram_bus_data[17] = DFFEAS(Y1_d1_outgoing_ext_ram_bus_data[17]_lut_out, QC2__clk0, F1_data_out, , , , , , );

--Y1_d1_outgoing_ext_ram_bus_data[16] is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_outgoing_ext_ram_bus_data[16]

--operation mode is normal

Y1_d1_outgoing_ext_ram_bus_data[16]_lut_out = S1_M_st_data[16] & (Y1L52 # !Y1L50);

Y1_d1_outgoing_ext_ram_bus_data[16] = DFFEAS(Y1_d1_outgoing_ext_ram_bus_data[16]_lut_out, QC2__clk0, F1_data_out, , , , , , );

--Y1_d1_outgoing_ext_ram_bus_data[15] is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_outgoing_ext_ram_bus_data[15]

--operation mode is normal

Y1_d1_outgoing_ext_ram_bus_data[15]_lut_out = S1_M_st_data[15] & (Y1L52 # !Y1L50);

Y1_d1_outgoing_ext_ram_bus_data[15] = DFFEAS(Y1_d1_outgoing_ext_ram_bus_data[15]_lut_out, QC2__clk0, F1_data_out, , , , , , );

--Y1_d1_outgoing_ext_ram_bus_data[14] is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_outgoing_ext_ram_bus_data[14]

--operation mode is normal

Y1_d1_outgoing_ext_ram_bus_data[14]_lut_out = S1_M_st_data[14] & (Y1L52 # !Y1L50);

Y1_d1_outgoing_ext_ram_bus_data[14] = DFFEAS(Y1_d1_outgoing_ext_ram_bus_data[14]_lut_out, QC2__clk0, F1_data_out, , , , , , );

--Y1_d1_outgoing_ext_ram_bus_data[13] is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_outgoing_ext_ram_bus_data[13]

--operation mode is normal

Y1_d1_outgoing_ext_ram_bus_data[13]_lut_out = S1_M_st_data[13] & (Y1L52 # !Y1L50);

Y1_d1_outgoing_ext_ram_bus_data[13] = DFFEAS(Y1_d1_outgoing_ext_ram_bus_data[13]_lut_out, QC2__clk0, F1_data_out, , , , , , );

--Y1_d1_outgoing_ext_ram_bus_data[12] is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_outgoing_ext_ram_bus_data[12]

--operation mode is normal

Y1_d1_outgoing_ext_ram_bus_data[12]_lut_out = S1_M_st_data[12] & (Y1L52 # !Y1L50);

Y1_d1_outgoing_ext_ram_bus_data[12] = DFFEAS(Y1_d1_outgoing_ext_ram_bus_data[12]_lut_out, QC2__clk0, F1_data_out, , , , , , );

--Y1_d1_outgoing_ext_ram_bus_data[11] is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_outgoing_ext_ram_bus_data[11]

--operation mode is normal

Y1_d1_outgoing_ext_ram_bus_data[11]_lut_out = S1_M_st_data[11] & (Y1L52 # !Y1L50);

Y1_d1_outgoing_ext_ram_bus_data[11] = DFFEAS(Y1_d1_outgoing_ext_ram_bus_data[11]_lut_out, QC2__clk0, F1_data_out, , , , , , );

--Y1_d1_outgoing_ext_ram_bus_data[10] is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_outgoing_ext_ram_bus_data[10]

--operation mode is normal

Y1_d1_outgoing_ext_ram_bus_data[10]_lut_out = S1_M_st_data[10] & (Y1L52 # !Y1L50);

Y1_d1_outgoing_ext_ram_bus_data[10] = DFFEAS(Y1_d1_outgoing_ext_ram_bus_data[10]_lut_out, QC2__clk0, F1_data_out, , , , , , );

--Y1_d1_outgoing_ext_ram_bus_data[9] is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_outgoing_ext_ram_bus_data[9]

--operation mode is normal

Y1_d1_outgoing_ext_ram_bus_data[9]_lut_out = S1_M_st_data[9] & (Y1L52 # !Y1L50);

Y1_d1_outgoing_ext_ram_bus_data[9] = DFFEAS(Y1_d1_outgoing_ext_ram_bus_data[9]_lut_out, QC2__clk0, F1_data_out, , , , , , );

--Y1_d1_outgoing_ext_ram_bus_data[8] is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_outgoing_ext_ram_bus_data[8]

--operation mode is normal

Y1_d1_outgoing_ext_ram_bus_data[8]_lut_out = S1_M_st_data[8] & (Y1L52 # !Y1L50);

Y1_d1_outgoing_ext_ram_bus_data[8] = DFFEAS(Y1_d1_outgoing_ext_ram_bus_data[8]_lut_out, QC2__clk0, F1_data_out, , , , , , );

--Y1_d1_outgoing_ext_ram_bus_data[7] is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_outgoing_ext_ram_bus_data[7]

--operation mode is normal

Y1_d1_outgoing_ext_ram_bus_data[7]_lut_out = T1L237 & (Y1L278 & Y1L277 # !Y1L278 & (S1_M_st_data[7])) # !T1L237 & (S1_M_st_data[7]);

Y1_d1_outgoing_ext_ram_bus_data[7] = DFFEAS(Y1_d1_outgoing_ext_ram_bus_data[7]_lut_out, QC2__clk0, F1_data_out, , , , , , );

--Y1_d1_outgoing_ext_ram_bus_data[6] is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_outgoing_ext_ram_bus_data[6]

--operation mode is normal

Y1_d1_outgoing_ext_ram_bus_data[6]_lut_out = T1L237 & (Y1L278 & Y1L275 # !Y1L278 & (S1_M_st_data[6])) # !T1L237 & (S1_M_st_data[6]);

Y1_d1_outgoing_ext_ram_bus_data[6] = DFFEAS(Y1_d1_outgoing_ext_ram_bus_data[6]_lut_out, QC2__clk0, F1_data_out, , , , , , );

--Y1_d1_outgoing_ext_ram_bus_data[5] is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_outgoing_ext_ram_bus_data[5]

--operation mode is normal

Y1_d1_outgoing_ext_ram_bus_data[5]_lut_out = T1L237 & (Y1L278 & Y1L273 # !Y1L278 & (S1_M_st_data[5])) # !T1L237 & (S1_M_st_data[5]);

Y1_d1_outgoing_ext_ram_bus_data[5] = DFFEAS(Y1_d1_outgoing_ext_ram_bus_data[5]_lut_out, QC2__clk0, F1_data_out, , , , , , );

--Y1_d1_outgoing_ext_ram_bus_data[4] is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_outgoing_ext_ram_bus_data[4]

--operation mode is normal

Y1_d1_outgoing_ext_ram_bus_data[4]_lut_out = T1L237 & (Y1L278 & Y1L271 # !Y1L278 & (S1_M_st_data[4])) # !T1L237 & (S1_M_st_data[4]);

Y1_d1_outgoing_ext_ram_bus_data[4] = DFFEAS(Y1_d1_outgoing_ext_ram_bus_data[4]_lut_out, QC2__clk0, F1_data_out, , , , , , );

--Y1_d1_outgoing_ext_ram_bus_data[3] is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_outgoing_ext_ram_bus_data[3]

--operation mode is normal

Y1_d1_outgoing_ext_ram_bus_data[3]_lut_out = T1L237 & (Y1L278 & Y1L269 # !Y1L278 & (S1_M_st_data[3])) # !T1L237 & (S1_M_st_data[3]);

Y1_d1_outgoing_ext_ram_bus_data[3] = DFFEAS(Y1_d1_outgoing_ext_ram_bus_data[3]_lut_out, QC2__clk0, F1_data_out, , , , , , );

--Y1_d1_outgoing_ext_ram_bus_data[2] is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_outgoing_ext_ram_bus_data[2]

--operation mode is normal

Y1_d1_outgoing_ext_ram_bus_data[2]_lut_out = T1L237 & (Y1L278 & Y1L267 # !Y1L278 & (S1_M_st_data[2])) # !T1L237 & (S1_M_st_data[2]);

Y1_d1_outgoing_ext_ram_bus_data[2] = DFFEAS(Y1_d1_outgoing_ext_ram_bus_data[2]_lut_out, QC2__clk0, F1_data_out, , , , , , );

--Y1_d1_outgoing_ext_ram_bus_data[1] is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_outgoing_ext_ram_bus_data[1]

--operation mode is normal

Y1_d1_outgoing_ext_ram_bus_data[1]_lut_out = T1L237 & (Y1L278 & Y1L265 # !Y1L278 & (S1_M_st_data[1])) # !T1L237 & (S1_M_st_data[1]);

Y1_d1_outgoing_ext_ram_bus_data[1] = DFFEAS(Y1_d1_outgoing_ext_ram_bus_data[1]_lut_out, QC2__clk0, F1_data_out, , , , , , );

--Y1_d1_outgoing_ext_ram_bus_data[0] is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_outgoing_ext_ram_bus_data[0]

--operation mode is normal

Y1_d1_outgoing_ext_ram_bus_data[0]_lut_out = T1L237 & (Y1L278 & Y1L263 # !Y1L278 & (S1_M_st_data[0])) # !T1L237 & (S1_M_st_data[0]);

Y1_d1_outgoing_ext_ram_bus_data[0] = DFFEAS(Y1_d1_outgoing_ext_ram_bus_data[0]_lut_out, QC2__clk0, F1_data_out, , , , , , );

--KB1_m_data[31] is std_1c20:inst|sdram:the_sdram|m_data[31]

--operation mode is normal

KB1_m_data[31]_lut_out = KB1L511 & (KB1L510 & KB1L509 # !KB1L510 & (KB1_m_data[31])) # !KB1L511 & (KB1_m_data[31]);

KB1_m_data[31] = DFFEAS(KB1_m_data[31]_lut_out, QC2__clk0, F1_data_out, , , , , , );

--KB1_oe is std_1c20:inst|sdram:the_sdram|oe

--operation mode is normal

KB1_oe_lut_out = KB1L548 & (TE1L127 & !KB1L554 # !KB1_f_pop);

KB1_oe = DFFEAS(KB1_oe_lut_out, QC2__clk0, F1_data_out, , , , , , );

--KB1_m_data[30] is std_1c20:inst|sdram:the_sdram|m_data[30]

--operation mode is normal

KB1_m_data[30]_lut_out = KB1L511 & (KB1L510 & KB1L512 # !KB1L510 & (KB1_m_data[30])) # !KB1L511 & (KB1_m_data[30]);

KB1_m_data[30] = DFFEAS(KB1_m_data[30]_lut_out, QC2__clk0, F1_data_out, , , , , , );

--KB1_m_data[29] is std_1c20:inst|sdram:the_sdram|m_data[29]

--operation mode is normal

KB1_m_data[29]_lut_out = KB1L511 & (KB1L510 & KB1L513 # !KB1L510 & (KB1_m_data[29])) # !KB1L511 & (KB1_m_data[29]);

KB1_m_data[29] = DFFEAS(KB1_m_data[29]_lut_out, QC2__clk0, F1_data_out, , , , , , );

--KB1_m_data[28] is std_1c20:inst|sdram:the_sdram|m_data[28]

--operation mode is normal

KB1_m_data[28]_lut_out = KB1L511 & (KB1L510 & KB1L514 # !KB1L510 & (KB1_m_data[28])) # !KB1L511 & (KB1_m_data[28]);

KB1_m_data[28] = DFFEAS(KB1_m_data[28]_lut_out, QC2__clk0, F1_data_out, , , , , , );

--KB1_m_data[27] is std_1c20:inst|sdram:the_sdram|m_data[27]

--operation mode is normal

KB1_m_data[27]_lut_out = KB1L511 & (KB1L510 & KB1L515 # !KB1L510 & (KB1_m_data[27])) # !KB1L511 & (KB1_m_data[27]);

KB1_m_data[27] = DFFEAS(KB1_m_data[27]_lut_out, QC2__clk0, F1_data_out, , , , , , );

--KB1_m_data[26] is std_1c20:inst|sdram:the_sdram|m_data[26]

--operation mode is normal

KB1_m_data[26]_lut_out = KB1L511 & (KB1L510 & KB1L516 # !KB1L510 & (KB1_m_data[26])) # !KB1L511 & (KB1_m_data[26]);

KB1_m_data[26] = DFFEAS(KB1_m_data[26]_lut_out, QC2__clk0, F1_data_out, , , , , , );

--KB1_m_data[25] is std_1c20:inst|sdram:the_sdram|m_data[25]

--operation mode is normal

KB1_m_data[25]_lut_out = KB1L511 & (KB1L510 & KB1L517 # !KB1L510 & (KB1_m_data[25])) # !KB1L511 & (KB1_m_data[25]);

KB1_m_data[25] = DFFEAS(KB1_m_data[25]_lut_out, QC2__clk0, F1_data_out, , , , , , );

--KB1_m_data[24] is std_1c20:inst|sdram:the_sdram|m_data[24]

--operation mode is normal

KB1_m_data[24]_lut_out = KB1L511 & (KB1L510 & KB1L518 # !KB1L510 & (KB1_m_data[24])) # !KB1L511 & (KB1_m_data[24]);

KB1_m_data[24] = DFFEAS(KB1_m_data[24]_lut_out, QC2__clk0, F1_data_out, , , , , , );

--KB1_m_data[23] is std_1c20:inst|sdram:the_sdram|m_data[23]

--operation mode is normal

KB1_m_data[23]_lut_out = KB1L511 & (KB1L510 & KB1L519 # !KB1L510 & (KB1_m_data[23])) # !KB1L511 & (KB1_m_data[23]);

KB1_m_data[23] = DFFEAS(KB1_m_data[23]_lut_out, QC2__clk0, F1_data_out, , , , , , );

--KB1_m_data[22] is std_1c20:inst|sdram:the_sdram|m_data[22]

--operation mode is normal

KB1_m_data[22]_lut_out = KB1L511 & (KB1L510 & KB1L520 # !KB1L510 & (KB1_m_data[22])) # !KB1L511 & (KB1_m_data[22]);

KB1_m_data[22] = DFFEAS(KB1_m_data[22]_lut_out, QC2__clk0, F1_data_out, , , , , , );

--KB1_m_data[21] is std_1c20:inst|sdram:the_sdram|m_data[21]

--operation mode is normal

KB1_m_data[21]_lut_out = KB1L511 & (KB1L510 & KB1L521 # !KB1L510 & (KB1_m_data[21])) # !KB1L511 & (KB1_m_data[21]);

KB1_m_data[21] = DFFEAS(KB1_m_data[21]_lut_out, QC2__clk0, F1_data_out, , , , , , );

--KB1_m_data[20] is std_1c20:inst|sdram:the_sdram|m_data[20]

--operation mode is normal

KB1_m_data[20]_lut_out = KB1L511 & (KB1L510 & KB1L522 # !KB1L510 & (KB1_m_data[20])) # !KB1L511 & (KB1_m_data[20]);

KB1_m_data[20] = DFFEAS(KB1_m_data[20]_lut_out, QC2__clk0, F1_data_out, , , , , , );

--KB1_m_data[19] is std_1c20:inst|sdram:the_sdram|m_data[19]

--operation mode is normal

KB1_m_data[19]_lut_out = KB1L511 & (KB1L510 & KB1L523 # !KB1L510 & (KB1_m_data[19])) # !KB1L511 & (KB1_m_data[19]);

KB1_m_data[19] = DFFEAS(KB1_m_data[19]_lut_out, QC2__clk0, F1_data_out, , , , , , );

--KB1_m_data[18] is std_1c20:inst|sdram:the_sdram|m_data[18]

--operation mode is normal

KB1_m_data[18]_lut_out = KB1L511 & (KB1L510 & KB1L524 # !KB1L510 & (KB1_m_data[18])) # !KB1L511 & (KB1_m_data[18]);

KB1_m_data[18] = DFFEAS(KB1_m_data[18]_lut_out, QC2__clk0, F1_data_out, , , , , , );

--KB1_m_data[17] is std_1c20:inst|sdram:the_sdram|m_data[17]

--operation mode is normal

KB1_m_data[17]_lut_out = KB1L511 & (KB1L510 & KB1L525 # !KB1L510 & (KB1_m_data[17])) # !KB1L511 & (KB1_m_data[17]);

KB1_m_data[17] = DFFEAS(KB1_m_data[17]_lut_out, QC2__clk0, F1_data_out, , , , , , );

--KB1_m_data[16] is std_1c20:inst|sdram:the_sdram|m_data[16]

--operation mode is normal

KB1_m_data[16]_lut_out = KB1L511 & (KB1L510 & KB1L526 # !KB1L510 & (KB1_m_data[16])) # !KB1L511 & (KB1_m_data[16]);

KB1_m_data[16] = DFFEAS(KB1_m_data[16]_lut_out, QC2__clk0, F1_data_out, , , , , , );

--KB1_m_data[15] is std_1c20:inst|sdram:the_sdram|m_data[15]

--operation mode is normal

KB1_m_data[15]_lut_out = KB1L511 & (KB1L510 & KB1L527 # !KB1L510 & (KB1_m_data[15])) # !KB1L511 & (KB1_m_data[15]);

KB1_m_data[15] = DFFEAS(KB1_m_data[15]_lut_out, QC2__clk0, F1_data_out, , , , , , );

--KB1_m_data[14] is std_1c20:inst|sdram:the_sdram|m_data[14]

--operation mode is normal

KB1_m_data[14]_lut_out = KB1L511 & (KB1L510 & KB1L528 # !KB1L510 & (KB1_m_data[14])) # !KB1L511 & (KB1_m_data[14]);

KB1_m_data[14] = DFFEAS(KB1_m_data[14]_lut_out, QC2__clk0, F1_data_out, , , , , , );

--KB1_m_data[13] is std_1c20:inst|sdram:the_sdram|m_data[13]

--operation mode is normal

KB1_m_data[13]_lut_out = KB1L511 & (KB1L510 & KB1L529 # !KB1L510 & (KB1_m_data[13])) # !KB1L511 & (KB1_m_data[13]);

KB1_m_data[13] = DFFEAS(KB1_m_data[13]_lut_out, QC2__clk0, F1_data_out, , , , , , );

--KB1_m_data[12] is std_1c20:inst|sdram:the_sdram|m_data[12]

--operation mode is normal

KB1_m_data[12]_lut_out = KB1L511 & (KB1L510 & KB1L530 # !KB1L510 & (KB1_m_data[12])) # !KB1L511 & (KB1_m_data[12]);

KB1_m_data[12] = DFFEAS(KB1_m_data[12]_lut_out, QC2__clk0, F1_data_out, , , , , , );

--KB1_m_data[11] is std_1c20:inst|sdram:the_sdram|m_data[11]

--operation mode is normal

KB1_m_data[11]_lut_out = KB1L511 & (KB1L510 & KB1L531 # !KB1L510 & (KB1_m_data[11])) # !KB1L511 & (KB1_m_data[11]);

KB1_m_data[11] = DFFEAS(KB1_m_data[11]_lut_out, QC2__clk0, F1_data_out, , , , , , );

--KB1_m_data[10] is std_1c20:inst|sdram:the_sdram|m_data[10]

--operation mode is normal

KB1_m_data[10]_lut_out = KB1L511 & (KB1L510 & KB1L532 # !KB1L510 & (KB1_m_data[10])) # !KB1L511 & (KB1_m_data[10]);

KB1_m_data[10] = DFFEAS(KB1_m_data[10]_lut_out, QC2__clk0, F1_data_out, , , , , , );

--KB1_m_data[9] is std_1c20:inst|sdram:the_sdram|m_data[9]

--operation mode is normal

KB1_m_data[9]_lut_out = KB1L511 & (KB1L510 & KB1L533 # !KB1L510 & (KB1_m_data[9])) # !KB1L511 & (KB1_m_data[9]);

KB1_m_data[9] = DFFEAS(KB1_m_data[9]_lut_out, QC2__clk0, F1_data_out, , , , , , );

--KB1_m_data[8] is std_1c20:inst|sdram:the_sdram|m_data[8]

--operation mode is normal

KB1_m_data[8]_lut_out = KB1L511 & (KB1L510 & KB1L534 # !KB1L510 & (KB1_m_data[8])) # !KB1L511 & (KB1_m_data[8]);

KB1_m_data[8] = DFFEAS(KB1_m_data[8]_lut_out, QC2__clk0, F1_data_out, , , , , , );

--KB1_m_data[7] is std_1c20:inst|sdram:the_sdram|m_data[7]

--operation mode is normal

KB1_m_data[7]_lut_out = KB1L511 & (KB1L510 & KB1L535 # !KB1L510 & (KB1_m_data[7])) # !KB1L511 & (KB1_m_data[7]);

KB1_m_data[7] = DFFEAS(KB1_m_data[7]_lut_out, QC2__clk0, F1_data_out, , , , , , );

--KB1_m_data[6] is std_1c20:inst|sdram:the_sdram|m_data[6]

--operation mode is normal

KB1_m_data[6]_lut_out = KB1L511 & (KB1L510 & KB1L536 # !KB1L510 & (KB1_m_data[6])) # !KB1L511 & (KB1_m_data[6]);

KB1_m_data[6] = DFFEAS(KB1_m_data[6]_lut_out, QC2__clk0, F1_data_out, , , , , , );

--KB1_m_data[5] is std_1c20:inst|sdram:the_sdram|m_data[5]

--operation mode is normal

KB1_m_data[5]_lut_out = KB1L511 & (KB1L510 & KB1L537 # !KB1L510 & (KB1_m_data[5])) # !KB1L511 & (KB1_m_data[5]);

KB1_m_data[5] = DFFEAS(KB1_m_data[5]_lut_out, QC2__clk0, F1_data_out, , , , , , );

--KB1_m_data[4] is std_1c20:inst|sdram:the_sdram|m_data[4]

--operation mode is normal

KB1_m_data[4]_lut_out = KB1L511 & (KB1L510 & KB1L538 # !KB1L510 & (KB1_m_data[4])) # !KB1L511 & (KB1_m_data[4]);

KB1_m_data[4] = DFFEAS(KB1_m_data[4]_lut_out, QC2__clk0, F1_data_out, , , , , , );

--KB1_m_data[3] is std_1c20:inst|sdram:the_sdram|m_data[3]

--operation mode is normal

KB1_m_data[3]_lut_out = KB1L511 & (KB1L510 & KB1L539 # !KB1L510 & (KB1_m_data[3])) # !KB1L511 & (KB1_m_data[3]);

KB1_m_data[3] = DFFEAS(KB1_m_data[3]_lut_out, QC2__clk0, F1_data_out, , , , , , );

--KB1_m_data[2] is std_1c20:inst|sdram:the_sdram|m_data[2]

--operation mode is normal

KB1_m_data[2]_lut_out = KB1L511 & (KB1L510 & KB1L540 # !KB1L510 & (KB1_m_data[2])) # !KB1L511 & (KB1_m_data[2]);

KB1_m_data[2] = DFFEAS(KB1_m_data[2]_lut_out, QC2__clk0, F1_data_out, , , , , , );

--KB1_m_data[1] is std_1c20:inst|sdram:the_sdram|m_data[1]

--operation mode is normal

KB1_m_data[1]_lut_out = KB1L511 & (KB1L510 & KB1L541 # !KB1L510 & (KB1_m_data[1])) # !KB1L511 & (KB1_m_data[1]);

KB1_m_data[1] = DFFEAS(KB1_m_data[1]_lut_out, QC2__clk0, F1_data_out, , , , , , );

--KB1_m_data[0] is std_1c20:inst|sdram:the_sdram|m_data[0]

--operation mode is normal

KB1_m_data[0]_lut_out = KB1L511 & (KB1L510 & KB1L542 # !KB1L510 & (KB1_m_data[0])) # !KB1L511 & (KB1_m_data[0]);

KB1_m_data[0] = DFFEAS(KB1_m_data[0]_lut_out, QC2__clk0, F1_data_out, , , , , , );

--S1_ic_fill_ap_cnt[2] is std_1c20:inst|cpu:the_cpu|ic_fill_ap_cnt[2]

--operation mode is normal

S1_ic_fill_ap_cnt[2] = AMPP_FUNCTION(QC2__clk0, S1_internal_i_read, U1L133, U1L131, S1L116, F1_data_out, S1L993);

--S1_ic_fill_ap_cnt[1] is std_1c20:inst|cpu:the_cpu|ic_fill_ap_cnt[1]

--operation mode is normal

S1_ic_fill_ap_cnt[1] = AMPP_FUNCTION(QC2__clk0, S1_internal_i_read, U1L133, U1L131, S1L117, F1_data_out, S1L993);

--S1_ic_fill_ap_cnt[0] is std_1c20:inst|cpu:the_cpu|ic_fill_ap_cnt[0]

--operation mode is normal

S1_ic_fill_ap_cnt[0] = AMPP_FUNCTION(QC2__clk0, S1_D_ic_fill_starting, S1_ic_fill_ap_cnt[0], S1_internal_i_read, U1L132, F1_data_out);

--S1L115 is std_1c20:inst|cpu:the_cpu|Add6~107

--operation mode is normal

S1L115 = AMPP_FUNCTION(S1_ic_fill_ap_cnt[3], S1_ic_fill_ap_cnt[2], S1_ic_fill_ap_cnt[1], S1_ic_fill_ap_cnt[0]);

--S1L993 is std_1c20:inst|cpu:the_cpu|ic_fill_initial_offset[0]~807

--operation mode is normal

S1L993 = AMPP_FUNCTION(S1_internal_i_read, U1L133, U1L131, S1_D_ic_fill_starting);

--V1L4 is std_1c20:inst|cpu_jtag_debug_module_arbitrator:the_cpu_jtag_debug_module|cpu_data_master_granted_cpu_jtag_debug_module~64

--operation mode is normal

V1L4 = V1_cpu_data_master_requests_cpu_jtag_debug_module & (V1_cpu_jtag_debug_module_arb_addend[1] # !V1_cpu_instruction_master_qualified_request_cpu_jtag_debug_module & !V1_cpu_jtag_debug_module_arb_addend[0]);

--V1L7 is std_1c20:inst|cpu_jtag_debug_module_arbitrator:the_cpu_jtag_debug_module|cpu_instruction_master_granted_cpu_jtag_debug_module~88

--operation mode is normal

V1L7 = V1_cpu_instruction_master_qualified_request_cpu_jtag_debug_module & (V1L2 # !V1_cpu_jtag_debug_module_arb_addend[0]);

--V1_cpu_jtag_debug_module_saved_chosen_master_vector[0] is std_1c20:inst|cpu_jtag_debug_module_arbitrator:the_cpu_jtag_debug_module|cpu_jtag_debug_module_saved_chosen_master_vector[0]

--operation mode is normal

V1_cpu_jtag_debug_module_saved_chosen_master_vector[0]_lut_out = V1L25;

V1_cpu_jtag_debug_module_saved_chosen_master_vector[0] = DFFEAS(V1_cpu_jtag_debug_module_saved_chosen_master_vector[0]_lut_out, QC2__clk0, F1_data_out, , , , , , );

--V1L25 is std_1c20:inst|cpu_jtag_debug_module_arbitrator:the_cpu_jtag_debug_module|cpu_jtag_debug_module_arb_winner[0]~20

--operation mode is normal

V1L25 = V1L7 # V1_cpu_jtag_debug_module_saved_chosen_master_vector[0] & (!V1L4);

--X1L8 is std_1c20:inst|epcs_controller_epcs_control_port_arbitrator:the_epcs_controller_epcs_control_port|cpu_instruction_master_read_data_valid_epcs_controller_epcs_control_port~17

--operation mode is normal

X1L8 = X1L12 & (!V1L36);

--U1L101 is std_1c20:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_readdatavalid~147

--operation mode is normal

U1L101 = S1_ic_fill_tag[5] & (V1L2 & (V1_cpu_instruction_master_qualified_request_cpu_jtag_debug_module # V1_cpu_jtag_debug_module_arb_addend[0]) # !V1L2 & (!V1_cpu_jtag_debug_module_arb_addend[0] # !V1_cpu_instruction_master_qualified_request_cpu_jtag_debug_module));

--V1L31 is std_1c20:inst|cpu_jtag_debug_module_arbitrator:the_cpu_jtag_debug_module|cpu_jtag_debug_module_end_xfer~41

--operation mode is normal

V1L31 = QB1L1 & (V1L4 # X1L8 & U1L101) # !QB1L1 & X1L8 & U1L101;

--V1L26 is std_1c20:inst|cpu_jtag_debug_module_arbitrator:the_cpu_jtag_debug_module|cpu_jtag_debug_module_begintransfer~58

--operation mode is normal

V1L26 = !V1_d1_reasons_to_wait & (V1_cpu_instruction_master_qualified_request_cpu_jtag_debug_module # V1L6 & K1L3);

--V1L23 is std_1c20:inst|cpu_jtag_debug_module_arbitrator:the_cpu_jtag_debug_module|cpu_jtag_debug_module_arb_addend[1]~745

--operation mode is normal

V1L23 = V1L4 & (V1L25 # V1L31 & V1L26);

--V1L32 is std_1c20:inst|cpu_jtag_debug_module_arbitrator:the_cpu_jtag_debug_module|cpu_jtag_debug_module_end_xfer~42

--operation mode is normal

V1L32 = V1L31 & V1L26;

--V1L20 is std_1c20:inst|cpu_jtag_debug_module_arbitrator:the_cpu_jtag_debug_module|cpu_jtag_debug_module_arb_addend[0]~747

--operation mode is normal

V1L20 = V1L4 & !V1L25 & (!V1L26 # !V1L31);

--X1L2 is std_1c20:inst|epcs_controller_epcs_control_port_arbitrator:the_epcs_controller_epcs_control_port|cpu_data_master_granted_epcs_controller_epcs_control_port~33

--operation mode is normal

X1L2 = X1_cpu_data_master_requests_epcs_controller_epcs_control_port & (X1_epcs_controller_epcs_control_port_arb_addend[1] # !X1_cpu_instruction_master_qualified_request_epcs_controller_epcs_control_port & !X1_epcs_controller_epcs_control_port_arb_addend[0]);

--X1L6 is std_1c20:inst|epcs_controller_epcs_control_port_arbitrator:the_epcs_controller_epcs_control_port|cpu_instruction_master_granted_epcs_controller_epcs_control_port~91

--operation mode is normal

X1L6 = X1_cpu_instruction_master_qualified_request_epcs_controller_epcs_control_port & (X1_epcs_controller_epcs_control_port_arb_addend[1] & !X1_cpu_data_master_requests_epcs_controller_epcs_control_port # !X1_epcs_controller_epcs_control_port_arb_addend[0]);

--X1_epcs_controller_epcs_control_port_saved_chosen_master_vector[0] is std_1c20:inst|epcs_controller_epcs_control_port_arbitrator:the_epcs_controller_epcs_control_port|epcs_controller_epcs_control_port_saved_chosen_master_vector[0]

--operation mode is normal

X1_epcs_controller_epcs_control_port_saved_chosen_master_vector[0]_lut_out = X1L6 # X1_epcs_controller_epcs_control_port_saved_chosen_master_vector[0] & (!X1L2);

X1_epcs_controller_epcs_control_port_saved_chosen_master_vector[0] = DFFEAS(X1_epcs_controller_epcs_control_port_saved_chosen_master_vector[0]_lut_out, QC2__clk0, F1_data_out, , , , , , );

--X1L26 is std_1c20:inst|epcs_controller_epcs_control_port_arbitrator:the_epcs_controller_epcs_control_port|epcs_controller_epcs_control_port_begins_xfer~59

--operation mode is normal

X1L26 = !X1_d1_reasons_to_wait & (X1_cpu_instruction_master_qualified_request_epcs_controller_epcs_control_port # X1_cpu_data_master_requests_epcs_controller_epcs_control_port);

--X1L28 is std_1c20:inst|epcs_controller_epcs_control_port_arbitrator:the_epcs_controller_epcs_control_port|epcs_controller_epcs_control_port_in_a_read_cycle~0

--operation mode is normal

X1L28 = S1_internal_d_read & X1L2;

--DE1L140 is std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|p1_wr_strobe~41

--operation mode is normal

DE1L140 = S1_internal_d_write & X1L2;

--X1L27 is std_1c20:inst|epcs_controller_epcs_control_port_arbitrator:the_epcs_controller_epcs_control_port|epcs_controller_epcs_control_port_end_xfer~21

--operation mode is normal

X1L27 = X1L26 & (X1L9 # X1L28 # DE1L140);

--NB1_sdram_s1_saved_chosen_master_vector[0] is std_1c20:inst|sdram_s1_arbitrator:the_sdram_s1|sdram_s1_saved_chosen_master_vector[0]

--operation mode is normal

NB1_sdram_s1_saved_chosen_master_vector[0]_lut_out = NB1L18;

NB1_sdram_s1_saved_chosen_master_vector[0] = DFFEAS(NB1_sdram_s1_saved_chosen_master_vector[0]_lut_out, QC2__clk0, F1_data_out, , NB1L72, , , , );

--NB1L70 is std_1c20:inst|sdram_s1_arbitrator:the_sdram_s1|sdram_s1_arb_share_counter_next_value[5]~577

--operation mode is normal

NB1L70 = NB1_sdram_s1_slavearbiterlockenable & (NB1L13 # NB1L69);

--NB1L71 is std_1c20:inst|sdram_s1_arbitrator:the_sdram_s1|sdram_s1_arb_winner[0]~34

--operation mode is normal

NB1L71 = NB1L70 & NB1_sdram_s1_saved_chosen_master_vector[0] # !NB1L70 & (NB1L18 # NB1_sdram_s1_saved_chosen_master_vector[0] & !NB1L14);

--NB1L55 is std_1c20:inst|sdram_s1_arbitrator:the_sdram_s1|sdram_s1_arb_addend[1]~735

--operation mode is normal

NB1L55 = TE1L126 & (KB1L237 & NB1L14 # !KB1L237 & (NB1L71)) # !TE1L126 & (NB1L71);

--NB1_WideOr1 is std_1c20:inst|sdram_s1_arbitrator:the_sdram_s1|WideOr1

--operation mode is normal

NB1_WideOr1 = NB1_sdram_s1_arb_addend[1] & (NB1L19 # NB1L16) # !NB1_sdram_s1_arb_addend[1] & !NB1_sdram_s1_arb_addend[0] & (NB1L19 # NB1L16);

--VE1_how_many_ones[3] is std_1c20:inst|sdram_s1_arbitrator:the_sdram_s1|rdv_fifo_for_cpu_data_master_to_sdram_s1_module:rdv_fifo_for_cpu_data_master_to_sdram_s1|how_many_ones[3]

--operation mode is normal

VE1_how_many_ones[3]_lut_out = VE1L2;

VE1_how_many_ones[3] = DFFEAS(VE1_how_many_ones[3]_lut_out, QC2__clk0, F1_data_out, , WE1L27, , , , );

--VE1L21 is std_1c20:inst|sdram_s1_arbitrator:the_sdram_s1|rdv_fifo_for_cpu_data_master_to_sdram_s1_module:rdv_fifo_for_cpu_data_master_to_sdram_s1|updated_one_count~70

--operation mode is normal

VE1L21 = NB1L14 & !TE1L126 & (S1_internal_d_read # NB1L18);

--VE1_how_many_ones[2] is std_1c20:inst|sdram_s1_arbitrator:the_sdram_s1|rdv_fifo_for_cpu_data_master_to_sdram_s1_module:rdv_fifo_for_cpu_data_master_to_sdram_s1|how_many_ones[2]

--operation mode is normal

VE1_how_many_ones[2]_lut_out = VE1L3;

VE1_how_many_ones[2] = DFFEAS(VE1_how_many_ones[2]_lut_out, QC2__clk0, F1_data_out, , WE1L27, , , , );

--VE1_how_many_ones[1] is std_1c20:inst|sdram_s1_arbitrator:the_sdram_s1|rdv_fifo_for_cpu_data_master_to_sdram_s1_module:rdv_fifo_for_cpu_data_master_to_sdram_s1|how_many_ones[1]

--operation mode is normal

VE1_how_many_ones[1]_lut_out = VE1L4;

VE1_how_many_ones[1] = DFFEAS(VE1_how_many_ones[1]_lut_out, QC2__clk0, F1_data_out, , WE1L27, , , , );

--VE1_how_many_ones[0] is std_1c20:inst|sdram_s1_arbitrator:the_sdram_s1|rdv_fifo_for_cpu_data_master_to_sdram_s1_module:rdv_fifo_for_cpu_data_master_to_sdram_s1|how_many_ones[0]

--operation mode is normal

VE1_how_many_ones[0]_lut_out = VE1L6;

VE1_how_many_ones[0] = DFFEAS(VE1_how_many_ones[0]_lut_out, QC2__clk0, F1_data_out, , WE1L27, , , , );

--VE1L22 is std_1c20:inst|sdram_s1_arbitrator:the_sdram_s1|rdv_fifo_for_cpu_data_master_to_sdram_s1_module:rdv_fifo_for_cpu_data_master_to_sdram_s1|updated_one_count~71

--operation mode is normal

VE1L22 = KB1_za_valid & VE1_stage_0;

--VE1L1 is std_1c20:inst|sdram_s1_arbitrator:the_sdram_s1|rdv_fifo_for_cpu_data_master_to_sdram_s1_module:rdv_fifo_for_cpu_data_master_to_sdram_s1|A_WE_StdLogicVector~1206

--operation mode is normal

VE1L1 = VE1_how_many_ones[2] & VE1_how_many_ones[1] & VE1_how_many_ones[0] & !VE1L22 # !VE1_how_many_ones[2] & !VE1_how_many_ones[1] & !VE1_how_many_ones[0] & VE1L22;

--VE1L2 is std_1c20:inst|sdram_s1_arbitrator:the_sdram_s1|rdv_fifo_for_cpu_data_master_to_sdram_s1_module:rdv_fifo_for_cpu_data_master_to_sdram_s1|A_WE_StdLogicVector~1207

--operation mode is normal

VE1L2 = VE1_how_many_ones[3] $ (VE1L1 & (VE1L21 $ !VE1_how_many_ones[2]));

--VE1L3 is std_1c20:inst|sdram_s1_arbitrator:the_sdram_s1|rdv_fifo_for_cpu_data_master_to_sdram_s1_module:rdv_fifo_for_cpu_data_master_to_sdram_s1|A_WE_StdLogicVector~1208

--operation mode is normal

VE1L3 = VE1_how_many_ones[2] $ (VE1L5 & (VE1L21 $ !VE1_how_many_ones[1]));

--VE1L4 is std_1c20:inst|sdram_s1_arbitrator:the_sdram_s1|rdv_fifo_for_cpu_data_master_to_sdram_s1_module:rdv_fifo_for_cpu_data_master_to_sdram_s1|A_WE_StdLogicVector~1209

--operation mode is normal

VE1L4 = VE1_how_many_ones[1] $ (VE1L22 & !VE1L21 & !VE1_how_many_ones[0] # !VE1L22 & VE1L21 & VE1_how_many_ones[0]);

--NB1L2 is std_1c20:inst|sdram_s1_arbitrator:the_sdram_s1|Add1~99

--operation mode is arithmetic

NB1L2 = !NB1_sdram_s1_arb_share_counter[0];

--NB1L3 is std_1c20:inst|sdram_s1_arbitrator:the_sdram_s1|Add1~100

--operation mode is arithmetic

NB1L3 = CARRY(NB1_sdram_s1_arb_share_counter[0]);

--NB1_sdram_s1_arb_share_counter[0] is std_1c20:inst|sdram_s1_arbitrator:the_sdram_s1|sdram_s1_arb_share_counter[0]

--operation mode is normal

NB1_sdram_s1_arb_share_counter[0]_lut_out = NB1L65;

NB1_sdram_s1_arb_share_counter[0] = DFFEAS(NB1_sdram_s1_arb_share_counter[0]_lut_out, QC2__clk0, F1_data_out, , NB1L57, , , , );

--NB1_sdram_s1_arb_share_counter[1] is std_1c20:inst|sdram_s1_arbitrator:the_sdram_s1|sdram_s1_arb_share_counter[1]

--operation mode is normal

NB1_sdram_s1_arb_share_counter[1]_lut_out = NB1L67;

NB1_sdram_s1_arb_share_counter[1] = DFFEAS(NB1_sdram_s1_arb_share_counter[1]_lut_out, QC2__clk0, F1_data_out, , NB1L57, , , , );

--NB1_sdram_s1_arb_share_counter[2] is std_1c20:inst|sdram_s1_arbitrator:the_sdram_s1|sdram_s1_arb_share_counter[2]

--operation mode is normal

NB1_sdram_s1_arb_share_counter[2]_lut_out = NB1L68;

NB1_sdram_s1_arb_share_counter[2] = DFFEAS(NB1_sdram_s1_arb_share_counter[2]_lut_out, QC2__clk0, F1_data_out, , NB1L57, , , , );

--NB1_sdram_s1_arb_share_counter[3] is std_1c20:inst|sdram_s1_arbitrator:the_sdram_s1|sdram_s1_arb_share_counter[3]

--operation mode is normal

NB1_sdram_s1_arb_share_counter[3]_lut_out = NB1L10 & NB1L66;

NB1_sdram_s1_arb_share_counter[3] = DFFEAS(NB1_sdram_s1_arb_share_counter[3]_lut_out, QC2__clk0, F1_data_out, , NB1L57, , , , );

--NB1L83 is std_1c20:inst|sdram_s1_arbitrator:the_sdram_s1|WideOr0~28

--operation mode is normal

NB1L83 = NB1_sdram_s1_arb_share_counter[0] # NB1_sdram_s1_arb_share_counter[1] # NB1_sdram_s1_arb_share_counter[2] # NB1_sdram_s1_arb_share_counter[3];

--NB1_sdram_s1_arb_share_counter[4] is std_1c20:inst|sdram_s1_arbitrator:the_sdram_s1|sdram_s1_arb_share_counter[4]

--operation mode is normal

NB1_sdram_s1_arb_share_counter[4]_lut_out = NB1L8 & NB1L66;

NB1_sdram_s1_arb_share_counter[4] = DFFEAS(NB1_sdram_s1_arb_share_counter[4]_lut_out, QC2__clk0, F1_data_out, , NB1L57, , , , );

--NB1_sdram_s1_arb_share_counter[5] is std_1c20:inst|sdram_s1_arbitrator:the_sdram_s1|sdram_s1_arb_share_counter[5]

--operation mode is normal

NB1_sdram_s1_arb_share_counter[5]_lut_out = NB1L12 & NB1L66;

NB1_sdram_s1_arb_share_counter[5] = DFFEAS(NB1_sdram_s1_arb_share_counter[5]_lut_out, QC2__clk0, F1_data_out, , NB1L57, , , , );

--NB1_WideOr0 is std_1c20:inst|sdram_s1_arbitrator:the_sdram_s1|WideOr0

--operation mode is normal

NB1_WideOr0 = NB1L83 # NB1_sdram_s1_arb_share_counter[4] # NB1_sdram_s1_arb_share_counter[5];

--NB1L65 is std_1c20:inst|sdram_s1_arbitrator:the_sdram_s1|sdram_s1_arb_share_counter_next_value[0]~578

--operation mode is normal

NB1L65 = NB1L70 & NB1L2 & NB1_WideOr0 # !NB1L70 & (NB1L18);

--NB1L4 is std_1c20:inst|sdram_s1_arbitrator:the_sdram_s1|Add1~101

--operation mode is arithmetic

NB1L4_carry_eqn = NB1L3;

NB1L4 = NB1_sdram_s1_arb_share_counter[1] $ (!NB1L4_carry_eqn);

--NB1L5 is std_1c20:inst|sdram_s1_arbitrator:the_sdram_s1|Add1~102

--operation mode is arithmetic

NB1L5 = CARRY(!NB1_sdram_s1_arb_share_counter[1] & (!NB1L3));

--NB1L67 is std_1c20:inst|sdram_s1_arbitrator:the_sdram_s1|sdram_s1_arb_share_counter_next_value[1]~579

--operation mode is normal

NB1L67 = NB1L70 & NB1L4 & NB1_WideOr0 # !NB1L70 & (NB1L18);

--NB1L6 is std_1c20:inst|sdram_s1_arbitrator:the_sdram_s1|Add1~103

--operation mode is arithmetic

NB1L6_carry_eqn = NB1L5;

NB1L6 = NB1_sdram_s1_arb_share_counter[2] $ (NB1L6_carry_eqn);

--NB1L7 is std_1c20:inst|sdram_s1_arbitrator:the_sdram_s1|Add1~104

--operation mode is arithmetic

NB1L7 = CARRY(NB1_sdram_s1_arb_share_counter[2] # !NB1L5);

--NB1L68 is std_1c20:inst|sdram_s1_arbitrator:the_sdram_s1|sdram_s1_arb_share_counter_next_value[2]~580

--operation mode is normal

NB1L68 = NB1L70 & NB1L6 & NB1_WideOr0 # !NB1L70 & (NB1L18);

--NB1L66 is std_1c20:inst|sdram_s1_arbitrator:the_sdram_s1|sdram_s1_arb_share_counter_next_value[0]~581

--operation mode is normal

NB1L66 = NB1_sdram_s1_slavearbiterlockenable & NB1_WideOr0 & (NB1L13 # NB1L69);

--NB1L8 is std_1c20:inst|sdram_s1_arbitrator:the_sdram_s1|Add1~105

--operation mode is arithmetic

NB1L8_carry_eqn = NB1L11;

NB1L8 = NB1_sdram_s1_arb_share_counter[4] $ (NB1L8_carry_eqn);

--NB1L9 is std_1c20:inst|sdram_s1_arbitrator:the_sdram_s1|Add1~106

--operation mode is arithmetic

NB1L9 = CARRY(NB1_sdram_s1_arb_share_counter[4] # !NB1L11);

--NB1L10 is std_1c20:inst|sdram_s1_arbitrator:the_sdram_s1|Add1~107

--operation mode is arithmetic

NB1L10_carry_eqn = NB1L7;

NB1L10 = NB1_sdram_s1_arb_share_counter[3] $ (!NB1L10_carry_eqn);

--NB1L11 is std_1c20:inst|sdram_s1_arbitrator:the_sdram_s1|Add1~108

--operation mode is arithmetic

NB1L11 = CARRY(!NB1_sdram_s1_arb_share_counter[3] & (!NB1L7));

--NB1L12 is std_1c20:inst|sdram_s1_arbitrator:the_sdram_s1|Add1~109

--operation mode is normal

NB1L12_carry_eqn = NB1L9;

NB1L12 = NB1_sdram_s1_arb_share_counter[5] $ (!NB1L12_carry_eqn);

--NB1L80 is std_1c20:inst|sdram_s1_arbitrator:the_sdram_s1|sdram_s1_slavearbiterlockenable~156

--operation mode is normal

NB1L80 = NB1L66 & (NB1L8 # NB1L10 # NB1L12);

--NB1L81 is std_1c20:inst|sdram_s1_arbitrator:the_sdram_s1|sdram_s1_slavearbiterlockenable~157

--operation mode is normal

NB1L81 = NB1L65 # NB1L67 # NB1L68 # NB1L80;

--NB1L28 is std_1c20:inst|sdram_s1_arbitrator:the_sdram_s1|process2~55

--operation mode is normal

NB1L28 = NB1L16 # NB1L21 & (!NB1L24) # !NB1L21 & !NB1L17;

--NB1_d1_reasons_to_wait is std_1c20:inst|sdram_s1_arbitrator:the_sdram_s1|d1_reasons_to_wait

--operation mode is normal

NB1_d1_reasons_to_wait_lut_out = NB1L74;

NB1_d1_reasons_to_wait = DFFEAS(NB1_d1_reasons_to_wait_lut_out, QC2__clk0, F1_data_out, , , , , , );

--NB1L73 is std_1c20:inst|sdram_s1_arbitrator:the_sdram_s1|sdram_s1_arbitration_holdoff_internal~152

--operation mode is normal

NB1L73 = !NB1L70 & !NB1_d1_reasons_to_wait & (NB1L19 # NB1L16);

--NB1_sdram_s1_saved_chosen_master_vector[1] is std_1c20:inst|sdram_s1_arbitrator:the_sdram_s1|sdram_s1_saved_chosen_master_vector[1]

--operation mode is normal

NB1_sdram_s1_saved_chosen_master_vector[1]_lut_out = NB1L14;

NB1_sdram_s1_saved_chosen_master_vector[1] = DFFEAS(NB1_sdram_s1_saved_chosen_master_vector[1]_lut_out, QC2__clk0, F1_data_out, , NB1L72, , , , );

--NB1L1 is std_1c20:inst|sdram_s1_arbitrator:the_sdram_s1|A_WE_StdLogicVector~132

--operation mode is normal

NB1L1 = NB1L70 & NB1_sdram_s1_saved_chosen_master_vector[1] # !NB1L70 & (NB1L14 # NB1_sdram_s1_saved_chosen_master_vector[1] & !NB1L18);

--NB1L53 is std_1c20:inst|sdram_s1_arbitrator:the_sdram_s1|sdram_s1_arb_addend[0]~737

--operation mode is normal

NB1L53 = TE1L126 & (KB1L237 & NB1L18 # !KB1L237 & (!NB1L71)) # !TE1L126 & (!NB1L71);

--S1L769 is std_1c20:inst|cpu:the_cpu|Equal53~860

--operation mode is normal

S1L769 = AMPP_FUNCTION(S1_D_iw[0], S1_D_iw[1], S1_D_iw[2], S1_D_iw[3]);

--S1L175 is std_1c20:inst|cpu:the_cpu|D_br_pred_taken~36

--operation mode is normal

S1L175 = AMPP_FUNCTION(S1L215, S1_D_iw[21], S1L201, S1L769);

--S1_D_refetch is std_1c20:inst|cpu:the_cpu|D_refetch

--operation mode is normal

S1_D_refetch = AMPP_FUNCTION(S1_D_kill, S1_D_inst_ram_hit);

--S1_F_kill is std_1c20:inst|cpu:the_cpu|F_kill

--operation mode is normal

S1_F_kill = AMPP_FUNCTION(S1_D_issue, S1L175, S1_M_pipe_flush, S1_D_refetch);

--S1_F_pc[12] is std_1c20:inst|cpu:the_cpu|F_pc[12]

--operation mode is normal

S1_F_pc[12] = AMPP_FUNCTION(QC2__clk0, S1L35, S1_D_pc[12], S1_M_pipe_flush_waddr[12], S1_D_refetch, F1_data_out, !S1_M_pipe_flush, S1_W_stall);

--S1_F_pc[16] is std_1c20:inst|cpu:the_cpu|F_pc[16]

--operation mode is normal

S1_F_pc[16] = AMPP_FUNCTION(QC2__clk0, S1L36, S1_D_pc[16], S1_M_pipe_flush_waddr[16], S1_D_refetch, F1_data_out, !S1_M_pipe_flush, S1_W_stall);

--BD1_q_b[14] is std_1c20:inst|cpu:the_cpu|cpu_ic_tag_module:cpu_ic_tag|altsyncram:the_altsyncram|altsyncram_09e1:auto_generated|q_b[14]

--RAM Block Operation Mode: Simple Dual-Port

--Port A Depth: 128, Port A Width: 1, Port B Depth: 128, Port B Width: 1

--Port A Logical Depth: 128, Port A Logical Width: 22, Port B Logical Depth: 128, Port B Logical Width: 22

--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered

BD1_q_b[14] = AMPP_FUNCTION(GND, GND, QC2__clk0, QC2__clk0, S1_ic_tag_wren, S1_W_stall, S1_ic_fill_tag[6], S1_ic_tag_wraddress[0], S1_ic_tag_wraddress[1], S1_ic_tag_wraddress[2], S1_ic_tag_wraddress[3], S1_ic_tag_wraddress[4], S1_ic_tag_wraddress[5], S1_ic_tag_wraddress[6], S1L821, S1L824, S1L827, S1L830, S1L833, S1L836, S1L839);

--BD1_q_b[10] is std_1c20:inst|cpu:the_cpu|cpu_ic_tag_module:cpu_ic_tag|altsyncram:the_altsyncram|altsyncram_09e1:auto_generated|q_b[10]

--RAM Block Operation Mode: Simple Dual-Port

--Port A Depth: 128, Port A Width: 1, Port B Depth: 128, Port B Width: 1

--Port A Logical Depth: 128, Port A Logical Width: 22, Port B Logical Depth: 128, Port B Logical Width: 22

--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered

BD1_q_b[10] = AMPP_FUNCTION(GND, GND, QC2__clk0, QC2__clk0, S1_ic_tag_wren, S1_W_stall, S1_ic_fill_tag[2], S1_ic_tag_wraddress[0], S1_ic_tag_wraddress[1], S1_ic_tag_wraddress[2], S1_ic_tag_wraddress[3], S1_ic_tag_wraddress[4], S1_ic_tag_wraddress[5], S1_ic_tag_wraddress[6], S1L821, S1L824, S1L827, S1L830, S1L833, S1L836, S1L839);

--S1L810 is std_1c20:inst|cpu:the_cpu|F_ic_hit~118

--operation mode is normal

S1L810 = AMPP_FUNCTION(S1_F_pc[12], S1_F_pc[16], BD1_q_b[14], BD1_q_b[10]);

--S1_F_pc[20] is std_1c20:inst|cpu:the_cpu|F_pc[20]

--operation mode is normal

S1_F_pc[20] = AMPP_FUNCTION(QC2__clk0, S1L37, S1_D_pc[20], S1_M_pipe_flush_waddr[20], S1_D_refetch, F1_data_out, !S1_M_pipe_flush, S1_W_stall);

--S1_F_pc[19] is std_1c20:inst|cpu:the_cpu|F_pc[19]

--operation mode is normal

S1_F_pc[19] = AMPP_FUNCTION(QC2__clk0, S1L38, S1_D_pc[19], S1_M_pipe_flush_waddr[19], S1_D_refetch, F1_data_out, !S1_M_pipe_flush, S1_W_stall);

--BD1_q_b[17] is std_1c20:inst|cpu:the_cpu|cpu_ic_tag_module:cpu_ic_tag|altsyncram:the_altsyncram|altsyncram_09e1:auto_generated|q_b[17]

--RAM Block Operation Mode: Simple Dual-Port

--Port A Depth: 128, Port A Width: 1, Port B Depth: 128, Port B Width: 1

--Port A Logical Depth: 128, Port A Logical Width: 22, Port B Logical Depth: 128, Port B Logical Width: 22

--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered

BD1_q_b[17] = AMPP_FUNCTION(GND, GND, QC2__clk0, QC2__clk0, S1_ic_tag_wren, S1_W_stall, S1_ic_fill_tag[9], S1_ic_tag_wraddress[0], S1_ic_tag_wraddress[1], S1_ic_tag_wraddress[2], S1_ic_tag_wraddress[3], S1_ic_tag_wraddress[4], S1_ic_tag_wraddress[5], S1_ic_tag_wraddress[6], S1L821, S1L824, S1L827, S1L830, S1L833, S1L836, S1L839);

--BD1_q_b[18] is std_1c20:inst|cpu:the_cpu|cpu_ic_tag_module:cpu_ic_tag|altsyncram:the_altsyncram|altsyncram_09e1:auto_generated|q_b[18]

--RAM Block Operation Mode: Simple Dual-Port

--Port A Depth: 128, Port A Width: 1, Port B Depth: 128, Port B Width: 1

--Port A Logical Depth: 128, Port A Logical Width: 22, Port B Logical Depth: 128, Port B Logical Width: 22

--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered

BD1_q_b[18] = AMPP_FUNCTION(GND, GND, QC2__clk0, QC2__clk0, S1_ic_tag_wren, S1_W_stall, S1_ic_fill_tag[10], S1_ic_tag_wraddress[0], S1_ic_tag_wraddress[1], S1_ic_tag_wraddress[2], S1_ic_tag_wraddress[3], S1_ic_tag_wraddress[4], S1_ic_tag_wraddress[5], S1_ic_tag_wraddress[6], S1L821, S1L824, S1L827, S1L830, S1L833, S1L836, S1L839);

--S1L811 is std_1c20:inst|cpu:the_cpu|F_ic_hit~119

--operation mode is normal

S1L811 = AMPP_FUNCTION(S1_F_pc[20], S1_F_pc[19], BD1_q_b[17], BD1_q_b[18]);

--S1_F_pc[18] is std_1c20:inst|cpu:the_cpu|F_pc[18]

--operation mode is normal

S1_F_pc[18] = AMPP_FUNCTION(QC2__clk0, S1L39, S1_D_pc[18], S1_M_pipe_flush_waddr[18], S1_D_refetch, F1_data_out, !S1_M_pipe_flush, S1_W_stall);

--S1_F_pc[17] is std_1c20:inst|cpu:the_cpu|F_pc[17]

--operation mode is normal

S1_F_pc[17] = AMPP_FUNCTION(QC2__clk0, S1L40, S1_D_pc[17], S1_M_pipe_flush_waddr[17], S1_D_refetch, F1_data_out, !S1_M_pipe_flush, S1_W_stall);

--BD1_q_b[15] is std_1c20:inst|cpu:the_cpu|cpu_ic_tag_module:cpu_ic_tag|altsyncram:the_altsyncram|altsyncram_09e1:auto_generated|q_b[15]

--RAM Block Operation Mode: Simple Dual-Port

--Port A Depth: 128, Port A Width: 1, Port B Depth: 128, Port B Width: 1

--Port A Logical Depth: 128, Port A Logical Width: 22, Port B Logical Depth: 128, Port B Logical Width: 22

--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered

BD1_q_b[15] = AMPP_FUNCTION(GND, GND, QC2__clk0, QC2__clk0, S1_ic_tag_wren, S1_W_stall, S1_ic_fill_tag[7], S1_ic_tag_wraddress[0], S1_ic_tag_wraddress[1], S1_ic_tag_wraddress[2], S1_ic_tag_wraddress[3], S1_ic_tag_wraddress[4], S1_ic_tag_wraddress[5], S1_ic_tag_wraddress[6], S1L821, S1L824, S1L827, S1L830, S1L833, S1L836, S1L839);

--BD1_q_b[16] is std_1c20:inst|cpu:the_cpu|cpu_ic_tag_module:cpu_ic_tag|altsyncram:the_altsyncram|altsyncram_09e1:auto_generated|q_b[16]

--RAM Block Operation Mode: Simple Dual-Port

--Port A Depth: 128, Port A Width: 1, Port B Depth: 128, Port B Width: 1

--Port A Logical Depth: 128, Port A Logical Width: 22, Port B Logical Depth: 128, Port B Logical Width: 22

--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered

BD1_q_b[16] = AMPP_FUNCTION(GND, GND, QC2__clk0, QC2__clk0, S1_ic_tag_wren, S1_W_stall, S1_ic_fill_tag[8], S1_ic_tag_wraddress[0], S1_ic_tag_wraddress[1], S1_ic_tag_wraddress[2], S1_ic_tag_wraddress[3], S1_ic_tag_wraddress[4], S1_ic_tag_wraddress[5], S1_ic_tag_wraddress[6], S1L821, S1L824, S1L827, S1L830, S1L833, S1L836, S1L839);

--S1L812 is std_1c20:inst|cpu:the_cpu|F_ic_hit~120

--operation mode is normal

S1L812 = AMPP_FUNCTION(S1_F_pc[18], S1_F_pc[17], BD1_q_b[15], BD1_q_b[16]);

--S1_F_pc[21] is std_1c20:inst|cpu:the_cpu|F_pc[21]

--operation mode is normal

S1_F_pc[21] = AMPP_FUNCTION(QC2__clk0, S1L41, S1_D_pc[21], S1_M_pipe_flush_waddr[21], S1_D_refetch, F1_data_out, !S1_M_pipe_flush, S1_W_stall);

--S1_F_pc[14] is std_1c20:inst|cpu:the_cpu|F_pc[14]

--operation mode is normal

S1_F_pc[14] = AMPP_FUNCTION(QC2__clk0, S1L42, S1_D_pc[14], S1_M_pipe_flush_waddr[14], S1_D_refetch, F1_data_out, !S1_M_pipe_flush, S1_W_stall);

--BD1_q_b[12] is std_1c20:inst|cpu:the_cpu|cpu_ic_tag_module:cpu_ic_tag|altsyncram:the_altsyncram|altsyncram_09e1:auto_generated|q_b[12]

--RAM Block Operation Mode: Simple Dual-Port

--Port A Depth: 128, Port A Width: 1, Port B Depth: 128, Port B Width: 1

--Port A Logical Depth: 128, Port A Logical Width: 22, Port B Logical Depth: 128, Port B Logical Width: 22

--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered

BD1_q_b[12] = AMPP_FUNCTION(GND, GND, QC2__clk0, QC2__clk0, S1_ic_tag_wren, S1_W_stall, S1_ic_fill_tag[4], S1_ic_tag_wraddress[0], S1_ic_tag_wraddress[1], S1_ic_tag_wraddress[2], S1_ic_tag_wraddress[3], S1_ic_tag_wraddress[4], S1_ic_tag_wraddress[5], S1_ic_tag_wraddress[6], S1L821, S1L824, S1L827, S1L830, S1L833, S1L836, S1L839);

--BD1_q_b[19] is std_1c20:inst|cpu:the_cpu|cpu_ic_tag_module:cpu_ic_tag|altsyncram:the_altsyncram|altsyncram_09e1:auto_generated|q_b[19]

--RAM Block Operation Mode: Simple Dual-Port

--Port A Depth: 128, Port A Width: 1, Port B Depth: 128, Port B Width: 1

--Port A Logical Depth: 128, Port A Logical Width: 22, Port B Logical Depth: 128, Port B Logical Width: 22

--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered

BD1_q_b[19] = AMPP_FUNCTION(GND, GND, QC2__clk0, QC2__clk0, S1_ic_tag_wren, S1_W_stall, S1_ic_fill_tag[11], S1_ic_tag_wraddress[0], S1_ic_tag_wraddress[1], S1_ic_tag_wraddress[2], S1_ic_tag_wraddress[3], S1_ic_tag_wraddress[4], S1_ic_tag_wraddress[5], S1_ic_tag_wraddress[6], S1L821, S1L824, S1L827, S1L830, S1L833, S1L836, S1L839);

--S1L813 is std_1c20:inst|cpu:the_cpu|F_ic_hit~121

--operation mode is normal

S1L813 = AMPP_FUNCTION(S1_F_pc[21], S1_F_pc[14], BD1_q_b[12], BD1_q_b[19]);

--S1L814 is std_1c20:inst|cpu:the_cpu|F_ic_hit~122

--operation mode is normal

S1L814 = AMPP_FUNCTION(S1L810, S1L811, S1L812, S1L813);

--S1_F_pc[11] is std_1c20:inst|cpu:the_cpu|F_pc[11]

--operation mode is normal

S1_F_pc[11] = AMPP_FUNCTION(QC2__clk0, S1L43, S1_D_pc[11], S1_M_pipe_flush_waddr[11], S1_D_refetch, F1_data_out, !S1_M_pipe_flush, S1_W_stall);

--S1_F_pc[22] is std_1c20:inst|cpu:the_cpu|F_pc[22]

--operation mode is normal

S1_F_pc[22] = AMPP_FUNCTION(QC2__clk0, S1L44, S1_D_pc[22], S1_M_pipe_flush_waddr[22], S1_D_refetch, F1_data_out, !S1_M_pipe_flush, S1_W_stall);

--BD1_q_b[20] is std_1c20:inst|cpu:the_cpu|cpu_ic_tag_module:cpu_ic_tag|altsyncram:the_altsyncram|altsyncram_09e1:auto_generated|q_b[20]

--RAM Block Operation Mode: Simple Dual-Port

--Port A Depth: 128, Port A Width: 1, Port B Depth: 128, Port B Width: 1

--Port A Logical Depth: 128, Port A Logical Width: 22, Port B Logical Depth: 128, Port B Logical Width: 22

--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered

BD1_q_b[20] = AMPP_FUNCTION(GND, GND, QC2__clk0, QC2__clk0, S1_ic_tag_wren, S1_W_stall, S1_ic_fill_tag[12], S1_ic_tag_wraddress[0], S1_ic_tag_wraddress[1], S1_ic_tag_wraddress[2], S1_ic_tag_wraddress[3], S1_ic_tag_wraddress[4], S1_ic_tag_wraddress[5], S1_ic_tag_wraddress[6], S1L821, S1L824, S1L827, S1L830, S1L833, S1L836, S1L839);

--BD1_q_b[9] is std_1c20:inst|cpu:the_cpu|cpu_ic_tag_module:cpu_ic_tag|altsyncram:the_altsyncram|altsyncram_09e1:auto_generated|q_b[9]

--RAM Block Operation Mode: Simple Dual-Port

--Port A Depth: 128, Port A Width: 1, Port B Depth: 128, Port B Width: 1

--Port A Logical Depth: 128, Port A Logical Width: 22, Port B Logical Depth: 128, Port B Logical Width: 22

--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered

BD1_q_b[9] = AMPP_FUNCTION(GND, GND, QC2__clk0, QC2__clk0, S1_ic_tag_wren, S1_W_stall, S1_ic_fill_tag[1], S1_ic_tag_wraddress[0], S1_ic_tag_wraddress[1], S1_ic_tag_wraddress[2], S1_ic_tag_wraddress[3], S1_ic_tag_wraddress[4], S1_ic_tag_wraddress[5], S1_ic_tag_wraddress[6], S1L821, S1L824, S1L827, S1L830, S1L833, S1L836, S1L839);

--S1L815 is std_1c20:inst|cpu:the_cpu|F_ic_hit~123

--operation mode is normal

S1L815 = AMPP_FUNCTION(S1_F_pc[11], S1_F_pc[22], BD1_q_b[20], BD1_q_b[9]);

--S1_F_pc[23] is std_1c20:inst|cpu:the_cpu|F_pc[23]

--operation mode is normal

S1_F_pc[23] = AMPP_FUNCTION(QC2__clk0, S1L45, S1_D_pc[23], S1_M_pipe_flush_waddr[23], S1_D_refetch, F1_data_out, !S1_M_pipe_flush, S1_W_stall);

--S1_F_pc[15] is std_1c20:inst|cpu:the_cpu|F_pc[15]

--operation mode is normal

S1_F_pc[15] = AMPP_FUNCTION(QC2__clk0, S1L46, S1_D_pc[15], S1_M_pipe_flush_waddr[15], S1_D_refetch, F1_data_out, !S1_M_pipe_flush, S1_W_stall);

--BD1_q_b[13] is std_1c20:inst|cpu:the_cpu|cpu_ic_tag_module:cpu_ic_tag|altsyncram:the_altsyncram|altsyncram_09e1:auto_generated|q_b[13]

--RAM Block Operation Mode: Simple Dual-Port

--Port A Depth: 128, Port A Width: 1, Port B Depth: 128, Port B Width: 1

--Port A Logical Depth: 128, Port A Logical Width: 22, Port B Logical Depth: 128, Port B Logical Width: 22

--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered

BD1_q_b[13] = AMPP_FUNCTION(GND, GND, QC2__clk0, QC2__clk0, S1_ic_tag_wren, S1_W_stall, S1_ic_fill_tag[5], S1_ic_tag_wraddress[0], S1_ic_tag_wraddress[1], S1_ic_tag_wraddress[2], S1_ic_tag_wraddress[3], S1_ic_tag_wraddress[4], S1_ic_tag_wraddress[5], S1_ic_tag_wraddress[6], S1L821, S1L824, S1L827, S1L830, S1L833, S1L836, S1L839);

--BD1_q_b[21] is std_1c20:inst|cpu:the_cpu|cpu_ic_tag_module:cpu_ic_tag|altsyncram:the_altsyncram|altsyncram_09e1:auto_generated|q_b[21]

--RAM Block Operation Mode: Simple Dual-Port

--Port A Depth: 128, Port A Width: 1, Port B Depth: 128, Port B Width: 1

--Port A Logical Depth: 128, Port A Logical Width: 22, Port B Logical Depth: 128, Port B Logical Width: 22

--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered

BD1_q_b[21] = AMPP_FUNCTION(GND, GND, QC2__clk0, QC2__clk0, S1_ic_tag_wren, S1_W_stall, S1_ic_fill_tag[13], S1_ic_tag_wraddress[0], S1_ic_tag_wraddress[1], S1_ic_tag_wraddress[2], S1_ic_tag_wraddress[3], S1_ic_tag_wraddress[4], S1_ic_tag_wraddress[5], S1_ic_tag_wraddress[6], S1L821, S1L824, S1L827, S1L830, S1L833, S1L836, S1L839);

--S1L816 is std_1c20:inst|cpu:the_cpu|F_ic_hit~124

--operation mode is normal

S1L816 = AMPP_FUNCTION(S1_F_pc[23], S1_F_pc[15], BD1_q_b[13], BD1_q_b[21]);

--S1_F_pc[13] is std_1c20:inst|cpu:the_cpu|F_pc[13]

--operation mode is normal

S1_F_pc[13] = AMPP_FUNCTION(QC2__clk0, S1L47, S1_D_pc[13], S1_M_pipe_flush_waddr[13], S1_D_refetch, F1_data_out, !S1_M_pipe_flush, S1_W_stall);

--S1_F_pc[10] is std_1c20:inst|cpu:the_cpu|F_pc[10]

--operation mode is normal

S1_F_pc[10] = AMPP_FUNCTION(QC2__clk0, S1L48, S1_D_pc[10], S1_M_pipe_flush_waddr[10], S1_D_refetch, F1_data_out, !S1_M_pipe_flush, S1_W_stall);

--BD1_q_b[8] is std_1c20:inst|cpu:the_cpu|cpu_ic_tag_module:cpu_ic_tag|altsyncram:the_altsyncram|altsyncram_09e1:auto_generated|q_b[8]

--RAM Block Operation Mode: Simple Dual-Port

--Port A Depth: 128, Port A Width: 1, Port B Depth: 128, Port B Width: 1

--Port A Logical Depth: 128, Port A Logical Width: 22, Port B Logical Depth: 128, Port B Logical Width: 22

--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered

BD1_q_b[8] = AMPP_FUNCTION(GND, GND, QC2__clk0, QC2__clk0, S1_ic_tag_wren, S1_W_stall, S1_ic_fill_tag[0], S1_ic_tag_wraddress[0], S1_ic_tag_wraddress[1], S1_ic_tag_wraddress[2], S1_ic_tag_wraddress[3], S1_ic_tag_wraddress[4], S1_ic_tag_wraddress[5], S1_ic_tag_wraddress[6], S1L821, S1L824, S1L827, S1L830, S1L833, S1L836, S1L839);

--BD1_q_b[11] is std_1c20:inst|cpu:the_cpu|cpu_ic_tag_module:cpu_ic_tag|altsyncram:the_altsyncram|altsyncram_09e1:auto_generated|q_b[11]

--RAM Block Operation Mode: Simple Dual-Port

--Port A Depth: 128, Port A Width: 1, Port B Depth: 128, Port B Width: 1

--Port A Logical Depth: 128, Port A Logical Width: 22, Port B Logical Depth: 128, Port B Logical Width: 22

--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered

BD1_q_b[11] = AMPP_FUNCTION(GND, GND, QC2__clk0, QC2__clk0, S1_ic_tag_wren, S1_W_stall, S1_ic_fill_tag[3], S1_ic_tag_wraddress[0], S1_ic_tag_wraddress[1], S1_ic_tag_wraddress[2], S1_ic_tag_wraddress[3], S1_ic_tag_wraddress[4], S1_ic_tag_wraddress[5], S1_ic_tag_wraddress[6], S1L821, S1L824, S1L827, S1L830, S1L833, S1L836, S1L839);

--S1L817 is std_1c20:inst|cpu:the_cpu|F_ic_hit~125

--operation mode is normal

S1L817 = AMPP_FUNCTION(S1_F_pc[13], S1_F_pc[10], BD1_q_b[8], BD1_q_b[11]);

--BD1_q_b[5] is std_1c20:inst|cpu:the_cpu|cpu_ic_tag_module:cpu_ic_tag|altsyncram:the_altsyncram|altsyncram_09e1:auto_generated|q_b[5]

--RAM Block Operation Mode: Simple Dual-Port

--Port A Depth: 128, Port A Width: 1, Port B Depth: 128, Port B Width: 1

--Port A Logical Depth: 128, Port A Logical Width: 22, Port B Logical Depth: 128, Port B Logical Width: 22

--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered

BD1_q_b[5] = AMPP_FUNCTION(GND, GND, QC2__clk0, QC2__clk0, S1_ic_tag_wren, S1_W_stall, S1_ic_fill_valid_bits[5], S1_ic_tag_wraddress[0], S1_ic_tag_wraddress[1], S1_ic_tag_wraddress[2], S1_ic_tag_wraddress[3], S1_ic_tag_wraddress[4], S1_ic_tag_wraddress[5], S1_ic_tag_wraddress[6], S1L821, S1L824, S1L827, S1L830, S1L833, S1L836, S1L839);

--S1_F_pc[2] is std_1c20:inst|cpu:the_cpu|F_pc[2]

--operation mode is normal

S1_F_pc[2] = AMPP_FUNCTION(QC2__clk0, S1L795, F1_data_out, S1_W_stall);

--BD1_q_b[3] is std_1c20:inst|cpu:the_cpu|cpu_ic_tag_module:cpu_ic_tag|altsyncram:the_altsyncram|altsyncram_09e1:auto_generated|q_b[3]

--RAM Block Operation Mode: Simple Dual-Port

--Port A Depth: 128, Port A Width: 1, Port B Depth: 128, Port B Width: 1

--Port A Logical Depth: 128, Port A Logical Width: 22, Port B Logical Depth: 128, Port B Logical Width: 22

--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered

BD1_q_b[3] = AMPP_FUNCTION(GND, GND, QC2__clk0, QC2__clk0, S1_ic_tag_wren, S1_W_stall, S1_ic_fill_valid_bits[3], S1_ic_tag_wraddress[0], S1_ic_tag_wraddress[1], S1_ic_tag_wraddress[2], S1_ic_tag_wraddress[3], S1_ic_tag_wraddress[4], S1_ic_tag_wraddress[5], S1_ic_tag_wraddress[6], S1L821, S1L824, S1L827, S1L830, S1L833, S1L836, S1L839);

--S1_F_pc[1] is std_1c20:inst|cpu:the_cpu|F_pc[1]

--operation mode is normal

S1_F_pc[1] = AMPP_FUNCTION(QC2__clk0, S1L792, F1_data_out, S1_W_stall);

--BD1_q_b[1] is std_1c20:inst|cpu:the_cpu|cpu_ic_tag_module:cpu_ic_tag|altsyncram:the_altsyncram|altsyncram_09e1:auto_generated|q_b[1]

--RAM Block Operation Mode: Simple Dual-Port

--Port A Depth: 128, Port A Width: 1, Port B Depth: 128, Port B Width: 1

--Port A Logical Depth: 128, Port A Logical Width: 22, Port B Logical Depth: 128, Port B Logical Width: 22

--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered

BD1_q_b[1] = AMPP_FUNCTION(GND, GND, QC2__clk0, QC2__clk0, S1_ic_tag_wren, S1_W_stall, S1_ic_fill_valid_bits[1], S1_ic_tag_wraddress[0], S1_ic_tag_wraddress[1], S1_ic_tag_wraddress[2], S1_ic_tag_wraddress[3], S1_ic_tag_wraddress[4], S1_ic_tag_wraddress[5], S1_ic_tag_wraddress[6], S1L821, S1L824, S1L827, S1L830, S1L833, S1L836, S1L839);

--S1L841 is std_1c20:inst|cpu:the_cpu|F_ic_valid~23

--operation mode is normal

S1L841 = AMPP_FUNCTION(S1_F_pc[2], BD1_q_b[3], S1_F_pc[1], BD1_q_b[1]);

--BD1_q_b[7] is std_1c20:inst|cpu:the_cpu|cpu_ic_tag_module:cpu_ic_tag|altsyncram:the_altsyncram|altsyncram_09e1:auto_generated|q_b[7]

--RAM Block Operation Mode: Simple Dual-Port

--Port A Depth: 128, Port A Width: 1, Port B Depth: 128, Port B Width: 1

--Port A Logical Depth: 128, Port A Logical Width: 22, Port B Logical Depth: 128, Port B Logical Width: 22

--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered

BD1_q_b[7] = AMPP_FUNCTION(GND, GND, QC2__clk0, QC2__clk0, S1_ic_tag_wren, S1_W_stall, S1_ic_fill_valid_bits[7], S1_ic_tag_wraddress[0], S1_ic_tag_wraddress[1], S1_ic_tag_wraddress[2], S1_ic_tag_wraddress[3], S1_ic_tag_wraddress[4], S1_ic_tag_wraddress[5], S1_ic_tag_wraddress[6], S1L821, S1L824, S1L827, S1L830, S1L833, S1L836, S1L839);

--S1L842 is std_1c20:inst|cpu:the_cpu|F_ic_valid~24

--operation mode is normal

S1L842 = AMPP_FUNCTION(BD1_q_b[5], S1_F_pc[2], S1L841, BD1_q_b[7]);

--BD1_q_b[2] is std_1c20:inst|cpu:the_cpu|cpu_ic_tag_module:cpu_ic_tag|altsyncram:the_altsyncram|altsyncram_09e1:auto_generated|q_b[2]

--RAM Block Operation Mode: Simple Dual-Port

--Port A Depth: 128, Port A Width: 1, Port B Depth: 128, Port B Width: 1

--Port A Logical Depth: 128, Port A Logical Width: 22, Port B Logical Depth: 128, Port B Logical Width: 22

--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered

BD1_q_b[2] = AMPP_FUNCTION(GND, GND, QC2__clk0, QC2__clk0, S1_ic_tag_wren, S1_W_stall, S1_ic_fill_valid_bits[2], S1_ic_tag_wraddress[0], S1_ic_tag_wraddress[1], S1_ic_tag_wraddress[2], S1_ic_tag_wraddress[3], S1_ic_tag_wraddress[4], S1_ic_tag_wraddress[5], S1_ic_tag_wraddress[6], S1L821, S1L824, S1L827, S1L830, S1L833, S1L836, S1L839);

--BD1_q_b[4] is std_1c20:inst|cpu:the_cpu|cpu_ic_tag_module:cpu_ic_tag|altsyncram:the_altsyncram|altsyncram_09e1:auto_generated|q_b[4]

--RAM Block Operation Mode: Simple Dual-Port

--Port A Depth: 128, Port A Width: 1, Port B Depth: 128, Port B Width: 1

--Port A Logical Depth: 128, Port A Logical Width: 22, Port B Logical Depth: 128, Port B Logical Width: 22

--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered

BD1_q_b[4] = AMPP_FUNCTION(GND, GND, QC2__clk0, QC2__clk0, S1_ic_tag_wren, S1_W_stall, S1_ic_fill_valid_bits[4], S1_ic_tag_wraddress[0], S1_ic_tag_wraddress[1], S1_ic_tag_wraddress[2], S1_ic_tag_wraddress[3], S1_ic_tag_wraddress[4], S1_ic_tag_wraddress[5], S1_ic_tag_wraddress[6], S1L821, S1L824, S1L827, S1L830, S1L833, S1L836, S1L839);

--BD1_q_b[0] is std_1c20:inst|cpu:the_cpu|cpu_ic_tag_module:cpu_ic_tag|altsyncram:the_altsyncram|altsyncram_09e1:auto_generated|q_b[0]

--RAM Block Operation Mode: Simple Dual-Port

--Port A Depth: 128, Port A Width: 1, Port B Depth: 128, Port B Width: 1

--Port A Logical Depth: 128, Port A Logical Width: 22, Port B Logical Depth: 128, Port B Logical Width: 22

--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered

BD1_q_b[0] = AMPP_FUNCTION(GND, GND, QC2__clk0, QC2__clk0, S1_ic_tag_wren, S1_W_stall, S1_ic_fill_valid_bits[0], S1_ic_tag_wraddress[0], S1_ic_tag_wraddress[1], S1_ic_tag_wraddress[2], S1_ic_tag_wraddress[3], S1_ic_tag_wraddress[4], S1_ic_tag_wraddress[5], S1_ic_tag_wraddress[6], S1L821, S1L824, S1L827, S1L830, S1L833, S1L836, S1L839);

--S1L843 is std_1c20:inst|cpu:the_cpu|F_ic_valid~25

--operation mode is normal

S1L843 = AMPP_FUNCTION(S1_F_pc[1], BD1_q_b[4], S1_F_pc[2], BD1_q_b[0]);

--BD1_q_b[6] is std_1c20:inst|cpu:the_cpu|cpu_ic_tag_module:cpu_ic_tag|altsyncram:the_altsyncram|altsyncram_09e1:auto_generated|q_b[6]

--RAM Block Operation Mode: Simple Dual-Port

--Port A Depth: 128, Port A Width: 1, Port B Depth: 128, Port B Width: 1

--Port A Logical Depth: 128, Port A Logical Width: 22, Port B Logical Depth: 128, Port B Logical Width: 22

--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered

BD1_q_b[6] = AMPP_FUNCTION(GND, GND, QC2__clk0, QC2__clk0, S1_ic_tag_wren, S1_W_stall, S1_ic_fill_valid_bits[6], S1_ic_tag_wraddress[0], S1_ic_tag_wraddress[1], S1_ic_tag_wraddress[2], S1_ic_tag_wraddress[3], S1_ic_tag_wraddress[4], S1_ic_tag_wraddress[5], S1_ic_tag_wraddress[6], S1L821, S1L824, S1L827, S1L830, S1L833, S1L836, S1L839);

--S1L844 is std_1c20:inst|cpu:the_cpu|F_ic_valid~26

--operation mode is normal

S1L844 = AMPP_FUNCTION(BD1_q_b[2], S1_F_pc[1], S1L843, BD1_q_b[6]);

--S1_F_pc[0] is std_1c20:inst|cpu:the_cpu|F_pc[0]

--operation mode is normal

S1_F_pc[0] = AMPP_FUNCTION(QC2__clk0, S1L789, F1_data_out, S1_W_stall);

--S1L818 is std_1c20:inst|cpu:the_cpu|F_ic_hit~126

--operation mode is normal

S1L818 = AMPP_FUNCTION(S1L817, S1L842, S1L844, S1_F_pc[0]);

--S1_M_ctrl_invalidate_i is std_1c20:inst|cpu:the_cpu|M_ctrl_invalidate_i

--operation mode is normal

S1_M_ctrl_invalidate_i = AMPP_FUNCTION(QC2__clk0, S1_E_iw[14], S1L540, S1L541, S1L433, F1_data_out, S1_W_stall);

--S1L1006 is std_1c20:inst|cpu:the_cpu|ic_fill_prevent_refill_nxt~0

--operation mode is normal

S1L1006 = AMPP_FUNCTION(S1_M_valid_from_E, S1_M_ctrl_invalidate_i);

--S1L797 is std_1c20:inst|cpu:the_cpu|F_ic_fill_same_tag_line~197

--operation mode is normal

S1L797 = AMPP_FUNCTION(S1_F_pc[19], S1_F_pc[17], S1_ic_fill_tag[7], S1_ic_fill_tag[9]);

--S1_F_pc[9] is std_1c20:inst|cpu:the_cpu|F_pc[9]

--operation mode is normal

S1_F_pc[9] = AMPP_FUNCTION(QC2__clk0, S1L839, F1_data_out, S1_W_stall);

--S1L798 is std_1c20:inst|cpu:the_cpu|F_ic_fill_same_tag_line~198

--operation mode is normal

S1L798 = AMPP_FUNCTION(S1_F_pc[13], S1_ic_fill_line[6], S1_F_pc[9], S1_ic_fill_tag[3]);

--S1_F_pc[7] is std_1c20:inst|cpu:the_cpu|F_pc[7]

--operation mode is normal

S1_F_pc[7] = AMPP_FUNCTION(QC2__clk0, S1L833, F1_data_out, S1_W_stall);

--S1L799 is std_1c20:inst|cpu:the_cpu|F_ic_fill_same_tag_line~199

--operation mode is normal

S1L799 = AMPP_FUNCTION(S1_F_pc[21], S1_ic_fill_line[4], S1_F_pc[7], S1_ic_fill_tag[11]);

--S1_F_pc[5] is std_1c20:inst|cpu:the_cpu|F_pc[5]

--operation mode is normal

S1_F_pc[5] = AMPP_FUNCTION(QC2__clk0, S1L827, F1_data_out, S1_W_stall);

--S1L800 is std_1c20:inst|cpu:the_cpu|F_ic_fill_same_tag_line~200

--operation mode is normal

S1L800 = AMPP_FUNCTION(S1_F_pc[11], S1_ic_fill_line[2], S1_F_pc[5], S1_ic_fill_tag[1]);

--S1L801 is std_1c20:inst|cpu:the_cpu|F_ic_fill_same_tag_line~201

--operation mode is normal

S1L801 = AMPP_FUNCTION(S1L797, S1L798, S1L799, S1L800);

--S1_F_pc[3] is std_1c20:inst|cpu:the_cpu|F_pc[3]

--operation mode is normal

S1_F_pc[3] = AMPP_FUNCTION(QC2__clk0, S1L821, F1_data_out, S1_W_stall);

--S1L802 is std_1c20:inst|cpu:the_cpu|F_ic_fill_same_tag_line~202

--operation mode is normal

S1L802 = AMPP_FUNCTION(S1_F_pc[14], S1_ic_fill_line[0], S1_F_pc[3], S1_ic_fill_tag[4]);

--S1_F_pc[8] is std_1c20:inst|cpu:the_cpu|F_pc[8]

--operation mode is normal

S1_F_pc[8] = AMPP_FUNCTION(QC2__clk0, S1L836, F1_data_out, S1_W_stall);

--S1L803 is std_1c20:inst|cpu:the_cpu|F_ic_fill_same_tag_line~203

--operation mode is normal

S1L803 = AMPP_FUNCTION(S1_F_pc[18], S1_ic_fill_line[5], S1_F_pc[8], S1_ic_fill_tag[8]);

--S1L804 is std_1c20:inst|cpu:the_cpu|F_ic_fill_same_tag_line~204

--operation mode is normal

S1L804 = AMPP_FUNCTION(S1_F_pc[20], S1_F_pc[10], S1_ic_fill_tag[0], S1_ic_fill_tag[10]);

--S1_F_pc[4] is std_1c20:inst|cpu:the_cpu|F_pc[4]

--operation mode is normal

S1_F_pc[4] = AMPP_FUNCTION(QC2__clk0, S1L824, F1_data_out, S1_W_stall);

--S1L805 is std_1c20:inst|cpu:the_cpu|F_ic_fill_same_tag_line~205

--operation mode is normal

S1L805 = AMPP_FUNCTION(S1_F_pc[15], S1_ic_fill_line[1], S1_F_pc[4], S1_ic_fill_tag[5]);

--S1L806 is std_1c20:inst|cpu:the_cpu|F_ic_fill_same_tag_line~206

--operation mode is normal

S1L806 = AMPP_FUNCTION(S1L802, S1L803, S1L804, S1L805);

--S1L807 is std_1c20:inst|cpu:the_cpu|F_ic_fill_same_tag_line~207

--operation mode is normal

S1L807 = AMPP_FUNCTION(S1_F_pc[16], S1_F_pc[23], S1_ic_fill_tag[13], S1_ic_fill_tag[6]);

--S1_F_pc[6] is std_1c20:inst|cpu:the_cpu|F_pc[6]

--operation mode is normal

S1_F_pc[6] = AMPP_FUNCTION(QC2__clk0, S1L830, F1_data_out, S1_W_stall);

--S1L808 is std_1c20:inst|cpu:the_cpu|F_ic_fill_same_tag_line~208

--operation mode is normal

S1L808 = AMPP_FUNCTION(S1_F_pc[12], S1_ic_fill_line[3], S1_F_pc[6], S1_ic_fill_tag[2]);

--S1L809 is std_1c20:inst|cpu:the_cpu|F_ic_fill_same_tag_line~209

--operation mode is normal

S1L809 = AMPP_FUNCTION(S1L808, S1_F_pc[22], S1_ic_fill_tag[12]);

--S1_i_readdatavalid_d1 is std_1c20:inst|cpu:the_cpu|i_readdatavalid_d1

--operation mode is normal

S1_i_readdatavalid_d1 = AMPP_FUNCTION(QC2__clk0, U1L103, X1L8, U1L104, U1L105, F1_data_out);

--S1_D_ic_fill_starting_d1 is std_1c20:inst|cpu:the_cpu|D_ic_fill_starting_d1

--operation mode is normal

S1_D_ic_fill_starting_d1 = AMPP_FUNCTION(QC2__clk0, S1_D_ic_fill_starting, F1_data_out);

--S1_ic_fill_dp_offset[2] is std_1c20:inst|cpu:the_cpu|ic_fill_dp_offset[2]

--operation mode is normal

S1_ic_fill_dp_offset[2] = AMPP_FUNCTION(QC2__clk0, S1_ic_fill_initial_offset[2], S1_D_ic_fill_starting_d1, S1L989, F1_data_out, S1L986);

--S1_ic_fill_dp_offset[0] is std_1c20:inst|cpu:the_cpu|ic_fill_dp_offset[0]

--operation mode is normal

S1_ic_fill_dp_offset[0] = AMPP_FUNCTION(QC2__clk0, S1L987, F1_data_out, S1L986);

--S1_ic_fill_dp_offset[1] is std_1c20:inst|cpu:the_cpu|ic_fill_dp_offset[1]

--operation mode is normal

S1_ic_fill_dp_offset[1] = AMPP_FUNCTION(QC2__clk0, S1L988, F1_data_out, S1L986);

--S1L989 is std_1c20:inst|cpu:the_cpu|ic_fill_dp_offset_nxt[2]~152

--operation mode is normal

S1L989 = AMPP_FUNCTION(S1_ic_fill_dp_offset[2], S1_ic_fill_dp_offset[0], S1_ic_fill_dp_offset[1], S1_D_ic_fill_starting_d1);

--S1_ic_fill_initial_offset[2] is std_1c20:inst|cpu:the_cpu|ic_fill_initial_offset[2]

--operation mode is normal

S1_ic_fill_initial_offset[2] = AMPP_FUNCTION(QC2__clk0, S1_D_pc[2], F1_data_out, S1_D_ic_fill_starting);

--S1_ic_fill_initial_offset[1] is std_1c20:inst|cpu:the_cpu|ic_fill_initial_offset[1]

--operation mode is normal

S1_ic_fill_initial_offset[1] = AMPP_FUNCTION(QC2__clk0, S1_D_pc[1], F1_data_out, S1_D_ic_fill_starting);

--S1_ic_fill_initial_offset[0] is std_1c20:inst|cpu:the_cpu|ic_fill_initial_offset[0]

--operation mode is normal

S1_ic_fill_initial_offset[0] = AMPP_FUNCTION(QC2__clk0, S1_D_pc[0], F1_data_out, S1_D_ic_fill_starting);

--S1L970 is std_1c20:inst|cpu:the_cpu|ic_fill_active_nxt~270

--operation mode is normal

S1L970 = AMPP_FUNCTION(S1_ic_fill_dp_offset[0], S1_ic_fill_dp_offset[1], S1_ic_fill_initial_offset[1], S1_ic_fill_initial_offset[0]);

--S1L971 is std_1c20:inst|cpu:the_cpu|ic_fill_active_nxt~271

--operation mode is normal

S1L971 = AMPP_FUNCTION(S1_D_ic_fill_starting_d1, S1L989, S1_ic_fill_initial_offset[2], S1L970);

--Y1_ext_ram_bus_avalon_slave_arb_share_counter[0] is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_avalon_slave_arb_share_counter[0]

--operation mode is normal

Y1_ext_ram_bus_avalon_slave_arb_share_counter[0]_lut_out = Y1L189 # !Y1L198 & (Y1L50 # Y1L82);

Y1_ext_ram_bus_avalon_slave_arb_share_counter[0] = DFFEAS(Y1_ext_ram_bus_avalon_slave_arb_share_counter[0]_lut_out, QC2__clk0, F1_data_out, , Y1L185, , , , );

--Y1L190 is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_avalon_slave_arb_share_counter_next_value[1]~93

--operation mode is normal

Y1L190 = Y1L198 & Y1_ext_ram_bus_avalon_slave_arb_share_counter[0] & Y1_ext_ram_bus_avalon_slave_arb_share_counter[1];

--Y1L185 is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_avalon_slave_arb_counter_enable~20

--operation mode is normal

Y1L185 = !Y1L196 & (Y1L293 # !U1L5 # !Y1L300);

--Y1_ext_ram_bus_avalon_slave_saved_chosen_master_vector[3] is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_avalon_slave_saved_chosen_master_vector[3]

--operation mode is normal

Y1_ext_ram_bus_avalon_slave_saved_chosen_master_vector[3]_lut_out = Y1L50;

Y1_ext_ram_bus_avalon_slave_saved_chosen_master_vector[3] = DFFEAS(Y1_ext_ram_bus_avalon_slave_saved_chosen_master_vector[3]_lut_out, QC2__clk0, F1_data_out, , Y1L191, , , , );

--Y1_WideOr6 is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|WideOr6

--operation mode is normal

Y1_WideOr6 = Y1L52 # Y1L50 # Y1L51 # !U1L5;

--Y1_ext_ram_bus_avalon_slave_saved_chosen_master_vector[1] is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_avalon_slave_saved_chosen_master_vector[1]

--operation mode is normal

Y1_ext_ram_bus_avalon_slave_saved_chosen_master_vector[1]_lut_out = Y1L52;

Y1_ext_ram_bus_avalon_slave_saved_chosen_master_vector[1] = DFFEAS(Y1_ext_ram_bus_avalon_slave_saved_chosen_master_vector[1]_lut_out, QC2__clk0, F1_data_out, , Y1L191, , , , );

--KB1_rd_valid[2] is std_1c20:inst|sdram:the_sdram|rd_valid[2]

--operation mode is normal

KB1_rd_valid[2]_lut_out = KB1_rd_valid[1];

KB1_rd_valid[2] = DFFEAS(KB1_rd_valid[2]_lut_out, QC2__clk0, F1_data_out, , , , , , );

--WE1_stage_1 is std_1c20:inst|sdram_s1_arbitrator:the_sdram_s1|rdv_fifo_for_cpu_instruction_master_to_sdram_s1_module:rdv_fifo_for_cpu_instruction_master_to_sdram_s1|stage_1

--operation mode is normal

WE1_stage_1_lut_out = WE1_full_2 & WE1_stage_2 # !WE1_full_2 & (NB1L18);

WE1_stage_1 = DFFEAS(WE1_stage_1_lut_out, QC2__clk0, VCC, , WE1L25, , , , );

--WE1_full_1 is std_1c20:inst|sdram_s1_arbitrator:the_sdram_s1|rdv_fifo_for_cpu_instruction_master_to_sdram_s1_module:rdv_fifo_for_cpu_instruction_master_to_sdram_s1|full_1

--operation mode is normal

WE1_full_1_lut_out = KB1_za_valid & (NB1L27 & WE1_full_0 # !NB1L27 & (WE1_full_2)) # !KB1_za_valid & WE1_full_0;

WE1_full_1 = DFFEAS(WE1_full_1_lut_out, QC2__clk0, F1_data_out, , VE1L13, , , , );

--WE1_full_0 is std_1c20:inst|sdram_s1_arbitrator:the_sdram_s1|rdv_fifo_for_cpu_instruction_master_to_sdram_s1_module:rdv_fifo_for_cpu_instruction_master_to_sdram_s1|full_0

--operation mode is normal

WE1_full_0_lut_out = NB1L27 # WE1_full_1 # !KB1_za_valid;

WE1_full_0 = DFFEAS(WE1_full_0_lut_out, QC2__clk0, F1_data_out, , VE1L13, , , , );

--WE1L26 is std_1c20:inst|sdram_s1_arbitrator:the_sdram_s1|rdv_fifo_for_cpu_instruction_master_to_sdram_s1_module:rdv_fifo_for_cpu_instruction_master_to_sdram_s1|process12~3

--operation mode is normal

WE1L26 = KB1_za_valid # NB1L27 & (!WE1_full_0);

--Y1L7 is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|A_WE_StdLogicVector~4288

--operation mode is normal

Y1L7 = Y1L66 # Y1L82 # Y1L139;

--Y1L8 is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|A_WE_StdLogicVector~4290

--operation mode is normal

Y1L8 = !Y1L178 & !Y1L182 & !Y1L176 & !Y1L180;

--Y1_ext_ram_bus_avalon_slave_saved_chosen_master_vector[4] is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_avalon_slave_saved_chosen_master_vector[4]

--operation mode is normal

Y1_ext_ram_bus_avalon_slave_saved_chosen_master_vector[4]_lut_out = Y1L83;

Y1_ext_ram_bus_avalon_slave_saved_chosen_master_vector[4] = DFFEAS(Y1_ext_ram_bus_avalon_slave_saved_chosen_master_vector[4]_lut_out, QC2__clk0, F1_data_out, , Y1L191, , , , );

--Y1_ext_ram_bus_avalon_slave_saved_chosen_master_vector[2] is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_avalon_slave_saved_chosen_master_vector[2]

--operation mode is normal

Y1_ext_ram_bus_avalon_slave_saved_chosen_master_vector[2]_lut_out = Y1L82;

Y1_ext_ram_bus_avalon_slave_saved_chosen_master_vector[2] = DFFEAS(Y1_ext_ram_bus_avalon_slave_saved_chosen_master_vector[2]_lut_out, QC2__clk0, F1_data_out, , Y1L191, , , , );

--Y1_ext_ram_bus_avalon_slave_saved_chosen_master_vector[0] is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_avalon_slave_saved_chosen_master_vector[0]

--operation mode is normal

Y1_ext_ram_bus_avalon_slave_saved_chosen_master_vector[0]_lut_out = Y1L84;

Y1_ext_ram_bus_avalon_slave_saved_chosen_master_vector[0] = DFFEAS(Y1_ext_ram_bus_avalon_slave_saved_chosen_master_vector[0]_lut_out, QC2__clk0, F1_data_out, , Y1L191, , , , );

--NC1L8 is std_1c20:inst|clock_1:the_clock_1|clock_1_slave_FSM:slave_FSM|Mux2~233

--operation mode is normal

NC1L8 = NC1L7 # NC1_slave_state[2] & (!T1L10);

--N1_cpu_data_master_requests_clock_1_in is std_1c20:inst|clock_1_in_arbitrator:the_clock_1_in|cpu_data_master_requests_clock_1_in

--operation mode is normal

N1_cpu_data_master_requests_clock_1_in = S1_M_alu_result[5] & K1L3 & K1L5 & !S1_M_alu_result[17];

--NC1L9 is std_1c20:inst|clock_1:the_clock_1|clock_1_slave_FSM:slave_FSM|Mux2~234

--operation mode is normal

NC1L9 = !NC1_slave_state[1] & (T1_internal_cpu_data_master_waitrequest # !N1_cpu_data_master_requests_clock_1_in # !QB1L1);

--GC1_data_in_d1 is std_1c20:inst|clock_1:the_clock_1|clock_1_master_write_done_sync_module:clock_1_master_write_done_sync|data_in_d1

--operation mode is normal

GC1_data_in_d1_lut_out = LC1_internal_master_write_done;

GC1_data_in_d1 = DFFEAS(GC1_data_in_d1_lut_out, QC2__clk0, F1_data_out, , , , , , );

--NC1L6 is std_1c20:inst|clock_1:the_clock_1|clock_1_slave_FSM:slave_FSM|Mux1~134

--operation mode is normal

NC1L6 = NC1_slave_state[2] # NC1_slave_state[0] & (MC1_data_in_d1 $ FC1_data_out);

--NC1L5 is std_1c20:inst|clock_1:the_clock_1|clock_1_slave_FSM:slave_FSM|Mux0~141

--operation mode is normal

NC1L5 = NC1_slave_state[2] & (MC2_data_in_d1 $ GC1_data_out # !NC1_slave_state[0]) # !NC1_slave_state[2] & NC1_slave_state[0];

--NC1L4 is std_1c20:inst|clock_1:the_clock_1|clock_1_slave_FSM:slave_FSM|internal_slave_write_request~36

--operation mode is normal

NC1L4 = S1_internal_d_write & N1_cpu_data_master_requests_clock_1_in & !S1_internal_d_read & !T1_internal_cpu_data_master_waitrequest;

--FC1_data_in_d1 is std_1c20:inst|clock_1:the_clock_1|clock_1_master_read_done_sync_module:clock_1_master_read_done_sync|data_in_d1

--operation mode is normal

FC1_data_in_d1_lut_out = LC1_internal_master_read_done;

FC1_data_in_d1 = DFFEAS(FC1_data_in_d1_lut_out, QC2__clk0, F1_data_out, , , , , , );

--EC1L8 is std_1c20:inst|clock_0:the_clock_0|clock_0_slave_FSM:slave_FSM|Mux2~233

--operation mode is normal

EC1L8 = EC1L7 # EC1_slave_state[2] & (!T1L12);

--K1_cpu_data_master_requests_clock_0_in is std_1c20:inst|clock_0_in_arbitrator:the_clock_0_in|cpu_data_master_requests_clock_0_in

--operation mode is normal

K1_cpu_data_master_requests_clock_0_in = K1L3 & K1L5 & !S1_M_alu_result[17] & !S1_M_alu_result[5];

--EC1L9 is std_1c20:inst|clock_0:the_clock_0|clock_0_slave_FSM:slave_FSM|Mux2~234

--operation mode is normal

EC1L9 = !EC1_slave_state[1] & (T1_internal_cpu_data_master_waitrequest # !K1_cpu_data_master_requests_clock_0_in # !QB1L1);

--YB1_data_in_d1 is std_1c20:inst|clock_0:the_clock_0|clock_0_master_write_done_sync_module:clock_0_master_write_done_sync|data_in_d1

--operation mode is normal

YB1_data_in_d1_lut_out = CC1_internal_master_write_done;

YB1_data_in_d1 = DFFEAS(YB1_data_in_d1_lut_out, QC2__clk0, F1_data_out, , , , , , );

--EC1L6 is std_1c20:inst|clock_0:the_clock_0|clock_0_slave_FSM:slave_FSM|Mux1~129

--operation mode is normal

EC1L6 = EC1_slave_state[2] # EC1_slave_state[0] & (DC1_data_in_d1 $ XB1_data_out);

--EC1L5 is std_1c20:inst|clock_0:the_clock_0|clock_0_slave_FSM:slave_FSM|Mux0~141

--operation mode is normal

EC1L5 = EC1_slave_state[2] & (DC2_data_in_d1 $ YB1_data_out # !EC1_slave_state[0]) # !EC1_slave_state[2] & EC1_slave_state[0];

--EC1L4 is std_1c20:inst|clock_0:the_clock_0|clock_0_slave_FSM:slave_FSM|internal_slave_write_request~36

--operation mode is normal

EC1L4 = S1_internal_d_write & K1_cpu_data_master_requests_clock_0_in & !S1_internal_d_read & !T1_internal_cpu_data_master_waitrequest;

--XB1_data_in_d1 is std_1c20:inst|clock_0:the_clock_0|clock_0_master_read_done_sync_module:clock_0_master_read_done_sync|data_in_d1

--operation mode is normal

XB1_data_in_d1_lut_out = CC1_internal_master_read_done;

XB1_data_in_d1 = DFFEAS(XB1_data_in_d1_lut_out, QC2__clk0, F1_data_out, , , , , , );

--VE1_stage_1 is std_1c20:inst|sdram_s1_arbitrator:the_sdram_s1|rdv_fifo_for_cpu_data_master_to_sdram_s1_module:rdv_fifo_for_cpu_data_master_to_sdram_s1|stage_1

--operation mode is normal

VE1_stage_1_lut_out = WE1_full_2 & VE1_stage_2 # !WE1_full_2 & (NB1L14);

VE1_stage_1 = DFFEAS(VE1_stage_1_lut_out, QC2__clk0, VCC, , WE1L25, , , , );

--SD1_internal_jdo1[22] is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|internal_jdo1[22]

--operation mode is normal

SD1_internal_jdo1[22] = AMPP_FUNCTION(A1L8, SD1_sr[22], VCC, SD1L145);

--LB1_countup[4] is std_1c20:inst|sdram_pll:the_sdram_pll|countup[4]

--operation mode is arithmetic

LB1_countup[4]_carry_eqn = LB1L27;

LB1_countup[4]_lut_out = LB1_countup[4] $ (LB1_countup[4]_carry_eqn);

LB1_countup[4] = DFFEAS(LB1_countup[4]_lut_out, PLD_CLKFB, LB1_not_areset, , !LB1_count_done, , , , );

--LB1L29 is std_1c20:inst|sdram_pll:the_sdram_pll|countup[4]~594

--operation mode is arithmetic

LB1L29 = CARRY(!LB1L27 # !LB1_countup[4]);

--LB1_countup[5] is std_1c20:inst|sdram_pll:the_sdram_pll|countup[5]

--operation mode is normal

LB1_countup[5]_carry_eqn = LB1L29;

LB1_countup[5]_lut_out = LB1_countup[5] $ (!LB1_countup[5]_carry_eqn);

LB1_countup[5] = DFFEAS(LB1_countup[5]_lut_out, PLD_CLKFB, LB1_not_areset, , !LB1_count_done, , , , );

--LB1_countup[1] is std_1c20:inst|sdram_pll:the_sdram_pll|countup[1]

--operation mode is arithmetic

LB1_countup[1]_lut_out = LB1_countup[1] $ LB1_countup[0];

LB1_countup[1] = DFFEAS(LB1_countup[1]_lut_out, PLD_CLKFB, LB1_not_areset, , !LB1_count_done, , , , );

--LB1L23 is std_1c20:inst|sdram_pll:the_sdram_pll|countup[1]~596

--operation mode is arithmetic

LB1L23 = CARRY(LB1_countup[1] & LB1_countup[0]);

--LB1_countup[2] is std_1c20:inst|sdram_pll:the_sdram_pll|countup[2]

--operation mode is arithmetic

LB1_countup[2]_carry_eqn = LB1L23;

LB1_countup[2]_lut_out = LB1_countup[2] $ (LB1_countup[2]_carry_eqn);

LB1_countup[2] = DFFEAS(LB1_countup[2]_lut_out, PLD_CLKFB, LB1_not_areset, , !LB1_count_done, , , , );

--LB1L25 is std_1c20:inst|sdram_pll:the_sdram_pll|countup[2]~597

--operation mode is arithmetic

LB1L25 = CARRY(!LB1L23 # !LB1_countup[2]);

--LB1_countup[3] is std_1c20:inst|sdram_pll:the_sdram_pll|countup[3]

--operation mode is arithmetic

LB1_countup[3]_carry_eqn = LB1L25;

LB1_countup[3]_lut_out = LB1_countup[3] $ (!LB1_countup[3]_carry_eqn);

LB1_countup[3] = DFFEAS(LB1_countup[3]_lut_out, PLD_CLKFB, LB1_not_areset, , !LB1_count_done, , , , );

--LB1L27 is std_1c20:inst|sdram_pll:the_sdram_pll|countup[3]~598

--operation mode is arithmetic

LB1L27 = CARRY(LB1_countup[3] & (!LB1L25));

--LB1_countup[0] is std_1c20:inst|sdram_pll:the_sdram_pll|countup[0]

--operation mode is normal

LB1_countup[0]_lut_out = LB1_count_done $ !LB1_countup[0];

LB1_countup[0] = DFFEAS(LB1_countup[0]_lut_out, PLD_CLKFB, LB1_not_areset, , , , , , );

--LB1L31 is std_1c20:inst|sdram_pll:the_sdram_pll|Equal0~41

--operation mode is normal

LB1L31 = LB1_countup[1] & LB1_countup[2] & LB1_countup[3] & LB1_countup[0];

--LB1_not_areset is std_1c20:inst|sdram_pll:the_sdram_pll|not_areset

--operation mode is normal

LB1_not_areset_lut_out = VCC;

LB1_not_areset = DFFEAS(LB1_not_areset_lut_out, PLD_CLKFB, VCC, , , , , , );

--Q1_countup[4] is std_1c20:inst|connector_pll:the_connector_pll|countup[4]

--operation mode is arithmetic

Q1_countup[4]_carry_eqn = Q1L27;

Q1_countup[4]_lut_out = Q1_countup[4] $ (Q1_countup[4]_carry_eqn);

Q1_countup[4] = DFFEAS(Q1_countup[4]_lut_out, PLD_CLOCKINPUT[1], Q1_not_areset, , !Q1_count_done, , , , );

--Q1L29 is std_1c20:inst|connector_pll:the_connector_pll|countup[4]~594

--operation mode is arithmetic

Q1L29 = CARRY(!Q1L27 # !Q1_countup[4]);

--Q1_countup[5] is std_1c20:inst|connector_pll:the_connector_pll|countup[5]

--operation mode is normal

Q1_countup[5]_carry_eqn = Q1L29;

Q1_countup[5]_lut_out = Q1_countup[5] $ (!Q1_countup[5]_carry_eqn);

Q1_countup[5] = DFFEAS(Q1_countup[5]_lut_out, PLD_CLOCKINPUT[1], Q1_not_areset, , !Q1_count_done, , , , );

--Q1_countup[1] is std_1c20:inst|connector_pll:the_connector_pll|countup[1]

--operation mode is arithmetic

Q1_countup[1]_lut_out = Q1_countup[1] $ Q1_countup[0];

Q1_countup[1] = DFFEAS(Q1_countup[1]_lut_out, PLD_CLOCKINPUT[1], Q1_not_areset, , !Q1_count_done, , , , );

--Q1L23 is std_1c20:inst|connector_pll:the_connector_pll|countup[1]~596

--operation mode is arithmetic

Q1L23 = CARRY(Q1_countup[1] & Q1_countup[0]);

--Q1_countup[2] is std_1c20:inst|connector_pll:the_connector_pll|countup[2]

--operation mode is arithmetic

Q1_countup[2]_carry_eqn = Q1L23;

Q1_countup[2]_lut_out = Q1_countup[2] $ (Q1_countup[2]_carry_eqn);

Q1_countup[2] = DFFEAS(Q1_countup[2]_lut_out, PLD_CLOCKINPUT[1], Q1_not_areset, , !Q1_count_done, , , , );

--Q1L25 is std_1c20:inst|connector_pll:the_connector_pll|countup[2]~597

--operation mode is arithmetic

Q1L25 = CARRY(!Q1L23 # !Q1_countup[2]);

--Q1_countup[3] is std_1c20:inst|connector_pll:the_connector_pll|countup[3]

--operation mode is arithmetic

Q1_countup[3]_carry_eqn = Q1L25;

Q1_countup[3]_lut_out = Q1_countup[3] $ (!Q1_countup[3]_carry_eqn);

Q1_countup[3] = DFFEAS(Q1_countup[3]_lut_out, PLD_CLOCKINPUT[1], Q1_not_areset, , !Q1_count_done, , , , );

--Q1L27 is std_1c20:inst|connector_pll:the_connector_pll|countup[3]~598

--operation mode is arithmetic

Q1L27 = CARRY(Q1_countup[3] & (!Q1L25));

--Q1_countup[0] is std_1c20:inst|connector_pll:the_connector_pll|countup[0]

--operation mode is normal

Q1_countup[0]_lut_out = Q1_count_done $ !Q1_countup[0];

Q1_countup[0] = DFFEAS(Q1_countup[0]_lut_out, PLD_CLOCKINPUT[1], Q1_not_areset, , , , , , );

--Q1L31 is std_1c20:inst|connector_pll:the_connector_pll|Equal0~41

--operation mode is normal

Q1L31 = Q1_countup[1] & Q1_countup[2] & Q1_countup[3] & Q1_countup[0];

--Q1_not_areset is std_1c20:inst|connector_pll:the_connector_pll|not_areset

--operation mode is normal

Q1_not_areset_lut_out = VCC;

Q1_not_areset = DFFEAS(Q1_not_areset_lut_out, PLD_CLOCKINPUT[1], VCC, , , , , , );

--KB1L350 is std_1c20:inst|sdram:the_sdram|Mux40~1467

--operation mode is normal

KB1L350 = !KB1_m_state[7] & !KB1_m_state[5] & !KB1_m_state[2] & !KB1_m_state[1];

--KB1L351 is std_1c20:inst|sdram:the_sdram|Mux40~1468

--operation mode is normal

KB1L351 = !KB1_refresh_request & (!KB1L554 # !TE1L127) # !KB1L364;

--KB1L352 is std_1c20:inst|sdram:the_sdram|Mux40~1469

--operation mode is normal

KB1L352 = KB1_m_count[2] & (!KB1L350 # !KB1L176 # !KB1L348);

--KB1L353 is std_1c20:inst|sdram:the_sdram|Mux40~1470

--operation mode is normal

KB1L353 = !KB1_m_state[3] & !KB1_m_state[7] & !KB1_m_state[2] & !KB1_m_state[1];

--KB1L354 is std_1c20:inst|sdram:the_sdram|Mux40~1471

--operation mode is normal

KB1L354 = KB1L554 # !KB1L353 # !KB1_refresh_request # !TE1L127;

--KB1_m_count[0] is std_1c20:inst|sdram:the_sdram|m_count[0]

--operation mode is normal

KB1_m_count[0]_lut_out = KB1_m_state[5] & (KB1L388 & (KB1_m_count[0]) # !KB1L388 & KB1L380) # !KB1_m_state[5] & (KB1L388);

KB1_m_count[0] = DFFEAS(KB1_m_count[0]_lut_out, QC2__clk0, F1_data_out, , !KB1_m_state[6], , , , );

--KB1L355 is std_1c20:inst|sdram:the_sdram|Mux40~1472

--operation mode is normal

KB1L355 = KB1_m_count[2] & (KB1_m_count[1] # KB1_m_count[0] # !KB1L353);

--KB1L356 is std_1c20:inst|sdram:the_sdram|Mux40~1473

--operation mode is normal

KB1L356 = KB1L554 # !KB1L299 # !KB1_refresh_request # !TE1L127;

--KB1L357 is std_1c20:inst|sdram:the_sdram|Mux40~1474

--operation mode is normal

KB1L357 = KB1_m_count[2] & (KB1_m_count[1] # KB1_m_count[0] # !KB1L299);

--KB1L358 is std_1c20:inst|sdram:the_sdram|Mux40~1475

--operation mode is normal

KB1L358 = KB1_m_count[2] & (KB1_m_state[7] $ !KB1_m_state[1]);

--KB1L359 is std_1c20:inst|sdram:the_sdram|Mux40~1476

--operation mode is normal

KB1L359 = KB1_m_state[3] & (KB1_m_state[2]) # !KB1_m_state[3] & (KB1_m_state[2] & KB1L357 # !KB1_m_state[2] & (KB1L358));

--KB1L360 is std_1c20:inst|sdram:the_sdram|Mux40~1477

--operation mode is normal

KB1L360 = KB1_m_state[3] & KB1_m_count[2] & (KB1L356 # KB1L359) # !KB1_m_state[3] & (KB1L359);

--KB1L361 is std_1c20:inst|sdram:the_sdram|Mux40~1478

--operation mode is normal

KB1L361 = KB1_m_state[4] & (KB1_m_state[5]) # !KB1_m_state[4] & (KB1_m_state[5] & KB1L355 # !KB1_m_state[5] & (KB1L360));

--KB1L362 is std_1c20:inst|sdram:the_sdram|Mux40~1479

--operation mode is normal

KB1L362 = KB1_m_state[4] & KB1_m_count[2] & (KB1L354 # KB1L361) # !KB1_m_state[4] & (KB1L361);

--KB1L363 is std_1c20:inst|sdram:the_sdram|Mux40~1480

--operation mode is normal

KB1L363 = KB1_m_state[8] & (!KB1_m_state[0]) # !KB1_m_state[8] & (KB1_m_state[0] & (KB1L362) # !KB1_m_state[0] & KB1L352);

--KB1L366 is std_1c20:inst|sdram:the_sdram|Mux41~1467

--operation mode is normal

KB1L366 = KB1L554 # !KB1L377 # !KB1_refresh_request # !TE1L127;

--KB1L367 is std_1c20:inst|sdram:the_sdram|Mux41~1468

--operation mode is normal

KB1L367 = KB1_m_count[1] & (!KB1L222 # !KB1L350 # !KB1L365);

--KB1L368 is std_1c20:inst|sdram:the_sdram|Mux41~1469

--operation mode is normal

KB1L368 = TE1L127 & KB1_refresh_request & KB1L350 & !KB1L554;

--KB1L369 is std_1c20:inst|sdram:the_sdram|Mux41~1470

--operation mode is normal

KB1L369 = !KB1_m_state[5] & !KB1_m_state[2];

--KB1L370 is std_1c20:inst|sdram:the_sdram|Mux41~1471

--operation mode is normal

KB1L370 = KB1_m_state[1] & (KB1_m_state[5] # KB1_m_state[2]) # !KB1_m_state[1] & !KB1_m_count[0] & (KB1_m_state[5] $ KB1_m_state[2]);

--KB1L371 is std_1c20:inst|sdram:the_sdram|Mux41~1472

--operation mode is normal

KB1L371 = KB1L370 & (KB1_m_count[1] # KB1_m_count[2]);

--KB1L372 is std_1c20:inst|sdram:the_sdram|Mux41~1473

--operation mode is normal

KB1L372 = KB1_m_state[7] & KB1_m_state[1] # !KB1_m_state[7] & (KB1_m_state[1] & KB1_m_count[1] & KB1L371 # !KB1_m_state[1] & (KB1_m_count[1] $ KB1L371));

--KB1L373 is std_1c20:inst|sdram:the_sdram|Mux41~1474

--operation mode is normal

KB1L373 = KB1_m_state[7] & (KB1_m_count[1] # KB1L369 & !KB1L372) # !KB1_m_state[7] & (KB1L372);

--KB1L374 is std_1c20:inst|sdram:the_sdram|Mux41~1475

--operation mode is normal

KB1L374 = KB1_m_state[3] & (!KB1_m_state[0]) # !KB1_m_state[3] & (KB1_m_state[0] & (KB1L373) # !KB1_m_state[0] & KB1L378);

--KB1L375 is std_1c20:inst|sdram:the_sdram|Mux41~1476

--operation mode is normal

KB1L375 = KB1_m_state[3] & (KB1_m_count[1] # KB1L368 & !KB1L374) # !KB1_m_state[3] & (KB1L374);

--KB1L376 is std_1c20:inst|sdram:the_sdram|Mux41~1477

--operation mode is normal

KB1L376 = KB1_m_state[4] & (KB1_m_state[8]) # !KB1_m_state[4] & (KB1_m_state[8] & KB1L367 # !KB1_m_state[8] & (KB1L375));

--KB1_i_next[0] is std_1c20:inst|sdram:the_sdram|i_next[0]

--operation mode is normal

KB1_i_next[0]_lut_out = KB1_i_state[2] # RD1L26 & !KB1_i_refs[1] & !KB1_i_refs[2];

KB1_i_next[0] = DFFEAS(KB1_i_next[0]_lut_out, QC2__clk0, F1_data_out, , RD1L27, , , , );

--KB1_i_count[2] is std_1c20:inst|sdram:the_sdram|i_count[2]

--operation mode is normal

KB1_i_count[2]_lut_out = KB1_i_state[0] & KB1_i_state[1] & (KB1_i_state[2] # KB1L242);

KB1_i_count[2] = DFFEAS(KB1_i_count[2]_lut_out, QC2__clk0, F1_data_out, , KB1L243, , , , );

--KB1_i_count[1] is std_1c20:inst|sdram:the_sdram|i_count[1]

--operation mode is normal

KB1_i_count[1]_lut_out = KB1_i_state[1] & !KB1_i_state[2] & (KB1L244 # !KB1_i_state[0]);

KB1_i_count[1] = DFFEAS(KB1_i_count[1]_lut_out, QC2__clk0, F1_data_out, , KB1L243, , , , );

--KB1L148 is std_1c20:inst|sdram:the_sdram|LessThan0~45

--operation mode is normal

KB1L148 = KB1_i_count[2] # KB1_i_count[1];

--KB1L240 is std_1c20:inst|sdram:the_sdram|Mux9~225

--operation mode is normal

KB1L240 = KB1_i_state[1] & (!KB1_i_state[2]);

--KB1L241 is std_1c20:inst|sdram:the_sdram|Mux9~226

--operation mode is normal

KB1L241 = KB1_i_state[0] & (KB1_i_next[0] # KB1L148 # !KB1L240);

--KB1L138 is std_1c20:inst|sdram:the_sdram|i_refs[0]~286

--operation mode is normal

KB1L138 = !KB1_i_state[0] & !KB1_i_state[2];

--KB1L238 is std_1c20:inst|sdram:the_sdram|Mux7~97

--operation mode is normal

KB1L238 = KB1_i_next[0] & (!KB1_i_count[2] & !KB1_i_count[1]);

--KB1_i_next[1] is std_1c20:inst|sdram:the_sdram|i_next[1]

--operation mode is normal

KB1_i_next[1]_lut_out = !KB1_i_state[2];

KB1_i_next[1] = DFFEAS(KB1_i_next[1]_lut_out, QC2__clk0, F1_data_out, , RD1L27, , , , );

--KB1L239 is std_1c20:inst|sdram:the_sdram|Mux8~208

--operation mode is normal

KB1L239 = KB1_i_count[2] # KB1_i_count[1] # KB1_i_next[1];

--KB1L74 is std_1c20:inst|sdram:the_sdram|Add0~218

--operation mode is arithmetic

KB1L74_carry_eqn = KB1L81;

KB1L74 = KB1_refresh_counter[3] $ (KB1L74_carry_eqn);

--KB1L75 is std_1c20:inst|sdram:the_sdram|Add0~219

--operation mode is arithmetic

KB1L75 = CARRY(KB1_refresh_counter[3] & (!KB1L81));

--KB1L76 is std_1c20:inst|sdram:the_sdram|Add0~220

--operation mode is arithmetic

KB1L76 = !KB1_refresh_counter[0];

--KB1L77 is std_1c20:inst|sdram:the_sdram|Add0~221

--operation mode is arithmetic

KB1L77 = CARRY(KB1_refresh_counter[0]);

--KB1L78 is std_1c20:inst|sdram:the_sdram|Add0~222

--operation mode is arithmetic

KB1L78_carry_eqn = KB1L77;

KB1L78 = KB1_refresh_counter[1] $ (!KB1L78_carry_eqn);

--KB1L79 is std_1c20:inst|sdram:the_sdram|Add0~223

--operation mode is arithmetic

KB1L79 = CARRY(!KB1_refresh_counter[1] & (!KB1L77));

--KB1L80 is std_1c20:inst|sdram:the_sdram|Add0~224

--operation mode is arithmetic

KB1L80_carry_eqn = KB1L79;

KB1L80 = KB1_refresh_counter[2] $ (KB1L80_carry_eqn);

--KB1L81 is std_1c20:inst|sdram:the_sdram|Add0~225

--operation mode is arithmetic

KB1L81 = CARRY(KB1_refresh_counter[2] # !KB1L79);

--KB1L82 is std_1c20:inst|sdram:the_sdram|Add0~226

--operation mode is arithmetic

KB1L82_carry_eqn = KB1L89;

KB1L82 = KB1_refresh_counter[7] $ (KB1L82_carry_eqn);

--KB1L83 is std_1c20:inst|sdram:the_sdram|Add0~227

--operation mode is arithmetic

KB1L83 = CARRY(KB1_refresh_counter[7] & (!KB1L89));

--KB1L84 is std_1c20:inst|sdram:the_sdram|Add0~228

--operation mode is arithmetic

KB1L84_carry_eqn = KB1L75;

KB1L84 = KB1_refresh_counter[4] $ (KB1L84_carry_eqn);

--KB1L85 is std_1c20:inst|sdram:the_sdram|Add0~229

--operation mode is arithmetic

KB1L85 = CARRY(KB1_refresh_counter[4] # !KB1L75);

--KB1L86 is std_1c20:inst|sdram:the_sdram|Add0~230

--operation mode is arithmetic

KB1L86_carry_eqn = KB1L85;

KB1L86 = KB1_refresh_counter[5] $ (!KB1L86_carry_eqn);

--KB1L87 is std_1c20:inst|sdram:the_sdram|Add0~231

--operation mode is arithmetic

KB1L87 = CARRY(!KB1_refresh_counter[5] & (!KB1L85));

--KB1L88 is std_1c20:inst|sdram:the_sdram|Add0~232

--operation mode is arithmetic

KB1L88_carry_eqn = KB1L87;

KB1L88 = KB1_refresh_counter[6] $ (KB1L88_carry_eqn);

--KB1L89 is std_1c20:inst|sdram:the_sdram|Add0~233

--operation mode is arithmetic

KB1L89 = CARRY(KB1_refresh_counter[6] # !KB1L87);

--KB1L90 is std_1c20:inst|sdram:the_sdram|Add0~234

--operation mode is normal

KB1L90_carry_eqn = KB1L98;

KB1L90 = KB1_refresh_counter[12] $ (!KB1L90_carry_eqn);

--KB1L91 is std_1c20:inst|sdram:the_sdram|Add0~236

--operation mode is arithmetic

KB1L91_carry_eqn = KB1L83;

KB1L91 = KB1_refresh_counter[8] $ (!KB1L91_carry_eqn);

--KB1L92 is std_1c20:inst|sdram:the_sdram|Add0~237

--operation mode is arithmetic

KB1L92 = CARRY(!KB1L83 # !KB1_refresh_counter[8]);

--KB1L93 is std_1c20:inst|sdram:the_sdram|Add0~238

--operation mode is arithmetic

KB1L93_carry_eqn = KB1L92;

KB1L93 = KB1_refresh_counter[9] $ (KB1L93_carry_eqn);

--KB1L94 is std_1c20:inst|sdram:the_sdram|Add0~239

--operation mode is arithmetic

KB1L94 = CARRY(KB1_refresh_counter[9] & (!KB1L92));

--KB1L95 is std_1c20:inst|sdram:the_sdram|Add0~240

--operation mode is arithmetic

KB1L95_carry_eqn = KB1L94;

KB1L95 = KB1_refresh_counter[10] $ (KB1L95_carry_eqn);

--KB1L96 is std_1c20:inst|sdram:the_sdram|Add0~241

--operation mode is arithmetic

KB1L96 = CARRY(KB1_refresh_counter[10] # !KB1L94);

--KB1L97 is std_1c20:inst|sdram:the_sdram|Add0~242

--operation mode is arithmetic

KB1L97_carry_eqn = KB1L96;

KB1L97 = KB1_refresh_counter[11] $ (!KB1L97_carry_eqn);

--KB1L98 is std_1c20:inst|sdram:the_sdram|Add0~243

--operation mode is arithmetic

KB1L98 = CARRY(!KB1_refresh_counter[11] & (!KB1L96));

--KB1L270 is std_1c20:inst|sdram:the_sdram|Mux21~1084

--operation mode is normal

KB1L270 = !KB1_m_state[2] & (KB1_m_state[7] $ !KB1_m_state[0]);

--KB1L271 is std_1c20:inst|sdram:the_sdram|Mux21~1085

--operation mode is normal

KB1L271 = KB1L246 & KB1L270 & !KB1_m_state[4] & !KB1_m_state[6];

--ZE1_do_load_shifter is std_1c20:inst|uart1:the_uart1|uart1_tx:the_uart1_tx|do_load_shifter

--operation mode is normal

ZE1_do_load_shifter_lut_out = !ZE1_unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out[0] & (ZE1L28 & ZE1_internal_tx_ready);

ZE1_do_load_shifter = DFFEAS(ZE1_do_load_shifter_lut_out, QC2__clk0, F1_data_out, , , , , , );

--ZE1_baud_clk_en is std_1c20:inst|uart1:the_uart1|uart1_tx:the_uart1_tx|baud_clk_en

--operation mode is normal

ZE1_baud_clk_en_lut_out = ZE1L21 & ZE1L22 & (!ZE1_baud_rate_counter[8]);

ZE1_baud_clk_en = DFFEAS(ZE1_baud_clk_en_lut_out, QC2__clk0, F1_data_out, , , , , , );

--ZE1L42 is std_1c20:inst|uart1:the_uart1|uart1_tx:the_uart1_tx|unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out[3]~2822

--operation mode is normal

ZE1L42 = ZE1_do_load_shifter # ZE1_baud_clk_en & (ZE1_unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out[0] # !ZE1L28);

--XE1_internal_tx_data[2] is std_1c20:inst|uart1:the_uart1|uart1_regs:the_uart1_regs|internal_tx_data[2]

--operation mode is normal

XE1_internal_tx_data[2]_lut_out = S1_M_st_data[2];

XE1_internal_tx_data[2] = DFFEAS(XE1_internal_tx_data[2]_lut_out, QC2__clk0, F1_data_out, , XE1L64, , , , );

--XE1_internal_tx_data[1] is std_1c20:inst|uart1:the_uart1|uart1_regs:the_uart1_regs|internal_tx_data[1]

--operation mode is normal

XE1_internal_tx_data[1]_lut_out = S1_M_st_data[1];

XE1_internal_tx_data[1] = DFFEAS(XE1_internal_tx_data[1]_lut_out, QC2__clk0, F1_data_out, , XE1L64, , , , );

--XE1_internal_tx_data[0] is std_1c20:inst|uart1:the_uart1|uart1_regs:the_uart1_regs|internal_tx_data[0]

--operation mode is normal

XE1_internal_tx_data[0]_lut_out = S1_M_st_data[0];

XE1_internal_tx_data[0] = DFFEAS(XE1_internal_tx_data[0]_lut_out, QC2__clk0, F1_data_out, , XE1L64, , , , );

--XE1_internal_tx_data[3] is std_1c20:inst|uart1:the_uart1|uart1_regs:the_uart1_regs|internal_tx_data[3]

--operation mode is normal

XE1_internal_tx_data[3]_lut_out = S1_M_st_data[3];

XE1_internal_tx_data[3] = DFFEAS(XE1_internal_tx_data[3]_lut_out, QC2__clk0, F1_data_out, , XE1L64, , , , );

--XE1_internal_tx_data[4] is std_1c20:inst|uart1:the_uart1|uart1_regs:the_uart1_regs|internal_tx_data[4]

--operation mode is normal

XE1_internal_tx_data[4]_lut_out = S1_M_st_data[4];

XE1_internal_tx_data[4] = DFFEAS(XE1_internal_tx_data[4]_lut_out, QC2__clk0, F1_data_out, , XE1L64, , , , );

--XE1_internal_tx_data[5] is std_1c20:inst|uart1:the_uart1|uart1_regs:the_uart1_regs|internal_tx_data[5]

--operation mode is normal

XE1_internal_tx_data[5]_lut_out = S1_M_st_data[5];

XE1_internal_tx_data[5] = DFFEAS(XE1_internal_tx_data[5]_lut_out, QC2__clk0, F1_data_out, , XE1L64, , , , );

--XE1_internal_tx_data[6] is std_1c20:inst|uart1:the_uart1|uart1_regs:the_uart1_regs|internal_tx_data[6]

--operation mode is normal

XE1_internal_tx_data[6]_lut_out = S1_M_st_data[6];

XE1_internal_tx_data[6] = DFFEAS(XE1_internal_tx_data[6]_lut_out, QC2__clk0, F1_data_out, , XE1L64, , , , );

--XE1_internal_tx_data[7] is std_1c20:inst|uart1:the_uart1|uart1_regs:the_uart1_regs|internal_tx_data[7]

--operation mode is normal

XE1_internal_tx_data[7]_lut_out = S1_M_st_data[7];

XE1_internal_tx_data[7] = DFFEAS(XE1_internal_tx_data[7]_lut_out, QC2__clk0, F1_data_out, , XE1L64, , , , );

--G1_edge_capture[3] is std_1c20:inst|button_pio:the_button_pio|edge_capture[3]

--operation mode is normal

G1_edge_capture[3]_lut_out = G1L17 & (!G1L16 # !H1_cpu_data_master_requests_button_pio_s1 # !S1_M_alu_result[2]);

G1_edge_capture[3] = DFFEAS(G1_edge_capture[3]_lut_out, QC2__clk0, F1_data_out, , , , , , );

--G1_edge_capture[1] is std_1c20:inst|button_pio:the_button_pio|edge_capture[1]

--operation mode is normal

G1_edge_capture[1]_lut_out = G1L18 & (!G1L16 # !H1_cpu_data_master_requests_button_pio_s1 # !S1_M_alu_result[2]);

G1_edge_capture[1] = DFFEAS(G1_edge_capture[1]_lut_out, QC2__clk0, F1_data_out, , , , , , );

--G1_irq_mask[1] is std_1c20:inst|button_pio:the_button_pio|irq_mask[1]

--operation mode is normal

G1_irq_mask[1]_lut_out = S1_M_st_data[1];

G1_irq_mask[1] = DFFEAS(G1_irq_mask[1]_lut_out, QC2__clk0, F1_data_out, , G1L26, , , , );

--G1_irq_mask[3] is std_1c20:inst|button_pio:the_button_pio|irq_mask[3]

--operation mode is normal

G1_irq_mask[3]_lut_out = S1_M_st_data[3];

G1_irq_mask[3] = DFFEAS(G1_irq_mask[3]_lut_out, QC2__clk0, F1_data_out, , G1L26, , , , );

--S1L1130 is std_1c20:inst|cpu:the_cpu|M_ipending_reg_nxt[2]~201

--operation mode is normal

S1L1130 = AMPP_FUNCTION(G1_edge_capture[3], G1_edge_capture[1], G1_irq_mask[1], G1_irq_mask[3]);

--G1_edge_capture[2] is std_1c20:inst|button_pio:the_button_pio|edge_capture[2]

--operation mode is normal

G1_edge_capture[2]_lut_out = G1L19 & (!G1L16 # !H1_cpu_data_master_requests_button_pio_s1 # !S1_M_alu_result[2]);

G1_edge_capture[2] = DFFEAS(G1_edge_capture[2]_lut_out, QC2__clk0, F1_data_out, , , , , , );

--G1_edge_capture[0] is std_1c20:inst|button_pio:the_button_pio|edge_capture[0]

--operation mode is normal

G1_edge_capture[0]_lut_out = G1L20 & (!G1L16 # !H1_cpu_data_master_requests_button_pio_s1 # !S1_M_alu_result[2]);

G1_edge_capture[0] = DFFEAS(G1_edge_capture[0]_lut_out, QC2__clk0, F1_data_out, , , , , , );

--G1_irq_mask[0] is std_1c20:inst|button_pio:the_button_pio|irq_mask[0]

--operation mode is normal

G1_irq_mask[0]_lut_out = S1_M_st_data[0];

G1_irq_mask[0] = DFFEAS(G1_irq_mask[0]_lut_out, QC2__clk0, F1_data_out, , G1L26, , , , );

--G1_irq_mask[2] is std_1c20:inst|button_pio:the_button_pio|irq_mask[2]

--operation mode is normal

G1_irq_mask[2]_lut_out = S1_M_st_data[2];

G1_irq_mask[2] = DFFEAS(G1_irq_mask[2]_lut_out, QC2__clk0, F1_data_out, , G1L26, , , , );

--S1L1131 is std_1c20:inst|cpu:the_cpu|M_ipending_reg_nxt[2]~202

--operation mode is normal

S1L1131 = AMPP_FUNCTION(G1_edge_capture[2], G1_edge_capture[0], G1_irq_mask[0], G1_irq_mask[2]);

--FD1_internal_oci_ienable1[2] is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_avalon_reg:the_cpu_nios2_avalon_reg|internal_oci_ienable1[2]

--operation mode is normal

FD1_internal_oci_ienable1[2] = AMPP_FUNCTION(QC2__clk0, S1_M_st_data[2], F1_data_out, FD1L13);

--S1_E_iw[6] is std_1c20:inst|cpu:the_cpu|E_iw[6]

--operation mode is normal

S1_E_iw[6] = AMPP_FUNCTION(QC2__clk0, S1_D_iw[6], F1_data_out, S1_W_stall);

--S1_E_iw[7] is std_1c20:inst|cpu:the_cpu|E_iw[7]

--operation mode is normal

S1_E_iw[7] = AMPP_FUNCTION(QC2__clk0, S1_D_iw[7], F1_data_out, S1_W_stall);

--S1_E_ctrl_wrctl_inst is std_1c20:inst|cpu:the_cpu|E_ctrl_wrctl_inst

--operation mode is normal

S1_E_ctrl_wrctl_inst = AMPP_FUNCTION(QC2__clk0, S1L776, F1_data_out, S1_W_stall);

--S1_E_iw[8] is std_1c20:inst|cpu:the_cpu|E_iw[8]

--operation mode is normal

S1_E_iw[8] = AMPP_FUNCTION(QC2__clk0, S1_D_iw[8], F1_data_out, S1_W_stall);

--S1L757 is std_1c20:inst|cpu:the_cpu|E_wrctl_bstatus~13

--operation mode is normal

S1L757 = AMPP_FUNCTION(S1_E_iw[7], S1_E_ctrl_wrctl_inst, S1_E_iw[8]);

--S1L1117 is std_1c20:inst|cpu:the_cpu|M_ienable_reg[2]~4

--operation mode is normal

S1L1117 = AMPP_FUNCTION(S1L752, S1_E_iw[6], S1L757, S1_W_stall);

--AD1_q_b[8] is std_1c20:inst|cpu:the_cpu|cpu_ic_data_module:cpu_ic_data|altsyncram:the_altsyncram|altsyncram_qmb1:auto_generated|q_b[8]

--RAM Block Operation Mode: Simple Dual-Port

--Port A Depth: 1024, Port A Width: 1, Port B Depth: 1024, Port B Width: 1

--Port A Logical Depth: 1024, Port A Logical Width: 32, Port B Logical Depth: 1024, Port B Logical Width: 32

--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered

AD1_q_b[8] = AMPP_FUNCTION(GND, GND, QC2__clk0, QC2__clk0, S1_i_readdatavalid_d1, S1_W_stall, S1_i_readdata_d1[8], S1_ic_fill_dp_offset[0], S1_ic_fill_dp_offset[1], S1_ic_fill_dp_offset[2], S1_ic_fill_line[0], S1_ic_fill_line[1], S1_ic_fill_line[2], S1_ic_fill_line[3], S1_ic_fill_line[4], S1_ic_fill_line[5], S1_ic_fill_line[6], S1L789, S1L792, S1L795, S1L821, S1L824, S1L827, S1L830, S1L833, S1L836, S1L839);

--S1_M_status_reg_pie is std_1c20:inst|cpu:the_cpu|M_status_reg_pie

--operation mode is normal

S1_M_status_reg_pie = AMPP_FUNCTION(QC2__clk0, S1L1272, S1L1277, S1L1274, S1L1275, F1_data_out);

--S1L1061 is std_1c20:inst|cpu:the_cpu|intr_req~83

--operation mode is normal

S1L1061 = AMPP_FUNCTION(S1_M_ipending_reg[2], S1_M_ipending_reg[3], S1_M_ipending_reg[5], S1_M_ipending_reg[4]);

--S1_M_ipending_reg[1] is std_1c20:inst|cpu:the_cpu|M_ipending_reg[1]

--operation mode is normal

S1_M_ipending_reg[1] = AMPP_FUNCTION(QC2__clk0, S1_M_ienable_reg[1], BB1L49, T1L287, FD1_internal_oci_ienable1[1], F1_data_out);

--S1_M_ipending_reg[0] is std_1c20:inst|cpu:the_cpu|M_ipending_reg[0]

--operation mode is normal

S1_M_ipending_reg[0] = AMPP_FUNCTION(QC2__clk0, S1_M_ienable_reg[0], RB1_control_register[0], RB1_timeout_occurred, FD1_internal_oci_ienable1[0], F1_data_out);

--S1L1062 is std_1c20:inst|cpu:the_cpu|intr_req~84

--operation mode is normal

S1L1062 = AMPP_FUNCTION(S1_M_ipending_reg[6], S1L1061, S1_M_ipending_reg[1], S1_M_ipending_reg[0]);

--S1L845 is std_1c20:inst|cpu:the_cpu|F_iw~0

--operation mode is normal

S1L845 = AMPP_FUNCTION(S1_latched_oci_tb_hbreak_req, S1_hbreak_enabled);

--AD1_q_b[7] is std_1c20:inst|cpu:the_cpu|cpu_ic_data_module:cpu_ic_data|altsyncram:the_altsyncram|altsyncram_qmb1:auto_generated|q_b[7]

--RAM Block Operation Mode: Simple Dual-Port

--Port A Depth: 1024, Port A Width: 1, Port B Depth: 1024, Port B Width: 1

--Port A Logical Depth: 1024, Port A Logical Width: 32, Port B Logical Depth: 1024, Port B Logical Width: 32

--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered

AD1_q_b[7] = AMPP_FUNCTION(GND, GND, QC2__clk0, QC2__clk0, S1_i_readdatavalid_d1, S1_W_stall, S1_i_readdata_d1[7], S1_ic_fill_dp_offset[0], S1_ic_fill_dp_offset[1], S1_ic_fill_dp_offset[2], S1_ic_fill_line[0], S1_ic_fill_line[1], S1_ic_fill_line[2], S1_ic_fill_line[3], S1_ic_fill_line[4], S1_ic_fill_line[5], S1_ic_fill_line[6], S1L789, S1L792, S1L795, S1L821, S1L824, S1L827, S1L830, S1L833, S1L836, S1L839);

--AD1_q_b[6] is std_1c20:inst|cpu:the_cpu|cpu_ic_data_module:cpu_ic_data|altsyncram:the_altsyncram|altsyncram_qmb1:auto_generated|q_b[6]

--RAM Block Operation Mode: Simple Dual-Port

--Port A Depth: 1024, Port A Width: 1, Port B Depth: 1024, Port B Width: 1

--Port A Logical Depth: 1024, Port A Logical Width: 32, Port B Logical Depth: 1024, Port B Logical Width: 32

--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered

AD1_q_b[6] = AMPP_FUNCTION(GND, GND, QC2__clk0, QC2__clk0, S1_i_readdatavalid_d1, S1_W_stall, U1L26, S1_ic_fill_dp_offset[0], S1_ic_fill_dp_offset[1], S1_ic_fill_dp_offset[2], S1_ic_fill_line[0], S1_ic_fill_line[1], S1_ic_fill_line[2], S1_ic_fill_line[3], S1_ic_fill_line[4], S1_ic_fill_line[5], S1_ic_fill_line[6], S1L789, S1L792, S1L795, S1L821, S1L824, S1L827, S1L830, S1L833, S1L836, S1L839);

--AD1_q_b[4] is std_1c20:inst|cpu:the_cpu|cpu_ic_data_module:cpu_ic_data|altsyncram:the_altsyncram|altsyncram_qmb1:auto_generated|q_b[4]

--RAM Block Operation Mode: Simple Dual-Port

--Port A Depth: 1024, Port A Width: 1, Port B Depth: 1024, Port B Width: 1

--Port A Logical Depth: 1024, Port A Logical Width: 32, Port B Logical Depth: 1024, Port B Logical Width: 32

--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered

AD1_q_b[4] = AMPP_FUNCTION(GND, GND, QC2__clk0, QC2__clk0, S1_i_readdatavalid_d1, S1_W_stall, U1L20, S1_ic_fill_dp_offset[0], S1_ic_fill_dp_offset[1], S1_ic_fill_dp_offset[2], S1_ic_fill_line[0], S1_ic_fill_line[1], S1_ic_fill_line[2], S1_ic_fill_line[3], S1_ic_fill_line[4], S1_ic_fill_line[5], S1_ic_fill_line[6], S1L789, S1L792, S1L795, S1L821, S1L824, S1L827, S1L830, S1L833, S1L836, S1L839);

--AD1_q_b[15] is std_1c20:inst|cpu:the_cpu|cpu_ic_data_module:cpu_ic_data|altsyncram:the_altsyncram|altsyncram_qmb1:auto_generated|q_b[15]

--RAM Block Operation Mode: Simple Dual-Port

--Port A Depth: 1024, Port A Width: 1, Port B Depth: 1024, Port B Width: 1

--Port A Logical Depth: 1024, Port A Logical Width: 32, Port B Logical Depth: 1024, Port B Logical Width: 32

--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered

AD1_q_b[15] = AMPP_FUNCTION(GND, GND, QC2__clk0, QC2__clk0, S1_i_readdatavalid_d1, S1_W_stall, S1_i_readdata_d1[15], S1_ic_fill_dp_offset[0], S1_ic_fill_dp_offset[1], S1_ic_fill_dp_offset[2], S1_ic_fill_line[0], S1_ic_fill_line[1], S1_ic_fill_line[2], S1_ic_fill_line[3], S1_ic_fill_line[4], S1_ic_fill_line[5], S1_ic_fill_line[6], S1L789, S1L792, S1L795, S1L821, S1L824, S1L827, S1L830, S1L833, S1L836, S1L839);

--AD1_q_b[0] is std_1c20:inst|cpu:the_cpu|cpu_ic_data_module:cpu_ic_data|altsyncram:the_altsyncram|altsyncram_qmb1:auto_generated|q_b[0]

--RAM Block Operation Mode: Simple Dual-Port

--Port A Depth: 1024, Port A Width: 1, Port B Depth: 1024, Port B Width: 1

--Port A Logical Depth: 1024, Port A Logical Width: 32, Port B Logical Depth: 1024, Port B Logical Width: 32

--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered

AD1_q_b[0] = AMPP_FUNCTION(GND, GND, QC2__clk0, QC2__clk0, S1_i_readdatavalid_d1, S1_W_stall, U1L8, S1_ic_fill_dp_offset[0], S1_ic_fill_dp_offset[1], S1_ic_fill_dp_offset[2], S1_ic_fill_line[0], S1_ic_fill_line[1], S1_ic_fill_line[2], S1_ic_fill_line[3], S1_ic_fill_line[4], S1_ic_fill_line[5], S1_ic_fill_line[6], S1L789, S1L792, S1L795, S1L821, S1L824, S1L827, S1L830, S1L833, S1L836, S1L839);

--AD1_q_b[1] is std_1c20:inst|cpu:the_cpu|cpu_ic_data_module:cpu_ic_data|altsyncram:the_altsyncram|altsyncram_qmb1:auto_generated|q_b[1]

--RAM Block Operation Mode: Simple Dual-Port

--Port A Depth: 1024, Port A Width: 1, Port B Depth: 1024, Port B Width: 1

--Port A Logical Depth: 1024, Port A Logical Width: 32, Port B Logical Depth: 1024, Port B Logical Width: 32

--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered

AD1_q_b[1] = AMPP_FUNCTION(GND, GND, QC2__clk0, QC2__clk0, S1_i_readdatavalid_d1, S1_W_stall, U1L11, S1_ic_fill_dp_offset[0], S1_ic_fill_dp_offset[1], S1_ic_fill_dp_offset[2], S1_ic_fill_line[0], S1_ic_fill_line[1], S1_ic_fill_line[2], S1_ic_fill_line[3], S1_ic_fill_line[4], S1_ic_fill_line[5], S1_ic_fill_line[6], S1L789, S1L792, S1L795, S1L821, S1L824, S1L827, S1L830, S1L833, S1L836, S1L839);

--AD1_q_b[2] is std_1c20:inst|cpu:the_cpu|cpu_ic_data_module:cpu_ic_data|altsyncram:the_altsyncram|altsyncram_qmb1:auto_generated|q_b[2]

--RAM Block Operation Mode: Simple Dual-Port

--Port A Depth: 1024, Port A Width: 1, Port B Depth: 1024, Port B Width: 1

--Port A Logical Depth: 1024, Port A Logical Width: 32, Port B Logical Depth: 1024, Port B Logical Width: 32

--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered

AD1_q_b[2] = AMPP_FUNCTION(GND, GND, QC2__clk0, QC2__clk0, S1_i_readdatavalid_d1, S1_W_stall, U1L14, S1_ic_fill_dp_offset[0], S1_ic_fill_dp_offset[1], S1_ic_fill_dp_offset[2], S1_ic_fill_line[0], S1_ic_fill_line[1], S1_ic_fill_line[2], S1_ic_fill_line[3], S1_ic_fill_line[4], S1_ic_fill_line[5], S1_ic_fill_line[6], S1L789, S1L792, S1L795, S1L821, S1L824, S1L827, S1L830, S1L833, S1L836, S1L839);

--AD1_q_b[3] is std_1c20:inst|cpu:the_cpu|cpu_ic_data_module:cpu_ic_data|altsyncram:the_altsyncram|altsyncram_qmb1:auto_generated|q_b[3]

--RAM Block Operation Mode: Simple Dual-Port

--Port A Depth: 1024, Port A Width: 1, Port B Depth: 1024, Port B Width: 1

--Port A Logical Depth: 1024, Port A Logical Width: 32, Port B Logical Depth: 1024, Port B Logical Width: 32

--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered

AD1_q_b[3] = AMPP_FUNCTION(GND, GND, QC2__clk0, QC2__clk0, S1_i_readdatavalid_d1, S1_W_stall, U1L17, S1_ic_fill_dp_offset[0], S1_ic_fill_dp_offset[1], S1_ic_fill_dp_offset[2], S1_ic_fill_line[0], S1_ic_fill_line[1], S1_ic_fill_line[2], S1_ic_fill_line[3], S1_ic_fill_line[4], S1_ic_fill_line[5], S1_ic_fill_line[6], S1L789, S1L792, S1L795, S1L821, S1L824, S1L827, S1L830, S1L833, S1L836, S1L839);

--AD1_q_b[5] is std_1c20:inst|cpu:the_cpu|cpu_ic_data_module:cpu_ic_data|altsyncram:the_altsyncram|altsyncram_qmb1:auto_generated|q_b[5]

--RAM Block Operation Mode: Simple Dual-Port

--Port A Depth: 1024, Port A Width: 1, Port B Depth: 1024, Port B Width: 1

--Port A Logical Depth: 1024, Port A Logical Width: 32, Port B Logical Depth: 1024, Port B Logical Width: 32

--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered

AD1_q_b[5] = AMPP_FUNCTION(GND, GND, QC2__clk0, QC2__clk0, S1_i_readdatavalid_d1, S1_W_stall, U1L23, S1_ic_fill_dp_offset[0], S1_ic_fill_dp_offset[1], S1_ic_fill_dp_offset[2], S1_ic_fill_line[0], S1_ic_fill_line[1], S1_ic_fill_line[2], S1_ic_fill_line[3], S1_ic_fill_line[4], S1_ic_fill_line[5], S1_ic_fill_line[6], S1L789, S1L792, S1L795, S1L821, S1L824, S1L827, S1L830, S1L833, S1L836, S1L839);

--AD1_q_b[27] is std_1c20:inst|cpu:the_cpu|cpu_ic_data_module:cpu_ic_data|altsyncram:the_altsyncram|altsyncram_qmb1:auto_generated|q_b[27]

--RAM Block Operation Mode: Simple Dual-Port

--Port A Depth: 1024, Port A Width: 1, Port B Depth: 1024, Port B Width: 1

--Port A Logical Depth: 1024, Port A Logical Width: 32, Port B Logical Depth: 1024, Port B Logical Width: 32

--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered

AD1_q_b[27] = AMPP_FUNCTION(GND, GND, QC2__clk0, QC2__clk0, S1_i_readdatavalid_d1, S1_W_stall, S1_i_readdata_d1[27], S1_ic_fill_dp_offset[0], S1_ic_fill_dp_offset[1], S1_ic_fill_dp_offset[2], S1_ic_fill_line[0], S1_ic_fill_line[1], S1_ic_fill_line[2], S1_ic_fill_line[3], S1_ic_fill_line[4], S1_ic_fill_line[5], S1_ic_fill_line[6], S1L789, S1L792, S1L795, S1L821, S1L824, S1L827, S1L830, S1L833, S1L836, S1L839);

--AD1_q_b[28] is std_1c20:inst|cpu:the_cpu|cpu_ic_data_module:cpu_ic_data|altsyncram:the_altsyncram|altsyncram_qmb1:auto_generated|q_b[28]

--RAM Block Operation Mode: Simple Dual-Port

--Port A Depth: 1024, Port A Width: 1, Port B Depth: 1024, Port B Width: 1

--Port A Logical Depth: 1024, Port A Logical Width: 32, Port B Logical Depth: 1024, Port B Logical Width: 32

--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered

AD1_q_b[28] = AMPP_FUNCTION(GND, GND, QC2__clk0, QC2__clk0, S1_i_readdatavalid_d1, S1_W_stall, S1_i_readdata_d1[28], S1_ic_fill_dp_offset[0], S1_ic_fill_dp_offset[1], S1_ic_fill_dp_offset[2], S1_ic_fill_line[0], S1_ic_fill_line[1], S1_ic_fill_line[2], S1_ic_fill_line[3], S1_ic_fill_line[4], S1_ic_fill_line[5], S1_ic_fill_line[6], S1L789, S1L792, S1L795, S1L821, S1L824, S1L827, S1L830, S1L833, S1L836, S1L839);

--AD1_q_b[29] is std_1c20:inst|cpu:the_cpu|cpu_ic_data_module:cpu_ic_data|altsyncram:the_altsyncram|altsyncram_qmb1:auto_generated|q_b[29]

--RAM Block Operation Mode: Simple Dual-Port

--Port A Depth: 1024, Port A Width: 1, Port B Depth: 1024, Port B Width: 1

--Port A Logical Depth: 1024, Port A Logical Width: 32, Port B Logical Depth: 1024, Port B Logical Width: 32

--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered

AD1_q_b[29] = AMPP_FUNCTION(GND, GND, QC2__clk0, QC2__clk0, S1_i_readdatavalid_d1, S1_W_stall, S1_i_readdata_d1[29], S1_ic_fill_dp_offset[0], S1_ic_fill_dp_offset[1], S1_ic_fill_dp_offset[2], S1_ic_fill_line[0], S1_ic_fill_line[1], S1_ic_fill_line[2], S1_ic_fill_line[3], S1_ic_fill_line[4], S1_ic_fill_line[5], S1_ic_fill_line[6], S1L789, S1L792, S1L795, S1L821, S1L824, S1L827, S1L830, S1L833, S1L836, S1L839);

--AD1_q_b[30] is std_1c20:inst|cpu:the_cpu|cpu_ic_data_module:cpu_ic_data|altsyncram:the_altsyncram|altsyncram_qmb1:auto_generated|q_b[30]

--RAM Block Operation Mode: Simple Dual-Port

--Port A Depth: 1024, Port A Width: 1, Port B Depth: 1024, Port B Width: 1

--Port A Logical Depth: 1024, Port A Logical Width: 32, Port B Logical Depth: 1024, Port B Logical Width: 32

--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered

AD1_q_b[30] = AMPP_FUNCTION(GND, GND, QC2__clk0, QC2__clk0, S1_i_readdatavalid_d1, S1_W_stall, S1_i_readdata_d1[30], S1_ic_fill_dp_offset[0], S1_ic_fill_dp_offset[1], S1_ic_fill_dp_offset[2], S1_ic_fill_line[0], S1_ic_fill_line[1], S1_ic_fill_line[2], S1_ic_fill_line[3], S1_ic_fill_line[4], S1_ic_fill_line[5], S1_ic_fill_line[6], S1L789, S1L792, S1L795, S1L821, S1L824, S1L827, S1L830, S1L833, S1L836, S1L839);

--AD1_q_b[31] is std_1c20:inst|cpu:the_cpu|cpu_ic_data_module:cpu_ic_data|altsyncram:the_altsyncram|altsyncram_qmb1:auto_generated|q_b[31]

--RAM Block Operation Mode: Simple Dual-Port

--Port A Depth: 1024, Port A Width: 1, Port B Depth: 1024, Port B Width: 1

--Port A Logical Depth: 1024, Port A Logical Width: 32, Port B Logical Depth: 1024, Port B Logical Width: 32

--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered

AD1_q_b[31] = AMPP_FUNCTION(GND, GND, QC2__clk0, QC2__clk0, S1_i_readdatavalid_d1, S1_W_stall, S1_i_readdata_d1[31], S1_ic_fill_dp_offset[0], S1_ic_fill_dp_offset[1], S1_ic_fill_dp_offset[2], S1_ic_fill_line[0], S1_ic_fill_line[1], S1_ic_fill_line[2], S1_ic_fill_line[3], S1_ic_fill_line[4], S1_ic_fill_line[5], S1_ic_fill_line[6], S1L789, S1L792, S1L795, S1L821, S1L824, S1L827, S1L830, S1L833, S1L836, S1L839);

--S1L229 is std_1c20:inst|cpu:the_cpu|D_ctrl_implicit_dst_eretaddr~147

--operation mode is normal

S1L229 = AMPP_FUNCTION(S1_D_iw[11], S1_D_iw[12], S1L774, S1_D_iw[15]);

--S1L230 is std_1c20:inst|cpu:the_cpu|D_ctrl_implicit_dst_eretaddr~148

--operation mode is normal

S1L230 = AMPP_FUNCTION(S1_D_iw[13], S1L760, S1L229);

--S1L231 is std_1c20:inst|cpu:the_cpu|D_ctrl_implicit_dst_eretaddr~149

--operation mode is normal

S1L231 = AMPP_FUNCTION(S1L764, S1_D_iw[4], S1_D_iw[5], S1L230);

--S1L242 is std_1c20:inst|cpu:the_cpu|D_dst_regnum[3]~620

--operation mode is normal

S1L242 = AMPP_FUNCTION(S1_D_iw[25], S1_D_iw[20], S1L212, S1L762);

--S1L243 is std_1c20:inst|cpu:the_cpu|D_dst_regnum[3]~621

--operation mode is normal

S1L243 = AMPP_FUNCTION(S1L202, S1L231, S1L242);

--S1L240 is std_1c20:inst|cpu:the_cpu|D_dst_regnum[1]~622

--operation mode is normal

S1L240 = AMPP_FUNCTION(S1_D_iw[23], S1_D_iw[18], S1L212, S1L762);

--S1L244 is std_1c20:inst|cpu:the_cpu|D_dst_regnum[4]~623

--operation mode is normal

S1L244 = AMPP_FUNCTION(S1_D_iw[26], S1_D_iw[21], S1L212, S1L762);

--S1L780 is std_1c20:inst|cpu:the_cpu|Equal171~108

--operation mode is normal

S1L780 = AMPP_FUNCTION(S1L202, S1L231, S1L240, S1L244);

--S1L241 is std_1c20:inst|cpu:the_cpu|D_dst_regnum[2]~624

--operation mode is normal

S1L241 = AMPP_FUNCTION(S1_D_iw[24], S1_D_iw[19], S1L212, S1L762);

--S1L239 is std_1c20:inst|cpu:the_cpu|D_dst_regnum[0]~625

--operation mode is normal

S1L239 = AMPP_FUNCTION(S1_D_iw[22], S1_D_iw[17], S1L212, S1L762);

--S1L781 is std_1c20:inst|cpu:the_cpu|Equal171~109

--operation mode is normal

S1L781 = AMPP_FUNCTION(S1L202, S1L231, S1L241, S1L239);

--S1_E_ctrl_shift_rot_right is std_1c20:inst|cpu:the_cpu|E_ctrl_shift_rot_right

--operation mode is normal

S1_E_ctrl_shift_rot_right = AMPP_FUNCTION(QC2__clk0, S1_D_iw[14], S1L234, F1_data_out, S1_W_stall);

--G1_readdata[2] is std_1c20:inst|button_pio:the_button_pio|readdata[2]

--operation mode is normal

G1_readdata[2]_lut_out = S1_M_alu_result[3] & G1L29 # !S1_M_alu_result[3] & (in_port_to_the_button_pio[2] & !S1_M_alu_result[2]);

G1_readdata[2] = DFFEAS(G1_readdata[2]_lut_out, QC2__clk0, F1_data_out, , , , , , );

--XE1_readdata[2] is std_1c20:inst|uart1:the_uart1|uart1_regs:the_uart1_regs|readdata[2]

--operation mode is normal

XE1_readdata[2]_lut_out = !S1_M_alu_result[4] & (S1_M_alu_result[2] & XE1L52 # !S1_M_alu_result[2] & (XE1L53));

XE1_readdata[2] = DFFEAS(XE1_readdata[2]_lut_out, QC2__clk0, F1_data_out, , , , , , );

--WB1_cpu_data_master_granted_uart1_s1 is std_1c20:inst|uart1_s1_arbitrator:the_uart1_s1|cpu_data_master_granted_uart1_s1

--operation mode is normal

WB1_cpu_data_master_granted_uart1_s1 = S1_M_alu_result[6] & SB1L2 & (!S1_M_alu_result[5]);

--H1L2 is std_1c20:inst|button_pio_s1_arbitrator:the_button_pio_s1|cpu_data_master_requests_button_pio_s1~74

--operation mode is normal

H1L2 = S1_M_alu_result[6] & (!S1_M_alu_result[4]);

--T1L41 is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[2]~5162

--operation mode is normal

T1L41 = G1_readdata[2] & (XE1_readdata[2] # !WB1_cpu_data_master_granted_uart1_s1) # !G1_readdata[2] & !H1_cpu_data_master_requests_button_pio_s1 & (XE1_readdata[2] # !WB1_cpu_data_master_granted_uart1_s1);

--RB1_readdata[2] is std_1c20:inst|sys_clk_timer:the_sys_clk_timer|readdata[2]

--operation mode is normal

RB1_readdata[2]_lut_out = RB1L164 # RB1L165 # XE1L20 & !RB1_period_l_register[2];

RB1_readdata[2] = DFFEAS(RB1_readdata[2]_lut_out, QC2__clk0, F1_data_out, , , , , , );

--SB1_cpu_data_master_requests_sys_clk_timer_s1 is std_1c20:inst|sys_clk_timer_s1_arbitrator:the_sys_clk_timer_s1|cpu_data_master_requests_sys_clk_timer_s1

--operation mode is normal

SB1_cpu_data_master_requests_sys_clk_timer_s1 = SB1L2 & (!S1_M_alu_result[5] & !S1_M_alu_result[6]);

--UB1L10 is std_1c20:inst|sysid_control_slave_arbitrator:the_sysid_control_slave|cpu_data_master_granted_sysid_control_slave~158

--operation mode is normal

UB1L10 = S1_M_alu_result[3] & S1_M_alu_result[4] & S1_internal_d_read;

--JB1_cpu_data_master_requests_reconfig_request_pio_s1 is std_1c20:inst|reconfig_request_pio_s1_arbitrator:the_reconfig_request_pio_s1|cpu_data_master_requests_reconfig_request_pio_s1

--operation mode is normal

JB1_cpu_data_master_requests_reconfig_request_pio_s1 = S1_M_alu_result[5] & JB1L3;

--T1L42 is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[2]~5163

--operation mode is normal

T1L42 = !UB1_cpu_data_master_granted_sysid_control_slave & !JB1_cpu_data_master_requests_reconfig_request_pio_s1 & (RB1_readdata[2] # !SB1_cpu_data_master_requests_sys_clk_timer_s1);

--T1_registered_cpu_data_master_readdata[2] is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|registered_cpu_data_master_readdata[2]

--operation mode is normal

T1_registered_cpu_data_master_readdata[2]_lut_out = T1L245 & T1L275 & (KB1_za_data[2] # !NB1L17);

T1_registered_cpu_data_master_readdata[2] = DFFEAS(T1_registered_cpu_data_master_readdata[2]_lut_out, QC2__clk0, F1_data_out, , , , , , );

--T1L43 is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[2]~5164

--operation mode is normal

T1L43 = T1_registered_cpu_data_master_readdata[2] # !N1_cpu_data_master_requests_clock_1_in & (!CB1L2 # !UB1L9);

--Z1_readdata[2] is std_1c20:inst|high_res_timer:the_high_res_timer|readdata[2]

--operation mode is normal

Z1_readdata[2]_lut_out = Z1L163 # Z1L164 # XE1L20 & !Z1_period_l_register[2];

Z1_readdata[2] = DFFEAS(Z1_readdata[2]_lut_out, QC2__clk0, F1_data_out, , , , , , );

--AB1_cpu_data_master_requests_high_res_timer_s1 is std_1c20:inst|high_res_timer_s1_arbitrator:the_high_res_timer_s1|cpu_data_master_requests_high_res_timer_s1

--operation mode is normal

AB1_cpu_data_master_requests_high_res_timer_s1 = S1_M_alu_result[5] & SB1L2 & (!S1_M_alu_result[6]);

--T1L44 is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[2]~5165

--operation mode is normal

T1L44 = T1L43 & (Z1_readdata[2] # !AB1_cpu_data_master_requests_high_res_timer_s1);

--Y1_internal_incoming_ext_ram_bus_data[2] is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|internal_incoming_ext_ram_bus_data[2]

--operation mode is normal

Y1_internal_incoming_ext_ram_bus_data[2]_lut_out = A1L114;

Y1_internal_incoming_ext_ram_bus_data[2] = DFFEAS(Y1_internal_incoming_ext_ram_bus_data[2]_lut_out, QC2__clk0, F1_data_out, , , , , , );

--T1_dbs_8_reg_segment_0[2] is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|dbs_8_reg_segment_0[2]

--operation mode is normal

T1_dbs_8_reg_segment_0[2]_lut_out = Y1_internal_incoming_ext_ram_bus_data[2];

T1_dbs_8_reg_segment_0[2] = DFFEAS(T1_dbs_8_reg_segment_0[2]_lut_out, QC2__clk0, F1_data_out, , T1L294, , , , );

--EB1L12 is std_1c20:inst|lcd_display_control_slave_arbitrator:the_lcd_display_control_slave|cpu_data_master_granted_lcd_display_control_slave~123

--operation mode is normal

EB1L12 = JB1L3 & (!S1_M_alu_result[5]);

--T1L45 is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[2]~5166

--operation mode is normal

T1L45 = T1_dbs_8_reg_segment_0[2] & (!A1L139 & EB1L12) # !T1_dbs_8_reg_segment_0[2] & (Y1_cpu_data_master_requests_ext_flash_s1 # !A1L139 & EB1L12);

--T1L46 is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[2]~5167

--operation mode is normal

T1L46 = T1L45 # !T1_registered_cpu_data_master_readdata[2] & (NB1L17 # K1_cpu_data_master_requests_clock_0_in);

--T1L47 is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[2]~5168

--operation mode is normal

T1L47 = !T1L46 & (Y1_internal_incoming_ext_ram_bus_data[2] # !Y1L78 & !Y1_cpu_data_master_requests_ext_ram_s1);

--T1L48 is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[2]~5169

--operation mode is normal

T1L48 = T1L41 & T1L42 & T1L44 & T1L47;

--DE1_data_to_cpu[2] is std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|data_to_cpu[2]

--operation mode is normal

DE1_data_to_cpu[2]_lut_out = !DE1L134 & (DE1L114 & DE1_endofpacketvalue_reg[2] # !DE1L114 & (DE1L133));

DE1_data_to_cpu[2] = DFFEAS(DE1_data_to_cpu[2]_lut_out, QC2__clk0, F1_data_out, , , , , , );

--FE1_q_a[2] is std_1c20:inst|epcs_controller:the_epcs_controller|altsyncram:the_boot_copier_rom|altsyncram_3h31:auto_generated|q_a[2]

--RAM Block Operation Mode: ROM

--Port A Depth: 128, Port A Width: 1

--Port A Logical Depth: 128, Port A Logical Width: 32

--Port A Input: Registered, Port A Output: Un-registered

FE1_q_a[2]_PORT_A_address = BUS(X1L14, X1L15, X1L16, X1L17, X1L18, X1L19, X1L20);

FE1_q_a[2]_PORT_A_address_reg = DFFE(FE1_q_a[2]_PORT_A_address, FE1_q_a[2]_clock_0, , , );

FE1_q_a[2]_clock_0 = QC2__clk0;

FE1_q_a[2]_PORT_A_data_out = MEMORY(, , FE1_q_a[2]_PORT_A_address_reg, , , , , , FE1_q_a[2]_clock_0, , , , , );

FE1_q_a[2] = FE1_q_a[2]_PORT_A_data_out[0];

--W1L1 is std_1c20:inst|epcs_controller:the_epcs_controller|epcs_select~62

--operation mode is normal

W1L1 = X1L2 & S1_M_alu_result[9] # !X1L2 & (S1_ic_fill_line[4] & X1L6);

--U1L112 is std_1c20:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_readdata~2397

--operation mode is normal

U1L112 = W1L1 & DE1_data_to_cpu[2] # !W1L1 & (FE1_q_a[2]);

--V1L17 is std_1c20:inst|cpu_jtag_debug_module_arbitrator:the_cpu_jtag_debug_module|cpu_jtag_debug_module_address[8]~90

--operation mode is normal

V1L17 = V1L4 & S1_M_alu_result[10] # !V1L4 & (S1_ic_fill_line[5]);

--V1L10 is std_1c20:inst|cpu_jtag_debug_module_arbitrator:the_cpu_jtag_debug_module|cpu_jtag_debug_module_address[1]~91

--operation mode is normal

V1L10 = V1L4 & S1_M_alu_result[3] # !V1L4 & (S1_ic_fill_ap_offset[1]);

--V1L16 is std_1c20:inst|cpu_jtag_debug_module_arbitrator:the_cpu_jtag_debug_module|cpu_jtag_debug_module_address[7]~92

--operation mode is normal

V1L16 = V1L4 & S1_M_alu_result[9] # !V1L4 & (S1_ic_fill_line[4]);

--V1L14 is std_1c20:inst|cpu_jtag_debug_module_arbitrator:the_cpu_jtag_debug_module|cpu_jtag_debug_module_address[5]~93

--operation mode is normal

V1L14 = V1L4 & S1_M_alu_result[7] # !V1L4 & (S1_ic_fill_line[2]);

--FD1L1 is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_avalon_reg:the_cpu_nios2_avalon_reg|Equal0~71

--operation mode is normal

FD1L1 = AMPP_FUNCTION(V1L17, V1L10, V1L16, V1L14);

--V1L12 is std_1c20:inst|cpu_jtag_debug_module_arbitrator:the_cpu_jtag_debug_module|cpu_jtag_debug_module_address[3]~94

--operation mode is normal

V1L12 = V1L4 & S1_M_alu_result[5] # !V1L4 & (S1_ic_fill_line[0]);

--V1L13 is std_1c20:inst|cpu_jtag_debug_module_arbitrator:the_cpu_jtag_debug_module|cpu_jtag_debug_module_address[4]~95

--operation mode is normal

V1L13 = V1L4 & S1_M_alu_result[6] # !V1L4 & (S1_ic_fill_line[1]);

--V1L15 is std_1c20:inst|cpu_jtag_debug_module_arbitrator:the_cpu_jtag_debug_module|cpu_jtag_debug_module_address[6]~96

--operation mode is normal

V1L15 = V1L4 & S1_M_alu_result[8] # !V1L4 & (S1_ic_fill_line[3]);

--V1L11 is std_1c20:inst|cpu_jtag_debug_module_arbitrator:the_cpu_jtag_debug_module|cpu_jtag_debug_module_address[2]~97

--operation mode is normal

V1L11 = V1L4 & S1_M_alu_result[4] # !V1L4 & (S1_ic_fill_ap_offset[2]);

--FD1L2 is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_avalon_reg:the_cpu_nios2_avalon_reg|Equal0~72

--operation mode is normal

FD1L2 = AMPP_FUNCTION(V1L12, V1L13, V1L15, V1L11);

--V1L9 is std_1c20:inst|cpu_jtag_debug_module_arbitrator:the_cpu_jtag_debug_module|cpu_jtag_debug_module_address[0]~98

--operation mode is normal

V1L9 = V1L4 & S1_M_alu_result[2] # !V1L4 & (S1_ic_fill_ap_offset[0]);

--FD1L3 is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_avalon_reg:the_cpu_nios2_avalon_reg|Equal0~73

--operation mode is normal

FD1L3 = AMPP_FUNCTION(FD1L1, FD1L2, V1L9);

--JD1_internal_monitor_go is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_debug:the_cpu_nios2_oci_debug|internal_monitor_go

--operation mode is normal

JD1_internal_monitor_go = AMPP_FUNCTION(QC2__clk0, SD1_internal_jdo1[23], FD1L14, JD1_internal_monitor_go, JD1L5, VCC);

--CE1_q_a[0] is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|cpu_ociram_lpm_dram_bdp_component_module:cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_bp62:auto_generated|q_a[0]

--RAM Block Operation Mode: True Dual-Port

--Port A Depth: 256, Port A Width: 8, Port B Depth: 256, Port B Width: 8

--Port A Logical Depth: 256, Port A Logical Width: 32, Port B Logical Depth: 256, Port B Logical Width: 32

--Port A Input: Registered, Port A Output: Un-registered, Port B Input: Registered, Port B Output: Un-registered

CE1_q_a[0] = AMPP_FUNCTION(RD1L62, RD1_MonWr, QC2__clk0, QC2__clk0, S1_M_st_data[0], S1_M_st_data[1], S1_M_st_data[2], S1_M_st_data[3], S1_M_st_data[4], S1_M_st_data[5], S1_M_st_data[6], S1_M_st_data[7], V1L9, V1L10, V1L11, V1L12, V1L13, V1L14, V1L15, V1L16, V1L27, RD1_internal_MonDReg[0], RD1_internal_MonDReg[1], RD1_internal_MonDReg[2], RD1_internal_MonDReg[3], RD1_internal_MonDReg[4], RD1_internal_MonDReg[5], RD1_internal_MonDReg[6], RD1_internal_MonDReg[7], RD1_MonAReg[2], RD1_MonAReg[3], RD1_MonAReg[4], RD1_MonAReg[5], RD1_MonAReg[6], RD1_MonAReg[7], RD1_MonAReg[8], RD1_MonAReg[9]);

--CE1_q_a[1] is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|cpu_ociram_lpm_dram_bdp_component_module:cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_bp62:auto_generated|q_a[1]

CE1_q_a[1] = AMPP_FUNCTION(RD1L62, RD1_MonWr, QC2__clk0, QC2__clk0, S1_M_st_data[0], S1_M_st_data[1], S1_M_st_data[2], S1_M_st_data[3], S1_M_st_data[4], S1_M_st_data[5], S1_M_st_data[6], S1_M_st_data[7], V1L9, V1L10, V1L11, V1L12, V1L13, V1L14, V1L15, V1L16, V1L27, RD1_internal_MonDReg[0], RD1_internal_MonDReg[1], RD1_internal_MonDReg[2], RD1_internal_MonDReg[3], RD1_internal_MonDReg[4], RD1_internal_MonDReg[5], RD1_internal_MonDReg[6], RD1_internal_MonDReg[7], RD1_MonAReg[2], RD1_MonAReg[3], RD1_MonAReg[4], RD1_MonAReg[5], RD1_MonAReg[6], RD1_MonAReg[7], RD1_MonAReg[8], RD1_MonAReg[9]);

--CE1_q_a[2] is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|cpu_ociram_lpm_dram_bdp_component_module:cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_bp62:auto_generated|q_a[2]

CE1_q_a[2] = AMPP_FUNCTION(RD1L62, RD1_MonWr, QC2__clk0, QC2__clk0, S1_M_st_data[0], S1_M_st_data[1], S1_M_st_data[2], S1_M_st_data[3], S1_M_st_data[4], S1_M_st_data[5], S1_M_st_data[6], S1_M_st_data[7], V1L9, V1L10, V1L11, V1L12, V1L13, V1L14, V1L15, V1L16, V1L27, RD1_internal_MonDReg[0], RD1_internal_MonDReg[1], RD1_internal_MonDReg[2], RD1_internal_MonDReg[3], RD1_internal_MonDReg[4], RD1_internal_MonDReg[5], RD1_internal_MonDReg[6], RD1_internal_MonDReg[7], RD1_MonAReg[2], RD1_MonAReg[3], RD1_MonAReg[4], RD1_MonAReg[5], RD1_MonAReg[6], RD1_MonAReg[7], RD1_MonAReg[8], RD1_MonAReg[9]);

--CE1_q_a[3] is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|cpu_ociram_lpm_dram_bdp_component_module:cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_bp62:auto_generated|q_a[3]

CE1_q_a[3] = AMPP_FUNCTION(RD1L62, RD1_MonWr, QC2__clk0, QC2__clk0, S1_M_st_data[0], S1_M_st_data[1], S1_M_st_data[2], S1_M_st_data[3], S1_M_st_data[4], S1_M_st_data[5], S1_M_st_data[6], S1_M_st_data[7], V1L9, V1L10, V1L11, V1L12, V1L13, V1L14, V1L15, V1L16, V1L27, RD1_internal_MonDReg[0], RD1_internal_MonDReg[1], RD1_internal_MonDReg[2], RD1_internal_MonDReg[3], RD1_internal_MonDReg[4], RD1_internal_MonDReg[5], RD1_internal_MonDReg[6], RD1_internal_MonDReg[7], RD1_MonAReg[2], RD1_MonAReg[3], RD1_MonAReg[4], RD1_MonAReg[5], RD1_MonAReg[6], RD1_MonAReg[7], RD1_MonAReg[8], RD1_MonAReg[9]);

--CE1_q_a[4] is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|cpu_ociram_lpm_dram_bdp_component_module:cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_bp62:auto_generated|q_a[4]

CE1_q_a[4] = AMPP_FUNCTION(RD1L62, RD1_MonWr, QC2__clk0, QC2__clk0, S1_M_st_data[0], S1_M_st_data[1], S1_M_st_data[2], S1_M_st_data[3], S1_M_st_data[4], S1_M_st_data[5], S1_M_st_data[6], S1_M_st_data[7], V1L9, V1L10, V1L11, V1L12, V1L13, V1L14, V1L15, V1L16, V1L27, RD1_internal_MonDReg[0], RD1_internal_MonDReg[1], RD1_internal_MonDReg[2], RD1_internal_MonDReg[3], RD1_internal_MonDReg[4], RD1_internal_MonDReg[5], RD1_internal_MonDReg[6], RD1_internal_MonDReg[7], RD1_MonAReg[2], RD1_MonAReg[3], RD1_MonAReg[4], RD1_MonAReg[5], RD1_MonAReg[6], RD1_MonAReg[7], RD1_MonAReg[8], RD1_MonAReg[9]);

--CE1_q_a[5] is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|cpu_ociram_lpm_dram_bdp_component_module:cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_bp62:auto_generated|q_a[5]

CE1_q_a[5] = AMPP_FUNCTION(RD1L62, RD1_MonWr, QC2__clk0, QC2__clk0, S1_M_st_data[0], S1_M_st_data[1], S1_M_st_data[2], S1_M_st_data[3], S1_M_st_data[4], S1_M_st_data[5], S1_M_st_data[6], S1_M_st_data[7], V1L9, V1L10, V1L11, V1L12, V1L13, V1L14, V1L15, V1L16, V1L27, RD1_internal_MonDReg[0], RD1_internal_MonDReg[1], RD1_internal_MonDReg[2], RD1_internal_MonDReg[3], RD1_internal_MonDReg[4], RD1_internal_MonDReg[5], RD1_internal_MonDReg[6], RD1_internal_MonDReg[7], RD1_MonAReg[2], RD1_MonAReg[3], RD1_MonAReg[4], RD1_MonAReg[5], RD1_MonAReg[6], RD1_MonAReg[7], RD1_MonAReg[8], RD1_MonAReg[9]);

--CE1_q_a[6] is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|cpu_ociram_lpm_dram_bdp_component_module:cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_bp62:auto_generated|q_a[6]

CE1_q_a[6] = AMPP_FUNCTION(RD1L62, RD1_MonWr, QC2__clk0, QC2__clk0, S1_M_st_data[0], S1_M_st_data[1], S1_M_st_data[2], S1_M_st_data[3], S1_M_st_data[4], S1_M_st_data[5], S1_M_st_data[6], S1_M_st_data[7], V1L9, V1L10, V1L11, V1L12, V1L13, V1L14, V1L15, V1L16, V1L27, RD1_internal_MonDReg[0], RD1_internal_MonDReg[1], RD1_internal_MonDReg[2], RD1_internal_MonDReg[3], RD1_internal_MonDReg[4], RD1_internal_MonDReg[5], RD1_internal_MonDReg[6], RD1_internal_MonDReg[7], RD1_MonAReg[2], RD1_MonAReg[3], RD1_MonAReg[4], RD1_MonAReg[5], RD1_MonAReg[6], RD1_MonAReg[7], RD1_MonAReg[8], RD1_MonAReg[9]);

--CE1_q_a[7] is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|cpu_ociram_lpm_dram_bdp_component_module:cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_bp62:auto_generated|q_a[7]

CE1_q_a[7] = AMPP_FUNCTION(RD1L62, RD1_MonWr, QC2__clk0, QC2__clk0, S1_M_st_data[0], S1_M_st_data[1], S1_M_st_data[2], S1_M_st_data[3], S1_M_st_data[4], S1_M_st_data[5], S1_M_st_data[6], S1_M_st_data[7], V1L9, V1L10, V1L11, V1L12, V1L13, V1L14, V1L15, V1L16, V1L27, RD1_internal_MonDReg[0], RD1_internal_MonDReg[1], RD1_internal_MonDReg[2], RD1_internal_MonDReg[3], RD1_internal_MonDReg[4], RD1_internal_MonDReg[5], RD1_internal_MonDReg[6], RD1_internal_MonDReg[7], RD1_MonAReg[2], RD1_MonAReg[3], RD1_MonAReg[4], RD1_MonAReg[5], RD1_MonAReg[6], RD1_MonAReg[7], RD1_MonAReg[8], RD1_MonAReg[9]);

--CE1_q_b[0] is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|cpu_ociram_lpm_dram_bdp_component_module:cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_bp62:auto_generated|q_b[0]

CE1_q_b[0] = AMPP_FUNCTION(RD1L62, RD1_MonWr, QC2__clk0, QC2__clk0, S1_M_st_data[0], S1_M_st_data[1], S1_M_st_data[2], S1_M_st_data[3], S1_M_st_data[4], S1_M_st_data[5], S1_M_st_data[6], S1_M_st_data[7], V1L9, V1L10, V1L11, V1L12, V1L13, V1L14, V1L15, V1L16, V1L27, RD1_internal_MonDReg[0], RD1_internal_MonDReg[1], RD1_internal_MonDReg[2], RD1_internal_MonDReg[3], RD1_internal_MonDReg[4], RD1_internal_MonDReg[5], RD1_internal_MonDReg[6], RD1_internal_MonDReg[7], RD1_MonAReg[2], RD1_MonAReg[3], RD1_MonAReg[4], RD1_MonAReg[5], RD1_MonAReg[6], RD1_MonAReg[7], RD1_MonAReg[8], RD1_MonAReg[9]);

--CE1_q_b[1] is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|cpu_ociram_lpm_dram_bdp_component_module:cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_bp62:auto_generated|q_b[1]

CE1_q_b[1] = AMPP_FUNCTION(RD1L62, RD1_MonWr, QC2__clk0, QC2__clk0, S1_M_st_data[0], S1_M_st_data[1], S1_M_st_data[2], S1_M_st_data[3], S1_M_st_data[4], S1_M_st_data[5], S1_M_st_data[6], S1_M_st_data[7], V1L9, V1L10, V1L11, V1L12, V1L13, V1L14, V1L15, V1L16, V1L27, RD1_internal_MonDReg[0], RD1_internal_MonDReg[1], RD1_internal_MonDReg[2], RD1_internal_MonDReg[3], RD1_internal_MonDReg[4], RD1_internal_MonDReg[5], RD1_internal_MonDReg[6], RD1_internal_MonDReg[7], RD1_MonAReg[2], RD1_MonAReg[3], RD1_MonAReg[4], RD1_MonAReg[5], RD1_MonAReg[6], RD1_MonAReg[7], RD1_MonAReg[8], RD1_MonAReg[9]);

--CE1_q_b[2] is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|cpu_ociram_lpm_dram_bdp_component_module:cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_bp62:auto_generated|q_b[2]

CE1_q_b[2] = AMPP_FUNCTION(RD1L62, RD1_MonWr, QC2__clk0, QC2__clk0, S1_M_st_data[0], S1_M_st_data[1], S1_M_st_data[2], S1_M_st_data[3], S1_M_st_data[4], S1_M_st_data[5], S1_M_st_data[6], S1_M_st_data[7], V1L9, V1L10, V1L11, V1L12, V1L13, V1L14, V1L15, V1L16, V1L27, RD1_internal_MonDReg[0], RD1_internal_MonDReg[1], RD1_internal_MonDReg[2], RD1_internal_MonDReg[3], RD1_internal_MonDReg[4], RD1_internal_MonDReg[5], RD1_internal_MonDReg[6], RD1_internal_MonDReg[7], RD1_MonAReg[2], RD1_MonAReg[3], RD1_MonAReg[4], RD1_MonAReg[5], RD1_MonAReg[6], RD1_MonAReg[7], RD1_MonAReg[8], RD1_MonAReg[9]);

--CE1_q_b[3] is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|cpu_ociram_lpm_dram_bdp_component_module:cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_bp62:auto_generated|q_b[3]

CE1_q_b[3] = AMPP_FUNCTION(RD1L62, RD1_MonWr, QC2__clk0, QC2__clk0, S1_M_st_data[0], S1_M_st_data[1], S1_M_st_data[2], S1_M_st_data[3], S1_M_st_data[4], S1_M_st_data[5], S1_M_st_data[6], S1_M_st_data[7], V1L9, V1L10, V1L11, V1L12, V1L13, V1L14, V1L15, V1L16, V1L27, RD1_internal_MonDReg[0], RD1_internal_MonDReg[1], RD1_internal_MonDReg[2], RD1_internal_MonDReg[3], RD1_internal_MonDReg[4], RD1_internal_MonDReg[5], RD1_internal_MonDReg[6], RD1_internal_MonDReg[7], RD1_MonAReg[2], RD1_MonAReg[3], RD1_MonAReg[4], RD1_MonAReg[5], RD1_MonAReg[6], RD1_MonAReg[7], RD1_MonAReg[8], RD1_MonAReg[9]);

--CE1_q_b[4] is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|cpu_ociram_lpm_dram_bdp_component_module:cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_bp62:auto_generated|q_b[4]

CE1_q_b[4] = AMPP_FUNCTION(RD1L62, RD1_MonWr, QC2__clk0, QC2__clk0, S1_M_st_data[0], S1_M_st_data[1], S1_M_st_data[2], S1_M_st_data[3], S1_M_st_data[4], S1_M_st_data[5], S1_M_st_data[6], S1_M_st_data[7], V1L9, V1L10, V1L11, V1L12, V1L13, V1L14, V1L15, V1L16, V1L27, RD1_internal_MonDReg[0], RD1_internal_MonDReg[1], RD1_internal_MonDReg[2], RD1_internal_MonDReg[3], RD1_internal_MonDReg[4], RD1_internal_MonDReg[5], RD1_internal_MonDReg[6], RD1_internal_MonDReg[7], RD1_MonAReg[2], RD1_MonAReg[3], RD1_MonAReg[4], RD1_MonAReg[5], RD1_MonAReg[6], RD1_MonAReg[7], RD1_MonAReg[8], RD1_MonAReg[9]);

--CE1_q_b[5] is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|cpu_ociram_lpm_dram_bdp_component_module:cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_bp62:auto_generated|q_b[5]

CE1_q_b[5] = AMPP_FUNCTION(RD1L62, RD1_MonWr, QC2__clk0, QC2__clk0, S1_M_st_data[0], S1_M_st_data[1], S1_M_st_data[2], S1_M_st_data[3], S1_M_st_data[4], S1_M_st_data[5], S1_M_st_data[6], S1_M_st_data[7], V1L9, V1L10, V1L11, V1L12, V1L13, V1L14, V1L15, V1L16, V1L27, RD1_internal_MonDReg[0], RD1_internal_MonDReg[1], RD1_internal_MonDReg[2], RD1_internal_MonDReg[3], RD1_internal_MonDReg[4], RD1_internal_MonDReg[5], RD1_internal_MonDReg[6], RD1_internal_MonDReg[7], RD1_MonAReg[2], RD1_MonAReg[3], RD1_MonAReg[4], RD1_MonAReg[5], RD1_MonAReg[6], RD1_MonAReg[7], RD1_MonAReg[8], RD1_MonAReg[9]);

--CE1_q_b[6] is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|cpu_ociram_lpm_dram_bdp_component_module:cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_bp62:auto_generated|q_b[6]

CE1_q_b[6] = AMPP_FUNCTION(RD1L62, RD1_MonWr, QC2__clk0, QC2__clk0, S1_M_st_data[0], S1_M_st_data[1], S1_M_st_data[2], S1_M_st_data[3], S1_M_st_data[4], S1_M_st_data[5], S1_M_st_data[6], S1_M_st_data[7], V1L9, V1L10, V1L11, V1L12, V1L13, V1L14, V1L15, V1L16, V1L27, RD1_internal_MonDReg[0], RD1_internal_MonDReg[1], RD1_internal_MonDReg[2], RD1_internal_MonDReg[3], RD1_internal_MonDReg[4], RD1_internal_MonDReg[5], RD1_internal_MonDReg[6], RD1_internal_MonDReg[7], RD1_MonAReg[2], RD1_MonAReg[3], RD1_MonAReg[4], RD1_MonAReg[5], RD1_MonAReg[6], RD1_MonAReg[7], RD1_MonAReg[8], RD1_MonAReg[9]);

--CE1_q_b[7] is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|cpu_ociram_lpm_dram_bdp_component_module:cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_bp62:auto_generated|q_b[7]

CE1_q_b[7] = AMPP_FUNCTION(RD1L62, RD1_MonWr, QC2__clk0, QC2__clk0, S1_M_st_data[0], S1_M_st_data[1], S1_M_st_data[2], S1_M_st_data[3], S1_M_st_data[4], S1_M_st_data[5], S1_M_st_data[6], S1_M_st_data[7], V1L9, V1L10, V1L11, V1L12, V1L13, V1L14, V1L15, V1L16, V1L27, RD1_internal_MonDReg[0], RD1_internal_MonDReg[1], RD1_internal_MonDReg[2], RD1_internal_MonDReg[3], RD1_internal_MonDReg[4], RD1_internal_MonDReg[5], RD1_internal_MonDReg[6], RD1_internal_MonDReg[7], RD1_MonAReg[2], RD1_MonAReg[3], RD1_MonAReg[4], RD1_MonAReg[5], RD1_MonAReg[6], RD1_MonAReg[7], RD1_MonAReg[8], RD1_MonAReg[9]);

--WC1L3 is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|readdata[2]~1336

--operation mode is normal

WC1L3 = AMPP_FUNCTION(FD1L3, JD1_internal_monitor_go, CE1_q_a[2], V1L17);

--WC1L19 is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|readdata[18]~1337

--operation mode is normal

WC1L19 = AMPP_FUNCTION(V1L17, V1L9, FD1L1, FD1L2);

--T1L100 is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[9]~5171

--operation mode is normal

T1L100 = !JB1L3 & (!H1L2 # !SB1L2 # !S1_M_alu_result[5]);

--T1L143 is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[16]~5172

--operation mode is normal

T1L143 = S1_M_alu_result[6] # !SB1L2;

--T1L150 is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[18]~5173

--operation mode is normal

T1L150 = T1L100 & T1L143 & !WB1_cpu_data_master_granted_uart1_s1 & !UB1_cpu_data_master_granted_sysid_control_slave;

--Y1_internal_incoming_ext_ram_bus_data[18] is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|internal_incoming_ext_ram_bus_data[18]

--operation mode is normal

Y1_internal_incoming_ext_ram_bus_data[18]_lut_out = A1L98;

Y1_internal_incoming_ext_ram_bus_data[18] = DFFEAS(Y1_internal_incoming_ext_ram_bus_data[18]_lut_out, QC2__clk0, F1_data_out, , , , , , );

--T1_dbs_8_reg_segment_2[2] is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|dbs_8_reg_segment_2[2]

--operation mode is normal

T1_dbs_8_reg_segment_2[2]_lut_out = Y1_internal_incoming_ext_ram_bus_data[2];

T1_dbs_8_reg_segment_2[2] = DFFEAS(T1_dbs_8_reg_segment_2[2]_lut_out, QC2__clk0, F1_data_out, , T1L296, , , , );

--T1_registered_cpu_data_master_readdata[18] is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|registered_cpu_data_master_readdata[18]

--operation mode is normal

T1_registered_cpu_data_master_readdata[18]_lut_out = T1L259 & !K1L6 & (BB1L18 # !CB1_cpu_data_master_requests_jtag_uart_avalon_jtag_slave);

T1_registered_cpu_data_master_readdata[18] = DFFEAS(T1_registered_cpu_data_master_readdata[18]_lut_out, QC2__clk0, F1_data_out, , , , , , );

--CB1_cpu_data_master_requests_jtag_uart_avalon_jtag_slave is std_1c20:inst|jtag_uart_avalon_jtag_slave_arbitrator:the_jtag_uart_avalon_jtag_slave|cpu_data_master_requests_jtag_uart_avalon_jtag_slave

--operation mode is normal

CB1_cpu_data_master_requests_jtag_uart_avalon_jtag_slave = UB1L9 & CB1L2;

--T1L151 is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[18]~5174

--operation mode is normal

T1L151 = NB1L17 # K1_cpu_data_master_requests_clock_0_in # N1_cpu_data_master_requests_clock_1_in # CB1_cpu_data_master_requests_jtag_uart_avalon_jtag_slave;

--T1L152 is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[18]~5175

--operation mode is normal

T1L152 = T1_dbs_8_reg_segment_2[2] & (!T1_registered_cpu_data_master_readdata[18] & T1L151) # !T1_dbs_8_reg_segment_2[2] & (Y1_cpu_data_master_requests_ext_flash_s1 # !T1_registered_cpu_data_master_readdata[18] & T1L151);

--T1L153 is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[18]~5176

--operation mode is normal

T1L153 = !T1L152 & (Y1_internal_incoming_ext_ram_bus_data[18] # !Y1L78 & !Y1_cpu_data_master_requests_ext_ram_s1);

--FE1_q_a[18] is std_1c20:inst|epcs_controller:the_epcs_controller|altsyncram:the_boot_copier_rom|altsyncram_3h31:auto_generated|q_a[18]

--RAM Block Operation Mode: ROM

--Port A Depth: 128, Port A Width: 1

--Port A Logical Depth: 128, Port A Logical Width: 32

--Port A Input: Registered, Port A Output: Un-registered

FE1_q_a[18]_PORT_A_address = BUS(X1L14, X1L15, X1L16, X1L17, X1L18, X1L19, X1L20);

FE1_q_a[18]_PORT_A_address_reg = DFFE(FE1_q_a[18]_PORT_A_address, FE1_q_a[18]_clock_0, , , );

FE1_q_a[18]_clock_0 = QC2__clk0;

FE1_q_a[18]_PORT_A_data_out = MEMORY(, , FE1_q_a[18]_PORT_A_address_reg, , , , , , FE1_q_a[18]_clock_0, , , , , );

FE1_q_a[18] = FE1_q_a[18]_PORT_A_data_out[0];

--W1L4 is std_1c20:inst|epcs_controller:the_epcs_controller|readdata[18]~688

--operation mode is normal

W1L4 = FE1_q_a[18] & (!W1L1);

--T1L154 is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[18]~5177

--operation mode is normal

T1L154 = T1L150 & T1L153 & (W1L4 # !X1_cpu_data_master_requests_epcs_controller_epcs_control_port);

--CE1_q_a[16] is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|cpu_ociram_lpm_dram_bdp_component_module:cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_bp62:auto_generated|q_a[16]

--RAM Block Operation Mode: True Dual-Port

--Port A Depth: 256, Port A Width: 8, Port B Depth: 256, Port B Width: 8

--Port A Logical Depth: 256, Port A Logical Width: 32, Port B Logical Depth: 256, Port B Logical Width: 32

--Port A Input: Registered, Port A Output: Un-registered, Port B Input: Registered, Port B Output: Un-registered

CE1_q_a[16] = AMPP_FUNCTION(RD1L62, RD1_MonWr, QC2__clk0, QC2__clk0, S1_M_st_data[16], S1_M_st_data[17], S1_M_st_data[18], S1_M_st_data[19], S1_M_st_data[20], S1_M_st_data[21], S1_M_st_data[22], S1_M_st_data[23], V1L9, V1L10, V1L11, V1L12, V1L13, V1L14, V1L15, V1L16, V1L29, RD1_internal_MonDReg[16], RD1_internal_MonDReg[17], RD1_internal_MonDReg[18], RD1_internal_MonDReg[19], RD1_internal_MonDReg[20], RD1_internal_MonDReg[21], RD1_internal_MonDReg[22], RD1_internal_MonDReg[23], RD1_MonAReg[2], RD1_MonAReg[3], RD1_MonAReg[4], RD1_MonAReg[5], RD1_MonAReg[6], RD1_MonAReg[7], RD1_MonAReg[8], RD1_MonAReg[9]);

--CE1_q_a[17] is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|cpu_ociram_lpm_dram_bdp_component_module:cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_bp62:auto_generated|q_a[17]

CE1_q_a[17] = AMPP_FUNCTION(RD1L62, RD1_MonWr, QC2__clk0, QC2__clk0, S1_M_st_data[16], S1_M_st_data[17], S1_M_st_data[18], S1_M_st_data[19], S1_M_st_data[20], S1_M_st_data[21], S1_M_st_data[22], S1_M_st_data[23], V1L9, V1L10, V1L11, V1L12, V1L13, V1L14, V1L15, V1L16, V1L29, RD1_internal_MonDReg[16], RD1_internal_MonDReg[17], RD1_internal_MonDReg[18], RD1_internal_MonDReg[19], RD1_internal_MonDReg[20], RD1_internal_MonDReg[21], RD1_internal_MonDReg[22], RD1_internal_MonDReg[23], RD1_MonAReg[2], RD1_MonAReg[3], RD1_MonAReg[4], RD1_MonAReg[5], RD1_MonAReg[6], RD1_MonAReg[7], RD1_MonAReg[8], RD1_MonAReg[9]);

--CE1_q_a[18] is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|cpu_ociram_lpm_dram_bdp_component_module:cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_bp62:auto_generated|q_a[18]

CE1_q_a[18] = AMPP_FUNCTION(RD1L62, RD1_MonWr, QC2__clk0, QC2__clk0, S1_M_st_data[16], S1_M_st_data[17], S1_M_st_data[18], S1_M_st_data[19], S1_M_st_data[20], S1_M_st_data[21], S1_M_st_data[22], S1_M_st_data[23], V1L9, V1L10, V1L11, V1L12, V1L13, V1L14, V1L15, V1L16, V1L29, RD1_internal_MonDReg[16], RD1_internal_MonDReg[17], RD1_internal_MonDReg[18], RD1_internal_MonDReg[19], RD1_internal_MonDReg[20], RD1_internal_MonDReg[21], RD1_internal_MonDReg[22], RD1_internal_MonDReg[23], RD1_MonAReg[2], RD1_MonAReg[3], RD1_MonAReg[4], RD1_MonAReg[5], RD1_MonAReg[6], RD1_MonAReg[7], RD1_MonAReg[8], RD1_MonAReg[9]);

--CE1_q_a[19] is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|cpu_ociram_lpm_dram_bdp_component_module:cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_bp62:auto_generated|q_a[19]

CE1_q_a[19] = AMPP_FUNCTION(RD1L62, RD1_MonWr, QC2__clk0, QC2__clk0, S1_M_st_data[16], S1_M_st_data[17], S1_M_st_data[18], S1_M_st_data[19], S1_M_st_data[20], S1_M_st_data[21], S1_M_st_data[22], S1_M_st_data[23], V1L9, V1L10, V1L11, V1L12, V1L13, V1L14, V1L15, V1L16, V1L29, RD1_internal_MonDReg[16], RD1_internal_MonDReg[17], RD1_internal_MonDReg[18], RD1_internal_MonDReg[19], RD1_internal_MonDReg[20], RD1_internal_MonDReg[21], RD1_internal_MonDReg[22], RD1_internal_MonDReg[23], RD1_MonAReg[2], RD1_MonAReg[3], RD1_MonAReg[4], RD1_MonAReg[5], RD1_MonAReg[6], RD1_MonAReg[7], RD1_MonAReg[8], RD1_MonAReg[9]);

--CE1_q_a[20] is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|cpu_ociram_lpm_dram_bdp_component_module:cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_bp62:auto_generated|q_a[20]

CE1_q_a[20] = AMPP_FUNCTION(RD1L62, RD1_MonWr, QC2__clk0, QC2__clk0, S1_M_st_data[16], S1_M_st_data[17], S1_M_st_data[18], S1_M_st_data[19], S1_M_st_data[20], S1_M_st_data[21], S1_M_st_data[22], S1_M_st_data[23], V1L9, V1L10, V1L11, V1L12, V1L13, V1L14, V1L15, V1L16, V1L29, RD1_internal_MonDReg[16], RD1_internal_MonDReg[17], RD1_internal_MonDReg[18], RD1_internal_MonDReg[19], RD1_internal_MonDReg[20], RD1_internal_MonDReg[21], RD1_internal_MonDReg[22], RD1_internal_MonDReg[23], RD1_MonAReg[2], RD1_MonAReg[3], RD1_MonAReg[4], RD1_MonAReg[5], RD1_MonAReg[6], RD1_MonAReg[7], RD1_MonAReg[8], RD1_MonAReg[9]);

--CE1_q_a[21] is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|cpu_ociram_lpm_dram_bdp_component_module:cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_bp62:auto_generated|q_a[21]

CE1_q_a[21] = AMPP_FUNCTION(RD1L62, RD1_MonWr, QC2__clk0, QC2__clk0, S1_M_st_data[16], S1_M_st_data[17], S1_M_st_data[18], S1_M_st_data[19], S1_M_st_data[20], S1_M_st_data[21], S1_M_st_data[22], S1_M_st_data[23], V1L9, V1L10, V1L11, V1L12, V1L13, V1L14, V1L15, V1L16, V1L29, RD1_internal_MonDReg[16], RD1_internal_MonDReg[17], RD1_internal_MonDReg[18], RD1_internal_MonDReg[19], RD1_internal_MonDReg[20], RD1_internal_MonDReg[21], RD1_internal_MonDReg[22], RD1_internal_MonDReg[23], RD1_MonAReg[2], RD1_MonAReg[3], RD1_MonAReg[4], RD1_MonAReg[5], RD1_MonAReg[6], RD1_MonAReg[7], RD1_MonAReg[8], RD1_MonAReg[9]);

--CE1_q_a[22] is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|cpu_ociram_lpm_dram_bdp_component_module:cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_bp62:auto_generated|q_a[22]

CE1_q_a[22] = AMPP_FUNCTION(RD1L62, RD1_MonWr, QC2__clk0, QC2__clk0, S1_M_st_data[16], S1_M_st_data[17], S1_M_st_data[18], S1_M_st_data[19], S1_M_st_data[20], S1_M_st_data[21], S1_M_st_data[22], S1_M_st_data[23], V1L9, V1L10, V1L11, V1L12, V1L13, V1L14, V1L15, V1L16, V1L29, RD1_internal_MonDReg[16], RD1_internal_MonDReg[17], RD1_internal_MonDReg[18], RD1_internal_MonDReg[19], RD1_internal_MonDReg[20], RD1_internal_MonDReg[21], RD1_internal_MonDReg[22], RD1_internal_MonDReg[23], RD1_MonAReg[2], RD1_MonAReg[3], RD1_MonAReg[4], RD1_MonAReg[5], RD1_MonAReg[6], RD1_MonAReg[7], RD1_MonAReg[8], RD1_MonAReg[9]);

--CE1_q_a[23] is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|cpu_ociram_lpm_dram_bdp_component_module:cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_bp62:auto_generated|q_a[23]

CE1_q_a[23] = AMPP_FUNCTION(RD1L62, RD1_MonWr, QC2__clk0, QC2__clk0, S1_M_st_data[16], S1_M_st_data[17], S1_M_st_data[18], S1_M_st_data[19], S1_M_st_data[20], S1_M_st_data[21], S1_M_st_data[22], S1_M_st_data[23], V1L9, V1L10, V1L11, V1L12, V1L13, V1L14, V1L15, V1L16, V1L29, RD1_internal_MonDReg[16], RD1_internal_MonDReg[17], RD1_internal_MonDReg[18], RD1_internal_MonDReg[19], RD1_internal_MonDReg[20], RD1_internal_MonDReg[21], RD1_internal_MonDReg[22], RD1_internal_MonDReg[23], RD1_MonAReg[2], RD1_MonAReg[3], RD1_MonAReg[4], RD1_MonAReg[5], RD1_MonAReg[6], RD1_MonAReg[7], RD1_MonAReg[8], RD1_MonAReg[9]);

--CE1_q_b[16] is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|cpu_ociram_lpm_dram_bdp_component_module:cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_bp62:auto_generated|q_b[16]

CE1_q_b[16] = AMPP_FUNCTION(RD1L62, RD1_MonWr, QC2__clk0, QC2__clk0, S1_M_st_data[16], S1_M_st_data[17], S1_M_st_data[18], S1_M_st_data[19], S1_M_st_data[20], S1_M_st_data[21], S1_M_st_data[22], S1_M_st_data[23], V1L9, V1L10, V1L11, V1L12, V1L13, V1L14, V1L15, V1L16, V1L29, RD1_internal_MonDReg[16], RD1_internal_MonDReg[17], RD1_internal_MonDReg[18], RD1_internal_MonDReg[19], RD1_internal_MonDReg[20], RD1_internal_MonDReg[21], RD1_internal_MonDReg[22], RD1_internal_MonDReg[23], RD1_MonAReg[2], RD1_MonAReg[3], RD1_MonAReg[4], RD1_MonAReg[5], RD1_MonAReg[6], RD1_MonAReg[7], RD1_MonAReg[8], RD1_MonAReg[9]);

--CE1_q_b[17] is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|cpu_ociram_lpm_dram_bdp_component_module:cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_bp62:auto_generated|q_b[17]

CE1_q_b[17] = AMPP_FUNCTION(RD1L62, RD1_MonWr, QC2__clk0, QC2__clk0, S1_M_st_data[16], S1_M_st_data[17], S1_M_st_data[18], S1_M_st_data[19], S1_M_st_data[20], S1_M_st_data[21], S1_M_st_data[22], S1_M_st_data[23], V1L9, V1L10, V1L11, V1L12, V1L13, V1L14, V1L15, V1L16, V1L29, RD1_internal_MonDReg[16], RD1_internal_MonDReg[17], RD1_internal_MonDReg[18], RD1_internal_MonDReg[19], RD1_internal_MonDReg[20], RD1_internal_MonDReg[21], RD1_internal_MonDReg[22], RD1_internal_MonDReg[23], RD1_MonAReg[2], RD1_MonAReg[3], RD1_MonAReg[4], RD1_MonAReg[5], RD1_MonAReg[6], RD1_MonAReg[7], RD1_MonAReg[8], RD1_MonAReg[9]);

--CE1_q_b[18] is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|cpu_ociram_lpm_dram_bdp_component_module:cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_bp62:auto_generated|q_b[18]

CE1_q_b[18] = AMPP_FUNCTION(RD1L62, RD1_MonWr, QC2__clk0, QC2__clk0, S1_M_st_data[16], S1_M_st_data[17], S1_M_st_data[18], S1_M_st_data[19], S1_M_st_data[20], S1_M_st_data[21], S1_M_st_data[22], S1_M_st_data[23], V1L9, V1L10, V1L11, V1L12, V1L13, V1L14, V1L15, V1L16, V1L29, RD1_internal_MonDReg[16], RD1_internal_MonDReg[17], RD1_internal_MonDReg[18], RD1_internal_MonDReg[19], RD1_internal_MonDReg[20], RD1_internal_MonDReg[21], RD1_internal_MonDReg[22], RD1_internal_MonDReg[23], RD1_MonAReg[2], RD1_MonAReg[3], RD1_MonAReg[4], RD1_MonAReg[5], RD1_MonAReg[6], RD1_MonAReg[7], RD1_MonAReg[8], RD1_MonAReg[9]);

--CE1_q_b[19] is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|cpu_ociram_lpm_dram_bdp_component_module:cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_bp62:auto_generated|q_b[19]

CE1_q_b[19] = AMPP_FUNCTION(RD1L62, RD1_MonWr, QC2__clk0, QC2__clk0, S1_M_st_data[16], S1_M_st_data[17], S1_M_st_data[18], S1_M_st_data[19], S1_M_st_data[20], S1_M_st_data[21], S1_M_st_data[22], S1_M_st_data[23], V1L9, V1L10, V1L11, V1L12, V1L13, V1L14, V1L15, V1L16, V1L29, RD1_internal_MonDReg[16], RD1_internal_MonDReg[17], RD1_internal_MonDReg[18], RD1_internal_MonDReg[19], RD1_internal_MonDReg[20], RD1_internal_MonDReg[21], RD1_internal_MonDReg[22], RD1_internal_MonDReg[23], RD1_MonAReg[2], RD1_MonAReg[3], RD1_MonAReg[4], RD1_MonAReg[5], RD1_MonAReg[6], RD1_MonAReg[7], RD1_MonAReg[8], RD1_MonAReg[9]);

--CE1_q_b[20] is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|cpu_ociram_lpm_dram_bdp_component_module:cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_bp62:auto_generated|q_b[20]

CE1_q_b[20] = AMPP_FUNCTION(RD1L62, RD1_MonWr, QC2__clk0, QC2__clk0, S1_M_st_data[16], S1_M_st_data[17], S1_M_st_data[18], S1_M_st_data[19], S1_M_st_data[20], S1_M_st_data[21], S1_M_st_data[22], S1_M_st_data[23], V1L9, V1L10, V1L11, V1L12, V1L13, V1L14, V1L15, V1L16, V1L29, RD1_internal_MonDReg[16], RD1_internal_MonDReg[17], RD1_internal_MonDReg[18], RD1_internal_MonDReg[19], RD1_internal_MonDReg[20], RD1_internal_MonDReg[21], RD1_internal_MonDReg[22], RD1_internal_MonDReg[23], RD1_MonAReg[2], RD1_MonAReg[3], RD1_MonAReg[4], RD1_MonAReg[5], RD1_MonAReg[6], RD1_MonAReg[7], RD1_MonAReg[8], RD1_MonAReg[9]);

--CE1_q_b[21] is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|cpu_ociram_lpm_dram_bdp_component_module:cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_bp62:auto_generated|q_b[21]

CE1_q_b[21] = AMPP_FUNCTION(RD1L62, RD1_MonWr, QC2__clk0, QC2__clk0, S1_M_st_data[16], S1_M_st_data[17], S1_M_st_data[18], S1_M_st_data[19], S1_M_st_data[20], S1_M_st_data[21], S1_M_st_data[22], S1_M_st_data[23], V1L9, V1L10, V1L11, V1L12, V1L13, V1L14, V1L15, V1L16, V1L29, RD1_internal_MonDReg[16], RD1_internal_MonDReg[17], RD1_internal_MonDReg[18], RD1_internal_MonDReg[19], RD1_internal_MonDReg[20], RD1_internal_MonDReg[21], RD1_internal_MonDReg[22], RD1_internal_MonDReg[23], RD1_MonAReg[2], RD1_MonAReg[3], RD1_MonAReg[4], RD1_MonAReg[5], RD1_MonAReg[6], RD1_MonAReg[7], RD1_MonAReg[8], RD1_MonAReg[9]);

--CE1_q_b[22] is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|cpu_ociram_lpm_dram_bdp_component_module:cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_bp62:auto_generated|q_b[22]

CE1_q_b[22] = AMPP_FUNCTION(RD1L62, RD1_MonWr, QC2__clk0, QC2__clk0, S1_M_st_data[16], S1_M_st_data[17], S1_M_st_data[18], S1_M_st_data[19], S1_M_st_data[20], S1_M_st_data[21], S1_M_st_data[22], S1_M_st_data[23], V1L9, V1L10, V1L11, V1L12, V1L13, V1L14, V1L15, V1L16, V1L29, RD1_internal_MonDReg[16], RD1_internal_MonDReg[17], RD1_internal_MonDReg[18], RD1_internal_MonDReg[19], RD1_internal_MonDReg[20], RD1_internal_MonDReg[21], RD1_internal_MonDReg[22], RD1_internal_MonDReg[23], RD1_MonAReg[2], RD1_MonAReg[3], RD1_MonAReg[4], RD1_MonAReg[5], RD1_MonAReg[6], RD1_MonAReg[7], RD1_MonAReg[8], RD1_MonAReg[9]);

--CE1_q_b[23] is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|cpu_ociram_lpm_dram_bdp_component_module:cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_bp62:auto_generated|q_b[23]

CE1_q_b[23] = AMPP_FUNCTION(RD1L62, RD1_MonWr, QC2__clk0, QC2__clk0, S1_M_st_data[16], S1_M_st_data[17], S1_M_st_data[18], S1_M_st_data[19], S1_M_st_data[20], S1_M_st_data[21], S1_M_st_data[22], S1_M_st_data[23], V1L9, V1L10, V1L11, V1L12, V1L13, V1L14, V1L15, V1L16, V1L29, RD1_internal_MonDReg[16], RD1_internal_MonDReg[17], RD1_internal_MonDReg[18], RD1_internal_MonDReg[19], RD1_internal_MonDReg[20], RD1_internal_MonDReg[21], RD1_internal_MonDReg[22], RD1_internal_MonDReg[23], RD1_MonAReg[2], RD1_MonAReg[3], RD1_MonAReg[4], RD1_MonAReg[5], RD1_MonAReg[6], RD1_MonAReg[7], RD1_MonAReg[8], RD1_MonAReg[9]);

--WC1L20 is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|readdata[18]~1339

--operation mode is normal

WC1L20 = AMPP_FUNCTION(CE1_q_a[18], V1L4, S1_ic_fill_line[5], S1_M_alu_result[10]);

--DD1_q_b[2] is std_1c20:inst|cpu:the_cpu|cpu_register_bank_b_module:cpu_register_bank_b|altsyncram:the_altsyncram|altsyncram_4vd1:auto_generated|q_b[2]

--RAM Block Operation Mode: Simple Dual-Port

--Port A Depth: 32, Port A Width: 1, Port B Depth: 32, Port B Width: 1

--Port A Logical Depth: 32, Port A Logical Width: 32, Port B Logical Depth: 32, Port B Logical Width: 32

--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered

DD1_q_b[2] = AMPP_FUNCTION(GND, GND, QC2__clk0, QC2__clk0, !S1_M_wr_dst_reg, S1_W_stall, S1L1288, S1_M_dst_regnum[0], S1_M_dst_regnum[1], S1_M_dst_regnum[2], S1_M_dst_regnum[3], S1_M_dst_regnum[4], AD1_q_b[22], AD1_q_b[23], AD1_q_b[24], AD1_q_b[25], AD1_q_b[26]);

--AD1_q_b[12] is std_1c20:inst|cpu:the_cpu|cpu_ic_data_module:cpu_ic_data|altsyncram:the_altsyncram|altsyncram_qmb1:auto_generated|q_b[12]

--RAM Block Operation Mode: Simple Dual-Port

--Port A Depth: 1024, Port A Width: 1, Port B Depth: 1024, Port B Width: 1

--Port A Logical Depth: 1024, Port A Logical Width: 32, Port B Logical Depth: 1024, Port B Logical Width: 32

--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered

AD1_q_b[12] = AMPP_FUNCTION(GND, GND, QC2__clk0, QC2__clk0, S1_i_readdatavalid_d1, S1_W_stall, S1_i_readdata_d1[12], S1_ic_fill_dp_offset[0], S1_ic_fill_dp_offset[1], S1_ic_fill_dp_offset[2], S1_ic_fill_line[0], S1_ic_fill_line[1], S1_ic_fill_line[2], S1_ic_fill_line[3], S1_ic_fill_line[4], S1_ic_fill_line[5], S1_ic_fill_line[6], S1L789, S1L792, S1L795, S1L821, S1L824, S1L827, S1L830, S1L833, S1L836, S1L839);

--AD1_q_b[13] is std_1c20:inst|cpu:the_cpu|cpu_ic_data_module:cpu_ic_data|altsyncram:the_altsyncram|altsyncram_qmb1:auto_generated|q_b[13]

--RAM Block Operation Mode: Simple Dual-Port

--Port A Depth: 1024, Port A Width: 1, Port B Depth: 1024, Port B Width: 1

--Port A Logical Depth: 1024, Port A Logical Width: 32, Port B Logical Depth: 1024, Port B Logical Width: 32

--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered

AD1_q_b[13] = AMPP_FUNCTION(GND, GND, QC2__clk0, QC2__clk0, S1_i_readdatavalid_d1, S1_W_stall, S1_i_readdata_d1[13], S1_ic_fill_dp_offset[0], S1_ic_fill_dp_offset[1], S1_ic_fill_dp_offset[2], S1_ic_fill_line[0], S1_ic_fill_line[1], S1_ic_fill_line[2], S1_ic_fill_line[3], S1_ic_fill_line[4], S1_ic_fill_line[5], S1_ic_fill_line[6], S1L789, S1L792, S1L795, S1L821, S1L824, S1L827, S1L830, S1L833, S1L836, S1L839);

--AD1_q_b[11] is std_1c20:inst|cpu:the_cpu|cpu_ic_data_module:cpu_ic_data|altsyncram:the_altsyncram|altsyncram_qmb1:auto_generated|q_b[11]

--RAM Block Operation Mode: Simple Dual-Port

--Port A Depth: 1024, Port A Width: 1, Port B Depth: 1024, Port B Width: 1

--Port A Logical Depth: 1024, Port A Logical Width: 32, Port B Logical Depth: 1024, Port B Logical Width: 32

--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered

AD1_q_b[11] = AMPP_FUNCTION(GND, GND, QC2__clk0, QC2__clk0, S1_i_readdatavalid_d1, S1_W_stall, S1_i_readdata_d1[11], S1_ic_fill_dp_offset[0], S1_ic_fill_dp_offset[1], S1_ic_fill_dp_offset[2], S1_ic_fill_line[0], S1_ic_fill_line[1], S1_ic_fill_line[2], S1_ic_fill_line[3], S1_ic_fill_line[4], S1_ic_fill_line[5], S1_ic_fill_line[6], S1L789, S1L792, S1L795, S1L821, S1L824, S1L827, S1L830, S1L833, S1L836, S1L839);

--AD1_q_b[14] is std_1c20:inst|cpu:the_cpu|cpu_ic_data_module:cpu_ic_data|altsyncram:the_altsyncram|altsyncram_qmb1:auto_generated|q_b[14]

--RAM Block Operation Mode: Simple Dual-Port

--Port A Depth: 1024, Port A Width: 1, Port B Depth: 1024, Port B Width: 1

--Port A Logical Depth: 1024, Port A Logical Width: 32, Port B Logical Depth: 1024, Port B Logical Width: 32

--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered

AD1_q_b[14] = AMPP_FUNCTION(GND, GND, QC2__clk0, QC2__clk0, S1_i_readdatavalid_d1, S1_W_stall, S1_i_readdata_d1[14], S1_ic_fill_dp_offset[0], S1_ic_fill_dp_offset[1], S1_ic_fill_dp_offset[2], S1_ic_fill_line[0], S1_ic_fill_line[1], S1_ic_fill_line[2], S1_ic_fill_line[3], S1_ic_fill_line[4], S1_ic_fill_line[5], S1_ic_fill_line[6], S1L789, S1L792, S1L795, S1L821, S1L824, S1L827, S1L830, S1L833, S1L836, S1L839);

--S1L872 is std_1c20:inst|cpu:the_cpu|F_pc_plus_one[0]~48

--operation mode is arithmetic

S1L872 = AMPP_FUNCTION(S1_F_pc[0]);

--S1L873 is std_1c20:inst|cpu:the_cpu|F_pc_plus_one[0]~49

--operation mode is arithmetic

S1L873 = AMPP_FUNCTION(S1_F_pc[0]);

--AD1_q_b[21] is std_1c20:inst|cpu:the_cpu|cpu_ic_data_module:cpu_ic_data|altsyncram:the_altsyncram|altsyncram_qmb1:auto_generated|q_b[21]

--RAM Block Operation Mode: Simple Dual-Port

--Port A Depth: 1024, Port A Width: 1, Port B Depth: 1024, Port B Width: 1

--Port A Logical Depth: 1024, Port A Logical Width: 32, Port B Logical Depth: 1024, Port B Logical Width: 32

--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered

AD1_q_b[21] = AMPP_FUNCTION(GND, GND, QC2__clk0, QC2__clk0, S1_i_readdatavalid_d1, S1_W_stall, S1_i_readdata_d1[21], S1_ic_fill_dp_offset[0], S1_ic_fill_dp_offset[1], S1_ic_fill_dp_offset[2], S1_ic_fill_line[0], S1_ic_fill_line[1], S1_ic_fill_line[2], S1_ic_fill_line[3], S1_ic_fill_line[4], S1_ic_fill_line[5], S1_ic_fill_line[6], S1L789, S1L792, S1L795, S1L821, S1L824, S1L827, S1L830, S1L833, S1L836, S1L839);

--S1L770 is std_1c20:inst|cpu:the_cpu|Equal53~861

--operation mode is normal

S1L770 = AMPP_FUNCTION(S1_D_iw[0], S1_D_iw[1], S1_D_iw[2], S1_D_iw[3]);

--S1L207 is std_1c20:inst|cpu:the_cpu|D_ctrl_alu_subtract~405

--operation mode is normal

S1L207 = AMPP_FUNCTION(S1L760, S1L768, S1L770, S1_D_iw[4]);

--S1L208 is std_1c20:inst|cpu:the_cpu|D_ctrl_alu_subtract~406

--operation mode is normal

S1L208 = AMPP_FUNCTION(S1_D_iw[4], S1L767, S1L769);

--S1L209 is std_1c20:inst|cpu:the_cpu|D_ctrl_alu_subtract~407

--operation mode is normal

S1L209 = AMPP_FUNCTION(S1L760, S1_D_iw[5], S1_D_iw[12], S1_D_iw[13]);

--S1L210 is std_1c20:inst|cpu:the_cpu|D_ctrl_alu_subtract~408

--operation mode is normal

S1L210 = AMPP_FUNCTION(S1_D_iw[14], S1_D_iw[15], S1_D_iw[11]);

--AD1_q_b[16] is std_1c20:inst|cpu:the_cpu|cpu_ic_data_module:cpu_ic_data|altsyncram:the_altsyncram|altsyncram_qmb1:auto_generated|q_b[16]

--RAM Block Operation Mode: Simple Dual-Port

--Port A Depth: 1024, Port A Width: 1, Port B Depth: 1024, Port B Width: 1

--Port A Logical Depth: 1024, Port A Logical Width: 32, Port B Logical Depth: 1024, Port B Logical Width: 32

--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered

AD1_q_b[16] = AMPP_FUNCTION(GND, GND, QC2__clk0, QC2__clk0, S1_i_readdatavalid_d1, S1_W_stall, S1_i_readdata_d1[16], S1_ic_fill_dp_offset[0], S1_ic_fill_dp_offset[1], S1_ic_fill_dp_offset[2], S1_ic_fill_line[0], S1_ic_fill_line[1], S1_ic_fill_line[2], S1_ic_fill_line[3], S1_ic_fill_line[4], S1_ic_fill_line[5], S1_ic_fill_line[6], S1L789, S1L792, S1L795, S1L821, S1L824, S1L827, S1L830, S1L833, S1L836, S1L839);

--S1_M_shift_rot_cnt[1] is std_1c20:inst|cpu:the_cpu|M_shift_rot_cnt[1]

--operation mode is normal

S1_M_shift_rot_cnt[1] = AMPP_FUNCTION(QC2__clk0, S1L120, F1_data_out);

--S1_M_shift_rot_cnt[0] is std_1c20:inst|cpu:the_cpu|M_shift_rot_cnt[0]

--operation mode is normal

S1_M_shift_rot_cnt[0] = AMPP_FUNCTION(QC2__clk0, S1L121, S1L635, S1_M_shift_rot_stall, F1_data_out);

--S1_M_shift_rot_cnt[2] is std_1c20:inst|cpu:the_cpu|M_shift_rot_cnt[2]

--operation mode is normal

S1_M_shift_rot_cnt[2] = AMPP_FUNCTION(QC2__clk0, S1L123, S1L637, S1_M_shift_rot_stall, F1_data_out);

--S1_M_shift_rot_cnt[4] is std_1c20:inst|cpu:the_cpu|M_shift_rot_cnt[4]

--operation mode is normal

S1_M_shift_rot_cnt[4] = AMPP_FUNCTION(QC2__clk0, S1L125, S1L639, S1_M_shift_rot_stall, F1_data_out);

--S1_M_shift_rot_cnt[3] is std_1c20:inst|cpu:the_cpu|M_shift_rot_cnt[3]

--operation mode is normal

S1_M_shift_rot_cnt[3] = AMPP_FUNCTION(QC2__clk0, S1L126, S1L638, S1_M_shift_rot_stall, F1_data_out);

--Z1_control_register[0] is std_1c20:inst|high_res_timer:the_high_res_timer|control_register[0]

--operation mode is normal

Z1_control_register[0]_lut_out = S1_M_st_data[0];

Z1_control_register[0] = DFFEAS(Z1_control_register[0]_lut_out, QC2__clk0, F1_data_out, , Z1_control_wr_strobe, , , , );

--Z1_timeout_occurred is std_1c20:inst|high_res_timer:the_high_res_timer|timeout_occurred

--operation mode is normal

Z1_timeout_occurred_lut_out = Z1L210 & (!XE1L21 # !AB1_cpu_data_master_requests_high_res_timer_s1 # !RB1L7);

Z1_timeout_occurred = DFFEAS(Z1_timeout_occurred_lut_out, QC2__clk0, F1_data_out, , , , , , );

--FD1_internal_oci_ienable1[3] is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_avalon_reg:the_cpu_nios2_avalon_reg|internal_oci_ienable1[3]

--operation mode is normal

FD1_internal_oci_ienable1[3] = AMPP_FUNCTION(QC2__clk0, S1_M_st_data[3], F1_data_out, FD1L13);

--G1_readdata[3] is std_1c20:inst|button_pio:the_button_pio|readdata[3]

--operation mode is normal

G1_readdata[3]_lut_out = S1_M_alu_result[3] & G1L30 # !S1_M_alu_result[3] & (in_port_to_the_button_pio[3] & !S1_M_alu_result[2]);

G1_readdata[3] = DFFEAS(G1_readdata[3]_lut_out, QC2__clk0, F1_data_out, , , , , , );

--T1L50 is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[3]~5178

--operation mode is normal

T1L50 = !UB1_cpu_data_master_granted_sysid_control_slave & !JB1_cpu_data_master_requests_reconfig_request_pio_s1 & (G1_readdata[3] # !H1_cpu_data_master_requests_button_pio_s1);

--XE1_readdata[3] is std_1c20:inst|uart1:the_uart1|uart1_regs:the_uart1_regs|readdata[3]

--operation mode is normal

XE1_readdata[3]_lut_out = !S1_M_alu_result[4] & (S1_M_alu_result[2] & XE1L54 # !S1_M_alu_result[2] & (XE1L55));

XE1_readdata[3] = DFFEAS(XE1_readdata[3]_lut_out, QC2__clk0, F1_data_out, , , , , , );

--RB1_readdata[3] is std_1c20:inst|sys_clk_timer:the_sys_clk_timer|readdata[3]

--operation mode is normal

RB1_readdata[3]_lut_out = RB1L166 # RB1L167 # XE1L20 & !RB1_period_l_register[3];

RB1_readdata[3] = DFFEAS(RB1_readdata[3]_lut_out, QC2__clk0, F1_data_out, , , , , , );

--SB1L3 is std_1c20:inst|sys_clk_timer_s1_arbitrator:the_sys_clk_timer_s1|cpu_data_master_requests_sys_clk_timer_s1~181

--operation mode is normal

SB1L3 = SB1L2 & (!S1_M_alu_result[5]);

--T1L51 is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[3]~5179

--operation mode is normal

T1L51 = S1_M_alu_result[6] & XE1_readdata[3] # !S1_M_alu_result[6] & (RB1_readdata[3]) # !SB1L3;

--T1_registered_cpu_data_master_readdata[3] is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|registered_cpu_data_master_readdata[3]

--operation mode is normal

T1_registered_cpu_data_master_readdata[3]_lut_out = T1L246 & T1L276 & (KB1_za_data[3] # !NB1L17);

T1_registered_cpu_data_master_readdata[3] = DFFEAS(T1_registered_cpu_data_master_readdata[3]_lut_out, QC2__clk0, F1_data_out, , , , , , );

--T1L52 is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[3]~5180

--operation mode is normal

T1L52 = T1_registered_cpu_data_master_readdata[3] # !N1_cpu_data_master_requests_clock_1_in & (!CB1L2 # !UB1L9);

--Z1_readdata[3] is std_1c20:inst|high_res_timer:the_high_res_timer|readdata[3]

--operation mode is normal

Z1_readdata[3]_lut_out = Z1L165 # Z1L166 # XE1L20 & !Z1_period_l_register[3];

Z1_readdata[3] = DFFEAS(Z1_readdata[3]_lut_out, QC2__clk0, F1_data_out, , , , , , );

--T1L53 is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[3]~5181

--operation mode is normal

T1L53 = T1L52 & (Z1_readdata[3] # !AB1_cpu_data_master_requests_high_res_timer_s1);

--Y1_internal_incoming_ext_ram_bus_data[3] is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|internal_incoming_ext_ram_bus_data[3]

--operation mode is normal

Y1_internal_incoming_ext_ram_bus_data[3]_lut_out = A1L113;

Y1_internal_incoming_ext_ram_bus_data[3] = DFFEAS(Y1_internal_incoming_ext_ram_bus_data[3]_lut_out, QC2__clk0, F1_data_out, , , , , , );

--T1_dbs_8_reg_segment_0[3] is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|dbs_8_reg_segment_0[3]

--operation mode is normal

T1_dbs_8_reg_segment_0[3]_lut_out = Y1_internal_incoming_ext_ram_bus_data[3];

T1_dbs_8_reg_segment_0[3] = DFFEAS(T1_dbs_8_reg_segment_0[3]_lut_out, QC2__clk0, F1_data_out, , T1L294, , , , );

--T1L54 is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[3]~5182

--operation mode is normal

T1L54 = T1_dbs_8_reg_segment_0[3] & (!A1L138 & EB1L12) # !T1_dbs_8_reg_segment_0[3] & (Y1_cpu_data_master_requests_ext_flash_s1 # !A1L138 & EB1L12);

--T1L55 is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[3]~5183

--operation mode is normal

T1L55 = T1L54 # !T1_registered_cpu_data_master_readdata[3] & (NB1L17 # K1_cpu_data_master_requests_clock_0_in);

--T1L56 is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[3]~5184

--operation mode is normal

T1L56 = !T1L55 & (Y1_internal_incoming_ext_ram_bus_data[3] # !Y1L78 & !Y1_cpu_data_master_requests_ext_ram_s1);

--T1L57 is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[3]~5185

--operation mode is normal

T1L57 = T1L50 & T1L51 & T1L53 & T1L56;

--DE1_data_to_cpu[3] is std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|data_to_cpu[3]

--operation mode is normal

DE1_data_to_cpu[3]_lut_out = DE1L115 & DE1_iROE_reg # !DE1L115 & (DE1L3);

DE1_data_to_cpu[3] = DFFEAS(DE1_data_to_cpu[3]_lut_out, QC2__clk0, F1_data_out, , , DE1_ROE, , , DE1L116);

--FE1_q_a[3] is std_1c20:inst|epcs_controller:the_epcs_controller|altsyncram:the_boot_copier_rom|altsyncram_3h31:auto_generated|q_a[3]

--RAM Block Operation Mode: ROM

--Port A Depth: 128, Port A Width: 1

--Port A Logical Depth: 128, Port A Logical Width: 32

--Port A Input: Registered, Port A Output: Un-registered

FE1_q_a[3]_PORT_A_address = BUS(X1L14, X1L15, X1L16, X1L17, X1L18, X1L19, X1L20);

FE1_q_a[3]_PORT_A_address_reg = DFFE(FE1_q_a[3]_PORT_A_address, FE1_q_a[3]_clock_0, , , );

FE1_q_a[3]_clock_0 = QC2__clk0;

FE1_q_a[3]_PORT_A_data_out = MEMORY(, , FE1_q_a[3]_PORT_A_address_reg, , , , , , FE1_q_a[3]_clock_0, , , , , );

FE1_q_a[3] = FE1_q_a[3]_PORT_A_data_out[0];

--U1L113 is std_1c20:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_readdata~2398

--operation mode is normal

U1L113 = W1L1 & DE1_data_to_cpu[3] # !W1L1 & (FE1_q_a[3]);

--WC1L4 is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|readdata[3]~1340

--operation mode is normal

WC1L4 = AMPP_FUNCTION(FD1_internal_oci_single_step_mode1, FD1L3, CE1_q_a[3], V1L17);

--T1L209 is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata~775

--operation mode is normal

T1L209 = S1_M_alu_result[2] # !UB1L10 # !UB1L9;

--T1L178 is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[26]~5187

--operation mode is normal

T1L178 = T1L100 & T1L143 & T1L209 & !WB1_cpu_data_master_granted_uart1_s1;

--Y1_internal_incoming_ext_ram_bus_data[19] is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|internal_incoming_ext_ram_bus_data[19]

--operation mode is normal

Y1_internal_incoming_ext_ram_bus_data[19]_lut_out = A1L97;

Y1_internal_incoming_ext_ram_bus_data[19] = DFFEAS(Y1_internal_incoming_ext_ram_bus_data[19]_lut_out, QC2__clk0, F1_data_out, , , , , , );

--T1_dbs_8_reg_segment_2[3] is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|dbs_8_reg_segment_2[3]

--operation mode is normal

T1_dbs_8_reg_segment_2[3]_lut_out = Y1_internal_incoming_ext_ram_bus_data[3];

T1_dbs_8_reg_segment_2[3] = DFFEAS(T1_dbs_8_reg_segment_2[3]_lut_out, QC2__clk0, F1_data_out, , T1L296, , , , );

--T1_registered_cpu_data_master_readdata[19] is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|registered_cpu_data_master_readdata[19]

--operation mode is normal

T1_registered_cpu_data_master_readdata[19]_lut_out = T1L260 & !K1L6 & (BB1L21 # !CB1_cpu_data_master_requests_jtag_uart_avalon_jtag_slave);

T1_registered_cpu_data_master_readdata[19] = DFFEAS(T1_registered_cpu_data_master_readdata[19]_lut_out, QC2__clk0, F1_data_out, , , , , , );

--T1L155 is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[19]~5188

--operation mode is normal

T1L155 = T1_dbs_8_reg_segment_2[3] & (!T1_registered_cpu_data_master_readdata[19] & T1L151) # !T1_dbs_8_reg_segment_2[3] & (Y1_cpu_data_master_requests_ext_flash_s1 # !T1_registered_cpu_data_master_readdata[19] & T1L151);

--T1L156 is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[19]~5189

--operation mode is normal

T1L156 = !T1L155 & (Y1_internal_incoming_ext_ram_bus_data[19] # !Y1L78 & !Y1_cpu_data_master_requests_ext_ram_s1);

--FE1_q_a[19] is std_1c20:inst|epcs_controller:the_epcs_controller|altsyncram:the_boot_copier_rom|altsyncram_3h31:auto_generated|q_a[19]

--RAM Block Operation Mode: ROM

--Port A Depth: 128, Port A Width: 1

--Port A Logical Depth: 128, Port A Logical Width: 32

--Port A Input: Registered, Port A Output: Un-registered

FE1_q_a[19]_PORT_A_address = BUS(X1L14, X1L15, X1L16, X1L17, X1L18, X1L19, X1L20);

FE1_q_a[19]_PORT_A_address_reg = DFFE(FE1_q_a[19]_PORT_A_address, FE1_q_a[19]_clock_0, , , );

FE1_q_a[19]_clock_0 = QC2__clk0;

FE1_q_a[19]_PORT_A_data_out = MEMORY(, , FE1_q_a[19]_PORT_A_address_reg, , , , , , FE1_q_a[19]_clock_0, , , , , );

FE1_q_a[19] = FE1_q_a[19]_PORT_A_data_out[0];

--W1L5 is std_1c20:inst|epcs_controller:the_epcs_controller|readdata[19]~689

--operation mode is normal

W1L5 = FE1_q_a[19] & (!W1L1);

--T1L157 is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[19]~5190

--operation mode is normal

T1L157 = T1L178 & T1L156 & (W1L5 # !X1_cpu_data_master_requests_epcs_controller_epcs_control_port);

--WC1L21 is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|readdata[19]~1342

--operation mode is normal

WC1L21 = AMPP_FUNCTION(CE1_q_a[19], V1L4, S1_ic_fill_line[5], S1_M_alu_result[10]);

--AD1_q_b[9] is std_1c20:inst|cpu:the_cpu|cpu_ic_data_module:cpu_ic_data|altsyncram:the_altsyncram|altsyncram_qmb1:auto_generated|q_b[9]

--RAM Block Operation Mode: Simple Dual-Port

--Port A Depth: 1024, Port A Width: 1, Port B Depth: 1024, Port B Width: 1

--Port A Logical Depth: 1024, Port A Logical Width: 32, Port B Logical Depth: 1024, Port B Logical Width: 32

--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered

AD1_q_b[9] = AMPP_FUNCTION(GND, GND, QC2__clk0, QC2__clk0, S1_i_readdatavalid_d1, S1_W_stall, S1_i_readdata_d1[9], S1_ic_fill_dp_offset[0], S1_ic_fill_dp_offset[1], S1_ic_fill_dp_offset[2], S1_ic_fill_line[0], S1_ic_fill_line[1], S1_ic_fill_line[2], S1_ic_fill_line[3], S1_ic_fill_line[4], S1_ic_fill_line[5], S1_ic_fill_line[6], S1L789, S1L792, S1L795, S1L821, S1L824, S1L827, S1L830, S1L833, S1L836, S1L839);

--DD1_q_b[3] is std_1c20:inst|cpu:the_cpu|cpu_register_bank_b_module:cpu_register_bank_b|altsyncram:the_altsyncram|altsyncram_4vd1:auto_generated|q_b[3]

--RAM Block Operation Mode: Simple Dual-Port

--Port A Depth: 32, Port A Width: 1, Port B Depth: 32, Port B Width: 1

--Port A Logical Depth: 32, Port A Logical Width: 32, Port B Logical Depth: 32, Port B Logical Width: 32

--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered

DD1_q_b[3] = AMPP_FUNCTION(GND, GND, QC2__clk0, QC2__clk0, !S1_M_wr_dst_reg, S1_W_stall, S1L1291, S1_M_dst_regnum[0], S1_M_dst_regnum[1], S1_M_dst_regnum[2], S1_M_dst_regnum[3], S1_M_dst_regnum[4], AD1_q_b[22], AD1_q_b[23], AD1_q_b[24], AD1_q_b[25], AD1_q_b[26]);

--S1L874 is std_1c20:inst|cpu:the_cpu|F_pc_plus_one[1]~50

--operation mode is arithmetic

S1L874 = AMPP_FUNCTION(S1_F_pc[1], S1L873);

--S1L875 is std_1c20:inst|cpu:the_cpu|F_pc_plus_one[1]~51

--operation mode is arithmetic

S1L875 = AMPP_FUNCTION(S1_F_pc[1], S1L873);

--S1L819 is std_1c20:inst|cpu:the_cpu|F_ic_hit~127

--operation mode is normal

S1L819 = AMPP_FUNCTION(S1L815, S1L816);

--S1L775 is std_1c20:inst|cpu:the_cpu|Equal77~1064

--operation mode is normal

S1L775 = AMPP_FUNCTION(S1_D_iw[14], S1_D_iw[16]);

--S1L776 is std_1c20:inst|cpu:the_cpu|Equal77~1065

--operation mode is normal

S1L776 = AMPP_FUNCTION(S1L772, S1L775, S1_D_iw[11], S1_D_iw[15]);

--S1L221 is std_1c20:inst|cpu:the_cpu|D_ctrl_flush_pipe_always~582

--operation mode is normal

S1L221 = AMPP_FUNCTION(S1_D_iw[13], S1_D_iw[16]);

--S1L222 is std_1c20:inst|cpu:the_cpu|D_ctrl_flush_pipe_always~583

--operation mode is normal

S1L222 = AMPP_FUNCTION(S1L221, S1L771, S1_D_iw[11], S1_D_iw[12]);

--S1L232 is std_1c20:inst|cpu:the_cpu|D_ctrl_jmp_indirect~44

--operation mode is normal

S1L232 = AMPP_FUNCTION(S1_D_iw[11], S1_D_iw[16]);

--S1L223 is std_1c20:inst|cpu:the_cpu|D_ctrl_flush_pipe_always~584

--operation mode is normal

S1L223 = AMPP_FUNCTION(S1_D_iw[16], S1_D_iw[11], S1_D_iw[14], S1_D_iw[13]);

--S1L224 is std_1c20:inst|cpu:the_cpu|D_ctrl_flush_pipe_always~585

--operation mode is normal

S1L224 = AMPP_FUNCTION(S1L232, S1L223, S1_D_iw[15], S1_D_iw[12]);

--S1L225 is std_1c20:inst|cpu:the_cpu|D_ctrl_flush_pipe_always~586

--operation mode is normal

S1L225 = AMPP_FUNCTION(S1L760, S1L763, S1L222, S1L224);

--XC1L3 is std_1c20:inst|cpu:the_cpu|cpu_test_bench:the_cpu_test_bench|Add0~561

--operation mode is arithmetic

XC1L3 = AMPP_FUNCTION(S1L600, S1L666, XC1L5);

--YC1_result[31] is std_1c20:inst|cpu:the_cpu|lpm_add_sub:Add8|alt_stratix_add_sub:stratix_adder|result[31]

--operation mode is arithmetic

YC1_result[31] = AMPP_FUNCTION(S1L414, S1L413, YC1L63, S1_E_ctrl_alu_subtract);

--YC1L65 is std_1c20:inst|cpu:the_cpu|lpm_add_sub:Add8|alt_stratix_add_sub:stratix_adder|add_sub_cell[31]~COUT

--operation mode is arithmetic

YC1L65 = AMPP_FUNCTION(S1L414, S1L413, YC1L63, S1_E_ctrl_alu_subtract);

--SD1_internal_jdo1[19] is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|internal_jdo1[19]

--operation mode is normal

SD1_internal_jdo1[19] = AMPP_FUNCTION(A1L8, SD1_sr[19], VCC, SD1L145);

--SD1_internal_jdo1[18] is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|internal_jdo1[18]

--operation mode is normal

SD1_internal_jdo1[18] = AMPP_FUNCTION(A1L8, SD1_sr[18], VCC, SD1L145);

--SD1_sr[21] is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|sr[21]

--operation mode is normal

SD1_sr[21] = AMPP_FUNCTION(A1L5, SD1L8, SD1_sr[22], SD1L9, SD1L10, !C1_CLR_SIGNAL, SD1L12);

--C1_jtag_debug_mode is sld_hub:sld_hub_inst|jtag_debug_mode

--operation mode is normal

C1_jtag_debug_mode = AMPP_FUNCTION(A1L5, C1L32, C1_jtag_debug_mode, C1L33, FF1_state[15], FF1_state[0]);

--BF2_Q[0] is sld_hub:sld_hub_inst|sld_dffex:BROADCAST|Q[0]

--operation mode is normal

BF2_Q[0] = AMPP_FUNCTION(A1L5, GF1_dffe1a[1], BF2_Q[0], BF9_Q[0], C1L1, !C1_CLR_SIGNAL);

--SD1L145 is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|process3~14

--operation mode is normal

SD1L145 = AMPP_FUNCTION(BF8_Q[0], C1_jtag_debug_mode, C1_jtag_debug_mode_usr1, BF2_Q[0]);

--SD1_sr[20] is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|sr[20]

--operation mode is normal

SD1_sr[20] = AMPP_FUNCTION(A1L5, SD1L14, SD1_sr[21], SD1L9, SD1L15, !C1_CLR_SIGNAL, SD1L12);

--FF1_state[1] is sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state[1]

--operation mode is normal

FF1_state[1] = AMPP_FUNCTION(A1L5, FF1_state[0], FF1_state[8], FF1_state[1], FF1_state[15], VCC, A1L7);

--BF1_Q[0] is sld_hub:sld_hub_inst|sld_dffex:RESET|Q[0]

--operation mode is normal

BF1_Q[0] = AMPP_FUNCTION(A1L5, BF1_Q[0], GF1_dffe1a[7], C1L2, BF2_Q[0], C1_jtag_debug_mode_usr1);

--SD1_sr[34] is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|sr[34]

--operation mode is normal

SD1_sr[34] = AMPP_FUNCTION(A1L5, SD1_sr[35], SD1L16, SD1L142, SD1L17, !C1_CLR_SIGNAL, SD1L12);

--SD1_dr_update2 is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|dr_update2

--operation mode is normal

SD1_dr_update2 = AMPP_FUNCTION(QC2__clk0, SD1_dr_update1, VCC);

--SD1_dr_update1 is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|dr_update1

--operation mode is normal

SD1_dr_update1 = AMPP_FUNCTION(QC2__clk0, SD1_st_updatedr, VCC);

--SD1_sr[35] is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|sr[35]

--operation mode is normal

SD1_sr[35] = AMPP_FUNCTION(A1L5, SD1L18, SD1L134, SD1L19, SD1_ir[1], !C1_CLR_SIGNAL, !SD1_ir[0], SD1L12);

--BF5_Q[0] is sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:1:IRF|Q[0]

--operation mode is normal

BF5_Q[0] = AMPP_FUNCTION(A1L5, BF7_Q[0], BF3_Q[0], BF2_Q[0], !C1_CLR_SIGNAL, C1L26);

--SD1_st_updateir is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|st_updateir

--operation mode is normal

SD1_st_updateir = AMPP_FUNCTION(A1L5, SD1L146, VCC, A1L8);

--SD1L117 is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|ir[0]~0

--operation mode is normal

SD1L117 = AMPP_FUNCTION(SD1_st_updateir, C1_CLR_SIGNAL);

--BF5_Q[1] is sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:1:IRF|Q[1]

--operation mode is normal

BF5_Q[1] = AMPP_FUNCTION(A1L5, BF7_Q[1], BF3_Q[1], BF2_Q[0], !C1_CLR_SIGNAL, C1L26);

--S1_E_ctrl_break is std_1c20:inst|cpu:the_cpu|E_ctrl_break

--operation mode is normal

S1_E_ctrl_break = AMPP_FUNCTION(QC2__clk0, S1_D_iw[13], S1L774, S1_D_iw[15], S1L233, F1_data_out, S1_W_stall);

--RD1L61 is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|module_input6~26

--operation mode is normal

RD1L61 = AMPP_FUNCTION(S1_internal_d_write, S1_hbreak_enabled, V1L4);

--FD1L14 is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_avalon_reg:the_cpu_nios2_avalon_reg|take_action_ocireg~15

--operation mode is normal

FD1L14 = AMPP_FUNCTION(FD1L1, FD1L2, RD1L61, V1L9);

--S1L912 is std_1c20:inst|cpu:the_cpu|F_pc_plus_one[20]~52

--operation mode is arithmetic

S1L912 = AMPP_FUNCTION(S1_F_pc[20], S1L911);

--S1L913 is std_1c20:inst|cpu:the_cpu|F_pc_plus_one[20]~53

--operation mode is arithmetic

S1L913 = AMPP_FUNCTION(S1_F_pc[20], S1L911);

--Y1_internal_incoming_ext_ram_bus_data[22] is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|internal_incoming_ext_ram_bus_data[22]

--operation mode is normal

Y1_internal_incoming_ext_ram_bus_data[22]_lut_out = A1L94;

Y1_internal_incoming_ext_ram_bus_data[22] = DFFEAS(Y1_internal_incoming_ext_ram_bus_data[22]_lut_out, QC2__clk0, F1_data_out, , , , , , );

--T1_dbs_8_reg_segment_2[6] is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|dbs_8_reg_segment_2[6]

--operation mode is normal

T1_dbs_8_reg_segment_2[6]_lut_out = Y1_internal_incoming_ext_ram_bus_data[6];

T1_dbs_8_reg_segment_2[6] = DFFEAS(T1_dbs_8_reg_segment_2[6]_lut_out, QC2__clk0, F1_data_out, , T1L296, , , , );

--T1_registered_cpu_data_master_readdata[22] is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|registered_cpu_data_master_readdata[22]

--operation mode is normal

T1_registered_cpu_data_master_readdata[22]_lut_out = T1L263 & !K1L6 & (BB1L24 # !CB1_cpu_data_master_requests_jtag_uart_avalon_jtag_slave);

T1_registered_cpu_data_master_readdata[22] = DFFEAS(T1_registered_cpu_data_master_readdata[22]_lut_out, QC2__clk0, F1_data_out, , , , , , );

--T1L164 is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[22]~5191

--operation mode is normal

T1L164 = NB1L17 # N1_cpu_data_master_requests_clock_1_in # K1_cpu_data_master_requests_clock_0_in # CB1_cpu_data_master_requests_jtag_uart_avalon_jtag_slave;

--T1L165 is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[22]~5192

--operation mode is normal

T1L165 = T1_dbs_8_reg_segment_2[6] & (!T1_registered_cpu_data_master_readdata[22] & T1L164) # !T1_dbs_8_reg_segment_2[6] & (Y1_cpu_data_master_requests_ext_flash_s1 # !T1_registered_cpu_data_master_readdata[22] & T1L164);

--T1L166 is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[22]~5193

--operation mode is normal

T1L166 = !T1L165 & (Y1_internal_incoming_ext_ram_bus_data[22] # !Y1L78 & !Y1_cpu_data_master_requests_ext_ram_s1);

--FE1_q_a[22] is std_1c20:inst|epcs_controller:the_epcs_controller|altsyncram:the_boot_copier_rom|altsyncram_3h31:auto_generated|q_a[22]

--RAM Block Operation Mode: ROM

--Port A Depth: 128, Port A Width: 1

--Port A Logical Depth: 128, Port A Logical Width: 32

--Port A Input: Registered, Port A Output: Un-registered

FE1_q_a[22]_PORT_A_address = BUS(X1L14, X1L15, X1L16, X1L17, X1L18, X1L19, X1L20);

FE1_q_a[22]_PORT_A_address_reg = DFFE(FE1_q_a[22]_PORT_A_address, FE1_q_a[22]_clock_0, , , );

FE1_q_a[22]_clock_0 = QC2__clk0;

FE1_q_a[22]_PORT_A_data_out = MEMORY(, , FE1_q_a[22]_PORT_A_address_reg, , , , , , FE1_q_a[22]_clock_0, , , , , );

FE1_q_a[22] = FE1_q_a[22]_PORT_A_data_out[0];

--W1L8 is std_1c20:inst|epcs_controller:the_epcs_controller|readdata[22]~690

--operation mode is normal

W1L8 = FE1_q_a[22] & (!W1L1);

--T1L167 is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[22]~5194

--operation mode is normal

T1L167 = T1L178 & T1L166 & (W1L8 # !X1_cpu_data_master_requests_epcs_controller_epcs_control_port);

--WC1L24 is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|readdata[22]~1343

--operation mode is normal

WC1L24 = AMPP_FUNCTION(CE1_q_a[22], V1L4, S1_ic_fill_line[5], S1_M_alu_result[10]);

--DE1_data_to_cpu[15] is std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|data_to_cpu[15]

--operation mode is normal

DE1_data_to_cpu[15]_lut_out = DE1L114 & DE1_endofpacketvalue_reg[15] # !DE1L114 & (DE1L113 & DE1_epcs_slave_select_reg[15]);

DE1_data_to_cpu[15] = DFFEAS(DE1_data_to_cpu[15]_lut_out, QC2__clk0, F1_data_out, , , , , , );

--FE1_q_a[15] is std_1c20:inst|epcs_controller:the_epcs_controller|altsyncram:the_boot_copier_rom|altsyncram_3h31:auto_generated|q_a[15]

--RAM Block Operation Mode: ROM

--Port A Depth: 128, Port A Width: 1

--Port A Logical Depth: 128, Port A Logical Width: 32

--Port A Input: Registered, Port A Output: Un-registered

FE1_q_a[15]_PORT_A_address = BUS(X1L14, X1L15, X1L16, X1L17, X1L18, X1L19, X1L20);

FE1_q_a[15]_PORT_A_address_reg = DFFE(FE1_q_a[15]_PORT_A_address, FE1_q_a[15]_clock_0, , , );

FE1_q_a[15]_clock_0 = QC2__clk0;

FE1_q_a[15]_PORT_A_data_out = MEMORY(, , FE1_q_a[15]_PORT_A_address_reg, , , , , , FE1_q_a[15]_clock_0, , , , , );

FE1_q_a[15] = FE1_q_a[15]_PORT_A_data_out[0];

--T1L201 is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata~211

--operation mode is normal

T1L201 = W1L1 & DE1_data_to_cpu[15] # !W1L1 & (FE1_q_a[15]) # !X1_cpu_data_master_requests_epcs_controller_epcs_control_port;

--Z1_readdata[15] is std_1c20:inst|high_res_timer:the_high_res_timer|readdata[15]

--operation mode is normal

Z1_readdata[15]_lut_out = S1_M_alu_result[3] & !S1_M_alu_result[4] & (Z1L189 $ !Z1L190) # !S1_M_alu_result[3] & S1_M_alu_result[4] & Z1L189;

Z1_readdata[15] = DFFEAS(Z1_readdata[15]_lut_out, QC2__clk0, F1_data_out, , , , , , );

--RB1_readdata[15] is std_1c20:inst|sys_clk_timer:the_sys_clk_timer|readdata[15]

--operation mode is normal

RB1_readdata[15]_lut_out = S1_M_alu_result[3] & !S1_M_alu_result[4] & (RB1L190 $ !RB1L191) # !S1_M_alu_result[3] & S1_M_alu_result[4] & RB1L190;

RB1_readdata[15] = DFFEAS(RB1_readdata[15]_lut_out, QC2__clk0, F1_data_out, , , , , , );

--T1L139 is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[15]~5195

--operation mode is normal

T1L139 = Z1_readdata[15] & (RB1_readdata[15] # !SB1_cpu_data_master_requests_sys_clk_timer_s1) # !Z1_readdata[15] & !AB1_cpu_data_master_requests_high_res_timer_s1 & (RB1_readdata[15] # !SB1_cpu_data_master_requests_sys_clk_timer_s1);

--Y1_internal_incoming_ext_ram_bus_data[15] is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|internal_incoming_ext_ram_bus_data[15]

--operation mode is normal

Y1_internal_incoming_ext_ram_bus_data[15]_lut_out = A1L101;

Y1_internal_incoming_ext_ram_bus_data[15] = DFFEAS(Y1_internal_incoming_ext_ram_bus_data[15]_lut_out, QC2__clk0, F1_data_out, , , , , , );

--T1_dbs_8_reg_segment_1[7] is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|dbs_8_reg_segment_1[7]

--operation mode is normal

T1_dbs_8_reg_segment_1[7]_lut_out = Y1_internal_incoming_ext_ram_bus_data[7];

T1_dbs_8_reg_segment_1[7] = DFFEAS(T1_dbs_8_reg_segment_1[7]_lut_out, QC2__clk0, F1_data_out, , T1L295, , , , );

--T1_registered_cpu_data_master_readdata[15] is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|registered_cpu_data_master_readdata[15]

--operation mode is normal

T1_registered_cpu_data_master_readdata[15]_lut_out = T1L258 & T1L286 & (KB1_za_data[15] # !NB1L17);

T1_registered_cpu_data_master_readdata[15] = DFFEAS(T1_registered_cpu_data_master_readdata[15]_lut_out, QC2__clk0, F1_data_out, , , , , , );

--T1L140 is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[15]~5196

--operation mode is normal

T1L140 = T1_dbs_8_reg_segment_1[7] & (!T1_registered_cpu_data_master_readdata[15] & T1L164) # !T1_dbs_8_reg_segment_1[7] & (Y1_cpu_data_master_requests_ext_flash_s1 # !T1_registered_cpu_data_master_readdata[15] & T1L164);

--T1L141 is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[15]~5197

--operation mode is normal

T1L141 = !T1L140 & (Y1_internal_incoming_ext_ram_bus_data[15] # !Y1L78 & !Y1_cpu_data_master_requests_ext_ram_s1);

--T1L142 is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[15]~5198

--operation mode is normal

T1L142 = T1L112 & T1L201 & T1L139 & T1L141;

--CE1_q_a[8] is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|cpu_ociram_lpm_dram_bdp_component_module:cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_bp62:auto_generated|q_a[8]

--RAM Block Operation Mode: True Dual-Port

--Port A Depth: 256, Port A Width: 8, Port B Depth: 256, Port B Width: 8

--Port A Logical Depth: 256, Port A Logical Width: 32, Port B Logical Depth: 256, Port B Logical Width: 32

--Port A Input: Registered, Port A Output: Un-registered, Port B Input: Registered, Port B Output: Un-registered

CE1_q_a[8] = AMPP_FUNCTION(RD1L62, RD1_MonWr, QC2__clk0, QC2__clk0, S1_M_st_data[8], S1_M_st_data[9], S1_M_st_data[10], S1_M_st_data[11], S1_M_st_data[12], S1_M_st_data[13], S1_M_st_data[14], S1_M_st_data[15], V1L9, V1L10, V1L11, V1L12, V1L13, V1L14, V1L15, V1L16, V1L28, RD1_internal_MonDReg[8], RD1_internal_MonDReg[9], RD1_internal_MonDReg[10], RD1_internal_MonDReg[11], RD1_internal_MonDReg[12], RD1_internal_MonDReg[13], RD1_internal_MonDReg[14], RD1_internal_MonDReg[15], RD1_MonAReg[2], RD1_MonAReg[3], RD1_MonAReg[4], RD1_MonAReg[5], RD1_MonAReg[6], RD1_MonAReg[7], RD1_MonAReg[8], RD1_MonAReg[9]);

--CE1_q_a[9] is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|cpu_ociram_lpm_dram_bdp_component_module:cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_bp62:auto_generated|q_a[9]

CE1_q_a[9] = AMPP_FUNCTION(RD1L62, RD1_MonWr, QC2__clk0, QC2__clk0, S1_M_st_data[8], S1_M_st_data[9], S1_M_st_data[10], S1_M_st_data[11], S1_M_st_data[12], S1_M_st_data[13], S1_M_st_data[14], S1_M_st_data[15], V1L9, V1L10, V1L11, V1L12, V1L13, V1L14, V1L15, V1L16, V1L28, RD1_internal_MonDReg[8], RD1_internal_MonDReg[9], RD1_internal_MonDReg[10], RD1_internal_MonDReg[11], RD1_internal_MonDReg[12], RD1_internal_MonDReg[13], RD1_internal_MonDReg[14], RD1_internal_MonDReg[15], RD1_MonAReg[2], RD1_MonAReg[3], RD1_MonAReg[4], RD1_MonAReg[5], RD1_MonAReg[6], RD1_MonAReg[7], RD1_MonAReg[8], RD1_MonAReg[9]);

--CE1_q_a[10] is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|cpu_ociram_lpm_dram_bdp_component_module:cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_bp62:auto_generated|q_a[10]

CE1_q_a[10] = AMPP_FUNCTION(RD1L62, RD1_MonWr, QC2__clk0, QC2__clk0, S1_M_st_data[8], S1_M_st_data[9], S1_M_st_data[10], S1_M_st_data[11], S1_M_st_data[12], S1_M_st_data[13], S1_M_st_data[14], S1_M_st_data[15], V1L9, V1L10, V1L11, V1L12, V1L13, V1L14, V1L15, V1L16, V1L28, RD1_internal_MonDReg[8], RD1_internal_MonDReg[9], RD1_internal_MonDReg[10], RD1_internal_MonDReg[11], RD1_internal_MonDReg[12], RD1_internal_MonDReg[13], RD1_internal_MonDReg[14], RD1_internal_MonDReg[15], RD1_MonAReg[2], RD1_MonAReg[3], RD1_MonAReg[4], RD1_MonAReg[5], RD1_MonAReg[6], RD1_MonAReg[7], RD1_MonAReg[8], RD1_MonAReg[9]);

--CE1_q_a[11] is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|cpu_ociram_lpm_dram_bdp_component_module:cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_bp62:auto_generated|q_a[11]

CE1_q_a[11] = AMPP_FUNCTION(RD1L62, RD1_MonWr, QC2__clk0, QC2__clk0, S1_M_st_data[8], S1_M_st_data[9], S1_M_st_data[10], S1_M_st_data[11], S1_M_st_data[12], S1_M_st_data[13], S1_M_st_data[14], S1_M_st_data[15], V1L9, V1L10, V1L11, V1L12, V1L13, V1L14, V1L15, V1L16, V1L28, RD1_internal_MonDReg[8], RD1_internal_MonDReg[9], RD1_internal_MonDReg[10], RD1_internal_MonDReg[11], RD1_internal_MonDReg[12], RD1_internal_MonDReg[13], RD1_internal_MonDReg[14], RD1_internal_MonDReg[15], RD1_MonAReg[2], RD1_MonAReg[3], RD1_MonAReg[4], RD1_MonAReg[5], RD1_MonAReg[6], RD1_MonAReg[7], RD1_MonAReg[8], RD1_MonAReg[9]);

--CE1_q_a[12] is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|cpu_ociram_lpm_dram_bdp_component_module:cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_bp62:auto_generated|q_a[12]

CE1_q_a[12] = AMPP_FUNCTION(RD1L62, RD1_MonWr, QC2__clk0, QC2__clk0, S1_M_st_data[8], S1_M_st_data[9], S1_M_st_data[10], S1_M_st_data[11], S1_M_st_data[12], S1_M_st_data[13], S1_M_st_data[14], S1_M_st_data[15], V1L9, V1L10, V1L11, V1L12, V1L13, V1L14, V1L15, V1L16, V1L28, RD1_internal_MonDReg[8], RD1_internal_MonDReg[9], RD1_internal_MonDReg[10], RD1_internal_MonDReg[11], RD1_internal_MonDReg[12], RD1_internal_MonDReg[13], RD1_internal_MonDReg[14], RD1_internal_MonDReg[15], RD1_MonAReg[2], RD1_MonAReg[3], RD1_MonAReg[4], RD1_MonAReg[5], RD1_MonAReg[6], RD1_MonAReg[7], RD1_MonAReg[8], RD1_MonAReg[9]);

--CE1_q_a[13] is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|cpu_ociram_lpm_dram_bdp_component_module:cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_bp62:auto_generated|q_a[13]

CE1_q_a[13] = AMPP_FUNCTION(RD1L62, RD1_MonWr, QC2__clk0, QC2__clk0, S1_M_st_data[8], S1_M_st_data[9], S1_M_st_data[10], S1_M_st_data[11], S1_M_st_data[12], S1_M_st_data[13], S1_M_st_data[14], S1_M_st_data[15], V1L9, V1L10, V1L11, V1L12, V1L13, V1L14, V1L15, V1L16, V1L28, RD1_internal_MonDReg[8], RD1_internal_MonDReg[9], RD1_internal_MonDReg[10], RD1_internal_MonDReg[11], RD1_internal_MonDReg[12], RD1_internal_MonDReg[13], RD1_internal_MonDReg[14], RD1_internal_MonDReg[15], RD1_MonAReg[2], RD1_MonAReg[3], RD1_MonAReg[4], RD1_MonAReg[5], RD1_MonAReg[6], RD1_MonAReg[7], RD1_MonAReg[8], RD1_MonAReg[9]);

--CE1_q_a[14] is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|cpu_ociram_lpm_dram_bdp_component_module:cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_bp62:auto_generated|q_a[14]

CE1_q_a[14] = AMPP_FUNCTION(RD1L62, RD1_MonWr, QC2__clk0, QC2__clk0, S1_M_st_data[8], S1_M_st_data[9], S1_M_st_data[10], S1_M_st_data[11], S1_M_st_data[12], S1_M_st_data[13], S1_M_st_data[14], S1_M_st_data[15], V1L9, V1L10, V1L11, V1L12, V1L13, V1L14, V1L15, V1L16, V1L28, RD1_internal_MonDReg[8], RD1_internal_MonDReg[9], RD1_internal_MonDReg[10], RD1_internal_MonDReg[11], RD1_internal_MonDReg[12], RD1_internal_MonDReg[13], RD1_internal_MonDReg[14], RD1_internal_MonDReg[15], RD1_MonAReg[2], RD1_MonAReg[3], RD1_MonAReg[4], RD1_MonAReg[5], RD1_MonAReg[6], RD1_MonAReg[7], RD1_MonAReg[8], RD1_MonAReg[9]);

--CE1_q_a[15] is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|cpu_ociram_lpm_dram_bdp_component_module:cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_bp62:auto_generated|q_a[15]

CE1_q_a[15] = AMPP_FUNCTION(RD1L62, RD1_MonWr, QC2__clk0, QC2__clk0, S1_M_st_data[8], S1_M_st_data[9], S1_M_st_data[10], S1_M_st_data[11], S1_M_st_data[12], S1_M_st_data[13], S1_M_st_data[14], S1_M_st_data[15], V1L9, V1L10, V1L11, V1L12, V1L13, V1L14, V1L15, V1L16, V1L28, RD1_internal_MonDReg[8], RD1_internal_MonDReg[9], RD1_internal_MonDReg[10], RD1_internal_MonDReg[11], RD1_internal_MonDReg[12], RD1_internal_MonDReg[13], RD1_internal_MonDReg[14], RD1_internal_MonDReg[15], RD1_MonAReg[2], RD1_MonAReg[3], RD1_MonAReg[4], RD1_MonAReg[5], RD1_MonAReg[6], RD1_MonAReg[7], RD1_MonAReg[8], RD1_MonAReg[9]);

--CE1_q_b[8] is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|cpu_ociram_lpm_dram_bdp_component_module:cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_bp62:auto_generated|q_b[8]

CE1_q_b[8] = AMPP_FUNCTION(RD1L62, RD1_MonWr, QC2__clk0, QC2__clk0, S1_M_st_data[8], S1_M_st_data[9], S1_M_st_data[10], S1_M_st_data[11], S1_M_st_data[12], S1_M_st_data[13], S1_M_st_data[14], S1_M_st_data[15], V1L9, V1L10, V1L11, V1L12, V1L13, V1L14, V1L15, V1L16, V1L28, RD1_internal_MonDReg[8], RD1_internal_MonDReg[9], RD1_internal_MonDReg[10], RD1_internal_MonDReg[11], RD1_internal_MonDReg[12], RD1_internal_MonDReg[13], RD1_internal_MonDReg[14], RD1_internal_MonDReg[15], RD1_MonAReg[2], RD1_MonAReg[3], RD1_MonAReg[4], RD1_MonAReg[5], RD1_MonAReg[6], RD1_MonAReg[7], RD1_MonAReg[8], RD1_MonAReg[9]);

--CE1_q_b[9] is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|cpu_ociram_lpm_dram_bdp_component_module:cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_bp62:auto_generated|q_b[9]

CE1_q_b[9] = AMPP_FUNCTION(RD1L62, RD1_MonWr, QC2__clk0, QC2__clk0, S1_M_st_data[8], S1_M_st_data[9], S1_M_st_data[10], S1_M_st_data[11], S1_M_st_data[12], S1_M_st_data[13], S1_M_st_data[14], S1_M_st_data[15], V1L9, V1L10, V1L11, V1L12, V1L13, V1L14, V1L15, V1L16, V1L28, RD1_internal_MonDReg[8], RD1_internal_MonDReg[9], RD1_internal_MonDReg[10], RD1_internal_MonDReg[11], RD1_internal_MonDReg[12], RD1_internal_MonDReg[13], RD1_internal_MonDReg[14], RD1_internal_MonDReg[15], RD1_MonAReg[2], RD1_MonAReg[3], RD1_MonAReg[4], RD1_MonAReg[5], RD1_MonAReg[6], RD1_MonAReg[7], RD1_MonAReg[8], RD1_MonAReg[9]);

--CE1_q_b[10] is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|cpu_ociram_lpm_dram_bdp_component_module:cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_bp62:auto_generated|q_b[10]

CE1_q_b[10] = AMPP_FUNCTION(RD1L62, RD1_MonWr, QC2__clk0, QC2__clk0, S1_M_st_data[8], S1_M_st_data[9], S1_M_st_data[10], S1_M_st_data[11], S1_M_st_data[12], S1_M_st_data[13], S1_M_st_data[14], S1_M_st_data[15], V1L9, V1L10, V1L11, V1L12, V1L13, V1L14, V1L15, V1L16, V1L28, RD1_internal_MonDReg[8], RD1_internal_MonDReg[9], RD1_internal_MonDReg[10], RD1_internal_MonDReg[11], RD1_internal_MonDReg[12], RD1_internal_MonDReg[13], RD1_internal_MonDReg[14], RD1_internal_MonDReg[15], RD1_MonAReg[2], RD1_MonAReg[3], RD1_MonAReg[4], RD1_MonAReg[5], RD1_MonAReg[6], RD1_MonAReg[7], RD1_MonAReg[8], RD1_MonAReg[9]);

--CE1_q_b[11] is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|cpu_ociram_lpm_dram_bdp_component_module:cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_bp62:auto_generated|q_b[11]

CE1_q_b[11] = AMPP_FUNCTION(RD1L62, RD1_MonWr, QC2__clk0, QC2__clk0, S1_M_st_data[8], S1_M_st_data[9], S1_M_st_data[10], S1_M_st_data[11], S1_M_st_data[12], S1_M_st_data[13], S1_M_st_data[14], S1_M_st_data[15], V1L9, V1L10, V1L11, V1L12, V1L13, V1L14, V1L15, V1L16, V1L28, RD1_internal_MonDReg[8], RD1_internal_MonDReg[9], RD1_internal_MonDReg[10], RD1_internal_MonDReg[11], RD1_internal_MonDReg[12], RD1_internal_MonDReg[13], RD1_internal_MonDReg[14], RD1_internal_MonDReg[15], RD1_MonAReg[2], RD1_MonAReg[3], RD1_MonAReg[4], RD1_MonAReg[5], RD1_MonAReg[6], RD1_MonAReg[7], RD1_MonAReg[8], RD1_MonAReg[9]);

--CE1_q_b[12] is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|cpu_ociram_lpm_dram_bdp_component_module:cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_bp62:auto_generated|q_b[12]

CE1_q_b[12] = AMPP_FUNCTION(RD1L62, RD1_MonWr, QC2__clk0, QC2__clk0, S1_M_st_data[8], S1_M_st_data[9], S1_M_st_data[10], S1_M_st_data[11], S1_M_st_data[12], S1_M_st_data[13], S1_M_st_data[14], S1_M_st_data[15], V1L9, V1L10, V1L11, V1L12, V1L13, V1L14, V1L15, V1L16, V1L28, RD1_internal_MonDReg[8], RD1_internal_MonDReg[9], RD1_internal_MonDReg[10], RD1_internal_MonDReg[11], RD1_internal_MonDReg[12], RD1_internal_MonDReg[13], RD1_internal_MonDReg[14], RD1_internal_MonDReg[15], RD1_MonAReg[2], RD1_MonAReg[3], RD1_MonAReg[4], RD1_MonAReg[5], RD1_MonAReg[6], RD1_MonAReg[7], RD1_MonAReg[8], RD1_MonAReg[9]);

--CE1_q_b[13] is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|cpu_ociram_lpm_dram_bdp_component_module:cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_bp62:auto_generated|q_b[13]

CE1_q_b[13] = AMPP_FUNCTION(RD1L62, RD1_MonWr, QC2__clk0, QC2__clk0, S1_M_st_data[8], S1_M_st_data[9], S1_M_st_data[10], S1_M_st_data[11], S1_M_st_data[12], S1_M_st_data[13], S1_M_st_data[14], S1_M_st_data[15], V1L9, V1L10, V1L11, V1L12, V1L13, V1L14, V1L15, V1L16, V1L28, RD1_internal_MonDReg[8], RD1_internal_MonDReg[9], RD1_internal_MonDReg[10], RD1_internal_MonDReg[11], RD1_internal_MonDReg[12], RD1_internal_MonDReg[13], RD1_internal_MonDReg[14], RD1_internal_MonDReg[15], RD1_MonAReg[2], RD1_MonAReg[3], RD1_MonAReg[4], RD1_MonAReg[5], RD1_MonAReg[6], RD1_MonAReg[7], RD1_MonAReg[8], RD1_MonAReg[9]);

--CE1_q_b[14] is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|cpu_ociram_lpm_dram_bdp_component_module:cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_bp62:auto_generated|q_b[14]

CE1_q_b[14] = AMPP_FUNCTION(RD1L62, RD1_MonWr, QC2__clk0, QC2__clk0, S1_M_st_data[8], S1_M_st_data[9], S1_M_st_data[10], S1_M_st_data[11], S1_M_st_data[12], S1_M_st_data[13], S1_M_st_data[14], S1_M_st_data[15], V1L9, V1L10, V1L11, V1L12, V1L13, V1L14, V1L15, V1L16, V1L28, RD1_internal_MonDReg[8], RD1_internal_MonDReg[9], RD1_internal_MonDReg[10], RD1_internal_MonDReg[11], RD1_internal_MonDReg[12], RD1_internal_MonDReg[13], RD1_internal_MonDReg[14], RD1_internal_MonDReg[15], RD1_MonAReg[2], RD1_MonAReg[3], RD1_MonAReg[4], RD1_MonAReg[5], RD1_MonAReg[6], RD1_MonAReg[7], RD1_MonAReg[8], RD1_MonAReg[9]);

--CE1_q_b[15] is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|cpu_ociram_lpm_dram_bdp_component_module:cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_bp62:auto_generated|q_b[15]

CE1_q_b[15] = AMPP_FUNCTION(RD1L62, RD1_MonWr, QC2__clk0, QC2__clk0, S1_M_st_data[8], S1_M_st_data[9], S1_M_st_data[10], S1_M_st_data[11], S1_M_st_data[12], S1_M_st_data[13], S1_M_st_data[14], S1_M_st_data[15], V1L9, V1L10, V1L11, V1L12, V1L13, V1L14, V1L15, V1L16, V1L28, RD1_internal_MonDReg[8], RD1_internal_MonDReg[9], RD1_internal_MonDReg[10], RD1_internal_MonDReg[11], RD1_internal_MonDReg[12], RD1_internal_MonDReg[13], RD1_internal_MonDReg[14], RD1_internal_MonDReg[15], RD1_MonAReg[2], RD1_MonAReg[3], RD1_MonAReg[4], RD1_MonAReg[5], RD1_MonAReg[6], RD1_MonAReg[7], RD1_MonAReg[8], RD1_MonAReg[9]);

--WC1L16 is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|readdata[15]~1344

--operation mode is normal

WC1L16 = AMPP_FUNCTION(CE1_q_a[15], V1L4, S1_ic_fill_line[5], S1_M_alu_result[10]);

--T1L208 is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata~772

--operation mode is normal

T1L208 = !UB1L10 # !UB1L9 # !S1_M_alu_result[2];

--T1L168 is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[23]~5199

--operation mode is normal

T1L168 = T1L100 & T1L143 & T1L208 & !WB1_cpu_data_master_granted_uart1_s1;

--Y1_internal_incoming_ext_ram_bus_data[23] is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|internal_incoming_ext_ram_bus_data[23]

--operation mode is normal

Y1_internal_incoming_ext_ram_bus_data[23]_lut_out = A1L93;

Y1_internal_incoming_ext_ram_bus_data[23] = DFFEAS(Y1_internal_incoming_ext_ram_bus_data[23]_lut_out, QC2__clk0, F1_data_out, , , , , , );

--T1_dbs_8_reg_segment_2[7] is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|dbs_8_reg_segment_2[7]

--operation mode is normal

T1_dbs_8_reg_segment_2[7]_lut_out = Y1_internal_incoming_ext_ram_bus_data[7];

T1_dbs_8_reg_segment_2[7] = DFFEAS(T1_dbs_8_reg_segment_2[7]_lut_out, QC2__clk0, F1_data_out, , T1L296, , , , );

--T1_registered_cpu_data_master_readdata[23] is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|registered_cpu_data_master_readdata[23]

--operation mode is normal

T1_registered_cpu_data_master_readdata[23]_lut_out = T1L264 & !K1L6 & (KB1_za_data[23] # !NB1L17);

T1_registered_cpu_data_master_readdata[23] = DFFEAS(T1_registered_cpu_data_master_readdata[23]_lut_out, QC2__clk0, F1_data_out, , , , , , );

--T1L169 is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[23]~5200

--operation mode is normal

T1L169 = T1_dbs_8_reg_segment_2[7] & (!T1_registered_cpu_data_master_readdata[23] & T1L164) # !T1_dbs_8_reg_segment_2[7] & (Y1_cpu_data_master_requests_ext_flash_s1 # !T1_registered_cpu_data_master_readdata[23] & T1L164);

--T1L170 is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[23]~5201

--operation mode is normal

T1L170 = !T1L169 & (Y1_internal_incoming_ext_ram_bus_data[23] # !Y1L78 & !Y1_cpu_data_master_requests_ext_ram_s1);

--FE1_q_a[23] is std_1c20:inst|epcs_controller:the_epcs_controller|altsyncram:the_boot_copier_rom|altsyncram_3h31:auto_generated|q_a[23]

--RAM Block Operation Mode: ROM

--Port A Depth: 128, Port A Width: 1

--Port A Logical Depth: 128, Port A Logical Width: 32

--Port A Input: Registered, Port A Output: Un-registered

FE1_q_a[23]_PORT_A_address = BUS(X1L14, X1L15, X1L16, X1L17, X1L18, X1L19, X1L20);

FE1_q_a[23]_PORT_A_address_reg = DFFE(FE1_q_a[23]_PORT_A_address, FE1_q_a[23]_clock_0, , , );

FE1_q_a[23]_clock_0 = QC2__clk0;

FE1_q_a[23]_PORT_A_data_out = MEMORY(, , FE1_q_a[23]_PORT_A_address_reg, , , , , , FE1_q_a[23]_clock_0, , , , , );

FE1_q_a[23] = FE1_q_a[23]_PORT_A_data_out[0];

--W1L9 is std_1c20:inst|epcs_controller:the_epcs_controller|readdata[23]~691

--operation mode is normal

W1L9 = FE1_q_a[23] & (!W1L1);

--T1L171 is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[23]~5202

--operation mode is normal

T1L171 = T1L168 & T1L170 & (W1L9 # !X1_cpu_data_master_requests_epcs_controller_epcs_control_port);

--WC1L25 is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|readdata[23]~1345

--operation mode is normal

WC1L25 = AMPP_FUNCTION(CE1_q_a[23], V1L4, S1_ic_fill_line[5], S1_M_alu_result[10]);

--T1L59 is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[4]~5203

--operation mode is normal

T1L59 = !JB1L3 & (!H1L2 # !SB1L2) # !S1_M_alu_result[5];

--RB1_readdata[7] is std_1c20:inst|sys_clk_timer:the_sys_clk_timer|readdata[7]

--operation mode is normal

RB1_readdata[7]_lut_out = S1_M_alu_result[3] & !S1_M_alu_result[4] & (RB1L174 $ !RB1L175) # !S1_M_alu_result[3] & S1_M_alu_result[4] & RB1L174;

RB1_readdata[7] = DFFEAS(RB1_readdata[7]_lut_out, QC2__clk0, F1_data_out, , , , , , );

--T1L84 is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[7]~5204

--operation mode is normal

T1L84 = T1L59 & (RB1_readdata[7] # !SB1_cpu_data_master_requests_sys_clk_timer_s1);

--Z1_readdata[7] is std_1c20:inst|high_res_timer:the_high_res_timer|readdata[7]

--operation mode is normal

Z1_readdata[7]_lut_out = S1_M_alu_result[3] & !S1_M_alu_result[4] & (Z1L173 $ !Z1L174) # !S1_M_alu_result[3] & S1_M_alu_result[4] & Z1L173;

Z1_readdata[7] = DFFEAS(Z1_readdata[7]_lut_out, QC2__clk0, F1_data_out, , , , , , );

--XE1_readdata[7] is std_1c20:inst|uart1:the_uart1|uart1_regs:the_uart1_regs|readdata[7]

--operation mode is normal

XE1_readdata[7]_lut_out = !S1_M_alu_result[4] & (S1_M_alu_result[2] & XE1L62 # !S1_M_alu_result[2] & (XE1L63));

XE1_readdata[7] = DFFEAS(XE1_readdata[7]_lut_out, QC2__clk0, F1_data_out, , , , , , );

--T1L85 is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[7]~5205

--operation mode is normal

T1L85 = Z1_readdata[7] & (XE1_readdata[7] # !WB1_cpu_data_master_granted_uart1_s1) # !Z1_readdata[7] & !AB1_cpu_data_master_requests_high_res_timer_s1 & (XE1_readdata[7] # !WB1_cpu_data_master_granted_uart1_s1);

--T1_registered_cpu_data_master_readdata[7] is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|registered_cpu_data_master_readdata[7]

--operation mode is normal

T1_registered_cpu_data_master_readdata[7]_lut_out = T1L250 & T1L280 & (KB1_za_data[7] # !NB1L17);

T1_registered_cpu_data_master_readdata[7] = DFFEAS(T1_registered_cpu_data_master_readdata[7]_lut_out, QC2__clk0, F1_data_out, , , , , , );

--T1L86 is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[7]~5206

--operation mode is normal

T1L86 = T1_registered_cpu_data_master_readdata[7] # !K1_cpu_data_master_requests_clock_0_in & (!CB1L2 # !UB1L9);

--Y1_internal_incoming_ext_ram_bus_data[7] is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|internal_incoming_ext_ram_bus_data[7]

--operation mode is normal

Y1_internal_incoming_ext_ram_bus_data[7]_lut_out = A1L109;

Y1_internal_incoming_ext_ram_bus_data[7] = DFFEAS(Y1_internal_incoming_ext_ram_bus_data[7]_lut_out, QC2__clk0, F1_data_out, , , , , , );

--T1_dbs_8_reg_segment_0[7] is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|dbs_8_reg_segment_0[7]

--operation mode is normal

T1_dbs_8_reg_segment_0[7]_lut_out = Y1_internal_incoming_ext_ram_bus_data[7];

T1_dbs_8_reg_segment_0[7] = DFFEAS(T1_dbs_8_reg_segment_0[7]_lut_out, QC2__clk0, F1_data_out, , T1L294, , , , );

--T1L87 is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[7]~5207

--operation mode is normal

T1L87 = T1_dbs_8_reg_segment_0[7] & (!A1L134 & EB1L12) # !T1_dbs_8_reg_segment_0[7] & (Y1_cpu_data_master_requests_ext_flash_s1 # !A1L134 & EB1L12);

--T1L88 is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[7]~5208

--operation mode is normal

T1L88 = T1L87 # !T1_registered_cpu_data_master_readdata[7] & (NB1L17 # N1_cpu_data_master_requests_clock_1_in);

--T1L89 is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[7]~5209

--operation mode is normal

T1L89 = !T1L88 & (Y1_internal_incoming_ext_ram_bus_data[7] # !Y1L78 & !Y1_cpu_data_master_requests_ext_ram_s1);

--T1L90 is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[7]~5210

--operation mode is normal

T1L90 = T1L84 & T1L85 & T1L86 & T1L89;

--DE1_data_to_cpu[7] is std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|data_to_cpu[7]

--operation mode is normal

DE1_data_to_cpu[7]_lut_out = DE1L115 & DE1_iRRDY_reg # !DE1L115 & (DE1L6);

DE1_data_to_cpu[7] = DFFEAS(DE1_data_to_cpu[7]_lut_out, QC2__clk0, F1_data_out, , , DE1_RRDY, , , DE1L116);

--FE1_q_a[7] is std_1c20:inst|epcs_controller:the_epcs_controller|altsyncram:the_boot_copier_rom|altsyncram_3h31:auto_generated|q_a[7]

--RAM Block Operation Mode: ROM

--Port A Depth: 128, Port A Width: 1

--Port A Logical Depth: 128, Port A Logical Width: 32

--Port A Input: Registered, Port A Output: Un-registered

FE1_q_a[7]_PORT_A_address = BUS(X1L14, X1L15, X1L16, X1L17, X1L18, X1L19, X1L20);

FE1_q_a[7]_PORT_A_address_reg = DFFE(FE1_q_a[7]_PORT_A_address, FE1_q_a[7]_clock_0, , , );

FE1_q_a[7]_clock_0 = QC2__clk0;

FE1_q_a[7]_PORT_A_data_out = MEMORY(, , FE1_q_a[7]_PORT_A_address_reg, , , , , , FE1_q_a[7]_clock_0, , , , , );

FE1_q_a[7] = FE1_q_a[7]_PORT_A_data_out[0];

--U1L114 is std_1c20:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_readdata~2399

--operation mode is normal

U1L114 = W1L1 & DE1_data_to_cpu[7] # !W1L1 & (FE1_q_a[7]);

--T1L91 is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[7]~5211

--operation mode is normal

T1L91 = T1L90 & (U1L114 # !X1_cpu_data_master_requests_epcs_controller_epcs_control_port);

--WC1L8 is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|readdata[7]~1346

--operation mode is normal

WC1L8 = AMPP_FUNCTION(CE1_q_a[7], V1L4, S1_ic_fill_line[5], S1_M_alu_result[10]);

--Y1_internal_incoming_ext_ram_bus_data[31] is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|internal_incoming_ext_ram_bus_data[31]

--operation mode is normal

Y1_internal_incoming_ext_ram_bus_data[31]_lut_out = A1L85;

Y1_internal_incoming_ext_ram_bus_data[31] = DFFEAS(Y1_internal_incoming_ext_ram_bus_data[31]_lut_out, QC2__clk0, F1_data_out, , , , , , );

--T1_registered_cpu_data_master_readdata[31] is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|registered_cpu_data_master_readdata[31]

--operation mode is normal

T1_registered_cpu_data_master_readdata[31]_lut_out = T1L272 & !K1L6 & (!CB1L2 # !UB1L9);

T1_registered_cpu_data_master_readdata[31] = DFFEAS(T1_registered_cpu_data_master_readdata[31]_lut_out, QC2__clk0, F1_data_out, , , , , , );

--T1L196 is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[31]~5212

--operation mode is normal

T1L196 = Y1_internal_incoming_ext_ram_bus_data[7] & (!T1_registered_cpu_data_master_readdata[31] & T1L164) # !Y1_internal_incoming_ext_ram_bus_data[7] & (Y1_cpu_data_master_requests_ext_flash_s1 # !T1_registered_cpu_data_master_readdata[31] & T1L164);

--T1L197 is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[31]~5213

--operation mode is normal

T1L197 = !T1L196 & (Y1_internal_incoming_ext_ram_bus_data[31] # !Y1L78 & !Y1_cpu_data_master_requests_ext_ram_s1);

--FE1_q_a[31] is std_1c20:inst|epcs_controller:the_epcs_controller|altsyncram:the_boot_copier_rom|altsyncram_3h31:auto_generated|q_a[31]

--RAM Block Operation Mode: ROM

--Port A Depth: 128, Port A Width: 1

--Port A Logical Depth: 128, Port A Logical Width: 32

--Port A Input: Registered, Port A Output: Un-registered

FE1_q_a[31]_PORT_A_address = BUS(X1L14, X1L15, X1L16, X1L17, X1L18, X1L19, X1L20);

FE1_q_a[31]_PORT_A_address_reg = DFFE(FE1_q_a[31]_PORT_A_address, FE1_q_a[31]_clock_0, , , );

FE1_q_a[31]_clock_0 = QC2__clk0;

FE1_q_a[31]_PORT_A_data_out = MEMORY(, , FE1_q_a[31]_PORT_A_address_reg, , , , , , FE1_q_a[31]_clock_0, , , , , );

FE1_q_a[31] = FE1_q_a[31]_PORT_A_data_out[0];

--W1L16 is std_1c20:inst|epcs_controller:the_epcs_controller|readdata[31]~692

--operation mode is normal

W1L16 = FE1_q_a[31] & (!W1L1);

--T1L198 is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[31]~5214

--operation mode is normal

T1L198 = T1L150 & T1L197 & (W1L16 # !X1_cpu_data_master_requests_epcs_controller_epcs_control_port);

--CE1_q_a[24] is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|cpu_ociram_lpm_dram_bdp_component_module:cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_bp62:auto_generated|q_a[24]

--RAM Block Operation Mode: True Dual-Port

--Port A Depth: 256, Port A Width: 8, Port B Depth: 256, Port B Width: 8

--Port A Logical Depth: 256, Port A Logical Width: 32, Port B Logical Depth: 256, Port B Logical Width: 32

--Port A Input: Registered, Port A Output: Un-registered, Port B Input: Registered, Port B Output: Un-registered

CE1_q_a[24] = AMPP_FUNCTION(RD1L62, RD1_MonWr, QC2__clk0, QC2__clk0, S1_M_st_data[24], S1_M_st_data[25], S1_M_st_data[26], S1_M_st_data[27], S1_M_st_data[28], S1_M_st_data[29], S1_M_st_data[30], S1_M_st_data[31], V1L9, V1L10, V1L11, V1L12, V1L13, V1L14, V1L15, V1L16, V1L30, RD1_internal_MonDReg[24], RD1_internal_MonDReg[25], RD1_internal_MonDReg[26], RD1_internal_MonDReg[27], RD1_internal_MonDReg[28], RD1_internal_MonDReg[29], RD1_internal_MonDReg[30], RD1_internal_MonDReg[31], RD1_MonAReg[2], RD1_MonAReg[3], RD1_MonAReg[4], RD1_MonAReg[5], RD1_MonAReg[6], RD1_MonAReg[7], RD1_MonAReg[8], RD1_MonAReg[9]);

--CE1_q_a[25] is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|cpu_ociram_lpm_dram_bdp_component_module:cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_bp62:auto_generated|q_a[25]

CE1_q_a[25] = AMPP_FUNCTION(RD1L62, RD1_MonWr, QC2__clk0, QC2__clk0, S1_M_st_data[24], S1_M_st_data[25], S1_M_st_data[26], S1_M_st_data[27], S1_M_st_data[28], S1_M_st_data[29], S1_M_st_data[30], S1_M_st_data[31], V1L9, V1L10, V1L11, V1L12, V1L13, V1L14, V1L15, V1L16, V1L30, RD1_internal_MonDReg[24], RD1_internal_MonDReg[25], RD1_internal_MonDReg[26], RD1_internal_MonDReg[27], RD1_internal_MonDReg[28], RD1_internal_MonDReg[29], RD1_internal_MonDReg[30], RD1_internal_MonDReg[31], RD1_MonAReg[2], RD1_MonAReg[3], RD1_MonAReg[4], RD1_MonAReg[5], RD1_MonAReg[6], RD1_MonAReg[7], RD1_MonAReg[8], RD1_MonAReg[9]);

--CE1_q_a[26] is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|cpu_ociram_lpm_dram_bdp_component_module:cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_bp62:auto_generated|q_a[26]

CE1_q_a[26] = AMPP_FUNCTION(RD1L62, RD1_MonWr, QC2__clk0, QC2__clk0, S1_M_st_data[24], S1_M_st_data[25], S1_M_st_data[26], S1_M_st_data[27], S1_M_st_data[28], S1_M_st_data[29], S1_M_st_data[30], S1_M_st_data[31], V1L9, V1L10, V1L11, V1L12, V1L13, V1L14, V1L15, V1L16, V1L30, RD1_internal_MonDReg[24], RD1_internal_MonDReg[25], RD1_internal_MonDReg[26], RD1_internal_MonDReg[27], RD1_internal_MonDReg[28], RD1_internal_MonDReg[29], RD1_internal_MonDReg[30], RD1_internal_MonDReg[31], RD1_MonAReg[2], RD1_MonAReg[3], RD1_MonAReg[4], RD1_MonAReg[5], RD1_MonAReg[6], RD1_MonAReg[7], RD1_MonAReg[8], RD1_MonAReg[9]);

--CE1_q_a[27] is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|cpu_ociram_lpm_dram_bdp_component_module:cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_bp62:auto_generated|q_a[27]

CE1_q_a[27] = AMPP_FUNCTION(RD1L62, RD1_MonWr, QC2__clk0, QC2__clk0, S1_M_st_data[24], S1_M_st_data[25], S1_M_st_data[26], S1_M_st_data[27], S1_M_st_data[28], S1_M_st_data[29], S1_M_st_data[30], S1_M_st_data[31], V1L9, V1L10, V1L11, V1L12, V1L13, V1L14, V1L15, V1L16, V1L30, RD1_internal_MonDReg[24], RD1_internal_MonDReg[25], RD1_internal_MonDReg[26], RD1_internal_MonDReg[27], RD1_internal_MonDReg[28], RD1_internal_MonDReg[29], RD1_internal_MonDReg[30], RD1_internal_MonDReg[31], RD1_MonAReg[2], RD1_MonAReg[3], RD1_MonAReg[4], RD1_MonAReg[5], RD1_MonAReg[6], RD1_MonAReg[7], RD1_MonAReg[8], RD1_MonAReg[9]);

--CE1_q_a[28] is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|cpu_ociram_lpm_dram_bdp_component_module:cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_bp62:auto_generated|q_a[28]

CE1_q_a[28] = AMPP_FUNCTION(RD1L62, RD1_MonWr, QC2__clk0, QC2__clk0, S1_M_st_data[24], S1_M_st_data[25], S1_M_st_data[26], S1_M_st_data[27], S1_M_st_data[28], S1_M_st_data[29], S1_M_st_data[30], S1_M_st_data[31], V1L9, V1L10, V1L11, V1L12, V1L13, V1L14, V1L15, V1L16, V1L30, RD1_internal_MonDReg[24], RD1_internal_MonDReg[25], RD1_internal_MonDReg[26], RD1_internal_MonDReg[27], RD1_internal_MonDReg[28], RD1_internal_MonDReg[29], RD1_internal_MonDReg[30], RD1_internal_MonDReg[31], RD1_MonAReg[2], RD1_MonAReg[3], RD1_MonAReg[4], RD1_MonAReg[5], RD1_MonAReg[6], RD1_MonAReg[7], RD1_MonAReg[8], RD1_MonAReg[9]);

--CE1_q_a[29] is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|cpu_ociram_lpm_dram_bdp_component_module:cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_bp62:auto_generated|q_a[29]

CE1_q_a[29] = AMPP_FUNCTION(RD1L62, RD1_MonWr, QC2__clk0, QC2__clk0, S1_M_st_data[24], S1_M_st_data[25], S1_M_st_data[26], S1_M_st_data[27], S1_M_st_data[28], S1_M_st_data[29], S1_M_st_data[30], S1_M_st_data[31], V1L9, V1L10, V1L11, V1L12, V1L13, V1L14, V1L15, V1L16, V1L30, RD1_internal_MonDReg[24], RD1_internal_MonDReg[25], RD1_internal_MonDReg[26], RD1_internal_MonDReg[27], RD1_internal_MonDReg[28], RD1_internal_MonDReg[29], RD1_internal_MonDReg[30], RD1_internal_MonDReg[31], RD1_MonAReg[2], RD1_MonAReg[3], RD1_MonAReg[4], RD1_MonAReg[5], RD1_MonAReg[6], RD1_MonAReg[7], RD1_MonAReg[8], RD1_MonAReg[9]);

--CE1_q_a[30] is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|cpu_ociram_lpm_dram_bdp_component_module:cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_bp62:auto_generated|q_a[30]

CE1_q_a[30] = AMPP_FUNCTION(RD1L62, RD1_MonWr, QC2__clk0, QC2__clk0, S1_M_st_data[24], S1_M_st_data[25], S1_M_st_data[26], S1_M_st_data[27], S1_M_st_data[28], S1_M_st_data[29], S1_M_st_data[30], S1_M_st_data[31], V1L9, V1L10, V1L11, V1L12, V1L13, V1L14, V1L15, V1L16, V1L30, RD1_internal_MonDReg[24], RD1_internal_MonDReg[25], RD1_internal_MonDReg[26], RD1_internal_MonDReg[27], RD1_internal_MonDReg[28], RD1_internal_MonDReg[29], RD1_internal_MonDReg[30], RD1_internal_MonDReg[31], RD1_MonAReg[2], RD1_MonAReg[3], RD1_MonAReg[4], RD1_MonAReg[5], RD1_MonAReg[6], RD1_MonAReg[7], RD1_MonAReg[8], RD1_MonAReg[9]);

--CE1_q_a[31] is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|cpu_ociram_lpm_dram_bdp_component_module:cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_bp62:auto_generated|q_a[31]

CE1_q_a[31] = AMPP_FUNCTION(RD1L62, RD1_MonWr, QC2__clk0, QC2__clk0, S1_M_st_data[24], S1_M_st_data[25], S1_M_st_data[26], S1_M_st_data[27], S1_M_st_data[28], S1_M_st_data[29], S1_M_st_data[30], S1_M_st_data[31], V1L9, V1L10, V1L11, V1L12, V1L13, V1L14, V1L15, V1L16, V1L30, RD1_internal_MonDReg[24], RD1_internal_MonDReg[25], RD1_internal_MonDReg[26], RD1_internal_MonDReg[27], RD1_internal_MonDReg[28], RD1_internal_MonDReg[29], RD1_internal_MonDReg[30], RD1_internal_MonDReg[31], RD1_MonAReg[2], RD1_MonAReg[3], RD1_MonAReg[4], RD1_MonAReg[5], RD1_MonAReg[6], RD1_MonAReg[7], RD1_MonAReg[8], RD1_MonAReg[9]);

--CE1_q_b[24] is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|cpu_ociram_lpm_dram_bdp_component_module:cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_bp62:auto_generated|q_b[24]

CE1_q_b[24] = AMPP_FUNCTION(RD1L62, RD1_MonWr, QC2__clk0, QC2__clk0, S1_M_st_data[24], S1_M_st_data[25], S1_M_st_data[26], S1_M_st_data[27], S1_M_st_data[28], S1_M_st_data[29], S1_M_st_data[30], S1_M_st_data[31], V1L9, V1L10, V1L11, V1L12, V1L13, V1L14, V1L15, V1L16, V1L30, RD1_internal_MonDReg[24], RD1_internal_MonDReg[25], RD1_internal_MonDReg[26], RD1_internal_MonDReg[27], RD1_internal_MonDReg[28], RD1_internal_MonDReg[29], RD1_internal_MonDReg[30], RD1_internal_MonDReg[31], RD1_MonAReg[2], RD1_MonAReg[3], RD1_MonAReg[4], RD1_MonAReg[5], RD1_MonAReg[6], RD1_MonAReg[7], RD1_MonAReg[8], RD1_MonAReg[9]);

--CE1_q_b[25] is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|cpu_ociram_lpm_dram_bdp_component_module:cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_bp62:auto_generated|q_b[25]

CE1_q_b[25] = AMPP_FUNCTION(RD1L62, RD1_MonWr, QC2__clk0, QC2__clk0, S1_M_st_data[24], S1_M_st_data[25], S1_M_st_data[26], S1_M_st_data[27], S1_M_st_data[28], S1_M_st_data[29], S1_M_st_data[30], S1_M_st_data[31], V1L9, V1L10, V1L11, V1L12, V1L13, V1L14, V1L15, V1L16, V1L30, RD1_internal_MonDReg[24], RD1_internal_MonDReg[25], RD1_internal_MonDReg[26], RD1_internal_MonDReg[27], RD1_internal_MonDReg[28], RD1_internal_MonDReg[29], RD1_internal_MonDReg[30], RD1_internal_MonDReg[31], RD1_MonAReg[2], RD1_MonAReg[3], RD1_MonAReg[4], RD1_MonAReg[5], RD1_MonAReg[6], RD1_MonAReg[7], RD1_MonAReg[8], RD1_MonAReg[9]);

--CE1_q_b[26] is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|cpu_ociram_lpm_dram_bdp_component_module:cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_bp62:auto_generated|q_b[26]

CE1_q_b[26] = AMPP_FUNCTION(RD1L62, RD1_MonWr, QC2__clk0, QC2__clk0, S1_M_st_data[24], S1_M_st_data[25], S1_M_st_data[26], S1_M_st_data[27], S1_M_st_data[28], S1_M_st_data[29], S1_M_st_data[30], S1_M_st_data[31], V1L9, V1L10, V1L11, V1L12, V1L13, V1L14, V1L15, V1L16, V1L30, RD1_internal_MonDReg[24], RD1_internal_MonDReg[25], RD1_internal_MonDReg[26], RD1_internal_MonDReg[27], RD1_internal_MonDReg[28], RD1_internal_MonDReg[29], RD1_internal_MonDReg[30], RD1_internal_MonDReg[31], RD1_MonAReg[2], RD1_MonAReg[3], RD1_MonAReg[4], RD1_MonAReg[5], RD1_MonAReg[6], RD1_MonAReg[7], RD1_MonAReg[8], RD1_MonAReg[9]);

--CE1_q_b[27] is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|cpu_ociram_lpm_dram_bdp_component_module:cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_bp62:auto_generated|q_b[27]

CE1_q_b[27] = AMPP_FUNCTION(RD1L62, RD1_MonWr, QC2__clk0, QC2__clk0, S1_M_st_data[24], S1_M_st_data[25], S1_M_st_data[26], S1_M_st_data[27], S1_M_st_data[28], S1_M_st_data[29], S1_M_st_data[30], S1_M_st_data[31], V1L9, V1L10, V1L11, V1L12, V1L13, V1L14, V1L15, V1L16, V1L30, RD1_internal_MonDReg[24], RD1_internal_MonDReg[25], RD1_internal_MonDReg[26], RD1_internal_MonDReg[27], RD1_internal_MonDReg[28], RD1_internal_MonDReg[29], RD1_internal_MonDReg[30], RD1_internal_MonDReg[31], RD1_MonAReg[2], RD1_MonAReg[3], RD1_MonAReg[4], RD1_MonAReg[5], RD1_MonAReg[6], RD1_MonAReg[7], RD1_MonAReg[8], RD1_MonAReg[9]);

--CE1_q_b[28] is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|cpu_ociram_lpm_dram_bdp_component_module:cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_bp62:auto_generated|q_b[28]

CE1_q_b[28] = AMPP_FUNCTION(RD1L62, RD1_MonWr, QC2__clk0, QC2__clk0, S1_M_st_data[24], S1_M_st_data[25], S1_M_st_data[26], S1_M_st_data[27], S1_M_st_data[28], S1_M_st_data[29], S1_M_st_data[30], S1_M_st_data[31], V1L9, V1L10, V1L11, V1L12, V1L13, V1L14, V1L15, V1L16, V1L30, RD1_internal_MonDReg[24], RD1_internal_MonDReg[25], RD1_internal_MonDReg[26], RD1_internal_MonDReg[27], RD1_internal_MonDReg[28], RD1_internal_MonDReg[29], RD1_internal_MonDReg[30], RD1_internal_MonDReg[31], RD1_MonAReg[2], RD1_MonAReg[3], RD1_MonAReg[4], RD1_MonAReg[5], RD1_MonAReg[6], RD1_MonAReg[7], RD1_MonAReg[8], RD1_MonAReg[9]);

--CE1_q_b[29] is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|cpu_ociram_lpm_dram_bdp_component_module:cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_bp62:auto_generated|q_b[29]

CE1_q_b[29] = AMPP_FUNCTION(RD1L62, RD1_MonWr, QC2__clk0, QC2__clk0, S1_M_st_data[24], S1_M_st_data[25], S1_M_st_data[26], S1_M_st_data[27], S1_M_st_data[28], S1_M_st_data[29], S1_M_st_data[30], S1_M_st_data[31], V1L9, V1L10, V1L11, V1L12, V1L13, V1L14, V1L15, V1L16, V1L30, RD1_internal_MonDReg[24], RD1_internal_MonDReg[25], RD1_internal_MonDReg[26], RD1_internal_MonDReg[27], RD1_internal_MonDReg[28], RD1_internal_MonDReg[29], RD1_internal_MonDReg[30], RD1_internal_MonDReg[31], RD1_MonAReg[2], RD1_MonAReg[3], RD1_MonAReg[4], RD1_MonAReg[5], RD1_MonAReg[6], RD1_MonAReg[7], RD1_MonAReg[8], RD1_MonAReg[9]);

--CE1_q_b[30] is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|cpu_ociram_lpm_dram_bdp_component_module:cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_bp62:auto_generated|q_b[30]

CE1_q_b[30] = AMPP_FUNCTION(RD1L62, RD1_MonWr, QC2__clk0, QC2__clk0, S1_M_st_data[24], S1_M_st_data[25], S1_M_st_data[26], S1_M_st_data[27], S1_M_st_data[28], S1_M_st_data[29], S1_M_st_data[30], S1_M_st_data[31], V1L9, V1L10, V1L11, V1L12, V1L13, V1L14, V1L15, V1L16, V1L30, RD1_internal_MonDReg[24], RD1_internal_MonDReg[25], RD1_internal_MonDReg[26], RD1_internal_MonDReg[27], RD1_internal_MonDReg[28], RD1_internal_MonDReg[29], RD1_internal_MonDReg[30], RD1_internal_MonDReg[31], RD1_MonAReg[2], RD1_MonAReg[3], RD1_MonAReg[4], RD1_MonAReg[5], RD1_MonAReg[6], RD1_MonAReg[7], RD1_MonAReg[8], RD1_MonAReg[9]);

--CE1_q_b[31] is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|cpu_ociram_lpm_dram_bdp_component_module:cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_bp62:auto_generated|q_b[31]

CE1_q_b[31] = AMPP_FUNCTION(RD1L62, RD1_MonWr, QC2__clk0, QC2__clk0, S1_M_st_data[24], S1_M_st_data[25], S1_M_st_data[26], S1_M_st_data[27], S1_M_st_data[28], S1_M_st_data[29], S1_M_st_data[30], S1_M_st_data[31], V1L9, V1L10, V1L11, V1L12, V1L13, V1L14, V1L15, V1L16, V1L30, RD1_internal_MonDReg[24], RD1_internal_MonDReg[25], RD1_internal_MonDReg[26], RD1_internal_MonDReg[27], RD1_internal_MonDReg[28], RD1_internal_MonDReg[29], RD1_internal_MonDReg[30], RD1_internal_MonDReg[31], RD1_MonAReg[2], RD1_MonAReg[3], RD1_MonAReg[4], RD1_MonAReg[5], RD1_MonAReg[6], RD1_MonAReg[7], RD1_MonAReg[8], RD1_MonAReg[9]);

--WC1L33 is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|readdata[31]~1347

--operation mode is normal

WC1L33 = AMPP_FUNCTION(CE1_q_a[31], V1L4, S1_ic_fill_line[5], S1_M_alu_result[10]);

--DD1_q_b[22] is std_1c20:inst|cpu:the_cpu|cpu_register_bank_b_module:cpu_register_bank_b|altsyncram:the_altsyncram|altsyncram_4vd1:auto_generated|q_b[22]

--RAM Block Operation Mode: Simple Dual-Port

--Port A Depth: 32, Port A Width: 1, Port B Depth: 32, Port B Width: 1

--Port A Logical Depth: 32, Port A Logical Width: 32, Port B Logical Depth: 32, Port B Logical Width: 32

--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered

DD1_q_b[22] = AMPP_FUNCTION(GND, GND, QC2__clk0, QC2__clk0, !S1_M_wr_dst_reg, S1_W_stall, S1L1348, S1_M_dst_regnum[0], S1_M_dst_regnum[1], S1_M_dst_regnum[2], S1_M_dst_regnum[3], S1_M_dst_regnum[4], AD1_q_b[22], AD1_q_b[23], AD1_q_b[24], AD1_q_b[25], AD1_q_b[26]);

--S1L910 is std_1c20:inst|cpu:the_cpu|F_pc_plus_one[19]~54

--operation mode is arithmetic

S1L910 = AMPP_FUNCTION(S1_F_pc[19], S1L909);

--S1L911 is std_1c20:inst|cpu:the_cpu|F_pc_plus_one[19]~55

--operation mode is arithmetic

S1L911 = AMPP_FUNCTION(S1_F_pc[19], S1L909);

--Y1_internal_incoming_ext_ram_bus_data[21] is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|internal_incoming_ext_ram_bus_data[21]

--operation mode is normal

Y1_internal_incoming_ext_ram_bus_data[21]_lut_out = A1L95;

Y1_internal_incoming_ext_ram_bus_data[21] = DFFEAS(Y1_internal_incoming_ext_ram_bus_data[21]_lut_out, QC2__clk0, F1_data_out, , , , , , );

--T1_dbs_8_reg_segment_2[5] is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|dbs_8_reg_segment_2[5]

--operation mode is normal

T1_dbs_8_reg_segment_2[5]_lut_out = Y1_internal_incoming_ext_ram_bus_data[5];

T1_dbs_8_reg_segment_2[5] = DFFEAS(T1_dbs_8_reg_segment_2[5]_lut_out, QC2__clk0, F1_data_out, , T1L296, , , , );

--T1_registered_cpu_data_master_readdata[21] is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|registered_cpu_data_master_readdata[21]

--operation mode is normal

T1_registered_cpu_data_master_readdata[21]_lut_out = T1L262 & !K1L6 & (BB1L28 # !CB1_cpu_data_master_requests_jtag_uart_avalon_jtag_slave);

T1_registered_cpu_data_master_readdata[21] = DFFEAS(T1_registered_cpu_data_master_readdata[21]_lut_out, QC2__clk0, F1_data_out, , , , , , );

--T1L161 is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[21]~5215

--operation mode is normal

T1L161 = T1_dbs_8_reg_segment_2[5] & (!T1_registered_cpu_data_master_readdata[21] & T1L151) # !T1_dbs_8_reg_segment_2[5] & (Y1_cpu_data_master_requests_ext_flash_s1 # !T1_registered_cpu_data_master_readdata[21] & T1L151);

--T1L162 is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[21]~5216

--operation mode is normal

T1L162 = !T1L161 & (Y1_internal_incoming_ext_ram_bus_data[21] # !Y1L78 & !Y1_cpu_data_master_requests_ext_ram_s1);

--FE1_q_a[21] is std_1c20:inst|epcs_controller:the_epcs_controller|altsyncram:the_boot_copier_rom|altsyncram_3h31:auto_generated|q_a[21]

--RAM Block Operation Mode: ROM

--Port A Depth: 128, Port A Width: 1

--Port A Logical Depth: 128, Port A Logical Width: 32

--Port A Input: Registered, Port A Output: Un-registered

FE1_q_a[21]_PORT_A_address = BUS(X1L14, X1L15, X1L16, X1L17, X1L18, X1L19, X1L20);

FE1_q_a[21]_PORT_A_address_reg = DFFE(FE1_q_a[21]_PORT_A_address, FE1_q_a[21]_clock_0, , , );

FE1_q_a[21]_clock_0 = QC2__clk0;

FE1_q_a[21]_PORT_A_data_out = MEMORY(, , FE1_q_a[21]_PORT_A_address_reg, , , , , , FE1_q_a[21]_clock_0, , , , , );

FE1_q_a[21] = FE1_q_a[21]_PORT_A_data_out[0];

--W1L7 is std_1c20:inst|epcs_controller:the_epcs_controller|readdata[21]~693

--operation mode is normal

W1L7 = FE1_q_a[21] & (!W1L1);

--T1L163 is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[21]~5217

--operation mode is normal

T1L163 = T1L168 & T1L162 & (W1L7 # !X1_cpu_data_master_requests_epcs_controller_epcs_control_port);

--WC1L23 is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|readdata[21]~1348

--operation mode is normal

WC1L23 = AMPP_FUNCTION(CE1_q_a[21], V1L4, S1_ic_fill_line[5], S1_M_alu_result[10]);

--DD1_q_b[21] is std_1c20:inst|cpu:the_cpu|cpu_register_bank_b_module:cpu_register_bank_b|altsyncram:the_altsyncram|altsyncram_4vd1:auto_generated|q_b[21]

--RAM Block Operation Mode: Simple Dual-Port

--Port A Depth: 32, Port A Width: 1, Port B Depth: 32, Port B Width: 1

--Port A Logical Depth: 32, Port A Logical Width: 32, Port B Logical Depth: 32, Port B Logical Width: 32

--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered

DD1_q_b[21] = AMPP_FUNCTION(GND, GND, QC2__clk0, QC2__clk0, !S1_M_wr_dst_reg, S1_W_stall, S1L1345, S1_M_dst_regnum[0], S1_M_dst_regnum[1], S1_M_dst_regnum[2], S1_M_dst_regnum[3], S1_M_dst_regnum[4], AD1_q_b[22], AD1_q_b[23], AD1_q_b[24], AD1_q_b[25], AD1_q_b[26]);

--S1L906 is std_1c20:inst|cpu:the_cpu|F_pc_plus_one[17]~56

--operation mode is arithmetic

S1L906 = AMPP_FUNCTION(S1_F_pc[17], S1L905);

--S1L907 is std_1c20:inst|cpu:the_cpu|F_pc_plus_one[17]~57

--operation mode is arithmetic

S1L907 = AMPP_FUNCTION(S1_F_pc[17], S1L905);

--DD1_q_b[19] is std_1c20:inst|cpu:the_cpu|cpu_register_bank_b_module:cpu_register_bank_b|altsyncram:the_altsyncram|altsyncram_4vd1:auto_generated|q_b[19]

--RAM Block Operation Mode: Simple Dual-Port

--Port A Depth: 32, Port A Width: 1, Port B Depth: 32, Port B Width: 1

--Port A Logical Depth: 32, Port A Logical Width: 32, Port B Logical Depth: 32, Port B Logical Width: 32

--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered

DD1_q_b[19] = AMPP_FUNCTION(GND, GND, QC2__clk0, QC2__clk0, !S1_M_wr_dst_reg, S1_W_stall, S1L1339, S1_M_dst_regnum[0], S1_M_dst_regnum[1], S1_M_dst_regnum[2], S1_M_dst_regnum[3], S1_M_dst_regnum[4], AD1_q_b[22], AD1_q_b[23], AD1_q_b[24], AD1_q_b[25], AD1_q_b[26]);

--S1L904 is std_1c20:inst|cpu:the_cpu|F_pc_plus_one[16]~58

--operation mode is arithmetic

S1L904 = AMPP_FUNCTION(S1_F_pc[16], S1L903);

--S1L905 is std_1c20:inst|cpu:the_cpu|F_pc_plus_one[16]~59

--operation mode is arithmetic

S1L905 = AMPP_FUNCTION(S1_F_pc[16], S1L903);

--DD1_q_b[18] is std_1c20:inst|cpu:the_cpu|cpu_register_bank_b_module:cpu_register_bank_b|altsyncram:the_altsyncram|altsyncram_4vd1:auto_generated|q_b[18]

--RAM Block Operation Mode: Simple Dual-Port

--Port A Depth: 32, Port A Width: 1, Port B Depth: 32, Port B Width: 1

--Port A Logical Depth: 32, Port A Logical Width: 32, Port B Logical Depth: 32, Port B Logical Width: 32

--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered

DD1_q_b[18] = AMPP_FUNCTION(GND, GND, QC2__clk0, QC2__clk0, !S1_M_wr_dst_reg, S1_W_stall, S1L1336, S1_M_dst_regnum[0], S1_M_dst_regnum[1], S1_M_dst_regnum[2], S1_M_dst_regnum[3], S1_M_dst_regnum[4], AD1_q_b[22], AD1_q_b[23], AD1_q_b[24], AD1_q_b[25], AD1_q_b[26]);

--S1L916 is std_1c20:inst|cpu:the_cpu|F_pc_plus_one[22]~60

--operation mode is arithmetic

S1L916 = AMPP_FUNCTION(S1_F_pc[22], S1L915);

--S1L917 is std_1c20:inst|cpu:the_cpu|F_pc_plus_one[22]~61

--operation mode is arithmetic

S1L917 = AMPP_FUNCTION(S1_F_pc[22], S1L915);

--AD1_q_b[22] is std_1c20:inst|cpu:the_cpu|cpu_ic_data_module:cpu_ic_data|altsyncram:the_altsyncram|altsyncram_qmb1:auto_generated|q_b[22]

--RAM Block Operation Mode: Simple Dual-Port

--Port A Depth: 1024, Port A Width: 1, Port B Depth: 1024, Port B Width: 1

--Port A Logical Depth: 1024, Port A Logical Width: 32, Port B Logical Depth: 1024, Port B Logical Width: 32

--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered

AD1_q_b[22] = AMPP_FUNCTION(GND, GND, QC2__clk0, QC2__clk0, S1_i_readdatavalid_d1, S1_W_stall, S1_i_readdata_d1[22], S1_ic_fill_dp_offset[0], S1_ic_fill_dp_offset[1], S1_ic_fill_dp_offset[2], S1_ic_fill_line[0], S1_ic_fill_line[1], S1_ic_fill_line[2], S1_ic_fill_line[3], S1_ic_fill_line[4], S1_ic_fill_line[5], S1_ic_fill_line[6], S1L789, S1L792, S1L795, S1L821, S1L824, S1L827, S1L830, S1L833, S1L836, S1L839);

--AD1_q_b[23] is std_1c20:inst|cpu:the_cpu|cpu_ic_data_module:cpu_ic_data|altsyncram:the_altsyncram|altsyncram_qmb1:auto_generated|q_b[23]

--RAM Block Operation Mode: Simple Dual-Port

--Port A Depth: 1024, Port A Width: 1, Port B Depth: 1024, Port B Width: 1

--Port A Logical Depth: 1024, Port A Logical Width: 32, Port B Logical Depth: 1024, Port B Logical Width: 32

--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered

AD1_q_b[23] = AMPP_FUNCTION(GND, GND, QC2__clk0, QC2__clk0, S1_i_readdatavalid_d1, S1_W_stall, S1_i_readdata_d1[23], S1_ic_fill_dp_offset[0], S1_ic_fill_dp_offset[1], S1_ic_fill_dp_offset[2], S1_ic_fill_line[0], S1_ic_fill_line[1], S1_ic_fill_line[2], S1_ic_fill_line[3], S1_ic_fill_line[4], S1_ic_fill_line[5], S1_ic_fill_line[6], S1L789, S1L792, S1L795, S1L821, S1L824, S1L827, S1L830, S1L833, S1L836, S1L839);

--AD1_q_b[24] is std_1c20:inst|cpu:the_cpu|cpu_ic_data_module:cpu_ic_data|altsyncram:the_altsyncram|altsyncram_qmb1:auto_generated|q_b[24]

--RAM Block Operation Mode: Simple Dual-Port

--Port A Depth: 1024, Port A Width: 1, Port B Depth: 1024, Port B Width: 1

--Port A Logical Depth: 1024, Port A Logical Width: 32, Port B Logical Depth: 1024, Port B Logical Width: 32

--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered

AD1_q_b[24] = AMPP_FUNCTION(GND, GND, QC2__clk0, QC2__clk0, S1_i_readdatavalid_d1, S1_W_stall, S1_i_readdata_d1[24], S1_ic_fill_dp_offset[0], S1_ic_fill_dp_offset[1], S1_ic_fill_dp_offset[2], S1_ic_fill_line[0], S1_ic_fill_line[1], S1_ic_fill_line[2], S1_ic_fill_line[3], S1_ic_fill_line[4], S1_ic_fill_line[5], S1_ic_fill_line[6], S1L789, S1L792, S1L795, S1L821, S1L824, S1L827, S1L830, S1L833, S1L836, S1L839);

--AD1_q_b[25] is std_1c20:inst|cpu:the_cpu|cpu_ic_data_module:cpu_ic_data|altsyncram:the_altsyncram|altsyncram_qmb1:auto_generated|q_b[25]

--RAM Block Operation Mode: Simple Dual-Port

--Port A Depth: 1024, Port A Width: 1, Port B Depth: 1024, Port B Width: 1

--Port A Logical Depth: 1024, Port A Logical Width: 32, Port B Logical Depth: 1024, Port B Logical Width: 32

--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered

AD1_q_b[25] = AMPP_FUNCTION(GND, GND, QC2__clk0, QC2__clk0, S1_i_readdatavalid_d1, S1_W_stall, S1_i_readdata_d1[25], S1_ic_fill_dp_offset[0], S1_ic_fill_dp_offset[1], S1_ic_fill_dp_offset[2], S1_ic_fill_line[0], S1_ic_fill_line[1], S1_ic_fill_line[2], S1_ic_fill_line[3], S1_ic_fill_line[4], S1_ic_fill_line[5], S1_ic_fill_line[6], S1L789, S1L792, S1L795, S1L821, S1L824, S1L827, S1L830, S1L833, S1L836, S1L839);

--AD1_q_b[26] is std_1c20:inst|cpu:the_cpu|cpu_ic_data_module:cpu_ic_data|altsyncram:the_altsyncram|altsyncram_qmb1:auto_generated|q_b[26]

--RAM Block Operation Mode: Simple Dual-Port

--Port A Depth: 1024, Port A Width: 1, Port B Depth: 1024, Port B Width: 1

--Port A Logical Depth: 1024, Port A Logical Width: 32, Port B Logical Depth: 1024, Port B Logical Width: 32

--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered

AD1_q_b[26] = AMPP_FUNCTION(GND, GND, QC2__clk0, QC2__clk0, S1_i_readdatavalid_d1, S1_W_stall, S1_i_readdata_d1[26], S1_ic_fill_dp_offset[0], S1_ic_fill_dp_offset[1], S1_ic_fill_dp_offset[2], S1_ic_fill_line[0], S1_ic_fill_line[1], S1_ic_fill_line[2], S1_ic_fill_line[3], S1_ic_fill_line[4], S1_ic_fill_line[5], S1_ic_fill_line[6], S1L789, S1L792, S1L795, S1L821, S1L824, S1L827, S1L830, S1L833, S1L836, S1L839);

--Y1_internal_incoming_ext_ram_bus_data[24] is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|internal_incoming_ext_ram_bus_data[24]

--operation mode is normal

Y1_internal_incoming_ext_ram_bus_data[24]_lut_out = A1L92;

Y1_internal_incoming_ext_ram_bus_data[24] = DFFEAS(Y1_internal_incoming_ext_ram_bus_data[24]_lut_out, QC2__clk0, F1_data_out, , , , , , );

--Y1_internal_incoming_ext_ram_bus_data[0] is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|internal_incoming_ext_ram_bus_data[0]

--operation mode is normal

Y1_internal_incoming_ext_ram_bus_data[0]_lut_out = A1L116;

Y1_internal_incoming_ext_ram_bus_data[0] = DFFEAS(Y1_internal_incoming_ext_ram_bus_data[0]_lut_out, QC2__clk0, F1_data_out, , , , , , );

--T1_registered_cpu_data_master_readdata[24] is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|registered_cpu_data_master_readdata[24]

--operation mode is normal

T1_registered_cpu_data_master_readdata[24]_lut_out = T1L265 & !K1L6 & (!CB1L2 # !UB1L9);

T1_registered_cpu_data_master_readdata[24] = DFFEAS(T1_registered_cpu_data_master_readdata[24]_lut_out, QC2__clk0, F1_data_out, , , , , , );

--T1L172 is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[24]~5218

--operation mode is normal

T1L172 = Y1_internal_incoming_ext_ram_bus_data[0] & (!T1_registered_cpu_data_master_readdata[24] & T1L164) # !Y1_internal_incoming_ext_ram_bus_data[0] & (Y1_cpu_data_master_requests_ext_flash_s1 # !T1_registered_cpu_data_master_readdata[24] & T1L164);

--T1L173 is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[24]~5219

--operation mode is normal

T1L173 = !T1L172 & (Y1_internal_incoming_ext_ram_bus_data[24] # !Y1L78 & !Y1_cpu_data_master_requests_ext_ram_s1);

--FE1_q_a[24] is std_1c20:inst|epcs_controller:the_epcs_controller|altsyncram:the_boot_copier_rom|altsyncram_3h31:auto_generated|q_a[24]

--RAM Block Operation Mode: ROM

--Port A Depth: 128, Port A Width: 1

--Port A Logical Depth: 128, Port A Logical Width: 32

--Port A Input: Registered, Port A Output: Un-registered

FE1_q_a[24]_PORT_A_address = BUS(X1L14, X1L15, X1L16, X1L17, X1L18, X1L19, X1L20);

FE1_q_a[24]_PORT_A_address_reg = DFFE(FE1_q_a[24]_PORT_A_address, FE1_q_a[24]_clock_0, , , );

FE1_q_a[24]_clock_0 = QC2__clk0;

FE1_q_a[24]_PORT_A_data_out = MEMORY(, , FE1_q_a[24]_PORT_A_address_reg, , , , , , FE1_q_a[24]_clock_0, , , , , );

FE1_q_a[24] = FE1_q_a[24]_PORT_A_data_out[0];

--W1L10 is std_1c20:inst|epcs_controller:the_epcs_controller|readdata[24]~694

--operation mode is normal

W1L10 = FE1_q_a[24] & (!W1L1);

--T1L174 is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[24]~5220

--operation mode is normal

T1L174 = T1L150 & T1L173 & (W1L10 # !X1_cpu_data_master_requests_epcs_controller_epcs_control_port);

--WC1L26 is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|readdata[24]~1349

--operation mode is normal

WC1L26 = AMPP_FUNCTION(CE1_q_a[24], V1L4, S1_ic_fill_line[5], S1_M_alu_result[10]);

--S1L900 is std_1c20:inst|cpu:the_cpu|F_pc_plus_one[14]~62

--operation mode is arithmetic

S1L900 = AMPP_FUNCTION(S1_F_pc[14], S1L899);

--S1L901 is std_1c20:inst|cpu:the_cpu|F_pc_plus_one[14]~63

--operation mode is arithmetic

S1L901 = AMPP_FUNCTION(S1_F_pc[14], S1L899);

--Y1_internal_incoming_ext_ram_bus_data[16] is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|internal_incoming_ext_ram_bus_data[16]

--operation mode is normal

Y1_internal_incoming_ext_ram_bus_data[16]_lut_out = A1L100;

Y1_internal_incoming_ext_ram_bus_data[16] = DFFEAS(Y1_internal_incoming_ext_ram_bus_data[16]_lut_out, QC2__clk0, F1_data_out, , , , , , );

--T1_dbs_8_reg_segment_2[0] is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|dbs_8_reg_segment_2[0]

--operation mode is normal

T1_dbs_8_reg_segment_2[0]_lut_out = Y1_internal_incoming_ext_ram_bus_data[0];

T1_dbs_8_reg_segment_2[0] = DFFEAS(T1_dbs_8_reg_segment_2[0]_lut_out, QC2__clk0, F1_data_out, , T1L296, , , , );

--T1_registered_cpu_data_master_readdata[16] is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|registered_cpu_data_master_readdata[16]

--operation mode is normal

T1_registered_cpu_data_master_readdata[16]_lut_out = BB1L30 & !K1L6 & (KB1_za_data[16] # !NB1L17);

T1_registered_cpu_data_master_readdata[16] = DFFEAS(T1_registered_cpu_data_master_readdata[16]_lut_out, QC2__clk0, F1_data_out, , , , , , );

--T1L144 is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[16]~5221

--operation mode is normal

T1L144 = T1_dbs_8_reg_segment_2[0] & (!T1_registered_cpu_data_master_readdata[16] & T1L164) # !T1_dbs_8_reg_segment_2[0] & (Y1_cpu_data_master_requests_ext_flash_s1 # !T1_registered_cpu_data_master_readdata[16] & T1L164);

--T1L145 is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[16]~5222

--operation mode is normal

T1L145 = !T1L144 & (Y1_internal_incoming_ext_ram_bus_data[16] # !Y1L78 & !Y1_cpu_data_master_requests_ext_ram_s1);

--FE1_q_a[16] is std_1c20:inst|epcs_controller:the_epcs_controller|altsyncram:the_boot_copier_rom|altsyncram_3h31:auto_generated|q_a[16]

--RAM Block Operation Mode: ROM

--Port A Depth: 128, Port A Width: 1

--Port A Logical Depth: 128, Port A Logical Width: 32

--Port A Input: Registered, Port A Output: Un-registered

FE1_q_a[16]_PORT_A_address = BUS(X1L14, X1L15, X1L16, X1L17, X1L18, X1L19, X1L20);

FE1_q_a[16]_PORT_A_address_reg = DFFE(FE1_q_a[16]_PORT_A_address, FE1_q_a[16]_clock_0, , , );

FE1_q_a[16]_clock_0 = QC2__clk0;

FE1_q_a[16]_PORT_A_data_out = MEMORY(, , FE1_q_a[16]_PORT_A_address_reg, , , , , , FE1_q_a[16]_clock_0, , , , , );

FE1_q_a[16] = FE1_q_a[16]_PORT_A_data_out[0];

--W1L2 is std_1c20:inst|epcs_controller:the_epcs_controller|readdata[16]~695

--operation mode is normal

W1L2 = FE1_q_a[16] & (!W1L1);

--T1L146 is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[16]~5223

--operation mode is normal

T1L146 = T1L168 & T1L145 & (W1L2 # !X1_cpu_data_master_requests_epcs_controller_epcs_control_port);

--WC1L17 is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|readdata[16]~1350

--operation mode is normal

WC1L17 = AMPP_FUNCTION(CE1_q_a[16], V1L4, S1_ic_fill_line[5], S1_M_alu_result[10]);

--DD1_q_b[16] is std_1c20:inst|cpu:the_cpu|cpu_register_bank_b_module:cpu_register_bank_b|altsyncram:the_altsyncram|altsyncram_4vd1:auto_generated|q_b[16]

--RAM Block Operation Mode: Simple Dual-Port

--Port A Depth: 32, Port A Width: 1, Port B Depth: 32, Port B Width: 1

--Port A Logical Depth: 32, Port A Logical Width: 32, Port B Logical Depth: 32, Port B Logical Width: 32

--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered

DD1_q_b[16] = AMPP_FUNCTION(GND, GND, QC2__clk0, QC2__clk0, !S1_M_wr_dst_reg, S1_W_stall, S1L1330, S1_M_dst_regnum[0], S1_M_dst_regnum[1], S1_M_dst_regnum[2], S1_M_dst_regnum[3], S1_M_dst_regnum[4], AD1_q_b[22], AD1_q_b[23], AD1_q_b[24], AD1_q_b[25], AD1_q_b[26]);

--S1L898 is std_1c20:inst|cpu:the_cpu|F_pc_plus_one[13]~64

--operation mode is arithmetic

S1L898 = AMPP_FUNCTION(S1_F_pc[13], S1L897);

--S1L899 is std_1c20:inst|cpu:the_cpu|F_pc_plus_one[13]~65

--operation mode is arithmetic

S1L899 = AMPP_FUNCTION(S1_F_pc[13], S1L897);

--S1L896 is std_1c20:inst|cpu:the_cpu|F_pc_plus_one[12]~66

--operation mode is arithmetic

S1L896 = AMPP_FUNCTION(S1_F_pc[12], S1L895);

--S1L897 is std_1c20:inst|cpu:the_cpu|F_pc_plus_one[12]~67

--operation mode is arithmetic

S1L897 = AMPP_FUNCTION(S1_F_pc[12], S1L895);

--AD1_q_b[20] is std_1c20:inst|cpu:the_cpu|cpu_ic_data_module:cpu_ic_data|altsyncram:the_altsyncram|altsyncram_qmb1:auto_generated|q_b[20]

--RAM Block Operation Mode: Simple Dual-Port

--Port A Depth: 1024, Port A Width: 1, Port B Depth: 1024, Port B Width: 1

--Port A Logical Depth: 1024, Port A Logical Width: 32, Port B Logical Depth: 1024, Port B Logical Width: 32

--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered

AD1_q_b[20] = AMPP_FUNCTION(GND, GND, QC2__clk0, QC2__clk0, S1_i_readdatavalid_d1, S1_W_stall, S1_i_readdata_d1[20], S1_ic_fill_dp_offset[0], S1_ic_fill_dp_offset[1], S1_ic_fill_dp_offset[2], S1_ic_fill_line[0], S1_ic_fill_line[1], S1_ic_fill_line[2], S1_ic_fill_line[3], S1_ic_fill_line[4], S1_ic_fill_line[5], S1_ic_fill_line[6], S1L789, S1L792, S1L795, S1L821, S1L824, S1L827, S1L830, S1L833, S1L836, S1L839);

--T1L120 is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[12]~5224

--operation mode is normal

T1L120 = T1L100 & (!WB1_cpu_data_master_granted_uart1_s1 & !UB1_cpu_data_master_granted_sysid_control_slave);

--T1_registered_cpu_data_master_readdata[14] is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|registered_cpu_data_master_readdata[14]

--operation mode is normal

T1_registered_cpu_data_master_readdata[14]_lut_out = T1L257 & T1L285 & (KB1_za_data[14] # !NB1L17);

T1_registered_cpu_data_master_readdata[14] = DFFEAS(T1_registered_cpu_data_master_readdata[14]_lut_out, QC2__clk0, F1_data_out, , , , , , );

--T1L133 is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[14]~5225

--operation mode is normal

T1L133 = T1_registered_cpu_data_master_readdata[14] # !K1_cpu_data_master_requests_clock_0_in & (!CB1L2 # !UB1L9);

--T1_dbs_8_reg_segment_1[6] is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|dbs_8_reg_segment_1[6]

--operation mode is normal

T1_dbs_8_reg_segment_1[6]_lut_out = Y1_internal_incoming_ext_ram_bus_data[6];

T1_dbs_8_reg_segment_1[6] = DFFEAS(T1_dbs_8_reg_segment_1[6]_lut_out, QC2__clk0, F1_data_out, , T1L295, , , , );

--T1L205 is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata~338

--operation mode is normal

T1L205 = T1_dbs_8_reg_segment_1[6] # !Y1_cpu_data_master_requests_ext_flash_s1;

--Y1_internal_incoming_ext_ram_bus_data[14] is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|internal_incoming_ext_ram_bus_data[14]

--operation mode is normal

Y1_internal_incoming_ext_ram_bus_data[14]_lut_out = A1L102;

Y1_internal_incoming_ext_ram_bus_data[14] = DFFEAS(Y1_internal_incoming_ext_ram_bus_data[14]_lut_out, QC2__clk0, F1_data_out, , , , , , );

--T1L134 is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[14]~5226

--operation mode is normal

T1L134 = T1L205 & (Y1_internal_incoming_ext_ram_bus_data[14] # !Y1L78 & !Y1_cpu_data_master_requests_ext_ram_s1);

--T1L135 is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[14]~5227

--operation mode is normal

T1L135 = T1L134 & (T1_registered_cpu_data_master_readdata[14] # !NB1L17 & !N1_cpu_data_master_requests_clock_1_in);

--RB1_readdata[14] is std_1c20:inst|sys_clk_timer:the_sys_clk_timer|readdata[14]

--operation mode is normal

RB1_readdata[14]_lut_out = S1_M_alu_result[3] & !S1_M_alu_result[4] & (RB1L188 $ !RB1L189) # !S1_M_alu_result[3] & S1_M_alu_result[4] & RB1L188;

RB1_readdata[14] = DFFEAS(RB1_readdata[14]_lut_out, QC2__clk0, F1_data_out, , , , , , );

--T1L136 is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[14]~5228

--operation mode is normal

T1L136 = T1L133 & T1L135 & (RB1_readdata[14] # !SB1_cpu_data_master_requests_sys_clk_timer_s1);

--Z1_readdata[14] is std_1c20:inst|high_res_timer:the_high_res_timer|readdata[14]

--operation mode is normal

Z1_readdata[14]_lut_out = S1_M_alu_result[3] & !S1_M_alu_result[4] & (Z1L187 $ !Z1L188) # !S1_M_alu_result[3] & S1_M_alu_result[4] & Z1L187;

Z1_readdata[14] = DFFEAS(Z1_readdata[14]_lut_out, QC2__clk0, F1_data_out, , , , , , );

--T1L137 is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[14]~5229

--operation mode is normal

T1L137 = T1L120 & T1L136 & (Z1_readdata[14] # !AB1_cpu_data_master_requests_high_res_timer_s1);

--DE1_data_to_cpu[14] is std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|data_to_cpu[14]

--operation mode is normal

DE1_data_to_cpu[14]_lut_out = DE1L114 & DE1_endofpacketvalue_reg[14] # !DE1L114 & (DE1L113 & DE1_epcs_slave_select_reg[14]);

DE1_data_to_cpu[14] = DFFEAS(DE1_data_to_cpu[14]_lut_out, QC2__clk0, F1_data_out, , , , , , );

--FE1_q_a[14] is std_1c20:inst|epcs_controller:the_epcs_controller|altsyncram:the_boot_copier_rom|altsyncram_3h31:auto_generated|q_a[14]

--RAM Block Operation Mode: ROM

--Port A Depth: 128, Port A Width: 1

--Port A Logical Depth: 128, Port A Logical Width: 32

--Port A Input: Registered, Port A Output: Un-registered

FE1_q_a[14]_PORT_A_address = BUS(X1L14, X1L15, X1L16, X1L17, X1L18, X1L19, X1L20);

FE1_q_a[14]_PORT_A_address_reg = DFFE(FE1_q_a[14]_PORT_A_address, FE1_q_a[14]_clock_0, , , );

FE1_q_a[14]_clock_0 = QC2__clk0;

FE1_q_a[14]_PORT_A_data_out = MEMORY(, , FE1_q_a[14]_PORT_A_address_reg, , , , , , FE1_q_a[14]_clock_0, , , , , );

FE1_q_a[14] = FE1_q_a[14]_PORT_A_data_out[0];

--U1L115 is std_1c20:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_readdata~2400

--operation mode is normal

U1L115 = W1L1 & DE1_data_to_cpu[14] # !W1L1 & (FE1_q_a[14]);

--T1L138 is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[14]~5230

--operation mode is normal

T1L138 = T1L137 & (U1L115 # !X1_cpu_data_master_requests_epcs_controller_epcs_control_port);

--WC1L15 is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|readdata[14]~1351

--operation mode is normal

WC1L15 = AMPP_FUNCTION(CE1_q_a[14], V1L4, S1_ic_fill_line[5], S1_M_alu_result[10]);

--T1_registered_cpu_data_master_readdata[30] is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|registered_cpu_data_master_readdata[30]

--operation mode is normal

T1_registered_cpu_data_master_readdata[30]_lut_out = T1L271 & !K1L6 & (!CB1L2 # !UB1L9);

T1_registered_cpu_data_master_readdata[30] = DFFEAS(T1_registered_cpu_data_master_readdata[30]_lut_out, QC2__clk0, F1_data_out, , , , , , );

--T1L191 is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[30]~5231

--operation mode is normal

T1L191 = T1_registered_cpu_data_master_readdata[30] # !K1_cpu_data_master_requests_clock_0_in & (!CB1L2 # !UB1L9);

--Y1_internal_incoming_ext_ram_bus_data[6] is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|internal_incoming_ext_ram_bus_data[6]

--operation mode is normal

Y1_internal_incoming_ext_ram_bus_data[6]_lut_out = A1L110;

Y1_internal_incoming_ext_ram_bus_data[6] = DFFEAS(Y1_internal_incoming_ext_ram_bus_data[6]_lut_out, QC2__clk0, F1_data_out, , , , , , );

--T1L206 is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata~354

--operation mode is normal

T1L206 = Y1_internal_incoming_ext_ram_bus_data[6] # !Y1_cpu_data_master_requests_ext_flash_s1;

--Y1_internal_incoming_ext_ram_bus_data[30] is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|internal_incoming_ext_ram_bus_data[30]

--operation mode is normal

Y1_internal_incoming_ext_ram_bus_data[30]_lut_out = A1L86;

Y1_internal_incoming_ext_ram_bus_data[30] = DFFEAS(Y1_internal_incoming_ext_ram_bus_data[30]_lut_out, QC2__clk0, F1_data_out, , , , , , );

--T1L192 is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[30]~5232

--operation mode is normal

T1L192 = T1L206 & (Y1_internal_incoming_ext_ram_bus_data[30] # !Y1L78 & !Y1_cpu_data_master_requests_ext_ram_s1);

--T1L193 is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[30]~5233

--operation mode is normal

T1L193 = T1L192 & (T1_registered_cpu_data_master_readdata[30] # !NB1L17 & !N1_cpu_data_master_requests_clock_1_in);

--T1L194 is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[30]~5234

--operation mode is normal

T1L194 = T1L112 & T1L143 & T1L191 & T1L193;

--FE1_q_a[30] is std_1c20:inst|epcs_controller:the_epcs_controller|altsyncram:the_boot_copier_rom|altsyncram_3h31:auto_generated|q_a[30]

--RAM Block Operation Mode: ROM

--Port A Depth: 128, Port A Width: 1

--Port A Logical Depth: 128, Port A Logical Width: 32

--Port A Input: Registered, Port A Output: Un-registered

FE1_q_a[30]_PORT_A_address = BUS(X1L14, X1L15, X1L16, X1L17, X1L18, X1L19, X1L20);

FE1_q_a[30]_PORT_A_address_reg = DFFE(FE1_q_a[30]_PORT_A_address, FE1_q_a[30]_clock_0, , , );

FE1_q_a[30]_clock_0 = QC2__clk0;

FE1_q_a[30]_PORT_A_data_out = MEMORY(, , FE1_q_a[30]_PORT_A_address_reg, , , , , , FE1_q_a[30]_clock_0, , , , , );

FE1_q_a[30] = FE1_q_a[30]_PORT_A_data_out[0];

--T1L195 is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[30]~5235

--operation mode is normal

T1L195 = T1L194 & (FE1_q_a[30] & !W1L1 # !X1_cpu_data_master_requests_epcs_controller_epcs_control_port);

--WC1L32 is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|readdata[30]~1352

--operation mode is normal

WC1L32 = AMPP_FUNCTION(CE1_q_a[30], V1L4, S1_ic_fill_line[5], S1_M_alu_result[10]);

--S1L894 is std_1c20:inst|cpu:the_cpu|F_pc_plus_one[11]~68

--operation mode is arithmetic

S1L894 = AMPP_FUNCTION(S1_F_pc[11], S1L893);

--S1L895 is std_1c20:inst|cpu:the_cpu|F_pc_plus_one[11]~69

--operation mode is arithmetic

S1L895 = AMPP_FUNCTION(S1_F_pc[11], S1L893);

--AD1_q_b[19] is std_1c20:inst|cpu:the_cpu|cpu_ic_data_module:cpu_ic_data|altsyncram:the_altsyncram|altsyncram_qmb1:auto_generated|q_b[19]

--RAM Block Operation Mode: Simple Dual-Port

--Port A Depth: 1024, Port A Width: 1, Port B Depth: 1024, Port B Width: 1

--Port A Logical Depth: 1024, Port A Logical Width: 32, Port B Logical Depth: 1024, Port B Logical Width: 32

--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered

AD1_q_b[19] = AMPP_FUNCTION(GND, GND, QC2__clk0, QC2__clk0, S1_i_readdatavalid_d1, S1_W_stall, S1_i_readdata_d1[19], S1_ic_fill_dp_offset[0], S1_ic_fill_dp_offset[1], S1_ic_fill_dp_offset[2], S1_ic_fill_line[0], S1_ic_fill_line[1], S1_ic_fill_line[2], S1_ic_fill_line[3], S1_ic_fill_line[4], S1_ic_fill_line[5], S1_ic_fill_line[6], S1L789, S1L792, S1L795, S1L821, S1L824, S1L827, S1L830, S1L833, S1L836, S1L839);

--T1L113 is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[11]~5236

--operation mode is normal

T1L113 = T1L100 & T1L209 & (!WB1_cpu_data_master_granted_uart1_s1);

--T1_registered_cpu_data_master_readdata[13] is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|registered_cpu_data_master_readdata[13]

--operation mode is normal

T1_registered_cpu_data_master_readdata[13]_lut_out = T1L256 & T1L284 & (KB1_za_data[13] # !NB1L17);

T1_registered_cpu_data_master_readdata[13] = DFFEAS(T1_registered_cpu_data_master_readdata[13]_lut_out, QC2__clk0, F1_data_out, , , , , , );

--T1L127 is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[13]~5237

--operation mode is normal

T1L127 = T1_registered_cpu_data_master_readdata[13] # !K1_cpu_data_master_requests_clock_0_in & (!CB1L2 # !UB1L9);

--T1_dbs_8_reg_segment_1[5] is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|dbs_8_reg_segment_1[5]

--operation mode is normal

T1_dbs_8_reg_segment_1[5]_lut_out = Y1_internal_incoming_ext_ram_bus_data[5];

T1_dbs_8_reg_segment_1[5] = DFFEAS(T1_dbs_8_reg_segment_1[5]_lut_out, QC2__clk0, F1_data_out, , T1L295, , , , );

--T1L204 is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata~337

--operation mode is normal

T1L204 = T1_dbs_8_reg_segment_1[5] # !Y1_cpu_data_master_requests_ext_flash_s1;

--Y1_internal_incoming_ext_ram_bus_data[13] is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|internal_incoming_ext_ram_bus_data[13]

--operation mode is normal

Y1_internal_incoming_ext_ram_bus_data[13]_lut_out = A1L103;

Y1_internal_incoming_ext_ram_bus_data[13] = DFFEAS(Y1_internal_incoming_ext_ram_bus_data[13]_lut_out, QC2__clk0, F1_data_out, , , , , , );

--T1L128 is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[13]~5238

--operation mode is normal

T1L128 = T1L204 & (Y1_internal_incoming_ext_ram_bus_data[13] # !Y1L78 & !Y1_cpu_data_master_requests_ext_ram_s1);

--T1L129 is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[13]~5239

--operation mode is normal

T1L129 = T1L128 & (T1_registered_cpu_data_master_readdata[13] # !NB1L17 & !N1_cpu_data_master_requests_clock_1_in);

--Z1_readdata[13] is std_1c20:inst|high_res_timer:the_high_res_timer|readdata[13]

--operation mode is normal

Z1_readdata[13]_lut_out = S1_M_alu_result[3] & !S1_M_alu_result[4] & (Z1L185 $ !Z1L186) # !S1_M_alu_result[3] & S1_M_alu_result[4] & Z1L185;

Z1_readdata[13] = DFFEAS(Z1_readdata[13]_lut_out, QC2__clk0, F1_data_out, , , , , , );

--T1L130 is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[13]~5240

--operation mode is normal

T1L130 = T1L127 & T1L129 & (Z1_readdata[13] # !AB1_cpu_data_master_requests_high_res_timer_s1);

--RB1_readdata[13] is std_1c20:inst|sys_clk_timer:the_sys_clk_timer|readdata[13]

--operation mode is normal

RB1_readdata[13]_lut_out = S1_M_alu_result[3] & !S1_M_alu_result[4] & (RB1L186 $ !RB1L187) # !S1_M_alu_result[3] & S1_M_alu_result[4] & RB1L186;

RB1_readdata[13] = DFFEAS(RB1_readdata[13]_lut_out, QC2__clk0, F1_data_out, , , , , , );

--T1L131 is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[13]~5241

--operation mode is normal

T1L131 = T1L113 & T1L130 & (RB1_readdata[13] # !SB1_cpu_data_master_requests_sys_clk_timer_s1);

--DE1_data_to_cpu[13] is std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|data_to_cpu[13]

--operation mode is normal

DE1_data_to_cpu[13]_lut_out = DE1L114 & DE1_endofpacketvalue_reg[13] # !DE1L114 & (DE1L113 & DE1_epcs_slave_select_reg[13]);

DE1_data_to_cpu[13] = DFFEAS(DE1_data_to_cpu[13]_lut_out, QC2__clk0, F1_data_out, , , , , , );

--FE1_q_a[13] is std_1c20:inst|epcs_controller:the_epcs_controller|altsyncram:the_boot_copier_rom|altsyncram_3h31:auto_generated|q_a[13]

--RAM Block Operation Mode: ROM

--Port A Depth: 128, Port A Width: 1

--Port A Logical Depth: 128, Port A Logical Width: 32

--Port A Input: Registered, Port A Output: Un-registered

FE1_q_a[13]_PORT_A_address = BUS(X1L14, X1L15, X1L16, X1L17, X1L18, X1L19, X1L20);

FE1_q_a[13]_PORT_A_address_reg = DFFE(FE1_q_a[13]_PORT_A_address, FE1_q_a[13]_clock_0, , , );

FE1_q_a[13]_clock_0 = QC2__clk0;

FE1_q_a[13]_PORT_A_data_out = MEMORY(, , FE1_q_a[13]_PORT_A_address_reg, , , , , , FE1_q_a[13]_clock_0, , , , , );

FE1_q_a[13] = FE1_q_a[13]_PORT_A_data_out[0];

--U1L116 is std_1c20:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_readdata~2401

--operation mode is normal

U1L116 = W1L1 & DE1_data_to_cpu[13] # !W1L1 & (FE1_q_a[13]);

--T1L132 is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[13]~5242

--operation mode is normal

T1L132 = T1L131 & (U1L116 # !X1_cpu_data_master_requests_epcs_controller_epcs_control_port);

--WC1L14 is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|readdata[13]~1353

--operation mode is normal

WC1L14 = AMPP_FUNCTION(CE1_q_a[13], V1L4, S1_ic_fill_line[5], S1_M_alu_result[10]);

--Y1_internal_incoming_ext_ram_bus_data[29] is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|internal_incoming_ext_ram_bus_data[29]

--operation mode is normal

Y1_internal_incoming_ext_ram_bus_data[29]_lut_out = A1L87;

Y1_internal_incoming_ext_ram_bus_data[29] = DFFEAS(Y1_internal_incoming_ext_ram_bus_data[29]_lut_out, QC2__clk0, F1_data_out, , , , , , );

--Y1_internal_incoming_ext_ram_bus_data[5] is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|internal_incoming_ext_ram_bus_data[5]

--operation mode is normal

Y1_internal_incoming_ext_ram_bus_data[5]_lut_out = A1L111;

Y1_internal_incoming_ext_ram_bus_data[5] = DFFEAS(Y1_internal_incoming_ext_ram_bus_data[5]_lut_out, QC2__clk0, F1_data_out, , , , , , );

--T1_registered_cpu_data_master_readdata[29] is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|registered_cpu_data_master_readdata[29]

--operation mode is normal

T1_registered_cpu_data_master_readdata[29]_lut_out = T1L270 & !K1L6 & (!CB1L2 # !UB1L9);

T1_registered_cpu_data_master_readdata[29] = DFFEAS(T1_registered_cpu_data_master_readdata[29]_lut_out, QC2__clk0, F1_data_out, , , , , , );

--T1L188 is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[29]~5243

--operation mode is normal

T1L188 = Y1_internal_incoming_ext_ram_bus_data[5] & (!T1_registered_cpu_data_master_readdata[29] & T1L164) # !Y1_internal_incoming_ext_ram_bus_data[5] & (Y1_cpu_data_master_requests_ext_flash_s1 # !T1_registered_cpu_data_master_readdata[29] & T1L164);

--T1L189 is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[29]~5244

--operation mode is normal

T1L189 = !T1L188 & (Y1_internal_incoming_ext_ram_bus_data[29] # !Y1L78 & !Y1_cpu_data_master_requests_ext_ram_s1);

--FE1_q_a[29] is std_1c20:inst|epcs_controller:the_epcs_controller|altsyncram:the_boot_copier_rom|altsyncram_3h31:auto_generated|q_a[29]

--RAM Block Operation Mode: ROM

--Port A Depth: 128, Port A Width: 1

--Port A Logical Depth: 128, Port A Logical Width: 32

--Port A Input: Registered, Port A Output: Un-registered

FE1_q_a[29]_PORT_A_address = BUS(X1L14, X1L15, X1L16, X1L17, X1L18, X1L19, X1L20);

FE1_q_a[29]_PORT_A_address_reg = DFFE(FE1_q_a[29]_PORT_A_address, FE1_q_a[29]_clock_0, , , );

FE1_q_a[29]_clock_0 = QC2__clk0;

FE1_q_a[29]_PORT_A_data_out = MEMORY(, , FE1_q_a[29]_PORT_A_address_reg, , , , , , FE1_q_a[29]_clock_0, , , , , );

FE1_q_a[29] = FE1_q_a[29]_PORT_A_data_out[0];

--W1L15 is std_1c20:inst|epcs_controller:the_epcs_controller|readdata[29]~696

--operation mode is normal

W1L15 = FE1_q_a[29] & (!W1L1);

--T1L190 is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[29]~5245

--operation mode is normal

T1L190 = T1L150 & T1L189 & (W1L15 # !X1_cpu_data_master_requests_epcs_controller_epcs_control_port);

--WC1L31 is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|readdata[29]~1354

--operation mode is normal

WC1L31 = AMPP_FUNCTION(CE1_q_a[29], V1L4, S1_ic_fill_line[5], S1_M_alu_result[10]);

--S1L892 is std_1c20:inst|cpu:the_cpu|F_pc_plus_one[10]~70

--operation mode is arithmetic

S1L892 = AMPP_FUNCTION(S1_F_pc[10], S1L891);

--S1L893 is std_1c20:inst|cpu:the_cpu|F_pc_plus_one[10]~71

--operation mode is arithmetic

S1L893 = AMPP_FUNCTION(S1_F_pc[10], S1L891);

--S1L112 is std_1c20:inst|cpu:the_cpu|Add1~279

--operation mode is arithmetic

S1L112 = AMPP_FUNCTION(S1_D_br_taken_waddr_partial[10]);

--AD1_q_b[18] is std_1c20:inst|cpu:the_cpu|cpu_ic_data_module:cpu_ic_data|altsyncram:the_altsyncram|altsyncram_qmb1:auto_generated|q_b[18]

--RAM Block Operation Mode: Simple Dual-Port

--Port A Depth: 1024, Port A Width: 1, Port B Depth: 1024, Port B Width: 1

--Port A Logical Depth: 1024, Port A Logical Width: 32, Port B Logical Depth: 1024, Port B Logical Width: 32

--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered

AD1_q_b[18] = AMPP_FUNCTION(GND, GND, QC2__clk0, QC2__clk0, S1_i_readdatavalid_d1, S1_W_stall, S1_i_readdata_d1[18], S1_ic_fill_dp_offset[0], S1_ic_fill_dp_offset[1], S1_ic_fill_dp_offset[2], S1_ic_fill_line[0], S1_ic_fill_line[1], S1_ic_fill_line[2], S1_ic_fill_line[3], S1_ic_fill_line[4], S1_ic_fill_line[5], S1_ic_fill_line[6], S1L789, S1L792, S1L795, S1L821, S1L824, S1L827, S1L830, S1L833, S1L836, S1L839);

--T1_registered_cpu_data_master_readdata[12] is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|registered_cpu_data_master_readdata[12]

--operation mode is normal

T1_registered_cpu_data_master_readdata[12]_lut_out = T1L255 & T1L283 & (KB1_za_data[12] # !NB1L17);

T1_registered_cpu_data_master_readdata[12] = DFFEAS(T1_registered_cpu_data_master_readdata[12]_lut_out, QC2__clk0, F1_data_out, , , , , , );

--T1L121 is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[12]~5246

--operation mode is normal

T1L121 = T1_registered_cpu_data_master_readdata[12] # !K1_cpu_data_master_requests_clock_0_in & (!CB1L2 # !UB1L9);

--T1_dbs_8_reg_segment_1[4] is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|dbs_8_reg_segment_1[4]

--operation mode is normal

T1_dbs_8_reg_segment_1[4]_lut_out = Y1_internal_incoming_ext_ram_bus_data[4];

T1_dbs_8_reg_segment_1[4] = DFFEAS(T1_dbs_8_reg_segment_1[4]_lut_out, QC2__clk0, F1_data_out, , T1L295, , , , );

--T1L203 is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata~336

--operation mode is normal

T1L203 = T1_dbs_8_reg_segment_1[4] # !Y1_cpu_data_master_requests_ext_flash_s1;

--Y1_internal_incoming_ext_ram_bus_data[12] is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|internal_incoming_ext_ram_bus_data[12]

--operation mode is normal

Y1_internal_incoming_ext_ram_bus_data[12]_lut_out = A1L104;

Y1_internal_incoming_ext_ram_bus_data[12] = DFFEAS(Y1_internal_incoming_ext_ram_bus_data[12]_lut_out, QC2__clk0, F1_data_out, , , , , , );

--T1L122 is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[12]~5247

--operation mode is normal

T1L122 = T1L203 & (Y1_internal_incoming_ext_ram_bus_data[12] # !Y1L78 & !Y1_cpu_data_master_requests_ext_ram_s1);

--T1L123 is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[12]~5248

--operation mode is normal

T1L123 = T1L122 & (T1_registered_cpu_data_master_readdata[12] # !NB1L17 & !N1_cpu_data_master_requests_clock_1_in);

--Z1_readdata[12] is std_1c20:inst|high_res_timer:the_high_res_timer|readdata[12]

--operation mode is normal

Z1_readdata[12]_lut_out = S1_M_alu_result[3] & !S1_M_alu_result[4] & (Z1L183 $ !Z1L184) # !S1_M_alu_result[3] & S1_M_alu_result[4] & Z1L183;

Z1_readdata[12] = DFFEAS(Z1_readdata[12]_lut_out, QC2__clk0, F1_data_out, , , , , , );

--T1L124 is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[12]~5249

--operation mode is normal

T1L124 = T1L121 & T1L123 & (Z1_readdata[12] # !AB1_cpu_data_master_requests_high_res_timer_s1);

--RB1_readdata[12] is std_1c20:inst|sys_clk_timer:the_sys_clk_timer|readdata[12]

--operation mode is normal

RB1_readdata[12]_lut_out = S1_M_alu_result[3] & !S1_M_alu_result[4] & (RB1L184 $ !RB1L185) # !S1_M_alu_result[3] & S1_M_alu_result[4] & RB1L184;

RB1_readdata[12] = DFFEAS(RB1_readdata[12]_lut_out, QC2__clk0, F1_data_out, , , , , , );

--T1L125 is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[12]~5250

--operation mode is normal

T1L125 = T1L120 & T1L124 & (RB1_readdata[12] # !SB1_cpu_data_master_requests_sys_clk_timer_s1);

--DE1_data_to_cpu[12] is std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|data_to_cpu[12]

--operation mode is normal

DE1_data_to_cpu[12]_lut_out = DE1L114 & DE1_endofpacketvalue_reg[12] # !DE1L114 & (DE1L113 & DE1_epcs_slave_select_reg[12]);

DE1_data_to_cpu[12] = DFFEAS(DE1_data_to_cpu[12]_lut_out, QC2__clk0, F1_data_out, , , , , , );

--FE1_q_a[12] is std_1c20:inst|epcs_controller:the_epcs_controller|altsyncram:the_boot_copier_rom|altsyncram_3h31:auto_generated|q_a[12]

--RAM Block Operation Mode: ROM

--Port A Depth: 128, Port A Width: 1

--Port A Logical Depth: 128, Port A Logical Width: 32

--Port A Input: Registered, Port A Output: Un-registered

FE1_q_a[12]_PORT_A_address = BUS(X1L14, X1L15, X1L16, X1L17, X1L18, X1L19, X1L20);

FE1_q_a[12]_PORT_A_address_reg = DFFE(FE1_q_a[12]_PORT_A_address, FE1_q_a[12]_clock_0, , , );

FE1_q_a[12]_clock_0 = QC2__clk0;

FE1_q_a[12]_PORT_A_data_out = MEMORY(, , FE1_q_a[12]_PORT_A_address_reg, , , , , , FE1_q_a[12]_clock_0, , , , , );

FE1_q_a[12] = FE1_q_a[12]_PORT_A_data_out[0];

--U1L117 is std_1c20:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_readdata~2402

--operation mode is normal

U1L117 = W1L1 & DE1_data_to_cpu[12] # !W1L1 & (FE1_q_a[12]);

--T1L126 is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[12]~5251

--operation mode is normal

T1L126 = T1L125 & (U1L117 # !X1_cpu_data_master_requests_epcs_controller_epcs_control_port);

--WC1L13 is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|readdata[12]~1355

--operation mode is normal

WC1L13 = AMPP_FUNCTION(CE1_q_a[12], V1L4, S1_ic_fill_line[5], S1_M_alu_result[10]);

--Y1_internal_incoming_ext_ram_bus_data[28] is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|internal_incoming_ext_ram_bus_data[28]

--operation mode is normal

Y1_internal_incoming_ext_ram_bus_data[28]_lut_out = A1L88;

Y1_internal_incoming_ext_ram_bus_data[28] = DFFEAS(Y1_internal_incoming_ext_ram_bus_data[28]_lut_out, QC2__clk0, F1_data_out, , , , , , );

--Y1_internal_incoming_ext_ram_bus_data[4] is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|internal_incoming_ext_ram_bus_data[4]

--operation mode is normal

Y1_internal_incoming_ext_ram_bus_data[4]_lut_out = A1L112;

Y1_internal_incoming_ext_ram_bus_data[4] = DFFEAS(Y1_internal_incoming_ext_ram_bus_data[4]_lut_out, QC2__clk0, F1_data_out, , , , , , );

--T1_registered_cpu_data_master_readdata[28] is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|registered_cpu_data_master_readdata[28]

--operation mode is normal

T1_registered_cpu_data_master_readdata[28]_lut_out = T1L269 & !K1L6 & (!CB1L2 # !UB1L9);

T1_registered_cpu_data_master_readdata[28] = DFFEAS(T1_registered_cpu_data_master_readdata[28]_lut_out, QC2__clk0, F1_data_out, , , , , , );

--T1L185 is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[28]~5252

--operation mode is normal

T1L185 = Y1_internal_incoming_ext_ram_bus_data[4] & (!T1_registered_cpu_data_master_readdata[28] & T1L164) # !Y1_internal_incoming_ext_ram_bus_data[4] & (Y1_cpu_data_master_requests_ext_flash_s1 # !T1_registered_cpu_data_master_readdata[28] & T1L164);

--T1L186 is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[28]~5253

--operation mode is normal

T1L186 = !T1L185 & (Y1_internal_incoming_ext_ram_bus_data[28] # !Y1L78 & !Y1_cpu_data_master_requests_ext_ram_s1);

--FE1_q_a[28] is std_1c20:inst|epcs_controller:the_epcs_controller|altsyncram:the_boot_copier_rom|altsyncram_3h31:auto_generated|q_a[28]

--RAM Block Operation Mode: ROM

--Port A Depth: 128, Port A Width: 1

--Port A Logical Depth: 128, Port A Logical Width: 32

--Port A Input: Registered, Port A Output: Un-registered

FE1_q_a[28]_PORT_A_address = BUS(X1L14, X1L15, X1L16, X1L17, X1L18, X1L19, X1L20);

FE1_q_a[28]_PORT_A_address_reg = DFFE(FE1_q_a[28]_PORT_A_address, FE1_q_a[28]_clock_0, , , );

FE1_q_a[28]_clock_0 = QC2__clk0;

FE1_q_a[28]_PORT_A_data_out = MEMORY(, , FE1_q_a[28]_PORT_A_address_reg, , , , , , FE1_q_a[28]_clock_0, , , , , );

FE1_q_a[28] = FE1_q_a[28]_PORT_A_data_out[0];

--W1L14 is std_1c20:inst|epcs_controller:the_epcs_controller|readdata[28]~697

--operation mode is normal

W1L14 = FE1_q_a[28] & (!W1L1);

--T1L187 is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[28]~5254

--operation mode is normal

T1L187 = T1L150 & T1L186 & (W1L14 # !X1_cpu_data_master_requests_epcs_controller_epcs_control_port);

--WC1L30 is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|readdata[28]~1356

--operation mode is normal

WC1L30 = AMPP_FUNCTION(CE1_q_a[28], V1L4, S1_ic_fill_line[5], S1_M_alu_result[10]);

--S1L902 is std_1c20:inst|cpu:the_cpu|F_pc_plus_one[15]~72

--operation mode is arithmetic

S1L902 = AMPP_FUNCTION(S1_F_pc[15], S1L901);

--S1L903 is std_1c20:inst|cpu:the_cpu|F_pc_plus_one[15]~73

--operation mode is arithmetic

S1L903 = AMPP_FUNCTION(S1_F_pc[15], S1L901);

--Y1_internal_incoming_ext_ram_bus_data[17] is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|internal_incoming_ext_ram_bus_data[17]

--operation mode is normal

Y1_internal_incoming_ext_ram_bus_data[17]_lut_out = A1L99;

Y1_internal_incoming_ext_ram_bus_data[17] = DFFEAS(Y1_internal_incoming_ext_ram_bus_data[17]_lut_out, QC2__clk0, F1_data_out, , , , , , );

--T1_dbs_8_reg_segment_2[1] is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|dbs_8_reg_segment_2[1]

--operation mode is normal

T1_dbs_8_reg_segment_2[1]_lut_out = Y1_internal_incoming_ext_ram_bus_data[1];

T1_dbs_8_reg_segment_2[1] = DFFEAS(T1_dbs_8_reg_segment_2[1]_lut_out, QC2__clk0, F1_data_out, , T1L296, , , , );

--T1_registered_cpu_data_master_readdata[17] is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|registered_cpu_data_master_readdata[17]

--operation mode is normal

T1_registered_cpu_data_master_readdata[17]_lut_out = BB1L34 & !K1L6 & (KB1_za_data[17] # !NB1L17);

T1_registered_cpu_data_master_readdata[17] = DFFEAS(T1_registered_cpu_data_master_readdata[17]_lut_out, QC2__clk0, F1_data_out, , , , , , );

--T1L147 is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[17]~5255

--operation mode is normal

T1L147 = T1_dbs_8_reg_segment_2[1] & (!T1_registered_cpu_data_master_readdata[17] & T1L164) # !T1_dbs_8_reg_segment_2[1] & (Y1_cpu_data_master_requests_ext_flash_s1 # !T1_registered_cpu_data_master_readdata[17] & T1L164);

--T1L148 is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[17]~5256

--operation mode is normal

T1L148 = !T1L147 & (Y1_internal_incoming_ext_ram_bus_data[17] # !Y1L78 & !Y1_cpu_data_master_requests_ext_ram_s1);

--FE1_q_a[17] is std_1c20:inst|epcs_controller:the_epcs_controller|altsyncram:the_boot_copier_rom|altsyncram_3h31:auto_generated|q_a[17]

--RAM Block Operation Mode: ROM

--Port A Depth: 128, Port A Width: 1

--Port A Logical Depth: 128, Port A Logical Width: 32

--Port A Input: Registered, Port A Output: Un-registered

FE1_q_a[17]_PORT_A_address = BUS(X1L14, X1L15, X1L16, X1L17, X1L18, X1L19, X1L20);

FE1_q_a[17]_PORT_A_address_reg = DFFE(FE1_q_a[17]_PORT_A_address, FE1_q_a[17]_clock_0, , , );

FE1_q_a[17]_clock_0 = QC2__clk0;

FE1_q_a[17]_PORT_A_data_out = MEMORY(, , FE1_q_a[17]_PORT_A_address_reg, , , , , , FE1_q_a[17]_clock_0, , , , , );

FE1_q_a[17] = FE1_q_a[17]_PORT_A_data_out[0];

--W1L3 is std_1c20:inst|epcs_controller:the_epcs_controller|readdata[17]~698

--operation mode is normal

W1L3 = FE1_q_a[17] & (!W1L1);

--T1L149 is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[17]~5257

--operation mode is normal

T1L149 = T1L168 & T1L148 & (W1L3 # !X1_cpu_data_master_requests_epcs_controller_epcs_control_port);

--WC1L18 is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|readdata[17]~1357

--operation mode is normal

WC1L18 = AMPP_FUNCTION(CE1_q_a[17], V1L4, S1_ic_fill_line[5], S1_M_alu_result[10]);

--DD1_q_b[17] is std_1c20:inst|cpu:the_cpu|cpu_register_bank_b_module:cpu_register_bank_b|altsyncram:the_altsyncram|altsyncram_4vd1:auto_generated|q_b[17]

--RAM Block Operation Mode: Simple Dual-Port

--Port A Depth: 32, Port A Width: 1, Port B Depth: 32, Port B Width: 1

--Port A Logical Depth: 32, Port A Logical Width: 32, Port B Logical Depth: 32, Port B Logical Width: 32

--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered

DD1_q_b[17] = AMPP_FUNCTION(GND, GND, QC2__clk0, QC2__clk0, !S1_M_wr_dst_reg, S1_W_stall, S1L1333, S1_M_dst_regnum[0], S1_M_dst_regnum[1], S1_M_dst_regnum[2], S1_M_dst_regnum[3], S1_M_dst_regnum[4], AD1_q_b[22], AD1_q_b[23], AD1_q_b[24], AD1_q_b[25], AD1_q_b[26]);

--S1L918 is std_1c20:inst|cpu:the_cpu|F_pc_plus_one[23]~74

--operation mode is normal

S1L918 = AMPP_FUNCTION(S1_F_pc[23], S1L917);

--S1_M_shift_rot_result[27] is std_1c20:inst|cpu:the_cpu|M_shift_rot_result[27]

--operation mode is normal

S1_M_shift_rot_result[27] = AMPP_FUNCTION(QC2__clk0, S1_M_shift_rot_result[26], S1_M_shift_rot_result[28], S1L596, S1_M_ctrl_shift_rot_right, F1_data_out, !S1_M_shift_rot_stall);

--S1_E_src1_prelim[26] is std_1c20:inst|cpu:the_cpu|E_src1_prelim[26]

--operation mode is normal

S1_E_src1_prelim[26] = AMPP_FUNCTION(QC2__clk0, CD1_q_b[26], S1_W_wr_data[26], S1L1360, S1_D_src1_hazard_W, F1_data_out, S1_D_src1_hazard_M, S1_W_stall);

--S1L1358 is std_1c20:inst|cpu:the_cpu|M_wr_data_unfiltered[26]~3697

--operation mode is normal

S1L1358 = AMPP_FUNCTION(S1_M_shift_rot_result[26], S1_M_ctrl_shift_rot);

--S1_av_ld_data_aligned_or_div[26] is std_1c20:inst|cpu:the_cpu|av_ld_data_aligned_or_div[26]

--operation mode is normal

S1_av_ld_data_aligned_or_div[26] = AMPP_FUNCTION(QC2__clk0, S1_d_readdata_d1[26], S1_M_ctrl_ld_signed, S1L174, S1_M_iw[4], F1_data_out);

--S1_M_alu_result[26] is std_1c20:inst|cpu:the_cpu|M_alu_result[26]

--operation mode is normal

S1_M_alu_result[26] = AMPP_FUNCTION(QC2__clk0, S1L49, S1L534, A1L276, S1_E_ctrl_dst_data_sel_logic_result, F1_data_out, S1_E_ctrl_dst_data_sel_cmp, S1_E_ctrl_rdctl_inst, S1_W_stall);

--S1L1359 is std_1c20:inst|cpu:the_cpu|M_wr_data_unfiltered[26]~3698

--operation mode is normal

S1L1359 = AMPP_FUNCTION(S1_av_ld_data_aligned_or_div[26], S1_M_alu_result[26], S1_av_ld_or_div_done, S1_M_ctrl_shift_rot);

--S1L595 is std_1c20:inst|cpu:the_cpu|E_src1[26]~2041

--operation mode is normal

S1L595 = AMPP_FUNCTION(S1_E_src1_prelim[26], S1_E_src1_hazard_M, S1L1358, S1L1359);

--Y1_internal_incoming_ext_ram_bus_data[25] is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|internal_incoming_ext_ram_bus_data[25]

--operation mode is normal

Y1_internal_incoming_ext_ram_bus_data[25]_lut_out = A1L91;

Y1_internal_incoming_ext_ram_bus_data[25] = DFFEAS(Y1_internal_incoming_ext_ram_bus_data[25]_lut_out, QC2__clk0, F1_data_out, , , , , , );

--Y1_internal_incoming_ext_ram_bus_data[1] is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|internal_incoming_ext_ram_bus_data[1]

--operation mode is normal

Y1_internal_incoming_ext_ram_bus_data[1]_lut_out = A1L115;

Y1_internal_incoming_ext_ram_bus_data[1] = DFFEAS(Y1_internal_incoming_ext_ram_bus_data[1]_lut_out, QC2__clk0, F1_data_out, , , , , , );

--T1_registered_cpu_data_master_readdata[25] is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|registered_cpu_data_master_readdata[25]

--operation mode is normal

T1_registered_cpu_data_master_readdata[25]_lut_out = T1L266 & !K1L6 & (!CB1L2 # !UB1L9);

T1_registered_cpu_data_master_readdata[25] = DFFEAS(T1_registered_cpu_data_master_readdata[25]_lut_out, QC2__clk0, F1_data_out, , , , , , );

--T1L175 is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[25]~5258

--operation mode is normal

T1L175 = Y1_internal_incoming_ext_ram_bus_data[1] & (!T1_registered_cpu_data_master_readdata[25] & T1L164) # !Y1_internal_incoming_ext_ram_bus_data[1] & (Y1_cpu_data_master_requests_ext_flash_s1 # !T1_registered_cpu_data_master_readdata[25] & T1L164);

--T1L176 is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[25]~5259

--operation mode is normal

T1L176 = !T1L175 & (Y1_internal_incoming_ext_ram_bus_data[25] # !Y1L78 & !Y1_cpu_data_master_requests_ext_ram_s1);

--FE1_q_a[25] is std_1c20:inst|epcs_controller:the_epcs_controller|altsyncram:the_boot_copier_rom|altsyncram_3h31:auto_generated|q_a[25]

--RAM Block Operation Mode: ROM

--Port A Depth: 128, Port A Width: 1

--Port A Logical Depth: 128, Port A Logical Width: 32

--Port A Input: Registered, Port A Output: Un-registered

FE1_q_a[25]_PORT_A_address = BUS(X1L14, X1L15, X1L16, X1L17, X1L18, X1L19, X1L20);

FE1_q_a[25]_PORT_A_address_reg = DFFE(FE1_q_a[25]_PORT_A_address, FE1_q_a[25]_clock_0, , , );

FE1_q_a[25]_clock_0 = QC2__clk0;

FE1_q_a[25]_PORT_A_data_out = MEMORY(, , FE1_q_a[25]_PORT_A_address_reg, , , , , , FE1_q_a[25]_clock_0, , , , , );

FE1_q_a[25] = FE1_q_a[25]_PORT_A_data_out[0];

--W1L11 is std_1c20:inst|epcs_controller:the_epcs_controller|readdata[25]~699

--operation mode is normal

W1L11 = FE1_q_a[25] & (!W1L1);

--T1L177 is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[25]~5260

--operation mode is normal

T1L177 = T1L168 & T1L176 & (W1L11 # !X1_cpu_data_master_requests_epcs_controller_epcs_control_port);

--WC1L27 is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|readdata[25]~1358

--operation mode is normal

WC1L27 = AMPP_FUNCTION(CE1_q_a[25], V1L4, S1_ic_fill_line[5], S1_M_alu_result[10]);

--S1L908 is std_1c20:inst|cpu:the_cpu|F_pc_plus_one[18]~76

--operation mode is arithmetic

S1L908 = AMPP_FUNCTION(S1_F_pc[18], S1L907);

--S1L909 is std_1c20:inst|cpu:the_cpu|F_pc_plus_one[18]~77

--operation mode is arithmetic

S1L909 = AMPP_FUNCTION(S1_F_pc[18], S1L907);

--Y1_internal_incoming_ext_ram_bus_data[20] is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|internal_incoming_ext_ram_bus_data[20]

--operation mode is normal

Y1_internal_incoming_ext_ram_bus_data[20]_lut_out = A1L96;

Y1_internal_incoming_ext_ram_bus_data[20] = DFFEAS(Y1_internal_incoming_ext_ram_bus_data[20]_lut_out, QC2__clk0, F1_data_out, , , , , , );

--T1_dbs_8_reg_segment_2[4] is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|dbs_8_reg_segment_2[4]

--operation mode is normal

T1_dbs_8_reg_segment_2[4]_lut_out = Y1_internal_incoming_ext_ram_bus_data[4];

T1_dbs_8_reg_segment_2[4] = DFFEAS(T1_dbs_8_reg_segment_2[4]_lut_out, QC2__clk0, F1_data_out, , T1L296, , , , );

--T1_registered_cpu_data_master_readdata[20] is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|registered_cpu_data_master_readdata[20]

--operation mode is normal

T1_registered_cpu_data_master_readdata[20]_lut_out = T1L261 & !K1L6 & (BB1L37 # !CB1_cpu_data_master_requests_jtag_uart_avalon_jtag_slave);

T1_registered_cpu_data_master_readdata[20] = DFFEAS(T1_registered_cpu_data_master_readdata[20]_lut_out, QC2__clk0, F1_data_out, , , , , , );

--T1L158 is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[20]~5261

--operation mode is normal

T1L158 = T1_dbs_8_reg_segment_2[4] & (!T1_registered_cpu_data_master_readdata[20] & T1L164) # !T1_dbs_8_reg_segment_2[4] & (Y1_cpu_data_master_requests_ext_flash_s1 # !T1_registered_cpu_data_master_readdata[20] & T1L164);

--T1L159 is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[20]~5262

--operation mode is normal

T1L159 = !T1L158 & (Y1_internal_incoming_ext_ram_bus_data[20] # !Y1L78 & !Y1_cpu_data_master_requests_ext_ram_s1);

--FE1_q_a[20] is std_1c20:inst|epcs_controller:the_epcs_controller|altsyncram:the_boot_copier_rom|altsyncram_3h31:auto_generated|q_a[20]

--RAM Block Operation Mode: ROM

--Port A Depth: 128, Port A Width: 1

--Port A Logical Depth: 128, Port A Logical Width: 32

--Port A Input: Registered, Port A Output: Un-registered

FE1_q_a[20]_PORT_A_address = BUS(X1L14, X1L15, X1L16, X1L17, X1L18, X1L19, X1L20);

FE1_q_a[20]_PORT_A_address_reg = DFFE(FE1_q_a[20]_PORT_A_address, FE1_q_a[20]_clock_0, , , );

FE1_q_a[20]_clock_0 = QC2__clk0;

FE1_q_a[20]_PORT_A_data_out = MEMORY(, , FE1_q_a[20]_PORT_A_address_reg, , , , , , FE1_q_a[20]_clock_0, , , , , );

FE1_q_a[20] = FE1_q_a[20]_PORT_A_data_out[0];

--W1L6 is std_1c20:inst|epcs_controller:the_epcs_controller|readdata[20]~700

--operation mode is normal

W1L6 = FE1_q_a[20] & (!W1L1);

--T1L160 is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[20]~5263

--operation mode is normal

T1L160 = T1L168 & T1L159 & (W1L6 # !X1_cpu_data_master_requests_epcs_controller_epcs_control_port);

--WC1L22 is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|readdata[20]~1359

--operation mode is normal

WC1L22 = AMPP_FUNCTION(CE1_q_a[20], V1L4, S1_ic_fill_line[5], S1_M_alu_result[10]);

--AD1_q_b[10] is std_1c20:inst|cpu:the_cpu|cpu_ic_data_module:cpu_ic_data|altsyncram:the_altsyncram|altsyncram_qmb1:auto_generated|q_b[10]

--RAM Block Operation Mode: Simple Dual-Port

--Port A Depth: 1024, Port A Width: 1, Port B Depth: 1024, Port B Width: 1

--Port A Logical Depth: 1024, Port A Logical Width: 32, Port B Logical Depth: 1024, Port B Logical Width: 32

--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered

AD1_q_b[10] = AMPP_FUNCTION(GND, GND, QC2__clk0, QC2__clk0, S1_i_readdatavalid_d1, S1_W_stall, S1_i_readdata_d1[10], S1_ic_fill_dp_offset[0], S1_ic_fill_dp_offset[1], S1_ic_fill_dp_offset[2], S1_ic_fill_line[0], S1_ic_fill_line[1], S1_ic_fill_line[2], S1_ic_fill_line[3], S1_ic_fill_line[4], S1_ic_fill_line[5], S1_ic_fill_line[6], S1L789, S1L792, S1L795, S1L821, S1L824, S1L827, S1L830, S1L833, S1L836, S1L839);

--DD1_q_b[20] is std_1c20:inst|cpu:the_cpu|cpu_register_bank_b_module:cpu_register_bank_b|altsyncram:the_altsyncram|altsyncram_4vd1:auto_generated|q_b[20]

--RAM Block Operation Mode: Simple Dual-Port

--Port A Depth: 32, Port A Width: 1, Port B Depth: 32, Port B Width: 1

--Port A Logical Depth: 32, Port A Logical Width: 32, Port B Logical Depth: 32, Port B Logical Width: 32

--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered

DD1_q_b[20] = AMPP_FUNCTION(GND, GND, QC2__clk0, QC2__clk0, !S1_M_wr_dst_reg, S1_W_stall, S1L1342, S1_M_dst_regnum[0], S1_M_dst_regnum[1], S1_M_dst_regnum[2], S1_M_dst_regnum[3], S1_M_dst_regnum[4], AD1_q_b[22], AD1_q_b[23], AD1_q_b[24], AD1_q_b[25], AD1_q_b[26]);

--S1L914 is std_1c20:inst|cpu:the_cpu|F_pc_plus_one[21]~78

--operation mode is arithmetic

S1L914 = AMPP_FUNCTION(S1_F_pc[21], S1L913);

--S1L915 is std_1c20:inst|cpu:the_cpu|F_pc_plus_one[21]~79

--operation mode is arithmetic

S1L915 = AMPP_FUNCTION(S1_F_pc[21], S1L913);

--DD1_q_b[23] is std_1c20:inst|cpu:the_cpu|cpu_register_bank_b_module:cpu_register_bank_b|altsyncram:the_altsyncram|altsyncram_4vd1:auto_generated|q_b[23]

--RAM Block Operation Mode: Simple Dual-Port

--Port A Depth: 32, Port A Width: 1, Port B Depth: 32, Port B Width: 1

--Port A Logical Depth: 32, Port A Logical Width: 32, Port B Logical Depth: 32, Port B Logical Width: 32

--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered

DD1_q_b[23] = AMPP_FUNCTION(GND, GND, QC2__clk0, QC2__clk0, !S1_M_wr_dst_reg, S1_W_stall, S1L1351, S1_M_dst_regnum[0], S1_M_dst_regnum[1], S1_M_dst_regnum[2], S1_M_dst_regnum[3], S1_M_dst_regnum[4], AD1_q_b[22], AD1_q_b[23], AD1_q_b[24], AD1_q_b[25], AD1_q_b[26]);

--S1L890 is std_1c20:inst|cpu:the_cpu|F_pc_plus_one[9]~80

--operation mode is arithmetic

S1L890 = AMPP_FUNCTION(S1_F_pc[9], S1L889);

--S1L891 is std_1c20:inst|cpu:the_cpu|F_pc_plus_one[9]~81

--operation mode is arithmetic

S1L891 = AMPP_FUNCTION(S1_F_pc[9], S1L889);

--AD1_q_b[17] is std_1c20:inst|cpu:the_cpu|cpu_ic_data_module:cpu_ic_data|altsyncram:the_altsyncram|altsyncram_qmb1:auto_generated|q_b[17]

--RAM Block Operation Mode: Simple Dual-Port

--Port A Depth: 1024, Port A Width: 1, Port B Depth: 1024, Port B Width: 1

--Port A Logical Depth: 1024, Port A Logical Width: 32, Port B Logical Depth: 1024, Port B Logical Width: 32

--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered

AD1_q_b[17] = AMPP_FUNCTION(GND, GND, QC2__clk0, QC2__clk0, S1_i_readdatavalid_d1, S1_W_stall, S1_i_readdata_d1[17], S1_ic_fill_dp_offset[0], S1_ic_fill_dp_offset[1], S1_ic_fill_dp_offset[2], S1_ic_fill_line[0], S1_ic_fill_line[1], S1_ic_fill_line[2], S1_ic_fill_line[3], S1_ic_fill_line[4], S1_ic_fill_line[5], S1_ic_fill_line[6], S1L789, S1L792, S1L795, S1L821, S1L824, S1L827, S1L830, S1L833, S1L836, S1L839);

--T1_registered_cpu_data_master_readdata[11] is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|registered_cpu_data_master_readdata[11]

--operation mode is normal

T1_registered_cpu_data_master_readdata[11]_lut_out = T1L254 & !CB1_cpu_data_master_requests_jtag_uart_avalon_jtag_slave & (M1_slave_readdata[11] # !N1_cpu_data_master_requests_clock_1_in);

T1_registered_cpu_data_master_readdata[11] = DFFEAS(T1_registered_cpu_data_master_readdata[11]_lut_out, QC2__clk0, F1_data_out, , , , , , );

--T1L114 is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[11]~5264

--operation mode is normal

T1L114 = T1_registered_cpu_data_master_readdata[11] # !K1_cpu_data_master_requests_clock_0_in & (!CB1L2 # !UB1L9);

--T1_dbs_8_reg_segment_1[3] is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|dbs_8_reg_segment_1[3]

--operation mode is normal

T1_dbs_8_reg_segment_1[3]_lut_out = Y1_internal_incoming_ext_ram_bus_data[3];

T1_dbs_8_reg_segment_1[3] = DFFEAS(T1_dbs_8_reg_segment_1[3]_lut_out, QC2__clk0, F1_data_out, , T1L295, , , , );

--T1L202 is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata~335

--operation mode is normal

T1L202 = T1_dbs_8_reg_segment_1[3] # !Y1_cpu_data_master_requests_ext_flash_s1;

--Y1_internal_incoming_ext_ram_bus_data[11] is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|internal_incoming_ext_ram_bus_data[11]

--operation mode is normal

Y1_internal_incoming_ext_ram_bus_data[11]_lut_out = A1L105;

Y1_internal_incoming_ext_ram_bus_data[11] = DFFEAS(Y1_internal_incoming_ext_ram_bus_data[11]_lut_out, QC2__clk0, F1_data_out, , , , , , );

--T1L115 is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[11]~5265

--operation mode is normal

T1L115 = T1L202 & (Y1_internal_incoming_ext_ram_bus_data[11] # !Y1L78 & !Y1_cpu_data_master_requests_ext_ram_s1);

--T1L116 is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[11]~5266

--operation mode is normal

T1L116 = T1L115 & (T1_registered_cpu_data_master_readdata[11] # !NB1L17 & !N1_cpu_data_master_requests_clock_1_in);

--Z1_readdata[11] is std_1c20:inst|high_res_timer:the_high_res_timer|readdata[11]

--operation mode is normal

Z1_readdata[11]_lut_out = S1_M_alu_result[3] & !S1_M_alu_result[4] & (Z1L181 $ !Z1L182) # !S1_M_alu_result[3] & S1_M_alu_result[4] & Z1L181;

Z1_readdata[11] = DFFEAS(Z1_readdata[11]_lut_out, QC2__clk0, F1_data_out, , , , , , );

--T1L117 is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[11]~5267

--operation mode is normal

T1L117 = T1L114 & T1L116 & (Z1_readdata[11] # !AB1_cpu_data_master_requests_high_res_timer_s1);

--RB1_readdata[11] is std_1c20:inst|sys_clk_timer:the_sys_clk_timer|readdata[11]

--operation mode is normal

RB1_readdata[11]_lut_out = S1_M_alu_result[3] & !S1_M_alu_result[4] & (RB1L182 $ !RB1L183) # !S1_M_alu_result[3] & S1_M_alu_result[4] & RB1L182;

RB1_readdata[11] = DFFEAS(RB1_readdata[11]_lut_out, QC2__clk0, F1_data_out, , , , , , );

--T1L118 is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[11]~5268

--operation mode is normal

T1L118 = T1L113 & T1L117 & (RB1_readdata[11] # !SB1_cpu_data_master_requests_sys_clk_timer_s1);

--DE1_data_to_cpu[11] is std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|data_to_cpu[11]

--operation mode is normal

DE1_data_to_cpu[11]_lut_out = DE1L114 & DE1_endofpacketvalue_reg[11] # !DE1L114 & (DE1L113 & DE1_epcs_slave_select_reg[11]);

DE1_data_to_cpu[11] = DFFEAS(DE1_data_to_cpu[11]_lut_out, QC2__clk0, F1_data_out, , , , , , );

--FE1_q_a[11] is std_1c20:inst|epcs_controller:the_epcs_controller|altsyncram:the_boot_copier_rom|altsyncram_3h31:auto_generated|q_a[11]

--RAM Block Operation Mode: ROM

--Port A Depth: 128, Port A Width: 1

--Port A Logical Depth: 128, Port A Logical Width: 32

--Port A Input: Registered, Port A Output: Un-registered

FE1_q_a[11]_PORT_A_address = BUS(X1L14, X1L15, X1L16, X1L17, X1L18, X1L19, X1L20);

FE1_q_a[11]_PORT_A_address_reg = DFFE(FE1_q_a[11]_PORT_A_address, FE1_q_a[11]_clock_0, , , );

FE1_q_a[11]_clock_0 = QC2__clk0;

FE1_q_a[11]_PORT_A_data_out = MEMORY(, , FE1_q_a[11]_PORT_A_address_reg, , , , , , FE1_q_a[11]_clock_0, , , , , );

FE1_q_a[11] = FE1_q_a[11]_PORT_A_data_out[0];

--U1L118 is std_1c20:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_readdata~2403

--operation mode is normal

U1L118 = W1L1 & DE1_data_to_cpu[11] # !W1L1 & (FE1_q_a[11]);

--T1L119 is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[11]~5269

--operation mode is normal

T1L119 = T1L118 & (U1L118 # !X1_cpu_data_master_requests_epcs_controller_epcs_control_port);

--WC1L12 is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|readdata[11]~1360

--operation mode is normal

WC1L12 = AMPP_FUNCTION(CE1_q_a[11], V1L4, S1_ic_fill_line[5], S1_M_alu_result[10]);

--Y1_internal_incoming_ext_ram_bus_data[27] is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|internal_incoming_ext_ram_bus_data[27]

--operation mode is normal

Y1_internal_incoming_ext_ram_bus_data[27]_lut_out = A1L89;

Y1_internal_incoming_ext_ram_bus_data[27] = DFFEAS(Y1_internal_incoming_ext_ram_bus_data[27]_lut_out, QC2__clk0, F1_data_out, , , , , , );

--T1_registered_cpu_data_master_readdata[27] is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|registered_cpu_data_master_readdata[27]

--operation mode is normal

T1_registered_cpu_data_master_readdata[27]_lut_out = T1L268 & !K1L6 & (!CB1L2 # !UB1L9);

T1_registered_cpu_data_master_readdata[27] = DFFEAS(T1_registered_cpu_data_master_readdata[27]_lut_out, QC2__clk0, F1_data_out, , , , , , );

--T1L182 is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[27]~5270

--operation mode is normal

T1L182 = Y1_internal_incoming_ext_ram_bus_data[3] & (!T1_registered_cpu_data_master_readdata[27] & T1L164) # !Y1_internal_incoming_ext_ram_bus_data[3] & (Y1_cpu_data_master_requests_ext_flash_s1 # !T1_registered_cpu_data_master_readdata[27] & T1L164);

--T1L183 is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[27]~5271

--operation mode is normal

T1L183 = !T1L182 & (Y1_internal_incoming_ext_ram_bus_data[27] # !Y1L78 & !Y1_cpu_data_master_requests_ext_ram_s1);

--FE1_q_a[27] is std_1c20:inst|epcs_controller:the_epcs_controller|altsyncram:the_boot_copier_rom|altsyncram_3h31:auto_generated|q_a[27]

--RAM Block Operation Mode: ROM

--Port A Depth: 128, Port A Width: 1

--Port A Logical Depth: 128, Port A Logical Width: 32

--Port A Input: Registered, Port A Output: Un-registered

FE1_q_a[27]_PORT_A_address = BUS(X1L14, X1L15, X1L16, X1L17, X1L18, X1L19, X1L20);

FE1_q_a[27]_PORT_A_address_reg = DFFE(FE1_q_a[27]_PORT_A_address, FE1_q_a[27]_clock_0, , , );

FE1_q_a[27]_clock_0 = QC2__clk0;

FE1_q_a[27]_PORT_A_data_out = MEMORY(, , FE1_q_a[27]_PORT_A_address_reg, , , , , , FE1_q_a[27]_clock_0, , , , , );

FE1_q_a[27] = FE1_q_a[27]_PORT_A_data_out[0];

--W1L13 is std_1c20:inst|epcs_controller:the_epcs_controller|readdata[27]~701

--operation mode is normal

W1L13 = FE1_q_a[27] & (!W1L1);

--T1L184 is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[27]~5272

--operation mode is normal

T1L184 = T1L168 & T1L183 & (W1L13 # !X1_cpu_data_master_requests_epcs_controller_epcs_control_port);

--WC1L29 is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|readdata[27]~1361

--operation mode is normal

WC1L29 = AMPP_FUNCTION(CE1_q_a[27], V1L4, S1_ic_fill_line[5], S1_M_alu_result[10]);

--S1L888 is std_1c20:inst|cpu:the_cpu|F_pc_plus_one[8]~82

--operation mode is arithmetic

S1L888 = AMPP_FUNCTION(S1_F_pc[8], S1L887);

--S1L889 is std_1c20:inst|cpu:the_cpu|F_pc_plus_one[8]~83

--operation mode is arithmetic

S1L889 = AMPP_FUNCTION(S1_F_pc[8], S1L887);

--DE1_data_to_cpu[10] is std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|data_to_cpu[10]

--operation mode is normal

DE1_data_to_cpu[10]_lut_out = DE1L114 & (DE1_endofpacketvalue_reg[10]) # !DE1L114 & DE1L7;

DE1_data_to_cpu[10] = DFFEAS(DE1_data_to_cpu[10]_lut_out, QC2__clk0, F1_data_out, , , DE1_SSO_reg, , , DE1L115);

--FE1_q_a[10] is std_1c20:inst|epcs_controller:the_epcs_controller|altsyncram:the_boot_copier_rom|altsyncram_3h31:auto_generated|q_a[10]

--RAM Block Operation Mode: ROM

--Port A Depth: 128, Port A Width: 1

--Port A Logical Depth: 128, Port A Logical Width: 32

--Port A Input: Registered, Port A Output: Un-registered

FE1_q_a[10]_PORT_A_address = BUS(X1L14, X1L15, X1L16, X1L17, X1L18, X1L19, X1L20);

FE1_q_a[10]_PORT_A_address_reg = DFFE(FE1_q_a[10]_PORT_A_address, FE1_q_a[10]_clock_0, , , );

FE1_q_a[10]_clock_0 = QC2__clk0;

FE1_q_a[10]_PORT_A_data_out = MEMORY(, , FE1_q_a[10]_PORT_A_address_reg, , , , , , FE1_q_a[10]_clock_0, , , , , );

FE1_q_a[10] = FE1_q_a[10]_PORT_A_data_out[0];

--T1L200 is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata~206

--operation mode is normal

T1L200 = W1L1 & DE1_data_to_cpu[10] # !W1L1 & (FE1_q_a[10]) # !X1_cpu_data_master_requests_epcs_controller_epcs_control_port;

--Z1_readdata[10] is std_1c20:inst|high_res_timer:the_high_res_timer|readdata[10]

--operation mode is normal

Z1_readdata[10]_lut_out = S1_M_alu_result[3] & !S1_M_alu_result[4] & (Z1L179 $ !Z1L180) # !S1_M_alu_result[3] & S1_M_alu_result[4] & Z1L179;

Z1_readdata[10] = DFFEAS(Z1_readdata[10]_lut_out, QC2__clk0, F1_data_out, , , , , , );

--RB1_readdata[10] is std_1c20:inst|sys_clk_timer:the_sys_clk_timer|readdata[10]

--operation mode is normal

RB1_readdata[10]_lut_out = S1_M_alu_result[3] & !S1_M_alu_result[4] & (RB1L180 $ !RB1L181) # !S1_M_alu_result[3] & S1_M_alu_result[4] & RB1L180;

RB1_readdata[10] = DFFEAS(RB1_readdata[10]_lut_out, QC2__clk0, F1_data_out, , , , , , );

--T1L106 is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[10]~5273

--operation mode is normal

T1L106 = Z1_readdata[10] & (RB1_readdata[10] # !SB1_cpu_data_master_requests_sys_clk_timer_s1) # !Z1_readdata[10] & !AB1_cpu_data_master_requests_high_res_timer_s1 & (RB1_readdata[10] # !SB1_cpu_data_master_requests_sys_clk_timer_s1);

--T1_dbs_8_reg_segment_1[2] is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|dbs_8_reg_segment_1[2]

--operation mode is normal

T1_dbs_8_reg_segment_1[2]_lut_out = Y1_internal_incoming_ext_ram_bus_data[2];

T1_dbs_8_reg_segment_1[2] = DFFEAS(T1_dbs_8_reg_segment_1[2]_lut_out, QC2__clk0, F1_data_out, , T1L295, , , , );

--T1_registered_cpu_data_master_readdata[10] is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|registered_cpu_data_master_readdata[10]

--operation mode is normal

T1_registered_cpu_data_master_readdata[10]_lut_out = T1L253 & T1L282 & (KB1_za_data[10] # !NB1L17);

T1_registered_cpu_data_master_readdata[10] = DFFEAS(T1_registered_cpu_data_master_readdata[10]_lut_out, QC2__clk0, F1_data_out, , , , , , );

--T1L107 is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[10]~5274

--operation mode is normal

T1L107 = T1_registered_cpu_data_master_readdata[10] # !K1_cpu_data_master_requests_clock_0_in & (!CB1L2 # !UB1L9);

--Y1_internal_incoming_ext_ram_bus_data[10] is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|internal_incoming_ext_ram_bus_data[10]

--operation mode is normal

Y1_internal_incoming_ext_ram_bus_data[10]_lut_out = A1L106;

Y1_internal_incoming_ext_ram_bus_data[10] = DFFEAS(Y1_internal_incoming_ext_ram_bus_data[10]_lut_out, QC2__clk0, F1_data_out, , , , , , );

--T1L108 is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[10]~5275

--operation mode is normal

T1L108 = T1L208 & (Y1_internal_incoming_ext_ram_bus_data[10] # !Y1L78 & !Y1_cpu_data_master_requests_ext_ram_s1);

--T1L109 is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[10]~5276

--operation mode is normal

T1L109 = T1L108 & (T1_registered_cpu_data_master_readdata[10] # !NB1L17 & !N1_cpu_data_master_requests_clock_1_in);

--T1L110 is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[10]~5277

--operation mode is normal

T1L110 = T1L107 & T1L109 & (T1_dbs_8_reg_segment_1[2] # !Y1_cpu_data_master_requests_ext_flash_s1);

--T1L111 is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[10]~5278

--operation mode is normal

T1L111 = T1L112 & T1L200 & T1L106 & T1L110;

--WC1L11 is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|readdata[10]~1362

--operation mode is normal

WC1L11 = AMPP_FUNCTION(CE1_q_a[10], V1L4, S1_ic_fill_line[5], S1_M_alu_result[10]);

--Y1_internal_incoming_ext_ram_bus_data[26] is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|internal_incoming_ext_ram_bus_data[26]

--operation mode is normal

Y1_internal_incoming_ext_ram_bus_data[26]_lut_out = A1L90;

Y1_internal_incoming_ext_ram_bus_data[26] = DFFEAS(Y1_internal_incoming_ext_ram_bus_data[26]_lut_out, QC2__clk0, F1_data_out, , , , , , );

--T1_registered_cpu_data_master_readdata[26] is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|registered_cpu_data_master_readdata[26]

--operation mode is normal

T1_registered_cpu_data_master_readdata[26]_lut_out = T1L267 & !K1L6 & (!CB1L2 # !UB1L9);

T1_registered_cpu_data_master_readdata[26] = DFFEAS(T1_registered_cpu_data_master_readdata[26]_lut_out, QC2__clk0, F1_data_out, , , , , , );

--T1L179 is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[26]~5279

--operation mode is normal

T1L179 = Y1_internal_incoming_ext_ram_bus_data[2] & (!T1_registered_cpu_data_master_readdata[26] & T1L164) # !Y1_internal_incoming_ext_ram_bus_data[2] & (Y1_cpu_data_master_requests_ext_flash_s1 # !T1_registered_cpu_data_master_readdata[26] & T1L164);

--T1L180 is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[26]~5280

--operation mode is normal

T1L180 = !T1L179 & (Y1_internal_incoming_ext_ram_bus_data[26] # !Y1L78 & !Y1_cpu_data_master_requests_ext_ram_s1);

--FE1_q_a[26] is std_1c20:inst|epcs_controller:the_epcs_controller|altsyncram:the_boot_copier_rom|altsyncram_3h31:auto_generated|q_a[26]

--RAM Block Operation Mode: ROM

--Port A Depth: 128, Port A Width: 1

--Port A Logical Depth: 128, Port A Logical Width: 32

--Port A Input: Registered, Port A Output: Un-registered

FE1_q_a[26]_PORT_A_address = BUS(X1L14, X1L15, X1L16, X1L17, X1L18, X1L19, X1L20);

FE1_q_a[26]_PORT_A_address_reg = DFFE(FE1_q_a[26]_PORT_A_address, FE1_q_a[26]_clock_0, , , );

FE1_q_a[26]_clock_0 = QC2__clk0;

FE1_q_a[26]_PORT_A_data_out = MEMORY(, , FE1_q_a[26]_PORT_A_address_reg, , , , , , FE1_q_a[26]_clock_0, , , , , );

FE1_q_a[26] = FE1_q_a[26]_PORT_A_data_out[0];

--W1L12 is std_1c20:inst|epcs_controller:the_epcs_controller|readdata[26]~702

--operation mode is normal

W1L12 = FE1_q_a[26] & (!W1L1);

--T1L181 is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[26]~5281

--operation mode is normal

T1L181 = T1L178 & T1L180 & (W1L12 # !X1_cpu_data_master_requests_epcs_controller_epcs_control_port);

--WC1L28 is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|readdata[26]~1363

--operation mode is normal

WC1L28 = AMPP_FUNCTION(CE1_q_a[26], V1L4, S1_ic_fill_line[5], S1_M_alu_result[10]);

--S1L886 is std_1c20:inst|cpu:the_cpu|F_pc_plus_one[7]~84

--operation mode is arithmetic

S1L886 = AMPP_FUNCTION(S1_F_pc[7], S1L885);

--S1L887 is std_1c20:inst|cpu:the_cpu|F_pc_plus_one[7]~85

--operation mode is arithmetic

S1L887 = AMPP_FUNCTION(S1_F_pc[7], S1L885);

--DE1_data_to_cpu[9] is std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|data_to_cpu[9]

--operation mode is normal

DE1_data_to_cpu[9]_lut_out = DE1L115 & DE1_iEOP_reg # !DE1L115 & (DE1L8);

DE1_data_to_cpu[9] = DFFEAS(DE1_data_to_cpu[9]_lut_out, QC2__clk0, F1_data_out, , , DE1_EOP, , , DE1L116);

--FE1_q_a[9] is std_1c20:inst|epcs_controller:the_epcs_controller|altsyncram:the_boot_copier_rom|altsyncram_3h31:auto_generated|q_a[9]

--RAM Block Operation Mode: ROM

--Port A Depth: 128, Port A Width: 1

--Port A Logical Depth: 128, Port A Logical Width: 32

--Port A Input: Registered, Port A Output: Un-registered

FE1_q_a[9]_PORT_A_address = BUS(X1L14, X1L15, X1L16, X1L17, X1L18, X1L19, X1L20);

FE1_q_a[9]_PORT_A_address_reg = DFFE(FE1_q_a[9]_PORT_A_address, FE1_q_a[9]_clock_0, , , );

FE1_q_a[9]_clock_0 = QC2__clk0;

FE1_q_a[9]_PORT_A_data_out = MEMORY(, , FE1_q_a[9]_PORT_A_address_reg, , , , , , FE1_q_a[9]_clock_0, , , , , );

FE1_q_a[9] = FE1_q_a[9]_PORT_A_data_out[0];

--T1L199 is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata~205

--operation mode is normal

T1L199 = W1L1 & DE1_data_to_cpu[9] # !W1L1 & (FE1_q_a[9]) # !X1_cpu_data_master_requests_epcs_controller_epcs_control_port;

--XE1_readdata[9] is std_1c20:inst|uart1:the_uart1|uart1_regs:the_uart1_regs|readdata[9]

--operation mode is normal

XE1_readdata[9]_lut_out = S1_M_alu_result[2] & S1_M_alu_result[3] & XE1_control_reg[9] & !S1_M_alu_result[4];

XE1_readdata[9] = DFFEAS(XE1_readdata[9]_lut_out, QC2__clk0, F1_data_out, , , , , , );

--T1L101 is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[9]~5282

--operation mode is normal

T1L101 = T1L100 & (XE1_readdata[9] # !WB1_cpu_data_master_granted_uart1_s1);

--Z1_readdata[9] is std_1c20:inst|high_res_timer:the_high_res_timer|readdata[9]

--operation mode is normal

Z1_readdata[9]_lut_out = S1_M_alu_result[3] & !S1_M_alu_result[4] & (Z1L177 $ !Z1L178) # !S1_M_alu_result[3] & S1_M_alu_result[4] & Z1L177;

Z1_readdata[9] = DFFEAS(Z1_readdata[9]_lut_out, QC2__clk0, F1_data_out, , , , , , );

--RB1_readdata[9] is std_1c20:inst|sys_clk_timer:the_sys_clk_timer|readdata[9]

--operation mode is normal

RB1_readdata[9]_lut_out = S1_M_alu_result[3] & !S1_M_alu_result[4] & (RB1L178 $ !RB1L179) # !S1_M_alu_result[3] & S1_M_alu_result[4] & RB1L178;

RB1_readdata[9] = DFFEAS(RB1_readdata[9]_lut_out, QC2__clk0, F1_data_out, , , , , , );

--T1L102 is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[9]~5283

--operation mode is normal

T1L102 = Z1_readdata[9] & (RB1_readdata[9] # !SB1_cpu_data_master_requests_sys_clk_timer_s1) # !Z1_readdata[9] & !AB1_cpu_data_master_requests_high_res_timer_s1 & (RB1_readdata[9] # !SB1_cpu_data_master_requests_sys_clk_timer_s1);

--Y1_internal_incoming_ext_ram_bus_data[9] is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|internal_incoming_ext_ram_bus_data[9]

--operation mode is normal

Y1_internal_incoming_ext_ram_bus_data[9]_lut_out = A1L107;

Y1_internal_incoming_ext_ram_bus_data[9] = DFFEAS(Y1_internal_incoming_ext_ram_bus_data[9]_lut_out, QC2__clk0, F1_data_out, , , , , , );

--T1_dbs_8_reg_segment_1[1] is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|dbs_8_reg_segment_1[1]

--operation mode is normal

T1_dbs_8_reg_segment_1[1]_lut_out = Y1_internal_incoming_ext_ram_bus_data[1];

T1_dbs_8_reg_segment_1[1] = DFFEAS(T1_dbs_8_reg_segment_1[1]_lut_out, QC2__clk0, F1_data_out, , T1L295, , , , );

--T1_registered_cpu_data_master_readdata[9] is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|registered_cpu_data_master_readdata[9]

--operation mode is normal

T1_registered_cpu_data_master_readdata[9]_lut_out = T1L252 & T1L281 & (KB1_za_data[9] # !NB1L17);

T1_registered_cpu_data_master_readdata[9] = DFFEAS(T1_registered_cpu_data_master_readdata[9]_lut_out, QC2__clk0, F1_data_out, , , , , , );

--T1L103 is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[9]~5284

--operation mode is normal

T1L103 = T1_dbs_8_reg_segment_1[1] & (!T1_registered_cpu_data_master_readdata[9] & T1L164) # !T1_dbs_8_reg_segment_1[1] & (Y1_cpu_data_master_requests_ext_flash_s1 # !T1_registered_cpu_data_master_readdata[9] & T1L164);

--T1L104 is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[9]~5285

--operation mode is normal

T1L104 = !T1L103 & (Y1_internal_incoming_ext_ram_bus_data[9] # !Y1L78 & !Y1_cpu_data_master_requests_ext_ram_s1);

--T1L105 is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[9]~5286

--operation mode is normal

T1L105 = T1L199 & T1L101 & T1L102 & T1L104;

--WC1L10 is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|readdata[9]~1364

--operation mode is normal

WC1L10 = AMPP_FUNCTION(CE1_q_a[9], V1L4, S1_ic_fill_line[5], S1_M_alu_result[10]);

--S1L884 is std_1c20:inst|cpu:the_cpu|F_pc_plus_one[6]~86

--operation mode is arithmetic

S1L884 = AMPP_FUNCTION(S1_F_pc[6], S1L883);

--S1L885 is std_1c20:inst|cpu:the_cpu|F_pc_plus_one[6]~87

--operation mode is arithmetic

S1L885 = AMPP_FUNCTION(S1_F_pc[6], S1L883);

--Z1_readdata[8] is std_1c20:inst|high_res_timer:the_high_res_timer|readdata[8]

--operation mode is normal

Z1_readdata[8]_lut_out = S1_M_alu_result[3] & !S1_M_alu_result[4] & (Z1L175 $ !Z1L176) # !S1_M_alu_result[3] & S1_M_alu_result[4] & Z1L175;

Z1_readdata[8] = DFFEAS(Z1_readdata[8]_lut_out, QC2__clk0, F1_data_out, , , , , , );

--XE1_readdata[8] is std_1c20:inst|uart1:the_uart1|uart1_regs:the_uart1_regs|readdata[8]

--operation mode is normal

XE1_readdata[8]_lut_out = XE1L22 & (S1_M_alu_result[2] & XE1_control_reg[8] # !S1_M_alu_result[2] & (XE1L1));

XE1_readdata[8] = DFFEAS(XE1_readdata[8]_lut_out, QC2__clk0, F1_data_out, , , , , , );

--T1L92 is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[8]~5287

--operation mode is normal

T1L92 = Z1_readdata[8] & (XE1_readdata[8] # !WB1_cpu_data_master_granted_uart1_s1) # !Z1_readdata[8] & !AB1_cpu_data_master_requests_high_res_timer_s1 & (XE1_readdata[8] # !WB1_cpu_data_master_granted_uart1_s1);

--T1_registered_cpu_data_master_readdata[8] is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|registered_cpu_data_master_readdata[8]

--operation mode is normal

T1_registered_cpu_data_master_readdata[8]_lut_out = T1L251 & T1L288 & (KB1_za_data[8] # !NB1L17);

T1_registered_cpu_data_master_readdata[8] = DFFEAS(T1_registered_cpu_data_master_readdata[8]_lut_out, QC2__clk0, F1_data_out, , , , , , );

--T1L93 is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[8]~5288

--operation mode is normal

T1L93 = T1_registered_cpu_data_master_readdata[8] # !K1_cpu_data_master_requests_clock_0_in & (!CB1L2 # !UB1L9);

--RB1_readdata[8] is std_1c20:inst|sys_clk_timer:the_sys_clk_timer|readdata[8]

--operation mode is normal

RB1_readdata[8]_lut_out = S1_M_alu_result[3] & !S1_M_alu_result[4] & (RB1L176 $ !RB1L177) # !S1_M_alu_result[3] & S1_M_alu_result[4] & RB1L176;

RB1_readdata[8] = DFFEAS(RB1_readdata[8]_lut_out, QC2__clk0, F1_data_out, , , , , , );

--T1L94 is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[8]~5289

--operation mode is normal

T1L94 = T1L93 & (RB1_readdata[8] # !SB1_cpu_data_master_requests_sys_clk_timer_s1);

--Y1_internal_incoming_ext_ram_bus_data[8] is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|internal_incoming_ext_ram_bus_data[8]

--operation mode is normal

Y1_internal_incoming_ext_ram_bus_data[8]_lut_out = A1L108;

Y1_internal_incoming_ext_ram_bus_data[8] = DFFEAS(Y1_internal_incoming_ext_ram_bus_data[8]_lut_out, QC2__clk0, F1_data_out, , , , , , );

--T1_dbs_8_reg_segment_1[0] is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|dbs_8_reg_segment_1[0]

--operation mode is normal

T1_dbs_8_reg_segment_1[0]_lut_out = Y1_internal_incoming_ext_ram_bus_data[0];

T1_dbs_8_reg_segment_1[0] = DFFEAS(T1_dbs_8_reg_segment_1[0]_lut_out, QC2__clk0, F1_data_out, , T1L295, , , , );

--T1L95 is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[8]~5290

--operation mode is normal

T1L95 = T1_dbs_8_reg_segment_1[0] & (!T1_registered_cpu_data_master_readdata[8] & NB1L17) # !T1_dbs_8_reg_segment_1[0] & (Y1_cpu_data_master_requests_ext_flash_s1 # !T1_registered_cpu_data_master_readdata[8] & NB1L17);

--T1L96 is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[8]~5291

--operation mode is normal

T1L96 = !T1L95 & (Y1_internal_incoming_ext_ram_bus_data[8] # !Y1L78 & !Y1_cpu_data_master_requests_ext_ram_s1);

--T1L97 is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[8]~5292

--operation mode is normal

T1L97 = T1L96 & !EB1L12 & (T1_registered_cpu_data_master_readdata[8] # !N1_cpu_data_master_requests_clock_1_in);

--T1L98 is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[8]~5293

--operation mode is normal

T1L98 = T1L75 & T1L92 & T1L94 & T1L97;

--DE1_data_to_cpu[8] is std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|data_to_cpu[8]

--operation mode is normal

DE1_data_to_cpu[8]_lut_out = DE1L115 & DE1_iE_reg # !DE1L115 & (DE1L9);

DE1_data_to_cpu[8] = DFFEAS(DE1_data_to_cpu[8]_lut_out, QC2__clk0, F1_data_out, , , DE1_E, , , DE1L116);

--FE1_q_a[8] is std_1c20:inst|epcs_controller:the_epcs_controller|altsyncram:the_boot_copier_rom|altsyncram_3h31:auto_generated|q_a[8]

--RAM Block Operation Mode: ROM

--Port A Depth: 128, Port A Width: 1

--Port A Logical Depth: 128, Port A Logical Width: 32

--Port A Input: Registered, Port A Output: Un-registered

FE1_q_a[8]_PORT_A_address = BUS(X1L14, X1L15, X1L16, X1L17, X1L18, X1L19, X1L20);

FE1_q_a[8]_PORT_A_address_reg = DFFE(FE1_q_a[8]_PORT_A_address, FE1_q_a[8]_clock_0, , , );

FE1_q_a[8]_clock_0 = QC2__clk0;

FE1_q_a[8]_PORT_A_data_out = MEMORY(, , FE1_q_a[8]_PORT_A_address_reg, , , , , , FE1_q_a[8]_clock_0, , , , , );

FE1_q_a[8] = FE1_q_a[8]_PORT_A_data_out[0];

--U1L119 is std_1c20:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_readdata~2404

--operation mode is normal

U1L119 = W1L1 & DE1_data_to_cpu[8] # !W1L1 & (FE1_q_a[8]);

--T1L99 is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[8]~5294

--operation mode is normal

T1L99 = T1L98 & (U1L119 # !X1_cpu_data_master_requests_epcs_controller_epcs_control_port);

--WC1L9 is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|readdata[8]~1365

--operation mode is normal

WC1L9 = AMPP_FUNCTION(CE1_q_a[8], V1L4, S1_ic_fill_line[5], S1_M_alu_result[10]);

--S1L882 is std_1c20:inst|cpu:the_cpu|F_pc_plus_one[5]~88

--operation mode is arithmetic

S1L882 = AMPP_FUNCTION(S1_F_pc[5], S1L881);

--S1L883 is std_1c20:inst|cpu:the_cpu|F_pc_plus_one[5]~89

--operation mode is arithmetic

S1L883 = AMPP_FUNCTION(S1_F_pc[5], S1L881);

--DD1_q_b[7] is std_1c20:inst|cpu:the_cpu|cpu_register_bank_b_module:cpu_register_bank_b|altsyncram:the_altsyncram|altsyncram_4vd1:auto_generated|q_b[7]

--RAM Block Operation Mode: Simple Dual-Port

--Port A Depth: 32, Port A Width: 1, Port B Depth: 32, Port B Width: 1

--Port A Logical Depth: 32, Port A Logical Width: 32, Port B Logical Depth: 32, Port B Logical Width: 32

--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered

DD1_q_b[7] = AMPP_FUNCTION(GND, GND, QC2__clk0, QC2__clk0, !S1_M_wr_dst_reg, S1_W_stall, S1L1303, S1_M_dst_regnum[0], S1_M_dst_regnum[1], S1_M_dst_regnum[2], S1_M_dst_regnum[3], S1_M_dst_regnum[4], AD1_q_b[22], AD1_q_b[23], AD1_q_b[24], AD1_q_b[25], AD1_q_b[26]);

--Y1_d1_irq_from_the_lan91c111 is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_irq_from_the_lan91c111

--operation mode is normal

Y1_d1_irq_from_the_lan91c111_lut_out = irq_from_the_lan91c111;

Y1_d1_irq_from_the_lan91c111 = DFFEAS(Y1_d1_irq_from_the_lan91c111_lut_out, QC2__clk0, F1_data_out, , , , , , );

--FD1_internal_oci_ienable1[6] is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_avalon_reg:the_cpu_nios2_avalon_reg|internal_oci_ienable1[6]

--operation mode is normal

FD1_internal_oci_ienable1[6] = AMPP_FUNCTION(QC2__clk0, S1_M_st_data[6], F1_data_out, FD1L13);

--RB1_readdata[6] is std_1c20:inst|sys_clk_timer:the_sys_clk_timer|readdata[6]

--operation mode is normal

RB1_readdata[6]_lut_out = S1_M_alu_result[3] & !S1_M_alu_result[4] & (RB1L172 $ !RB1L173) # !S1_M_alu_result[3] & S1_M_alu_result[4] & RB1L172;

RB1_readdata[6] = DFFEAS(RB1_readdata[6]_lut_out, QC2__clk0, F1_data_out, , , , , , );

--T1L77 is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[6]~5295

--operation mode is normal

T1L77 = T1L59 & (RB1_readdata[6] # !SB1_cpu_data_master_requests_sys_clk_timer_s1);

--Z1_readdata[6] is std_1c20:inst|high_res_timer:the_high_res_timer|readdata[6]

--operation mode is normal

Z1_readdata[6]_lut_out = S1_M_alu_result[3] & !S1_M_alu_result[4] & (Z1L171 $ !Z1L172) # !S1_M_alu_result[3] & S1_M_alu_result[4] & Z1L171;

Z1_readdata[6] = DFFEAS(Z1_readdata[6]_lut_out, QC2__clk0, F1_data_out, , , , , , );

--XE1_readdata[6] is std_1c20:inst|uart1:the_uart1|uart1_regs:the_uart1_regs|readdata[6]

--operation mode is normal

XE1_readdata[6]_lut_out = !S1_M_alu_result[4] & (S1_M_alu_result[2] & XE1L60 # !S1_M_alu_result[2] & (XE1L61));

XE1_readdata[6] = DFFEAS(XE1_readdata[6]_lut_out, QC2__clk0, F1_data_out, , , , , , );

--T1L78 is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[6]~5296

--operation mode is normal

T1L78 = Z1_readdata[6] & (XE1_readdata[6] # !WB1_cpu_data_master_granted_uart1_s1) # !Z1_readdata[6] & !AB1_cpu_data_master_requests_high_res_timer_s1 & (XE1_readdata[6] # !WB1_cpu_data_master_granted_uart1_s1);

--T1_registered_cpu_data_master_readdata[6] is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|registered_cpu_data_master_readdata[6]

--operation mode is normal

T1_registered_cpu_data_master_readdata[6]_lut_out = T1L249 & T1L279 & (KB1_za_data[6] # !NB1L17);

T1_registered_cpu_data_master_readdata[6] = DFFEAS(T1_registered_cpu_data_master_readdata[6]_lut_out, QC2__clk0, F1_data_out, , , , , , );

--T1L79 is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[6]~5297

--operation mode is normal

T1L79 = T1_registered_cpu_data_master_readdata[6] # !K1_cpu_data_master_requests_clock_0_in & (!CB1L2 # !UB1L9);

--T1_dbs_8_reg_segment_0[6] is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|dbs_8_reg_segment_0[6]

--operation mode is normal

T1_dbs_8_reg_segment_0[6]_lut_out = Y1_internal_incoming_ext_ram_bus_data[6];

T1_dbs_8_reg_segment_0[6] = DFFEAS(T1_dbs_8_reg_segment_0[6]_lut_out, QC2__clk0, F1_data_out, , T1L294, , , , );

--T1L80 is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[6]~5298

--operation mode is normal

T1L80 = T1_dbs_8_reg_segment_0[6] & (!A1L135 & EB1L12) # !T1_dbs_8_reg_segment_0[6] & (Y1_cpu_data_master_requests_ext_flash_s1 # !A1L135 & EB1L12);

--T1L81 is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[6]~5299

--operation mode is normal

T1L81 = T1L80 # !T1_registered_cpu_data_master_readdata[6] & (NB1L17 # N1_cpu_data_master_requests_clock_1_in);

--T1L82 is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[6]~5300

--operation mode is normal

T1L82 = !T1L81 & (Y1_internal_incoming_ext_ram_bus_data[6] # !Y1L78 & !Y1_cpu_data_master_requests_ext_ram_s1);

--T1L83 is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[6]~5301

--operation mode is normal

T1L83 = T1L77 & T1L78 & T1L79 & T1L82;

--DE1_data_to_cpu[6] is std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|data_to_cpu[6]

--operation mode is normal

DE1_data_to_cpu[6]_lut_out = DE1L115 & DE1_iTRDY_reg # !DE1L115 & (DE1L12);

DE1_data_to_cpu[6] = DFFEAS(DE1_data_to_cpu[6]_lut_out, QC2__clk0, F1_data_out, , , DE1L193, , , DE1L116);

--FE1_q_a[6] is std_1c20:inst|epcs_controller:the_epcs_controller|altsyncram:the_boot_copier_rom|altsyncram_3h31:auto_generated|q_a[6]

--RAM Block Operation Mode: ROM

--Port A Depth: 128, Port A Width: 1

--Port A Logical Depth: 128, Port A Logical Width: 32

--Port A Input: Registered, Port A Output: Un-registered

FE1_q_a[6]_PORT_A_address = BUS(X1L14, X1L15, X1L16, X1L17, X1L18, X1L19, X1L20);

FE1_q_a[6]_PORT_A_address_reg = DFFE(FE1_q_a[6]_PORT_A_address, FE1_q_a[6]_clock_0, , , );

FE1_q_a[6]_clock_0 = QC2__clk0;

FE1_q_a[6]_PORT_A_data_out = MEMORY(, , FE1_q_a[6]_PORT_A_address_reg, , , , , , FE1_q_a[6]_clock_0, , , , , );

FE1_q_a[6] = FE1_q_a[6]_PORT_A_data_out[0];

--U1L120 is std_1c20:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_readdata~2405

--operation mode is normal

U1L120 = W1L1 & DE1_data_to_cpu[6] # !W1L1 & (FE1_q_a[6]);

--WC1L7 is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|readdata[6]~1366

--operation mode is normal

WC1L7 = AMPP_FUNCTION(CE1_q_a[6], V1L4, S1_ic_fill_line[5], S1_M_alu_result[10]);

--DD1_q_b[6] is std_1c20:inst|cpu:the_cpu|cpu_register_bank_b_module:cpu_register_bank_b|altsyncram:the_altsyncram|altsyncram_4vd1:auto_generated|q_b[6]

--RAM Block Operation Mode: Simple Dual-Port

--Port A Depth: 32, Port A Width: 1, Port B Depth: 32, Port B Width: 1

--Port A Logical Depth: 32, Port A Logical Width: 32, Port B Logical Depth: 32, Port B Logical Width: 32

--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered

DD1_q_b[6] = AMPP_FUNCTION(GND, GND, QC2__clk0, QC2__clk0, !S1_M_wr_dst_reg, S1_W_stall, S1L1300, S1_M_dst_regnum[0], S1_M_dst_regnum[1], S1_M_dst_regnum[2], S1_M_dst_regnum[3], S1_M_dst_regnum[4], AD1_q_b[22], AD1_q_b[23], AD1_q_b[24], AD1_q_b[25], AD1_q_b[26]);

--S1L880 is std_1c20:inst|cpu:the_cpu|F_pc_plus_one[4]~90

--operation mode is arithmetic

S1L880 = AMPP_FUNCTION(S1_F_pc[4], S1L879);

--S1L881 is std_1c20:inst|cpu:the_cpu|F_pc_plus_one[4]~91

--operation mode is arithmetic

S1L881 = AMPP_FUNCTION(S1_F_pc[4], S1L879);

--XE1_irq is std_1c20:inst|uart1:the_uart1|uart1_regs:the_uart1_regs|irq

--operation mode is normal

XE1_irq_lut_out = XE1L36 # XE1L37 # YE1_internal_rx_char_ready & XE1_control_reg[7];

XE1_irq = DFFEAS(XE1_irq_lut_out, QC2__clk0, F1_data_out, , , , , , );

--FD1_internal_oci_ienable1[4] is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_avalon_reg:the_cpu_nios2_avalon_reg|internal_oci_ienable1[4]

--operation mode is normal

FD1_internal_oci_ienable1[4] = AMPP_FUNCTION(QC2__clk0, S1_M_st_data[4], F1_data_out, FD1L13);

--Z1_readdata[4] is std_1c20:inst|high_res_timer:the_high_res_timer|readdata[4]

--operation mode is normal

Z1_readdata[4]_lut_out = S1_M_alu_result[3] & !S1_M_alu_result[4] & (Z1L167 $ !Z1L168) # !S1_M_alu_result[3] & S1_M_alu_result[4] & Z1L167;

Z1_readdata[4] = DFFEAS(Z1_readdata[4]_lut_out, QC2__clk0, F1_data_out, , , , , , );

--T1L60 is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[4]~5303

--operation mode is normal

T1L60 = T1L59 & (Z1_readdata[4] # !AB1_cpu_data_master_requests_high_res_timer_s1);

--XE1_readdata[4] is std_1c20:inst|uart1:the_uart1|uart1_regs:the_uart1_regs|readdata[4]

--operation mode is normal

XE1_readdata[4]_lut_out = !S1_M_alu_result[4] & (S1_M_alu_result[2] & XE1L56 # !S1_M_alu_result[2] & (XE1L57));

XE1_readdata[4] = DFFEAS(XE1_readdata[4]_lut_out, QC2__clk0, F1_data_out, , , , , , );

--RB1_readdata[4] is std_1c20:inst|sys_clk_timer:the_sys_clk_timer|readdata[4]

--operation mode is normal

RB1_readdata[4]_lut_out = S1_M_alu_result[3] & !S1_M_alu_result[4] & (RB1L168 $ !RB1L169) # !S1_M_alu_result[3] & S1_M_alu_result[4] & RB1L168;

RB1_readdata[4] = DFFEAS(RB1_readdata[4]_lut_out, QC2__clk0, F1_data_out, , , , , , );

--T1L61 is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[4]~5304

--operation mode is normal

T1L61 = S1_M_alu_result[6] & XE1_readdata[4] # !S1_M_alu_result[6] & (RB1_readdata[4]) # !SB1L3;

--T1_registered_cpu_data_master_readdata[4] is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|registered_cpu_data_master_readdata[4]

--operation mode is normal

T1_registered_cpu_data_master_readdata[4]_lut_out = T1L247 & T1L277 & (KB1_za_data[4] # !NB1L17);

T1_registered_cpu_data_master_readdata[4] = DFFEAS(T1_registered_cpu_data_master_readdata[4]_lut_out, QC2__clk0, F1_data_out, , , , , , );

--T1L62 is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[4]~5305

--operation mode is normal

T1L62 = T1_registered_cpu_data_master_readdata[4] # !N1_cpu_data_master_requests_clock_1_in & (!CB1L2 # !UB1L9);

--T1L63 is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[4]~5306

--operation mode is normal

T1L63 = T1L208 & (Y1_internal_incoming_ext_ram_bus_data[4] # !Y1L78 & !Y1_cpu_data_master_requests_ext_ram_s1);

--T1_dbs_8_reg_segment_0[4] is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|dbs_8_reg_segment_0[4]

--operation mode is normal

T1_dbs_8_reg_segment_0[4]_lut_out = Y1_internal_incoming_ext_ram_bus_data[4];

T1_dbs_8_reg_segment_0[4] = DFFEAS(T1_dbs_8_reg_segment_0[4]_lut_out, QC2__clk0, F1_data_out, , T1L294, , , , );

--T1L64 is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[4]~5307

--operation mode is normal

T1L64 = T1L62 & T1L63 & (T1_dbs_8_reg_segment_0[4] # !Y1_cpu_data_master_requests_ext_flash_s1);

--T1L207 is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata~568

--operation mode is normal

T1L207 = S1_M_alu_result[5] # A1L137 # !JB1L3;

--T1L65 is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[4]~5308

--operation mode is normal

T1L65 = T1L207 & (T1_registered_cpu_data_master_readdata[4] # !NB1L17 & !K1_cpu_data_master_requests_clock_0_in);

--T1L66 is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[4]~5309

--operation mode is normal

T1L66 = T1L60 & T1L61 & T1L64 & T1L65;

--DE1_data_to_cpu[4] is std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|data_to_cpu[4]

--operation mode is normal

DE1_data_to_cpu[4]_lut_out = DE1L115 & DE1_iTOE_reg # !DE1L115 & (DE1L15);

DE1_data_to_cpu[4] = DFFEAS(DE1_data_to_cpu[4]_lut_out, QC2__clk0, F1_data_out, , , DE1_TOE, , , DE1L116);

--FE1_q_a[4] is std_1c20:inst|epcs_controller:the_epcs_controller|altsyncram:the_boot_copier_rom|altsyncram_3h31:auto_generated|q_a[4]

--RAM Block Operation Mode: ROM

--Port A Depth: 128, Port A Width: 1

--Port A Logical Depth: 128, Port A Logical Width: 32

--Port A Input: Registered, Port A Output: Un-registered

FE1_q_a[4]_PORT_A_address = BUS(X1L14, X1L15, X1L16, X1L17, X1L18, X1L19, X1L20);

FE1_q_a[4]_PORT_A_address_reg = DFFE(FE1_q_a[4]_PORT_A_address, FE1_q_a[4]_clock_0, , , );

FE1_q_a[4]_clock_0 = QC2__clk0;

FE1_q_a[4]_PORT_A_data_out = MEMORY(, , FE1_q_a[4]_PORT_A_address_reg, , , , , , FE1_q_a[4]_clock_0, , , , , );

FE1_q_a[4] = FE1_q_a[4]_PORT_A_data_out[0];

--U1L121 is std_1c20:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_readdata~2406

--operation mode is normal

U1L121 = W1L1 & DE1_data_to_cpu[4] # !W1L1 & (FE1_q_a[4]);

--WC1L5 is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|readdata[4]~1367

--operation mode is normal

WC1L5 = AMPP_FUNCTION(CE1_q_a[4], V1L4, S1_ic_fill_line[5], S1_M_alu_result[10]);

--DD1_q_b[4] is std_1c20:inst|cpu:the_cpu|cpu_register_bank_b_module:cpu_register_bank_b|altsyncram:the_altsyncram|altsyncram_4vd1:auto_generated|q_b[4]

--RAM Block Operation Mode: Simple Dual-Port

--Port A Depth: 32, Port A Width: 1, Port B Depth: 32, Port B Width: 1

--Port A Logical Depth: 32, Port A Logical Width: 32, Port B Logical Depth: 32, Port B Logical Width: 32

--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered

DD1_q_b[4] = AMPP_FUNCTION(GND, GND, QC2__clk0, QC2__clk0, !S1_M_wr_dst_reg, S1_W_stall, S1L1294, S1_M_dst_regnum[0], S1_M_dst_regnum[1], S1_M_dst_regnum[2], S1_M_dst_regnum[3], S1_M_dst_regnum[4], AD1_q_b[22], AD1_q_b[23], AD1_q_b[24], AD1_q_b[25], AD1_q_b[26]);

--S1L876 is std_1c20:inst|cpu:the_cpu|F_pc_plus_one[2]~92

--operation mode is arithmetic

S1L876 = AMPP_FUNCTION(S1_F_pc[2], S1L875);

--S1L877 is std_1c20:inst|cpu:the_cpu|F_pc_plus_one[2]~93

--operation mode is arithmetic

S1L877 = AMPP_FUNCTION(S1_F_pc[2], S1L875);

--DE1_irq_reg is std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|irq_reg

--operation mode is normal

DE1_irq_reg_lut_out = DE1L124 # DE1L125 # DE1_iROE_reg & DE1_ROE;

DE1_irq_reg = DFFEAS(DE1_irq_reg_lut_out, QC2__clk0, F1_data_out, , , , , , );

--FD1_internal_oci_ienable1[5] is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_avalon_reg:the_cpu_nios2_avalon_reg|internal_oci_ienable1[5]

--operation mode is normal

FD1_internal_oci_ienable1[5] = AMPP_FUNCTION(QC2__clk0, S1_M_st_data[5], F1_data_out, FD1L13);

--Z1_readdata[5] is std_1c20:inst|high_res_timer:the_high_res_timer|readdata[5]

--operation mode is normal

Z1_readdata[5]_lut_out = S1_M_alu_result[3] & !S1_M_alu_result[4] & (Z1L169 $ !Z1L170) # !S1_M_alu_result[3] & S1_M_alu_result[4] & Z1L169;

Z1_readdata[5] = DFFEAS(Z1_readdata[5]_lut_out, QC2__clk0, F1_data_out, , , , , , );

--XE1_readdata[5] is std_1c20:inst|uart1:the_uart1|uart1_regs:the_uart1_regs|readdata[5]

--operation mode is normal

XE1_readdata[5]_lut_out = !S1_M_alu_result[4] & (S1_M_alu_result[2] & XE1L58 # !S1_M_alu_result[2] & (XE1L59));

XE1_readdata[5] = DFFEAS(XE1_readdata[5]_lut_out, QC2__clk0, F1_data_out, , , , , , );

--T1L68 is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[5]~5311

--operation mode is normal

T1L68 = Z1_readdata[5] & (XE1_readdata[5] # !WB1_cpu_data_master_granted_uart1_s1) # !Z1_readdata[5] & !AB1_cpu_data_master_requests_high_res_timer_s1 & (XE1_readdata[5] # !WB1_cpu_data_master_granted_uart1_s1);

--T1_registered_cpu_data_master_readdata[5] is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|registered_cpu_data_master_readdata[5]

--operation mode is normal

T1_registered_cpu_data_master_readdata[5]_lut_out = T1L248 & T1L278 & (KB1_za_data[5] # !NB1L17);

T1_registered_cpu_data_master_readdata[5] = DFFEAS(T1_registered_cpu_data_master_readdata[5]_lut_out, QC2__clk0, F1_data_out, , , , , , );

--T1L69 is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[5]~5312

--operation mode is normal

T1L69 = T1_registered_cpu_data_master_readdata[5] # !K1_cpu_data_master_requests_clock_0_in & (!CB1L2 # !UB1L9);

--RB1_readdata[5] is std_1c20:inst|sys_clk_timer:the_sys_clk_timer|readdata[5]

--operation mode is normal

RB1_readdata[5]_lut_out = S1_M_alu_result[3] & !S1_M_alu_result[4] & (RB1L170 $ !RB1L171) # !S1_M_alu_result[3] & S1_M_alu_result[4] & RB1L170;

RB1_readdata[5] = DFFEAS(RB1_readdata[5]_lut_out, QC2__clk0, F1_data_out, , , , , , );

--T1L70 is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[5]~5313

--operation mode is normal

T1L70 = T1L69 & (RB1_readdata[5] # !SB1_cpu_data_master_requests_sys_clk_timer_s1);

--T1_dbs_8_reg_segment_0[5] is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|dbs_8_reg_segment_0[5]

--operation mode is normal

T1_dbs_8_reg_segment_0[5]_lut_out = Y1_internal_incoming_ext_ram_bus_data[5];

T1_dbs_8_reg_segment_0[5] = DFFEAS(T1_dbs_8_reg_segment_0[5]_lut_out, QC2__clk0, F1_data_out, , T1L294, , , , );

--T1L71 is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[5]~5314

--operation mode is normal

T1L71 = T1_dbs_8_reg_segment_0[5] & (!A1L136 & EB1L12) # !T1_dbs_8_reg_segment_0[5] & (Y1_cpu_data_master_requests_ext_flash_s1 # !A1L136 & EB1L12);

--T1L72 is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[5]~5315

--operation mode is normal

T1L72 = T1L71 # !T1_registered_cpu_data_master_readdata[5] & (NB1L17 # N1_cpu_data_master_requests_clock_1_in);

--T1L73 is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[5]~5316

--operation mode is normal

T1L73 = !T1L72 & (Y1_internal_incoming_ext_ram_bus_data[5] # !Y1L78 & !Y1_cpu_data_master_requests_ext_ram_s1);

--T1L74 is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[5]~5317

--operation mode is normal

T1L74 = T1L75 & T1L68 & T1L70 & T1L73;

--DE1_data_to_cpu[5] is std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|data_to_cpu[5]

--operation mode is normal

DE1_data_to_cpu[5]_lut_out = DE1L134 & (DE1L192 & !X1L14) # !DE1L134 & DE1L137;

DE1_data_to_cpu[5] = DFFEAS(DE1_data_to_cpu[5]_lut_out, QC2__clk0, F1_data_out, , , , , , );

--FE1_q_a[5] is std_1c20:inst|epcs_controller:the_epcs_controller|altsyncram:the_boot_copier_rom|altsyncram_3h31:auto_generated|q_a[5]

--RAM Block Operation Mode: ROM

--Port A Depth: 128, Port A Width: 1

--Port A Logical Depth: 128, Port A Logical Width: 32

--Port A Input: Registered, Port A Output: Un-registered

FE1_q_a[5]_PORT_A_address = BUS(X1L14, X1L15, X1L16, X1L17, X1L18, X1L19, X1L20);

FE1_q_a[5]_PORT_A_address_reg = DFFE(FE1_q_a[5]_PORT_A_address, FE1_q_a[5]_clock_0, , , );

FE1_q_a[5]_clock_0 = QC2__clk0;

FE1_q_a[5]_PORT_A_data_out = MEMORY(, , FE1_q_a[5]_PORT_A_address_reg, , , , , , FE1_q_a[5]_clock_0, , , , , );

FE1_q_a[5] = FE1_q_a[5]_PORT_A_data_out[0];

--U1L122 is std_1c20:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_readdata~2407

--operation mode is normal

U1L122 = W1L1 & DE1_data_to_cpu[5] # !W1L1 & (FE1_q_a[5]);

--WC1L6 is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|readdata[5]~1368

--operation mode is normal

WC1L6 = AMPP_FUNCTION(CE1_q_a[5], V1L4, S1_ic_fill_line[5], S1_M_alu_result[10]);

--DD1_q_b[5] is std_1c20:inst|cpu:the_cpu|cpu_register_bank_b_module:cpu_register_bank_b|altsyncram:the_altsyncram|altsyncram_4vd1:auto_generated|q_b[5]

--RAM Block Operation Mode: Simple Dual-Port

--Port A Depth: 32, Port A Width: 1, Port B Depth: 32, Port B Width: 1

--Port A Logical Depth: 32, Port A Logical Width: 32, Port B Logical Depth: 32, Port B Logical Width: 32

--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered

DD1_q_b[5] = AMPP_FUNCTION(GND, GND, QC2__clk0, QC2__clk0, !S1_M_wr_dst_reg, S1_W_stall, S1L1297, S1_M_dst_regnum[0], S1_M_dst_regnum[1], S1_M_dst_regnum[2], S1_M_dst_regnum[3], S1_M_dst_regnum[4], AD1_q_b[22], AD1_q_b[23], AD1_q_b[24], AD1_q_b[25], AD1_q_b[26]);

--S1L878 is std_1c20:inst|cpu:the_cpu|F_pc_plus_one[3]~94

--operation mode is arithmetic

S1L878 = AMPP_FUNCTION(S1_F_pc[3], S1L877);

--S1L879 is std_1c20:inst|cpu:the_cpu|F_pc_plus_one[3]~95

--operation mode is arithmetic

S1L879 = AMPP_FUNCTION(S1_F_pc[3], S1L877);

--CD1_q_b[0] is std_1c20:inst|cpu:the_cpu|cpu_register_bank_a_module:cpu_register_bank_a|altsyncram:the_altsyncram|altsyncram_3vd1:auto_generated|q_b[0]

--RAM Block Operation Mode: Simple Dual-Port

--Port A Depth: 32, Port A Width: 1, Port B Depth: 32, Port B Width: 1

--Port A Logical Depth: 32, Port A Logical Width: 32, Port B Logical Depth: 32, Port B Logical Width: 32

--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered

CD1_q_b[0] = AMPP_FUNCTION(GND, GND, QC2__clk0, QC2__clk0, !S1_M_wr_dst_reg, S1_W_stall, S1L1282, S1_M_dst_regnum[0], S1_M_dst_regnum[1], S1_M_dst_regnum[2], S1_M_dst_regnum[3], S1_M_dst_regnum[4], AD1_q_b[27], AD1_q_b[28], AD1_q_b[29], AD1_q_b[30], AD1_q_b[31]);

--S1_W_wr_data[0] is std_1c20:inst|cpu:the_cpu|W_wr_data[0]

--operation mode is normal

S1_W_wr_data[0] = AMPP_FUNCTION(QC2__clk0, S1L1282, F1_data_out, S1_W_stall);

--S1_M_shift_rot_result[31] is std_1c20:inst|cpu:the_cpu|M_shift_rot_result[31]

--operation mode is normal

S1_M_shift_rot_result[31] = AMPP_FUNCTION(QC2__clk0, S1_M_shift_rot_result[30], S1L1185, S1L600, S1_M_ctrl_shift_rot_right, F1_data_out, !S1_M_shift_rot_stall);

--S1_M_ctrl_rot_right is std_1c20:inst|cpu:the_cpu|M_ctrl_rot_right

--operation mode is normal

S1_M_ctrl_rot_right = AMPP_FUNCTION(QC2__clk0, S1_E_ctrl_rot_right, F1_data_out, S1_W_stall);

--S1_M_ctrl_shift_logical is std_1c20:inst|cpu:the_cpu|M_ctrl_shift_logical

--operation mode is normal

S1_M_ctrl_shift_logical = AMPP_FUNCTION(QC2__clk0, S1_E_ctrl_shift_logical, F1_data_out, S1_W_stall);

--S1L1185 is std_1c20:inst|cpu:the_cpu|M_shift_rot_fill_bit~45

--operation mode is normal

S1L1185 = AMPP_FUNCTION(S1_M_shift_rot_result[0], S1_M_shift_rot_result[31], S1_M_ctrl_rot_right, S1_M_ctrl_shift_logical);

--S1L338Q is std_1c20:inst|cpu:the_cpu|d_readdata_d1[0]~95

--operation mode is normal

S1L338Q = AMPP_FUNCTION(QC2__clk0, T1L30, U1L123, X1_cpu_data_master_requests_epcs_controller_epcs_control_port, F1_data_out);

--S1L929Q is std_1c20:inst|cpu:the_cpu|i_readdata_d1[0]~91

--operation mode is normal

S1L929Q = AMPP_FUNCTION(QC2__clk0, WC1L1, WC1L19, FD1L3, FD1_internal_oci_ienable1[0], F1_data_out);

--T1_cpu_data_master_readdata[0] is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[0]

--operation mode is normal

T1_cpu_data_master_readdata[0] = S1L338Q & (S1L339Q # S1L929Q);

--CD1_q_b[1] is std_1c20:inst|cpu:the_cpu|cpu_register_bank_a_module:cpu_register_bank_a|altsyncram:the_altsyncram|altsyncram_3vd1:auto_generated|q_b[1]

--RAM Block Operation Mode: Simple Dual-Port

--Port A Depth: 32, Port A Width: 1, Port B Depth: 32, Port B Width: 1

--Port A Logical Depth: 32, Port A Logical Width: 32, Port B Logical Depth: 32, Port B Logical Width: 32

--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered

CD1_q_b[1] = AMPP_FUNCTION(GND, GND, QC2__clk0, QC2__clk0, !S1_M_wr_dst_reg, S1_W_stall, S1L1285, S1_M_dst_regnum[0], S1_M_dst_regnum[1], S1_M_dst_regnum[2], S1_M_dst_regnum[3], S1_M_dst_regnum[4], AD1_q_b[27], AD1_q_b[28], AD1_q_b[29], AD1_q_b[30], AD1_q_b[31]);

--S1_W_wr_data[1] is std_1c20:inst|cpu:the_cpu|W_wr_data[1]

--operation mode is normal

S1_W_wr_data[1] = AMPP_FUNCTION(QC2__clk0, S1L1285, F1_data_out, S1_W_stall);

--S1L340Q is std_1c20:inst|cpu:the_cpu|d_readdata_d1[1]~94

--operation mode is normal

S1L340Q = AMPP_FUNCTION(QC2__clk0, T1L38, U1L124, X1_cpu_data_master_requests_epcs_controller_epcs_control_port, F1_data_out);

--S1L931Q is std_1c20:inst|cpu:the_cpu|i_readdata_d1[1]~93

--operation mode is normal

S1L931Q = AMPP_FUNCTION(QC2__clk0, WC1L2, WC1L19, FD1L3, FD1_internal_oci_ienable1[1], F1_data_out);

--T1_cpu_data_master_readdata[1] is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[1]

--operation mode is normal

T1_cpu_data_master_readdata[1] = S1L340Q & (S1L339Q # S1L931Q);

--S1_D_pc[9] is std_1c20:inst|cpu:the_cpu|D_pc[9]

--operation mode is normal

S1_D_pc[9] = AMPP_FUNCTION(QC2__clk0, S1_F_pc[9], F1_data_out, S1_W_stall);

--S1_reset_d1 is std_1c20:inst|cpu:the_cpu|reset_d1

--operation mode is normal

S1_reset_d1 = AMPP_FUNCTION(QC2__clk0, F1_data_out);

--S1_D_pc[8] is std_1c20:inst|cpu:the_cpu|D_pc[8]

--operation mode is normal

S1_D_pc[8] = AMPP_FUNCTION(QC2__clk0, S1_F_pc[8], F1_data_out, S1_W_stall);

--S1_D_pc[7] is std_1c20:inst|cpu:the_cpu|D_pc[7]

--operation mode is normal

S1_D_pc[7] = AMPP_FUNCTION(QC2__clk0, S1_F_pc[7], F1_data_out, S1_W_stall);

--S1_D_pc[6] is std_1c20:inst|cpu:the_cpu|D_pc[6]

--operation mode is normal

S1_D_pc[6] = AMPP_FUNCTION(QC2__clk0, S1_F_pc[6], F1_data_out, S1_W_stall);

--S1_D_pc[5] is std_1c20:inst|cpu:the_cpu|D_pc[5]

--operation mode is normal

S1_D_pc[5] = AMPP_FUNCTION(QC2__clk0, S1_F_pc[5], F1_data_out, S1_W_stall);

--S1_D_pc[4] is std_1c20:inst|cpu:the_cpu|D_pc[4]

--operation mode is normal

S1_D_pc[4] = AMPP_FUNCTION(QC2__clk0, S1_F_pc[4], F1_data_out, S1_W_stall);

--S1_M_ienable_reg[1] is std_1c20:inst|cpu:the_cpu|M_ienable_reg[1]

--operation mode is normal

S1_M_ienable_reg[1] = AMPP_FUNCTION(QC2__clk0, S1L407, F1_data_out, S1L1117);

--S1_M_bstatus_reg is std_1c20:inst|cpu:the_cpu|M_bstatus_reg

--operation mode is normal

S1_M_bstatus_reg = AMPP_FUNCTION(QC2__clk0, S1_M_bstatus_reg, S1L404, S1_M_status_reg_pie, S1_E_wrctl_bstatus, F1_data_out, S1_E_ctrl_break, S1L1278);

--S1_M_estatus_reg is std_1c20:inst|cpu:the_cpu|M_estatus_reg

--operation mode is normal

S1_M_estatus_reg = AMPP_FUNCTION(QC2__clk0, S1_M_estatus_reg, S1L404, S1_M_status_reg_pie, S1_E_wrctl_estatus, F1_data_out, S1_E_ctrl_exception, S1L1278);

--S1_M_ienable_reg[0] is std_1c20:inst|cpu:the_cpu|M_ienable_reg[0]

--operation mode is normal

S1_M_ienable_reg[0] = AMPP_FUNCTION(QC2__clk0, S1L404, F1_data_out, S1L1117);

--S1L198 is std_1c20:inst|cpu:the_cpu|D_control_rd_data_without_mmu_regs[0]~504

--operation mode is normal

S1L198 = AMPP_FUNCTION(S1_D_iw[7], S1_M_estatus_reg, S1_D_iw[6], S1_M_ienable_reg[0]);

--S1L199 is std_1c20:inst|cpu:the_cpu|D_control_rd_data_without_mmu_regs[0]~505

--operation mode is normal

S1L199 = AMPP_FUNCTION(S1_M_status_reg_pie, S1_M_ipending_reg[0], S1_D_iw[8], S1L198);

--DD1_q_b[1] is std_1c20:inst|cpu:the_cpu|cpu_register_bank_b_module:cpu_register_bank_b|altsyncram:the_altsyncram|altsyncram_4vd1:auto_generated|q_b[1]

--RAM Block Operation Mode: Simple Dual-Port

--Port A Depth: 32, Port A Width: 1, Port B Depth: 32, Port B Width: 1

--Port A Logical Depth: 32, Port A Logical Width: 32, Port B Logical Depth: 32, Port B Logical Width: 32

--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered

DD1_q_b[1] = AMPP_FUNCTION(GND, GND, QC2__clk0, QC2__clk0, !S1_M_wr_dst_reg, S1_W_stall, S1L1285, S1_M_dst_regnum[0], S1_M_dst_regnum[1], S1_M_dst_regnum[2], S1_M_dst_regnum[3], S1_M_dst_regnum[4], AD1_q_b[22], AD1_q_b[23], AD1_q_b[24], AD1_q_b[25], AD1_q_b[26]);

--DD1_q_b[0] is std_1c20:inst|cpu:the_cpu|cpu_register_bank_b_module:cpu_register_bank_b|altsyncram:the_altsyncram|altsyncram_4vd1:auto_generated|q_b[0]

--RAM Block Operation Mode: Simple Dual-Port

--Port A Depth: 32, Port A Width: 1, Port B Depth: 32, Port B Width: 1

--Port A Logical Depth: 32, Port A Logical Width: 32, Port B Logical Depth: 32, Port B Logical Width: 32

--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered

DD1_q_b[0] = AMPP_FUNCTION(GND, GND, QC2__clk0, QC2__clk0, !S1_M_wr_dst_reg, S1_W_stall, S1L1282, S1_M_dst_regnum[0], S1_M_dst_regnum[1], S1_M_dst_regnum[2], S1_M_dst_regnum[3], S1_M_dst_regnum[4], AD1_q_b[22], AD1_q_b[23], AD1_q_b[24], AD1_q_b[25], AD1_q_b[26]);

--EF1_dffs[1] is sld_hub:sld_hub_inst|lpm_shiftreg:jtag_ir_register|dffs[1]

--operation mode is normal

EF1_dffs[1] = AMPP_FUNCTION(A1L5, EF1_dffs[2], FF1_state[0], FF1_state[11]);

--EF1_dffs[9] is sld_hub:sld_hub_inst|lpm_shiftreg:jtag_ir_register|dffs[9]

--operation mode is normal

EF1_dffs[9] = AMPP_FUNCTION(A1L5, altera_internal_jtag, FF1_state[0], FF1_state[11]);

--EF1_dffs[8] is sld_hub:sld_hub_inst|lpm_shiftreg:jtag_ir_register|dffs[8]

--operation mode is normal

EF1_dffs[8] = AMPP_FUNCTION(A1L5, EF1_dffs[9], FF1_state[0], FF1_state[11]);

--EF1_dffs[7] is sld_hub:sld_hub_inst|lpm_shiftreg:jtag_ir_register|dffs[7]

--operation mode is normal

EF1_dffs[7] = AMPP_FUNCTION(A1L5, EF1_dffs[8], FF1_state[0], FF1_state[11]);

--EF1_dffs[6] is sld_hub:sld_hub_inst|lpm_shiftreg:jtag_ir_register|dffs[6]

--operation mode is normal

EF1_dffs[6] = AMPP_FUNCTION(A1L5, EF1_dffs[7], FF1_state[0], FF1_state[11]);

--C1L6 is sld_hub:sld_hub_inst|Equal0~87

--operation mode is normal

C1L6 = AMPP_FUNCTION(EF1_dffs[9], EF1_dffs[8], EF1_dffs[7], EF1_dffs[6]);

--EF1_dffs[3] is sld_hub:sld_hub_inst|lpm_shiftreg:jtag_ir_register|dffs[3]

--operation mode is normal

EF1_dffs[3] = AMPP_FUNCTION(A1L5, EF1_dffs[4], FF1_state[0], FF1_state[11]);

--EF1_dffs[2] is sld_hub:sld_hub_inst|lpm_shiftreg:jtag_ir_register|dffs[2]

--operation mode is normal

EF1_dffs[2] = AMPP_FUNCTION(A1L5, EF1_dffs[3], FF1_state[0], FF1_state[11]);

--EF1_dffs[5] is sld_hub:sld_hub_inst|lpm_shiftreg:jtag_ir_register|dffs[5]

--operation mode is normal

EF1_dffs[5] = AMPP_FUNCTION(A1L5, EF1_dffs[6], FF1_state[0], FF1_state[11]);

--EF1_dffs[4] is sld_hub:sld_hub_inst|lpm_shiftreg:jtag_ir_register|dffs[4]

--operation mode is normal

EF1_dffs[4] = AMPP_FUNCTION(A1L5, EF1_dffs[5], FF1_state[0], FF1_state[11]);

--C1L7 is sld_hub:sld_hub_inst|Equal0~88

--operation mode is normal

C1L7 = AMPP_FUNCTION(EF1_dffs[3], EF1_dffs[2], EF1_dffs[5], EF1_dffs[4]);

--EF1_dffs[0] is sld_hub:sld_hub_inst|lpm_shiftreg:jtag_ir_register|dffs[0]

--operation mode is normal

EF1_dffs[0] = AMPP_FUNCTION(A1L5, EF1_dffs[1], FF1_state[0], FF1_state[11]);

--FF1_state[0] is sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state[0]

--operation mode is normal

FF1_state[0] = AMPP_FUNCTION(A1L5, A1L7, FF1_state[9], FF1L19, FF1_state[0], VCC);

--FF1_state[12] is sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state[12]

--operation mode is normal

FF1_state[12] = AMPP_FUNCTION(A1L5, FF1_state[10], FF1_state[11], VCC, !A1L7);

--FF1_state[5] is sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state[5]

--operation mode is normal

FF1_state[5] = AMPP_FUNCTION(A1L5, A1L7, FF1_state[4], FF1_state[3], VCC);

--FF1_state[7] is sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state[7]

--operation mode is normal

FF1_state[7] = AMPP_FUNCTION(A1L5, A1L7, FF1_state[6], VCC);

--BF3_Q[6] is sld_hub:sld_hub_inst|sld_dffex:IRSR|Q[6]

--operation mode is normal

BF3_Q[6] = AMPP_FUNCTION(A1L5, altera_internal_jtag, !C1_CLR_SIGNAL, FF1_state[4], C1_IRSR_ENA);

--C1_OK_TO_UPDATE_IR_Q is sld_hub:sld_hub_inst|OK_TO_UPDATE_IR_Q

--operation mode is normal

C1_OK_TO_UPDATE_IR_Q = AMPP_FUNCTION(A1L5, C1_jtag_debug_mode_usr1, C1_OK_TO_UPDATE_IR_Q, FF1_state[4], FF1_state[8], VCC);

--C1L24 is sld_hub:sld_hub_inst|IRF_ENA_ENABLE~29

--operation mode is normal

C1L24 = AMPP_FUNCTION(A1L7, FF1_state[4], C1_jtag_debug_mode_usr1, C1_OK_TO_UPDATE_IR_Q);

--CF1_WORD_SR[1] is sld_hub:sld_hub_inst|sld_rom_sr:HUB_INFO_REG|WORD_SR[1]

--operation mode is normal

CF1_WORD_SR[1] = AMPP_FUNCTION(A1L5, CF1_WORD_SR[2], CF1L15, FF1_state[4], CF1_clear_signal, VCC, CF1L21);

--CF1_word_counter[4] is sld_hub:sld_hub_inst|sld_rom_sr:HUB_INFO_REG|word_counter[4]

--operation mode is normal

CF1_word_counter[4] = AMPP_FUNCTION(A1L5, CF1L1, CF1_word_counter[3], CF1L11, CF1_clear_signal, VCC, CF1L20);

--CF1_word_counter[0] is sld_hub:sld_hub_inst|sld_rom_sr:HUB_INFO_REG|word_counter[0]

--operation mode is normal

CF1_word_counter[0] = AMPP_FUNCTION(A1L5, CF1L2, CF1_word_counter[3], CF1L11, CF1_clear_signal, VCC, CF1L20);

--CF1_word_counter[1] is sld_hub:sld_hub_inst|sld_rom_sr:HUB_INFO_REG|word_counter[1]

--operation mode is normal

CF1_word_counter[1] = AMPP_FUNCTION(A1L5, FF1_state[8], C1_jtag_debug_mode_usr1, CF1L4, VCC, CF1L20);

--CF1_word_counter[2] is sld_hub:sld_hub_inst|sld_rom_sr:HUB_INFO_REG|word_counter[2]

--operation mode is normal

CF1_word_counter[2] = AMPP_FUNCTION(A1L5, FF1_state[8], C1_jtag_debug_mode_usr1, CF1L6, VCC, CF1L20);

--CF1_word_counter[3] is sld_hub:sld_hub_inst|sld_rom_sr:HUB_INFO_REG|word_counter[3]

--operation mode is normal

CF1_word_counter[3] = AMPP_FUNCTION(A1L5, CF1L8, CF1_word_counter[3], CF1L11, CF1_clear_signal, VCC, CF1L20);

--CF1L16 is sld_hub:sld_hub_inst|sld_rom_sr:HUB_INFO_REG|Mux3~33

--operation mode is normal

CF1L16 = AMPP_FUNCTION(CF1_word_counter[0], CF1_word_counter[1], CF1_word_counter[2], CF1_word_counter[3]);

--CF1L19 is sld_hub:sld_hub_inst|sld_rom_sr:HUB_INFO_REG|word_counter[0]~1274

--operation mode is normal

CF1L19 = AMPP_FUNCTION(CF1_word_counter[4], CF1L16);

--CF1_clear_signal is sld_hub:sld_hub_inst|sld_rom_sr:HUB_INFO_REG|clear_signal

--operation mode is normal

CF1_clear_signal = AMPP_FUNCTION(FF1_state[8], C1_jtag_debug_mode_usr1);

--C1_jtag_debug_mode_usr0 is sld_hub:sld_hub_inst|jtag_debug_mode_usr0

--operation mode is normal

C1_jtag_debug_mode_usr0 = AMPP_FUNCTION(A1L5, C1L6, C1L7, EF1_dffs[1], EF1_dffs[0], FF1_state[0], FF1_state[12]);

--C1L11 is sld_hub:sld_hub_inst|HUB_BYPASS_REG~20

--operation mode is normal

C1L11 = AMPP_FUNCTION(altera_internal_jtag, FF1_state[4]);

--C1L32 is sld_hub:sld_hub_inst|jtag_debug_mode~2

--operation mode is normal

C1L32 = AMPP_FUNCTION(C1_jtag_debug_mode_usr1, C1_jtag_debug_mode_usr0);

--BF3_Q[1] is sld_hub:sld_hub_inst|sld_dffex:IRSR|Q[1]

--operation mode is normal

BF3_Q[1] = AMPP_FUNCTION(A1L5, C1L23, SD1L120Q, BF3_Q[2], !C1_CLR_SIGNAL, FF1_state[4], BF3L4);

--BF3_Q[3] is sld_hub:sld_hub_inst|sld_dffex:IRSR|Q[3]

--operation mode is normal

BF3_Q[3] = AMPP_FUNCTION(A1L5, FF1_state[4], BF3_Q[4], !C1_CLR_SIGNAL, BF3L4);

--BF3_Q[2] is sld_hub:sld_hub_inst|sld_dffex:IRSR|Q[2]

--operation mode is normal

BF3_Q[2] = AMPP_FUNCTION(A1L5, FF1_state[4], BF3_Q[3], !C1_CLR_SIGNAL, BF3L4);

--C1L4 is sld_hub:sld_hub_inst|comb~98

--operation mode is normal

C1L4 = AMPP_FUNCTION(FF1_state[4], FF1_state[3], C1_jtag_debug_mode_usr0, C1_jtag_debug_mode_usr1);

--SD1_sr[1] is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|sr[1]

--operation mode is normal

SD1_sr[1] = AMPP_FUNCTION(A1L5, SD1L131, SD1_sr[2], SD1L144, SD1L142, !C1_CLR_SIGNAL, SD1L6);

--SD1_DRsize[1] is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|DRsize[1]

--operation mode is normal

SD1_DRsize[1] = AMPP_FUNCTION(A1L5, SD1L122, !C1_CLR_SIGNAL, SD1_st_updateir);

--SD1_DRsize[2] is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|DRsize[2]

--operation mode is normal

SD1_DRsize[2] = AMPP_FUNCTION(A1L5, SD1L122, !C1_CLR_SIGNAL, SD1_st_updateir);

--SD1_DRsize[0] is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|DRsize[0]

--operation mode is normal

SD1_DRsize[0] = AMPP_FUNCTION(A1L5, BF5_Q[0], BF5_Q[1], !C1_CLR_SIGNAL, SD1_st_updateir);

--SD1L73Q is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|DRsize[1]~19729

--operation mode is normal

SD1L73Q = AMPP_FUNCTION(A1L5, !C1_CLR_SIGNAL, SD1_st_updateir);

--SD1L140 is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|Mux45~158

--operation mode is normal

SD1L140 = AMPP_FUNCTION(SD1_DRsize[1], SD1_DRsize[2], SD1_DRsize[0], SD1L73Q);

--SD1L141 is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|Mux45~159

--operation mode is normal

SD1L141 = AMPP_FUNCTION(altera_internal_jtag, SD1_sr[1], SD1L140);

--JD1_internal_monitor_ready is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_debug:the_cpu_nios2_oci_debug|internal_monitor_ready

--operation mode is normal

JD1_internal_monitor_ready = AMPP_FUNCTION(QC2__clk0, JD1L7, S1_M_st_data[0], FD1L14, SD1L191, VCC);

--SD1L5 is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|DRsize[0]~19969

--operation mode is normal

SD1L5 = AMPP_FUNCTION(JD1_internal_monitor_ready, SD1_ir[0], SD1_ir[1]);

--SD1_in_between_shiftdr_and_updatedr is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|in_between_shiftdr_and_updatedr

--operation mode is normal

SD1_in_between_shiftdr_and_updatedr = AMPP_FUNCTION(A1L5, SD1_st_shiftdr, SD1_in_between_shiftdr_and_updatedr, SD1_st_updatedr, !C1_CLR_SIGNAL);

--SD1L143 is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|process2~311

--operation mode is normal

SD1L143 = AMPP_FUNCTION(A1L4, SD1_in_between_shiftdr_and_updatedr);

--SD1L144 is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|process2~312

--operation mode is normal

SD1L144 = AMPP_FUNCTION(A1L4, SD1L145);

--SD1L6 is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|DRsize[0]~19971

--operation mode is normal

SD1L6 = AMPP_FUNCTION(SD1L145, A1L4, SD1_in_between_shiftdr_and_updatedr, SD1_st_updateir);

--GE1_rvalid is std_1c20:inst|jtag_uart:the_jtag_uart|alt_jtag_atlantic:jtag_uart_alt_jtag_atlantic|rvalid

--operation mode is normal

GE1_rvalid = AMPP_FUNCTION(QC2__clk0, GE1_rvalid0, F1_data_out);

--GE1_td_shift[1] is std_1c20:inst|jtag_uart:the_jtag_uart|alt_jtag_atlantic:jtag_uart_alt_jtag_atlantic|td_shift[1]

--operation mode is normal

GE1_td_shift[1] = AMPP_FUNCTION(A1L5, GE1L53, GE1L54, GE1L63, !C1_CLR_SIGNAL, GE1L52);

--GE1_count[9] is std_1c20:inst|jtag_uart:the_jtag_uart|alt_jtag_atlantic:jtag_uart_alt_jtag_atlantic|count[9]

--operation mode is normal

GE1_count[9] = AMPP_FUNCTION(A1L5, GE1L55, GND, VCC, C1_CLR_SIGNAL, GE1L52);

--GE1L65 is std_1c20:inst|jtag_uart:the_jtag_uart|alt_jtag_atlantic:jtag_uart_alt_jtag_atlantic|td_shift~3548

--operation mode is normal

GE1L65 = AMPP_FUNCTION(GE1_rvalid, GE1_td_shift[1], GE1_count[9]);

--GE1_state is std_1c20:inst|jtag_uart:the_jtag_uart|alt_jtag_atlantic:jtag_uart_alt_jtag_atlantic|state

--operation mode is normal

GE1_state = AMPP_FUNCTION(A1L5, GE1L1, C1L11, GE1_state, GE1L36, !C1_CLR_SIGNAL);

--GE1L66 is std_1c20:inst|jtag_uart:the_jtag_uart|alt_jtag_atlantic:jtag_uart_alt_jtag_atlantic|td_shift~3549

--operation mode is normal

GE1L66 = AMPP_FUNCTION(altera_internal_jtag, GE1_state);

--GE1_count[1] is std_1c20:inst|jtag_uart:the_jtag_uart|alt_jtag_atlantic:jtag_uart_alt_jtag_atlantic|count[1]

--operation mode is normal

GE1_count[1] = AMPP_FUNCTION(A1L5, FF1_state[4], GE1_count[0], !C1_CLR_SIGNAL, GE1L52);

--GE1_td_shift[9] is std_1c20:inst|jtag_uart:the_jtag_uart|alt_jtag_atlantic:jtag_uart_alt_jtag_atlantic|td_shift[9]

--operation mode is normal

GE1_td_shift[9] = AMPP_FUNCTION(A1L5, GE1_td_shift[10], GE1_rdata[7], GE1_count[9], !C1_CLR_SIGNAL, !FF1_state[4], GE1L52);

--GE1_user_saw_rvalid is std_1c20:inst|jtag_uart:the_jtag_uart|alt_jtag_atlantic:jtag_uart_alt_jtag_atlantic|user_saw_rvalid

--operation mode is normal

GE1_user_saw_rvalid = AMPP_FUNCTION(A1L5, GE1_td_shift[0], GE1_user_saw_rvalid, GE1_count[0], GE1L69, !C1_CLR_SIGNAL);

--BB1_t_dav is std_1c20:inst|jtag_uart:the_jtag_uart|t_dav

--operation mode is normal

BB1_t_dav_lut_out = NE2_b_full;

BB1_t_dav = DFFEAS(BB1_t_dav_lut_out, QC2__clk0, F1_data_out, , , , , , );

--GE1L67 is std_1c20:inst|jtag_uart:the_jtag_uart|alt_jtag_atlantic:jtag_uart_alt_jtag_atlantic|td_shift~3550

--operation mode is normal

GE1L67 = AMPP_FUNCTION(GE1L66, GE1L65, GE1L62, BB1_t_dav);

--BF4_Q[0] is sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:2:IRF|Q[0]

--operation mode is normal

BF4_Q[0] = AMPP_FUNCTION(A1L5, BF4L3, BF4_Q[0], C1L27, !C1_CLR_SIGNAL);

--GE1L1 is std_1c20:inst|jtag_uart:the_jtag_uart|alt_jtag_atlantic:jtag_uart_alt_jtag_atlantic|always0~58

--operation mode is normal

GE1L1 = AMPP_FUNCTION(BF8_Q[1], C1_jtag_debug_mode, C1_jtag_debug_mode_usr1, BF2_Q[0]);

--GE1L52 is std_1c20:inst|jtag_uart:the_jtag_uart|alt_jtag_atlantic:jtag_uart_alt_jtag_atlantic|td_shift[9]~3551

--operation mode is normal

GE1L52 = AMPP_FUNCTION(GE1L1, FF1_state[4], FF1_state[3]);

--SD1L119Q is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|ir_out[0]~reg0

--operation mode is normal

SD1L119Q = AMPP_FUNCTION(A1L5, JD1_internal_monitor_ready, !C1_CLR_SIGNAL);

--BF3_Q[4] is sld_hub:sld_hub_inst|sld_dffex:IRSR|Q[4]

--operation mode is normal

BF3_Q[4] = AMPP_FUNCTION(A1L5, FF1_state[4], BF3_Q[5], !C1_CLR_SIGNAL, BF3L4);

--GF1_dffe1a[3] is sld_hub:sld_hub_inst|lpm_decode:instruction_decoder|decode_ogi:auto_generated|dffe1a[3]

--operation mode is normal

GF1_dffe1a[3] = AMPP_FUNCTION(A1L5, BF3_Q[1], BF3_Q[2], C1L32, BF3_Q[3], !C1_CLR_SIGNAL, C1L5);

--C1L23 is sld_hub:sld_hub_inst|IR_MUX_SEL[1]~30

--operation mode is normal

C1L23 = AMPP_FUNCTION(BF3_Q[4], BF3_Q[6], GF1_dffe1a[3]);

--BF3_Q[5] is sld_hub:sld_hub_inst|sld_dffex:IRSR|Q[5]

--operation mode is normal

BF3_Q[5] = AMPP_FUNCTION(A1L5, BF3_Q[6], BF3_Q[5], FF1_state[4], C1_jtag_debug_mode_usr1, !C1_CLR_SIGNAL);

--C1L22 is sld_hub:sld_hub_inst|IR_MUX_SEL[0]~31

--operation mode is normal

C1L22 = AMPP_FUNCTION(BF3_Q[3], BF3_Q[5], GF1_dffe1a[3]);

--BF3L3 is sld_hub:sld_hub_inst|sld_dffex:IRSR|Q[0]~7720

--operation mode is normal

BF3L3 = AMPP_FUNCTION(C1L23, BF4_Q[0], C1L22);

--C1_IRSR_ENA is sld_hub:sld_hub_inst|IRSR_ENA

--operation mode is normal

C1_IRSR_ENA = AMPP_FUNCTION(C1_jtag_debug_mode_usr1, FF1_state[4], FF1_state[3]);

--BF3L4 is sld_hub:sld_hub_inst|sld_dffex:IRSR|Q[0]~7721

--operation mode is normal

BF3L4 = AMPP_FUNCTION(C1_IRSR_ENA, FF1_state[4], C1L23, C1L22);

--FF1_state[2] is sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state[2]

--operation mode is normal

FF1_state[2] = AMPP_FUNCTION(A1L5, FF1_state[8], FF1_state[1], FF1_state[15], VCC, !A1L7);

--XE1L16 is std_1c20:inst|uart1:the_uart1|uart1_regs:the_uart1_regs|Equal1~117

--operation mode is normal

XE1L16 = !S1_M_alu_result[2] & !S1_M_alu_result[3];

--XE1L17 is std_1c20:inst|uart1:the_uart1|uart1_regs:the_uart1_regs|Equal1~118

--operation mode is normal

XE1L17 = S1_M_alu_result[2] & (!S1_M_alu_result[3]);

--S1_M_st_data[31] is std_1c20:inst|cpu:the_cpu|M_st_data[31]

--operation mode is normal

S1_M_st_data[31] = AMPP_FUNCTION(QC2__clk0, S1L1245, S1L749, S1L741, S1_E_iw[3], F1_data_out, S1_E_iw[4], S1_W_stall);

--S1_M_st_data[30] is std_1c20:inst|cpu:the_cpu|M_st_data[30]

--operation mode is normal

S1_M_st_data[30] = AMPP_FUNCTION(QC2__clk0, S1L1243, S1L748, S1L740, S1_E_iw[3], F1_data_out, S1_E_iw[4], S1_W_stall);

--S1_M_st_data[29] is std_1c20:inst|cpu:the_cpu|M_st_data[29]

--operation mode is normal

S1_M_st_data[29] = AMPP_FUNCTION(QC2__clk0, S1L1241, S1L747, S1L739, S1_E_iw[3], F1_data_out, S1_E_iw[4], S1_W_stall);

--S1_M_st_data[28] is std_1c20:inst|cpu:the_cpu|M_st_data[28]

--operation mode is normal

S1_M_st_data[28] = AMPP_FUNCTION(QC2__clk0, S1L1239, S1L746, S1L738, S1_E_iw[3], F1_data_out, S1_E_iw[4], S1_W_stall);

--S1_M_st_data[27] is std_1c20:inst|cpu:the_cpu|M_st_data[27]

--operation mode is normal

S1_M_st_data[27] = AMPP_FUNCTION(QC2__clk0, S1L1237, S1L745, S1L737, S1_E_iw[3], F1_data_out, S1_E_iw[4], S1_W_stall);

--S1_M_st_data[26] is std_1c20:inst|cpu:the_cpu|M_st_data[26]

--operation mode is normal

S1_M_st_data[26] = AMPP_FUNCTION(QC2__clk0, S1L1235, S1L744, S1L736, S1_E_iw[3], F1_data_out, S1_E_iw[4], S1_W_stall);

--S1_M_st_data[25] is std_1c20:inst|cpu:the_cpu|M_st_data[25]

--operation mode is normal

S1_M_st_data[25] = AMPP_FUNCTION(QC2__clk0, S1L1233, S1L743, S1L735, S1_E_iw[3], F1_data_out, S1_E_iw[4], S1_W_stall);

--S1_M_st_data[24] is std_1c20:inst|cpu:the_cpu|M_st_data[24]

--operation mode is normal

S1_M_st_data[24] = AMPP_FUNCTION(QC2__clk0, S1L1231, S1L742, S1L734, S1_E_iw[3], F1_data_out, S1_E_iw[4], S1_W_stall);

--Y1L276 is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|outgoing_ext_ram_bus_data[7]~2893

--operation mode is normal

Y1L276 = T1_internal_cpu_data_master_dbs_address[1] & (T1_internal_cpu_data_master_dbs_address[0] & S1_M_st_data[31] # !T1_internal_cpu_data_master_dbs_address[0] & (S1_M_st_data[23])) # !T1_internal_cpu_data_master_dbs_address[1] & S1_M_st_data[31] & (!T1_internal_cpu_data_master_dbs_address[0]);

--Y1L277 is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|outgoing_ext_ram_bus_data[7]~2894

--operation mode is normal

Y1L277 = Y1L276 # S1_M_st_data[15] & T1_internal_cpu_data_master_dbs_address[0] & !T1_internal_cpu_data_master_dbs_address[1];

--T1L237 is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|Equal1~40

--operation mode is normal

T1L237 = T1_internal_cpu_data_master_dbs_address[1] # T1_internal_cpu_data_master_dbs_address[0];

--Y1L278 is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|outgoing_ext_ram_bus_data[31]~2895

--operation mode is normal

Y1L278 = Y1L55 & !Y1L52 & (Y1L17 # Y1L19);

--Y1L274 is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|outgoing_ext_ram_bus_data[6]~2897

--operation mode is normal

Y1L274 = T1_internal_cpu_data_master_dbs_address[1] & (T1_internal_cpu_data_master_dbs_address[0] & S1_M_st_data[30] # !T1_internal_cpu_data_master_dbs_address[0] & (S1_M_st_data[22])) # !T1_internal_cpu_data_master_dbs_address[1] & S1_M_st_data[30] & (!T1_internal_cpu_data_master_dbs_address[0]);

--Y1L275 is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|outgoing_ext_ram_bus_data[6]~2898

--operation mode is normal

Y1L275 = Y1L274 # S1_M_st_data[14] & T1_internal_cpu_data_master_dbs_address[0] & !T1_internal_cpu_data_master_dbs_address[1];

--Y1L272 is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|outgoing_ext_ram_bus_data[5]~2900

--operation mode is normal

Y1L272 = T1_internal_cpu_data_master_dbs_address[1] & (T1_internal_cpu_data_master_dbs_address[0] & S1_M_st_data[29] # !T1_internal_cpu_data_master_dbs_address[0] & (S1_M_st_data[21])) # !T1_internal_cpu_data_master_dbs_address[1] & S1_M_st_data[29] & (!T1_internal_cpu_data_master_dbs_address[0]);

--Y1L273 is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|outgoing_ext_ram_bus_data[5]~2901

--operation mode is normal

Y1L273 = Y1L272 # S1_M_st_data[13] & T1_internal_cpu_data_master_dbs_address[0] & !T1_internal_cpu_data_master_dbs_address[1];

--Y1L270 is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|outgoing_ext_ram_bus_data[4]~2903

--operation mode is normal

Y1L270 = T1_internal_cpu_data_master_dbs_address[1] & (T1_internal_cpu_data_master_dbs_address[0] & S1_M_st_data[28] # !T1_internal_cpu_data_master_dbs_address[0] & (S1_M_st_data[20])) # !T1_internal_cpu_data_master_dbs_address[1] & S1_M_st_data[28] & (!T1_internal_cpu_data_master_dbs_address[0]);

--Y1L271 is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|outgoing_ext_ram_bus_data[4]~2904

--operation mode is normal

Y1L271 = Y1L270 # S1_M_st_data[12] & T1_internal_cpu_data_master_dbs_address[0] & !T1_internal_cpu_data_master_dbs_address[1];

--Y1L268 is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|outgoing_ext_ram_bus_data[3]~2906

--operation mode is normal

Y1L268 = T1_internal_cpu_data_master_dbs_address[1] & (T1_internal_cpu_data_master_dbs_address[0] & S1_M_st_data[27] # !T1_internal_cpu_data_master_dbs_address[0] & (S1_M_st_data[19])) # !T1_internal_cpu_data_master_dbs_address[1] & S1_M_st_data[27] & (!T1_internal_cpu_data_master_dbs_address[0]);

--Y1L269 is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|outgoing_ext_ram_bus_data[3]~2907

--operation mode is normal

Y1L269 = Y1L268 # S1_M_st_data[11] & T1_internal_cpu_data_master_dbs_address[0] & !T1_internal_cpu_data_master_dbs_address[1];

--Y1L266 is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|outgoing_ext_ram_bus_data[2]~2909

--operation mode is normal

Y1L266 = T1_internal_cpu_data_master_dbs_address[1] & (T1_internal_cpu_data_master_dbs_address[0] & S1_M_st_data[26] # !T1_internal_cpu_data_master_dbs_address[0] & (S1_M_st_data[18])) # !T1_internal_cpu_data_master_dbs_address[1] & S1_M_st_data[26] & (!T1_internal_cpu_data_master_dbs_address[0]);

--Y1L267 is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|outgoing_ext_ram_bus_data[2]~2910

--operation mode is normal

Y1L267 = Y1L266 # S1_M_st_data[10] & T1_internal_cpu_data_master_dbs_address[0] & !T1_internal_cpu_data_master_dbs_address[1];

--Y1L264 is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|outgoing_ext_ram_bus_data[1]~2912

--operation mode is normal

Y1L264 = T1_internal_cpu_data_master_dbs_address[1] & (T1_internal_cpu_data_master_dbs_address[0] & S1_M_st_data[25] # !T1_internal_cpu_data_master_dbs_address[0] & (S1_M_st_data[17])) # !T1_internal_cpu_data_master_dbs_address[1] & S1_M_st_data[25] & (!T1_internal_cpu_data_master_dbs_address[0]);

--Y1L265 is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|outgoing_ext_ram_bus_data[1]~2913

--operation mode is normal

Y1L265 = Y1L264 # S1_M_st_data[9] & T1_internal_cpu_data_master_dbs_address[0] & !T1_internal_cpu_data_master_dbs_address[1];

--Y1L262 is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|outgoing_ext_ram_bus_data[0]~2915

--operation mode is normal

Y1L262 = T1_internal_cpu_data_master_dbs_address[1] & (T1_internal_cpu_data_master_dbs_address[0] & S1_M_st_data[24] # !T1_internal_cpu_data_master_dbs_address[0] & (S1_M_st_data[16])) # !T1_internal_cpu_data_master_dbs_address[1] & S1_M_st_data[24] & (!T1_internal_cpu_data_master_dbs_address[0]);

--Y1L263 is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|outgoing_ext_ram_bus_data[0]~2916

--operation mode is normal

Y1L263 = Y1L262 # S1_M_st_data[8] & T1_internal_cpu_data_master_dbs_address[0] & !T1_internal_cpu_data_master_dbs_address[1];

--KB1_active_data[31] is std_1c20:inst|sdram:the_sdram|active_data[31]

--operation mode is normal

KB1_active_data[31]_lut_out = KB1L12 & (KB1L14 & (TE1L160) # !KB1L14 & KB1_active_data[31]) # !KB1L12 & KB1_active_data[31];

KB1_active_data[31] = DFFEAS(KB1_active_data[31]_lut_out, QC2__clk0, VCC, , , , , , );

--TE1_entry_1[31] is std_1c20:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_1[31]

--operation mode is normal

TE1_entry_1[31]_lut_out = S1_M_st_data[31];

TE1_entry_1[31] = DFFEAS(TE1_entry_1[31]_lut_out, QC2__clk0, VCC, , TE1L123, , , , );

--TE1_entry_0[31] is std_1c20:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_0[31]

--operation mode is normal

TE1_entry_0[31]_lut_out = S1_M_st_data[31];

TE1_entry_0[31] = DFFEAS(TE1_entry_0[31]_lut_out, QC2__clk0, VCC, , TE1L62, , , , );

--TE1L160 is std_1c20:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|rd_data[31]~510

--operation mode is normal

TE1L160 = TE1_rd_address & TE1_entry_1[31] # !TE1_rd_address & (TE1_entry_0[31]);

--KB1L509 is std_1c20:inst|sdram:the_sdram|Mux118~1218

--operation mode is normal

KB1L509 = KB1_f_select & (KB1_m_state[1] & KB1_active_data[31] # !KB1_m_state[1] & (TE1L160)) # !KB1_f_select & KB1_active_data[31];

--KB1L510 is std_1c20:inst|sdram:the_sdram|Mux118~1219

--operation mode is normal

KB1L510 = !KB1_m_state[3] & (KB1_m_state[4] $ KB1_m_state[1]);

--KB1L548 is std_1c20:inst|sdram:the_sdram|Mux154~549

--operation mode is normal

KB1L548 = KB1_m_state[4] & KB1L298 & (!KB1_m_state[3]);

--KB1_active_data[30] is std_1c20:inst|sdram:the_sdram|active_data[30]

--operation mode is normal

KB1_active_data[30]_lut_out = KB1L65 & (KB1L66 & TE1L159 # !KB1L66 & (KB1_active_data[30])) # !KB1L65 & (KB1_active_data[30]);

KB1_active_data[30] = DFFEAS(KB1_active_data[30]_lut_out, QC2__clk0, VCC, , , , , , );

--TE1_entry_1[30] is std_1c20:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_1[30]

--operation mode is normal

TE1_entry_1[30]_lut_out = S1_M_st_data[30];

TE1_entry_1[30] = DFFEAS(TE1_entry_1[30]_lut_out, QC2__clk0, VCC, , TE1L123, , , , );

--TE1_entry_0[30] is std_1c20:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_0[30]

--operation mode is normal

TE1_entry_0[30]_lut_out = S1_M_st_data[30];

TE1_entry_0[30] = DFFEAS(TE1_entry_0[30]_lut_out, QC2__clk0, VCC, , TE1L62, , , , );

--TE1L159 is std_1c20:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|rd_data[30]~511

--operation mode is normal

TE1L159 = TE1_rd_address & TE1_entry_1[30] # !TE1_rd_address & (TE1_entry_0[30]);

--KB1L512 is std_1c20:inst|sdram:the_sdram|Mux119~1170

--operation mode is normal

KB1L512 = KB1_f_select & (KB1_m_state[1] & KB1_active_data[30] # !KB1_m_state[1] & (TE1L159)) # !KB1_f_select & KB1_active_data[30];

--KB1_active_data[29] is std_1c20:inst|sdram:the_sdram|active_data[29]

--operation mode is normal

KB1_active_data[29]_lut_out = KB1L12 & (KB1L14 & (TE1L158) # !KB1L14 & KB1_active_data[29]) # !KB1L12 & KB1_active_data[29];

KB1_active_data[29] = DFFEAS(KB1_active_data[29]_lut_out, QC2__clk0, VCC, , , , , , );

--TE1_entry_1[29] is std_1c20:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_1[29]

--operation mode is normal

TE1_entry_1[29]_lut_out = S1_M_st_data[29];

TE1_entry_1[29] = DFFEAS(TE1_entry_1[29]_lut_out, QC2__clk0, VCC, , TE1L123, , , , );

--TE1_entry_0[29] is std_1c20:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_0[29]

--operation mode is normal

TE1_entry_0[29]_lut_out = S1_M_st_data[29];

TE1_entry_0[29] = DFFEAS(TE1_entry_0[29]_lut_out, QC2__clk0, VCC, , TE1L62, , , , );

--TE1L158 is std_1c20:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|rd_data[29]~512

--operation mode is normal

TE1L158 = TE1_rd_address & TE1_entry_1[29] # !TE1_rd_address & (TE1_entry_0[29]);

--KB1L513 is std_1c20:inst|sdram:the_sdram|Mux120~1170

--operation mode is normal

KB1L513 = KB1_f_select & (KB1_m_state[1] & KB1_active_data[29] # !KB1_m_state[1] & (TE1L158)) # !KB1_f_select & KB1_active_data[29];

--KB1_active_data[28] is std_1c20:inst|sdram:the_sdram|active_data[28]

--operation mode is normal

KB1_active_data[28]_lut_out = KB1L65 & (KB1L66 & TE1L157 # !KB1L66 & (KB1_active_data[28])) # !KB1L65 & (KB1_active_data[28]);

KB1_active_data[28] = DFFEAS(KB1_active_data[28]_lut_out, QC2__clk0, VCC, , , , , , );

--TE1_entry_1[28] is std_1c20:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_1[28]

--operation mode is normal

TE1_entry_1[28]_lut_out = S1_M_st_data[28];

TE1_entry_1[28] = DFFEAS(TE1_entry_1[28]_lut_out, QC2__clk0, VCC, , TE1L123, , , , );

--TE1_entry_0[28] is std_1c20:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_0[28]

--operation mode is normal

TE1_entry_0[28]_lut_out = S1_M_st_data[28];

TE1_entry_0[28] = DFFEAS(TE1_entry_0[28]_lut_out, QC2__clk0, VCC, , TE1L62, , , , );

--TE1L157 is std_1c20:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|rd_data[28]~513

--operation mode is normal

TE1L157 = TE1_rd_address & TE1_entry_1[28] # !TE1_rd_address & (TE1_entry_0[28]);

--KB1L514 is std_1c20:inst|sdram:the_sdram|Mux121~1170

--operation mode is normal

KB1L514 = KB1_f_select & (KB1_m_state[1] & KB1_active_data[28] # !KB1_m_state[1] & (TE1L157)) # !KB1_f_select & KB1_active_data[28];

--KB1_active_data[27] is std_1c20:inst|sdram:the_sdram|active_data[27]

--operation mode is normal

KB1_active_data[27]_lut_out = KB1L12 & (KB1L14 & (TE1L156) # !KB1L14 & KB1_active_data[27]) # !KB1L12 & KB1_active_data[27];

KB1_active_data[27] = DFFEAS(KB1_active_data[27]_lut_out, QC2__clk0, VCC, , , , , , );

--TE1_entry_1[27] is std_1c20:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_1[27]

--operation mode is normal

TE1_entry_1[27]_lut_out = S1_M_st_data[27];

TE1_entry_1[27] = DFFEAS(TE1_entry_1[27]_lut_out, QC2__clk0, VCC, , TE1L123, , , , );

--TE1_entry_0[27] is std_1c20:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_0[27]

--operation mode is normal

TE1_entry_0[27]_lut_out = S1_M_st_data[27];

TE1_entry_0[27] = DFFEAS(TE1_entry_0[27]_lut_out, QC2__clk0, VCC, , TE1L62, , , , );

--TE1L156 is std_1c20:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|rd_data[27]~514

--operation mode is normal

TE1L156 = TE1_rd_address & TE1_entry_1[27] # !TE1_rd_address & (TE1_entry_0[27]);

--KB1L515 is std_1c20:inst|sdram:the_sdram|Mux122~1170

--operation mode is normal

KB1L515 = KB1_f_select & (KB1_m_state[1] & KB1_active_data[27] # !KB1_m_state[1] & (TE1L156)) # !KB1_f_select & KB1_active_data[27];

--KB1_active_data[26] is std_1c20:inst|sdram:the_sdram|active_data[26]

--operation mode is normal

KB1_active_data[26]_lut_out = KB1L65 & (KB1L66 & TE1L155 # !KB1L66 & (KB1_active_data[26])) # !KB1L65 & (KB1_active_data[26]);

KB1_active_data[26] = DFFEAS(KB1_active_data[26]_lut_out, QC2__clk0, VCC, , , , , , );

--TE1_entry_1[26] is std_1c20:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_1[26]

--operation mode is normal

TE1_entry_1[26]_lut_out = S1_M_st_data[26];

TE1_entry_1[26] = DFFEAS(TE1_entry_1[26]_lut_out, QC2__clk0, VCC, , TE1L123, , , , );

--TE1_entry_0[26] is std_1c20:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_0[26]

--operation mode is normal

TE1_entry_0[26]_lut_out = S1_M_st_data[26];

TE1_entry_0[26] = DFFEAS(TE1_entry_0[26]_lut_out, QC2__clk0, VCC, , TE1L62, , , , );

--TE1L155 is std_1c20:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|rd_data[26]~515

--operation mode is normal

TE1L155 = TE1_rd_address & TE1_entry_1[26] # !TE1_rd_address & (TE1_entry_0[26]);

--KB1L516 is std_1c20:inst|sdram:the_sdram|Mux123~1170

--operation mode is normal

KB1L516 = KB1_f_select & (KB1_m_state[1] & KB1_active_data[26] # !KB1_m_state[1] & (TE1L155)) # !KB1_f_select & KB1_active_data[26];

--KB1_active_data[25] is std_1c20:inst|sdram:the_sdram|active_data[25]

--operation mode is normal

KB1_active_data[25]_lut_out = KB1L12 & (KB1L14 & (TE1L154) # !KB1L14 & KB1_active_data[25]) # !KB1L12 & KB1_active_data[25];

KB1_active_data[25] = DFFEAS(KB1_active_data[25]_lut_out, QC2__clk0, VCC, , , , , , );

--TE1_entry_1[25] is std_1c20:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_1[25]

--operation mode is normal

TE1_entry_1[25]_lut_out = S1_M_st_data[25];

TE1_entry_1[25] = DFFEAS(TE1_entry_1[25]_lut_out, QC2__clk0, VCC, , TE1L123, , , , );

--TE1_entry_0[25] is std_1c20:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_0[25]

--operation mode is normal

TE1_entry_0[25]_lut_out = S1_M_st_data[25];

TE1_entry_0[25] = DFFEAS(TE1_entry_0[25]_lut_out, QC2__clk0, VCC, , TE1L62, , , , );

--TE1L154 is std_1c20:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|rd_data[25]~516

--operation mode is normal

TE1L154 = TE1_rd_address & TE1_entry_1[25] # !TE1_rd_address & (TE1_entry_0[25]);

--KB1L517 is std_1c20:inst|sdram:the_sdram|Mux124~1170

--operation mode is normal

KB1L517 = KB1_f_select & (KB1_m_state[1] & KB1_active_data[25] # !KB1_m_state[1] & (TE1L154)) # !KB1_f_select & KB1_active_data[25];

--KB1_active_data[24] is std_1c20:inst|sdram:the_sdram|active_data[24]

--operation mode is normal

KB1_active_data[24]_lut_out = KB1L65 & (KB1L66 & TE1L153 # !KB1L66 & (KB1_active_data[24])) # !KB1L65 & (KB1_active_data[24]);

KB1_active_data[24] = DFFEAS(KB1_active_data[24]_lut_out, QC2__clk0, VCC, , , , , , );

--TE1_entry_1[24] is std_1c20:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_1[24]

--operation mode is normal

TE1_entry_1[24]_lut_out = S1_M_st_data[24];

TE1_entry_1[24] = DFFEAS(TE1_entry_1[24]_lut_out, QC2__clk0, VCC, , TE1L123, , , , );

--TE1_entry_0[24] is std_1c20:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_0[24]

--operation mode is normal

TE1_entry_0[24]_lut_out = S1_M_st_data[24];

TE1_entry_0[24] = DFFEAS(TE1_entry_0[24]_lut_out, QC2__clk0, VCC, , TE1L62, , , , );

--TE1L153 is std_1c20:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|rd_data[24]~517

--operation mode is normal

TE1L153 = TE1_rd_address & TE1_entry_1[24] # !TE1_rd_address & (TE1_entry_0[24]);

--KB1L518 is std_1c20:inst|sdram:the_sdram|Mux125~1170

--operation mode is normal

KB1L518 = KB1_f_select & (KB1_m_state[1] & KB1_active_data[24] # !KB1_m_state[1] & (TE1L153)) # !KB1_f_select & KB1_active_data[24];

--KB1_active_data[23] is std_1c20:inst|sdram:the_sdram|active_data[23]

--operation mode is normal

KB1_active_data[23]_lut_out = KB1L12 & (KB1L14 & (TE1L152) # !KB1L14 & KB1_active_data[23]) # !KB1L12 & KB1_active_data[23];

KB1_active_data[23] = DFFEAS(KB1_active_data[23]_lut_out, QC2__clk0, VCC, , , , , , );

--TE1_entry_1[23] is std_1c20:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_1[23]

--operation mode is normal

TE1_entry_1[23]_lut_out = S1_M_st_data[23];

TE1_entry_1[23] = DFFEAS(TE1_entry_1[23]_lut_out, QC2__clk0, VCC, , TE1L123, , , , );

--TE1_entry_0[23] is std_1c20:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_0[23]

--operation mode is normal

TE1_entry_0[23]_lut_out = S1_M_st_data[23];

TE1_entry_0[23] = DFFEAS(TE1_entry_0[23]_lut_out, QC2__clk0, VCC, , TE1L62, , , , );

--TE1L152 is std_1c20:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|rd_data[23]~518

--operation mode is normal

TE1L152 = TE1_rd_address & TE1_entry_1[23] # !TE1_rd_address & (TE1_entry_0[23]);

--KB1L519 is std_1c20:inst|sdram:the_sdram|Mux126~1170

--operation mode is normal

KB1L519 = KB1_f_select & (KB1_m_state[1] & KB1_active_data[23] # !KB1_m_state[1] & (TE1L152)) # !KB1_f_select & KB1_active_data[23];

--KB1_active_data[22] is std_1c20:inst|sdram:the_sdram|active_data[22]

--operation mode is normal

KB1_active_data[22]_lut_out = KB1L65 & (KB1L66 & TE1L151 # !KB1L66 & (KB1_active_data[22])) # !KB1L65 & (KB1_active_data[22]);

KB1_active_data[22] = DFFEAS(KB1_active_data[22]_lut_out, QC2__clk0, VCC, , , , , , );

--TE1_entry_1[22] is std_1c20:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_1[22]

--operation mode is normal

TE1_entry_1[22]_lut_out = S1_M_st_data[22];

TE1_entry_1[22] = DFFEAS(TE1_entry_1[22]_lut_out, QC2__clk0, VCC, , TE1L123, , , , );

--TE1_entry_0[22] is std_1c20:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_0[22]

--operation mode is normal

TE1_entry_0[22]_lut_out = S1_M_st_data[22];

TE1_entry_0[22] = DFFEAS(TE1_entry_0[22]_lut_out, QC2__clk0, VCC, , TE1L62, , , , );

--TE1L151 is std_1c20:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|rd_data[22]~519

--operation mode is normal

TE1L151 = TE1_rd_address & TE1_entry_1[22] # !TE1_rd_address & (TE1_entry_0[22]);

--KB1L520 is std_1c20:inst|sdram:the_sdram|Mux127~1170

--operation mode is normal

KB1L520 = KB1_f_select & (KB1_m_state[1] & KB1_active_data[22] # !KB1_m_state[1] & (TE1L151)) # !KB1_f_select & KB1_active_data[22];

--KB1_active_data[21] is std_1c20:inst|sdram:the_sdram|active_data[21]

--operation mode is normal

KB1_active_data[21]_lut_out = KB1L12 & (KB1L14 & (TE1L150) # !KB1L14 & KB1_active_data[21]) # !KB1L12 & KB1_active_data[21];

KB1_active_data[21] = DFFEAS(KB1_active_data[21]_lut_out, QC2__clk0, VCC, , , , , , );

--TE1_entry_1[21] is std_1c20:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_1[21]

--operation mode is normal

TE1_entry_1[21]_lut_out = S1_M_st_data[21];

TE1_entry_1[21] = DFFEAS(TE1_entry_1[21]_lut_out, QC2__clk0, VCC, , TE1L123, , , , );

--TE1_entry_0[21] is std_1c20:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_0[21]

--operation mode is normal

TE1_entry_0[21]_lut_out = S1_M_st_data[21];

TE1_entry_0[21] = DFFEAS(TE1_entry_0[21]_lut_out, QC2__clk0, VCC, , TE1L62, , , , );

--TE1L150 is std_1c20:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|rd_data[21]~520

--operation mode is normal

TE1L150 = TE1_rd_address & TE1_entry_1[21] # !TE1_rd_address & (TE1_entry_0[21]);

--KB1L521 is std_1c20:inst|sdram:the_sdram|Mux128~1170

--operation mode is normal

KB1L521 = KB1_f_select & (KB1_m_state[1] & KB1_active_data[21] # !KB1_m_state[1] & (TE1L150)) # !KB1_f_select & KB1_active_data[21];

--KB1_active_data[20] is std_1c20:inst|sdram:the_sdram|active_data[20]

--operation mode is normal

KB1_active_data[20]_lut_out = KB1L65 & (KB1L66 & TE1L149 # !KB1L66 & (KB1_active_data[20])) # !KB1L65 & (KB1_active_data[20]);

KB1_active_data[20] = DFFEAS(KB1_active_data[20]_lut_out, QC2__clk0, VCC, , , , , , );

--TE1_entry_1[20] is std_1c20:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_1[20]

--operation mode is normal

TE1_entry_1[20]_lut_out = S1_M_st_data[20];

TE1_entry_1[20] = DFFEAS(TE1_entry_1[20]_lut_out, QC2__clk0, VCC, , TE1L123, , , , );

--TE1_entry_0[20] is std_1c20:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_0[20]

--operation mode is normal

TE1_entry_0[20]_lut_out = S1_M_st_data[20];

TE1_entry_0[20] = DFFEAS(TE1_entry_0[20]_lut_out, QC2__clk0, VCC, , TE1L62, , , , );

--TE1L149 is std_1c20:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|rd_data[20]~521

--operation mode is normal

TE1L149 = TE1_rd_address & TE1_entry_1[20] # !TE1_rd_address & (TE1_entry_0[20]);

--KB1L522 is std_1c20:inst|sdram:the_sdram|Mux129~1170

--operation mode is normal

KB1L522 = KB1_f_select & (KB1_m_state[1] & KB1_active_data[20] # !KB1_m_state[1] & (TE1L149)) # !KB1_f_select & KB1_active_data[20];

--KB1_active_data[19] is std_1c20:inst|sdram:the_sdram|active_data[19]

--operation mode is normal

KB1_active_data[19]_lut_out = KB1L12 & (KB1L14 & (TE1L148) # !KB1L14 & KB1_active_data[19]) # !KB1L12 & KB1_active_data[19];

KB1_active_data[19] = DFFEAS(KB1_active_data[19]_lut_out, QC2__clk0, VCC, , , , , , );

--TE1_entry_1[19] is std_1c20:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_1[19]

--operation mode is normal

TE1_entry_1[19]_lut_out = S1_M_st_data[19];

TE1_entry_1[19] = DFFEAS(TE1_entry_1[19]_lut_out, QC2__clk0, VCC, , TE1L123, , , , );

--TE1_entry_0[19] is std_1c20:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_0[19]

--operation mode is normal

TE1_entry_0[19]_lut_out = S1_M_st_data[19];

TE1_entry_0[19] = DFFEAS(TE1_entry_0[19]_lut_out, QC2__clk0, VCC, , TE1L62, , , , );

--TE1L148 is std_1c20:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|rd_data[19]~522

--operation mode is normal

TE1L148 = TE1_rd_address & TE1_entry_1[19] # !TE1_rd_address & (TE1_entry_0[19]);

--KB1L523 is std_1c20:inst|sdram:the_sdram|Mux130~1170

--operation mode is normal

KB1L523 = KB1_f_select & (KB1_m_state[1] & KB1_active_data[19] # !KB1_m_state[1] & (TE1L148)) # !KB1_f_select & KB1_active_data[19];

--KB1_active_data[18] is std_1c20:inst|sdram:the_sdram|active_data[18]

--operation mode is normal

KB1_active_data[18]_lut_out = KB1L65 & (KB1L66 & TE1L147 # !KB1L66 & (KB1_active_data[18])) # !KB1L65 & (KB1_active_data[18]);

KB1_active_data[18] = DFFEAS(KB1_active_data[18]_lut_out, QC2__clk0, VCC, , , , , , );

--TE1_entry_1[18] is std_1c20:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_1[18]

--operation mode is normal

TE1_entry_1[18]_lut_out = S1_M_st_data[18];

TE1_entry_1[18] = DFFEAS(TE1_entry_1[18]_lut_out, QC2__clk0, VCC, , TE1L123, , , , );

--TE1_entry_0[18] is std_1c20:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_0[18]

--operation mode is normal

TE1_entry_0[18]_lut_out = S1_M_st_data[18];

TE1_entry_0[18] = DFFEAS(TE1_entry_0[18]_lut_out, QC2__clk0, VCC, , TE1L62, , , , );

--TE1L147 is std_1c20:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|rd_data[18]~523

--operation mode is normal

TE1L147 = TE1_rd_address & TE1_entry_1[18] # !TE1_rd_address & (TE1_entry_0[18]);

--KB1L524 is std_1c20:inst|sdram:the_sdram|Mux131~1170

--operation mode is normal

KB1L524 = KB1_f_select & (KB1_m_state[1] & KB1_active_data[18] # !KB1_m_state[1] & (TE1L147)) # !KB1_f_select & KB1_active_data[18];

--KB1_active_data[17] is std_1c20:inst|sdram:the_sdram|active_data[17]

--operation mode is normal

KB1_active_data[17]_lut_out = KB1L12 & (KB1L14 & (TE1L146) # !KB1L14 & KB1_active_data[17]) # !KB1L12 & KB1_active_data[17];

KB1_active_data[17] = DFFEAS(KB1_active_data[17]_lut_out, QC2__clk0, VCC, , , , , , );

--TE1_entry_1[17] is std_1c20:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_1[17]

--operation mode is normal

TE1_entry_1[17]_lut_out = S1_M_st_data[17];

TE1_entry_1[17] = DFFEAS(TE1_entry_1[17]_lut_out, QC2__clk0, VCC, , TE1L123, , , , );

--TE1_entry_0[17] is std_1c20:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_0[17]

--operation mode is normal

TE1_entry_0[17]_lut_out = S1_M_st_data[17];

TE1_entry_0[17] = DFFEAS(TE1_entry_0[17]_lut_out, QC2__clk0, VCC, , TE1L62, , , , );

--TE1L146 is std_1c20:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|rd_data[17]~524

--operation mode is normal

TE1L146 = TE1_rd_address & TE1_entry_1[17] # !TE1_rd_address & (TE1_entry_0[17]);

--KB1L525 is std_1c20:inst|sdram:the_sdram|Mux132~1170

--operation mode is normal

KB1L525 = KB1_f_select & (KB1_m_state[1] & KB1_active_data[17] # !KB1_m_state[1] & (TE1L146)) # !KB1_f_select & KB1_active_data[17];

--KB1_active_data[16] is std_1c20:inst|sdram:the_sdram|active_data[16]

--operation mode is normal

KB1_active_data[16]_lut_out = KB1L65 & (KB1L66 & TE1L145 # !KB1L66 & (KB1_active_data[16])) # !KB1L65 & (KB1_active_data[16]);

KB1_active_data[16] = DFFEAS(KB1_active_data[16]_lut_out, QC2__clk0, VCC, , , , , , );

--TE1_entry_1[16] is std_1c20:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_1[16]

--operation mode is normal

TE1_entry_1[16]_lut_out = S1_M_st_data[16];

TE1_entry_1[16] = DFFEAS(TE1_entry_1[16]_lut_out, QC2__clk0, VCC, , TE1L123, , , , );

--TE1_entry_0[16] is std_1c20:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_0[16]

--operation mode is normal

TE1_entry_0[16]_lut_out = S1_M_st_data[16];

TE1_entry_0[16] = DFFEAS(TE1_entry_0[16]_lut_out, QC2__clk0, VCC, , TE1L62, , , , );

--TE1L145 is std_1c20:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|rd_data[16]~525

--operation mode is normal

TE1L145 = TE1_rd_address & TE1_entry_1[16] # !TE1_rd_address & (TE1_entry_0[16]);

--KB1L526 is std_1c20:inst|sdram:the_sdram|Mux133~1170

--operation mode is normal

KB1L526 = KB1_f_select & (KB1_m_state[1] & KB1_active_data[16] # !KB1_m_state[1] & (TE1L145)) # !KB1_f_select & KB1_active_data[16];

--KB1_active_data[15] is std_1c20:inst|sdram:the_sdram|active_data[15]

--operation mode is normal

KB1_active_data[15]_lut_out = KB1L12 & (KB1L14 & (TE1L144) # !KB1L14 & KB1_active_data[15]) # !KB1L12 & KB1_active_data[15];

KB1_active_data[15] = DFFEAS(KB1_active_data[15]_lut_out, QC2__clk0, VCC, , , , , , );

--TE1_entry_1[15] is std_1c20:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_1[15]

--operation mode is normal

TE1_entry_1[15]_lut_out = S1_M_st_data[15];

TE1_entry_1[15] = DFFEAS(TE1_entry_1[15]_lut_out, QC2__clk0, VCC, , TE1L123, , , , );

--TE1_entry_0[15] is std_1c20:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_0[15]

--operation mode is normal

TE1_entry_0[15]_lut_out = S1_M_st_data[15];

TE1_entry_0[15] = DFFEAS(TE1_entry_0[15]_lut_out, QC2__clk0, VCC, , TE1L62, , , , );

--TE1L144 is std_1c20:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|rd_data[15]~526

--operation mode is normal

TE1L144 = TE1_rd_address & TE1_entry_1[15] # !TE1_rd_address & (TE1_entry_0[15]);

--KB1L527 is std_1c20:inst|sdram:the_sdram|Mux134~1170

--operation mode is normal

KB1L527 = KB1_f_select & (KB1_m_state[1] & KB1_active_data[15] # !KB1_m_state[1] & (TE1L144)) # !KB1_f_select & KB1_active_data[15];

--KB1_active_data[14] is std_1c20:inst|sdram:the_sdram|active_data[14]

--operation mode is normal

KB1_active_data[14]_lut_out = KB1L65 & (KB1L66 & TE1L143 # !KB1L66 & (KB1_active_data[14])) # !KB1L65 & (KB1_active_data[14]);

KB1_active_data[14] = DFFEAS(KB1_active_data[14]_lut_out, QC2__clk0, VCC, , , , , , );

--TE1_entry_1[14] is std_1c20:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_1[14]

--operation mode is normal

TE1_entry_1[14]_lut_out = S1_M_st_data[14];

TE1_entry_1[14] = DFFEAS(TE1_entry_1[14]_lut_out, QC2__clk0, VCC, , TE1L123, , , , );

--TE1_entry_0[14] is std_1c20:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_0[14]

--operation mode is normal

TE1_entry_0[14]_lut_out = S1_M_st_data[14];

TE1_entry_0[14] = DFFEAS(TE1_entry_0[14]_lut_out, QC2__clk0, VCC, , TE1L62, , , , );

--TE1L143 is std_1c20:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|rd_data[14]~527

--operation mode is normal

TE1L143 = TE1_rd_address & TE1_entry_1[14] # !TE1_rd_address & (TE1_entry_0[14]);

--KB1L528 is std_1c20:inst|sdram:the_sdram|Mux135~1170

--operation mode is normal

KB1L528 = KB1_f_select & (KB1_m_state[1] & KB1_active_data[14] # !KB1_m_state[1] & (TE1L143)) # !KB1_f_select & KB1_active_data[14];

--KB1_active_data[13] is std_1c20:inst|sdram:the_sdram|active_data[13]

--operation mode is normal

KB1_active_data[13]_lut_out = KB1L12 & (KB1L14 & (TE1L142) # !KB1L14 & KB1_active_data[13]) # !KB1L12 & KB1_active_data[13];

KB1_active_data[13] = DFFEAS(KB1_active_data[13]_lut_out, QC2__clk0, VCC, , , , , , );

--TE1_entry_1[13] is std_1c20:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_1[13]

--operation mode is normal

TE1_entry_1[13]_lut_out = S1_M_st_data[13];

TE1_entry_1[13] = DFFEAS(TE1_entry_1[13]_lut_out, QC2__clk0, VCC, , TE1L123, , , , );

--TE1_entry_0[13] is std_1c20:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_0[13]

--operation mode is normal

TE1_entry_0[13]_lut_out = S1_M_st_data[13];

TE1_entry_0[13] = DFFEAS(TE1_entry_0[13]_lut_out, QC2__clk0, VCC, , TE1L62, , , , );

--TE1L142 is std_1c20:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|rd_data[13]~528

--operation mode is normal

TE1L142 = TE1_rd_address & TE1_entry_1[13] # !TE1_rd_address & (TE1_entry_0[13]);

--KB1L529 is std_1c20:inst|sdram:the_sdram|Mux136~1170

--operation mode is normal

KB1L529 = KB1_f_select & (KB1_m_state[1] & KB1_active_data[13] # !KB1_m_state[1] & (TE1L142)) # !KB1_f_select & KB1_active_data[13];

--KB1_active_data[12] is std_1c20:inst|sdram:the_sdram|active_data[12]

--operation mode is normal

KB1_active_data[12]_lut_out = KB1L65 & (KB1L66 & TE1L141 # !KB1L66 & (KB1_active_data[12])) # !KB1L65 & (KB1_active_data[12]);

KB1_active_data[12] = DFFEAS(KB1_active_data[12]_lut_out, QC2__clk0, VCC, , , , , , );

--TE1_entry_1[12] is std_1c20:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_1[12]

--operation mode is normal

TE1_entry_1[12]_lut_out = S1_M_st_data[12];

TE1_entry_1[12] = DFFEAS(TE1_entry_1[12]_lut_out, QC2__clk0, VCC, , TE1L123, , , , );

--TE1_entry_0[12] is std_1c20:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_0[12]

--operation mode is normal

TE1_entry_0[12]_lut_out = S1_M_st_data[12];

TE1_entry_0[12] = DFFEAS(TE1_entry_0[12]_lut_out, QC2__clk0, VCC, , TE1L62, , , , );

--TE1L141 is std_1c20:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|rd_data[12]~529

--operation mode is normal

TE1L141 = TE1_rd_address & TE1_entry_1[12] # !TE1_rd_address & (TE1_entry_0[12]);

--KB1L530 is std_1c20:inst|sdram:the_sdram|Mux137~1170

--operation mode is normal

KB1L530 = KB1_f_select & (KB1_m_state[1] & KB1_active_data[12] # !KB1_m_state[1] & (TE1L141)) # !KB1_f_select & KB1_active_data[12];

--KB1_active_data[11] is std_1c20:inst|sdram:the_sdram|active_data[11]

--operation mode is normal

KB1_active_data[11]_lut_out = KB1L12 & (KB1L14 & (TE1L140) # !KB1L14 & KB1_active_data[11]) # !KB1L12 & KB1_active_data[11];

KB1_active_data[11] = DFFEAS(KB1_active_data[11]_lut_out, QC2__clk0, VCC, , , , , , );

--TE1_entry_1[11] is std_1c20:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_1[11]

--operation mode is normal

TE1_entry_1[11]_lut_out = S1_M_st_data[11];

TE1_entry_1[11] = DFFEAS(TE1_entry_1[11]_lut_out, QC2__clk0, VCC, , TE1L123, , , , );

--TE1_entry_0[11] is std_1c20:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_0[11]

--operation mode is normal

TE1_entry_0[11]_lut_out = S1_M_st_data[11];

TE1_entry_0[11] = DFFEAS(TE1_entry_0[11]_lut_out, QC2__clk0, VCC, , TE1L62, , , , );

--TE1L140 is std_1c20:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|rd_data[11]~530

--operation mode is normal

TE1L140 = TE1_rd_address & TE1_entry_1[11] # !TE1_rd_address & (TE1_entry_0[11]);

--KB1L531 is std_1c20:inst|sdram:the_sdram|Mux138~1170

--operation mode is normal

KB1L531 = KB1_f_select & (KB1_m_state[1] & KB1_active_data[11] # !KB1_m_state[1] & (TE1L140)) # !KB1_f_select & KB1_active_data[11];

--KB1_active_data[10] is std_1c20:inst|sdram:the_sdram|active_data[10]

--operation mode is normal

KB1_active_data[10]_lut_out = KB1L65 & (KB1L66 & TE1L139 # !KB1L66 & (KB1_active_data[10])) # !KB1L65 & (KB1_active_data[10]);

KB1_active_data[10] = DFFEAS(KB1_active_data[10]_lut_out, QC2__clk0, VCC, , , , , , );

--TE1_entry_1[10] is std_1c20:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_1[10]

--operation mode is normal

TE1_entry_1[10]_lut_out = S1_M_st_data[10];

TE1_entry_1[10] = DFFEAS(TE1_entry_1[10]_lut_out, QC2__clk0, VCC, , TE1L123, , , , );

--TE1_entry_0[10] is std_1c20:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_0[10]

--operation mode is normal

TE1_entry_0[10]_lut_out = S1_M_st_data[10];

TE1_entry_0[10] = DFFEAS(TE1_entry_0[10]_lut_out, QC2__clk0, VCC, , TE1L62, , , , );

--TE1L139 is std_1c20:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|rd_data[10]~531

--operation mode is normal

TE1L139 = TE1_rd_address & TE1_entry_1[10] # !TE1_rd_address & (TE1_entry_0[10]);

--KB1L532 is std_1c20:inst|sdram:the_sdram|Mux139~1170

--operation mode is normal

KB1L532 = KB1_f_select & (KB1_m_state[1] & KB1_active_data[10] # !KB1_m_state[1] & (TE1L139)) # !KB1_f_select & KB1_active_data[10];

--KB1_active_data[9] is std_1c20:inst|sdram:the_sdram|active_data[9]

--operation mode is normal

KB1_active_data[9]_lut_out = KB1L12 & (KB1L14 & (TE1L138) # !KB1L14 & KB1_active_data[9]) # !KB1L12 & KB1_active_data[9];

KB1_active_data[9] = DFFEAS(KB1_active_data[9]_lut_out, QC2__clk0, VCC, , , , , , );

--TE1_entry_1[9] is std_1c20:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_1[9]

--operation mode is normal

TE1_entry_1[9]_lut_out = S1_M_st_data[9];

TE1_entry_1[9] = DFFEAS(TE1_entry_1[9]_lut_out, QC2__clk0, VCC, , TE1L123, , , , );

--TE1_entry_0[9] is std_1c20:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_0[9]

--operation mode is normal

TE1_entry_0[9]_lut_out = S1_M_st_data[9];

TE1_entry_0[9] = DFFEAS(TE1_entry_0[9]_lut_out, QC2__clk0, VCC, , TE1L62, , , , );

--TE1L138 is std_1c20:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|rd_data[9]~532

--operation mode is normal

TE1L138 = TE1_rd_address & TE1_entry_1[9] # !TE1_rd_address & (TE1_entry_0[9]);

--KB1L533 is std_1c20:inst|sdram:the_sdram|Mux140~1170

--operation mode is normal

KB1L533 = KB1_f_select & (KB1_m_state[1] & KB1_active_data[9] # !KB1_m_state[1] & (TE1L138)) # !KB1_f_select & KB1_active_data[9];

--KB1_active_data[8] is std_1c20:inst|sdram:the_sdram|active_data[8]

--operation mode is normal

KB1_active_data[8]_lut_out = KB1L65 & (KB1L66 & TE1L137 # !KB1L66 & (KB1_active_data[8])) # !KB1L65 & (KB1_active_data[8]);

KB1_active_data[8] = DFFEAS(KB1_active_data[8]_lut_out, QC2__clk0, VCC, , , , , , );

--TE1_entry_1[8] is std_1c20:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_1[8]

--operation mode is normal

TE1_entry_1[8]_lut_out = S1_M_st_data[8];

TE1_entry_1[8] = DFFEAS(TE1_entry_1[8]_lut_out, QC2__clk0, VCC, , TE1L123, , , , );

--TE1_entry_0[8] is std_1c20:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_0[8]

--operation mode is normal

TE1_entry_0[8]_lut_out = S1_M_st_data[8];

TE1_entry_0[8] = DFFEAS(TE1_entry_0[8]_lut_out, QC2__clk0, VCC, , TE1L62, , , , );

--TE1L137 is std_1c20:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|rd_data[8]~533

--operation mode is normal

TE1L137 = TE1_rd_address & TE1_entry_1[8] # !TE1_rd_address & (TE1_entry_0[8]);

--KB1L534 is std_1c20:inst|sdram:the_sdram|Mux141~1170

--operation mode is normal

KB1L534 = KB1_f_select & (KB1_m_state[1] & KB1_active_data[8] # !KB1_m_state[1] & (TE1L137)) # !KB1_f_select & KB1_active_data[8];

--KB1_active_data[7] is std_1c20:inst|sdram:the_sdram|active_data[7]

--operation mode is normal

KB1_active_data[7]_lut_out = KB1L12 & (KB1L14 & (TE1L136) # !KB1L14 & KB1_active_data[7]) # !KB1L12 & KB1_active_data[7];

KB1_active_data[7] = DFFEAS(KB1_active_data[7]_lut_out, QC2__clk0, VCC, , , , , , );

--TE1_entry_1[7] is std_1c20:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_1[7]

--operation mode is normal

TE1_entry_1[7]_lut_out = S1_M_st_data[7];

TE1_entry_1[7] = DFFEAS(TE1_entry_1[7]_lut_out, QC2__clk0, VCC, , TE1L123, , , , );

--TE1_entry_0[7] is std_1c20:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_0[7]

--operation mode is normal

TE1_entry_0[7]_lut_out = S1_M_st_data[7];

TE1_entry_0[7] = DFFEAS(TE1_entry_0[7]_lut_out, QC2__clk0, VCC, , TE1L62, , , , );

--TE1L136 is std_1c20:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|rd_data[7]~534

--operation mode is normal

TE1L136 = TE1_rd_address & TE1_entry_1[7] # !TE1_rd_address & (TE1_entry_0[7]);

--KB1L535 is std_1c20:inst|sdram:the_sdram|Mux142~1170

--operation mode is normal

KB1L535 = KB1_f_select & (KB1_m_state[1] & KB1_active_data[7] # !KB1_m_state[1] & (TE1L136)) # !KB1_f_select & KB1_active_data[7];

--KB1_active_data[6] is std_1c20:inst|sdram:the_sdram|active_data[6]

--operation mode is normal

KB1_active_data[6]_lut_out = KB1L65 & (KB1L66 & TE1L135 # !KB1L66 & (KB1_active_data[6])) # !KB1L65 & (KB1_active_data[6]);

KB1_active_data[6] = DFFEAS(KB1_active_data[6]_lut_out, QC2__clk0, VCC, , , , , , );

--TE1_entry_1[6] is std_1c20:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_1[6]

--operation mode is normal

TE1_entry_1[6]_lut_out = S1_M_st_data[6];

TE1_entry_1[6] = DFFEAS(TE1_entry_1[6]_lut_out, QC2__clk0, VCC, , TE1L123, , , , );

--TE1_entry_0[6] is std_1c20:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_0[6]

--operation mode is normal

TE1_entry_0[6]_lut_out = S1_M_st_data[6];

TE1_entry_0[6] = DFFEAS(TE1_entry_0[6]_lut_out, QC2__clk0, VCC, , TE1L62, , , , );

--TE1L135 is std_1c20:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|rd_data[6]~535

--operation mode is normal

TE1L135 = TE1_rd_address & TE1_entry_1[6] # !TE1_rd_address & (TE1_entry_0[6]);

--KB1L536 is std_1c20:inst|sdram:the_sdram|Mux143~1170

--operation mode is normal

KB1L536 = KB1_f_select & (KB1_m_state[1] & KB1_active_data[6] # !KB1_m_state[1] & (TE1L135)) # !KB1_f_select & KB1_active_data[6];

--KB1_active_data[5] is std_1c20:inst|sdram:the_sdram|active_data[5]

--operation mode is normal

KB1_active_data[5]_lut_out = KB1L12 & (KB1L14 & (TE1L134) # !KB1L14 & KB1_active_data[5]) # !KB1L12 & KB1_active_data[5];

KB1_active_data[5] = DFFEAS(KB1_active_data[5]_lut_out, QC2__clk0, VCC, , , , , , );

--TE1_entry_1[5] is std_1c20:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_1[5]

--operation mode is normal

TE1_entry_1[5]_lut_out = S1_M_st_data[5];

TE1_entry_1[5] = DFFEAS(TE1_entry_1[5]_lut_out, QC2__clk0, VCC, , TE1L123, , , , );

--TE1_entry_0[5] is std_1c20:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_0[5]

--operation mode is normal

TE1_entry_0[5]_lut_out = S1_M_st_data[5];

TE1_entry_0[5] = DFFEAS(TE1_entry_0[5]_lut_out, QC2__clk0, VCC, , TE1L62, , , , );

--TE1L134 is std_1c20:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|rd_data[5]~536

--operation mode is normal

TE1L134 = TE1_rd_address & TE1_entry_1[5] # !TE1_rd_address & (TE1_entry_0[5]);

--KB1L537 is std_1c20:inst|sdram:the_sdram|Mux144~1170

--operation mode is normal

KB1L537 = KB1_f_select & (KB1_m_state[1] & KB1_active_data[5] # !KB1_m_state[1] & (TE1L134)) # !KB1_f_select & KB1_active_data[5];

--KB1_active_data[4] is std_1c20:inst|sdram:the_sdram|active_data[4]

--operation mode is normal

KB1_active_data[4]_lut_out = KB1L65 & (KB1L66 & TE1L133 # !KB1L66 & (KB1_active_data[4])) # !KB1L65 & (KB1_active_data[4]);

KB1_active_data[4] = DFFEAS(KB1_active_data[4]_lut_out, QC2__clk0, VCC, , , , , , );

--TE1_entry_1[4] is std_1c20:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_1[4]

--operation mode is normal

TE1_entry_1[4]_lut_out = S1_M_st_data[4];

TE1_entry_1[4] = DFFEAS(TE1_entry_1[4]_lut_out, QC2__clk0, VCC, , TE1L123, , , , );

--TE1_entry_0[4] is std_1c20:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_0[4]

--operation mode is normal

TE1_entry_0[4]_lut_out = S1_M_st_data[4];

TE1_entry_0[4] = DFFEAS(TE1_entry_0[4]_lut_out, QC2__clk0, VCC, , TE1L62, , , , );

--TE1L133 is std_1c20:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|rd_data[4]~537

--operation mode is normal

TE1L133 = TE1_rd_address & TE1_entry_1[4] # !TE1_rd_address & (TE1_entry_0[4]);

--KB1L538 is std_1c20:inst|sdram:the_sdram|Mux145~1170

--operation mode is normal

KB1L538 = KB1_f_select & (KB1_m_state[1] & KB1_active_data[4] # !KB1_m_state[1] & (TE1L133)) # !KB1_f_select & KB1_active_data[4];

--KB1_active_data[3] is std_1c20:inst|sdram:the_sdram|active_data[3]

--operation mode is normal

KB1_active_data[3]_lut_out = KB1L12 & (KB1L14 & (TE1L132) # !KB1L14 & KB1_active_data[3]) # !KB1L12 & KB1_active_data[3];

KB1_active_data[3] = DFFEAS(KB1_active_data[3]_lut_out, QC2__clk0, VCC, , , , , , );

--TE1_entry_1[3] is std_1c20:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_1[3]

--operation mode is normal

TE1_entry_1[3]_lut_out = S1_M_st_data[3];

TE1_entry_1[3] = DFFEAS(TE1_entry_1[3]_lut_out, QC2__clk0, VCC, , TE1L123, , , , );

--TE1_entry_0[3] is std_1c20:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_0[3]

--operation mode is normal

TE1_entry_0[3]_lut_out = S1_M_st_data[3];

TE1_entry_0[3] = DFFEAS(TE1_entry_0[3]_lut_out, QC2__clk0, VCC, , TE1L62, , , , );

--TE1L132 is std_1c20:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|rd_data[3]~538

--operation mode is normal

TE1L132 = TE1_rd_address & TE1_entry_1[3] # !TE1_rd_address & (TE1_entry_0[3]);

--KB1L539 is std_1c20:inst|sdram:the_sdram|Mux146~1170

--operation mode is normal

KB1L539 = KB1_f_select & (KB1_m_state[1] & KB1_active_data[3] # !KB1_m_state[1] & (TE1L132)) # !KB1_f_select & KB1_active_data[3];

--KB1_active_data[2] is std_1c20:inst|sdram:the_sdram|active_data[2]

--operation mode is normal

KB1_active_data[2]_lut_out = KB1L65 & (KB1L66 & TE1L131 # !KB1L66 & (KB1_active_data[2])) # !KB1L65 & (KB1_active_data[2]);

KB1_active_data[2] = DFFEAS(KB1_active_data[2]_lut_out, QC2__clk0, VCC, , , , , , );

--TE1_entry_1[2] is std_1c20:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_1[2]

--operation mode is normal

TE1_entry_1[2]_lut_out = S1_M_st_data[2];

TE1_entry_1[2] = DFFEAS(TE1_entry_1[2]_lut_out, QC2__clk0, VCC, , TE1L123, , , , );

--TE1_entry_0[2] is std_1c20:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_0[2]

--operation mode is normal

TE1_entry_0[2]_lut_out = S1_M_st_data[2];

TE1_entry_0[2] = DFFEAS(TE1_entry_0[2]_lut_out, QC2__clk0, VCC, , TE1L62, , , , );

--TE1L131 is std_1c20:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|rd_data[2]~539

--operation mode is normal

TE1L131 = TE1_rd_address & TE1_entry_1[2] # !TE1_rd_address & (TE1_entry_0[2]);

--KB1L540 is std_1c20:inst|sdram:the_sdram|Mux147~1170

--operation mode is normal

KB1L540 = KB1_f_select & (KB1_m_state[1] & KB1_active_data[2] # !KB1_m_state[1] & (TE1L131)) # !KB1_f_select & KB1_active_data[2];

--KB1_active_data[1] is std_1c20:inst|sdram:the_sdram|active_data[1]

--operation mode is normal

KB1_active_data[1]_lut_out = KB1L12 & (KB1L14 & (TE1L130) # !KB1L14 & KB1_active_data[1]) # !KB1L12 & KB1_active_data[1];

KB1_active_data[1] = DFFEAS(KB1_active_data[1]_lut_out, QC2__clk0, VCC, , , , , , );

--TE1_entry_1[1] is std_1c20:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_1[1]

--operation mode is normal

TE1_entry_1[1]_lut_out = S1_M_st_data[1];

TE1_entry_1[1] = DFFEAS(TE1_entry_1[1]_lut_out, QC2__clk0, VCC, , TE1L123, , , , );

--TE1_entry_0[1] is std_1c20:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_0[1]

--operation mode is normal

TE1_entry_0[1]_lut_out = S1_M_st_data[1];

TE1_entry_0[1] = DFFEAS(TE1_entry_0[1]_lut_out, QC2__clk0, VCC, , TE1L62, , , , );

--TE1L130 is std_1c20:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|rd_data[1]~540

--operation mode is normal

TE1L130 = TE1_rd_address & TE1_entry_1[1] # !TE1_rd_address & (TE1_entry_0[1]);

--KB1L541 is std_1c20:inst|sdram:the_sdram|Mux148~1170

--operation mode is normal

KB1L541 = KB1_f_select & (KB1_m_state[1] & KB1_active_data[1] # !KB1_m_state[1] & (TE1L130)) # !KB1_f_select & KB1_active_data[1];

--KB1_active_data[0] is std_1c20:inst|sdram:the_sdram|active_data[0]

--operation mode is normal

KB1_active_data[0]_lut_out = KB1L65 & (KB1L66 & TE1L129 # !KB1L66 & (KB1_active_data[0])) # !KB1L65 & (KB1_active_data[0]);

KB1_active_data[0] = DFFEAS(KB1_active_data[0]_lut_out, QC2__clk0, VCC, , , , , , );

--TE1_entry_1[0] is std_1c20:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_1[0]

--operation mode is normal

TE1_entry_1[0]_lut_out = S1_M_st_data[0];

TE1_entry_1[0] = DFFEAS(TE1_entry_1[0]_lut_out, QC2__clk0, VCC, , TE1L123, , , , );

--TE1_entry_0[0] is std_1c20:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_0[0]

--operation mode is normal

TE1_entry_0[0]_lut_out = S1_M_st_data[0];

TE1_entry_0[0] = DFFEAS(TE1_entry_0[0]_lut_out, QC2__clk0, VCC, , TE1L62, , , , );

--TE1L129 is std_1c20:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|rd_data[0]~541

--operation mode is normal

TE1L129 = TE1_rd_address & TE1_entry_1[0] # !TE1_rd_address & (TE1_entry_0[0]);

--KB1L542 is std_1c20:inst|sdram:the_sdram|Mux149~1170

--operation mode is normal

KB1L542 = KB1_f_select & (KB1_m_state[1] & KB1_active_data[0] # !KB1_m_state[1] & (TE1L129)) # !KB1_f_select & KB1_active_data[0];

--S1L116 is std_1c20:inst|cpu:the_cpu|Add6~108

--operation mode is normal

S1L116 = AMPP_FUNCTION(S1_ic_fill_ap_cnt[2], S1_ic_fill_ap_cnt[1], S1_ic_fill_ap_cnt[0]);

--S1L117 is std_1c20:inst|cpu:the_cpu|Add6~109

--operation mode is normal

S1L117 = AMPP_FUNCTION(S1_ic_fill_ap_cnt[1], S1_ic_fill_ap_cnt[0]);

--NB1L56 is std_1c20:inst|sdram_s1_arbitrator:the_sdram_s1|sdram_s1_arb_counter_enable~44

--operation mode is normal

NB1L56 = NB1_WideOr1 # !NB1L21 & !NB1L17;

--S1L35 is std_1c20:inst|cpu:the_cpu|A_WE_StdLogicVector~14115

--operation mode is normal

S1L35 = AMPP_FUNCTION(S1L98, S1L896, S1_D_issue, S1L175);

--S1_M_pipe_flush_waddr[12] is std_1c20:inst|cpu:the_cpu|M_pipe_flush_waddr[12]

--operation mode is normal

S1_M_pipe_flush_waddr[12] = AMPP_FUNCTION(QC2__clk0, S1L50, S1L583, S1_E_pc[12], S1_E_ctrl_jmp_indirect, F1_data_out, S1_E_hbreak_req, S1_W_stall);

--S1L36 is std_1c20:inst|cpu:the_cpu|A_WE_StdLogicVector~14116

--operation mode is normal

S1L36 = AMPP_FUNCTION(S1L90, S1L904, S1_D_issue, S1L175);

--S1_M_pipe_flush_waddr[16] is std_1c20:inst|cpu:the_cpu|M_pipe_flush_waddr[16]

--operation mode is normal

S1_M_pipe_flush_waddr[16] = AMPP_FUNCTION(QC2__clk0, S1L51, S1L587, S1_E_pc[16], S1_E_ctrl_jmp_indirect, F1_data_out, S1_E_hbreak_req, S1_W_stall);

--S1_ic_tag_clr_valid_bits is std_1c20:inst|cpu:the_cpu|ic_tag_clr_valid_bits

--operation mode is normal

S1_ic_tag_clr_valid_bits = AMPP_FUNCTION(QC2__clk0, S1_ic_tag_clr_valid_bits_nxt, F1_data_out);

--S1_ic_tag_wren is std_1c20:inst|cpu:the_cpu|ic_tag_wren

--operation mode is normal

S1_ic_tag_wren = AMPP_FUNCTION(S1_i_readdatavalid_d1, S1_ic_tag_clr_valid_bits);

--S1_ic_tag_wraddress[0] is std_1c20:inst|cpu:the_cpu|ic_tag_wraddress[0]

--operation mode is normal

S1_ic_tag_wraddress[0] = AMPP_FUNCTION(QC2__clk0, S1_M_alu_result[5], S1L1004, S1L1006, S1_reset_d1, F1_data_out);

--S1L820 is std_1c20:inst|cpu:the_cpu|F_ic_tag_rd_addr_nxt[0]~4242

--operation mode is normal

S1L820 = AMPP_FUNCTION(S1_D_br_taken_waddr_partial[3], S1L878, S1_D_issue, S1L175);

--S1_M_pipe_flush_waddr[3] is std_1c20:inst|cpu:the_cpu|M_pipe_flush_waddr[3]

--operation mode is normal

S1_M_pipe_flush_waddr[3] = AMPP_FUNCTION(QC2__clk0, S1L52, S1L574, S1_E_pc[3], S1_E_ctrl_jmp_indirect, F1_data_out, S1_E_hbreak_req, S1_W_stall);

--S1L821 is std_1c20:inst|cpu:the_cpu|F_ic_tag_rd_addr_nxt[0]~4243

--operation mode is normal

S1L821 = AMPP_FUNCTION(S1L822, S1_M_pipe_flush_waddr[3], S1_M_pipe_flush);

--S1L823 is std_1c20:inst|cpu:the_cpu|F_ic_tag_rd_addr_nxt[1]~4244

--operation mode is normal

S1L823 = AMPP_FUNCTION(S1_D_br_taken_waddr_partial[4], S1L880, S1_D_issue, S1L175);

--S1_M_pipe_flush_waddr[4] is std_1c20:inst|cpu:the_cpu|M_pipe_flush_waddr[4]

--operation mode is normal

S1_M_pipe_flush_waddr[4] = AMPP_FUNCTION(QC2__clk0, S1L53, S1L575, S1_E_pc[4], S1_E_ctrl_jmp_indirect, F1_data_out, S1_E_hbreak_req, S1_W_stall);

--S1L824 is std_1c20:inst|cpu:the_cpu|F_ic_tag_rd_addr_nxt[1]~4245

--operation mode is normal

S1L824 = AMPP_FUNCTION(S1L825, S1_M_pipe_flush_waddr[4], S1_M_pipe_flush);

--S1L826 is std_1c20:inst|cpu:the_cpu|F_ic_tag_rd_addr_nxt[2]~4246

--operation mode is normal

S1L826 = AMPP_FUNCTION(S1_D_br_taken_waddr_partial[5], S1L882, S1_D_issue, S1L175);

--S1_M_pipe_flush_waddr[5] is std_1c20:inst|cpu:the_cpu|M_pipe_flush_waddr[5]

--operation mode is normal

S1_M_pipe_flush_waddr[5] = AMPP_FUNCTION(QC2__clk0, S1L54, S1L576, S1_E_pc[5], S1_E_ctrl_jmp_indirect, F1_data_out, S1_E_hbreak_req, S1_W_stall);

--S1L827 is std_1c20:inst|cpu:the_cpu|F_ic_tag_rd_addr_nxt[2]~4247

--operation mode is normal

S1L827 = AMPP_FUNCTION(S1L828, S1_M_pipe_flush_waddr[5], S1_M_pipe_flush);

--S1L829 is std_1c20:inst|cpu:the_cpu|F_ic_tag_rd_addr_nxt[3]~4248

--operation mode is normal

S1L829 = AMPP_FUNCTION(S1_D_br_taken_waddr_partial[6], S1L884, S1_D_issue, S1L175);

--S1_M_pipe_flush_waddr[6] is std_1c20:inst|cpu:the_cpu|M_pipe_flush_waddr[6]

--operation mode is normal

S1_M_pipe_flush_waddr[6] = AMPP_FUNCTION(QC2__clk0, S1L55, S1L577, S1_E_pc[6], S1_E_ctrl_jmp_indirect, F1_data_out, S1_E_hbreak_req, S1_W_stall);

--S1L830 is std_1c20:inst|cpu:the_cpu|F_ic_tag_rd_addr_nxt[3]~4249

--operation mode is normal

S1L830 = AMPP_FUNCTION(S1L831, S1_M_pipe_flush_waddr[6], S1_M_pipe_flush);

--S1L832 is std_1c20:inst|cpu:the_cpu|F_ic_tag_rd_addr_nxt[4]~4250

--operation mode is normal

S1L832 = AMPP_FUNCTION(S1_D_br_taken_waddr_partial[7], S1L886, S1_D_issue, S1L175);

--S1_M_pipe_flush_waddr[7] is std_1c20:inst|cpu:the_cpu|M_pipe_flush_waddr[7]

--operation mode is normal

S1_M_pipe_flush_waddr[7] = AMPP_FUNCTION(QC2__clk0, S1L56, S1L578, S1_E_pc[7], S1_E_ctrl_jmp_indirect, F1_data_out, S1_E_hbreak_req, S1_W_stall);

--S1L833 is std_1c20:inst|cpu:the_cpu|F_ic_tag_rd_addr_nxt[4]~4251

--operation mode is normal

S1L833 = AMPP_FUNCTION(S1L834, S1_M_pipe_flush_waddr[7], S1_M_pipe_flush);

--S1L835 is std_1c20:inst|cpu:the_cpu|F_ic_tag_rd_addr_nxt[5]~4252

--operation mode is normal

S1L835 = AMPP_FUNCTION(S1_D_br_taken_waddr_partial[8], S1L888, S1_D_issue, S1L175);

--S1_M_pipe_flush_waddr[8] is std_1c20:inst|cpu:the_cpu|M_pipe_flush_waddr[8]

--operation mode is normal

S1_M_pipe_flush_waddr[8] = AMPP_FUNCTION(QC2__clk0, S1L57, S1L579, S1_E_pc[8], S1_E_ctrl_jmp_indirect, F1_data_out, S1_E_hbreak_req, S1_W_stall);

--S1L836 is std_1c20:inst|cpu:the_cpu|F_ic_tag_rd_addr_nxt[5]~4253

--operation mode is normal

S1L836 = AMPP_FUNCTION(S1L837, S1_M_pipe_flush_waddr[8], S1_M_pipe_flush);

--S1L838 is std_1c20:inst|cpu:the_cpu|F_ic_tag_rd_addr_nxt[6]~4254

--operation mode is normal

S1L838 = AMPP_FUNCTION(S1_D_br_taken_waddr_partial[9], S1L890, S1_D_issue, S1L175);

--S1_M_pipe_flush_waddr[9] is std_1c20:inst|cpu:the_cpu|M_pipe_flush_waddr[9]

--operation mode is normal

S1_M_pipe_flush_waddr[9] = AMPP_FUNCTION(QC2__clk0, S1L58, S1L580, S1_E_pc[9], S1_E_ctrl_jmp_indirect, F1_data_out, S1_E_hbreak_req, S1_W_stall);

--S1L839 is std_1c20:inst|cpu:the_cpu|F_ic_tag_rd_addr_nxt[6]~4255

--operation mode is normal

S1L839 = AMPP_FUNCTION(S1L840, S1_M_pipe_flush_waddr[9], S1_M_pipe_flush);

--S1L37 is std_1c20:inst|cpu:the_cpu|A_WE_StdLogicVector~14117

--operation mode is normal

S1L37 = AMPP_FUNCTION(S1L84, S1L912, S1_D_issue, S1L175);

--S1_M_pipe_flush_waddr[20] is std_1c20:inst|cpu:the_cpu|M_pipe_flush_waddr[20]

--operation mode is normal

S1_M_pipe_flush_waddr[20] = AMPP_FUNCTION(QC2__clk0, S1L59, S1L591, S1_E_pc[20], S1_E_ctrl_jmp_indirect, F1_data_out, S1_E_hbreak_req, S1_W_stall);

--S1L38 is std_1c20:inst|cpu:the_cpu|A_WE_StdLogicVector~14118

--operation mode is normal

S1L38 = AMPP_FUNCTION(S1L86, S1L910, S1_D_issue, S1L175);

--S1_M_pipe_flush_waddr[19] is std_1c20:inst|cpu:the_cpu|M_pipe_flush_waddr[19]

--operation mode is normal

S1_M_pipe_flush_waddr[19] = AMPP_FUNCTION(QC2__clk0, S1L60, S1L590, S1_E_pc[19], S1_E_ctrl_jmp_indirect, F1_data_out, S1_E_hbreak_req, S1_W_stall);

--S1L39 is std_1c20:inst|cpu:the_cpu|A_WE_StdLogicVector~14119

--operation mode is normal

S1L39 = AMPP_FUNCTION(S1L107, S1L908, S1_D_issue, S1L175);

--S1_M_pipe_flush_waddr[18] is std_1c20:inst|cpu:the_cpu|M_pipe_flush_waddr[18]

--operation mode is normal

S1_M_pipe_flush_waddr[18] = AMPP_FUNCTION(QC2__clk0, S1L62, S1L589, S1_E_pc[18], S1_E_ctrl_jmp_indirect, F1_data_out, S1_E_hbreak_req, S1_W_stall);

--S1L40 is std_1c20:inst|cpu:the_cpu|A_WE_StdLogicVector~14120

--operation mode is normal

S1L40 = AMPP_FUNCTION(S1L88, S1L906, S1_D_issue, S1L175);

--S1_M_pipe_flush_waddr[17] is std_1c20:inst|cpu:the_cpu|M_pipe_flush_waddr[17]

--operation mode is normal

S1_M_pipe_flush_waddr[17] = AMPP_FUNCTION(QC2__clk0, S1L63, S1L588, S1_E_pc[17], S1_E_ctrl_jmp_indirect, F1_data_out, S1_E_hbreak_req, S1_W_stall);

--S1L41 is std_1c20:inst|cpu:the_cpu|A_WE_StdLogicVector~14121

--operation mode is normal

S1L41 = AMPP_FUNCTION(S1L109, S1L914, S1_D_issue, S1L175);

--S1_M_pipe_flush_waddr[21] is std_1c20:inst|cpu:the_cpu|M_pipe_flush_waddr[21]

--operation mode is normal

S1_M_pipe_flush_waddr[21] = AMPP_FUNCTION(QC2__clk0, S1L64, S1L592, S1_E_pc[21], S1_E_ctrl_jmp_indirect, F1_data_out, S1_E_hbreak_req, S1_W_stall);

--S1L42 is std_1c20:inst|cpu:the_cpu|A_WE_StdLogicVector~14122

--operation mode is normal

S1L42 = AMPP_FUNCTION(S1L94, S1L900, S1_D_issue, S1L175);

--S1_M_pipe_flush_waddr[14] is std_1c20:inst|cpu:the_cpu|M_pipe_flush_waddr[14]

--operation mode is normal

S1_M_pipe_flush_waddr[14] = AMPP_FUNCTION(QC2__clk0, S1L65, S1L585, S1_E_pc[14], S1_E_ctrl_jmp_indirect, F1_data_out, S1_E_hbreak_req, S1_W_stall);

--S1L43 is std_1c20:inst|cpu:the_cpu|A_WE_StdLogicVector~14123

--operation mode is normal

S1L43 = AMPP_FUNCTION(S1L100, S1L894, S1_D_issue, S1L175);

--S1_M_pipe_flush_waddr[11] is std_1c20:inst|cpu:the_cpu|M_pipe_flush_waddr[11]

--operation mode is normal

S1_M_pipe_flush_waddr[11] = AMPP_FUNCTION(QC2__clk0, S1L66, S1L582, S1_E_pc[11], S1_E_ctrl_jmp_indirect, F1_data_out, S1_E_hbreak_req, S1_W_stall);

--S1L44 is std_1c20:inst|cpu:the_cpu|A_WE_StdLogicVector~14124

--operation mode is normal

S1L44 = AMPP_FUNCTION(S1L92, S1L916, S1_D_issue, S1L175);

--S1_M_pipe_flush_waddr[22] is std_1c20:inst|cpu:the_cpu|M_pipe_flush_waddr[22]

--operation mode is normal

S1_M_pipe_flush_waddr[22] = AMPP_FUNCTION(QC2__clk0, S1L68, S1L593, S1_E_pc[22], S1_E_ctrl_jmp_indirect, F1_data_out, S1_E_hbreak_req, S1_W_stall);

--S1L45 is std_1c20:inst|cpu:the_cpu|A_WE_StdLogicVector~14125

--operation mode is normal

S1L45 = AMPP_FUNCTION(S1L106, S1L918, S1_D_issue, S1L175);

--S1_M_pipe_flush_waddr[23] is std_1c20:inst|cpu:the_cpu|M_pipe_flush_waddr[23]

--operation mode is normal

S1_M_pipe_flush_waddr[23] = AMPP_FUNCTION(QC2__clk0, S1L70, S1L594, S1_E_pc[23], S1_E_ctrl_jmp_indirect, F1_data_out, S1_E_hbreak_req, S1_W_stall);

--S1L46 is std_1c20:inst|cpu:the_cpu|A_WE_StdLogicVector~14126

--operation mode is normal

S1L46 = AMPP_FUNCTION(S1L104, S1L902, S1_D_issue, S1L175);

--S1_M_pipe_flush_waddr[15] is std_1c20:inst|cpu:the_cpu|M_pipe_flush_waddr[15]

--operation mode is normal

S1_M_pipe_flush_waddr[15] = AMPP_FUNCTION(QC2__clk0, S1L72, S1L586, S1_E_pc[15], S1_E_ctrl_jmp_indirect, F1_data_out, S1_E_hbreak_req, S1_W_stall);

--S1L47 is std_1c20:inst|cpu:the_cpu|A_WE_StdLogicVector~14127

--operation mode is normal

S1L47 = AMPP_FUNCTION(S1L96, S1L898, S1_D_issue, S1L175);

--S1_M_pipe_flush_waddr[13] is std_1c20:inst|cpu:the_cpu|M_pipe_flush_waddr[13]

--operation mode is normal

S1_M_pipe_flush_waddr[13] = AMPP_FUNCTION(QC2__clk0, S1L73, S1L584, S1_E_pc[13], S1_E_ctrl_jmp_indirect, F1_data_out, S1_E_hbreak_req, S1_W_stall);

--S1L48 is std_1c20:inst|cpu:the_cpu|A_WE_StdLogicVector~14128

--operation mode is normal

S1L48 = AMPP_FUNCTION(S1L102, S1L892, S1_D_issue, S1L175);

--S1_M_pipe_flush_waddr[10] is std_1c20:inst|cpu:the_cpu|M_pipe_flush_waddr[10]

--operation mode is normal

S1_M_pipe_flush_waddr[10] = AMPP_FUNCTION(QC2__clk0, S1L74, S1L581, S1_E_pc[10], S1_E_ctrl_jmp_indirect, F1_data_out, S1_E_hbreak_req, S1_W_stall);

--S1_ic_fill_valid_bits[5] is std_1c20:inst|cpu:the_cpu|ic_fill_valid_bits[5]

--operation mode is normal

S1_ic_fill_valid_bits[5] = AMPP_FUNCTION(QC2__clk0, S1L1038, S1_ic_fill_valid_bits[5], S1_D_ic_fill_starting_d1, S1_ic_tag_clr_valid_bits_nxt, F1_data_out, S1_ic_fill_valid_bits_en);

--S1L794 is std_1c20:inst|cpu:the_cpu|F_ic_data_rd_addr_nxt[2]~1818

--operation mode is normal

S1L794 = AMPP_FUNCTION(S1_D_br_taken_waddr_partial[2], S1L876, S1_D_issue, S1L175);

--S1_M_pipe_flush_waddr[2] is std_1c20:inst|cpu:the_cpu|M_pipe_flush_waddr[2]

--operation mode is normal

S1_M_pipe_flush_waddr[2] = AMPP_FUNCTION(QC2__clk0, S1L75, S1L573, S1_E_pc[2], S1_E_ctrl_jmp_indirect, F1_data_out, S1_E_hbreak_req, S1_W_stall);

--S1L795 is std_1c20:inst|cpu:the_cpu|F_ic_data_rd_addr_nxt[2]~1819

--operation mode is normal

S1L795 = AMPP_FUNCTION(S1L796, S1_M_pipe_flush_waddr[2], S1_M_pipe_flush);

--S1_ic_fill_valid_bits[3] is std_1c20:inst|cpu:the_cpu|ic_fill_valid_bits[3]

--operation mode is normal

S1_ic_fill_valid_bits[3] = AMPP_FUNCTION(QC2__clk0, S1L1036, S1_ic_fill_valid_bits[3], S1_D_ic_fill_starting_d1, S1_ic_tag_clr_valid_bits_nxt, F1_data_out, S1_ic_fill_valid_bits_en);

--S1L791 is std_1c20:inst|cpu:the_cpu|F_ic_data_rd_addr_nxt[1]~1820

--operation mode is normal

S1L791 = AMPP_FUNCTION(S1_D_br_taken_waddr_partial[1], S1L874, S1_D_issue, S1L175);

--S1_M_pipe_flush_waddr[1] is std_1c20:inst|cpu:the_cpu|M_pipe_flush_waddr[1]

--operation mode is normal

S1_M_pipe_flush_waddr[1] = AMPP_FUNCTION(QC2__clk0, S1L76, S1L572, S1_E_pc[1], S1_E_ctrl_jmp_indirect, F1_data_out, S1_E_hbreak_req, S1_W_stall);

--S1L792 is std_1c20:inst|cpu:the_cpu|F_ic_data_rd_addr_nxt[1]~1821

--operation mode is normal

S1L792 = AMPP_FUNCTION(S1L793, S1_M_pipe_flush_waddr[1], S1_M_pipe_flush);

--S1_ic_fill_valid_bits[1] is std_1c20:inst|cpu:the_cpu|ic_fill_valid_bits[1]

--operation mode is normal

S1_ic_fill_valid_bits[1] = AMPP_FUNCTION(QC2__clk0, S1L1034, S1_ic_fill_valid_bits[1], S1_D_ic_fill_starting_d1, S1_ic_tag_clr_valid_bits_nxt, F1_data_out, S1_ic_fill_valid_bits_en);

--S1_ic_fill_valid_bits[7] is std_1c20:inst|cpu:the_cpu|ic_fill_valid_bits[7]

--operation mode is normal

S1_ic_fill_valid_bits[7] = AMPP_FUNCTION(QC2__clk0, S1L1039, S1_ic_fill_valid_bits[7], S1_D_ic_fill_starting_d1, S1_ic_tag_clr_valid_bits_nxt, F1_data_out, S1_ic_fill_valid_bits_en);

--S1_ic_fill_valid_bits[2] is std_1c20:inst|cpu:the_cpu|ic_fill_valid_bits[2]

--operation mode is normal

S1_ic_fill_valid_bits[2] = AMPP_FUNCTION(QC2__clk0, S1L1035, S1_ic_fill_valid_bits[2], S1_D_ic_fill_starting_d1, S1_ic_tag_clr_valid_bits_nxt, F1_data_out, S1_ic_fill_valid_bits_en);

--S1_ic_fill_valid_bits[4] is std_1c20:inst|cpu:the_cpu|ic_fill_valid_bits[4]

--operation mode is normal

S1_ic_fill_valid_bits[4] = AMPP_FUNCTION(QC2__clk0, S1L1037, S1_ic_fill_valid_bits[4], S1_D_ic_fill_starting_d1, S1_ic_tag_clr_valid_bits_nxt, F1_data_out, S1_ic_fill_valid_bits_en);

--S1_ic_fill_valid_bits[0] is std_1c20:inst|cpu:the_cpu|ic_fill_valid_bits[0]

--operation mode is normal

S1_ic_fill_valid_bits[0] = AMPP_FUNCTION(QC2__clk0, S1L1033, S1_ic_fill_valid_bits[0], S1_D_ic_fill_starting_d1, S1_ic_tag_clr_valid_bits_nxt, F1_data_out, S1_ic_fill_valid_bits_en);

--S1_ic_fill_valid_bits[6] is std_1c20:inst|cpu:the_cpu|ic_fill_valid_bits[6]

--operation mode is normal

S1_ic_fill_valid_bits[6] = AMPP_FUNCTION(QC2__clk0, S1L779, S1_ic_fill_valid_bits[6], S1_D_ic_fill_starting_d1, S1_ic_tag_clr_valid_bits_nxt, F1_data_out, S1_ic_fill_valid_bits_en);

--S1L788 is std_1c20:inst|cpu:the_cpu|F_ic_data_rd_addr_nxt[0]~1822

--operation mode is normal

S1L788 = AMPP_FUNCTION(S1_D_br_taken_waddr_partial[0], S1L872, S1_D_issue, S1L175);

--S1_M_pipe_flush_waddr[0] is std_1c20:inst|cpu:the_cpu|M_pipe_flush_waddr[0]

--operation mode is normal

S1_M_pipe_flush_waddr[0] = AMPP_FUNCTION(QC2__clk0, S1L77, S1L571, S1_E_pc[0], S1_E_ctrl_jmp_indirect, F1_data_out, S1_E_hbreak_req, S1_W_stall);

--S1L789 is std_1c20:inst|cpu:the_cpu|F_ic_data_rd_addr_nxt[0]~1823

--operation mode is normal

S1L789 = AMPP_FUNCTION(S1L790, S1_M_pipe_flush_waddr[0], S1_M_pipe_flush);

--S1L433 is std_1c20:inst|cpu:the_cpu|E_ctrl_invalidate_i~119

--operation mode is normal

S1L433 = AMPP_FUNCTION(S1_E_iw[11], S1_E_iw[16], S1_E_iw[13], S1_E_iw[15]);

--U1_cpu_instruction_master_read_but_no_slave_selected is std_1c20:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_read_but_no_slave_selected

--operation mode is normal

U1_cpu_instruction_master_read_but_no_slave_selected_lut_out = S1_internal_i_read & U1L133 & U1L131 & U1L7;

U1_cpu_instruction_master_read_but_no_slave_selected = DFFEAS(U1_cpu_instruction_master_read_but_no_slave_selected_lut_out, QC2__clk0, F1_data_out, , , , , , );

--U1_cpu_instruction_master_dbs_rdv_counter[1] is std_1c20:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_dbs_rdv_counter[1]

--operation mode is normal

U1_cpu_instruction_master_dbs_rdv_counter[1]_lut_out = U1_cpu_instruction_master_dbs_rdv_counter[1] $ U1_cpu_instruction_master_dbs_rdv_counter[0];

U1_cpu_instruction_master_dbs_rdv_counter[1] = DFFEAS(U1_cpu_instruction_master_dbs_rdv_counter[1]_lut_out, QC2__clk0, F1_data_out, , Y1_cpu_instruction_master_read_data_valid_ext_flash_s1_shift_register[1], , , , );

--U1_cpu_instruction_master_dbs_rdv_counter[0] is std_1c20:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_dbs_rdv_counter[0]

--operation mode is normal

U1_cpu_instruction_master_dbs_rdv_counter[0]_lut_out = !U1_cpu_instruction_master_dbs_rdv_counter[0];

U1_cpu_instruction_master_dbs_rdv_counter[0] = DFFEAS(U1_cpu_instruction_master_dbs_rdv_counter[0]_lut_out, QC2__clk0, F1_data_out, , Y1_cpu_instruction_master_read_data_valid_ext_flash_s1_shift_register[1], , , , );

--Y1_cpu_instruction_master_read_data_valid_ext_flash_s1_shift_register[1] is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|cpu_instruction_master_read_data_valid_ext_flash_s1_shift_register[1]

--operation mode is normal

Y1_cpu_instruction_master_read_data_valid_ext_flash_s1_shift_register[1]_lut_out = Y1_cpu_instruction_master_read_data_valid_ext_flash_s1_shift_register[0];

Y1_cpu_instruction_master_read_data_valid_ext_flash_s1_shift_register[1] = DFFEAS(Y1_cpu_instruction_master_read_data_valid_ext_flash_s1_shift_register[1]_lut_out, QC2__clk0, F1_data_out, , , , , , );

--U1L102 is std_1c20:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_readdatavalid~148

--operation mode is normal

U1L102 = U1_cpu_instruction_master_read_but_no_slave_selected # U1_cpu_instruction_master_dbs_rdv_counter[1] & U1_cpu_instruction_master_dbs_rdv_counter[0] & Y1_cpu_instruction_master_read_data_valid_ext_flash_s1_shift_register[1];

--Y1_cpu_instruction_master_read_data_valid_lan91c111_s1_shift_register[1] is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|cpu_instruction_master_read_data_valid_lan91c111_s1_shift_register[1]

--operation mode is normal

Y1_cpu_instruction_master_read_data_valid_lan91c111_s1_shift_register[1]_lut_out = Y1_cpu_instruction_master_read_data_valid_lan91c111_s1_shift_register[0];

Y1_cpu_instruction_master_read_data_valid_lan91c111_s1_shift_register[1] = DFFEAS(Y1_cpu_instruction_master_read_data_valid_lan91c111_s1_shift_register[1]_lut_out, QC2__clk0, F1_data_out, , , , , , );

--Y1_cpu_instruction_master_read_data_valid_ext_ram_s1_shift_register[1] is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|cpu_instruction_master_read_data_valid_ext_ram_s1_shift_register[1]

--operation mode is normal

Y1_cpu_instruction_master_read_data_valid_ext_ram_s1_shift_register[1]_lut_out = Y1_cpu_instruction_master_read_data_valid_ext_ram_s1_shift_register[0];

Y1_cpu_instruction_master_read_data_valid_ext_ram_s1_shift_register[1] = DFFEAS(Y1_cpu_instruction_master_read_data_valid_ext_ram_s1_shift_register[1]_lut_out, QC2__clk0, F1_data_out, , , , , , );

--NB1_cpu_instruction_master_read_data_valid_sdram_s1 is std_1c20:inst|sdram_s1_arbitrator:the_sdram_s1|cpu_instruction_master_read_data_valid_sdram_s1

--operation mode is normal

NB1_cpu_instruction_master_read_data_valid_sdram_s1 = WE1_fifo_contains_ones_n & KB1_za_valid & WE1_stage_0;

--U1L103 is std_1c20:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_readdatavalid~149

--operation mode is normal

U1L103 = U1L102 # Y1_cpu_instruction_master_read_data_valid_lan91c111_s1_shift_register[1] # Y1_cpu_instruction_master_read_data_valid_ext_ram_s1_shift_register[1] # NB1_cpu_instruction_master_read_data_valid_sdram_s1;

--U1L104 is std_1c20:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_readdatavalid~150

--operation mode is normal

U1L104 = X1_cpu_instruction_master_granted_epcs_controller_epcs_control_port & (!S1_ic_fill_tag[5] & !X1L26);

--U1L105 is std_1c20:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_readdatavalid~151

--operation mode is normal

U1L105 = U1L101 & (!V1L26);

--S1L990 is std_1c20:inst|cpu:the_cpu|ic_fill_dp_offset_nxt[2]~153

--operation mode is normal

S1L990 = AMPP_FUNCTION(S1_ic_fill_initial_offset[2], S1_D_ic_fill_starting_d1);

--S1L986 is std_1c20:inst|cpu:the_cpu|ic_fill_dp_offset_en~5

--operation mode is normal

S1L986 = AMPP_FUNCTION(S1_D_ic_fill_starting_d1, S1_i_readdatavalid_d1);

--S1L987 is std_1c20:inst|cpu:the_cpu|ic_fill_dp_offset_nxt[0]~154

--operation mode is normal

S1L987 = AMPP_FUNCTION(S1_ic_fill_initial_offset[0], S1_D_ic_fill_starting_d1, S1_ic_fill_dp_offset[0]);

--S1L988 is std_1c20:inst|cpu:the_cpu|ic_fill_dp_offset_nxt[1]~155

--operation mode is normal

S1L988 = AMPP_FUNCTION(S1_ic_fill_initial_offset[1], S1_D_ic_fill_starting_d1, S1_ic_fill_dp_offset[0], S1_ic_fill_dp_offset[1]);

--Y1L189 is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_avalon_slave_arb_share_counter_next_value[0]~95

--operation mode is normal

Y1L189 = Y1L198 & Y1_ext_ram_bus_avalon_slave_arb_share_counter[1] & (!Y1_ext_ram_bus_avalon_slave_arb_share_counter[0]);

--KB1_rd_valid[1] is std_1c20:inst|sdram:the_sdram|rd_valid[1]

--operation mode is normal

KB1_rd_valid[1]_lut_out = KB1_rd_valid[0];

KB1_rd_valid[1] = DFFEAS(KB1_rd_valid[1]_lut_out, QC2__clk0, F1_data_out, , , , , , );

--WE1_stage_2 is std_1c20:inst|sdram_s1_arbitrator:the_sdram_s1|rdv_fifo_for_cpu_instruction_master_to_sdram_s1_module:rdv_fifo_for_cpu_instruction_master_to_sdram_s1|stage_2

--operation mode is normal

WE1_stage_2_lut_out = WE1_full_3 & WE1_stage_3 # !WE1_full_3 & (NB1L18);

WE1_stage_2 = DFFEAS(WE1_stage_2_lut_out, QC2__clk0, VCC, , WE1L24, , , , );

--WE1_full_2 is std_1c20:inst|sdram_s1_arbitrator:the_sdram_s1|rdv_fifo_for_cpu_instruction_master_to_sdram_s1_module:rdv_fifo_for_cpu_instruction_master_to_sdram_s1|full_2

--operation mode is normal

WE1_full_2_lut_out = KB1_za_valid & (NB1L27 & WE1_full_1 # !NB1L27 & (WE1_full_3)) # !KB1_za_valid & WE1_full_1;

WE1_full_2 = DFFEAS(WE1_full_2_lut_out, QC2__clk0, F1_data_out, , VE1L13, , , , );

--WE1L25 is std_1c20:inst|sdram_s1_arbitrator:the_sdram_s1|rdv_fifo_for_cpu_instruction_master_to_sdram_s1_module:rdv_fifo_for_cpu_instruction_master_to_sdram_s1|process10~1

--operation mode is normal

WE1L25 = KB1_za_valid # NB1L27 & (!WE1_full_1);

--VE1L13 is std_1c20:inst|sdram_s1_arbitrator:the_sdram_s1|rdv_fifo_for_cpu_data_master_to_sdram_s1_module:rdv_fifo_for_cpu_data_master_to_sdram_s1|process1~3

--operation mode is normal

VE1L13 = KB1_za_valid & (!WE1_full_0 # !NB1L27) # !KB1_za_valid & NB1L27;

--LC1_internal_master_write_done is std_1c20:inst|clock_1:the_clock_1|clock_1_master_FSM:master_FSM|internal_master_write_done

--operation mode is normal

LC1_internal_master_write_done_lut_out = LC1_internal_master_write_done $ (!LC1_master_state[1] & LC1_master_state[2] & LC1_master_state[0]);

LC1_internal_master_write_done = DFFEAS(LC1_internal_master_write_done_lut_out, PLD_CLOCKINPUT[1], E1_data_out, , , , , , );

--LC1_internal_master_read_done is std_1c20:inst|clock_1:the_clock_1|clock_1_master_FSM:master_FSM|internal_master_read_done

--operation mode is normal

LC1_internal_master_read_done_lut_out = LC1_internal_master_read_done $ (!LC1_master_state[2] & LC1L2 & LC1L3);

LC1_internal_master_read_done = DFFEAS(LC1_internal_master_read_done_lut_out, PLD_CLOCKINPUT[1], E1_data_out, , , , , , );

--CC1_internal_master_write_done is std_1c20:inst|clock_0:the_clock_0|clock_0_master_FSM:master_FSM|internal_master_write_done

--operation mode is normal

CC1_internal_master_write_done_lut_out = CC1_internal_master_write_done $ (!CC1_master_state[1] & CC1_master_state[2] & CC1_master_state[0]);

CC1_internal_master_write_done = DFFEAS(CC1_internal_master_write_done_lut_out, PLD_CLKFB, D1_data_out, , , , , , );

--CC1_internal_master_read_done is std_1c20:inst|clock_0:the_clock_0|clock_0_master_FSM:master_FSM|internal_master_read_done

--operation mode is normal

CC1_internal_master_read_done_lut_out = CC1_internal_master_read_done $ (!CC1_master_state[2] & CC1L2 & CC1L3);

CC1_internal_master_read_done = DFFEAS(CC1_internal_master_read_done_lut_out, PLD_CLKFB, D1_data_out, , , , , , );

--VE1_stage_2 is std_1c20:inst|sdram_s1_arbitrator:the_sdram_s1|rdv_fifo_for_cpu_data_master_to_sdram_s1_module:rdv_fifo_for_cpu_data_master_to_sdram_s1|stage_2

--operation mode is normal

VE1_stage_2_lut_out = WE1_full_3 & VE1_stage_3 # !WE1_full_3 & (NB1L14);

VE1_stage_2 = DFFEAS(VE1_stage_2_lut_out, QC2__clk0, VCC, , WE1L24, , , , );

--SD1_sr[22] is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|sr[22]

--operation mode is normal

SD1_sr[22] = AMPP_FUNCTION(A1L5, SD1L21, SD1_sr[23], SD1L9, SD1L22, !C1_CLR_SIGNAL, SD1L12);

--KB1L380 is std_1c20:inst|sdram:the_sdram|Mux42~1481

--operation mode is normal

KB1L380 = KB1_m_count[0] & (!KB1L349 # !KB1L379) # !KB1_m_count[0] & KB1L149 & KB1L379 & KB1L349;

--KB1L381 is std_1c20:inst|sdram:the_sdram|Mux42~1482

--operation mode is normal

KB1L381 = KB1_m_count[0] # KB1L379 & KB1L349 & KB1L222;

--KB1L382 is std_1c20:inst|sdram:the_sdram|Mux42~1483

--operation mode is normal

KB1L382 = KB1_m_state[0] & !KB1_m_state[7] & !KB1_m_state[2] & !KB1_m_state[1];

--KB1L383 is std_1c20:inst|sdram:the_sdram|Mux42~1484

--operation mode is normal

KB1L383 = TE1L127 & KB1_refresh_request & KB1L382 & !KB1L554;

--KB1L384 is std_1c20:inst|sdram:the_sdram|Mux42~1485

--operation mode is normal

KB1L384 = KB1L299 & (KB1_m_state[0] & KB1L149 # !KB1_m_state[0] & (KB1L176));

--KB1L385 is std_1c20:inst|sdram:the_sdram|Mux42~1486

--operation mode is normal

KB1L385 = KB1_m_state[2] # KB1_m_state[0] & (KB1_m_state[7] $ !KB1_m_state[1]);

--KB1L386 is std_1c20:inst|sdram:the_sdram|Mux42~1487

--operation mode is normal

KB1L386 = KB1_m_state[0] & (KB1_m_state[2] # KB1_m_state[7] $ KB1_m_state[1]);

--KB1L387 is std_1c20:inst|sdram:the_sdram|Mux42~1488

--operation mode is normal

KB1L387 = KB1_m_count[0] & (KB1L385 $ KB1L386 # !KB1L384) # !KB1_m_count[0] & KB1L386 & (KB1L384 # !KB1L385);

--KB1L388 is std_1c20:inst|sdram:the_sdram|Mux42~1489

--operation mode is normal

KB1L388 = KB1_m_state[5] & (KB1_m_state[8]) # !KB1_m_state[5] & (KB1_m_state[8] & KB1L381 # !KB1_m_state[8] & (KB1L390));

--KB1_i_refs[0] is std_1c20:inst|sdram:the_sdram|i_refs[0]

--operation mode is normal

KB1_i_refs[0]_lut_out = KB1_i_refs[0] & (!KB1L139) # !KB1_i_refs[0] & KB1L142;

KB1_i_refs[0] = DFFEAS(KB1_i_refs[0]_lut_out, QC2__clk0, VCC, , , , , , );

--RD1L26 is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|internal_MonDReg[1]~7323

--operation mode is normal

RD1L26 = AMPP_FUNCTION(KB1_i_state[1], KB1_i_refs[0]);

--KB1_i_refs[1] is std_1c20:inst|sdram:the_sdram|i_refs[1]

--operation mode is normal

KB1_i_refs[1]_lut_out = KB1_i_refs[1] & (KB1L142 & !KB1_i_refs[0] # !KB1L139) # !KB1_i_refs[1] & KB1L142 & KB1_i_refs[0];

KB1_i_refs[1] = DFFEAS(KB1_i_refs[1]_lut_out, QC2__clk0, VCC, , , , , , );

--KB1_i_refs[2] is std_1c20:inst|sdram:the_sdram|i_refs[2]

--operation mode is normal

KB1_i_refs[2]_lut_out = KB1_i_refs[2] & (KB1L142 & !KB1L99 # !KB1L139) # !KB1_i_refs[2] & KB1L142 & KB1L99;

KB1_i_refs[2] = DFFEAS(KB1_i_refs[2]_lut_out, QC2__clk0, VCC, , , , , , );

--RD1L27 is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|internal_MonDReg[1]~7325

--operation mode is normal

RD1L27 = AMPP_FUNCTION(KB1_i_state[0], KB1_i_state[1], KB1_i_state[2]);

--KB1_i_count[0] is std_1c20:inst|sdram:the_sdram|i_count[0]

--operation mode is normal

KB1_i_count[0]_lut_out = KB1L240 & (KB1L148 $ KB1_i_count[0] # !KB1_i_state[0]);

KB1_i_count[0] = DFFEAS(KB1_i_count[0]_lut_out, QC2__clk0, F1_data_out, , KB1L243, , , , );

--KB1L242 is std_1c20:inst|sdram:the_sdram|Mux10~94

--operation mode is normal

KB1L242 = KB1_i_count[2] & (KB1_i_count[1] # KB1_i_count[0]);

--KB1L243 is std_1c20:inst|sdram:the_sdram|Mux10~96

--operation mode is normal

KB1L243 = KB1_i_state[2] & (KB1_i_state[0] & KB1_i_state[1]) # !KB1_i_state[2] & (KB1_i_state[0] # KB1_i_state[1]);

--KB1L244 is std_1c20:inst|sdram:the_sdram|Mux11~67

--operation mode is normal

KB1L244 = KB1_i_count[1] & KB1_i_count[0] # !KB1_i_count[1] & !KB1_i_count[0] & KB1_i_count[2];

--ZE1_internal_tx_ready is std_1c20:inst|uart1:the_uart1|uart1_tx:the_uart1_tx|internal_tx_ready

--operation mode is normal

ZE1_internal_tx_ready_lut_out = ZE1L33 & ZE1L34 & ZE1L35 # !ZE1L24;

ZE1_internal_tx_ready = DFFEAS(ZE1_internal_tx_ready_lut_out, QC2__clk0, F1_data_out, , , , , , );

--ZE1_baud_rate_counter[0] is std_1c20:inst|uart1:the_uart1|uart1_tx:the_uart1_tx|baud_rate_counter[0]

--operation mode is arithmetic

ZE1_baud_rate_counter[0]_lut_out = !ZE1_baud_rate_counter[0];

ZE1_baud_rate_counter[0] = DFFEAS(ZE1_baud_rate_counter[0]_lut_out, QC2__clk0, F1_data_out, , , A1L276, , , ZE1L29);

--ZE1L4 is std_1c20:inst|uart1:the_uart1|uart1_tx:the_uart1_tx|baud_rate_counter[0]~54

--operation mode is arithmetic

ZE1L4 = CARRY(ZE1_baud_rate_counter[0]);

--ZE1_baud_rate_counter[1] is std_1c20:inst|uart1:the_uart1|uart1_tx:the_uart1_tx|baud_rate_counter[1]

--operation mode is arithmetic

ZE1_baud_rate_counter[1]_carry_eqn = ZE1L4;

ZE1_baud_rate_counter[1]_lut_out = ZE1_baud_rate_counter[1] $ (!ZE1_baud_rate_counter[1]_carry_eqn);

ZE1_baud_rate_counter[1] = DFFEAS(ZE1_baud_rate_counter[1]_lut_out, QC2__clk0, F1_data_out, , , VCC, , , ZE1L29);

--ZE1L6 is std_1c20:inst|uart1:the_uart1|uart1_tx:the_uart1_tx|baud_rate_counter[1]~55

--operation mode is arithmetic

ZE1L6 = CARRY(!ZE1_baud_rate_counter[1] & (!ZE1L4));

--ZE1_baud_rate_counter[2] is std_1c20:inst|uart1:the_uart1|uart1_tx:the_uart1_tx|baud_rate_counter[2]

--operation mode is arithmetic

ZE1_baud_rate_counter[2]_carry_eqn = ZE1L6;

ZE1_baud_rate_counter[2]_lut_out = ZE1_baud_rate_counter[2] $ (ZE1_baud_rate_counter[2]_carry_eqn);

ZE1_baud_rate_counter[2] = DFFEAS(ZE1_baud_rate_counter[2]_lut_out, QC2__clk0, F1_data_out, , , A1L276, , , ZE1L29);

--ZE1L8 is std_1c20:inst|uart1:the_uart1|uart1_tx:the_uart1_tx|baud_rate_counter[2]~56

--operation mode is arithmetic

ZE1L8 = CARRY(ZE1_baud_rate_counter[2] # !ZE1L6);

--ZE1_baud_rate_counter[3] is std_1c20:inst|uart1:the_uart1|uart1_tx:the_uart1_tx|baud_rate_counter[3]

--operation mode is arithmetic

ZE1_baud_rate_counter[3]_carry_eqn = ZE1L8;

ZE1_baud_rate_counter[3]_lut_out = ZE1_baud_rate_counter[3] $ (!ZE1_baud_rate_counter[3]_carry_eqn);

ZE1_baud_rate_counter[3] = DFFEAS(ZE1_baud_rate_counter[3]_lut_out, QC2__clk0, F1_data_out, , , A1L276, , , ZE1L29);

--ZE1L10 is std_1c20:inst|uart1:the_uart1|uart1_tx:the_uart1_tx|baud_rate_counter[3]~57

--operation mode is arithmetic

ZE1L10 = CARRY(!ZE1_baud_rate_counter[3] & (!ZE1L8));

--ZE1L21 is std_1c20:inst|uart1:the_uart1|uart1_tx:the_uart1_tx|Equal0~137

--operation mode is normal

ZE1L21 = !ZE1_baud_rate_counter[0] & !ZE1_baud_rate_counter[1] & !ZE1_baud_rate_counter[2] & !ZE1_baud_rate_counter[3];

--ZE1_baud_rate_counter[4] is std_1c20:inst|uart1:the_uart1|uart1_tx:the_uart1_tx|baud_rate_counter[4]

--operation mode is arithmetic

ZE1_baud_rate_counter[4]_carry_eqn = ZE1L10;

ZE1_baud_rate_counter[4]_lut_out = ZE1_baud_rate_counter[4] $ (ZE1_baud_rate_counter[4]_carry_eqn);

ZE1_baud_rate_counter[4] = DFFEAS(ZE1_baud_rate_counter[4]_lut_out, QC2__clk0, F1_data_out, , , VCC, , , ZE1L29);

--ZE1L12 is std_1c20:inst|uart1:the_uart1|uart1_tx:the_uart1_tx|baud_rate_counter[4]~58

--operation mode is arithmetic

ZE1L12 = CARRY(ZE1_baud_rate_counter[4] # !ZE1L10);

--ZE1_baud_rate_counter[5] is std_1c20:inst|uart1:the_uart1|uart1_tx:the_uart1_tx|baud_rate_counter[5]

--operation mode is arithmetic

ZE1_baud_rate_counter[5]_carry_eqn = ZE1L12;

ZE1_baud_rate_counter[5]_lut_out = ZE1_baud_rate_counter[5] $ (!ZE1_baud_rate_counter[5]_carry_eqn);

ZE1_baud_rate_counter[5] = DFFEAS(ZE1_baud_rate_counter[5]_lut_out, QC2__clk0, F1_data_out, , , VCC, , , ZE1L29);

--ZE1L14 is std_1c20:inst|uart1:the_uart1|uart1_tx:the_uart1_tx|baud_rate_counter[5]~59

--operation mode is arithmetic

ZE1L14 = CARRY(!ZE1_baud_rate_counter[5] & (!ZE1L12));

--ZE1_baud_rate_counter[6] is std_1c20:inst|uart1:the_uart1|uart1_tx:the_uart1_tx|baud_rate_counter[6]

--operation mode is arithmetic

ZE1_baud_rate_counter[6]_carry_eqn = ZE1L14;

ZE1_baud_rate_counter[6]_lut_out = ZE1_baud_rate_counter[6] $ (ZE1_baud_rate_counter[6]_carry_eqn);

ZE1_baud_rate_counter[6] = DFFEAS(ZE1_baud_rate_counter[6]_lut_out, QC2__clk0, F1_data_out, , , A1L276, , , ZE1L29);

--ZE1L16 is std_1c20:inst|uart1:the_uart1|uart1_tx:the_uart1_tx|baud_rate_counter[6]~60

--operation mode is arithmetic

ZE1L16 = CARRY(ZE1_baud_rate_counter[6] # !ZE1L14);

--ZE1_baud_rate_counter[7] is std_1c20:inst|uart1:the_uart1|uart1_tx:the_uart1_tx|baud_rate_counter[7]

--operation mode is arithmetic

ZE1_baud_rate_counter[7]_carry_eqn = ZE1L16;

ZE1_baud_rate_counter[7]_lut_out = ZE1_baud_rate_counter[7] $ (!ZE1_baud_rate_counter[7]_carry_eqn);

ZE1_baud_rate_counter[7] = DFFEAS(ZE1_baud_rate_counter[7]_lut_out, QC2__clk0, F1_data_out, , , VCC, , , ZE1L29);

--ZE1L18 is std_1c20:inst|uart1:the_uart1|uart1_tx:the_uart1_tx|baud_rate_counter[7]~61

--operation mode is arithmetic

ZE1L18 = CARRY(!ZE1_baud_rate_counter[7] & (!ZE1L16));

--ZE1L22 is std_1c20:inst|uart1:the_uart1|uart1_tx:the_uart1_tx|Equal0~138

--operation mode is normal

ZE1L22 = !ZE1_baud_rate_counter[4] & !ZE1_baud_rate_counter[5] & !ZE1_baud_rate_counter[6] & !ZE1_baud_rate_counter[7];

--ZE1_baud_rate_counter[8] is std_1c20:inst|uart1:the_uart1|uart1_tx:the_uart1_tx|baud_rate_counter[8]

--operation mode is normal

ZE1_baud_rate_counter[8]_carry_eqn = ZE1L18;

ZE1_baud_rate_counter[8]_lut_out = ZE1_baud_rate_counter[8] $ (ZE1_baud_rate_counter[8]_carry_eqn);

ZE1_baud_rate_counter[8] = DFFEAS(ZE1_baud_rate_counter[8]_lut_out, QC2__clk0, F1_data_out, , , VCC, , , ZE1L29);

--XE1L18 is std_1c20:inst|uart1:the_uart1|uart1_regs:the_uart1_regs|Equal1~119

--operation mode is normal

XE1L18 = S1_M_alu_result[2] & (!S1_M_alu_result[3] & !S1_M_alu_result[4]);

--G1_d2_data_in[3] is std_1c20:inst|button_pio:the_button_pio|d2_data_in[3]

--operation mode is normal

G1_d2_data_in[3]_lut_out = G1_d1_data_in[3];

G1_d2_data_in[3] = DFFEAS(G1_d2_data_in[3]_lut_out, QC2__clk0, F1_data_out, , , , , , );

--G1_d1_data_in[3] is std_1c20:inst|button_pio:the_button_pio|d1_data_in[3]

--operation mode is normal

G1_d1_data_in[3]_lut_out = in_port_to_the_button_pio[3];

G1_d1_data_in[3] = DFFEAS(G1_d1_data_in[3]_lut_out, QC2__clk0, F1_data_out, , , , , , );

--G1L17 is std_1c20:inst|button_pio:the_button_pio|edge_capture~124

--operation mode is normal

G1L17 = G1_edge_capture[3] # G1_d2_data_in[3] $ G1_d1_data_in[3];

--G1L16 is std_1c20:inst|button_pio:the_button_pio|edge_capture_wr_strobe~31

--operation mode is normal

G1L16 = S1_M_alu_result[3] & S1_internal_d_write & (!T1_internal_cpu_data_master_waitrequest);

--G1_d2_data_in[1] is std_1c20:inst|button_pio:the_button_pio|d2_data_in[1]

--operation mode is normal

G1_d2_data_in[1]_lut_out = G1_d1_data_in[1];

G1_d2_data_in[1] = DFFEAS(G1_d2_data_in[1]_lut_out, QC2__clk0, F1_data_out, , , , , , );

--G1_d1_data_in[1] is std_1c20:inst|button_pio:the_button_pio|d1_data_in[1]

--operation mode is normal

G1_d1_data_in[1]_lut_out = in_port_to_the_button_pio[1];

G1_d1_data_in[1] = DFFEAS(G1_d1_data_in[1]_lut_out, QC2__clk0, F1_data_out, , , , , , );

--G1L18 is std_1c20:inst|button_pio:the_button_pio|edge_capture~126

--operation mode is normal

G1L18 = G1_edge_capture[1] # G1_d2_data_in[1] $ G1_d1_data_in[1];

--G1L26 is std_1c20:inst|button_pio:the_button_pio|process1~14

--operation mode is normal

G1L26 = H1_cpu_data_master_requests_button_pio_s1 & G1L16 & (!S1_M_alu_result[2]);

--G1_d2_data_in[2] is std_1c20:inst|button_pio:the_button_pio|d2_data_in[2]

--operation mode is normal

G1_d2_data_in[2]_lut_out = G1_d1_data_in[2];

G1_d2_data_in[2] = DFFEAS(G1_d2_data_in[2]_lut_out, QC2__clk0, F1_data_out, , , , , , );

--G1_d1_data_in[2] is std_1c20:inst|button_pio:the_button_pio|d1_data_in[2]

--operation mode is normal

G1_d1_data_in[2]_lut_out = in_port_to_the_button_pio[2];

G1_d1_data_in[2] = DFFEAS(G1_d1_data_in[2]_lut_out, QC2__clk0, F1_data_out, , , , , , );

--G1L19 is std_1c20:inst|button_pio:the_button_pio|edge_capture~128

--operation mode is normal

G1L19 = G1_edge_capture[2] # G1_d2_data_in[2] $ G1_d1_data_in[2];

--G1_d2_data_in[0] is std_1c20:inst|button_pio:the_button_pio|d2_data_in[0]

--operation mode is normal

G1_d2_data_in[0]_lut_out = G1_d1_data_in[0];

G1_d2_data_in[0] = DFFEAS(G1_d2_data_in[0]_lut_out, QC2__clk0, F1_data_out, , , , , , );

--G1_d1_data_in[0] is std_1c20:inst|button_pio:the_button_pio|d1_data_in[0]

--operation mode is normal

G1_d1_data_in[0]_lut_out = in_port_to_the_button_pio[0];

G1_d1_data_in[0] = DFFEAS(G1_d1_data_in[0]_lut_out, QC2__clk0, F1_data_out, , , , , , );

--G1L20 is std_1c20:inst|button_pio:the_button_pio|edge_capture~130

--operation mode is normal

G1L20 = G1_edge_capture[0] # G1_d2_data_in[0] $ G1_d1_data_in[0];

--FD1L13 is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_avalon_reg:the_cpu_nios2_avalon_reg|take_action_oci_intr_mask_reg~10

--operation mode is normal

FD1L13 = AMPP_FUNCTION(V1L9, FD1L1, FD1L2, RD1L61);

--S1_i_readdata_d1[8] is std_1c20:inst|cpu:the_cpu|i_readdata_d1[8]

--operation mode is normal

S1_i_readdata_d1[8] = AMPP_FUNCTION(QC2__clk0, U1L34, WC1L19, WC1L9, V1_cpu_instruction_master_qualified_request_cpu_jtag_debug_module, F1_data_out);

--S1L542 is std_1c20:inst|cpu:the_cpu|E_op_eret~74

--operation mode is normal

S1L542 = AMPP_FUNCTION(S1_E_iw[16], S1_E_iw[15], S1_E_iw[13]);

--S1L543 is std_1c20:inst|cpu:the_cpu|E_op_eret~75

--operation mode is normal

S1L543 = AMPP_FUNCTION(S1_E_iw[11], S1L540, S1L541, S1L542);

--S1_E_wrctl_status is std_1c20:inst|cpu:the_cpu|E_wrctl_status

--operation mode is normal

S1_E_wrctl_status = AMPP_FUNCTION(S1_E_ctrl_wrctl_inst, S1_E_iw[6], S1_E_iw[7], S1_E_iw[8]);

--S1_E_ctrl_exception is std_1c20:inst|cpu:the_cpu|E_ctrl_exception

--operation mode is normal

S1_E_ctrl_exception = AMPP_FUNCTION(QC2__clk0, S1L765, S1L233, S1L219, S1L773, F1_data_out, S1_W_stall);

--S1L1271 is std_1c20:inst|cpu:the_cpu|M_status_reg_pie_inst_nxt~0

--operation mode is normal

S1L1271 = AMPP_FUNCTION(S1_E_ctrl_break, S1_E_ctrl_exception);

--S1L1272 is std_1c20:inst|cpu:the_cpu|M_status_reg_pie~156

--operation mode is normal

S1L1272 = AMPP_FUNCTION(S1_M_status_reg_pie, S1_W_stall, S1L1276, S1L752);

--S1L1273 is std_1c20:inst|cpu:the_cpu|M_status_reg_pie~157

--operation mode is normal

S1L1273 = AMPP_FUNCTION(S1_E_wrctl_status, S1L543);

--S1L1274 is std_1c20:inst|cpu:the_cpu|M_status_reg_pie~158

--operation mode is normal

S1L1274 = AMPP_FUNCTION(S1L1273, S1L415, S1L403, S1_E_ctrl_dst_data_sel_cmp);

--S1L1275 is std_1c20:inst|cpu:the_cpu|M_status_reg_pie~159

--operation mode is normal

S1L1275 = AMPP_FUNCTION(S1L543, S1_M_bstatus_reg, S1_M_estatus_reg, S1_E_iw[14]);

--BB1_ien_AE is std_1c20:inst|jtag_uart:the_jtag_uart|ien_AE

--operation mode is normal

BB1_ien_AE_lut_out = S1_M_st_data[1];

BB1_ien_AE = DFFEAS(BB1_ien_AE_lut_out, QC2__clk0, F1_data_out, , BB1L46, , , , );

--BB1_fifo_AE is std_1c20:inst|jtag_uart:the_jtag_uart|fifo_AE

--operation mode is normal

BB1_fifo_AE_lut_out = !RE1_safe_q[5] & !RE1_safe_q[4] & !NE1_b_full & !BB1L50;

BB1_fifo_AE = DFFEAS(BB1_fifo_AE_lut_out, QC2__clk0, F1_data_out, , , , , , );

--BB1L49 is std_1c20:inst|jtag_uart:the_jtag_uart|ipen_AE~17

--operation mode is normal

BB1L49 = BB1_ien_AE & BB1_fifo_AE;

--BB1_ien_AF is std_1c20:inst|jtag_uart:the_jtag_uart|ien_AF

--operation mode is normal

BB1_ien_AF_lut_out = S1_M_st_data[0];

BB1_ien_AF = DFFEAS(BB1_ien_AF_lut_out, QC2__clk0, F1_data_out, , BB1L46, , , , );

--BB1_fifo_AF is std_1c20:inst|jtag_uart:the_jtag_uart|fifo_AF

--operation mode is normal

BB1_fifo_AF_lut_out = !BB1L3 & !BB1L51 & !BB1L52 & BB1L15;

BB1_fifo_AF = DFFEAS(BB1_fifo_AF_lut_out, QC2__clk0, F1_data_out, , , , , , );

--BB1_pause_irq is std_1c20:inst|jtag_uart:the_jtag_uart|pause_irq

--operation mode is normal

BB1_pause_irq_lut_out = NE2_b_non_empty & (GE1L39Q # BB1_pause_irq & !BB1_read_0) # !NE2_b_non_empty & (BB1_pause_irq & !BB1_read_0);

BB1_pause_irq = DFFEAS(BB1_pause_irq_lut_out, QC2__clk0, F1_data_out, , , , , , );

--T1L287 is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|p1_registered_cpu_data_master_readdata~2026

--operation mode is normal

T1L287 = BB1_ien_AF & (BB1_fifo_AF # BB1_pause_irq);

--FD1_internal_oci_ienable1[1] is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_avalon_reg:the_cpu_nios2_avalon_reg|internal_oci_ienable1[1]

--operation mode is normal

FD1_internal_oci_ienable1[1] = AMPP_FUNCTION(QC2__clk0, S1_M_st_data[1], F1_data_out, FD1L13);

--RB1_control_register[0] is std_1c20:inst|sys_clk_timer:the_sys_clk_timer|control_register[0]

--operation mode is normal

RB1_control_register[0]_lut_out = S1_M_st_data[0];

RB1_control_register[0] = DFFEAS(RB1_control_register[0]_lut_out, QC2__clk0, F1_data_out, , RB1_control_wr_strobe, , , , );

--RB1_timeout_occurred is std_1c20:inst|sys_clk_timer:the_sys_clk_timer|timeout_occurred

--operation mode is normal

RB1_timeout_occurred_lut_out = RB1L211 & (!XE1L21 # !SB1_cpu_data_master_requests_sys_clk_timer_s1 # !RB1L7);

RB1_timeout_occurred = DFFEAS(RB1_timeout_occurred_lut_out, QC2__clk0, F1_data_out, , , , , , );

--FD1_internal_oci_ienable1[0] is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_avalon_reg:the_cpu_nios2_avalon_reg|internal_oci_ienable1[0]

--operation mode is normal

FD1_internal_oci_ienable1[0] = AMPP_FUNCTION(QC2__clk0, S1_M_st_data[0], F1_data_out, FD1L13);

--S1_i_readdata_d1[7] is std_1c20:inst|cpu:the_cpu|i_readdata_d1[7]

--operation mode is normal

S1_i_readdata_d1[7] = AMPP_FUNCTION(QC2__clk0, U1L31, WC1L19, WC1L8, V1_cpu_instruction_master_qualified_request_cpu_jtag_debug_module, F1_data_out);

--S1L941Q is std_1c20:inst|cpu:the_cpu|i_readdata_d1[6]~99

--operation mode is normal

S1L941Q = AMPP_FUNCTION(QC2__clk0, U1L120, X1_cpu_instruction_master_qualified_request_epcs_controller_epcs_control_port, U1L27, U1L28, F1_data_out);

--S1L942Q is std_1c20:inst|cpu:the_cpu|i_readdata_d1[6]~100

--operation mode is normal

S1L942Q = AMPP_FUNCTION(QC2__clk0, WC1L7, WC1L19, FD1_internal_oci_ienable1[6], V1_cpu_instruction_master_qualified_request_cpu_jtag_debug_module, F1_data_out);

--U1L26 is std_1c20:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_readdata[6]~2408

--operation mode is normal

U1L26 = S1L941Q & S1L942Q;

--S1L937Q is std_1c20:inst|cpu:the_cpu|i_readdata_d1[4]~86

--operation mode is normal

S1L937Q = AMPP_FUNCTION(QC2__clk0, U1L121, X1_cpu_instruction_master_qualified_request_epcs_controller_epcs_control_port, U1L21, U1L22, F1_data_out);

--S1L938Q is std_1c20:inst|cpu:the_cpu|i_readdata_d1[4]~87

--operation mode is normal

S1L938Q = AMPP_FUNCTION(QC2__clk0, WC1L5, WC1L19, FD1_internal_oci_ienable1[4], V1_cpu_instruction_master_qualified_request_cpu_jtag_debug_module, F1_data_out);

--U1L20 is std_1c20:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_readdata[4]~2409

--operation mode is normal

U1L20 = S1L937Q & S1L938Q;

--S1_i_readdata_d1[15] is std_1c20:inst|cpu:the_cpu|i_readdata_d1[15]

--operation mode is normal

S1_i_readdata_d1[15] = AMPP_FUNCTION(QC2__clk0, U1L52, WC1L19, WC1L16, V1_cpu_instruction_master_qualified_request_cpu_jtag_debug_module, F1_data_out);

--S1L928Q is std_1c20:inst|cpu:the_cpu|i_readdata_d1[0]~90

--operation mode is normal

S1L928Q = AMPP_FUNCTION(QC2__clk0, U1L123, X1_cpu_instruction_master_qualified_request_epcs_controller_epcs_control_port, U1L9, U1L10, F1_data_out);

--S1L935Q is std_1c20:inst|cpu:the_cpu|i_readdata_d1[3]~97

--operation mode is normal

S1L935Q = AMPP_FUNCTION(QC2__clk0, V1_cpu_instruction_master_qualified_request_cpu_jtag_debug_module, F1_data_out);

--U1L8 is std_1c20:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_readdata[0]~2410

--operation mode is normal

U1L8 = S1L928Q & (S1L929Q # S1L935Q);

--S1L930Q is std_1c20:inst|cpu:the_cpu|i_readdata_d1[1]~92

--operation mode is normal

S1L930Q = AMPP_FUNCTION(QC2__clk0, U1L124, X1_cpu_instruction_master_qualified_request_epcs_controller_epcs_control_port, U1L12, U1L13, F1_data_out);

--U1L11 is std_1c20:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_readdata[1]~2411

--operation mode is normal

U1L11 = S1L930Q & (S1L931Q # S1L935Q);

--S1L932Q is std_1c20:inst|cpu:the_cpu|i_readdata_d1[2]~94

--operation mode is normal

S1L932Q = AMPP_FUNCTION(QC2__clk0, U1L112, X1_cpu_instruction_master_qualified_request_epcs_controller_epcs_control_port, U1L15, U1L16, F1_data_out);

--U1L14 is std_1c20:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_readdata[2]~2412

--operation mode is normal

U1L14 = S1L932Q & (S1L933Q # S1L935Q);

--S1L934Q is std_1c20:inst|cpu:the_cpu|i_readdata_d1[3]~96

--operation mode is normal

S1L934Q = AMPP_FUNCTION(QC2__clk0, U1L113, X1_cpu_instruction_master_qualified_request_epcs_controller_epcs_control_port, U1L18, U1L19, F1_data_out);

--U1L17 is std_1c20:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_readdata[3]~2413

--operation mode is normal

U1L17 = S1L934Q & (S1L936Q # S1L935Q);

--S1L939Q is std_1c20:inst|cpu:the_cpu|i_readdata_d1[5]~88

--operation mode is normal

S1L939Q = AMPP_FUNCTION(QC2__clk0, U1L122, X1_cpu_instruction_master_qualified_request_epcs_controller_epcs_control_port, U1L24, U1L25, F1_data_out);

--S1L940Q is std_1c20:inst|cpu:the_cpu|i_readdata_d1[5]~89

--operation mode is normal

S1L940Q = AMPP_FUNCTION(QC2__clk0, WC1L6, WC1L19, FD1_internal_oci_ienable1[5], V1_cpu_instruction_master_qualified_request_cpu_jtag_debug_module, F1_data_out);

--U1L23 is std_1c20:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_readdata[5]~2414

--operation mode is normal

U1L23 = S1L939Q & S1L940Q;

--S1_i_readdata_d1[27] is std_1c20:inst|cpu:the_cpu|i_readdata_d1[27]

--operation mode is normal

S1_i_readdata_d1[27] = AMPP_FUNCTION(QC2__clk0, U1L88, WC1L19, WC1L29, V1_cpu_instruction_master_qualified_request_cpu_jtag_debug_module, F1_data_out);

--S1_i_readdata_d1[28] is std_1c20:inst|cpu:the_cpu|i_readdata_d1[28]

--operation mode is normal

S1_i_readdata_d1[28] = AMPP_FUNCTION(QC2__clk0, U1L91, WC1L19, WC1L30, V1_cpu_instruction_master_qualified_request_cpu_jtag_debug_module, F1_data_out);

--S1_i_readdata_d1[29] is std_1c20:inst|cpu:the_cpu|i_readdata_d1[29]

--operation mode is normal

S1_i_readdata_d1[29] = AMPP_FUNCTION(QC2__clk0, U1L94, WC1L19, WC1L31, V1_cpu_instruction_master_qualified_request_cpu_jtag_debug_module, F1_data_out);

--S1_i_readdata_d1[30] is std_1c20:inst|cpu:the_cpu|i_readdata_d1[30]

--operation mode is normal

S1_i_readdata_d1[30] = AMPP_FUNCTION(QC2__clk0, U1L97, WC1L19, WC1L32, V1_cpu_instruction_master_qualified_request_cpu_jtag_debug_module, F1_data_out);

--S1_i_readdata_d1[31] is std_1c20:inst|cpu:the_cpu|i_readdata_d1[31]

--operation mode is normal

S1_i_readdata_d1[31] = AMPP_FUNCTION(QC2__clk0, U1L100, WC1L19, WC1L33, V1_cpu_instruction_master_qualified_request_cpu_jtag_debug_module, F1_data_out);

--G1L29 is std_1c20:inst|button_pio:the_button_pio|read_mux_out[2]~376

--operation mode is normal

G1L29 = S1_M_alu_result[2] & G1_edge_capture[2] # !S1_M_alu_result[2] & (G1_irq_mask[2]);

--XE1_control_reg[2] is std_1c20:inst|uart1:the_uart1|uart1_regs:the_uart1_regs|control_reg[2]

--operation mode is normal

XE1_control_reg[2]_lut_out = S1_M_st_data[2];

XE1_control_reg[2] = DFFEAS(XE1_control_reg[2]_lut_out, QC2__clk0, F1_data_out, , XE1L14, , , , );

--XE1L52 is std_1c20:inst|uart1:the_uart1|uart1_regs:the_uart1_regs|selected_read_data[2]~677

--operation mode is normal

XE1L52 = S1_M_alu_result[3] & (XE1_control_reg[2]) # !S1_M_alu_result[3] & XE1_internal_tx_data[2];

--YE1_break_detect is std_1c20:inst|uart1:the_uart1|uart1_rx:the_uart1_rx|break_detect

--operation mode is normal

YE1_break_detect_lut_out = YE1L31 & (!XE1L20 # !XE1L13);

YE1_break_detect = DFFEAS(YE1_break_detect_lut_out, QC2__clk0, F1_data_out, , , , , , );

--YE1_rx_data[2] is std_1c20:inst|uart1:the_uart1|uart1_rx:the_uart1_rx|rx_data[2]

--operation mode is normal

YE1_rx_data[2]_lut_out = YE1_unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[3];

YE1_rx_data[2] = DFFEAS(YE1_rx_data[2]_lut_out, QC2__clk0, F1_data_out, , YE1_got_new_char, , , , );

--XE1L53 is std_1c20:inst|uart1:the_uart1|uart1_regs:the_uart1_regs|selected_read_data[2]~678

--operation mode is normal

XE1L53 = S1_M_alu_result[3] & YE1_break_detect # !S1_M_alu_result[3] & (YE1_rx_data[2]);

--RB1_counter_snapshot[2] is std_1c20:inst|sys_clk_timer:the_sys_clk_timer|counter_snapshot[2]

--operation mode is normal

RB1_counter_snapshot[2]_lut_out = !RB1_internal_counter[2];

RB1_counter_snapshot[2] = DFFEAS(RB1_counter_snapshot[2]_lut_out, QC2__clk0, F1_data_out, , RB1L209, , , , );

--XE1L19 is std_1c20:inst|uart1:the_uart1|uart1_regs:the_uart1_regs|Equal1~120

--operation mode is normal

XE1L19 = S1_M_alu_result[4] & (!S1_M_alu_result[2] & !S1_M_alu_result[3]);

--RB1_period_h_register[2] is std_1c20:inst|sys_clk_timer:the_sys_clk_timer|period_h_register[2]

--operation mode is normal

RB1_period_h_register[2]_lut_out = !S1_M_st_data[2];

RB1_period_h_register[2] = DFFEAS(RB1_period_h_register[2]_lut_out, QC2__clk0, F1_data_out, , RB1_period_h_wr_strobe, , , , );

--RB1L164 is std_1c20:inst|sys_clk_timer:the_sys_clk_timer|read_mux_out[2]~1238

--operation mode is normal

RB1L164 = RB1_counter_snapshot[2] & (XE1L19 # XE1L15 & !RB1_period_h_register[2]) # !RB1_counter_snapshot[2] & (XE1L15 & !RB1_period_h_register[2]);

--RB1_counter_snapshot[18] is std_1c20:inst|sys_clk_timer:the_sys_clk_timer|counter_snapshot[18]

--operation mode is normal

RB1_counter_snapshot[18]_lut_out = !RB1_internal_counter[18];

RB1_counter_snapshot[18] = DFFEAS(RB1_counter_snapshot[18]_lut_out, QC2__clk0, F1_data_out, , RB1L209, , , , );

--RB1_control_register[2] is std_1c20:inst|sys_clk_timer:the_sys_clk_timer|control_register[2]

--operation mode is normal

RB1_control_register[2]_lut_out = S1_M_st_data[2];

RB1_control_register[2] = DFFEAS(RB1_control_register[2]_lut_out, QC2__clk0, F1_data_out, , RB1_control_wr_strobe, , , , );

--RB1L165 is std_1c20:inst|sys_clk_timer:the_sys_clk_timer|read_mux_out[2]~1239

--operation mode is normal

RB1L165 = XE1L17 & (S1_M_alu_result[4] & RB1_counter_snapshot[18] # !S1_M_alu_result[4] & (RB1_control_register[2]));

--XE1L20 is std_1c20:inst|uart1:the_uart1|uart1_regs:the_uart1_regs|Equal1~121

--operation mode is normal

XE1L20 = S1_M_alu_result[3] & (!S1_M_alu_result[2] & !S1_M_alu_result[4]);

--RB1_period_l_register[2] is std_1c20:inst|sys_clk_timer:the_sys_clk_timer|period_l_register[2]

--operation mode is normal

RB1_period_l_register[2]_lut_out = !S1_M_st_data[2];

RB1_period_l_register[2] = DFFEAS(RB1_period_l_register[2]_lut_out, QC2__clk0, F1_data_out, , RB1_period_l_wr_strobe, , , , );

--M1_slave_readdata[2] is std_1c20:inst|clock_1:the_clock_1|slave_readdata[2]

--operation mode is normal

M1_slave_readdata[2]_lut_out = M1_slave_readdata_p1[2];

M1_slave_readdata[2] = DFFEAS(M1_slave_readdata[2]_lut_out, QC2__clk0, F1_data_out, , , , , , );

--J1_slave_readdata[2] is std_1c20:inst|clock_0:the_clock_0|slave_readdata[2]

--operation mode is normal

J1_slave_readdata[2]_lut_out = J1_slave_readdata_p1[2];

J1_slave_readdata[2] = DFFEAS(J1_slave_readdata[2]_lut_out, QC2__clk0, F1_data_out, , , , , , );

--T1L245 is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|p1_registered_cpu_data_master_readdata[2]~2027

--operation mode is normal

T1L245 = S1_M_alu_result[5] & M1_slave_readdata[2] # !S1_M_alu_result[5] & (J1_slave_readdata[2]) # !K1L6;

--SE2_q_b[2] is std_1c20:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_r:the_jtag_uart_scfifo_r|scfifo:rfifo|scfifo_jf21:auto_generated|a_dpfifo_ml21:dpfifo|dpram_j921:FIFOram|altsyncram_nll1:altsyncram1|q_b[2]

--RAM Block Operation Mode: Simple Dual-Port

--Port A Depth: 64, Port A Width: 1, Port B Depth: 64, Port B Width: 1

--Port A Logical Depth: 64, Port A Logical Width: 8, Port B Logical Depth: 64, Port B Logical Width: 8

--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered

SE2_q_b[2]_PORT_A_data_in = GE1_wdata[2];

SE2_q_b[2]_PORT_A_data_in_reg = DFFE(SE2_q_b[2]_PORT_A_data_in, SE2_q_b[2]_clock_0, , , SE2_q_b[2]_clock_enable_0);

SE2_q_b[2]_PORT_A_address = BUS(QE4_safe_q[0], QE4_safe_q[1], QE4_safe_q[2], QE4_safe_q[3], QE4_safe_q[4], QE4_safe_q[5]);

SE2_q_b[2]_PORT_A_address_reg = DFFE(SE2_q_b[2]_PORT_A_address, SE2_q_b[2]_clock_0, , , SE2_q_b[2]_clock_enable_0);

SE2_q_b[2]_PORT_B_address = BUS(QE3_safe_q[0], QE3_safe_q[1], QE3_safe_q[2], QE3_safe_q[3], QE3_safe_q[4], QE3_safe_q[5]);

SE2_q_b[2]_PORT_B_address_reg = DFFE(SE2_q_b[2]_PORT_B_address, SE2_q_b[2]_clock_1, , , SE2_q_b[2]_clock_enable_1);

SE2_q_b[2]_PORT_A_write_enable = VCC;

SE2_q_b[2]_PORT_A_write_enable_reg = DFFE(SE2_q_b[2]_PORT_A_write_enable, SE2_q_b[2]_clock_0, , , SE2_q_b[2]_clock_enable_0);

SE2_q_b[2]_PORT_B_read_enable = VCC;

SE2_q_b[2]_PORT_B_read_enable_reg = DFFE(SE2_q_b[2]_PORT_B_read_enable, SE2_q_b[2]_clock_1, , , SE2_q_b[2]_clock_enable_1);

SE2_q_b[2]_clock_0 = QC2__clk0;

SE2_q_b[2]_clock_1 = QC2__clk0;

SE2_q_b[2]_clock_enable_0 = BB1_wr_rfifo;

SE2_q_b[2]_clock_enable_1 = BB1L61;

SE2_q_b[2]_PORT_B_data_out = MEMORY(SE2_q_b[2]_PORT_A_data_in_reg, , SE2_q_b[2]_PORT_A_address_reg, SE2_q_b[2]_PORT_B_address_reg, SE2_q_b[2]_PORT_A_write_enable_reg, SE2_q_b[2]_PORT_B_read_enable_reg, , , SE2_q_b[2]_clock_0, SE2_q_b[2]_clock_1, SE2_q_b[2]_clock_enable_0, SE2_q_b[2]_clock_enable_1, , );

SE2_q_b[2] = SE2_q_b[2]_PORT_B_data_out[0];

--BB1_read_0 is std_1c20:inst|jtag_uart:the_jtag_uart|read_0

--operation mode is normal

BB1_read_0_lut_out = BB1L43;

BB1_read_0 = DFFEAS(BB1_read_0_lut_out, QC2__clk0, F1_data_out, , , , , , );

--T1L275 is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|p1_registered_cpu_data_master_readdata~51

--operation mode is normal

T1L275 = SE2_q_b[2] & BB1_read_0 # !CB1L2 # !UB1L9;

--KB1_za_data[2] is std_1c20:inst|sdram:the_sdram|za_data[2]

--operation mode is normal

KB1_za_data[2]_lut_out = A1L266;

KB1_za_data[2] = DFFEAS(KB1_za_data[2]_lut_out, QC2__clk0, F1_data_out, , , , , , );

--Z1_counter_snapshot[2] is std_1c20:inst|high_res_timer:the_high_res_timer|counter_snapshot[2]

--operation mode is normal

Z1_counter_snapshot[2]_lut_out = !Z1_internal_counter[2];

Z1_counter_snapshot[2] = DFFEAS(Z1_counter_snapshot[2]_lut_out, QC2__clk0, F1_data_out, , Z1L208, , , , );

--Z1_period_h_register[2] is std_1c20:inst|high_res_timer:the_high_res_timer|period_h_register[2]

--operation mode is normal

Z1_period_h_register[2]_lut_out = S1_M_st_data[2];

Z1_period_h_register[2] = DFFEAS(Z1_period_h_register[2]_lut_out, QC2__clk0, F1_data_out, , Z1_period_h_wr_strobe, , , , );

--Z1L163 is std_1c20:inst|high_res_timer:the_high_res_timer|read_mux_out[2]~1249

--operation mode is normal

Z1L163 = XE1L15 & (Z1_period_h_register[2] # XE1L19 & Z1_counter_snapshot[2]) # !XE1L15 & XE1L19 & Z1_counter_snapshot[2];

--Z1_counter_snapshot[18] is std_1c20:inst|high_res_timer:the_high_res_timer|counter_snapshot[18]

--operation mode is normal

Z1_counter_snapshot[18]_lut_out = Z1_internal_counter[18];

Z1_counter_snapshot[18] = DFFEAS(Z1_counter_snapshot[18]_lut_out, QC2__clk0, F1_data_out, , Z1L208, , , , );

--Z1_control_register[2] is std_1c20:inst|high_res_timer:the_high_res_timer|control_register[2]

--operation mode is normal

Z1_control_register[2]_lut_out = S1_M_st_data[2];

Z1_control_register[2] = DFFEAS(Z1_control_register[2]_lut_out, QC2__clk0, F1_data_out, , Z1_control_wr_strobe, , , , );

--Z1L164 is std_1c20:inst|high_res_timer:the_high_res_timer|read_mux_out[2]~1250

--operation mode is normal

Z1L164 = XE1L17 & (S1_M_alu_result[4] & Z1_counter_snapshot[18] # !S1_M_alu_result[4] & (Z1_control_register[2]));

--Z1_period_l_register[2] is std_1c20:inst|high_res_timer:the_high_res_timer|period_l_register[2]

--operation mode is normal

Z1_period_l_register[2]_lut_out = !S1_M_st_data[2];

Z1_period_l_register[2] = DFFEAS(Z1_period_l_register[2]_lut_out, QC2__clk0, F1_data_out, , Z1_period_l_wr_strobe, , , , );

--DE1_endofpacketvalue_reg[2] is std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|endofpacketvalue_reg[2]

--operation mode is normal

DE1_endofpacketvalue_reg[2]_lut_out = S1_M_st_data[2];

DE1_endofpacketvalue_reg[2] = DFFEAS(DE1_endofpacketvalue_reg[2]_lut_out, QC2__clk0, F1_data_out, , DE1_endofpacketvalue_wr_strobe, , , , );

--DE1_epcs_slave_select_reg[2] is std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|epcs_slave_select_reg[2]

--operation mode is normal

DE1_epcs_slave_select_reg[2]_lut_out = DE1_epcs_slave_select_holding_reg[2];

DE1_epcs_slave_select_reg[2] = DFFEAS(DE1_epcs_slave_select_reg[2]_lut_out, QC2__clk0, F1_data_out, , DE1L142, , , , );

--DE1_rx_holding_reg[2] is std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|rx_holding_reg[2]

--operation mode is normal

DE1_rx_holding_reg[2]_lut_out = DE1_shift_reg[2];

DE1_rx_holding_reg[2] = DFFEAS(DE1_rx_holding_reg[2]_lut_out, QC2__clk0, F1_data_out, , DE1L156, , , , );

--X1L14 is std_1c20:inst|epcs_controller_epcs_control_port_arbitrator:the_epcs_controller_epcs_control_port|epcs_controller_epcs_control_port_address[0]~67

--operation mode is normal

X1L14 = X1L2 & S1_M_alu_result[2] # !X1L2 & (S1_ic_fill_ap_offset[0]);

--X1L16 is std_1c20:inst|epcs_controller_epcs_control_port_arbitrator:the_epcs_controller_epcs_control_port|epcs_controller_epcs_control_port_address[2]~68

--operation mode is normal

X1L16 = X1L2 & S1_M_alu_result[4] # !X1L2 & (S1_ic_fill_ap_offset[2]);

--X1L15 is std_1c20:inst|epcs_controller_epcs_control_port_arbitrator:the_epcs_controller_epcs_control_port|epcs_controller_epcs_control_port_address[1]~69

--operation mode is normal

X1L15 = X1L2 & S1_M_alu_result[3] # !X1L2 & (S1_ic_fill_ap_offset[1]);

--DE1L113 is std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|Equal0~140

--operation mode is normal

DE1L113 = X1L14 & X1L16 & (!X1L15);

--DE1L133 is std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|p1_data_to_cpu[2]~867

--operation mode is normal

DE1L133 = DE1L113 & DE1_epcs_slave_select_reg[2] # !DE1L113 & (DE1_rx_holding_reg[2]);

--DE1L114 is std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|Equal0~141

--operation mode is normal

DE1L114 = X1L15 & X1L16 & (!X1L14);

--X1L17 is std_1c20:inst|epcs_controller_epcs_control_port_arbitrator:the_epcs_controller_epcs_control_port|epcs_controller_epcs_control_port_address[3]~70

--operation mode is normal

X1L17 = X1L2 & S1_M_alu_result[5] # !X1L2 & (S1_ic_fill_line[0]);

--X1L18 is std_1c20:inst|epcs_controller_epcs_control_port_arbitrator:the_epcs_controller_epcs_control_port|epcs_controller_epcs_control_port_address[4]~71

--operation mode is normal

X1L18 = X1L2 & S1_M_alu_result[6] # !X1L2 & (S1_ic_fill_line[1]);

--X1L19 is std_1c20:inst|epcs_controller_epcs_control_port_arbitrator:the_epcs_controller_epcs_control_port|epcs_controller_epcs_control_port_address[5]~72

--operation mode is normal

X1L19 = X1L2 & S1_M_alu_result[7] # !X1L2 & (S1_ic_fill_line[2]);

--X1L20 is std_1c20:inst|epcs_controller_epcs_control_port_arbitrator:the_epcs_controller_epcs_control_port|epcs_controller_epcs_control_port_address[6]~73

--operation mode is normal

X1L20 = X1L2 & S1_M_alu_result[8] # !X1L2 & (S1_ic_fill_line[3]);

--SD1_internal_jdo1[23] is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|internal_jdo1[23]

--operation mode is normal

SD1_internal_jdo1[23] = AMPP_FUNCTION(A1L8, SD1_sr[23], VCC, SD1L145);

--JD1L5 is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_debug:the_cpu_nios2_oci_debug|internal_monitor_go~102

--operation mode is normal

JD1L5 = AMPP_FUNCTION(SD1_internal_jdo1[34], SD1L190, A1L3, JD1_internal_monitor_go);

--RD1_MonWr is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|MonWr

--operation mode is normal

RD1_MonWr = AMPP_FUNCTION(QC2__clk0, RD1_MonWr, JD1_resetrequest, GND, V1L26, !C1_CLR_SIGNAL, SD1L192, SD1L190);

--V1L27 is std_1c20:inst|cpu_jtag_debug_module_arbitrator:the_cpu_jtag_debug_module|cpu_jtag_debug_module_byteenable[0]~4

--operation mode is normal

V1L27 = S1_M_mem_byte_en[0] # !V1L4;

--RD1_internal_MonDReg[0] is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|internal_MonDReg[0]

--operation mode is normal

RD1_internal_MonDReg[0] = AMPP_FUNCTION(QC2__clk0, SD1_internal_jdo1[3], RD1L28, RD1_MonRd1, SD1L192, !C1_CLR_SIGNAL, RD1L29);

--RD1_internal_MonDReg[1] is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|internal_MonDReg[1]

--operation mode is normal

RD1_internal_MonDReg[1] = AMPP_FUNCTION(QC2__clk0, CE1_q_b[1], RD1L19, SD1_internal_jdo1[4], RD1_MonAReg[10], !C1_CLR_SIGNAL, RD1L30, RD1L29);

--RD1_internal_MonDReg[2] is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|internal_MonDReg[2]

--operation mode is normal

RD1_internal_MonDReg[2] = AMPP_FUNCTION(QC2__clk0, CE1_q_b[2], RD1L20, SD1_internal_jdo1[5], RD1_MonAReg[10], !C1_CLR_SIGNAL, RD1L30, RD1L29);

--RD1_internal_MonDReg[3] is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|internal_MonDReg[3]

--operation mode is normal

RD1_internal_MonDReg[3] = AMPP_FUNCTION(QC2__clk0, CE1_q_b[3], RD1L1, SD1_internal_jdo1[6], RD1_MonAReg[10], !C1_CLR_SIGNAL, RD1L30, RD1L29);

--RD1_internal_MonDReg[4] is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|internal_MonDReg[4]

--operation mode is normal

RD1_internal_MonDReg[4] = AMPP_FUNCTION(QC2__clk0, CE1_q_b[4], RD1L19, SD1_internal_jdo1[7], RD1_MonAReg[10], !C1_CLR_SIGNAL, RD1L30, RD1L29);

--RD1_internal_MonDReg[5] is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|internal_MonDReg[5]

--operation mode is normal

RD1_internal_MonDReg[5] = AMPP_FUNCTION(QC2__clk0, CE1_q_b[5], RD1L21, SD1_internal_jdo1[8], RD1_MonAReg[10], !C1_CLR_SIGNAL, RD1L30, RD1L29);

--RD1_internal_MonDReg[6] is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|internal_MonDReg[6]

--operation mode is normal

RD1_internal_MonDReg[6] = AMPP_FUNCTION(QC2__clk0, SD1_internal_jdo1[9], CE1_q_b[6], RD1L30, RD1_MonAReg[10], !C1_CLR_SIGNAL, RD1L29);

--RD1_internal_MonDReg[7] is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|internal_MonDReg[7]

--operation mode is normal

RD1_internal_MonDReg[7] = AMPP_FUNCTION(QC2__clk0, SD1_internal_jdo1[10], CE1_q_b[7], RD1L30, RD1_MonAReg[10], !C1_CLR_SIGNAL, RD1L29);

--RD1_MonAReg[2] is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|MonAReg[2]

--operation mode is normal

RD1_MonAReg[2] = AMPP_FUNCTION(QC2__clk0, SD1_internal_jdo1[26], RD1L73, RD1L2, SD1L191, !C1_CLR_SIGNAL, SD1L193);

--RD1_MonAReg[3] is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|MonAReg[3]

--operation mode is normal

RD1_MonAReg[3] = AMPP_FUNCTION(QC2__clk0, SD1_internal_jdo1[27], RD1L74, RD1L4, SD1L191, !C1_CLR_SIGNAL, SD1L193);

--RD1_MonAReg[4] is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|MonAReg[4]

--operation mode is normal

RD1_MonAReg[4] = AMPP_FUNCTION(QC2__clk0, SD1_internal_jdo1[28], RD1L75, RD1L6, SD1L191, !C1_CLR_SIGNAL, SD1L193);

--RD1_MonAReg[5] is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|MonAReg[5]

--operation mode is normal

RD1_MonAReg[5] = AMPP_FUNCTION(QC2__clk0, SD1_internal_jdo1[29], RD1L76, RD1L8, SD1L191, !C1_CLR_SIGNAL, SD1L193);

--RD1_MonAReg[6] is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|MonAReg[6]

--operation mode is normal

RD1_MonAReg[6] = AMPP_FUNCTION(QC2__clk0, SD1_internal_jdo1[30], RD1L77, RD1L10, SD1L191, !C1_CLR_SIGNAL, SD1L193);

--RD1_MonAReg[7] is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|MonAReg[7]

--operation mode is normal

RD1_MonAReg[7] = AMPP_FUNCTION(QC2__clk0, SD1_internal_jdo1[31], RD1L78, RD1L12, SD1L191, !C1_CLR_SIGNAL, SD1L193);

--RD1_MonAReg[8] is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|MonAReg[8]

--operation mode is normal

RD1_MonAReg[8] = AMPP_FUNCTION(QC2__clk0, SD1_internal_jdo1[32], RD1L79, RD1L14, SD1L191, !C1_CLR_SIGNAL, SD1L193);

--RD1_MonAReg[9] is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|MonAReg[9]

--operation mode is normal

RD1_MonAReg[9] = AMPP_FUNCTION(QC2__clk0, SD1_internal_jdo1[33], RD1L80, RD1L16, SD1L191, !C1_CLR_SIGNAL, SD1L193);

--T1L296 is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|process5~0

--operation mode is normal

T1L296 = T1_internal_cpu_data_master_dbs_address[1] & T1L293 & (!T1_internal_cpu_data_master_dbs_address[0]);

--KB1_za_data[18] is std_1c20:inst|sdram:the_sdram|za_data[18]

--operation mode is normal

KB1_za_data[18]_lut_out = A1L250;

KB1_za_data[18] = DFFEAS(KB1_za_data[18]_lut_out, QC2__clk0, F1_data_out, , , , , , );

--T1L259 is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|p1_registered_cpu_data_master_readdata[18]~2029

--operation mode is normal

T1L259 = S1_M_alu_result[25] # KB1_za_data[18] # !QB1L1 # !S1_M_alu_result[24];

--RE2_safe_q[2] is std_1c20:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_r:the_jtag_uart_scfifo_r|scfifo:rfifo|scfifo_jf21:auto_generated|a_dpfifo_ml21:dpfifo|a_fefifo_7cf:fifo_state|cntr_9c7:count_usedw|safe_q[2]

--operation mode is arithmetic

RE2_safe_q[2]_carry_eqn = RE2L4;

RE2_safe_q[2]_lut_out = RE2_safe_q[2] $ (!RE2_safe_q[2]_carry_eqn);

RE2_safe_q[2] = DFFEAS(RE2_safe_q[2]_lut_out, QC2__clk0, F1_data_out, , NE2L1, , , , );

--RE2L6 is std_1c20:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_r:the_jtag_uart_scfifo_r|scfifo:rfifo|scfifo_jf21:auto_generated|a_dpfifo_ml21:dpfifo|a_fefifo_7cf:fifo_state|cntr_9c7:count_usedw|counter_cella2~COUT

--operation mode is arithmetic

RE2L6 = CARRY(!RE2L4 & (RE2_safe_q[2] $ !BB1_wr_rfifo));

--BB1L16 is std_1c20:inst|jtag_uart:the_jtag_uart|Add1~290

--operation mode is arithmetic

BB1L16_carry_eqn = BB1L32;

BB1L16 = RE1_safe_q[2] $ (BB1L16_carry_eqn);

--BB1L17 is std_1c20:inst|jtag_uart:the_jtag_uart|Add1~291

--operation mode is arithmetic

BB1L17 = CARRY(!RE1_safe_q[2] & (!BB1L32));

--BB1L18 is std_1c20:inst|jtag_uart:the_jtag_uart|Add1~292

--operation mode is normal

BB1L18 = BB1_read_0 & RE2_safe_q[2] # !BB1_read_0 & (BB1L16);

--V1L29 is std_1c20:inst|cpu_jtag_debug_module_arbitrator:the_cpu_jtag_debug_module|cpu_jtag_debug_module_byteenable[2]~5

--operation mode is normal

V1L29 = S1_M_mem_byte_en[2] # !V1L4;

--RD1_internal_MonDReg[16] is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|internal_MonDReg[16]

--operation mode is normal

RD1_internal_MonDReg[16] = AMPP_FUNCTION(QC2__clk0, SD1_internal_jdo1[19], CE1_q_b[16], RD1L30, RD1_MonAReg[10], !C1_CLR_SIGNAL, RD1L29);

--RD1_internal_MonDReg[17] is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|internal_MonDReg[17]

--operation mode is normal

RD1_internal_MonDReg[17] = AMPP_FUNCTION(QC2__clk0, SD1_internal_jdo1[20], CE1_q_b[17], RD1L30, RD1_MonAReg[10], !C1_CLR_SIGNAL, RD1L29);

--RD1_internal_MonDReg[18] is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|internal_MonDReg[18]

--operation mode is normal

RD1_internal_MonDReg[18] = AMPP_FUNCTION(QC2__clk0, CE1_q_b[18], RD1L22, SD1_internal_jdo1[21], RD1_MonAReg[10], !C1_CLR_SIGNAL, RD1L30, RD1L29);

--RD1_internal_MonDReg[19] is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|internal_MonDReg[19]

--operation mode is normal

RD1_internal_MonDReg[19] = AMPP_FUNCTION(QC2__clk0, SD1_internal_jdo1[22], CE1_q_b[19], RD1L30, RD1_MonAReg[10], !C1_CLR_SIGNAL, RD1L29);

--RD1_internal_MonDReg[20] is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|internal_MonDReg[20]

--operation mode is normal

RD1_internal_MonDReg[20] = AMPP_FUNCTION(QC2__clk0, SD1_internal_jdo1[23], CE1_q_b[20], RD1L30, RD1_MonAReg[10], !C1_CLR_SIGNAL, RD1L29);

--RD1_internal_MonDReg[21] is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|internal_MonDReg[21]

--operation mode is normal

RD1_internal_MonDReg[21] = AMPP_FUNCTION(QC2__clk0, SD1_internal_jdo1[24], CE1_q_b[21], RD1L30, RD1_MonAReg[10], !C1_CLR_SIGNAL, RD1L29);

--RD1_internal_MonDReg[22] is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|internal_MonDReg[22]

--operation mode is normal

RD1_internal_MonDReg[22] = AMPP_FUNCTION(QC2__clk0, SD1_internal_jdo1[25], CE1_q_b[22], RD1L30, RD1_MonAReg[10], !C1_CLR_SIGNAL, RD1L29);

--RD1_internal_MonDReg[23] is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|internal_MonDReg[23]

--operation mode is normal

RD1_internal_MonDReg[23] = AMPP_FUNCTION(QC2__clk0, SD1_internal_jdo1[26], CE1_q_b[23], RD1L30, RD1_MonAReg[10], !C1_CLR_SIGNAL, RD1L29);

--S1_i_readdata_d1[12] is std_1c20:inst|cpu:the_cpu|i_readdata_d1[12]

--operation mode is normal

S1_i_readdata_d1[12] = AMPP_FUNCTION(QC2__clk0, U1L44, WC1L19, WC1L13, V1_cpu_instruction_master_qualified_request_cpu_jtag_debug_module, F1_data_out);

--S1_i_readdata_d1[13] is std_1c20:inst|cpu:the_cpu|i_readdata_d1[13]

--operation mode is normal

S1_i_readdata_d1[13] = AMPP_FUNCTION(QC2__clk0, U1L47, WC1L19, WC1L14, V1_cpu_instruction_master_qualified_request_cpu_jtag_debug_module, F1_data_out);

--S1_i_readdata_d1[11] is std_1c20:inst|cpu:the_cpu|i_readdata_d1[11]

--operation mode is normal

S1_i_readdata_d1[11] = AMPP_FUNCTION(QC2__clk0, U1L41, WC1L19, WC1L12, V1_cpu_instruction_master_qualified_request_cpu_jtag_debug_module, F1_data_out);

--S1_i_readdata_d1[14] is std_1c20:inst|cpu:the_cpu|i_readdata_d1[14]

--operation mode is normal

S1_i_readdata_d1[14] = AMPP_FUNCTION(QC2__clk0, U1L50, WC1L19, WC1L15, V1_cpu_instruction_master_qualified_request_cpu_jtag_debug_module, F1_data_out);

--S1_i_readdata_d1[21] is std_1c20:inst|cpu:the_cpu|i_readdata_d1[21]

--operation mode is normal

S1_i_readdata_d1[21] = AMPP_FUNCTION(QC2__clk0, U1L70, WC1L19, WC1L23, V1_cpu_instruction_master_qualified_request_cpu_jtag_debug_module, F1_data_out);

--S1_i_readdata_d1[16] is std_1c20:inst|cpu:the_cpu|i_readdata_d1[16]

--operation mode is normal

S1_i_readdata_d1[16] = AMPP_FUNCTION(QC2__clk0, U1L55, WC1L19, WC1L17, V1_cpu_instruction_master_qualified_request_cpu_jtag_debug_module, F1_data_out);

--Z1_internal_counter[0] is std_1c20:inst|high_res_timer:the_high_res_timer|internal_counter[0]

--operation mode is arithmetic

Z1_internal_counter[0]_lut_out = !Z1_internal_counter[0];

Z1_internal_counter[0] = DFFEAS(Z1_internal_counter[0]_lut_out, QC2__clk0, F1_data_out, , Z1L155, Z1_period_l_register[0], , , Z1L156);

--Z1L57 is std_1c20:inst|high_res_timer:the_high_res_timer|internal_counter[0]~2944

--operation mode is arithmetic

Z1L57 = CARRY(!Z1_internal_counter[0]);

--Z1_internal_counter[1] is std_1c20:inst|high_res_timer:the_high_res_timer|internal_counter[1]

--operation mode is arithmetic

Z1_internal_counter[1]_carry_eqn = Z1L57;

Z1_internal_counter[1]_lut_out = Z1_internal_counter[1] $ (!Z1_internal_counter[1]_carry_eqn);

Z1_internal_counter[1] = DFFEAS(Z1_internal_counter[1]_lut_out, QC2__clk0, F1_data_out, , Z1L155, Z1_period_l_register[1], , , Z1L156);

--Z1L59 is std_1c20:inst|high_res_timer:the_high_res_timer|internal_counter[1]~2945

--operation mode is arithmetic

Z1L59 = CARRY(Z1_internal_counter[1] & (!Z1L57));

--Z1_internal_counter[2] is std_1c20:inst|high_res_timer:the_high_res_timer|internal_counter[2]

--operation mode is arithmetic

Z1_internal_counter[2]_carry_eqn = Z1L59;

Z1_internal_counter[2]_lut_out = Z1_internal_counter[2] $ (Z1_internal_counter[2]_carry_eqn);

Z1_internal_counter[2] = DFFEAS(Z1_internal_counter[2]_lut_out, QC2__clk0, F1_data_out, , Z1L155, Z1_period_l_register[2], , , Z1L156);

--Z1L61 is std_1c20:inst|high_res_timer:the_high_res_timer|internal_counter[2]~2946

--operation mode is arithmetic

Z1L61 = CARRY(!Z1L59 # !Z1_internal_counter[2]);

--Z1_internal_counter[3] is std_1c20:inst|high_res_timer:the_high_res_timer|internal_counter[3]

--operation mode is arithmetic

Z1_internal_counter[3]_carry_eqn = Z1L61;

Z1_internal_counter[3]_lut_out = Z1_internal_counter[3] $ (!Z1_internal_counter[3]_carry_eqn);

Z1_internal_counter[3] = DFFEAS(Z1_internal_counter[3]_lut_out, QC2__clk0, F1_data_out, , Z1L155, Z1_period_l_register[3], , , Z1L156);

--Z1L63 is std_1c20:inst|high_res_timer:the_high_res_timer|internal_counter[3]~2947

--operation mode is arithmetic

Z1L63 = CARRY(Z1_internal_counter[3] & (!Z1L61));

--Z1L44 is std_1c20:inst|high_res_timer:the_high_res_timer|Equal0~370

--operation mode is normal

Z1L44 = Z1_internal_counter[0] & Z1_internal_counter[1] & Z1_internal_counter[2] & Z1_internal_counter[3];

--Z1_internal_counter[6] is std_1c20:inst|high_res_timer:the_high_res_timer|internal_counter[6]

--operation mode is arithmetic

Z1_internal_counter[6]_carry_eqn = Z1L67;

Z1_internal_counter[6]_lut_out = Z1_internal_counter[6] $ (Z1_internal_counter[6]_carry_eqn);

Z1_internal_counter[6] = DFFEAS(Z1_internal_counter[6]_lut_out, QC2__clk0, F1_data_out, , Z1L155, Z1_period_l_register[6], , , Z1L156);

--Z1L69 is std_1c20:inst|high_res_timer:the_high_res_timer|internal_counter[6]~2948

--operation mode is arithmetic

Z1L69 = CARRY(!Z1L67 # !Z1_internal_counter[6]);

--Z1_internal_counter[4] is std_1c20:inst|high_res_timer:the_high_res_timer|internal_counter[4]

--operation mode is arithmetic

Z1_internal_counter[4]_carry_eqn = Z1L63;

Z1_internal_counter[4]_lut_out = Z1_internal_counter[4] $ (Z1_internal_counter[4]_carry_eqn);

Z1_internal_counter[4] = DFFEAS(Z1_internal_counter[4]_lut_out, QC2__clk0, F1_data_out, , Z1L155, Z1_period_l_register[4], , , Z1L156);

--Z1L65 is std_1c20:inst|high_res_timer:the_high_res_timer|internal_counter[4]~2949

--operation mode is arithmetic

Z1L65 = CARRY(Z1_internal_counter[4] # !Z1L63);

--Z1_internal_counter[5] is std_1c20:inst|high_res_timer:the_high_res_timer|internal_counter[5]

--operation mode is arithmetic

Z1_internal_counter[5]_carry_eqn = Z1L65;

Z1_internal_counter[5]_lut_out = Z1_internal_counter[5] $ (!Z1_internal_counter[5]_carry_eqn);

Z1_internal_counter[5] = DFFEAS(Z1_internal_counter[5]_lut_out, QC2__clk0, F1_data_out, , Z1L155, Z1_period_l_register[5], , , Z1L156);

--Z1L67 is std_1c20:inst|high_res_timer:the_high_res_timer|internal_counter[5]~2950

--operation mode is arithmetic

Z1L67 = CARRY(!Z1_internal_counter[5] & (!Z1L65));

--Z1_internal_counter[7] is std_1c20:inst|high_res_timer:the_high_res_timer|internal_counter[7]

--operation mode is arithmetic

Z1_internal_counter[7]_carry_eqn = Z1L69;

Z1_internal_counter[7]_lut_out = Z1_internal_counter[7] $ (!Z1_internal_counter[7]_carry_eqn);

Z1_internal_counter[7] = DFFEAS(Z1_internal_counter[7]_lut_out, QC2__clk0, F1_data_out, , Z1L155, Z1_period_l_register[7], , , Z1L156);

--Z1L71 is std_1c20:inst|high_res_timer:the_high_res_timer|internal_counter[7]~2951

--operation mode is arithmetic

Z1L71 = CARRY(!Z1_internal_counter[7] & (!Z1L69));

--Z1L45 is std_1c20:inst|high_res_timer:the_high_res_timer|Equal0~371

--operation mode is normal

Z1L45 = Z1_internal_counter[6] & !Z1_internal_counter[4] & !Z1_internal_counter[5] & !Z1_internal_counter[7];

--Z1_internal_counter[8] is std_1c20:inst|high_res_timer:the_high_res_timer|internal_counter[8]

--operation mode is arithmetic

Z1_internal_counter[8]_carry_eqn = Z1L71;

Z1_internal_counter[8]_lut_out = Z1_internal_counter[8] $ (Z1_internal_counter[8]_carry_eqn);

Z1_internal_counter[8] = DFFEAS(Z1_internal_counter[8]_lut_out, QC2__clk0, F1_data_out, , Z1L155, Z1_period_l_register[8], , , Z1L156);

--Z1L73 is std_1c20:inst|high_res_timer:the_high_res_timer|internal_counter[8]~2952

--operation mode is arithmetic

Z1L73 = CARRY(!Z1L71 # !Z1_internal_counter[8]);

--Z1_internal_counter[9] is std_1c20:inst|high_res_timer:the_high_res_timer|internal_counter[9]

--operation mode is arithmetic

Z1_internal_counter[9]_carry_eqn = Z1L73;

Z1_internal_counter[9]_lut_out = Z1_internal_counter[9] $ (!Z1_internal_counter[9]_carry_eqn);

Z1_internal_counter[9] = DFFEAS(Z1_internal_counter[9]_lut_out, QC2__clk0, F1_data_out, , Z1L155, Z1_period_l_register[9], , , Z1L156);

--Z1L75 is std_1c20:inst|high_res_timer:the_high_res_timer|internal_counter[9]~2953

--operation mode is arithmetic

Z1L75 = CARRY(Z1_internal_counter[9] & (!Z1L73));

--Z1_internal_counter[10] is std_1c20:inst|high_res_timer:the_high_res_timer|internal_counter[10]

--operation mode is arithmetic

Z1_internal_counter[10]_carry_eqn = Z1L75;

Z1_internal_counter[10]_lut_out = Z1_internal_counter[10] $ (Z1_internal_counter[10]_carry_eqn);

Z1_internal_counter[10] = DFFEAS(Z1_internal_counter[10]_lut_out, QC2__clk0, F1_data_out, , Z1L155, Z1_period_l_register[10], , , Z1L156);

--Z1L77 is std_1c20:inst|high_res_timer:the_high_res_timer|internal_counter[10]~2954

--operation mode is arithmetic

Z1L77 = CARRY(Z1_internal_counter[10] # !Z1L75);

--Z1_internal_counter[11] is std_1c20:inst|high_res_timer:the_high_res_timer|internal_counter[11]

--operation mode is arithmetic

Z1_internal_counter[11]_carry_eqn = Z1L77;

Z1_internal_counter[11]_lut_out = Z1_internal_counter[11] $ (!Z1_internal_counter[11]_carry_eqn);

Z1_internal_counter[11] = DFFEAS(Z1_internal_counter[11]_lut_out, QC2__clk0, F1_data_out, , Z1L155, Z1_period_l_register[11], , , Z1L156);

--Z1L79 is std_1c20:inst|high_res_timer:the_high_res_timer|internal_counter[11]~2955

--operation mode is arithmetic

Z1L79 = CARRY(!Z1_internal_counter[11] & (!Z1L77));

--Z1L46 is std_1c20:inst|high_res_timer:the_high_res_timer|Equal0~372

--operation mode is normal

Z1L46 = Z1_internal_counter[8] & Z1_internal_counter[9] & !Z1_internal_counter[10] & !Z1_internal_counter[11];

--Z1_internal_counter[14] is std_1c20:inst|high_res_timer:the_high_res_timer|internal_counter[14]

--operation mode is arithmetic

Z1_internal_counter[14]_carry_eqn = Z1L83;

Z1_internal_counter[14]_lut_out = Z1_internal_counter[14] $ (Z1_internal_counter[14]_carry_eqn);

Z1_internal_counter[14] = DFFEAS(Z1_internal_counter[14]_lut_out, QC2__clk0, F1_data_out, , Z1L155, Z1_period_l_register[14], , , Z1L156);

--Z1L85 is std_1c20:inst|high_res_timer:the_high_res_timer|internal_counter[14]~2956

--operation mode is arithmetic

Z1L85 = CARRY(!Z1L83 # !Z1_internal_counter[14]);

--Z1_internal_counter[15] is std_1c20:inst|high_res_timer:the_high_res_timer|internal_counter[15]

--operation mode is arithmetic

Z1_internal_counter[15]_carry_eqn = Z1L85;

Z1_internal_counter[15]_lut_out = Z1_internal_counter[15] $ (!Z1_internal_counter[15]_carry_eqn);

Z1_internal_counter[15] = DFFEAS(Z1_internal_counter[15]_lut_out, QC2__clk0, F1_data_out, , Z1L155, Z1_period_l_register[15], , , Z1L156);

--Z1L87 is std_1c20:inst|high_res_timer:the_high_res_timer|internal_counter[15]~2957

--operation mode is arithmetic

Z1L87 = CARRY(Z1_internal_counter[15] & (!Z1L85));

--Z1_internal_counter[12] is std_1c20:inst|high_res_timer:the_high_res_timer|internal_counter[12]

--operation mode is arithmetic

Z1_internal_counter[12]_carry_eqn = Z1L79;

Z1_internal_counter[12]_lut_out = Z1_internal_counter[12] $ (Z1_internal_counter[12]_carry_eqn);

Z1_internal_counter[12] = DFFEAS(Z1_internal_counter[12]_lut_out, QC2__clk0, F1_data_out, , Z1L155, Z1_period_l_register[12], , , Z1L156);

--Z1L81 is std_1c20:inst|high_res_timer:the_high_res_timer|internal_counter[12]~2958

--operation mode is arithmetic

Z1L81 = CARRY(Z1_internal_counter[12] # !Z1L79);

--Z1_internal_counter[13] is std_1c20:inst|high_res_timer:the_high_res_timer|internal_counter[13]

--operation mode is arithmetic

Z1_internal_counter[13]_carry_eqn = Z1L81;

Z1_internal_counter[13]_lut_out = Z1_internal_counter[13] $ (!Z1_internal_counter[13]_carry_eqn);

Z1_internal_counter[13] = DFFEAS(Z1_internal_counter[13]_lut_out, QC2__clk0, F1_data_out, , Z1L155, Z1_period_l_register[13], , , Z1L156);

--Z1L83 is std_1c20:inst|high_res_timer:the_high_res_timer|internal_counter[13]~2959

--operation mode is arithmetic

Z1L83 = CARRY(!Z1_internal_counter[13] & (!Z1L81));

--Z1L47 is std_1c20:inst|high_res_timer:the_high_res_timer|Equal0~373

--operation mode is normal

Z1L47 = Z1_internal_counter[14] & Z1_internal_counter[15] & !Z1_internal_counter[12] & !Z1_internal_counter[13];

--Z1L48 is std_1c20:inst|high_res_timer:the_high_res_timer|Equal0~374

--operation mode is normal

Z1L48 = Z1L44 & Z1L45 & Z1L46 & Z1L47;

--Z1_internal_counter[16] is std_1c20:inst|high_res_timer:the_high_res_timer|internal_counter[16]

--operation mode is arithmetic

Z1_internal_counter[16]_carry_eqn = Z1L87;

Z1_internal_counter[16]_lut_out = Z1_internal_counter[16] $ (Z1_internal_counter[16]_carry_eqn);

Z1_internal_counter[16] = DFFEAS(Z1_internal_counter[16]_lut_out, QC2__clk0, F1_data_out, , Z1L155, Z1_period_h_register[0], , , Z1L156);

--Z1L89 is std_1c20:inst|high_res_timer:the_high_res_timer|internal_counter[16]~2960

--operation mode is arithmetic

Z1L89 = CARRY(Z1_internal_counter[16] # !Z1L87);

--Z1_internal_counter[17] is std_1c20:inst|high_res_timer:the_high_res_timer|internal_counter[17]

--operation mode is arithmetic

Z1_internal_counter[17]_carry_eqn = Z1L89;

Z1_internal_counter[17]_lut_out = Z1_internal_counter[17] $ (!Z1_internal_counter[17]_carry_eqn);

Z1_internal_counter[17] = DFFEAS(Z1_internal_counter[17]_lut_out, QC2__clk0, F1_data_out, , Z1L155, Z1_period_h_register[1], , , Z1L156);

--Z1L91 is std_1c20:inst|high_res_timer:the_high_res_timer|internal_counter[17]~2961

--operation mode is arithmetic

Z1L91 = CARRY(!Z1_internal_counter[17] & (!Z1L89));

--Z1_internal_counter[18] is std_1c20:inst|high_res_timer:the_high_res_timer|internal_counter[18]

--operation mode is arithmetic

Z1_internal_counter[18]_carry_eqn = Z1L91;

Z1_internal_counter[18]_lut_out = Z1_internal_counter[18] $ (Z1_internal_counter[18]_carry_eqn);

Z1_internal_counter[18] = DFFEAS(Z1_internal_counter[18]_lut_out, QC2__clk0, F1_data_out, , Z1L155, Z1_period_h_register[2], , , Z1L156);

--Z1L93 is std_1c20:inst|high_res_timer:the_high_res_timer|internal_counter[18]~2962

--operation mode is arithmetic

Z1L93 = CARRY(Z1_internal_counter[18] # !Z1L91);

--Z1_internal_counter[19] is std_1c20:inst|high_res_timer:the_high_res_timer|internal_counter[19]

--operation mode is arithmetic

Z1_internal_counter[19]_carry_eqn = Z1L93;

Z1_internal_counter[19]_lut_out = Z1_internal_counter[19] $ (!Z1_internal_counter[19]_carry_eqn);

Z1_internal_counter[19] = DFFEAS(Z1_internal_counter[19]_lut_out, QC2__clk0, F1_data_out, , Z1L155, Z1_period_h_register[3], , , Z1L156);

--Z1L95 is std_1c20:inst|high_res_timer:the_high_res_timer|internal_counter[19]~2963

--operation mode is arithmetic

Z1L95 = CARRY(!Z1_internal_counter[19] & (!Z1L93));

--Z1L49 is std_1c20:inst|high_res_timer:the_high_res_timer|Equal0~375

--operation mode is normal

Z1L49 = !Z1_internal_counter[16] & !Z1_internal_counter[17] & !Z1_internal_counter[18] & !Z1_internal_counter[19];

--Z1_internal_counter[20] is std_1c20:inst|high_res_timer:the_high_res_timer|internal_counter[20]

--operation mode is arithmetic

Z1_internal_counter[20]_carry_eqn = Z1L95;

Z1_internal_counter[20]_lut_out = Z1_internal_counter[20] $ (Z1_internal_counter[20]_carry_eqn);

Z1_internal_counter[20] = DFFEAS(Z1_internal_counter[20]_lut_out, QC2__clk0, F1_data_out, , Z1L155, Z1_period_h_register[4], , , Z1L156);

--Z1L97 is std_1c20:inst|high_res_timer:the_high_res_timer|internal_counter[20]~2964

--operation mode is arithmetic

Z1L97 = CARRY(Z1_internal_counter[20] # !Z1L95);

--Z1_internal_counter[21] is std_1c20:inst|high_res_timer:the_high_res_timer|internal_counter[21]

--operation mode is arithmetic

Z1_internal_counter[21]_carry_eqn = Z1L97;

Z1_internal_counter[21]_lut_out = Z1_internal_counter[21] $ (!Z1_internal_counter[21]_carry_eqn);

Z1_internal_counter[21] = DFFEAS(Z1_internal_counter[21]_lut_out, QC2__clk0, F1_data_out, , Z1L155, Z1_period_h_register[5], , , Z1L156);

--Z1L99 is std_1c20:inst|high_res_timer:the_high_res_timer|internal_counter[21]~2965

--operation mode is arithmetic

Z1L99 = CARRY(!Z1_internal_counter[21] & (!Z1L97));

--Z1_internal_counter[22] is std_1c20:inst|high_res_timer:the_high_res_timer|internal_counter[22]

--operation mode is arithmetic

Z1_internal_counter[22]_carry_eqn = Z1L99;

Z1_internal_counter[22]_lut_out = Z1_internal_counter[22] $ (Z1_internal_counter[22]_carry_eqn);

Z1_internal_counter[22] = DFFEAS(Z1_internal_counter[22]_lut_out, QC2__clk0, F1_data_out, , Z1L155, Z1_period_h_register[6], , , Z1L156);

--Z1L101 is std_1c20:inst|high_res_timer:the_high_res_timer|internal_counter[22]~2966

--operation mode is arithmetic

Z1L101 = CARRY(Z1_internal_counter[22] # !Z1L99);

--Z1_internal_counter[23] is std_1c20:inst|high_res_timer:the_high_res_timer|internal_counter[23]

--operation mode is arithmetic

Z1_internal_counter[23]_carry_eqn = Z1L101;

Z1_internal_counter[23]_lut_out = Z1_internal_counter[23] $ (!Z1_internal_counter[23]_carry_eqn);

Z1_internal_counter[23] = DFFEAS(Z1_internal_counter[23]_lut_out, QC2__clk0, F1_data_out, , Z1L155, Z1_period_h_register[7], , , Z1L156);

--Z1L103 is std_1c20:inst|high_res_timer:the_high_res_timer|internal_counter[23]~2967

--operation mode is arithmetic

Z1L103 = CARRY(!Z1_internal_counter[23] & (!Z1L101));

--Z1L50 is std_1c20:inst|high_res_timer:the_high_res_timer|Equal0~376

--operation mode is normal

Z1L50 = !Z1_internal_counter[20] & !Z1_internal_counter[21] & !Z1_internal_counter[22] & !Z1_internal_counter[23];

--Z1_internal_counter[24] is std_1c20:inst|high_res_timer:the_high_res_timer|internal_counter[24]

--operation mode is arithmetic

Z1_internal_counter[24]_carry_eqn = Z1L103;

Z1_internal_counter[24]_lut_out = Z1_internal_counter[24] $ (Z1_internal_counter[24]_carry_eqn);

Z1_internal_counter[24] = DFFEAS(Z1_internal_counter[24]_lut_out, QC2__clk0, F1_data_out, , Z1L155, Z1_period_h_register[8], , , Z1L156);

--Z1L105 is std_1c20:inst|high_res_timer:the_high_res_timer|internal_counter[24]~2968

--operation mode is arithmetic

Z1L105 = CARRY(Z1_internal_counter[24] # !Z1L103);

--Z1_internal_counter[25] is std_1c20:inst|high_res_timer:the_high_res_timer|internal_counter[25]

--operation mode is arithmetic

Z1_internal_counter[25]_carry_eqn = Z1L105;

Z1_internal_counter[25]_lut_out = Z1_internal_counter[25] $ (!Z1_internal_counter[25]_carry_eqn);

Z1_internal_counter[25] = DFFEAS(Z1_internal_counter[25]_lut_out, QC2__clk0, F1_data_out, , Z1L155, Z1_period_h_register[9], , , Z1L156);

--Z1L107 is std_1c20:inst|high_res_timer:the_high_res_timer|internal_counter[25]~2969

--operation mode is arithmetic

Z1L107 = CARRY(!Z1_internal_counter[25] & (!Z1L105));

--Z1_internal_counter[26] is std_1c20:inst|high_res_timer:the_high_res_timer|internal_counter[26]

--operation mode is arithmetic

Z1_internal_counter[26]_carry_eqn = Z1L107;

Z1_internal_counter[26]_lut_out = Z1_internal_counter[26] $ (Z1_internal_counter[26]_carry_eqn);

Z1_internal_counter[26] = DFFEAS(Z1_internal_counter[26]_lut_out, QC2__clk0, F1_data_out, , Z1L155, Z1_period_h_register[10], , , Z1L156);

--Z1L109 is std_1c20:inst|high_res_timer:the_high_res_timer|internal_counter[26]~2970

--operation mode is arithmetic

Z1L109 = CARRY(Z1_internal_counter[26] # !Z1L107);

--Z1_internal_counter[27] is std_1c20:inst|high_res_timer:the_high_res_timer|internal_counter[27]

--operation mode is arithmetic

Z1_internal_counter[27]_carry_eqn = Z1L109;

Z1_internal_counter[27]_lut_out = Z1_internal_counter[27] $ (!Z1_internal_counter[27]_carry_eqn);

Z1_internal_counter[27] = DFFEAS(Z1_internal_counter[27]_lut_out, QC2__clk0, F1_data_out, , Z1L155, Z1_period_h_register[11], , , Z1L156);

--Z1L111 is std_1c20:inst|high_res_timer:the_high_res_timer|internal_counter[27]~2971

--operation mode is arithmetic

Z1L111 = CARRY(!Z1_internal_counter[27] & (!Z1L109));

--Z1L51 is std_1c20:inst|high_res_timer:the_high_res_timer|Equal0~377

--operation mode is normal

Z1L51 = !Z1_internal_counter[24] & !Z1_internal_counter[25] & !Z1_internal_counter[26] & !Z1_internal_counter[27];

--Z1_internal_counter[28] is std_1c20:inst|high_res_timer:the_high_res_timer|internal_counter[28]

--operation mode is arithmetic

Z1_internal_counter[28]_carry_eqn = Z1L111;

Z1_internal_counter[28]_lut_out = Z1_internal_counter[28] $ (Z1_internal_counter[28]_carry_eqn);

Z1_internal_counter[28] = DFFEAS(Z1_internal_counter[28]_lut_out, QC2__clk0, F1_data_out, , Z1L155, Z1_period_h_register[12], , , Z1L156);

--Z1L113 is std_1c20:inst|high_res_timer:the_high_res_timer|internal_counter[28]~2972

--operation mode is arithmetic

Z1L113 = CARRY(Z1_internal_counter[28] # !Z1L111);

--Z1_internal_counter[29] is std_1c20:inst|high_res_timer:the_high_res_timer|internal_counter[29]

--operation mode is arithmetic

Z1_internal_counter[29]_carry_eqn = Z1L113;

Z1_internal_counter[29]_lut_out = Z1_internal_counter[29] $ (!Z1_internal_counter[29]_carry_eqn);

Z1_internal_counter[29] = DFFEAS(Z1_internal_counter[29]_lut_out, QC2__clk0, F1_data_out, , Z1L155, Z1_period_h_register[13], , , Z1L156);

--Z1L115 is std_1c20:inst|high_res_timer:the_high_res_timer|internal_counter[29]~2973

--operation mode is arithmetic

Z1L115 = CARRY(!Z1_internal_counter[29] & (!Z1L113));

--Z1_internal_counter[30] is std_1c20:inst|high_res_timer:the_high_res_timer|internal_counter[30]

--operation mode is arithmetic

Z1_internal_counter[30]_carry_eqn = Z1L115;

Z1_internal_counter[30]_lut_out = Z1_internal_counter[30] $ (Z1_internal_counter[30]_carry_eqn);

Z1_internal_counter[30] = DFFEAS(Z1_internal_counter[30]_lut_out, QC2__clk0, F1_data_out, , Z1L155, Z1_period_h_register[14], , , Z1L156);

--Z1L117 is std_1c20:inst|high_res_timer:the_high_res_timer|internal_counter[30]~2974

--operation mode is arithmetic

Z1L117 = CARRY(Z1_internal_counter[30] # !Z1L115);

--Z1_internal_counter[31] is std_1c20:inst|high_res_timer:the_high_res_timer|internal_counter[31]

--operation mode is normal

Z1_internal_counter[31]_carry_eqn = Z1L117;

Z1_internal_counter[31]_lut_out = Z1_internal_counter[31] $ (!Z1_internal_counter[31]_carry_eqn);

Z1_internal_counter[31] = DFFEAS(Z1_internal_counter[31]_lut_out, QC2__clk0, F1_data_out, , Z1L155, Z1_period_h_register[15], , , Z1L156);

--Z1L52 is std_1c20:inst|high_res_timer:the_high_res_timer|Equal0~378

--operation mode is normal

Z1L52 = !Z1_internal_counter[28] & !Z1_internal_counter[29] & !Z1_internal_counter[30] & !Z1_internal_counter[31];

--Z1L53 is std_1c20:inst|high_res_timer:the_high_res_timer|Equal0~379

--operation mode is normal

Z1L53 = Z1L49 & Z1L50 & Z1L51 & Z1L52;

--Z1_delayed_unxcounter_is_zeroxx0 is std_1c20:inst|high_res_timer:the_high_res_timer|delayed_unxcounter_is_zeroxx0

--operation mode is normal

Z1_delayed_unxcounter_is_zeroxx0_lut_out = Z1L48 & Z1L53;

Z1_delayed_unxcounter_is_zeroxx0 = DFFEAS(Z1_delayed_unxcounter_is_zeroxx0_lut_out, QC2__clk0, F1_data_out, , , , , , );

--Z1L210 is std_1c20:inst|high_res_timer:the_high_res_timer|timeout_occurred~41

--operation mode is normal

Z1L210 = Z1_timeout_occurred # Z1L48 & Z1L53 & !Z1_delayed_unxcounter_is_zeroxx0;

--XE1L21 is std_1c20:inst|uart1:the_uart1|uart1_regs:the_uart1_regs|Equal1~122

--operation mode is normal

XE1L21 = !S1_M_alu_result[2] & !S1_M_alu_result[3] & !S1_M_alu_result[4];

--G1L30 is std_1c20:inst|button_pio:the_button_pio|read_mux_out[3]~378

--operation mode is normal

G1L30 = S1_M_alu_result[2] & G1_edge_capture[3] # !S1_M_alu_result[2] & (G1_irq_mask[3]);

--XE1_control_reg[3] is std_1c20:inst|uart1:the_uart1|uart1_regs:the_uart1_regs|control_reg[3]

--operation mode is normal

XE1_control_reg[3]_lut_out = S1_M_st_data[3];

XE1_control_reg[3] = DFFEAS(XE1_control_reg[3]_lut_out, QC2__clk0, F1_data_out, , XE1L14, , , , );

--XE1L54 is std_1c20:inst|uart1:the_uart1|uart1_regs:the_uart1_regs|selected_read_data[3]~680

--operation mode is normal

XE1L54 = S1_M_alu_result[3] & (XE1_control_reg[3]) # !S1_M_alu_result[3] & XE1_internal_tx_data[3];

--YE1_rx_overrun is std_1c20:inst|uart1:the_uart1|uart1_rx:the_uart1_rx|rx_overrun

--operation mode is normal

YE1_rx_overrun_lut_out = YE1_rx_overrun & (!XE1L20 # !XE1L13) # !YE1_rx_overrun & YE1L54 & (!XE1L20 # !XE1L13);

YE1_rx_overrun = DFFEAS(YE1_rx_overrun_lut_out, QC2__clk0, F1_data_out, , , , , , );

--YE1_rx_data[3] is std_1c20:inst|uart1:the_uart1|uart1_rx:the_uart1_rx|rx_data[3]

--operation mode is normal

YE1_rx_data[3]_lut_out = YE1_unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[4];

YE1_rx_data[3] = DFFEAS(YE1_rx_data[3]_lut_out, QC2__clk0, F1_data_out, , YE1_got_new_char, , , , );

--XE1L55 is std_1c20:inst|uart1:the_uart1|uart1_regs:the_uart1_regs|selected_read_data[3]~681

--operation mode is normal

XE1L55 = S1_M_alu_result[3] & YE1_rx_overrun # !S1_M_alu_result[3] & (YE1_rx_data[3]);

--RB1_counter_snapshot[3] is std_1c20:inst|sys_clk_timer:the_sys_clk_timer|counter_snapshot[3]

--operation mode is normal

RB1_counter_snapshot[3]_lut_out = !RB1_internal_counter[3];

RB1_counter_snapshot[3] = DFFEAS(RB1_counter_snapshot[3]_lut_out, QC2__clk0, F1_data_out, , RB1L209, , , , );

--RB1_period_h_register[3] is std_1c20:inst|sys_clk_timer:the_sys_clk_timer|period_h_register[3]

--operation mode is normal

RB1_period_h_register[3]_lut_out = S1_M_st_data[3];

RB1_period_h_register[3] = DFFEAS(RB1_period_h_register[3]_lut_out, QC2__clk0, F1_data_out, , RB1_period_h_wr_strobe, , , , );

--RB1L166 is std_1c20:inst|sys_clk_timer:the_sys_clk_timer|read_mux_out[3]~1240

--operation mode is normal

RB1L166 = XE1L15 & (RB1_period_h_register[3] # XE1L19 & RB1_counter_snapshot[3]) # !XE1L15 & XE1L19 & RB1_counter_snapshot[3];

--RB1_counter_snapshot[19] is std_1c20:inst|sys_clk_timer:the_sys_clk_timer|counter_snapshot[19]

--operation mode is normal

RB1_counter_snapshot[19]_lut_out = RB1_internal_counter[19];

RB1_counter_snapshot[19] = DFFEAS(RB1_counter_snapshot[19]_lut_out, QC2__clk0, F1_data_out, , RB1L209, , , , );

--RB1_control_register[3] is std_1c20:inst|sys_clk_timer:the_sys_clk_timer|control_register[3]

--operation mode is normal

RB1_control_register[3]_lut_out = S1_M_st_data[3];

RB1_control_register[3] = DFFEAS(RB1_control_register[3]_lut_out, QC2__clk0, F1_data_out, , RB1_control_wr_strobe, , , , );

--RB1L167 is std_1c20:inst|sys_clk_timer:the_sys_clk_timer|read_mux_out[3]~1241

--operation mode is normal

RB1L167 = XE1L17 & (S1_M_alu_result[4] & RB1_counter_snapshot[19] # !S1_M_alu_result[4] & (RB1_control_register[3]));

--RB1_period_l_register[3] is std_1c20:inst|sys_clk_timer:the_sys_clk_timer|period_l_register[3]

--operation mode is normal

RB1_period_l_register[3]_lut_out = !S1_M_st_data[3];

RB1_period_l_register[3] = DFFEAS(RB1_period_l_register[3]_lut_out, QC2__clk0, F1_data_out, , RB1_period_l_wr_strobe, , , , );

--M1_slave_readdata[3] is std_1c20:inst|clock_1:the_clock_1|slave_readdata[3]

--operation mode is normal

M1_slave_readdata[3]_lut_out = M1_slave_readdata_p1[3];

M1_slave_readdata[3] = DFFEAS(M1_slave_readdata[3]_lut_out, QC2__clk0, F1_data_out, , , , , , );

--J1_slave_readdata[3] is std_1c20:inst|clock_0:the_clock_0|slave_readdata[3]

--operation mode is normal

J1_slave_readdata[3]_lut_out = J1_slave_readdata_p1[3];

J1_slave_readdata[3] = DFFEAS(J1_slave_readdata[3]_lut_out, QC2__clk0, F1_data_out, , , , , , );

--T1L246 is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|p1_registered_cpu_data_master_readdata[3]~2031

--operation mode is normal

T1L246 = S1_M_alu_result[5] & M1_slave_readdata[3] # !S1_M_alu_result[5] & (J1_slave_readdata[3]) # !K1L6;

--SE2_q_b[3] is std_1c20:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_r:the_jtag_uart_scfifo_r|scfifo:rfifo|scfifo_jf21:auto_generated|a_dpfifo_ml21:dpfifo|dpram_j921:FIFOram|altsyncram_nll1:altsyncram1|q_b[3]

--RAM Block Operation Mode: Simple Dual-Port

--Port A Depth: 64, Port A Width: 1, Port B Depth: 64, Port B Width: 1

--Port A Logical Depth: 64, Port A Logical Width: 8, Port B Logical Depth: 64, Port B Logical Width: 8

--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered

SE2_q_b[3]_PORT_A_data_in = GE1_wdata[3];

SE2_q_b[3]_PORT_A_data_in_reg = DFFE(SE2_q_b[3]_PORT_A_data_in, SE2_q_b[3]_clock_0, , , SE2_q_b[3]_clock_enable_0);

SE2_q_b[3]_PORT_A_address = BUS(QE4_safe_q[0], QE4_safe_q[1], QE4_safe_q[2], QE4_safe_q[3], QE4_safe_q[4], QE4_safe_q[5]);

SE2_q_b[3]_PORT_A_address_reg = DFFE(SE2_q_b[3]_PORT_A_address, SE2_q_b[3]_clock_0, , , SE2_q_b[3]_clock_enable_0);

SE2_q_b[3]_PORT_B_address = BUS(QE3_safe_q[0], QE3_safe_q[1], QE3_safe_q[2], QE3_safe_q[3], QE3_safe_q[4], QE3_safe_q[5]);

SE2_q_b[3]_PORT_B_address_reg = DFFE(SE2_q_b[3]_PORT_B_address, SE2_q_b[3]_clock_1, , , SE2_q_b[3]_clock_enable_1);

SE2_q_b[3]_PORT_A_write_enable = VCC;

SE2_q_b[3]_PORT_A_write_enable_reg = DFFE(SE2_q_b[3]_PORT_A_write_enable, SE2_q_b[3]_clock_0, , , SE2_q_b[3]_clock_enable_0);

SE2_q_b[3]_PORT_B_read_enable = VCC;

SE2_q_b[3]_PORT_B_read_enable_reg = DFFE(SE2_q_b[3]_PORT_B_read_enable, SE2_q_b[3]_clock_1, , , SE2_q_b[3]_clock_enable_1);

SE2_q_b[3]_clock_0 = QC2__clk0;

SE2_q_b[3]_clock_1 = QC2__clk0;

SE2_q_b[3]_clock_enable_0 = BB1_wr_rfifo;

SE2_q_b[3]_clock_enable_1 = BB1L61;

SE2_q_b[3]_PORT_B_data_out = MEMORY(SE2_q_b[3]_PORT_A_data_in_reg, , SE2_q_b[3]_PORT_A_address_reg, SE2_q_b[3]_PORT_B_address_reg, SE2_q_b[3]_PORT_A_write_enable_reg, SE2_q_b[3]_PORT_B_read_enable_reg, , , SE2_q_b[3]_clock_0, SE2_q_b[3]_clock_1, SE2_q_b[3]_clock_enable_0, SE2_q_b[3]_clock_enable_1, , );

SE2_q_b[3] = SE2_q_b[3]_PORT_B_data_out[0];

--T1L276 is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|p1_registered_cpu_data_master_readdata~52

--operation mode is normal

T1L276 = SE2_q_b[3] & BB1_read_0 # !CB1L2 # !UB1L9;

--KB1_za_data[3] is std_1c20:inst|sdram:the_sdram|za_data[3]

--operation mode is normal

KB1_za_data[3]_lut_out = A1L265;

KB1_za_data[3] = DFFEAS(KB1_za_data[3]_lut_out, QC2__clk0, F1_data_out, , , , , , );

--Z1_counter_snapshot[3] is std_1c20:inst|high_res_timer:the_high_res_timer|counter_snapshot[3]

--operation mode is normal

Z1_counter_snapshot[3]_lut_out = !Z1_internal_counter[3];

Z1_counter_snapshot[3] = DFFEAS(Z1_counter_snapshot[3]_lut_out, QC2__clk0, F1_data_out, , Z1L208, , , , );

--Z1_period_h_register[3] is std_1c20:inst|high_res_timer:the_high_res_timer|period_h_register[3]

--operation mode is normal

Z1_period_h_register[3]_lut_out = S1_M_st_data[3];

Z1_period_h_register[3] = DFFEAS(Z1_period_h_register[3]_lut_out, QC2__clk0, F1_data_out, , Z1_period_h_wr_strobe, , , , );

--Z1L165 is std_1c20:inst|high_res_timer:the_high_res_timer|read_mux_out[3]~1251

--operation mode is normal

Z1L165 = XE1L15 & (Z1_period_h_register[3] # XE1L19 & Z1_counter_snapshot[3]) # !XE1L15 & XE1L19 & Z1_counter_snapshot[3];

--Z1_counter_snapshot[19] is std_1c20:inst|high_res_timer:the_high_res_timer|counter_snapshot[19]

--operation mode is normal

Z1_counter_snapshot[19]_lut_out = Z1_internal_counter[19];

Z1_counter_snapshot[19] = DFFEAS(Z1_counter_snapshot[19]_lut_out, QC2__clk0, F1_data_out, , Z1L208, , , , );

--Z1_control_register[3] is std_1c20:inst|high_res_timer:the_high_res_timer|control_register[3]

--operation mode is normal

Z1_control_register[3]_lut_out = S1_M_st_data[3];

Z1_control_register[3] = DFFEAS(Z1_control_register[3]_lut_out, QC2__clk0, F1_data_out, , Z1_control_wr_strobe, , , , );

--Z1L166 is std_1c20:inst|high_res_timer:the_high_res_timer|read_mux_out[3]~1252

--operation mode is normal

Z1L166 = XE1L17 & (S1_M_alu_result[4] & Z1_counter_snapshot[19] # !S1_M_alu_result[4] & (Z1_control_register[3]));

--Z1_period_l_register[3] is std_1c20:inst|high_res_timer:the_high_res_timer|period_l_register[3]

--operation mode is normal

Z1_period_l_register[3]_lut_out = !S1_M_st_data[3];

Z1_period_l_register[3] = DFFEAS(Z1_period_l_register[3]_lut_out, QC2__clk0, F1_data_out, , Z1_period_l_wr_strobe, , , , );

--DE1_iROE_reg is std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|iROE_reg

--operation mode is normal

DE1_iROE_reg_lut_out = S1_M_st_data[3];

DE1_iROE_reg = DFFEAS(DE1_iROE_reg_lut_out, QC2__clk0, F1_data_out, , DE1_control_wr_strobe, , , , );

--DE1_endofpacketvalue_reg[3] is std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|endofpacketvalue_reg[3]

--operation mode is normal

DE1_endofpacketvalue_reg[3]_lut_out = S1_M_st_data[3];

DE1_endofpacketvalue_reg[3] = DFFEAS(DE1_endofpacketvalue_reg[3]_lut_out, QC2__clk0, F1_data_out, , DE1_endofpacketvalue_wr_strobe, , , , );

--DE1_epcs_slave_select_reg[3] is std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|epcs_slave_select_reg[3]

--operation mode is normal

DE1_epcs_slave_select_reg[3]_lut_out = DE1_epcs_slave_select_holding_reg[3];

DE1_epcs_slave_select_reg[3] = DFFEAS(DE1_epcs_slave_select_reg[3]_lut_out, QC2__clk0, F1_data_out, , DE1L142, , , , );

--DE1L1 is std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|A_WE_StdLogicVector~1116

--operation mode is normal

DE1L1 = X1L14 & X1L16 & DE1_epcs_slave_select_reg[3] & !X1L15;

--DE1_rx_holding_reg[3] is std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|rx_holding_reg[3]

--operation mode is normal

DE1_rx_holding_reg[3]_lut_out = DE1_shift_reg[3];

DE1_rx_holding_reg[3] = DFFEAS(DE1_rx_holding_reg[3]_lut_out, QC2__clk0, F1_data_out, , DE1L156, , , , );

--DE1L2 is std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|A_WE_StdLogicVector~1117

--operation mode is normal

DE1L2 = DE1_rx_holding_reg[3] & (X1L15 # !X1L16 # !X1L14);

--DE1L3 is std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|A_WE_StdLogicVector~1118

--operation mode is normal

DE1L3 = DE1L114 & DE1_endofpacketvalue_reg[3] # !DE1L114 & (DE1L1 # DE1L2);

--DE1_ROE is std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|ROE

--operation mode is normal

DE1_ROE_lut_out = DE1_RRDY & (DE1L156 # DE1_ROE & !DE1_status_wr_strobe) # !DE1_RRDY & (DE1_ROE & !DE1_status_wr_strobe);

DE1_ROE = DFFEAS(DE1_ROE_lut_out, QC2__clk0, F1_data_out, , , , , , );

--DE1L115 is std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|Equal0~142

--operation mode is normal

DE1L115 = X1L14 & X1L15 & (!X1L16);

--DE1L116 is std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|Equal0~143

--operation mode is normal

DE1L116 = X1L15 & (!X1L14 & !X1L16);

--KB1_za_data[19] is std_1c20:inst|sdram:the_sdram|za_data[19]

--operation mode is normal

KB1_za_data[19]_lut_out = A1L249;

KB1_za_data[19] = DFFEAS(KB1_za_data[19]_lut_out, QC2__clk0, F1_data_out, , , , , , );

--T1L260 is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|p1_registered_cpu_data_master_readdata[19]~2033

--operation mode is normal

T1L260 = S1_M_alu_result[25] # KB1_za_data[19] # !QB1L1 # !S1_M_alu_result[24];

--RE2_safe_q[3] is std_1c20:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_r:the_jtag_uart_scfifo_r|scfifo:rfifo|scfifo_jf21:auto_generated|a_dpfifo_ml21:dpfifo|a_fefifo_7cf:fifo_state|cntr_9c7:count_usedw|safe_q[3]

--operation mode is arithmetic

RE2_safe_q[3]_carry_eqn = RE2L6;

RE2_safe_q[3]_lut_out = RE2_safe_q[3] $ (RE2_safe_q[3]_carry_eqn);

RE2_safe_q[3] = DFFEAS(RE2_safe_q[3]_lut_out, QC2__clk0, F1_data_out, , NE2L1, , , , );

--RE2L8 is std_1c20:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_r:the_jtag_uart_scfifo_r|scfifo:rfifo|scfifo_jf21:auto_generated|a_dpfifo_ml21:dpfifo|a_fefifo_7cf:fifo_state|cntr_9c7:count_usedw|counter_cella3~COUT

--operation mode is arithmetic

RE2L8 = CARRY(RE2_safe_q[3] $ BB1_wr_rfifo # !RE2L6);

--BB1L19 is std_1c20:inst|jtag_uart:the_jtag_uart|Add1~293

--operation mode is arithmetic

BB1L19_carry_eqn = BB1L17;

BB1L19 = RE1_safe_q[3] $ (!BB1L19_carry_eqn);

--BB1L20 is std_1c20:inst|jtag_uart:the_jtag_uart|Add1~294

--operation mode is arithmetic

BB1L20 = CARRY(RE1_safe_q[3] # !BB1L17);

--BB1L21 is std_1c20:inst|jtag_uart:the_jtag_uart|Add1~295

--operation mode is normal

BB1L21 = BB1_read_0 & RE2_safe_q[3] # !BB1_read_0 & (BB1L19);

--S1_i_readdata_d1[9] is std_1c20:inst|cpu:the_cpu|i_readdata_d1[9]

--operation mode is normal

S1_i_readdata_d1[9] = AMPP_FUNCTION(QC2__clk0, U1L36, WC1L19, WC1L10, V1_cpu_instruction_master_qualified_request_cpu_jtag_debug_module, F1_data_out);

--S1_E_src1_prelim[31] is std_1c20:inst|cpu:the_cpu|E_src1_prelim[31]

--operation mode is normal

S1_E_src1_prelim[31] = AMPP_FUNCTION(QC2__clk0, CD1_q_b[31], S1_W_wr_data[31], S1L1375, S1_D_src1_hazard_W, F1_data_out, S1_D_src1_hazard_M, S1_W_stall);

--S1L1373 is std_1c20:inst|cpu:the_cpu|M_wr_data_unfiltered[31]~3699

--operation mode is normal

S1L1373 = AMPP_FUNCTION(S1_M_shift_rot_result[31], S1_M_ctrl_shift_rot);

--S1_av_ld_data_aligned_or_div[31] is std_1c20:inst|cpu:the_cpu|av_ld_data_aligned_or_div[31]

--operation mode is normal

S1_av_ld_data_aligned_or_div[31] = AMPP_FUNCTION(QC2__clk0, S1_d_readdata_d1[31], S1_M_ctrl_ld_signed, S1L174, S1_M_iw[4], F1_data_out);

--S1_M_alu_result[31] is std_1c20:inst|cpu:the_cpu|M_alu_result[31]

--operation mode is normal

S1_M_alu_result[31] = AMPP_FUNCTION(QC2__clk0, S1L78, S1L539, A1L276, S1_E_ctrl_dst_data_sel_logic_result, F1_data_out, S1_E_ctrl_dst_data_sel_cmp, S1_E_ctrl_rdctl_inst, S1_W_stall);

--S1L1374 is std_1c20:inst|cpu:the_cpu|M_wr_data_unfiltered[31]~3700

--operation mode is normal

S1L1374 = AMPP_FUNCTION(S1_av_ld_data_aligned_or_div[31], S1_M_alu_result[31], S1_av_ld_or_div_done, S1_M_ctrl_shift_rot);

--S1L600 is std_1c20:inst|cpu:the_cpu|E_src1[31]~2042

--operation mode is normal

S1L600 = AMPP_FUNCTION(S1_E_src1_prelim[31], S1_E_src1_hazard_M, S1L1373, S1L1374);

--S1_E_src2_imm[31] is std_1c20:inst|cpu:the_cpu|E_src2_imm[31]

--operation mode is normal

S1_E_src2_imm[31] = AMPP_FUNCTION(QC2__clk0, S1_D_iw[21], S1L238, F1_data_out, S1_W_stall);

--S1_E_src2_prelim[31] is std_1c20:inst|cpu:the_cpu|E_src2_prelim[31]

--operation mode is normal

S1_E_src2_prelim[31] = AMPP_FUNCTION(QC2__clk0, DD1_q_b[31], S1_W_wr_data[31], S1L1375, S1L396, F1_data_out, S1L392, S1_W_stall);

--S1L741 is std_1c20:inst|cpu:the_cpu|E_src2_reg[31]~474

--operation mode is normal

S1L741 = AMPP_FUNCTION(S1_E_src2_prelim[31], S1_E_src2_hazard_M, S1L1373, S1L1374);

--S1L666 is std_1c20:inst|cpu:the_cpu|E_src2[31]~1529

--operation mode is normal

S1L666 = AMPP_FUNCTION(S1_E_src2_imm[31], S1L741, S1_E_ctrl_src2_is_imm);

--XC1L5 is std_1c20:inst|cpu:the_cpu|cpu_test_bench:the_cpu_test_bench|Add0~563

--operation mode is arithmetic

XC1L5 = AMPP_FUNCTION(S1L599, S1L665, XC1L7);

--S1_E_ctrl_alu_signed_cmp is std_1c20:inst|cpu:the_cpu|E_ctrl_alu_signed_cmp

--operation mode is normal

S1_E_ctrl_alu_signed_cmp = AMPP_FUNCTION(QC2__clk0, S1L205, S1L203, S1L204, S1_D_iw[5], F1_data_out, S1_W_stall);

--S1L414 is std_1c20:inst|cpu:the_cpu|E_arith_src2~0

--operation mode is normal

S1L414 = AMPP_FUNCTION(S1_E_ctrl_src2_is_imm, S1L741, S1_E_src2_imm[31], S1_E_ctrl_alu_signed_cmp);

--S1L413 is std_1c20:inst|cpu:the_cpu|E_arith_src1~0

--operation mode is normal

S1L413 = AMPP_FUNCTION(S1L600, S1_E_ctrl_alu_signed_cmp);

--YC1_result[30] is std_1c20:inst|cpu:the_cpu|lpm_add_sub:Add8|alt_stratix_add_sub:stratix_adder|result[30]

--operation mode is arithmetic

YC1_result[30] = AMPP_FUNCTION(S1L665, S1L599, YC1L61, S1_E_ctrl_alu_subtract);

--YC1L63 is std_1c20:inst|cpu:the_cpu|lpm_add_sub:Add8|alt_stratix_add_sub:stratix_adder|add_sub_cell[30]~COUT

--operation mode is arithmetic

YC1L63 = AMPP_FUNCTION(S1L665, S1L599, YC1L61, S1_E_ctrl_alu_subtract);

--SD1_sr[19] is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|sr[19]

--operation mode is normal

SD1_sr[19] = AMPP_FUNCTION(A1L5, SD1_sr[20], SD1L70, SD1L23, SD1L24, !C1_CLR_SIGNAL, SD1L12);

--SD1_sr[18] is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|sr[18]

--operation mode is normal

SD1_sr[18] = AMPP_FUNCTION(A1L5, SD1L26, SD1_sr[19], SD1L9, SD1L27, !C1_CLR_SIGNAL, SD1L12);

--GD1_break_readreg[20] is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_break:the_cpu_nios2_oci_break|break_readreg[20]

--operation mode is normal

GD1_break_readreg[20] = AMPP_FUNCTION(QC2__clk0, SD1_internal_jdo1[20], SD1_internal_jdo1[36], SD1_internal_jdo1[37], SD1L189, !C1_CLR_SIGNAL, SD1L189);

--SD1L7 is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|DRsize[0]~19972

--operation mode is normal

SD1L7 = AMPP_FUNCTION(GD1_break_readreg[20], RD1_internal_MonDReg[20], SD1_ir[1]);

--SD1L8 is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|DRsize[0]~19973

--operation mode is normal

SD1L8 = AMPP_FUNCTION(SD1L145, SD1L143, SD1L7, SD1_ir[0]);

--SD1L9 is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|DRsize[0]~19974

--operation mode is normal

SD1L9 = AMPP_FUNCTION(SD1_ir[0], SD1_ir[1], A1L4, SD1L145);

--SD1L10 is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|DRsize[0]~19975

--operation mode is normal

SD1L10 = AMPP_FUNCTION(SD1L7, A1L4, SD1L145, SD1_ir[0]);

--SD1L11 is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|DRsize[0]~19977

--operation mode is normal

SD1L11 = AMPP_FUNCTION(SD1_ir[0], SD1_ir[1]);

--SD1L12 is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|DRsize[0]~19978

--operation mode is normal

SD1L12 = AMPP_FUNCTION(SD1L144, SD1L142, SD1L11, SD1_st_updateir);

--C1L33 is sld_hub:sld_hub_inst|jtag_debug_mode~171

--operation mode is normal

C1L33 = AMPP_FUNCTION(FF1_state[12], A1L7, FF1_state[2]);

--FF1_state[15] is sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state[15]

--operation mode is normal

FF1_state[15] = AMPP_FUNCTION(A1L5, FF1_state[12], FF1_state[14], VCC, !A1L7);

--GF1_dffe1a[1] is sld_hub:sld_hub_inst|lpm_decode:instruction_decoder|decode_ogi:auto_generated|dffe1a[1]

--operation mode is normal

GF1_dffe1a[1] = AMPP_FUNCTION(A1L5, BF3_Q[1], C1L32, BF3_Q[3], BF3_Q[2], !C1_CLR_SIGNAL, C1L5);

--GF1_dffe1a[2] is sld_hub:sld_hub_inst|lpm_decode:instruction_decoder|decode_ogi:auto_generated|dffe1a[2]

--operation mode is normal

GF1_dffe1a[2] = AMPP_FUNCTION(A1L5, BF3_Q[2], C1L32, BF3_Q[1], BF3_Q[3], !C1_CLR_SIGNAL, C1L5);

--C1L1 is sld_hub:sld_hub_inst|BROADCAST_ENA~32

--operation mode is normal

C1L1 = AMPP_FUNCTION(FF1_state[8], C1_OK_TO_UPDATE_IR_Q, GF1_dffe1a[1], GF1_dffe1a[2]);

--GD1_break_readreg[19] is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_break:the_cpu_nios2_oci_break|break_readreg[19]

--operation mode is normal

GD1_break_readreg[19] = AMPP_FUNCTION(QC2__clk0, SD1_internal_jdo1[19], SD1_internal_jdo1[36], SD1_internal_jdo1[37], SD1L189, !C1_CLR_SIGNAL, SD1L189);

--SD1L13 is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|DRsize[0]~19979

--operation mode is normal

SD1L13 = AMPP_FUNCTION(GD1_break_readreg[19], RD1_internal_MonDReg[19], SD1_ir[1]);

--SD1L14 is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|DRsize[0]~19980

--operation mode is normal

SD1L14 = AMPP_FUNCTION(SD1L145, SD1L143, SD1L13, SD1_ir[0]);

--SD1L15 is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|DRsize[0]~19981

--operation mode is normal

SD1L15 = AMPP_FUNCTION(SD1L13, A1L4, SD1L145, SD1_ir[0]);

--GF1_dffe1a[7] is sld_hub:sld_hub_inst|lpm_decode:instruction_decoder|decode_ogi:auto_generated|dffe1a[7]

--operation mode is normal

GF1_dffe1a[7] = AMPP_FUNCTION(A1L5, BF3_Q[1], BF3_Q[3], BF3_Q[2], C1L32, !C1_CLR_SIGNAL, C1L5);

--C1L2 is sld_hub:sld_hub_inst|BROADCAST_ENA~33

--operation mode is normal

C1L2 = AMPP_FUNCTION(FF1_state[8], C1_OK_TO_UPDATE_IR_Q);

--JD1_internal_monitor_error is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_debug:the_cpu_nios2_oci_debug|internal_monitor_error

--operation mode is normal

JD1_internal_monitor_error = AMPP_FUNCTION(QC2__clk0, JD1L3, S1_M_st_data[1], FD1L14, SD1L191, VCC);

--SD1L16 is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|DRsize[0]~19983

--operation mode is normal

SD1L16 = AMPP_FUNCTION(JD1_internal_monitor_error, SD1_ir[0], SD1_ir[1]);

--SD1L17 is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|DRsize[0]~19984

--operation mode is normal

SD1L17 = AMPP_FUNCTION(A1L4, SD1_ir[0], SD1_ir[1], SD1L145);

--SD1_st_updatedr is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|st_updatedr

--operation mode is normal

SD1_st_updatedr = AMPP_FUNCTION(A1L5, SD1L145, VCC, A1L8);

--SD1L132 is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|Mux41~110

--operation mode is normal

SD1L132 = AMPP_FUNCTION(altera_internal_jtag, SD1_DRsize[2], SD1_DRsize[1], SD1_DRsize[0]);

--SD1_sr[36] is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|sr[36]

--operation mode is normal

SD1_sr[36] = AMPP_FUNCTION(A1L5, SD1_sr[37], SD1L28, A1L4, SD1L145, !C1_CLR_SIGNAL, SD1L30);

--SD1L133 is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|Mux41~111

--operation mode is normal

SD1L133 = AMPP_FUNCTION(SD1_sr[36], SD1_DRsize[1], SD1_DRsize[0], SD1_DRsize[2]);

--SD1L18 is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|DRsize[0]~19986

--operation mode is normal

SD1L18 = AMPP_FUNCTION(A1L4, SD1L145, SD1L132, SD1L133);

--SD1L134 is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|Mux41~112

--operation mode is normal

SD1L134 = AMPP_FUNCTION(SD1L132, SD1L133);

--SD1L19 is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|DRsize[0]~19987

--operation mode is normal

SD1L19 = AMPP_FUNCTION(SD1L134, SD1L144, S1_hbreak_enabled, SD1_ir[1]);

--BF7_Q[0] is sld_hub:sld_hub_inst|sld_dffex:\GEN_SHADOW_IRF:1:S_IRF|Q[0]

--operation mode is normal

BF7_Q[0] = AMPP_FUNCTION(A1L5, BF3_Q[0], !C1_CLR_SIGNAL, C1L8);

--C1L9 is sld_hub:sld_hub_inst|GEN_SHADOW_IRF~22

--operation mode is normal

C1L9 = AMPP_FUNCTION(FF1_state[5], C1_OK_TO_UPDATE_IR_Q);

--C1L25 is sld_hub:sld_hub_inst|IRF_ENABLE[1]~135

--operation mode is normal

C1L25 = AMPP_FUNCTION(BF9_Q[0], BF2_Q[0], GF1_dffe1a[2]);

--C1L26 is sld_hub:sld_hub_inst|IRF_ENABLE[1]~136

--operation mode is normal

C1L26 = AMPP_FUNCTION(C1L9, C1L25, BF8_Q[0], BF2_Q[0]);

--SD1L146 is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|process4~0

--operation mode is normal

SD1L146 = AMPP_FUNCTION(C1_jtag_debug_mode_usr1, BF8_Q[0], C1_jtag_debug_mode, BF2_Q[0]);

--BF7_Q[1] is sld_hub:sld_hub_inst|sld_dffex:\GEN_SHADOW_IRF:1:S_IRF|Q[1]

--operation mode is normal

BF7_Q[1] = AMPP_FUNCTION(A1L5, BF3_Q[1], !C1_CLR_SIGNAL, C1L8);

--KB1_za_data[22] is std_1c20:inst|sdram:the_sdram|za_data[22]

--operation mode is normal

KB1_za_data[22]_lut_out = A1L246;

KB1_za_data[22] = DFFEAS(KB1_za_data[22]_lut_out, QC2__clk0, F1_data_out, , , , , , );

--T1L263 is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|p1_registered_cpu_data_master_readdata[22]~2035

--operation mode is normal

T1L263 = S1_M_alu_result[25] # KB1_za_data[22] # !QB1L1 # !S1_M_alu_result[24];

--NE2_b_full is std_1c20:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_r:the_jtag_uart_scfifo_r|scfifo:rfifo|scfifo_jf21:auto_generated|a_dpfifo_ml21:dpfifo|a_fefifo_7cf:fifo_state|b_full

--operation mode is normal

NE2_b_full_lut_out = NE2_b_non_empty & !BB1L43 & (NE2_b_full # NE2L6) # !NE2_b_non_empty & NE2_b_full;

NE2_b_full = DFFEAS(NE2_b_full_lut_out, QC2__clk0, F1_data_out, , , , , , );

--BB1L22 is std_1c20:inst|jtag_uart:the_jtag_uart|Add1~296

--operation mode is arithmetic

BB1L22_carry_eqn = BB1L27;

BB1L22 = NE1_b_full $ (!BB1L22_carry_eqn);

--BB1L23 is std_1c20:inst|jtag_uart:the_jtag_uart|Add1~297

--operation mode is arithmetic

BB1L23 = CARRY(!BB1L27 # !NE1_b_full);

--BB1L24 is std_1c20:inst|jtag_uart:the_jtag_uart|Add1~298

--operation mode is normal

BB1L24 = BB1_read_0 & NE2_b_full # !BB1_read_0 & (BB1L22);

--DE1_endofpacketvalue_reg[15] is std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|endofpacketvalue_reg[15]

--operation mode is normal

DE1_endofpacketvalue_reg[15]_lut_out = S1_M_st_data[15];

DE1_endofpacketvalue_reg[15] = DFFEAS(DE1_endofpacketvalue_reg[15]_lut_out, QC2__clk0, F1_data_out, , DE1_endofpacketvalue_wr_strobe, , , , );

--DE1_epcs_slave_select_reg[15] is std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|epcs_slave_select_reg[15]

--operation mode is normal

DE1_epcs_slave_select_reg[15]_lut_out = DE1_epcs_slave_select_holding_reg[15];

DE1_epcs_slave_select_reg[15] = DFFEAS(DE1_epcs_slave_select_reg[15]_lut_out, QC2__clk0, F1_data_out, , DE1L142, , , , );

--Z1_counter_snapshot[15] is std_1c20:inst|high_res_timer:the_high_res_timer|counter_snapshot[15]

--operation mode is normal

Z1_counter_snapshot[15]_lut_out = !Z1_internal_counter[15];

Z1_counter_snapshot[15] = DFFEAS(Z1_counter_snapshot[15]_lut_out, QC2__clk0, F1_data_out, , Z1L208, , , , );

--Z1_counter_snapshot[31] is std_1c20:inst|high_res_timer:the_high_res_timer|counter_snapshot[31]

--operation mode is normal

Z1_counter_snapshot[31]_lut_out = Z1_internal_counter[31];

Z1_counter_snapshot[31] = DFFEAS(Z1_counter_snapshot[31]_lut_out, QC2__clk0, F1_data_out, , Z1L208, , , , );

--Z1L189 is std_1c20:inst|high_res_timer:the_high_res_timer|read_mux_out[15]~1253

--operation mode is normal

Z1L189 = S1_M_alu_result[2] & (Z1_counter_snapshot[31] # !S1_M_alu_result[4]) # !S1_M_alu_result[2] & S1_M_alu_result[4] & Z1_counter_snapshot[15];

--Z1_period_h_register[15] is std_1c20:inst|high_res_timer:the_high_res_timer|period_h_register[15]

--operation mode is normal

Z1_period_h_register[15]_lut_out = S1_M_st_data[15];

Z1_period_h_register[15] = DFFEAS(Z1_period_h_register[15]_lut_out, QC2__clk0, F1_data_out, , Z1_period_h_wr_strobe, , , , );

--Z1_period_l_register[15] is std_1c20:inst|high_res_timer:the_high_res_timer|period_l_register[15]

--operation mode is normal

Z1_period_l_register[15]_lut_out = !S1_M_st_data[15];

Z1_period_l_register[15] = DFFEAS(Z1_period_l_register[15]_lut_out, QC2__clk0, F1_data_out, , Z1_period_l_wr_strobe, , , , );

--Z1L190 is std_1c20:inst|high_res_timer:the_high_res_timer|read_mux_out[15]~1254

--operation mode is normal

Z1L190 = Z1L189 & Z1_period_h_register[15] # !Z1L189 & (Z1_period_l_register[15]);

--RB1_counter_snapshot[15] is std_1c20:inst|sys_clk_timer:the_sys_clk_timer|counter_snapshot[15]

--operation mode is normal

RB1_counter_snapshot[15]_lut_out = !RB1_internal_counter[15];

RB1_counter_snapshot[15] = DFFEAS(RB1_counter_snapshot[15]_lut_out, QC2__clk0, F1_data_out, , RB1L209, , , , );

--RB1_counter_snapshot[31] is std_1c20:inst|sys_clk_timer:the_sys_clk_timer|counter_snapshot[31]

--operation mode is normal

RB1_counter_snapshot[31]_lut_out = RB1_internal_counter[31];

RB1_counter_snapshot[31] = DFFEAS(RB1_counter_snapshot[31]_lut_out, QC2__clk0, F1_data_out, , RB1L209, , , , );

--RB1L190 is std_1c20:inst|sys_clk_timer:the_sys_clk_timer|read_mux_out[15]~1242

--operation mode is normal

RB1L190 = S1_M_alu_result[2] & (RB1_counter_snapshot[31] # !S1_M_alu_result[4]) # !S1_M_alu_result[2] & S1_M_alu_result[4] & RB1_counter_snapshot[15];

--RB1_period_h_register[15] is std_1c20:inst|sys_clk_timer:the_sys_clk_timer|period_h_register[15]

--operation mode is normal

RB1_period_h_register[15]_lut_out = S1_M_st_data[15];

RB1_period_h_register[15] = DFFEAS(RB1_period_h_register[15]_lut_out, QC2__clk0, F1_data_out, , RB1_period_h_wr_strobe, , , , );

--RB1_period_l_register[15] is std_1c20:inst|sys_clk_timer:the_sys_clk_timer|period_l_register[15]

--operation mode is normal

RB1_period_l_register[15]_lut_out = !S1_M_st_data[15];

RB1_period_l_register[15] = DFFEAS(RB1_period_l_register[15]_lut_out, QC2__clk0, F1_data_out, , RB1_period_l_wr_strobe, , , , );

--RB1L191 is std_1c20:inst|sys_clk_timer:the_sys_clk_timer|read_mux_out[15]~1243

--operation mode is normal

RB1L191 = RB1L190 & RB1_period_h_register[15] # !RB1L190 & (RB1_period_l_register[15]);

--T1L295 is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|process4~0

--operation mode is normal

T1L295 = T1_internal_cpu_data_master_dbs_address[0] & T1L293 & (!T1_internal_cpu_data_master_dbs_address[1]);

--M1_slave_readdata[15] is std_1c20:inst|clock_1:the_clock_1|slave_readdata[15]

--operation mode is normal

M1_slave_readdata[15]_lut_out = M1_slave_readdata_p1[15];

M1_slave_readdata[15] = DFFEAS(M1_slave_readdata[15]_lut_out, QC2__clk0, F1_data_out, , , , , , );

--J1_slave_readdata[15] is std_1c20:inst|clock_0:the_clock_0|slave_readdata[15]

--operation mode is normal

J1_slave_readdata[15]_lut_out = J1_slave_readdata_p1[15];

J1_slave_readdata[15] = DFFEAS(J1_slave_readdata[15]_lut_out, QC2__clk0, F1_data_out, , , , , , );

--T1L258 is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|p1_registered_cpu_data_master_readdata[15]~2037

--operation mode is normal

T1L258 = S1_M_alu_result[5] & M1_slave_readdata[15] # !S1_M_alu_result[5] & (J1_slave_readdata[15]) # !K1L6;

--BB1_rvalid is std_1c20:inst|jtag_uart:the_jtag_uart|rvalid

--operation mode is normal

BB1_rvalid_lut_out = BB1L43 & NE2_b_non_empty # !BB1L43 & (BB1_rvalid);

BB1_rvalid = DFFEAS(BB1_rvalid_lut_out, QC2__clk0, F1_data_out, , , , , , );

--T1L286 is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|p1_registered_cpu_data_master_readdata~64

--operation mode is normal

T1L286 = BB1_rvalid # !CB1L2 # !UB1L9;

--KB1_za_data[15] is std_1c20:inst|sdram:the_sdram|za_data[15]

--operation mode is normal

KB1_za_data[15]_lut_out = A1L253;

KB1_za_data[15] = DFFEAS(KB1_za_data[15]_lut_out, QC2__clk0, F1_data_out, , , , , , );

--V1L28 is std_1c20:inst|cpu_jtag_debug_module_arbitrator:the_cpu_jtag_debug_module|cpu_jtag_debug_module_byteenable[1]~6

--operation mode is normal

V1L28 = S1_M_mem_byte_en[1] # !V1L4;

--RD1_internal_MonDReg[8] is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|internal_MonDReg[8]

--operation mode is normal

RD1_internal_MonDReg[8] = AMPP_FUNCTION(QC2__clk0, SD1_internal_jdo1[11], CE1_q_b[8], RD1L30, RD1_MonAReg[10], !C1_CLR_SIGNAL, RD1L29);

--RD1_internal_MonDReg[9] is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|internal_MonDReg[9]

--operation mode is normal

RD1_internal_MonDReg[9] = AMPP_FUNCTION(QC2__clk0, CE1_q_b[9], RD1L19, SD1_internal_jdo1[12], RD1_MonAReg[10], !C1_CLR_SIGNAL, RD1L30, RD1L29);

--RD1_internal_MonDReg[10] is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|internal_MonDReg[10]

--operation mode is normal

RD1_internal_MonDReg[10] = AMPP_FUNCTION(QC2__clk0, SD1_internal_jdo1[13], CE1_q_b[10], RD1L30, RD1_MonAReg[10], !C1_CLR_SIGNAL, RD1L29);

--RD1_internal_MonDReg[11] is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|internal_MonDReg[11]

--operation mode is normal

RD1_internal_MonDReg[11] = AMPP_FUNCTION(QC2__clk0, CE1_q_b[11], RD1L19, SD1_internal_jdo1[14], RD1_MonAReg[10], !C1_CLR_SIGNAL, RD1L30, RD1L29);

--RD1_internal_MonDReg[12] is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|internal_MonDReg[12]

--operation mode is normal

RD1_internal_MonDReg[12] = AMPP_FUNCTION(QC2__clk0, CE1_q_b[12], RD1L19, SD1_internal_jdo1[15], RD1_MonAReg[10], !C1_CLR_SIGNAL, RD1L30, RD1L29);

--RD1_internal_MonDReg[13] is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|internal_MonDReg[13]

--operation mode is normal

RD1_internal_MonDReg[13] = AMPP_FUNCTION(QC2__clk0, SD1_internal_jdo1[16], CE1_q_b[13], RD1L30, RD1_MonAReg[10], !C1_CLR_SIGNAL, RD1L29);

--RD1_internal_MonDReg[14] is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|internal_MonDReg[14]

--operation mode is normal

RD1_internal_MonDReg[14] = AMPP_FUNCTION(QC2__clk0, SD1_internal_jdo1[17], CE1_q_b[14], RD1L30, RD1_MonAReg[10], !C1_CLR_SIGNAL, RD1L29);

--RD1_internal_MonDReg[15] is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|internal_MonDReg[15]

--operation mode is normal

RD1_internal_MonDReg[15] = AMPP_FUNCTION(QC2__clk0, SD1_internal_jdo1[18], CE1_q_b[15], RD1L30, RD1_MonAReg[10], !C1_CLR_SIGNAL, RD1L29);

--BB1L25 is std_1c20:inst|jtag_uart:the_jtag_uart|Add1~299

--operation mode is normal

BB1L25_carry_eqn = BB1L23;

BB1L25 = !BB1L25_carry_eqn;

--T1L264 is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|p1_registered_cpu_data_master_readdata[23]~2039

--operation mode is normal

T1L264 = BB1L25 & !BB1_read_0 # !CB1L2 # !UB1L9;

--KB1_za_data[23] is std_1c20:inst|sdram:the_sdram|za_data[23]

--operation mode is normal

KB1_za_data[23]_lut_out = A1L245;

KB1_za_data[23] = DFFEAS(KB1_za_data[23]_lut_out, QC2__clk0, F1_data_out, , , , , , );

--RB1_counter_snapshot[7] is std_1c20:inst|sys_clk_timer:the_sys_clk_timer|counter_snapshot[7]

--operation mode is normal

RB1_counter_snapshot[7]_lut_out = RB1_internal_counter[7];

RB1_counter_snapshot[7] = DFFEAS(RB1_counter_snapshot[7]_lut_out, QC2__clk0, F1_data_out, , RB1L209, , , , );

--RB1_counter_snapshot[23] is std_1c20:inst|sys_clk_timer:the_sys_clk_timer|counter_snapshot[23]

--operation mode is normal

RB1_counter_snapshot[23]_lut_out = RB1_internal_counter[23];

RB1_counter_snapshot[23] = DFFEAS(RB1_counter_snapshot[23]_lut_out, QC2__clk0, F1_data_out, , RB1L209, , , , );

--RB1L174 is std_1c20:inst|sys_clk_timer:the_sys_clk_timer|read_mux_out[7]~1245

--operation mode is normal

RB1L174 = S1_M_alu_result[2] & (RB1_counter_snapshot[23] # !S1_M_alu_result[4]) # !S1_M_alu_result[2] & S1_M_alu_result[4] & RB1_counter_snapshot[7];

--RB1_period_h_register[7] is std_1c20:inst|sys_clk_timer:the_sys_clk_timer|period_h_register[7]

--operation mode is normal

RB1_period_h_register[7]_lut_out = S1_M_st_data[7];

RB1_period_h_register[7] = DFFEAS(RB1_period_h_register[7]_lut_out, QC2__clk0, F1_data_out, , RB1_period_h_wr_strobe, , , , );

--RB1_period_l_register[7] is std_1c20:inst|sys_clk_timer:the_sys_clk_timer|period_l_register[7]

--operation mode is normal

RB1_period_l_register[7]_lut_out = S1_M_st_data[7];

RB1_period_l_register[7] = DFFEAS(RB1_period_l_register[7]_lut_out, QC2__clk0, F1_data_out, , RB1_period_l_wr_strobe, , , , );

--RB1L175 is std_1c20:inst|sys_clk_timer:the_sys_clk_timer|read_mux_out[7]~1246

--operation mode is normal

RB1L175 = RB1L174 & RB1_period_h_register[7] # !RB1L174 & (!RB1_period_l_register[7]);

--Z1_counter_snapshot[7] is std_1c20:inst|high_res_timer:the_high_res_timer|counter_snapshot[7]

--operation mode is normal

Z1_counter_snapshot[7]_lut_out = Z1_internal_counter[7];

Z1_counter_snapshot[7] = DFFEAS(Z1_counter_snapshot[7]_lut_out, QC2__clk0, F1_data_out, , Z1L208, , , , );

--Z1_counter_snapshot[23] is std_1c20:inst|high_res_timer:the_high_res_timer|counter_snapshot[23]

--operation mode is normal

Z1_counter_snapshot[23]_lut_out = Z1_internal_counter[23];

Z1_counter_snapshot[23] = DFFEAS(Z1_counter_snapshot[23]_lut_out, QC2__clk0, F1_data_out, , Z1L208, , , , );

--Z1L173 is std_1c20:inst|high_res_timer:the_high_res_timer|read_mux_out[7]~1256

--operation mode is normal

Z1L173 = S1_M_alu_result[2] & (Z1_counter_snapshot[23] # !S1_M_alu_result[4]) # !S1_M_alu_result[2] & S1_M_alu_result[4] & Z1_counter_snapshot[7];

--Z1_period_h_register[7] is std_1c20:inst|high_res_timer:the_high_res_timer|period_h_register[7]

--operation mode is normal

Z1_period_h_register[7]_lut_out = S1_M_st_data[7];

Z1_period_h_register[7] = DFFEAS(Z1_period_h_register[7]_lut_out, QC2__clk0, F1_data_out, , Z1_period_h_wr_strobe, , , , );

--Z1_period_l_register[7] is std_1c20:inst|high_res_timer:the_high_res_timer|period_l_register[7]

--operation mode is normal

Z1_period_l_register[7]_lut_out = S1_M_st_data[7];

Z1_period_l_register[7] = DFFEAS(Z1_period_l_register[7]_lut_out, QC2__clk0, F1_data_out, , Z1_period_l_wr_strobe, , , , );

--Z1L174 is std_1c20:inst|high_res_timer:the_high_res_timer|read_mux_out[7]~1257

--operation mode is normal

Z1L174 = Z1L173 & Z1_period_h_register[7] # !Z1L173 & (!Z1_period_l_register[7]);

--XE1_control_reg[7] is std_1c20:inst|uart1:the_uart1|uart1_regs:the_uart1_regs|control_reg[7]

--operation mode is normal

XE1_control_reg[7]_lut_out = S1_M_st_data[7];

XE1_control_reg[7] = DFFEAS(XE1_control_reg[7]_lut_out, QC2__clk0, F1_data_out, , XE1L14, , , , );

--XE1L62 is std_1c20:inst|uart1:the_uart1|uart1_regs:the_uart1_regs|selected_read_data[7]~683

--operation mode is normal

XE1L62 = S1_M_alu_result[3] & (XE1_control_reg[7]) # !S1_M_alu_result[3] & XE1_internal_tx_data[7];

--YE1_internal_rx_char_ready is std_1c20:inst|uart1:the_uart1|uart1_rx:the_uart1_rx|internal_rx_char_ready

--operation mode is normal

YE1_internal_rx_char_ready_lut_out = YE1L43 & (!YE1L55 # !ZE1L34 # !ZE1L33);

YE1_internal_rx_char_ready = DFFEAS(YE1_internal_rx_char_ready_lut_out, QC2__clk0, F1_data_out, , , , , , );

--YE1_rx_data[7] is std_1c20:inst|uart1:the_uart1|uart1_rx:the_uart1_rx|rx_data[7]

--operation mode is normal

YE1_rx_data[7]_lut_out = YE1_unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[8];

YE1_rx_data[7] = DFFEAS(YE1_rx_data[7]_lut_out, QC2__clk0, F1_data_out, , YE1_got_new_char, , , , );

--XE1L63 is std_1c20:inst|uart1:the_uart1|uart1_regs:the_uart1_regs|selected_read_data[7]~684

--operation mode is normal

XE1L63 = S1_M_alu_result[3] & YE1_internal_rx_char_ready # !S1_M_alu_result[3] & (YE1_rx_data[7]);

--M1_slave_readdata[7] is std_1c20:inst|clock_1:the_clock_1|slave_readdata[7]

--operation mode is normal

M1_slave_readdata[7]_lut_out = M1_slave_readdata_p1[7];

M1_slave_readdata[7] = DFFEAS(M1_slave_readdata[7]_lut_out, QC2__clk0, F1_data_out, , , , , , );

--J1_slave_readdata[7] is std_1c20:inst|clock_0:the_clock_0|slave_readdata[7]

--operation mode is normal

J1_slave_readdata[7]_lut_out = J1_slave_readdata_p1[7];

J1_slave_readdata[7] = DFFEAS(J1_slave_readdata[7]_lut_out, QC2__clk0, F1_data_out, , , , , , );

--T1L250 is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|p1_registered_cpu_data_master_readdata[7]~2041

--operation mode is normal

T1L250 = S1_M_alu_result[5] & M1_slave_readdata[7] # !S1_M_alu_result[5] & (J1_slave_readdata[7]) # !K1L6;

--SE2_q_b[7] is std_1c20:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_r:the_jtag_uart_scfifo_r|scfifo:rfifo|scfifo_jf21:auto_generated|a_dpfifo_ml21:dpfifo|dpram_j921:FIFOram|altsyncram_nll1:altsyncram1|q_b[7]

--RAM Block Operation Mode: Simple Dual-Port

--Port A Depth: 64, Port A Width: 1, Port B Depth: 64, Port B Width: 1

--Port A Logical Depth: 64, Port A Logical Width: 8, Port B Logical Depth: 64, Port B Logical Width: 8

--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered

SE2_q_b[7]_PORT_A_data_in = GE1_wdata[7];

SE2_q_b[7]_PORT_A_data_in_reg = DFFE(SE2_q_b[7]_PORT_A_data_in, SE2_q_b[7]_clock_0, , , SE2_q_b[7]_clock_enable_0);

SE2_q_b[7]_PORT_A_address = BUS(QE4_safe_q[0], QE4_safe_q[1], QE4_safe_q[2], QE4_safe_q[3], QE4_safe_q[4], QE4_safe_q[5]);

SE2_q_b[7]_PORT_A_address_reg = DFFE(SE2_q_b[7]_PORT_A_address, SE2_q_b[7]_clock_0, , , SE2_q_b[7]_clock_enable_0);

SE2_q_b[7]_PORT_B_address = BUS(QE3_safe_q[0], QE3_safe_q[1], QE3_safe_q[2], QE3_safe_q[3], QE3_safe_q[4], QE3_safe_q[5]);

SE2_q_b[7]_PORT_B_address_reg = DFFE(SE2_q_b[7]_PORT_B_address, SE2_q_b[7]_clock_1, , , SE2_q_b[7]_clock_enable_1);

SE2_q_b[7]_PORT_A_write_enable = VCC;

SE2_q_b[7]_PORT_A_write_enable_reg = DFFE(SE2_q_b[7]_PORT_A_write_enable, SE2_q_b[7]_clock_0, , , SE2_q_b[7]_clock_enable_0);

SE2_q_b[7]_PORT_B_read_enable = VCC;

SE2_q_b[7]_PORT_B_read_enable_reg = DFFE(SE2_q_b[7]_PORT_B_read_enable, SE2_q_b[7]_clock_1, , , SE2_q_b[7]_clock_enable_1);

SE2_q_b[7]_clock_0 = QC2__clk0;

SE2_q_b[7]_clock_1 = QC2__clk0;

SE2_q_b[7]_clock_enable_0 = BB1_wr_rfifo;

SE2_q_b[7]_clock_enable_1 = BB1L61;

SE2_q_b[7]_PORT_B_data_out = MEMORY(SE2_q_b[7]_PORT_A_data_in_reg, , SE2_q_b[7]_PORT_A_address_reg, SE2_q_b[7]_PORT_B_address_reg, SE2_q_b[7]_PORT_A_write_enable_reg, SE2_q_b[7]_PORT_B_read_enable_reg, , , SE2_q_b[7]_clock_0, SE2_q_b[7]_clock_1, SE2_q_b[7]_clock_enable_0, SE2_q_b[7]_clock_enable_1, , );

SE2_q_b[7] = SE2_q_b[7]_PORT_B_data_out[0];

--T1L280 is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|p1_registered_cpu_data_master_readdata~56

--operation mode is normal

T1L280 = SE2_q_b[7] & BB1_read_0 # !CB1L2 # !UB1L9;

--KB1_za_data[7] is std_1c20:inst|sdram:the_sdram|za_data[7]

--operation mode is normal

KB1_za_data[7]_lut_out = A1L261;

KB1_za_data[7] = DFFEAS(KB1_za_data[7]_lut_out, QC2__clk0, F1_data_out, , , , , , );

--DE1_iRRDY_reg is std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|iRRDY_reg

--operation mode is normal

DE1_iRRDY_reg_lut_out = S1_M_st_data[7];

DE1_iRRDY_reg = DFFEAS(DE1_iRRDY_reg_lut_out, QC2__clk0, F1_data_out, , DE1_control_wr_strobe, , , , );

--DE1_endofpacketvalue_reg[7] is std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|endofpacketvalue_reg[7]

--operation mode is normal

DE1_endofpacketvalue_reg[7]_lut_out = S1_M_st_data[7];

DE1_endofpacketvalue_reg[7] = DFFEAS(DE1_endofpacketvalue_reg[7]_lut_out, QC2__clk0, F1_data_out, , DE1_endofpacketvalue_wr_strobe, , , , );

--DE1_epcs_slave_select_reg[7] is std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|epcs_slave_select_reg[7]

--operation mode is normal

DE1_epcs_slave_select_reg[7]_lut_out = DE1_epcs_slave_select_holding_reg[7];

DE1_epcs_slave_select_reg[7] = DFFEAS(DE1_epcs_slave_select_reg[7]_lut_out, QC2__clk0, F1_data_out, , DE1L142, , , , );

--DE1L4 is std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|A_WE_StdLogicVector~1120

--operation mode is normal

DE1L4 = X1L14 & X1L16 & DE1_epcs_slave_select_reg[7] & !X1L15;

--DE1_rx_holding_reg[7] is std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|rx_holding_reg[7]

--operation mode is normal

DE1_rx_holding_reg[7]_lut_out = DE1_shift_reg[7];

DE1_rx_holding_reg[7] = DFFEAS(DE1_rx_holding_reg[7]_lut_out, QC2__clk0, F1_data_out, , DE1L156, , , , );

--DE1L5 is std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|A_WE_StdLogicVector~1121

--operation mode is normal

DE1L5 = DE1_rx_holding_reg[7] & (X1L15 # !X1L16 # !X1L14);

--DE1L6 is std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|A_WE_StdLogicVector~1122

--operation mode is normal

DE1L6 = DE1L114 & DE1_endofpacketvalue_reg[7] # !DE1L114 & (DE1L4 # DE1L5);

--DE1_RRDY is std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|RRDY

--operation mode is normal

DE1_RRDY_lut_out = DE1L156 # DE1_RRDY & !DE1_status_wr_strobe & !DE1_data_rd_strobe;

DE1_RRDY = DFFEAS(DE1_RRDY_lut_out, QC2__clk0, F1_data_out, , , , , , );

--KB1_za_data[31] is std_1c20:inst|sdram:the_sdram|za_data[31]

--operation mode is normal

KB1_za_data[31]_lut_out = A1L237;

KB1_za_data[31] = DFFEAS(KB1_za_data[31]_lut_out, QC2__clk0, F1_data_out, , , , , , );

--T1L272 is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|p1_registered_cpu_data_master_readdata[31]~2043

--operation mode is normal

T1L272 = S1_M_alu_result[25] # KB1_za_data[31] # !QB1L1 # !S1_M_alu_result[24];

--V1L30 is std_1c20:inst|cpu_jtag_debug_module_arbitrator:the_cpu_jtag_debug_module|cpu_jtag_debug_module_byteenable[3]~7

--operation mode is normal

V1L30 = S1_M_mem_byte_en[3] # !V1L4;

--RD1_internal_MonDReg[24] is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|internal_MonDReg[24]

--operation mode is normal

RD1_internal_MonDReg[24] = AMPP_FUNCTION(QC2__clk0, CE1_q_b[24], RD1L21, SD1_internal_jdo1[27], RD1_MonAReg[10], !C1_CLR_SIGNAL, RD1L30, RD1L29);

--RD1_internal_MonDReg[25] is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|internal_MonDReg[25]

--operation mode is normal

RD1_internal_MonDReg[25] = AMPP_FUNCTION(QC2__clk0, SD1_internal_jdo1[28], CE1_q_b[25], RD1L30, RD1_MonAReg[10], !C1_CLR_SIGNAL, RD1L29);

--RD1_internal_MonDReg[26] is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|internal_MonDReg[26]

--operation mode is normal

RD1_internal_MonDReg[26] = AMPP_FUNCTION(QC2__clk0, SD1_internal_jdo1[29], CE1_q_b[26], RD1L30, RD1_MonAReg[10], !C1_CLR_SIGNAL, RD1L29);

--RD1_internal_MonDReg[27] is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|internal_MonDReg[27]

--operation mode is normal

RD1_internal_MonDReg[27] = AMPP_FUNCTION(QC2__clk0, CE1_q_b[27], RD1L20, SD1_internal_jdo1[30], RD1_MonAReg[10], !C1_CLR_SIGNAL, RD1L30, RD1L29);

--RD1_internal_MonDReg[28] is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|internal_MonDReg[28]

--operation mode is normal

RD1_internal_MonDReg[28] = AMPP_FUNCTION(QC2__clk0, SD1_internal_jdo1[31], CE1_q_b[28], RD1L30, RD1_MonAReg[10], !C1_CLR_SIGNAL, RD1L29);

--RD1_internal_MonDReg[29] is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|internal_MonDReg[29]

--operation mode is normal

RD1_internal_MonDReg[29] = AMPP_FUNCTION(QC2__clk0, CE1_q_b[29], RD1L20, SD1_internal_jdo1[32], RD1_MonAReg[10], !C1_CLR_SIGNAL, RD1L30, RD1L29);

--RD1_internal_MonDReg[30] is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|internal_MonDReg[30]

--operation mode is normal

RD1_internal_MonDReg[30] = AMPP_FUNCTION(QC2__clk0, SD1_internal_jdo1[33], CE1_q_b[30], RD1L30, RD1_MonAReg[10], !C1_CLR_SIGNAL, RD1L29);

--RD1_internal_MonDReg[31] is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|internal_MonDReg[31]

--operation mode is normal

RD1_internal_MonDReg[31] = AMPP_FUNCTION(QC2__clk0, SD1_internal_jdo1[34], CE1_q_b[31], RD1L30, RD1_MonAReg[10], !C1_CLR_SIGNAL, RD1L29);

--KB1_za_data[21] is std_1c20:inst|sdram:the_sdram|za_data[21]

--operation mode is normal

KB1_za_data[21]_lut_out = A1L247;

KB1_za_data[21] = DFFEAS(KB1_za_data[21]_lut_out, QC2__clk0, F1_data_out, , , , , , );

--T1L262 is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|p1_registered_cpu_data_master_readdata[21]~2045

--operation mode is normal

T1L262 = S1_M_alu_result[25] # KB1_za_data[21] # !QB1L1 # !S1_M_alu_result[24];

--RE2_safe_q[5] is std_1c20:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_r:the_jtag_uart_scfifo_r|scfifo:rfifo|scfifo_jf21:auto_generated|a_dpfifo_ml21:dpfifo|a_fefifo_7cf:fifo_state|cntr_9c7:count_usedw|safe_q[5]

--operation mode is normal

RE2_safe_q[5]_carry_eqn = RE2L10;

RE2_safe_q[5]_lut_out = RE2_safe_q[5] $ (RE2_safe_q[5]_carry_eqn);

RE2_safe_q[5] = DFFEAS(RE2_safe_q[5]_lut_out, QC2__clk0, F1_data_out, , NE2L1, , , , );

--BB1L26 is std_1c20:inst|jtag_uart:the_jtag_uart|Add1~301

--operation mode is arithmetic

BB1L26_carry_eqn = BB1L36;

BB1L26 = RE1_safe_q[5] $ (!BB1L26_carry_eqn);

--BB1L27 is std_1c20:inst|jtag_uart:the_jtag_uart|Add1~302

--operation mode is arithmetic

BB1L27 = CARRY(RE1_safe_q[5] # !BB1L36);

--BB1L28 is std_1c20:inst|jtag_uart:the_jtag_uart|Add1~303

--operation mode is normal

BB1L28 = BB1_read_0 & RE2_safe_q[5] # !BB1_read_0 & (BB1L26);

--S1_i_readdata_d1[22] is std_1c20:inst|cpu:the_cpu|i_readdata_d1[22]

--operation mode is normal

S1_i_readdata_d1[22] = AMPP_FUNCTION(QC2__clk0, U1L73, WC1L19, WC1L24, V1_cpu_instruction_master_qualified_request_cpu_jtag_debug_module, F1_data_out);

--S1_i_readdata_d1[23] is std_1c20:inst|cpu:the_cpu|i_readdata_d1[23]

--operation mode is normal

S1_i_readdata_d1[23] = AMPP_FUNCTION(QC2__clk0, U1L76, WC1L19, WC1L25, V1_cpu_instruction_master_qualified_request_cpu_jtag_debug_module, F1_data_out);

--S1_i_readdata_d1[24] is std_1c20:inst|cpu:the_cpu|i_readdata_d1[24]

--operation mode is normal

S1_i_readdata_d1[24] = AMPP_FUNCTION(QC2__clk0, U1L79, WC1L19, WC1L26, V1_cpu_instruction_master_qualified_request_cpu_jtag_debug_module, F1_data_out);

--S1_i_readdata_d1[25] is std_1c20:inst|cpu:the_cpu|i_readdata_d1[25]

--operation mode is normal

S1_i_readdata_d1[25] = AMPP_FUNCTION(QC2__clk0, U1L82, WC1L19, WC1L27, V1_cpu_instruction_master_qualified_request_cpu_jtag_debug_module, F1_data_out);

--S1_i_readdata_d1[26] is std_1c20:inst|cpu:the_cpu|i_readdata_d1[26]

--operation mode is normal

S1_i_readdata_d1[26] = AMPP_FUNCTION(QC2__clk0, U1L85, WC1L19, WC1L28, V1_cpu_instruction_master_qualified_request_cpu_jtag_debug_module, F1_data_out);

--KB1_za_data[24] is std_1c20:inst|sdram:the_sdram|za_data[24]

--operation mode is normal

KB1_za_data[24]_lut_out = A1L244;

KB1_za_data[24] = DFFEAS(KB1_za_data[24]_lut_out, QC2__clk0, F1_data_out, , , , , , );

--T1L265 is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|p1_registered_cpu_data_master_readdata[24]~2047

--operation mode is normal

T1L265 = S1_M_alu_result[25] # KB1_za_data[24] # !QB1L1 # !S1_M_alu_result[24];

--RE2_safe_q[0] is std_1c20:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_r:the_jtag_uart_scfifo_r|scfifo:rfifo|scfifo_jf21:auto_generated|a_dpfifo_ml21:dpfifo|a_fefifo_7cf:fifo_state|cntr_9c7:count_usedw|safe_q[0]

--operation mode is arithmetic

RE2_safe_q[0]_lut_out = !RE2_safe_q[0];

RE2_safe_q[0] = DFFEAS(RE2_safe_q[0]_lut_out, QC2__clk0, F1_data_out, , NE2L1, , , , );

--RE2L2 is std_1c20:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_r:the_jtag_uart_scfifo_r|scfifo:rfifo|scfifo_jf21:auto_generated|a_dpfifo_ml21:dpfifo|a_fefifo_7cf:fifo_state|cntr_9c7:count_usedw|counter_cella0~COUT

--operation mode is arithmetic

RE2L2 = CARRY(RE2_safe_q[0] $ !BB1_wr_rfifo);

--RE1_safe_q[0] is std_1c20:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_w:the_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_jf21:auto_generated|a_dpfifo_ml21:dpfifo|a_fefifo_7cf:fifo_state|cntr_9c7:count_usedw|safe_q[0]

--operation mode is arithmetic

RE1_safe_q[0]_lut_out = !RE1_safe_q[0];

RE1_safe_q[0] = DFFEAS(RE1_safe_q[0]_lut_out, QC2__clk0, F1_data_out, , NE1L1, , , , );

--RE1L2 is std_1c20:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_w:the_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_jf21:auto_generated|a_dpfifo_ml21:dpfifo|a_fefifo_7cf:fifo_state|cntr_9c7:count_usedw|counter_cella0~COUT

--operation mode is arithmetic

RE1L2 = CARRY(RE1_safe_q[0] $ !BB1_fifo_wr);

--BB1L29 is std_1c20:inst|jtag_uart:the_jtag_uart|Add1~304

--operation mode is normal

BB1L29 = BB1_read_0 & RE2_safe_q[0] # !BB1_read_0 & (RE1_safe_q[0]);

--BB1L30 is std_1c20:inst|jtag_uart:the_jtag_uart|Add1~305

--operation mode is normal

BB1L30 = BB1L29 # !CB1L2 # !UB1L9;

--KB1_za_data[16] is std_1c20:inst|sdram:the_sdram|za_data[16]

--operation mode is normal

KB1_za_data[16]_lut_out = A1L252;

KB1_za_data[16] = DFFEAS(KB1_za_data[16]_lut_out, QC2__clk0, F1_data_out, , , , , , );

--S1_i_readdata_d1[20] is std_1c20:inst|cpu:the_cpu|i_readdata_d1[20]

--operation mode is normal

S1_i_readdata_d1[20] = AMPP_FUNCTION(QC2__clk0, U1L67, WC1L19, WC1L22, V1_cpu_instruction_master_qualified_request_cpu_jtag_debug_module, F1_data_out);

--M1_slave_readdata[14] is std_1c20:inst|clock_1:the_clock_1|slave_readdata[14]

--operation mode is normal

M1_slave_readdata[14]_lut_out = M1_slave_readdata_p1[14];

M1_slave_readdata[14] = DFFEAS(M1_slave_readdata[14]_lut_out, QC2__clk0, F1_data_out, , , , , , );

--J1_slave_readdata[14] is std_1c20:inst|clock_0:the_clock_0|slave_readdata[14]

--operation mode is normal

J1_slave_readdata[14]_lut_out = J1_slave_readdata_p1[14];

J1_slave_readdata[14] = DFFEAS(J1_slave_readdata[14]_lut_out, QC2__clk0, F1_data_out, , , , , , );

--T1L257 is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|p1_registered_cpu_data_master_readdata[14]~2050

--operation mode is normal

T1L257 = S1_M_alu_result[5] & M1_slave_readdata[14] # !S1_M_alu_result[5] & (J1_slave_readdata[14]) # !K1L6;

--BB1_woverflow is std_1c20:inst|jtag_uart:the_jtag_uart|woverflow

--operation mode is normal

BB1_woverflow_lut_out = BB1L56 & (S1_M_alu_result[2] & BB1_woverflow # !S1_M_alu_result[2] & (NE1_b_full)) # !BB1L56 & BB1_woverflow;

BB1_woverflow = DFFEAS(BB1_woverflow_lut_out, QC2__clk0, F1_data_out, , , , , , );

--T1L285 is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|p1_registered_cpu_data_master_readdata~63

--operation mode is normal

T1L285 = BB1_woverflow # !CB1L2 # !UB1L9;

--KB1_za_data[14] is std_1c20:inst|sdram:the_sdram|za_data[14]

--operation mode is normal

KB1_za_data[14]_lut_out = A1L254;

KB1_za_data[14] = DFFEAS(KB1_za_data[14]_lut_out, QC2__clk0, F1_data_out, , , , , , );

--RB1_counter_snapshot[14] is std_1c20:inst|sys_clk_timer:the_sys_clk_timer|counter_snapshot[14]

--operation mode is normal

RB1_counter_snapshot[14]_lut_out = RB1_internal_counter[14];

RB1_counter_snapshot[14] = DFFEAS(RB1_counter_snapshot[14]_lut_out, QC2__clk0, F1_data_out, , RB1L209, , , , );

--RB1_counter_snapshot[30] is std_1c20:inst|sys_clk_timer:the_sys_clk_timer|counter_snapshot[30]

--operation mode is normal

RB1_counter_snapshot[30]_lut_out = RB1_internal_counter[30];

RB1_counter_snapshot[30] = DFFEAS(RB1_counter_snapshot[30]_lut_out, QC2__clk0, F1_data_out, , RB1L209, , , , );

--RB1L188 is std_1c20:inst|sys_clk_timer:the_sys_clk_timer|read_mux_out[14]~1248

--operation mode is normal

RB1L188 = S1_M_alu_result[2] & (RB1_counter_snapshot[30] # !S1_M_alu_result[4]) # !S1_M_alu_result[2] & S1_M_alu_result[4] & RB1_counter_snapshot[14];

--RB1_period_h_register[14] is std_1c20:inst|sys_clk_timer:the_sys_clk_timer|period_h_register[14]

--operation mode is normal

RB1_period_h_register[14]_lut_out = S1_M_st_data[14];

RB1_period_h_register[14] = DFFEAS(RB1_period_h_register[14]_lut_out, QC2__clk0, F1_data_out, , RB1_period_h_wr_strobe, , , , );

--RB1_period_l_register[14] is std_1c20:inst|sys_clk_timer:the_sys_clk_timer|period_l_register[14]

--operation mode is normal

RB1_period_l_register[14]_lut_out = S1_M_st_data[14];

RB1_period_l_register[14] = DFFEAS(RB1_period_l_register[14]_lut_out, QC2__clk0, F1_data_out, , RB1_period_l_wr_strobe, , , , );

--RB1L189 is std_1c20:inst|sys_clk_timer:the_sys_clk_timer|read_mux_out[14]~1249

--operation mode is normal

RB1L189 = RB1L188 & RB1_period_h_register[14] # !RB1L188 & (!RB1_period_l_register[14]);

--Z1_counter_snapshot[14] is std_1c20:inst|high_res_timer:the_high_res_timer|counter_snapshot[14]

--operation mode is normal

Z1_counter_snapshot[14]_lut_out = !Z1_internal_counter[14];

Z1_counter_snapshot[14] = DFFEAS(Z1_counter_snapshot[14]_lut_out, QC2__clk0, F1_data_out, , Z1L208, , , , );

--Z1_counter_snapshot[30] is std_1c20:inst|high_res_timer:the_high_res_timer|counter_snapshot[30]

--operation mode is normal

Z1_counter_snapshot[30]_lut_out = Z1_internal_counter[30];

Z1_counter_snapshot[30] = DFFEAS(Z1_counter_snapshot[30]_lut_out, QC2__clk0, F1_data_out, , Z1L208, , , , );

--Z1L187 is std_1c20:inst|high_res_timer:the_high_res_timer|read_mux_out[14]~1259

--operation mode is normal

Z1L187 = S1_M_alu_result[2] & (Z1_counter_snapshot[30] # !S1_M_alu_result[4]) # !S1_M_alu_result[2] & S1_M_alu_result[4] & Z1_counter_snapshot[14];

--Z1_period_h_register[14] is std_1c20:inst|high_res_timer:the_high_res_timer|period_h_register[14]

--operation mode is normal

Z1_period_h_register[14]_lut_out = S1_M_st_data[14];

Z1_period_h_register[14] = DFFEAS(Z1_period_h_register[14]_lut_out, QC2__clk0, F1_data_out, , Z1_period_h_wr_strobe, , , , );

--Z1_period_l_register[14] is std_1c20:inst|high_res_timer:the_high_res_timer|period_l_register[14]

--operation mode is normal

Z1_period_l_register[14]_lut_out = !S1_M_st_data[14];

Z1_period_l_register[14] = DFFEAS(Z1_period_l_register[14]_lut_out, QC2__clk0, F1_data_out, , Z1_period_l_wr_strobe, , , , );

--Z1L188 is std_1c20:inst|high_res_timer:the_high_res_timer|read_mux_out[14]~1260

--operation mode is normal

Z1L188 = Z1L187 & Z1_period_h_register[14] # !Z1L187 & (Z1_period_l_register[14]);

--DE1_endofpacketvalue_reg[14] is std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|endofpacketvalue_reg[14]

--operation mode is normal

DE1_endofpacketvalue_reg[14]_lut_out = S1_M_st_data[14];

DE1_endofpacketvalue_reg[14] = DFFEAS(DE1_endofpacketvalue_reg[14]_lut_out, QC2__clk0, F1_data_out, , DE1_endofpacketvalue_wr_strobe, , , , );

--DE1_epcs_slave_select_reg[14] is std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|epcs_slave_select_reg[14]

--operation mode is normal

DE1_epcs_slave_select_reg[14]_lut_out = DE1_epcs_slave_select_holding_reg[14];

DE1_epcs_slave_select_reg[14] = DFFEAS(DE1_epcs_slave_select_reg[14]_lut_out, QC2__clk0, F1_data_out, , DE1L142, , , , );

--KB1_za_data[30] is std_1c20:inst|sdram:the_sdram|za_data[30]

--operation mode is normal

KB1_za_data[30]_lut_out = A1L238;

KB1_za_data[30] = DFFEAS(KB1_za_data[30]_lut_out, QC2__clk0, F1_data_out, , , , , , );

--T1L271 is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|p1_registered_cpu_data_master_readdata[30]~2052

--operation mode is normal

T1L271 = S1_M_alu_result[25] # KB1_za_data[30] # !QB1L1 # !S1_M_alu_result[24];

--S1_i_readdata_d1[19] is std_1c20:inst|cpu:the_cpu|i_readdata_d1[19]

--operation mode is normal

S1_i_readdata_d1[19] = AMPP_FUNCTION(QC2__clk0, U1L64, WC1L19, WC1L21, V1_cpu_instruction_master_qualified_request_cpu_jtag_debug_module, F1_data_out);

--M1_slave_readdata[13] is std_1c20:inst|clock_1:the_clock_1|slave_readdata[13]

--operation mode is normal

M1_slave_readdata[13]_lut_out = M1_slave_readdata_p1[13];

M1_slave_readdata[13] = DFFEAS(M1_slave_readdata[13]_lut_out, QC2__clk0, F1_data_out, , , , , , );

--J1_slave_readdata[13] is std_1c20:inst|clock_0:the_clock_0|slave_readdata[13]

--operation mode is normal

J1_slave_readdata[13]_lut_out = J1_slave_readdata_p1[13];

J1_slave_readdata[13] = DFFEAS(J1_slave_readdata[13]_lut_out, QC2__clk0, F1_data_out, , , , , , );

--T1L256 is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|p1_registered_cpu_data_master_readdata[13]~2054

--operation mode is normal

T1L256 = S1_M_alu_result[5] & M1_slave_readdata[13] # !S1_M_alu_result[5] & (J1_slave_readdata[13]) # !K1L6;

--NE1_b_full is std_1c20:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_w:the_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_jf21:auto_generated|a_dpfifo_ml21:dpfifo|a_fefifo_7cf:fifo_state|b_full

--operation mode is normal

NE1_b_full_lut_out = !BB1_rd_wfifo & (NE1_b_full # NE1L3 & NE1L4);

NE1_b_full = DFFEAS(NE1_b_full_lut_out, QC2__clk0, F1_data_out, , , , , , );

--T1L284 is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|p1_registered_cpu_data_master_readdata~62

--operation mode is normal

T1L284 = !NE1_b_full # !CB1L2 # !UB1L9;

--KB1_za_data[13] is std_1c20:inst|sdram:the_sdram|za_data[13]

--operation mode is normal

KB1_za_data[13]_lut_out = A1L255;

KB1_za_data[13] = DFFEAS(KB1_za_data[13]_lut_out, QC2__clk0, F1_data_out, , , , , , );

--Z1_counter_snapshot[13] is std_1c20:inst|high_res_timer:the_high_res_timer|counter_snapshot[13]

--operation mode is normal

Z1_counter_snapshot[13]_lut_out = Z1_internal_counter[13];

Z1_counter_snapshot[13] = DFFEAS(Z1_counter_snapshot[13]_lut_out, QC2__clk0, F1_data_out, , Z1L208, , , , );

--Z1_counter_snapshot[29] is std_1c20:inst|high_res_timer:the_high_res_timer|counter_snapshot[29]

--operation mode is normal

Z1_counter_snapshot[29]_lut_out = Z1_internal_counter[29];

Z1_counter_snapshot[29] = DFFEAS(Z1_counter_snapshot[29]_lut_out, QC2__clk0, F1_data_out, , Z1L208, , , , );

--Z1L185 is std_1c20:inst|high_res_timer:the_high_res_timer|read_mux_out[13]~1262

--operation mode is normal

Z1L185 = S1_M_alu_result[2] & (Z1_counter_snapshot[29] # !S1_M_alu_result[4]) # !S1_M_alu_result[2] & S1_M_alu_result[4] & Z1_counter_snapshot[13];

--Z1_period_h_register[13] is std_1c20:inst|high_res_timer:the_high_res_timer|period_h_register[13]

--operation mode is normal

Z1_period_h_register[13]_lut_out = S1_M_st_data[13];

Z1_period_h_register[13] = DFFEAS(Z1_period_h_register[13]_lut_out, QC2__clk0, F1_data_out, , Z1_period_h_wr_strobe, , , , );

--Z1_period_l_register[13] is std_1c20:inst|high_res_timer:the_high_res_timer|period_l_register[13]

--operation mode is normal

Z1_period_l_register[13]_lut_out = S1_M_st_data[13];

Z1_period_l_register[13] = DFFEAS(Z1_period_l_register[13]_lut_out, QC2__clk0, F1_data_out, , Z1_period_l_wr_strobe, , , , );

--Z1L186 is std_1c20:inst|high_res_timer:the_high_res_timer|read_mux_out[13]~1263

--operation mode is normal

Z1L186 = Z1L185 & Z1_period_h_register[13] # !Z1L185 & (!Z1_period_l_register[13]);

--RB1_counter_snapshot[13] is std_1c20:inst|sys_clk_timer:the_sys_clk_timer|counter_snapshot[13]

--operation mode is normal

RB1_counter_snapshot[13]_lut_out = !RB1_internal_counter[13];

RB1_counter_snapshot[13] = DFFEAS(RB1_counter_snapshot[13]_lut_out, QC2__clk0, F1_data_out, , RB1L209, , , , );

--RB1_counter_snapshot[29] is std_1c20:inst|sys_clk_timer:the_sys_clk_timer|counter_snapshot[29]

--operation mode is normal

RB1_counter_snapshot[29]_lut_out = RB1_internal_counter[29];

RB1_counter_snapshot[29] = DFFEAS(RB1_counter_snapshot[29]_lut_out, QC2__clk0, F1_data_out, , RB1L209, , , , );

--RB1L186 is std_1c20:inst|sys_clk_timer:the_sys_clk_timer|read_mux_out[13]~1251

--operation mode is normal

RB1L186 = S1_M_alu_result[2] & (RB1_counter_snapshot[29] # !S1_M_alu_result[4]) # !S1_M_alu_result[2] & S1_M_alu_result[4] & RB1_counter_snapshot[13];

--RB1_period_h_register[13] is std_1c20:inst|sys_clk_timer:the_sys_clk_timer|period_h_register[13]

--operation mode is normal

RB1_period_h_register[13]_lut_out = S1_M_st_data[13];

RB1_period_h_register[13] = DFFEAS(RB1_period_h_register[13]_lut_out, QC2__clk0, F1_data_out, , RB1_period_h_wr_strobe, , , , );

--RB1_period_l_register[13] is std_1c20:inst|sys_clk_timer:the_sys_clk_timer|period_l_register[13]

--operation mode is normal

RB1_period_l_register[13]_lut_out = !S1_M_st_data[13];

RB1_period_l_register[13] = DFFEAS(RB1_period_l_register[13]_lut_out, QC2__clk0, F1_data_out, , RB1_period_l_wr_strobe, , , , );

--RB1L187 is std_1c20:inst|sys_clk_timer:the_sys_clk_timer|read_mux_out[13]~1252

--operation mode is normal

RB1L187 = RB1L186 & RB1_period_h_register[13] # !RB1L186 & (RB1_period_l_register[13]);

--DE1_endofpacketvalue_reg[13] is std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|endofpacketvalue_reg[13]

--operation mode is normal

DE1_endofpacketvalue_reg[13]_lut_out = S1_M_st_data[13];

DE1_endofpacketvalue_reg[13] = DFFEAS(DE1_endofpacketvalue_reg[13]_lut_out, QC2__clk0, F1_data_out, , DE1_endofpacketvalue_wr_strobe, , , , );

--DE1_epcs_slave_select_reg[13] is std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|epcs_slave_select_reg[13]

--operation mode is normal

DE1_epcs_slave_select_reg[13]_lut_out = DE1_epcs_slave_select_holding_reg[13];

DE1_epcs_slave_select_reg[13] = DFFEAS(DE1_epcs_slave_select_reg[13]_lut_out, QC2__clk0, F1_data_out, , DE1L142, , , , );

--KB1_za_data[29] is std_1c20:inst|sdram:the_sdram|za_data[29]

--operation mode is normal

KB1_za_data[29]_lut_out = A1L239;

KB1_za_data[29] = DFFEAS(KB1_za_data[29]_lut_out, QC2__clk0, F1_data_out, , , , , , );

--T1L270 is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|p1_registered_cpu_data_master_readdata[29]~2056

--operation mode is normal

T1L270 = S1_M_alu_result[25] # KB1_za_data[29] # !QB1L1 # !S1_M_alu_result[24];

--S1_D_br_taken_waddr_partial[10] is std_1c20:inst|cpu:the_cpu|D_br_taken_waddr_partial[10]

--operation mode is normal

S1_D_br_taken_waddr_partial[10] = AMPP_FUNCTION(QC2__clk0, F1_data_out, S1_W_stall, S1L196);

--S1_i_readdata_d1[18] is std_1c20:inst|cpu:the_cpu|i_readdata_d1[18]

--operation mode is normal

S1_i_readdata_d1[18] = AMPP_FUNCTION(QC2__clk0, U1L61, WC1L19, WC1L20, V1_cpu_instruction_master_qualified_request_cpu_jtag_debug_module, F1_data_out);

--M1_slave_readdata[12] is std_1c20:inst|clock_1:the_clock_1|slave_readdata[12]

--operation mode is normal

M1_slave_readdata[12]_lut_out = M1_slave_readdata_p1[12];

M1_slave_readdata[12] = DFFEAS(M1_slave_readdata[12]_lut_out, QC2__clk0, F1_data_out, , , , , , );

--J1_slave_readdata[12] is std_1c20:inst|clock_0:the_clock_0|slave_readdata[12]

--operation mode is normal

J1_slave_readdata[12]_lut_out = J1_slave_readdata_p1[12];

J1_slave_readdata[12] = DFFEAS(J1_slave_readdata[12]_lut_out, QC2__clk0, F1_data_out, , , , , , );

--T1L255 is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|p1_registered_cpu_data_master_readdata[12]~2058

--operation mode is normal

T1L255 = S1_M_alu_result[5] & M1_slave_readdata[12] # !S1_M_alu_result[5] & (J1_slave_readdata[12]) # !K1L6;

--NE2_b_non_empty is std_1c20:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_r:the_jtag_uart_scfifo_r|scfifo:rfifo|scfifo_jf21:auto_generated|a_dpfifo_ml21:dpfifo|a_fefifo_7cf:fifo_state|b_non_empty

--operation mode is normal

NE2_b_non_empty_lut_out = NE2L8 # NE2_b_non_empty & (NE2L3 # !BB1L43);

NE2_b_non_empty = DFFEAS(NE2_b_non_empty_lut_out, QC2__clk0, F1_data_out, , , , , , );

--T1L283 is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|p1_registered_cpu_data_master_readdata~61

--operation mode is normal

T1L283 = NE2_b_non_empty # !CB1L2 # !UB1L9;

--KB1_za_data[12] is std_1c20:inst|sdram:the_sdram|za_data[12]

--operation mode is normal

KB1_za_data[12]_lut_out = A1L256;

KB1_za_data[12] = DFFEAS(KB1_za_data[12]_lut_out, QC2__clk0, F1_data_out, , , , , , );

--Z1_counter_snapshot[12] is std_1c20:inst|high_res_timer:the_high_res_timer|counter_snapshot[12]

--operation mode is normal

Z1_counter_snapshot[12]_lut_out = Z1_internal_counter[12];

Z1_counter_snapshot[12] = DFFEAS(Z1_counter_snapshot[12]_lut_out, QC2__clk0, F1_data_out, , Z1L208, , , , );

--Z1_counter_snapshot[28] is std_1c20:inst|high_res_timer:the_high_res_timer|counter_snapshot[28]

--operation mode is normal

Z1_counter_snapshot[28]_lut_out = Z1_internal_counter[28];

Z1_counter_snapshot[28] = DFFEAS(Z1_counter_snapshot[28]_lut_out, QC2__clk0, F1_data_out, , Z1L208, , , , );

--Z1L183 is std_1c20:inst|high_res_timer:the_high_res_timer|read_mux_out[12]~1265

--operation mode is normal

Z1L183 = S1_M_alu_result[2] & (Z1_counter_snapshot[28] # !S1_M_alu_result[4]) # !S1_M_alu_result[2] & S1_M_alu_result[4] & Z1_counter_snapshot[12];

--Z1_period_h_register[12] is std_1c20:inst|high_res_timer:the_high_res_timer|period_h_register[12]

--operation mode is normal

Z1_period_h_register[12]_lut_out = S1_M_st_data[12];

Z1_period_h_register[12] = DFFEAS(Z1_period_h_register[12]_lut_out, QC2__clk0, F1_data_out, , Z1_period_h_wr_strobe, , , , );

--Z1_period_l_register[12] is std_1c20:inst|high_res_timer:the_high_res_timer|period_l_register[12]

--operation mode is normal

Z1_period_l_register[12]_lut_out = S1_M_st_data[12];

Z1_period_l_register[12] = DFFEAS(Z1_period_l_register[12]_lut_out, QC2__clk0, F1_data_out, , Z1_period_l_wr_strobe, , , , );

--Z1L184 is std_1c20:inst|high_res_timer:the_high_res_timer|read_mux_out[12]~1266

--operation mode is normal

Z1L184 = Z1L183 & Z1_period_h_register[12] # !Z1L183 & (!Z1_period_l_register[12]);

--RB1_counter_snapshot[12] is std_1c20:inst|sys_clk_timer:the_sys_clk_timer|counter_snapshot[12]

--operation mode is normal

RB1_counter_snapshot[12]_lut_out = RB1_internal_counter[12];

RB1_counter_snapshot[12] = DFFEAS(RB1_counter_snapshot[12]_lut_out, QC2__clk0, F1_data_out, , RB1L209, , , , );

--RB1_counter_snapshot[28] is std_1c20:inst|sys_clk_timer:the_sys_clk_timer|counter_snapshot[28]

--operation mode is normal

RB1_counter_snapshot[28]_lut_out = RB1_internal_counter[28];

RB1_counter_snapshot[28] = DFFEAS(RB1_counter_snapshot[28]_lut_out, QC2__clk0, F1_data_out, , RB1L209, , , , );

--RB1L184 is std_1c20:inst|sys_clk_timer:the_sys_clk_timer|read_mux_out[12]~1254

--operation mode is normal

RB1L184 = S1_M_alu_result[2] & (RB1_counter_snapshot[28] # !S1_M_alu_result[4]) # !S1_M_alu_result[2] & S1_M_alu_result[4] & RB1_counter_snapshot[12];

--RB1_period_h_register[12] is std_1c20:inst|sys_clk_timer:the_sys_clk_timer|period_h_register[12]

--operation mode is normal

RB1_period_h_register[12]_lut_out = S1_M_st_data[12];

RB1_period_h_register[12] = DFFEAS(RB1_period_h_register[12]_lut_out, QC2__clk0, F1_data_out, , RB1_period_h_wr_strobe, , , , );

--RB1_period_l_register[12] is std_1c20:inst|sys_clk_timer:the_sys_clk_timer|period_l_register[12]

--operation mode is normal

RB1_period_l_register[12]_lut_out = S1_M_st_data[12];

RB1_period_l_register[12] = DFFEAS(RB1_period_l_register[12]_lut_out, QC2__clk0, F1_data_out, , RB1_period_l_wr_strobe, , , , );

--RB1L185 is std_1c20:inst|sys_clk_timer:the_sys_clk_timer|read_mux_out[12]~1255

--operation mode is normal

RB1L185 = RB1L184 & RB1_period_h_register[12] # !RB1L184 & (!RB1_period_l_register[12]);

--DE1_endofpacketvalue_reg[12] is std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|endofpacketvalue_reg[12]

--operation mode is normal

DE1_endofpacketvalue_reg[12]_lut_out = S1_M_st_data[12];

DE1_endofpacketvalue_reg[12] = DFFEAS(DE1_endofpacketvalue_reg[12]_lut_out, QC2__clk0, F1_data_out, , DE1_endofpacketvalue_wr_strobe, , , , );

--DE1_epcs_slave_select_reg[12] is std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|epcs_slave_select_reg[12]

--operation mode is normal

DE1_epcs_slave_select_reg[12]_lut_out = DE1_epcs_slave_select_holding_reg[12];

DE1_epcs_slave_select_reg[12] = DFFEAS(DE1_epcs_slave_select_reg[12]_lut_out, QC2__clk0, F1_data_out, , DE1L142, , , , );

--KB1_za_data[28] is std_1c20:inst|sdram:the_sdram|za_data[28]

--operation mode is normal

KB1_za_data[28]_lut_out = A1L240;

KB1_za_data[28] = DFFEAS(KB1_za_data[28]_lut_out, QC2__clk0, F1_data_out, , , , , , );

--T1L269 is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|p1_registered_cpu_data_master_readdata[28]~2060

--operation mode is normal

T1L269 = S1_M_alu_result[25] # KB1_za_data[28] # !QB1L1 # !S1_M_alu_result[24];

--RE2_safe_q[1] is std_1c20:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_r:the_jtag_uart_scfifo_r|scfifo:rfifo|scfifo_jf21:auto_generated|a_dpfifo_ml21:dpfifo|a_fefifo_7cf:fifo_state|cntr_9c7:count_usedw|safe_q[1]

--operation mode is arithmetic

RE2_safe_q[1]_carry_eqn = RE2L2;

RE2_safe_q[1]_lut_out = RE2_safe_q[1] $ (RE2_safe_q[1]_carry_eqn);

RE2_safe_q[1] = DFFEAS(RE2_safe_q[1]_lut_out, QC2__clk0, F1_data_out, , NE2L1, , , , );

--RE2L4 is std_1c20:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_r:the_jtag_uart_scfifo_r|scfifo:rfifo|scfifo_jf21:auto_generated|a_dpfifo_ml21:dpfifo|a_fefifo_7cf:fifo_state|cntr_9c7:count_usedw|counter_cella1~COUT

--operation mode is arithmetic

RE2L4 = CARRY(RE2_safe_q[1] $ BB1_wr_rfifo # !RE2L2);

--BB1L31 is std_1c20:inst|jtag_uart:the_jtag_uart|Add1~306

--operation mode is arithmetic

BB1L31_carry_eqn = BB1L39;

BB1L31 = RE1_safe_q[1] $ (!BB1L31_carry_eqn);

--BB1L32 is std_1c20:inst|jtag_uart:the_jtag_uart|Add1~307

--operation mode is arithmetic

BB1L32 = CARRY(RE1_safe_q[1] # !BB1L39);

--BB1L33 is std_1c20:inst|jtag_uart:the_jtag_uart|Add1~308

--operation mode is normal

BB1L33 = BB1_read_0 & RE2_safe_q[1] # !BB1_read_0 & (BB1L31);

--BB1L34 is std_1c20:inst|jtag_uart:the_jtag_uart|Add1~309

--operation mode is normal

BB1L34 = BB1L33 # !CB1L2 # !UB1L9;

--KB1_za_data[17] is std_1c20:inst|sdram:the_sdram|za_data[17]

--operation mode is normal

KB1_za_data[17]_lut_out = A1L251;

KB1_za_data[17] = DFFEAS(KB1_za_data[17]_lut_out, QC2__clk0, F1_data_out, , , , , , );

--S1_M_shift_rot_result[28] is std_1c20:inst|cpu:the_cpu|M_shift_rot_result[28]

--operation mode is normal

S1_M_shift_rot_result[28] = AMPP_FUNCTION(QC2__clk0, S1_M_shift_rot_result[27], S1_M_shift_rot_result[29], S1L597, S1_M_ctrl_shift_rot_right, F1_data_out, !S1_M_shift_rot_stall);

--S1_E_src1_prelim[27] is std_1c20:inst|cpu:the_cpu|E_src1_prelim[27]

--operation mode is normal

S1_E_src1_prelim[27] = AMPP_FUNCTION(QC2__clk0, CD1_q_b[27], S1_W_wr_data[27], S1L1363, S1_D_src1_hazard_W, F1_data_out, S1_D_src1_hazard_M, S1_W_stall);

--S1L1361 is std_1c20:inst|cpu:the_cpu|M_wr_data_unfiltered[27]~3701

--operation mode is normal

S1L1361 = AMPP_FUNCTION(S1_M_shift_rot_result[27], S1_M_ctrl_shift_rot);

--S1_av_ld_data_aligned_or_div[27] is std_1c20:inst|cpu:the_cpu|av_ld_data_aligned_or_div[27]

--operation mode is normal

S1_av_ld_data_aligned_or_div[27] = AMPP_FUNCTION(QC2__clk0, S1_d_readdata_d1[27], S1_M_ctrl_ld_signed, S1L174, S1_M_iw[4], F1_data_out);

--S1_M_alu_result[27] is std_1c20:inst|cpu:the_cpu|M_alu_result[27]

--operation mode is normal

S1_M_alu_result[27] = AMPP_FUNCTION(QC2__clk0, S1L79, S1L535, A1L276, S1_E_ctrl_dst_data_sel_logic_result, F1_data_out, S1_E_ctrl_dst_data_sel_cmp, S1_E_ctrl_rdctl_inst, S1_W_stall);

--S1L1362 is std_1c20:inst|cpu:the_cpu|M_wr_data_unfiltered[27]~3702

--operation mode is normal

S1L1362 = AMPP_FUNCTION(S1_av_ld_data_aligned_or_div[27], S1_M_alu_result[27], S1_av_ld_or_div_done, S1_M_ctrl_shift_rot);

--S1L596 is std_1c20:inst|cpu:the_cpu|E_src1[27]~2043

--operation mode is normal

S1L596 = AMPP_FUNCTION(S1_E_src1_prelim[27], S1_E_src1_hazard_M, S1L1361, S1L1362);

--CD1_q_b[26] is std_1c20:inst|cpu:the_cpu|cpu_register_bank_a_module:cpu_register_bank_a|altsyncram:the_altsyncram|altsyncram_3vd1:auto_generated|q_b[26]

--RAM Block Operation Mode: Simple Dual-Port

--Port A Depth: 32, Port A Width: 1, Port B Depth: 32, Port B Width: 1

--Port A Logical Depth: 32, Port A Logical Width: 32, Port B Logical Depth: 32, Port B Logical Width: 32

--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered

CD1_q_b[26] = AMPP_FUNCTION(GND, GND, QC2__clk0, QC2__clk0, !S1_M_wr_dst_reg, S1_W_stall, S1L1360, S1_M_dst_regnum[0], S1_M_dst_regnum[1], S1_M_dst_regnum[2], S1_M_dst_regnum[3], S1_M_dst_regnum[4], AD1_q_b[27], AD1_q_b[28], AD1_q_b[29], AD1_q_b[30], AD1_q_b[31]);

--S1_W_wr_data[26] is std_1c20:inst|cpu:the_cpu|W_wr_data[26]

--operation mode is normal

S1_W_wr_data[26] = AMPP_FUNCTION(QC2__clk0, S1L1360, F1_data_out, S1_W_stall);

--YC1_result[26] is std_1c20:inst|cpu:the_cpu|lpm_add_sub:Add8|alt_stratix_add_sub:stratix_adder|result[26]

--operation mode is arithmetic

YC1_result[26] = AMPP_FUNCTION(S1L661, S1L595, YC1L53, S1_E_ctrl_alu_subtract);

--YC1L55 is std_1c20:inst|cpu:the_cpu|lpm_add_sub:Add8|alt_stratix_add_sub:stratix_adder|add_sub_cell[26]~COUT

--operation mode is arithmetic

YC1L55 = AMPP_FUNCTION(S1L661, S1L595, YC1L53, S1_E_ctrl_alu_subtract);

--S1L49 is std_1c20:inst|cpu:the_cpu|A_WE_StdLogicVector~14129

--operation mode is normal

S1L49 = AMPP_FUNCTION(YC1_result[26], S1_E_ctrl_dst_data_sel_pc_plus_one);

--S1_E_src2_imm[26] is std_1c20:inst|cpu:the_cpu|E_src2_imm[26]

--operation mode is normal

S1_E_src2_imm[26] = AMPP_FUNCTION(QC2__clk0, S1_D_iw[16], S1_D_iw[21], S1L228, S1L238, F1_data_out, S1_W_stall);

--S1_E_src2_prelim[26] is std_1c20:inst|cpu:the_cpu|E_src2_prelim[26]

--operation mode is normal

S1_E_src2_prelim[26] = AMPP_FUNCTION(QC2__clk0, DD1_q_b[26], S1_W_wr_data[26], S1L1360, S1L396, F1_data_out, S1L392, S1_W_stall);

--S1L736 is std_1c20:inst|cpu:the_cpu|E_src2_reg[26]~475

--operation mode is normal

S1L736 = AMPP_FUNCTION(S1_E_src2_prelim[26], S1_E_src2_hazard_M, S1L1358, S1L1359);

--S1L661 is std_1c20:inst|cpu:the_cpu|E_src2[26]~1530

--operation mode is normal

S1L661 = AMPP_FUNCTION(S1_E_src2_imm[26], S1L736, S1_E_ctrl_src2_is_imm);

--S1L534 is std_1c20:inst|cpu:the_cpu|E_logic_result[26]~15614

--operation mode is normal

S1L534 = AMPP_FUNCTION(S1_E_logic_op[1], S1L595, S1L661, S1_E_logic_op[0]);

--KB1_za_data[25] is std_1c20:inst|sdram:the_sdram|za_data[25]

--operation mode is normal

KB1_za_data[25]_lut_out = A1L243;

KB1_za_data[25] = DFFEAS(KB1_za_data[25]_lut_out, QC2__clk0, F1_data_out, , , , , , );

--T1L266 is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|p1_registered_cpu_data_master_readdata[25]~2063

--operation mode is normal

T1L266 = S1_M_alu_result[25] # KB1_za_data[25] # !QB1L1 # !S1_M_alu_result[24];

--KB1_za_data[20] is std_1c20:inst|sdram:the_sdram|za_data[20]

--operation mode is normal

KB1_za_data[20]_lut_out = A1L248;

KB1_za_data[20] = DFFEAS(KB1_za_data[20]_lut_out, QC2__clk0, F1_data_out, , , , , , );

--T1L261 is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|p1_registered_cpu_data_master_readdata[20]~2065

--operation mode is normal

T1L261 = S1_M_alu_result[25] # KB1_za_data[20] # !QB1L1 # !S1_M_alu_result[24];

--RE2_safe_q[4] is std_1c20:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_r:the_jtag_uart_scfifo_r|scfifo:rfifo|scfifo_jf21:auto_generated|a_dpfifo_ml21:dpfifo|a_fefifo_7cf:fifo_state|cntr_9c7:count_usedw|safe_q[4]

--operation mode is arithmetic

RE2_safe_q[4]_carry_eqn = RE2L8;

RE2_safe_q[4]_lut_out = RE2_safe_q[4] $ (!RE2_safe_q[4]_carry_eqn);

RE2_safe_q[4] = DFFEAS(RE2_safe_q[4]_lut_out, QC2__clk0, F1_data_out, , NE2L1, , , , );

--RE2L10 is std_1c20:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_r:the_jtag_uart_scfifo_r|scfifo:rfifo|scfifo_jf21:auto_generated|a_dpfifo_ml21:dpfifo|a_fefifo_7cf:fifo_state|cntr_9c7:count_usedw|counter_cella4~COUT

--operation mode is arithmetic

RE2L10 = CARRY(!RE2L8 & (RE2_safe_q[4] $ !BB1_wr_rfifo));

--BB1L35 is std_1c20:inst|jtag_uart:the_jtag_uart|Add1~310

--operation mode is arithmetic

BB1L35_carry_eqn = BB1L20;

BB1L35 = RE1_safe_q[4] $ (BB1L35_carry_eqn);

--BB1L36 is std_1c20:inst|jtag_uart:the_jtag_uart|Add1~311

--operation mode is arithmetic

BB1L36 = CARRY(!RE1_safe_q[4] & (!BB1L20));

--BB1L37 is std_1c20:inst|jtag_uart:the_jtag_uart|Add1~312

--operation mode is normal

BB1L37 = BB1_read_0 & RE2_safe_q[4] # !BB1_read_0 & (BB1L35);

--S1_i_readdata_d1[10] is std_1c20:inst|cpu:the_cpu|i_readdata_d1[10]

--operation mode is normal

S1_i_readdata_d1[10] = AMPP_FUNCTION(QC2__clk0, U1L38, WC1L19, WC1L11, V1_cpu_instruction_master_qualified_request_cpu_jtag_debug_module, F1_data_out);

--S1_i_readdata_d1[17] is std_1c20:inst|cpu:the_cpu|i_readdata_d1[17]

--operation mode is normal

S1_i_readdata_d1[17] = AMPP_FUNCTION(QC2__clk0, U1L58, WC1L19, WC1L18, V1_cpu_instruction_master_qualified_request_cpu_jtag_debug_module, F1_data_out);

--J1_slave_readdata[11] is std_1c20:inst|clock_0:the_clock_0|slave_readdata[11]

--operation mode is normal

J1_slave_readdata[11]_lut_out = J1_slave_readdata_p1[11];

J1_slave_readdata[11] = DFFEAS(J1_slave_readdata[11]_lut_out, QC2__clk0, F1_data_out, , , , , , );

--KB1_za_data[11] is std_1c20:inst|sdram:the_sdram|za_data[11]

--operation mode is normal

KB1_za_data[11]_lut_out = A1L257;

KB1_za_data[11] = DFFEAS(KB1_za_data[11]_lut_out, QC2__clk0, F1_data_out, , , , , , );

--T1L254 is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|p1_registered_cpu_data_master_readdata[11]~2067

--operation mode is normal

T1L254 = J1_slave_readdata[11] & (KB1_za_data[11] # !NB1L17) # !J1_slave_readdata[11] & !K1_cpu_data_master_requests_clock_0_in & (KB1_za_data[11] # !NB1L17);

--M1_slave_readdata[11] is std_1c20:inst|clock_1:the_clock_1|slave_readdata[11]

--operation mode is normal

M1_slave_readdata[11]_lut_out = M1_slave_readdata_p1[11];

M1_slave_readdata[11] = DFFEAS(M1_slave_readdata[11]_lut_out, QC2__clk0, F1_data_out, , , , , , );

--Z1_counter_snapshot[11] is std_1c20:inst|high_res_timer:the_high_res_timer|counter_snapshot[11]

--operation mode is normal

Z1_counter_snapshot[11]_lut_out = Z1_internal_counter[11];

Z1_counter_snapshot[11] = DFFEAS(Z1_counter_snapshot[11]_lut_out, QC2__clk0, F1_data_out, , Z1L208, , , , );

--Z1_counter_snapshot[27] is std_1c20:inst|high_res_timer:the_high_res_timer|counter_snapshot[27]

--operation mode is normal

Z1_counter_snapshot[27]_lut_out = Z1_internal_counter[27];

Z1_counter_snapshot[27] = DFFEAS(Z1_counter_snapshot[27]_lut_out, QC2__clk0, F1_data_out, , Z1L208, , , , );

--Z1L181 is std_1c20:inst|high_res_timer:the_high_res_timer|read_mux_out[11]~1268

--operation mode is normal

Z1L181 = S1_M_alu_result[2] & (Z1_counter_snapshot[27] # !S1_M_alu_result[4]) # !S1_M_alu_result[2] & S1_M_alu_result[4] & Z1_counter_snapshot[11];

--Z1_period_h_register[11] is std_1c20:inst|high_res_timer:the_high_res_timer|period_h_register[11]

--operation mode is normal

Z1_period_h_register[11]_lut_out = S1_M_st_data[11];

Z1_period_h_register[11] = DFFEAS(Z1_period_h_register[11]_lut_out, QC2__clk0, F1_data_out, , Z1_period_h_wr_strobe, , , , );

--Z1_period_l_register[11] is std_1c20:inst|high_res_timer:the_high_res_timer|period_l_register[11]

--operation mode is normal

Z1_period_l_register[11]_lut_out = S1_M_st_data[11];

Z1_period_l_register[11] = DFFEAS(Z1_period_l_register[11]_lut_out, QC2__clk0, F1_data_out, , Z1_period_l_wr_strobe, , , , );

--Z1L182 is std_1c20:inst|high_res_timer:the_high_res_timer|read_mux_out[11]~1269

--operation mode is normal

Z1L182 = Z1L181 & Z1_period_h_register[11] # !Z1L181 & (!Z1_period_l_register[11]);

--RB1_counter_snapshot[11] is std_1c20:inst|sys_clk_timer:the_sys_clk_timer|counter_snapshot[11]

--operation mode is normal

RB1_counter_snapshot[11]_lut_out = RB1_internal_counter[11];

RB1_counter_snapshot[11] = DFFEAS(RB1_counter_snapshot[11]_lut_out, QC2__clk0, F1_data_out, , RB1L209, , , , );

--RB1_counter_snapshot[27] is std_1c20:inst|sys_clk_timer:the_sys_clk_timer|counter_snapshot[27]

--operation mode is normal

RB1_counter_snapshot[27]_lut_out = RB1_internal_counter[27];

RB1_counter_snapshot[27] = DFFEAS(RB1_counter_snapshot[27]_lut_out, QC2__clk0, F1_data_out, , RB1L209, , , , );

--RB1L182 is std_1c20:inst|sys_clk_timer:the_sys_clk_timer|read_mux_out[11]~1257

--operation mode is normal

RB1L182 = S1_M_alu_result[2] & (RB1_counter_snapshot[27] # !S1_M_alu_result[4]) # !S1_M_alu_result[2] & S1_M_alu_result[4] & RB1_counter_snapshot[11];

--RB1_period_h_register[11] is std_1c20:inst|sys_clk_timer:the_sys_clk_timer|period_h_register[11]

--operation mode is normal

RB1_period_h_register[11]_lut_out = S1_M_st_data[11];

RB1_period_h_register[11] = DFFEAS(RB1_period_h_register[11]_lut_out, QC2__clk0, F1_data_out, , RB1_period_h_wr_strobe, , , , );

--RB1_period_l_register[11] is std_1c20:inst|sys_clk_timer:the_sys_clk_timer|period_l_register[11]

--operation mode is normal

RB1_period_l_register[11]_lut_out = S1_M_st_data[11];

RB1_period_l_register[11] = DFFEAS(RB1_period_l_register[11]_lut_out, QC2__clk0, F1_data_out, , RB1_period_l_wr_strobe, , , , );

--RB1L183 is std_1c20:inst|sys_clk_timer:the_sys_clk_timer|read_mux_out[11]~1258

--operation mode is normal

RB1L183 = RB1L182 & RB1_period_h_register[11] # !RB1L182 & (!RB1_period_l_register[11]);

--DE1_endofpacketvalue_reg[11] is std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|endofpacketvalue_reg[11]

--operation mode is normal

DE1_endofpacketvalue_reg[11]_lut_out = S1_M_st_data[11];

DE1_endofpacketvalue_reg[11] = DFFEAS(DE1_endofpacketvalue_reg[11]_lut_out, QC2__clk0, F1_data_out, , DE1_endofpacketvalue_wr_strobe, , , , );

--DE1_epcs_slave_select_reg[11] is std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|epcs_slave_select_reg[11]

--operation mode is normal

DE1_epcs_slave_select_reg[11]_lut_out = DE1_epcs_slave_select_holding_reg[11];

DE1_epcs_slave_select_reg[11] = DFFEAS(DE1_epcs_slave_select_reg[11]_lut_out, QC2__clk0, F1_data_out, , DE1L142, , , , );

--KB1_za_data[27] is std_1c20:inst|sdram:the_sdram|za_data[27]

--operation mode is normal

KB1_za_data[27]_lut_out = A1L241;

KB1_za_data[27] = DFFEAS(KB1_za_data[27]_lut_out, QC2__clk0, F1_data_out, , , , , , );

--T1L268 is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|p1_registered_cpu_data_master_readdata[27]~2069

--operation mode is normal

T1L268 = S1_M_alu_result[25] # KB1_za_data[27] # !QB1L1 # !S1_M_alu_result[24];

--DE1_epcs_slave_select_reg[10] is std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|epcs_slave_select_reg[10]

--operation mode is normal

DE1_epcs_slave_select_reg[10]_lut_out = DE1_epcs_slave_select_holding_reg[10];

DE1_epcs_slave_select_reg[10] = DFFEAS(DE1_epcs_slave_select_reg[10]_lut_out, QC2__clk0, F1_data_out, , DE1L142, , , , );

--DE1L7 is std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|A_WE_StdLogicVector~1127

--operation mode is normal

DE1L7 = X1L14 & X1L16 & DE1_epcs_slave_select_reg[10] & !X1L15;

--DE1_endofpacketvalue_reg[10] is std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|endofpacketvalue_reg[10]

--operation mode is normal

DE1_endofpacketvalue_reg[10]_lut_out = S1_M_st_data[10];

DE1_endofpacketvalue_reg[10] = DFFEAS(DE1_endofpacketvalue_reg[10]_lut_out, QC2__clk0, F1_data_out, , DE1_endofpacketvalue_wr_strobe, , , , );

--DE1_SSO_reg is std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|SSO_reg

--operation mode is normal

DE1_SSO_reg_lut_out = S1_M_st_data[10];

DE1_SSO_reg = DFFEAS(DE1_SSO_reg_lut_out, QC2__clk0, F1_data_out, , DE1_control_wr_strobe, , , , );

--Z1_counter_snapshot[10] is std_1c20:inst|high_res_timer:the_high_res_timer|counter_snapshot[10]

--operation mode is normal

Z1_counter_snapshot[10]_lut_out = Z1_internal_counter[10];

Z1_counter_snapshot[10] = DFFEAS(Z1_counter_snapshot[10]_lut_out, QC2__clk0, F1_data_out, , Z1L208, , , , );

--Z1_counter_snapshot[26] is std_1c20:inst|high_res_timer:the_high_res_timer|counter_snapshot[26]

--operation mode is normal

Z1_counter_snapshot[26]_lut_out = Z1_internal_counter[26];

Z1_counter_snapshot[26] = DFFEAS(Z1_counter_snapshot[26]_lut_out, QC2__clk0, F1_data_out, , Z1L208, , , , );

--Z1L179 is std_1c20:inst|high_res_timer:the_high_res_timer|read_mux_out[10]~1271

--operation mode is normal

Z1L179 = S1_M_alu_result[2] & (Z1_counter_snapshot[26] # !S1_M_alu_result[4]) # !S1_M_alu_result[2] & S1_M_alu_result[4] & Z1_counter_snapshot[10];

--Z1_period_h_register[10] is std_1c20:inst|high_res_timer:the_high_res_timer|period_h_register[10]

--operation mode is normal

Z1_period_h_register[10]_lut_out = S1_M_st_data[10];

Z1_period_h_register[10] = DFFEAS(Z1_period_h_register[10]_lut_out, QC2__clk0, F1_data_out, , Z1_period_h_wr_strobe, , , , );

--Z1_period_l_register[10] is std_1c20:inst|high_res_timer:the_high_res_timer|period_l_register[10]

--operation mode is normal

Z1_period_l_register[10]_lut_out = S1_M_st_data[10];

Z1_period_l_register[10] = DFFEAS(Z1_period_l_register[10]_lut_out, QC2__clk0, F1_data_out, , Z1_period_l_wr_strobe, , , , );

--Z1L180 is std_1c20:inst|high_res_timer:the_high_res_timer|read_mux_out[10]~1272

--operation mode is normal

Z1L180 = Z1L179 & Z1_period_h_register[10] # !Z1L179 & (!Z1_period_l_register[10]);

--RB1_counter_snapshot[10] is std_1c20:inst|sys_clk_timer:the_sys_clk_timer|counter_snapshot[10]

--operation mode is normal

RB1_counter_snapshot[10]_lut_out = RB1_internal_counter[10];

RB1_counter_snapshot[10] = DFFEAS(RB1_counter_snapshot[10]_lut_out, QC2__clk0, F1_data_out, , RB1L209, , , , );

--RB1_counter_snapshot[26] is std_1c20:inst|sys_clk_timer:the_sys_clk_timer|counter_snapshot[26]

--operation mode is normal

RB1_counter_snapshot[26]_lut_out = RB1_internal_counter[26];

RB1_counter_snapshot[26] = DFFEAS(RB1_counter_snapshot[26]_lut_out, QC2__clk0, F1_data_out, , RB1L209, , , , );

--RB1L180 is std_1c20:inst|sys_clk_timer:the_sys_clk_timer|read_mux_out[10]~1260

--operation mode is normal

RB1L180 = S1_M_alu_result[2] & (RB1_counter_snapshot[26] # !S1_M_alu_result[4]) # !S1_M_alu_result[2] & S1_M_alu_result[4] & RB1_counter_snapshot[10];

--RB1_period_h_register[10] is std_1c20:inst|sys_clk_timer:the_sys_clk_timer|period_h_register[10]

--operation mode is normal

RB1_period_h_register[10]_lut_out = S1_M_st_data[10];

RB1_period_h_register[10] = DFFEAS(RB1_period_h_register[10]_lut_out, QC2__clk0, F1_data_out, , RB1_period_h_wr_strobe, , , , );

--RB1_period_l_register[10] is std_1c20:inst|sys_clk_timer:the_sys_clk_timer|period_l_register[10]

--operation mode is normal

RB1_period_l_register[10]_lut_out = S1_M_st_data[10];

RB1_period_l_register[10] = DFFEAS(RB1_period_l_register[10]_lut_out, QC2__clk0, F1_data_out, , RB1_period_l_wr_strobe, , , , );

--RB1L181 is std_1c20:inst|sys_clk_timer:the_sys_clk_timer|read_mux_out[10]~1261

--operation mode is normal

RB1L181 = RB1L180 & RB1_period_h_register[10] # !RB1L180 & (!RB1_period_l_register[10]);

--M1_slave_readdata[10] is std_1c20:inst|clock_1:the_clock_1|slave_readdata[10]

--operation mode is normal

M1_slave_readdata[10]_lut_out = M1_slave_readdata_p1[10];

M1_slave_readdata[10] = DFFEAS(M1_slave_readdata[10]_lut_out, QC2__clk0, F1_data_out, , , , , , );

--J1_slave_readdata[10] is std_1c20:inst|clock_0:the_clock_0|slave_readdata[10]

--operation mode is normal

J1_slave_readdata[10]_lut_out = J1_slave_readdata_p1[10];

J1_slave_readdata[10] = DFFEAS(J1_slave_readdata[10]_lut_out, QC2__clk0, F1_data_out, , , , , , );

--T1L253 is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|p1_registered_cpu_data_master_readdata[10]~2071

--operation mode is normal

T1L253 = S1_M_alu_result[5] & M1_slave_readdata[10] # !S1_M_alu_result[5] & (J1_slave_readdata[10]) # !K1L6;

--BB1_ac is std_1c20:inst|jtag_uart:the_jtag_uart|ac

--operation mode is normal

BB1_ac_lut_out = BB1L2 # BB1_ac & (!BB1L46 # !S1_M_st_data[10]);

BB1_ac = DFFEAS(BB1_ac_lut_out, QC2__clk0, F1_data_out, , , , , , );

--T1L282 is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|p1_registered_cpu_data_master_readdata~59

--operation mode is normal

T1L282 = BB1_ac # !CB1L2 # !UB1L9;

--KB1_za_data[10] is std_1c20:inst|sdram:the_sdram|za_data[10]

--operation mode is normal

KB1_za_data[10]_lut_out = A1L258;

KB1_za_data[10] = DFFEAS(KB1_za_data[10]_lut_out, QC2__clk0, F1_data_out, , , , , , );

--KB1_za_data[26] is std_1c20:inst|sdram:the_sdram|za_data[26]

--operation mode is normal

KB1_za_data[26]_lut_out = A1L242;

KB1_za_data[26] = DFFEAS(KB1_za_data[26]_lut_out, QC2__clk0, F1_data_out, , , , , , );

--T1L267 is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|p1_registered_cpu_data_master_readdata[26]~2073

--operation mode is normal

T1L267 = S1_M_alu_result[25] # KB1_za_data[26] # !QB1L1 # !S1_M_alu_result[24];

--DE1_iEOP_reg is std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|iEOP_reg

--operation mode is normal

DE1_iEOP_reg_lut_out = S1_M_st_data[9];

DE1_iEOP_reg = DFFEAS(DE1_iEOP_reg_lut_out, QC2__clk0, F1_data_out, , DE1_control_wr_strobe, , , , );

--DE1_endofpacketvalue_reg[9] is std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|endofpacketvalue_reg[9]

--operation mode is normal

DE1_endofpacketvalue_reg[9]_lut_out = S1_M_st_data[9];

DE1_endofpacketvalue_reg[9] = DFFEAS(DE1_endofpacketvalue_reg[9]_lut_out, QC2__clk0, F1_data_out, , DE1_endofpacketvalue_wr_strobe, , , , );

--DE1_epcs_slave_select_reg[9] is std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|epcs_slave_select_reg[9]

--operation mode is normal

DE1_epcs_slave_select_reg[9]_lut_out = DE1_epcs_slave_select_holding_reg[9];

DE1_epcs_slave_select_reg[9] = DFFEAS(DE1_epcs_slave_select_reg[9]_lut_out, QC2__clk0, F1_data_out, , DE1L142, , , , );

--DE1L8 is std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|A_WE_StdLogicVector~1128

--operation mode is normal

DE1L8 = DE1L114 & DE1_endofpacketvalue_reg[9] # !DE1L114 & (DE1L113 & DE1_epcs_slave_select_reg[9]);

--DE1_EOP is std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|EOP

--operation mode is normal

DE1_EOP_lut_out = !DE1_status_wr_strobe & (DE1_EOP # DE1L75 & DE1L78);

DE1_EOP = DFFEAS(DE1_EOP_lut_out, QC2__clk0, F1_data_out, , , , , , );

--Z1_counter_snapshot[9] is std_1c20:inst|high_res_timer:the_high_res_timer|counter_snapshot[9]

--operation mode is normal

Z1_counter_snapshot[9]_lut_out = !Z1_internal_counter[9];

Z1_counter_snapshot[9] = DFFEAS(Z1_counter_snapshot[9]_lut_out, QC2__clk0, F1_data_out, , Z1L208, , , , );

--Z1_counter_snapshot[25] is std_1c20:inst|high_res_timer:the_high_res_timer|counter_snapshot[25]

--operation mode is normal

Z1_counter_snapshot[25]_lut_out = Z1_internal_counter[25];

Z1_counter_snapshot[25] = DFFEAS(Z1_counter_snapshot[25]_lut_out, QC2__clk0, F1_data_out, , Z1L208, , , , );

--Z1L177 is std_1c20:inst|high_res_timer:the_high_res_timer|read_mux_out[9]~1274

--operation mode is normal

Z1L177 = S1_M_alu_result[2] & (Z1_counter_snapshot[25] # !S1_M_alu_result[4]) # !S1_M_alu_result[2] & S1_M_alu_result[4] & Z1_counter_snapshot[9];

--Z1_period_h_register[9] is std_1c20:inst|high_res_timer:the_high_res_timer|period_h_register[9]

--operation mode is normal

Z1_period_h_register[9]_lut_out = S1_M_st_data[9];

Z1_period_h_register[9] = DFFEAS(Z1_period_h_register[9]_lut_out, QC2__clk0, F1_data_out, , Z1_period_h_wr_strobe, , , , );

--Z1_period_l_register[9] is std_1c20:inst|high_res_timer:the_high_res_timer|period_l_register[9]

--operation mode is normal

Z1_period_l_register[9]_lut_out = !S1_M_st_data[9];

Z1_period_l_register[9] = DFFEAS(Z1_period_l_register[9]_lut_out, QC2__clk0, F1_data_out, , Z1_period_l_wr_strobe, , , , );

--Z1L178 is std_1c20:inst|high_res_timer:the_high_res_timer|read_mux_out[9]~1275

--operation mode is normal

Z1L178 = Z1L177 & Z1_period_h_register[9] # !Z1L177 & (Z1_period_l_register[9]);

--RB1_counter_snapshot[9] is std_1c20:inst|sys_clk_timer:the_sys_clk_timer|counter_snapshot[9]

--operation mode is normal

RB1_counter_snapshot[9]_lut_out = RB1_internal_counter[9];

RB1_counter_snapshot[9] = DFFEAS(RB1_counter_snapshot[9]_lut_out, QC2__clk0, F1_data_out, , RB1L209, , , , );

--RB1_counter_snapshot[25] is std_1c20:inst|sys_clk_timer:the_sys_clk_timer|counter_snapshot[25]

--operation mode is normal

RB1_counter_snapshot[25]_lut_out = RB1_internal_counter[25];

RB1_counter_snapshot[25] = DFFEAS(RB1_counter_snapshot[25]_lut_out, QC2__clk0, F1_data_out, , RB1L209, , , , );

--RB1L178 is std_1c20:inst|sys_clk_timer:the_sys_clk_timer|read_mux_out[9]~1263

--operation mode is normal

RB1L178 = S1_M_alu_result[2] & (RB1_counter_snapshot[25] # !S1_M_alu_result[4]) # !S1_M_alu_result[2] & S1_M_alu_result[4] & RB1_counter_snapshot[9];

--RB1_period_h_register[9] is std_1c20:inst|sys_clk_timer:the_sys_clk_timer|period_h_register[9]

--operation mode is normal

RB1_period_h_register[9]_lut_out = S1_M_st_data[9];

RB1_period_h_register[9] = DFFEAS(RB1_period_h_register[9]_lut_out, QC2__clk0, F1_data_out, , RB1_period_h_wr_strobe, , , , );

--RB1_period_l_register[9] is std_1c20:inst|sys_clk_timer:the_sys_clk_timer|period_l_register[9]

--operation mode is normal

RB1_period_l_register[9]_lut_out = S1_M_st_data[9];

RB1_period_l_register[9] = DFFEAS(RB1_period_l_register[9]_lut_out, QC2__clk0, F1_data_out, , RB1_period_l_wr_strobe, , , , );

--RB1L179 is std_1c20:inst|sys_clk_timer:the_sys_clk_timer|read_mux_out[9]~1264

--operation mode is normal

RB1L179 = RB1L178 & RB1_period_h_register[9] # !RB1L178 & (!RB1_period_l_register[9]);

--M1_slave_readdata[9] is std_1c20:inst|clock_1:the_clock_1|slave_readdata[9]

--operation mode is normal

M1_slave_readdata[9]_lut_out = M1_slave_readdata_p1[9];

M1_slave_readdata[9] = DFFEAS(M1_slave_readdata[9]_lut_out, QC2__clk0, F1_data_out, , , , , , );

--J1_slave_readdata[9] is std_1c20:inst|clock_0:the_clock_0|slave_readdata[9]

--operation mode is normal

J1_slave_readdata[9]_lut_out = J1_slave_readdata_p1[9];

J1_slave_readdata[9] = DFFEAS(J1_slave_readdata[9]_lut_out, QC2__clk0, F1_data_out, , , , , , );

--T1L252 is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|p1_registered_cpu_data_master_readdata[9]~2075

--operation mode is normal

T1L252 = S1_M_alu_result[5] & M1_slave_readdata[9] # !S1_M_alu_result[5] & (J1_slave_readdata[9]) # !K1L6;

--KB1_za_data[9] is std_1c20:inst|sdram:the_sdram|za_data[9]

--operation mode is normal

KB1_za_data[9]_lut_out = A1L259;

KB1_za_data[9] = DFFEAS(KB1_za_data[9]_lut_out, QC2__clk0, F1_data_out, , , , , , );

--Z1_counter_snapshot[8] is std_1c20:inst|high_res_timer:the_high_res_timer|counter_snapshot[8]

--operation mode is normal

Z1_counter_snapshot[8]_lut_out = !Z1_internal_counter[8];

Z1_counter_snapshot[8] = DFFEAS(Z1_counter_snapshot[8]_lut_out, QC2__clk0, F1_data_out, , Z1L208, , , , );

--Z1_counter_snapshot[24] is std_1c20:inst|high_res_timer:the_high_res_timer|counter_snapshot[24]

--operation mode is normal

Z1_counter_snapshot[24]_lut_out = Z1_internal_counter[24];

Z1_counter_snapshot[24] = DFFEAS(Z1_counter_snapshot[24]_lut_out, QC2__clk0, F1_data_out, , Z1L208, , , , );

--Z1L175 is std_1c20:inst|high_res_timer:the_high_res_timer|read_mux_out[8]~1277

--operation mode is normal

Z1L175 = S1_M_alu_result[2] & (Z1_counter_snapshot[24] # !S1_M_alu_result[4]) # !S1_M_alu_result[2] & S1_M_alu_result[4] & Z1_counter_snapshot[8];

--Z1_period_h_register[8] is std_1c20:inst|high_res_timer:the_high_res_timer|period_h_register[8]

--operation mode is normal

Z1_period_h_register[8]_lut_out = S1_M_st_data[8];

Z1_period_h_register[8] = DFFEAS(Z1_period_h_register[8]_lut_out, QC2__clk0, F1_data_out, , Z1_period_h_wr_strobe, , , , );

--Z1_period_l_register[8] is std_1c20:inst|high_res_timer:the_high_res_timer|period_l_register[8]

--operation mode is normal

Z1_period_l_register[8]_lut_out = !S1_M_st_data[8];

Z1_period_l_register[8] = DFFEAS(Z1_period_l_register[8]_lut_out, QC2__clk0, F1_data_out, , Z1_period_l_wr_strobe, , , , );

--Z1L176 is std_1c20:inst|high_res_timer:the_high_res_timer|read_mux_out[8]~1278

--operation mode is normal

Z1L176 = Z1L175 & Z1_period_h_register[8] # !Z1L175 & (Z1_period_l_register[8]);

--XE1L22 is std_1c20:inst|uart1:the_uart1|uart1_regs:the_uart1_regs|Equal1~123

--operation mode is normal

XE1L22 = S1_M_alu_result[3] & (!S1_M_alu_result[4]);

--XE1_control_reg[8] is std_1c20:inst|uart1:the_uart1|uart1_regs:the_uart1_regs|control_reg[8]

--operation mode is normal

XE1_control_reg[8]_lut_out = S1_M_st_data[8];

XE1_control_reg[8] = DFFEAS(XE1_control_reg[8]_lut_out, QC2__clk0, F1_data_out, , XE1L14, , , , );

--YE1_framing_error is std_1c20:inst|uart1:the_uart1|uart1_rx:the_uart1_rx|framing_error

--operation mode is normal

YE1_framing_error_lut_out = YE1L40 & (!XE1L20 # !XE1L13);

YE1_framing_error = DFFEAS(YE1_framing_error_lut_out, QC2__clk0, F1_data_out, , , , , , );

--ZE1_tx_overrun is std_1c20:inst|uart1:the_uart1|uart1_tx:the_uart1_tx|tx_overrun

--operation mode is normal

ZE1_tx_overrun_lut_out = ZE1_tx_overrun & (!XE1L20 # !XE1L13) # !ZE1_tx_overrun & ZE1L31 & (!XE1L20 # !XE1L13);

ZE1_tx_overrun = DFFEAS(ZE1_tx_overrun_lut_out, QC2__clk0, F1_data_out, , , , , , );

--XE1L1 is std_1c20:inst|uart1:the_uart1|uart1_regs:the_uart1_regs|any_error~21

--operation mode is normal

XE1L1 = YE1_break_detect # YE1_rx_overrun # YE1_framing_error # ZE1_tx_overrun;

--M1_slave_readdata[8] is std_1c20:inst|clock_1:the_clock_1|slave_readdata[8]

--operation mode is normal

M1_slave_readdata[8]_lut_out = M1_slave_readdata_p1[8];

M1_slave_readdata[8] = DFFEAS(M1_slave_readdata[8]_lut_out, QC2__clk0, F1_data_out, , , , , , );

--J1_slave_readdata[8] is std_1c20:inst|clock_0:the_clock_0|slave_readdata[8]

--operation mode is normal

J1_slave_readdata[8]_lut_out = J1_slave_readdata_p1[8];

J1_slave_readdata[8] = DFFEAS(J1_slave_readdata[8]_lut_out, QC2__clk0, F1_data_out, , , , , , );

--T1L251 is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|p1_registered_cpu_data_master_readdata[8]~2077

--operation mode is normal

T1L251 = S1_M_alu_result[5] & M1_slave_readdata[8] # !S1_M_alu_result[5] & (J1_slave_readdata[8]) # !K1L6;

--T1L288 is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|p1_registered_cpu_data_master_readdata~2078

--operation mode is normal

T1L288 = T1L287 # !CB1L2 # !UB1L9;

--KB1_za_data[8] is std_1c20:inst|sdram:the_sdram|za_data[8]

--operation mode is normal

KB1_za_data[8]_lut_out = A1L260;

KB1_za_data[8] = DFFEAS(KB1_za_data[8]_lut_out, QC2__clk0, F1_data_out, , , , , , );

--RB1_counter_snapshot[8] is std_1c20:inst|sys_clk_timer:the_sys_clk_timer|counter_snapshot[8]

--operation mode is normal

RB1_counter_snapshot[8]_lut_out = !RB1_internal_counter[8];

RB1_counter_snapshot[8] = DFFEAS(RB1_counter_snapshot[8]_lut_out, QC2__clk0, F1_data_out, , RB1L209, , , , );

--RB1_counter_snapshot[24] is std_1c20:inst|sys_clk_timer:the_sys_clk_timer|counter_snapshot[24]

--operation mode is normal

RB1_counter_snapshot[24]_lut_out = RB1_internal_counter[24];

RB1_counter_snapshot[24] = DFFEAS(RB1_counter_snapshot[24]_lut_out, QC2__clk0, F1_data_out, , RB1L209, , , , );

--RB1L176 is std_1c20:inst|sys_clk_timer:the_sys_clk_timer|read_mux_out[8]~1266

--operation mode is normal

RB1L176 = S1_M_alu_result[2] & (RB1_counter_snapshot[24] # !S1_M_alu_result[4]) # !S1_M_alu_result[2] & S1_M_alu_result[4] & RB1_counter_snapshot[8];

--RB1_period_h_register[8] is std_1c20:inst|sys_clk_timer:the_sys_clk_timer|period_h_register[8]

--operation mode is normal

RB1_period_h_register[8]_lut_out = S1_M_st_data[8];

RB1_period_h_register[8] = DFFEAS(RB1_period_h_register[8]_lut_out, QC2__clk0, F1_data_out, , RB1_period_h_wr_strobe, , , , );

--RB1_period_l_register[8] is std_1c20:inst|sys_clk_timer:the_sys_clk_timer|period_l_register[8]

--operation mode is normal

RB1_period_l_register[8]_lut_out = !S1_M_st_data[8];

RB1_period_l_register[8] = DFFEAS(RB1_period_l_register[8]_lut_out, QC2__clk0, F1_data_out, , RB1_period_l_wr_strobe, , , , );

--RB1L177 is std_1c20:inst|sys_clk_timer:the_sys_clk_timer|read_mux_out[8]~1267

--operation mode is normal

RB1L177 = RB1L176 & RB1_period_h_register[8] # !RB1L176 & (RB1_period_l_register[8]);

--DE1_iE_reg is std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|iE_reg

--operation mode is normal

DE1_iE_reg_lut_out = S1_M_st_data[8];

DE1_iE_reg = DFFEAS(DE1_iE_reg_lut_out, QC2__clk0, F1_data_out, , DE1_control_wr_strobe, , , , );

--DE1_endofpacketvalue_reg[8] is std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|endofpacketvalue_reg[8]

--operation mode is normal

DE1_endofpacketvalue_reg[8]_lut_out = S1_M_st_data[8];

DE1_endofpacketvalue_reg[8] = DFFEAS(DE1_endofpacketvalue_reg[8]_lut_out, QC2__clk0, F1_data_out, , DE1_endofpacketvalue_wr_strobe, , , , );

--DE1_epcs_slave_select_reg[8] is std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|epcs_slave_select_reg[8]

--operation mode is normal

DE1_epcs_slave_select_reg[8]_lut_out = DE1_epcs_slave_select_holding_reg[8];

DE1_epcs_slave_select_reg[8] = DFFEAS(DE1_epcs_slave_select_reg[8]_lut_out, QC2__clk0, F1_data_out, , DE1L142, , , , );

--DE1L9 is std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|A_WE_StdLogicVector~1129

--operation mode is normal

DE1L9 = DE1L114 & DE1_endofpacketvalue_reg[8] # !DE1L114 & (DE1L113 & DE1_epcs_slave_select_reg[8]);

--DE1_TOE is std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|TOE

--operation mode is normal

DE1_TOE_lut_out = !DE1_status_wr_strobe & (DE1_TOE # DE1_data_wr_strobe & !DE1L193);

DE1_TOE = DFFEAS(DE1_TOE_lut_out, QC2__clk0, F1_data_out, , , , , , );

--DE1_E is std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|E

--operation mode is normal

DE1_E = DE1_ROE # DE1_TOE;

--RB1_counter_snapshot[6] is std_1c20:inst|sys_clk_timer:the_sys_clk_timer|counter_snapshot[6]

--operation mode is normal

RB1_counter_snapshot[6]_lut_out = RB1_internal_counter[6];

RB1_counter_snapshot[6] = DFFEAS(RB1_counter_snapshot[6]_lut_out, QC2__clk0, F1_data_out, , RB1L209, , , , );

--RB1_counter_snapshot[22] is std_1c20:inst|sys_clk_timer:the_sys_clk_timer|counter_snapshot[22]

--operation mode is normal

RB1_counter_snapshot[22]_lut_out = RB1_internal_counter[22];

RB1_counter_snapshot[22] = DFFEAS(RB1_counter_snapshot[22]_lut_out, QC2__clk0, F1_data_out, , RB1L209, , , , );

--RB1L172 is std_1c20:inst|sys_clk_timer:the_sys_clk_timer|read_mux_out[6]~1269

--operation mode is normal

RB1L172 = S1_M_alu_result[2] & (RB1_counter_snapshot[22] # !S1_M_alu_result[4]) # !S1_M_alu_result[2] & S1_M_alu_result[4] & RB1_counter_snapshot[6];

--RB1_period_h_register[6] is std_1c20:inst|sys_clk_timer:the_sys_clk_timer|period_h_register[6]

--operation mode is normal

RB1_period_h_register[6]_lut_out = S1_M_st_data[6];

RB1_period_h_register[6] = DFFEAS(RB1_period_h_register[6]_lut_out, QC2__clk0, F1_data_out, , RB1_period_h_wr_strobe, , , , );

--RB1_period_l_register[6] is std_1c20:inst|sys_clk_timer:the_sys_clk_timer|period_l_register[6]

--operation mode is normal

RB1_period_l_register[6]_lut_out = S1_M_st_data[6];

RB1_period_l_register[6] = DFFEAS(RB1_period_l_register[6]_lut_out, QC2__clk0, F1_data_out, , RB1_period_l_wr_strobe, , , , );

--RB1L173 is std_1c20:inst|sys_clk_timer:the_sys_clk_timer|read_mux_out[6]~1270

--operation mode is normal

RB1L173 = RB1L172 & RB1_period_h_register[6] # !RB1L172 & (!RB1_period_l_register[6]);

--Z1_counter_snapshot[6] is std_1c20:inst|high_res_timer:the_high_res_timer|counter_snapshot[6]

--operation mode is normal

Z1_counter_snapshot[6]_lut_out = !Z1_internal_counter[6];

Z1_counter_snapshot[6] = DFFEAS(Z1_counter_snapshot[6]_lut_out, QC2__clk0, F1_data_out, , Z1L208, , , , );

--Z1_counter_snapshot[22] is std_1c20:inst|high_res_timer:the_high_res_timer|counter_snapshot[22]

--operation mode is normal

Z1_counter_snapshot[22]_lut_out = Z1_internal_counter[22];

Z1_counter_snapshot[22] = DFFEAS(Z1_counter_snapshot[22]_lut_out, QC2__clk0, F1_data_out, , Z1L208, , , , );

--Z1L171 is std_1c20:inst|high_res_timer:the_high_res_timer|read_mux_out[6]~1280

--operation mode is normal

Z1L171 = S1_M_alu_result[2] & (Z1_counter_snapshot[22] # !S1_M_alu_result[4]) # !S1_M_alu_result[2] & S1_M_alu_result[4] & Z1_counter_snapshot[6];

--Z1_period_h_register[6] is std_1c20:inst|high_res_timer:the_high_res_timer|period_h_register[6]

--operation mode is normal

Z1_period_h_register[6]_lut_out = S1_M_st_data[6];

Z1_period_h_register[6] = DFFEAS(Z1_period_h_register[6]_lut_out, QC2__clk0, F1_data_out, , Z1_period_h_wr_strobe, , , , );

--Z1_period_l_register[6] is std_1c20:inst|high_res_timer:the_high_res_timer|period_l_register[6]

--operation mode is normal

Z1_period_l_register[6]_lut_out = !S1_M_st_data[6];

Z1_period_l_register[6] = DFFEAS(Z1_period_l_register[6]_lut_out, QC2__clk0, F1_data_out, , Z1_period_l_wr_strobe, , , , );

--Z1L172 is std_1c20:inst|high_res_timer:the_high_res_timer|read_mux_out[6]~1281

--operation mode is normal

Z1L172 = Z1L171 & Z1_period_h_register[6] # !Z1L171 & (Z1_period_l_register[6]);

--XE1_control_reg[6] is std_1c20:inst|uart1:the_uart1|uart1_regs:the_uart1_regs|control_reg[6]

--operation mode is normal

XE1_control_reg[6]_lut_out = S1_M_st_data[6];

XE1_control_reg[6] = DFFEAS(XE1_control_reg[6]_lut_out, QC2__clk0, F1_data_out, , XE1L14, , , , );

--XE1L60 is std_1c20:inst|uart1:the_uart1|uart1_regs:the_uart1_regs|selected_read_data[6]~686

--operation mode is normal

XE1L60 = S1_M_alu_result[3] & (XE1_control_reg[6]) # !S1_M_alu_result[3] & XE1_internal_tx_data[6];

--YE1_rx_data[6] is std_1c20:inst|uart1:the_uart1|uart1_rx:the_uart1_rx|rx_data[6]

--operation mode is normal

YE1_rx_data[6]_lut_out = YE1_unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[7];

YE1_rx_data[6] = DFFEAS(YE1_rx_data[6]_lut_out, QC2__clk0, F1_data_out, , YE1_got_new_char, , , , );

--XE1L61 is std_1c20:inst|uart1:the_uart1|uart1_regs:the_uart1_regs|selected_read_data[6]~687

--operation mode is normal

XE1L61 = S1_M_alu_result[3] & !ZE1_internal_tx_ready # !S1_M_alu_result[3] & (YE1_rx_data[6]);

--M1_slave_readdata[6] is std_1c20:inst|clock_1:the_clock_1|slave_readdata[6]

--operation mode is normal

M1_slave_readdata[6]_lut_out = M1_slave_readdata_p1[6];

M1_slave_readdata[6] = DFFEAS(M1_slave_readdata[6]_lut_out, QC2__clk0, F1_data_out, , , , , , );

--J1_slave_readdata[6] is std_1c20:inst|clock_0:the_clock_0|slave_readdata[6]

--operation mode is normal

J1_slave_readdata[6]_lut_out = J1_slave_readdata_p1[6];

J1_slave_readdata[6] = DFFEAS(J1_slave_readdata[6]_lut_out, QC2__clk0, F1_data_out, , , , , , );

--T1L249 is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|p1_registered_cpu_data_master_readdata[6]~2080

--operation mode is normal

T1L249 = S1_M_alu_result[5] & M1_slave_readdata[6] # !S1_M_alu_result[5] & (J1_slave_readdata[6]) # !K1L6;

--SE2_q_b[6] is std_1c20:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_r:the_jtag_uart_scfifo_r|scfifo:rfifo|scfifo_jf21:auto_generated|a_dpfifo_ml21:dpfifo|dpram_j921:FIFOram|altsyncram_nll1:altsyncram1|q_b[6]

--RAM Block Operation Mode: Simple Dual-Port

--Port A Depth: 64, Port A Width: 1, Port B Depth: 64, Port B Width: 1

--Port A Logical Depth: 64, Port A Logical Width: 8, Port B Logical Depth: 64, Port B Logical Width: 8

--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered

SE2_q_b[6]_PORT_A_data_in = GE1_wdata[6];

SE2_q_b[6]_PORT_A_data_in_reg = DFFE(SE2_q_b[6]_PORT_A_data_in, SE2_q_b[6]_clock_0, , , SE2_q_b[6]_clock_enable_0);

SE2_q_b[6]_PORT_A_address = BUS(QE4_safe_q[0], QE4_safe_q[1], QE4_safe_q[2], QE4_safe_q[3], QE4_safe_q[4], QE4_safe_q[5]);

SE2_q_b[6]_PORT_A_address_reg = DFFE(SE2_q_b[6]_PORT_A_address, SE2_q_b[6]_clock_0, , , SE2_q_b[6]_clock_enable_0);

SE2_q_b[6]_PORT_B_address = BUS(QE3_safe_q[0], QE3_safe_q[1], QE3_safe_q[2], QE3_safe_q[3], QE3_safe_q[4], QE3_safe_q[5]);

SE2_q_b[6]_PORT_B_address_reg = DFFE(SE2_q_b[6]_PORT_B_address, SE2_q_b[6]_clock_1, , , SE2_q_b[6]_clock_enable_1);

SE2_q_b[6]_PORT_A_write_enable = VCC;

SE2_q_b[6]_PORT_A_write_enable_reg = DFFE(SE2_q_b[6]_PORT_A_write_enable, SE2_q_b[6]_clock_0, , , SE2_q_b[6]_clock_enable_0);

SE2_q_b[6]_PORT_B_read_enable = VCC;

SE2_q_b[6]_PORT_B_read_enable_reg = DFFE(SE2_q_b[6]_PORT_B_read_enable, SE2_q_b[6]_clock_1, , , SE2_q_b[6]_clock_enable_1);

SE2_q_b[6]_clock_0 = QC2__clk0;

SE2_q_b[6]_clock_1 = QC2__clk0;

SE2_q_b[6]_clock_enable_0 = BB1_wr_rfifo;

SE2_q_b[6]_clock_enable_1 = BB1L61;

SE2_q_b[6]_PORT_B_data_out = MEMORY(SE2_q_b[6]_PORT_A_data_in_reg, , SE2_q_b[6]_PORT_A_address_reg, SE2_q_b[6]_PORT_B_address_reg, SE2_q_b[6]_PORT_A_write_enable_reg, SE2_q_b[6]_PORT_B_read_enable_reg, , , SE2_q_b[6]_clock_0, SE2_q_b[6]_clock_1, SE2_q_b[6]_clock_enable_0, SE2_q_b[6]_clock_enable_1, , );

SE2_q_b[6] = SE2_q_b[6]_PORT_B_data_out[0];

--T1L279 is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|p1_registered_cpu_data_master_readdata~55

--operation mode is normal

T1L279 = SE2_q_b[6] & BB1_read_0 # !CB1L2 # !UB1L9;

--KB1_za_data[6] is std_1c20:inst|sdram:the_sdram|za_data[6]

--operation mode is normal

KB1_za_data[6]_lut_out = A1L262;

KB1_za_data[6] = DFFEAS(KB1_za_data[6]_lut_out, QC2__clk0, F1_data_out, , , , , , );

--DE1_iTRDY_reg is std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|iTRDY_reg

--operation mode is normal

DE1_iTRDY_reg_lut_out = S1_M_st_data[6];

DE1_iTRDY_reg = DFFEAS(DE1_iTRDY_reg_lut_out, QC2__clk0, F1_data_out, , DE1_control_wr_strobe, , , , );

--DE1_endofpacketvalue_reg[6] is std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|endofpacketvalue_reg[6]

--operation mode is normal

DE1_endofpacketvalue_reg[6]_lut_out = S1_M_st_data[6];

DE1_endofpacketvalue_reg[6] = DFFEAS(DE1_endofpacketvalue_reg[6]_lut_out, QC2__clk0, F1_data_out, , DE1_endofpacketvalue_wr_strobe, , , , );

--DE1_epcs_slave_select_reg[6] is std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|epcs_slave_select_reg[6]

--operation mode is normal

DE1_epcs_slave_select_reg[6]_lut_out = DE1_epcs_slave_select_holding_reg[6];

DE1_epcs_slave_select_reg[6] = DFFEAS(DE1_epcs_slave_select_reg[6]_lut_out, QC2__clk0, F1_data_out, , DE1L142, , , , );

--DE1L10 is std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|A_WE_StdLogicVector~1130

--operation mode is normal

DE1L10 = X1L14 & X1L16 & DE1_epcs_slave_select_reg[6] & !X1L15;

--DE1_rx_holding_reg[6] is std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|rx_holding_reg[6]

--operation mode is normal

DE1_rx_holding_reg[6]_lut_out = DE1_shift_reg[6];

DE1_rx_holding_reg[6] = DFFEAS(DE1_rx_holding_reg[6]_lut_out, QC2__clk0, F1_data_out, , DE1L156, , , , );

--DE1L11 is std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|A_WE_StdLogicVector~1131

--operation mode is normal

DE1L11 = DE1_rx_holding_reg[6] & (X1L15 # !X1L16 # !X1L14);

--DE1L12 is std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|A_WE_StdLogicVector~1132

--operation mode is normal

DE1L12 = DE1L114 & DE1_endofpacketvalue_reg[6] # !DE1L114 & (DE1L10 # DE1L11);

--DE1_tx_holding_primed is std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|tx_holding_primed

--operation mode is normal

DE1_tx_holding_primed_lut_out = DE1_data_wr_strobe # DE1_tx_holding_primed & DE1_transmitting;

DE1_tx_holding_primed = DFFEAS(DE1_tx_holding_primed_lut_out, QC2__clk0, F1_data_out, , , , , , );

--DE1_transmitting is std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|transmitting

--operation mode is normal

DE1_transmitting_lut_out = !DE1L192 & (!DE1L118 # !DE1_state[4] # !DE1_slowcount[0]);

DE1_transmitting = DFFEAS(DE1_transmitting_lut_out, QC2__clk0, F1_data_out, , , , , , );

--DE1L193 is std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|TRDY~0

--operation mode is normal

DE1L193 = !DE1_transmitting # !DE1_tx_holding_primed;

--XE1_control_reg[4] is std_1c20:inst|uart1:the_uart1|uart1_regs:the_uart1_regs|control_reg[4]

--operation mode is normal

XE1_control_reg[4]_lut_out = S1_M_st_data[4];

XE1_control_reg[4] = DFFEAS(XE1_control_reg[4]_lut_out, QC2__clk0, F1_data_out, , XE1L14, , , , );

--XE1_control_reg[5] is std_1c20:inst|uart1:the_uart1|uart1_regs:the_uart1_regs|control_reg[5]

--operation mode is normal

XE1_control_reg[5]_lut_out = S1_M_st_data[5];

XE1_control_reg[5] = DFFEAS(XE1_control_reg[5]_lut_out, QC2__clk0, F1_data_out, , XE1L14, , , , );

--ZE1_tx_shift_empty is std_1c20:inst|uart1:the_uart1|uart1_tx:the_uart1_tx|tx_shift_empty

--operation mode is normal

ZE1_tx_shift_empty_lut_out = ZE1_unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out[0] # ZE1_internal_tx_ready # !ZE1L28;

ZE1_tx_shift_empty = DFFEAS(ZE1_tx_shift_empty_lut_out, QC2__clk0, F1_data_out, , , , , , );

--XE1L34 is std_1c20:inst|uart1:the_uart1|uart1_regs:the_uart1_regs|qualified_irq~115

--operation mode is normal

XE1L34 = ZE1_tx_overrun & (XE1_control_reg[4] # XE1_control_reg[5] & !ZE1_tx_shift_empty) # !ZE1_tx_overrun & (XE1_control_reg[5] & !ZE1_tx_shift_empty);

--XE1_control_reg[1] is std_1c20:inst|uart1:the_uart1|uart1_regs:the_uart1_regs|control_reg[1]

--operation mode is normal

XE1_control_reg[1]_lut_out = S1_M_st_data[1];

XE1_control_reg[1] = DFFEAS(XE1_control_reg[1]_lut_out, QC2__clk0, F1_data_out, , XE1L14, , , , );

--XE1L35 is std_1c20:inst|uart1:the_uart1|uart1_regs:the_uart1_regs|qualified_irq~116

--operation mode is normal

XE1L35 = YE1_framing_error & (XE1_control_reg[1] # XE1_control_reg[6] & !ZE1_internal_tx_ready) # !YE1_framing_error & (XE1_control_reg[6] & !ZE1_internal_tx_ready);

--XE1L36 is std_1c20:inst|uart1:the_uart1|uart1_regs:the_uart1_regs|qualified_irq~117

--operation mode is normal

XE1L36 = XE1L34 # XE1L35 # XE1L1 & XE1_control_reg[8];

--XE1L37 is std_1c20:inst|uart1:the_uart1|uart1_regs:the_uart1_regs|qualified_irq~118

--operation mode is normal

XE1L37 = YE1_break_detect & (XE1_control_reg[2] # YE1_rx_overrun & XE1_control_reg[3]) # !YE1_break_detect & YE1_rx_overrun & XE1_control_reg[3];

--Z1_counter_snapshot[4] is std_1c20:inst|high_res_timer:the_high_res_timer|counter_snapshot[4]

--operation mode is normal

Z1_counter_snapshot[4]_lut_out = Z1_internal_counter[4];

Z1_counter_snapshot[4] = DFFEAS(Z1_counter_snapshot[4]_lut_out, QC2__clk0, F1_data_out, , Z1L208, , , , );

--Z1_counter_snapshot[20] is std_1c20:inst|high_res_timer:the_high_res_timer|counter_snapshot[20]

--operation mode is normal

Z1_counter_snapshot[20]_lut_out = Z1_internal_counter[20];

Z1_counter_snapshot[20] = DFFEAS(Z1_counter_snapshot[20]_lut_out, QC2__clk0, F1_data_out, , Z1L208, , , , );

--Z1L167 is std_1c20:inst|high_res_timer:the_high_res_timer|read_mux_out[4]~1283

--operation mode is normal

Z1L167 = S1_M_alu_result[2] & (Z1_counter_snapshot[20] # !S1_M_alu_result[4]) # !S1_M_alu_result[2] & S1_M_alu_result[4] & Z1_counter_snapshot[4];

--Z1_period_h_register[4] is std_1c20:inst|high_res_timer:the_high_res_timer|period_h_register[4]

--operation mode is normal

Z1_period_h_register[4]_lut_out = S1_M_st_data[4];

Z1_period_h_register[4] = DFFEAS(Z1_period_h_register[4]_lut_out, QC2__clk0, F1_data_out, , Z1_period_h_wr_strobe, , , , );

--Z1_period_l_register[4] is std_1c20:inst|high_res_timer:the_high_res_timer|period_l_register[4]

--operation mode is normal

Z1_period_l_register[4]_lut_out = S1_M_st_data[4];

Z1_period_l_register[4] = DFFEAS(Z1_period_l_register[4]_lut_out, QC2__clk0, F1_data_out, , Z1_period_l_wr_strobe, , , , );

--Z1L168 is std_1c20:inst|high_res_timer:the_high_res_timer|read_mux_out[4]~1284

--operation mode is normal

Z1L168 = Z1L167 & Z1_period_h_register[4] # !Z1L167 & (!Z1_period_l_register[4]);

--XE1L56 is std_1c20:inst|uart1:the_uart1|uart1_regs:the_uart1_regs|selected_read_data[4]~689

--operation mode is normal

XE1L56 = S1_M_alu_result[3] & (XE1_control_reg[4]) # !S1_M_alu_result[3] & XE1_internal_tx_data[4];

--YE1_rx_data[4] is std_1c20:inst|uart1:the_uart1|uart1_rx:the_uart1_rx|rx_data[4]

--operation mode is normal

YE1_rx_data[4]_lut_out = YE1_unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[5];

YE1_rx_data[4] = DFFEAS(YE1_rx_data[4]_lut_out, QC2__clk0, F1_data_out, , YE1_got_new_char, , , , );

--XE1L57 is std_1c20:inst|uart1:the_uart1|uart1_regs:the_uart1_regs|selected_read_data[4]~690

--operation mode is normal

XE1L57 = S1_M_alu_result[3] & ZE1_tx_overrun # !S1_M_alu_result[3] & (YE1_rx_data[4]);

--RB1_counter_snapshot[4] is std_1c20:inst|sys_clk_timer:the_sys_clk_timer|counter_snapshot[4]

--operation mode is normal

RB1_counter_snapshot[4]_lut_out = !RB1_internal_counter[4];

RB1_counter_snapshot[4] = DFFEAS(RB1_counter_snapshot[4]_lut_out, QC2__clk0, F1_data_out, , RB1L209, , , , );

--RB1_counter_snapshot[20] is std_1c20:inst|sys_clk_timer:the_sys_clk_timer|counter_snapshot[20]

--operation mode is normal

RB1_counter_snapshot[20]_lut_out = RB1_internal_counter[20];

RB1_counter_snapshot[20] = DFFEAS(RB1_counter_snapshot[20]_lut_out, QC2__clk0, F1_data_out, , RB1L209, , , , );

--RB1L168 is std_1c20:inst|sys_clk_timer:the_sys_clk_timer|read_mux_out[4]~1272

--operation mode is normal

RB1L168 = S1_M_alu_result[2] & (RB1_counter_snapshot[20] # !S1_M_alu_result[4]) # !S1_M_alu_result[2] & S1_M_alu_result[4] & RB1_counter_snapshot[4];

--RB1_period_h_register[4] is std_1c20:inst|sys_clk_timer:the_sys_clk_timer|period_h_register[4]

--operation mode is normal

RB1_period_h_register[4]_lut_out = S1_M_st_data[4];

RB1_period_h_register[4] = DFFEAS(RB1_period_h_register[4]_lut_out, QC2__clk0, F1_data_out, , RB1_period_h_wr_strobe, , , , );

--RB1_period_l_register[4] is std_1c20:inst|sys_clk_timer:the_sys_clk_timer|period_l_register[4]

--operation mode is normal

RB1_period_l_register[4]_lut_out = !S1_M_st_data[4];

RB1_period_l_register[4] = DFFEAS(RB1_period_l_register[4]_lut_out, QC2__clk0, F1_data_out, , RB1_period_l_wr_strobe, , , , );

--RB1L169 is std_1c20:inst|sys_clk_timer:the_sys_clk_timer|read_mux_out[4]~1273

--operation mode is normal

RB1L169 = RB1L168 & RB1_period_h_register[4] # !RB1L168 & (RB1_period_l_register[4]);

--M1_slave_readdata[4] is std_1c20:inst|clock_1:the_clock_1|slave_readdata[4]

--operation mode is normal

M1_slave_readdata[4]_lut_out = M1_slave_readdata_p1[4];

M1_slave_readdata[4] = DFFEAS(M1_slave_readdata[4]_lut_out, QC2__clk0, F1_data_out, , , , , , );

--J1_slave_readdata[4] is std_1c20:inst|clock_0:the_clock_0|slave_readdata[4]

--operation mode is normal

J1_slave_readdata[4]_lut_out = J1_slave_readdata_p1[4];

J1_slave_readdata[4] = DFFEAS(J1_slave_readdata[4]_lut_out, QC2__clk0, F1_data_out, , , , , , );

--T1L247 is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|p1_registered_cpu_data_master_readdata[4]~2082

--operation mode is normal

T1L247 = S1_M_alu_result[5] & M1_slave_readdata[4] # !S1_M_alu_result[5] & (J1_slave_readdata[4]) # !K1L6;

--SE2_q_b[4] is std_1c20:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_r:the_jtag_uart_scfifo_r|scfifo:rfifo|scfifo_jf21:auto_generated|a_dpfifo_ml21:dpfifo|dpram_j921:FIFOram|altsyncram_nll1:altsyncram1|q_b[4]

--RAM Block Operation Mode: Simple Dual-Port

--Port A Depth: 64, Port A Width: 1, Port B Depth: 64, Port B Width: 1

--Port A Logical Depth: 64, Port A Logical Width: 8, Port B Logical Depth: 64, Port B Logical Width: 8

--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered

SE2_q_b[4]_PORT_A_data_in = GE1_wdata[4];

SE2_q_b[4]_PORT_A_data_in_reg = DFFE(SE2_q_b[4]_PORT_A_data_in, SE2_q_b[4]_clock_0, , , SE2_q_b[4]_clock_enable_0);

SE2_q_b[4]_PORT_A_address = BUS(QE4_safe_q[0], QE4_safe_q[1], QE4_safe_q[2], QE4_safe_q[3], QE4_safe_q[4], QE4_safe_q[5]);

SE2_q_b[4]_PORT_A_address_reg = DFFE(SE2_q_b[4]_PORT_A_address, SE2_q_b[4]_clock_0, , , SE2_q_b[4]_clock_enable_0);

SE2_q_b[4]_PORT_B_address = BUS(QE3_safe_q[0], QE3_safe_q[1], QE3_safe_q[2], QE3_safe_q[3], QE3_safe_q[4], QE3_safe_q[5]);

SE2_q_b[4]_PORT_B_address_reg = DFFE(SE2_q_b[4]_PORT_B_address, SE2_q_b[4]_clock_1, , , SE2_q_b[4]_clock_enable_1);

SE2_q_b[4]_PORT_A_write_enable = VCC;

SE2_q_b[4]_PORT_A_write_enable_reg = DFFE(SE2_q_b[4]_PORT_A_write_enable, SE2_q_b[4]_clock_0, , , SE2_q_b[4]_clock_enable_0);

SE2_q_b[4]_PORT_B_read_enable = VCC;

SE2_q_b[4]_PORT_B_read_enable_reg = DFFE(SE2_q_b[4]_PORT_B_read_enable, SE2_q_b[4]_clock_1, , , SE2_q_b[4]_clock_enable_1);

SE2_q_b[4]_clock_0 = QC2__clk0;

SE2_q_b[4]_clock_1 = QC2__clk0;

SE2_q_b[4]_clock_enable_0 = BB1_wr_rfifo;

SE2_q_b[4]_clock_enable_1 = BB1L61;

SE2_q_b[4]_PORT_B_data_out = MEMORY(SE2_q_b[4]_PORT_A_data_in_reg, , SE2_q_b[4]_PORT_A_address_reg, SE2_q_b[4]_PORT_B_address_reg, SE2_q_b[4]_PORT_A_write_enable_reg, SE2_q_b[4]_PORT_B_read_enable_reg, , , SE2_q_b[4]_clock_0, SE2_q_b[4]_clock_1, SE2_q_b[4]_clock_enable_0, SE2_q_b[4]_clock_enable_1, , );

SE2_q_b[4] = SE2_q_b[4]_PORT_B_data_out[0];

--T1L277 is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|p1_registered_cpu_data_master_readdata~53

--operation mode is normal

T1L277 = SE2_q_b[4] & BB1_read_0 # !CB1L2 # !UB1L9;

--KB1_za_data[4] is std_1c20:inst|sdram:the_sdram|za_data[4]

--operation mode is normal

KB1_za_data[4]_lut_out = A1L264;

KB1_za_data[4] = DFFEAS(KB1_za_data[4]_lut_out, QC2__clk0, F1_data_out, , , , , , );

--DE1_iTOE_reg is std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|iTOE_reg

--operation mode is normal

DE1_iTOE_reg_lut_out = S1_M_st_data[4];

DE1_iTOE_reg = DFFEAS(DE1_iTOE_reg_lut_out, QC2__clk0, F1_data_out, , DE1_control_wr_strobe, , , , );

--DE1_endofpacketvalue_reg[4] is std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|endofpacketvalue_reg[4]

--operation mode is normal

DE1_endofpacketvalue_reg[4]_lut_out = S1_M_st_data[4];

DE1_endofpacketvalue_reg[4] = DFFEAS(DE1_endofpacketvalue_reg[4]_lut_out, QC2__clk0, F1_data_out, , DE1_endofpacketvalue_wr_strobe, , , , );

--DE1_epcs_slave_select_reg[4] is std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|epcs_slave_select_reg[4]

--operation mode is normal

DE1_epcs_slave_select_reg[4]_lut_out = DE1_epcs_slave_select_holding_reg[4];

DE1_epcs_slave_select_reg[4] = DFFEAS(DE1_epcs_slave_select_reg[4]_lut_out, QC2__clk0, F1_data_out, , DE1L142, , , , );

--DE1L13 is std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|A_WE_StdLogicVector~1133

--operation mode is normal

DE1L13 = X1L14 & X1L16 & DE1_epcs_slave_select_reg[4] & !X1L15;

--DE1_rx_holding_reg[4] is std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|rx_holding_reg[4]

--operation mode is normal

DE1_rx_holding_reg[4]_lut_out = DE1_shift_reg[4];

DE1_rx_holding_reg[4] = DFFEAS(DE1_rx_holding_reg[4]_lut_out, QC2__clk0, F1_data_out, , DE1L156, , , , );

--DE1L14 is std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|A_WE_StdLogicVector~1134

--operation mode is normal

DE1L14 = DE1_rx_holding_reg[4] & (X1L15 # !X1L16 # !X1L14);

--DE1L15 is std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|A_WE_StdLogicVector~1135

--operation mode is normal

DE1L15 = DE1L114 & DE1_endofpacketvalue_reg[4] # !DE1L114 & (DE1L13 # DE1L14);

--DE1L123 is std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|irq_reg~134

--operation mode is normal

DE1L123 = DE1_RRDY & (DE1_iRRDY_reg # DE1_EOP & DE1_iEOP_reg) # !DE1_RRDY & DE1_EOP & DE1_iEOP_reg;

--DE1L124 is std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|irq_reg~135

--operation mode is normal

DE1L124 = DE1L123 # DE1_iTRDY_reg & (!DE1_transmitting # !DE1_tx_holding_primed);

--DE1L125 is std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|irq_reg~136

--operation mode is normal

DE1L125 = DE1_iE_reg & (DE1_ROE # DE1_TOE) # !DE1_iE_reg & (DE1_TOE & DE1_iTOE_reg);

--Z1_counter_snapshot[5] is std_1c20:inst|high_res_timer:the_high_res_timer|counter_snapshot[5]

--operation mode is normal

Z1_counter_snapshot[5]_lut_out = Z1_internal_counter[5];

Z1_counter_snapshot[5] = DFFEAS(Z1_counter_snapshot[5]_lut_out, QC2__clk0, F1_data_out, , Z1L208, , , , );

--Z1_counter_snapshot[21] is std_1c20:inst|high_res_timer:the_high_res_timer|counter_snapshot[21]

--operation mode is normal

Z1_counter_snapshot[21]_lut_out = Z1_internal_counter[21];

Z1_counter_snapshot[21] = DFFEAS(Z1_counter_snapshot[21]_lut_out, QC2__clk0, F1_data_out, , Z1L208, , , , );

--Z1L169 is std_1c20:inst|high_res_timer:the_high_res_timer|read_mux_out[5]~1286

--operation mode is normal

Z1L169 = S1_M_alu_result[2] & (Z1_counter_snapshot[21] # !S1_M_alu_result[4]) # !S1_M_alu_result[2] & S1_M_alu_result[4] & Z1_counter_snapshot[5];

--Z1_period_h_register[5] is std_1c20:inst|high_res_timer:the_high_res_timer|period_h_register[5]

--operation mode is normal

Z1_period_h_register[5]_lut_out = S1_M_st_data[5];

Z1_period_h_register[5] = DFFEAS(Z1_period_h_register[5]_lut_out, QC2__clk0, F1_data_out, , Z1_period_h_wr_strobe, , , , );

--Z1_period_l_register[5] is std_1c20:inst|high_res_timer:the_high_res_timer|period_l_register[5]

--operation mode is normal

Z1_period_l_register[5]_lut_out = S1_M_st_data[5];

Z1_period_l_register[5] = DFFEAS(Z1_period_l_register[5]_lut_out, QC2__clk0, F1_data_out, , Z1_period_l_wr_strobe, , , , );

--Z1L170 is std_1c20:inst|high_res_timer:the_high_res_timer|read_mux_out[5]~1287

--operation mode is normal

Z1L170 = Z1L169 & Z1_period_h_register[5] # !Z1L169 & (!Z1_period_l_register[5]);

--XE1L58 is std_1c20:inst|uart1:the_uart1|uart1_regs:the_uart1_regs|selected_read_data[5]~692

--operation mode is normal

XE1L58 = S1_M_alu_result[3] & (XE1_control_reg[5]) # !S1_M_alu_result[3] & XE1_internal_tx_data[5];

--YE1_rx_data[5] is std_1c20:inst|uart1:the_uart1|uart1_rx:the_uart1_rx|rx_data[5]

--operation mode is normal

YE1_rx_data[5]_lut_out = YE1_unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[6];

YE1_rx_data[5] = DFFEAS(YE1_rx_data[5]_lut_out, QC2__clk0, F1_data_out, , YE1_got_new_char, , , , );

--XE1L59 is std_1c20:inst|uart1:the_uart1|uart1_regs:the_uart1_regs|selected_read_data[5]~693

--operation mode is normal

XE1L59 = S1_M_alu_result[3] & !ZE1_tx_shift_empty # !S1_M_alu_result[3] & (YE1_rx_data[5]);

--M1_slave_readdata[5] is std_1c20:inst|clock_1:the_clock_1|slave_readdata[5]

--operation mode is normal

M1_slave_readdata[5]_lut_out = M1_slave_readdata_p1[5];

M1_slave_readdata[5] = DFFEAS(M1_slave_readdata[5]_lut_out, QC2__clk0, F1_data_out, , , , , , );

--J1_slave_readdata[5] is std_1c20:inst|clock_0:the_clock_0|slave_readdata[5]

--operation mode is normal

J1_slave_readdata[5]_lut_out = J1_slave_readdata_p1[5];

J1_slave_readdata[5] = DFFEAS(J1_slave_readdata[5]_lut_out, QC2__clk0, F1_data_out, , , , , , );

--T1L248 is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|p1_registered_cpu_data_master_readdata[5]~2084

--operation mode is normal

T1L248 = S1_M_alu_result[5] & M1_slave_readdata[5] # !S1_M_alu_result[5] & (J1_slave_readdata[5]) # !K1L6;

--SE2_q_b[5] is std_1c20:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_r:the_jtag_uart_scfifo_r|scfifo:rfifo|scfifo_jf21:auto_generated|a_dpfifo_ml21:dpfifo|dpram_j921:FIFOram|altsyncram_nll1:altsyncram1|q_b[5]

--RAM Block Operation Mode: Simple Dual-Port

--Port A Depth: 64, Port A Width: 1, Port B Depth: 64, Port B Width: 1

--Port A Logical Depth: 64, Port A Logical Width: 8, Port B Logical Depth: 64, Port B Logical Width: 8

--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered

SE2_q_b[5]_PORT_A_data_in = GE1_wdata[5];

SE2_q_b[5]_PORT_A_data_in_reg = DFFE(SE2_q_b[5]_PORT_A_data_in, SE2_q_b[5]_clock_0, , , SE2_q_b[5]_clock_enable_0);

SE2_q_b[5]_PORT_A_address = BUS(QE4_safe_q[0], QE4_safe_q[1], QE4_safe_q[2], QE4_safe_q[3], QE4_safe_q[4], QE4_safe_q[5]);

SE2_q_b[5]_PORT_A_address_reg = DFFE(SE2_q_b[5]_PORT_A_address, SE2_q_b[5]_clock_0, , , SE2_q_b[5]_clock_enable_0);

SE2_q_b[5]_PORT_B_address = BUS(QE3_safe_q[0], QE3_safe_q[1], QE3_safe_q[2], QE3_safe_q[3], QE3_safe_q[4], QE3_safe_q[5]);

SE2_q_b[5]_PORT_B_address_reg = DFFE(SE2_q_b[5]_PORT_B_address, SE2_q_b[5]_clock_1, , , SE2_q_b[5]_clock_enable_1);

SE2_q_b[5]_PORT_A_write_enable = VCC;

SE2_q_b[5]_PORT_A_write_enable_reg = DFFE(SE2_q_b[5]_PORT_A_write_enable, SE2_q_b[5]_clock_0, , , SE2_q_b[5]_clock_enable_0);

SE2_q_b[5]_PORT_B_read_enable = VCC;

SE2_q_b[5]_PORT_B_read_enable_reg = DFFE(SE2_q_b[5]_PORT_B_read_enable, SE2_q_b[5]_clock_1, , , SE2_q_b[5]_clock_enable_1);

SE2_q_b[5]_clock_0 = QC2__clk0;

SE2_q_b[5]_clock_1 = QC2__clk0;

SE2_q_b[5]_clock_enable_0 = BB1_wr_rfifo;

SE2_q_b[5]_clock_enable_1 = BB1L61;

SE2_q_b[5]_PORT_B_data_out = MEMORY(SE2_q_b[5]_PORT_A_data_in_reg, , SE2_q_b[5]_PORT_A_address_reg, SE2_q_b[5]_PORT_B_address_reg, SE2_q_b[5]_PORT_A_write_enable_reg, SE2_q_b[5]_PORT_B_read_enable_reg, , , SE2_q_b[5]_clock_0, SE2_q_b[5]_clock_1, SE2_q_b[5]_clock_enable_0, SE2_q_b[5]_clock_enable_1, , );

SE2_q_b[5] = SE2_q_b[5]_PORT_B_data_out[0];

--T1L278 is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|p1_registered_cpu_data_master_readdata~54

--operation mode is normal

T1L278 = SE2_q_b[5] & BB1_read_0 # !CB1L2 # !UB1L9;

--KB1_za_data[5] is std_1c20:inst|sdram:the_sdram|za_data[5]

--operation mode is normal

KB1_za_data[5]_lut_out = A1L263;

KB1_za_data[5] = DFFEAS(KB1_za_data[5]_lut_out, QC2__clk0, F1_data_out, , , , , , );

--RB1_counter_snapshot[5] is std_1c20:inst|sys_clk_timer:the_sys_clk_timer|counter_snapshot[5]

--operation mode is normal

RB1_counter_snapshot[5]_lut_out = RB1_internal_counter[5];

RB1_counter_snapshot[5] = DFFEAS(RB1_counter_snapshot[5]_lut_out, QC2__clk0, F1_data_out, , RB1L209, , , , );

--RB1_counter_snapshot[21] is std_1c20:inst|sys_clk_timer:the_sys_clk_timer|counter_snapshot[21]

--operation mode is normal

RB1_counter_snapshot[21]_lut_out = RB1_internal_counter[21];

RB1_counter_snapshot[21] = DFFEAS(RB1_counter_snapshot[21]_lut_out, QC2__clk0, F1_data_out, , RB1L209, , , , );

--RB1L170 is std_1c20:inst|sys_clk_timer:the_sys_clk_timer|read_mux_out[5]~1275

--operation mode is normal

RB1L170 = S1_M_alu_result[2] & (RB1_counter_snapshot[21] # !S1_M_alu_result[4]) # !S1_M_alu_result[2] & S1_M_alu_result[4] & RB1_counter_snapshot[5];

--RB1_period_h_register[5] is std_1c20:inst|sys_clk_timer:the_sys_clk_timer|period_h_register[5]

--operation mode is normal

RB1_period_h_register[5]_lut_out = S1_M_st_data[5];

RB1_period_h_register[5] = DFFEAS(RB1_period_h_register[5]_lut_out, QC2__clk0, F1_data_out, , RB1_period_h_wr_strobe, , , , );

--RB1_period_l_register[5] is std_1c20:inst|sys_clk_timer:the_sys_clk_timer|period_l_register[5]

--operation mode is normal

RB1_period_l_register[5]_lut_out = S1_M_st_data[5];

RB1_period_l_register[5] = DFFEAS(RB1_period_l_register[5]_lut_out, QC2__clk0, F1_data_out, , RB1_period_l_wr_strobe, , , , );

--RB1L171 is std_1c20:inst|sys_clk_timer:the_sys_clk_timer|read_mux_out[5]~1276

--operation mode is normal

RB1L171 = RB1L170 & RB1_period_h_register[5] # !RB1L170 & (!RB1_period_l_register[5]);

--DE1_endofpacketvalue_reg[5] is std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|endofpacketvalue_reg[5]

--operation mode is normal

DE1_endofpacketvalue_reg[5]_lut_out = S1_M_st_data[5];

DE1_endofpacketvalue_reg[5] = DFFEAS(DE1_endofpacketvalue_reg[5]_lut_out, QC2__clk0, F1_data_out, , DE1_endofpacketvalue_wr_strobe, , , , );

--DE1_epcs_slave_select_reg[5] is std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|epcs_slave_select_reg[5]

--operation mode is normal

DE1_epcs_slave_select_reg[5]_lut_out = DE1_epcs_slave_select_holding_reg[5];

DE1_epcs_slave_select_reg[5] = DFFEAS(DE1_epcs_slave_select_reg[5]_lut_out, QC2__clk0, F1_data_out, , DE1L142, , , , );

--DE1L135 is std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|p1_data_to_cpu[5]~869

--operation mode is normal

DE1L135 = X1L14 & X1L16 & DE1_epcs_slave_select_reg[5] & !X1L15;

--DE1_rx_holding_reg[5] is std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|rx_holding_reg[5]

--operation mode is normal

DE1_rx_holding_reg[5]_lut_out = DE1_shift_reg[5];

DE1_rx_holding_reg[5] = DFFEAS(DE1_rx_holding_reg[5]_lut_out, QC2__clk0, F1_data_out, , DE1L156, , , , );

--DE1L136 is std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|p1_data_to_cpu[5]~870

--operation mode is normal

DE1L136 = DE1_rx_holding_reg[5] & (X1L15 # !X1L16 # !X1L14);

--DE1L137 is std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|p1_data_to_cpu[5]~871

--operation mode is normal

DE1L137 = DE1L114 & DE1_endofpacketvalue_reg[5] # !DE1L114 & (DE1L135 # DE1L136);

--DE1L192 is std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|transmitting~81

--operation mode is normal

DE1L192 = !DE1_tx_holding_primed & !DE1_transmitting;

--S1_M_shift_rot_result[30] is std_1c20:inst|cpu:the_cpu|M_shift_rot_result[30]

--operation mode is normal

S1_M_shift_rot_result[30] = AMPP_FUNCTION(QC2__clk0, S1_M_shift_rot_result[29], S1_M_shift_rot_result[31], S1L599, S1_M_ctrl_shift_rot_right, F1_data_out, !S1_M_shift_rot_stall);

--S1_E_ctrl_rot_right is std_1c20:inst|cpu:the_cpu|E_ctrl_rot_right

--operation mode is normal

S1_E_ctrl_rot_right = AMPP_FUNCTION(QC2__clk0, S1_D_iw[14], S1L234, S1_D_iw[15], F1_data_out, S1_W_stall);

--S1_E_ctrl_shift_logical is std_1c20:inst|cpu:the_cpu|E_ctrl_shift_logical

--operation mode is normal

S1_E_ctrl_shift_logical = AMPP_FUNCTION(QC2__clk0, S1_D_iw[15], S1L234, S1_D_iw[16], F1_data_out, S1_W_stall);

--Z1_readdata[0] is std_1c20:inst|high_res_timer:the_high_res_timer|readdata[0]

--operation mode is normal

Z1_readdata[0]_lut_out = Z1L157 # Z1L158 # Z1L159;

Z1_readdata[0] = DFFEAS(Z1_readdata[0]_lut_out, QC2__clk0, F1_data_out, , , , , , );

--RB1_readdata[0] is std_1c20:inst|sys_clk_timer:the_sys_clk_timer|readdata[0]

--operation mode is normal

RB1_readdata[0]_lut_out = RB1L158 # RB1L159 # RB1L160;

RB1_readdata[0] = DFFEAS(RB1_readdata[0]_lut_out, QC2__clk0, F1_data_out, , , , , , );

--T1L23 is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[0]~5319

--operation mode is normal

T1L23 = Z1_readdata[0] & (RB1_readdata[0] # !SB1_cpu_data_master_requests_sys_clk_timer_s1) # !Z1_readdata[0] & !AB1_cpu_data_master_requests_high_res_timer_s1 & (RB1_readdata[0] # !SB1_cpu_data_master_requests_sys_clk_timer_s1);

--G1_readdata[0] is std_1c20:inst|button_pio:the_button_pio|readdata[0]

--operation mode is normal

G1_readdata[0]_lut_out = S1_M_alu_result[3] & G1L27 # !S1_M_alu_result[3] & (in_port_to_the_button_pio[0] & !S1_M_alu_result[2]);

G1_readdata[0] = DFFEAS(G1_readdata[0]_lut_out, QC2__clk0, F1_data_out, , , , , , );

--XE1_readdata[0] is std_1c20:inst|uart1:the_uart1|uart1_regs:the_uart1_regs|readdata[0]

--operation mode is normal

XE1_readdata[0]_lut_out = S1_M_alu_result[4] & XE1L15 & XE1_control_reg[0] # !S1_M_alu_result[4] & (XE1L49 # XE1L15 & XE1_control_reg[0]);

XE1_readdata[0] = DFFEAS(XE1_readdata[0]_lut_out, QC2__clk0, F1_data_out, , , , , , );

--T1L24 is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[0]~5320

--operation mode is normal

T1L24 = G1_readdata[0] & (XE1_readdata[0] # !WB1_cpu_data_master_granted_uart1_s1) # !G1_readdata[0] & !H1_cpu_data_master_requests_button_pio_s1 & (XE1_readdata[0] # !WB1_cpu_data_master_granted_uart1_s1);

--HB1_readdata is std_1c20:inst|reconfig_request_pio:the_reconfig_request_pio|readdata

--operation mode is normal

HB1_readdata_lut_out = !S1_M_alu_result[3] & (S1_M_alu_result[2] & HB1_data_dir # !S1_M_alu_result[2] & (A1L20));

HB1_readdata = DFFEAS(HB1_readdata_lut_out, QC2__clk0, F1_data_out, , , , , , );

--T1L25 is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[0]~5321

--operation mode is normal

T1L25 = S1_M_alu_result[5] & HB1_readdata # !S1_M_alu_result[5] & (A1L141) # !JB1L3;

--T1_registered_cpu_data_master_readdata[0] is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|registered_cpu_data_master_readdata[0]

--operation mode is normal

T1_registered_cpu_data_master_readdata[0]_lut_out = T1L243 & T1L273 & (KB1_za_data[0] # !NB1L17);

T1_registered_cpu_data_master_readdata[0] = DFFEAS(T1_registered_cpu_data_master_readdata[0]_lut_out, QC2__clk0, F1_data_out, , , , , , );

--T1L26 is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[0]~5322

--operation mode is normal

T1L26 = T1L25 & (T1_registered_cpu_data_master_readdata[0] # !K1_cpu_data_master_requests_clock_0_in & !CB1_cpu_data_master_requests_jtag_uart_avalon_jtag_slave);

--T1_dbs_8_reg_segment_0[0] is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|dbs_8_reg_segment_0[0]

--operation mode is normal

T1_dbs_8_reg_segment_0[0]_lut_out = Y1_internal_incoming_ext_ram_bus_data[0];

T1_dbs_8_reg_segment_0[0] = DFFEAS(T1_dbs_8_reg_segment_0[0]_lut_out, QC2__clk0, F1_data_out, , T1L294, , , , );

--T1L27 is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[0]~5323

--operation mode is normal

T1L27 = !Y1_internal_incoming_ext_ram_bus_data[0] & (Y1L78 # Y1_cpu_data_master_requests_ext_ram_s1);

--T1L28 is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[0]~5324

--operation mode is normal

T1L28 = T1L27 # !T1_registered_cpu_data_master_readdata[0] & (NB1L17 # N1_cpu_data_master_requests_clock_1_in);

--T1L29 is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[0]~5325

--operation mode is normal

T1L29 = T1L208 & !T1L28 & (T1_dbs_8_reg_segment_0[0] # !Y1_cpu_data_master_requests_ext_flash_s1);

--T1L30 is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[0]~5326

--operation mode is normal

T1L30 = T1L23 & T1L24 & T1L26 & T1L29;

--DE1_data_to_cpu[0] is std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|data_to_cpu[0]

--operation mode is normal

DE1_data_to_cpu[0]_lut_out = !DE1L134 & (DE1L114 & DE1_endofpacketvalue_reg[0] # !DE1L114 & (DE1L131));

DE1_data_to_cpu[0] = DFFEAS(DE1_data_to_cpu[0]_lut_out, QC2__clk0, F1_data_out, , , , , , );

--FE1_q_a[0] is std_1c20:inst|epcs_controller:the_epcs_controller|altsyncram:the_boot_copier_rom|altsyncram_3h31:auto_generated|q_a[0]

--RAM Block Operation Mode: ROM

--Port A Depth: 128, Port A Width: 1

--Port A Logical Depth: 128, Port A Logical Width: 32

--Port A Input: Registered, Port A Output: Un-registered

FE1_q_a[0]_PORT_A_address = BUS(X1L14, X1L15, X1L16, X1L17, X1L18, X1L19, X1L20);

FE1_q_a[0]_PORT_A_address_reg = DFFE(FE1_q_a[0]_PORT_A_address, FE1_q_a[0]_clock_0, , , );

FE1_q_a[0]_clock_0 = QC2__clk0;

FE1_q_a[0]_PORT_A_data_out = MEMORY(, , FE1_q_a[0]_PORT_A_address_reg, , , , , , FE1_q_a[0]_clock_0, , , , , );

FE1_q_a[0] = FE1_q_a[0]_PORT_A_data_out[0];

--U1L123 is std_1c20:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_readdata~2415

--operation mode is normal

U1L123 = W1L1 & DE1_data_to_cpu[0] # !W1L1 & (FE1_q_a[0]);

--WC1L1 is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|readdata[0]~1369

--operation mode is normal

WC1L1 = AMPP_FUNCTION(FD1L3, JD1_internal_monitor_error, CE1_q_a[0], V1L17);

--Z1_readdata[1] is std_1c20:inst|high_res_timer:the_high_res_timer|readdata[1]

--operation mode is normal

Z1_readdata[1]_lut_out = Z1L160 # Z1L161 # Z1L162;

Z1_readdata[1] = DFFEAS(Z1_readdata[1]_lut_out, QC2__clk0, F1_data_out, , , , , , );

--G1_readdata[1] is std_1c20:inst|button_pio:the_button_pio|readdata[1]

--operation mode is normal

G1_readdata[1]_lut_out = S1_M_alu_result[3] & G1L28 # !S1_M_alu_result[3] & (in_port_to_the_button_pio[1] & !S1_M_alu_result[2]);

G1_readdata[1] = DFFEAS(G1_readdata[1]_lut_out, QC2__clk0, F1_data_out, , , , , , );

--T1L32 is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[1]~5328

--operation mode is normal

T1L32 = Z1_readdata[1] & (G1_readdata[1] # !H1_cpu_data_master_requests_button_pio_s1) # !Z1_readdata[1] & !AB1_cpu_data_master_requests_high_res_timer_s1 & (G1_readdata[1] # !H1_cpu_data_master_requests_button_pio_s1);

--XE1_readdata[1] is std_1c20:inst|uart1:the_uart1|uart1_regs:the_uart1_regs|readdata[1]

--operation mode is normal

XE1_readdata[1]_lut_out = !S1_M_alu_result[4] & (S1_M_alu_result[2] & XE1L50 # !S1_M_alu_result[2] & (XE1L51));

XE1_readdata[1] = DFFEAS(XE1_readdata[1]_lut_out, QC2__clk0, F1_data_out, , , , , , );

--RB1_readdata[1] is std_1c20:inst|sys_clk_timer:the_sys_clk_timer|readdata[1]

--operation mode is normal

RB1_readdata[1]_lut_out = RB1L161 # RB1L162 # RB1L163;

RB1_readdata[1] = DFFEAS(RB1_readdata[1]_lut_out, QC2__clk0, F1_data_out, , , , , , );

--T1L33 is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[1]~5329

--operation mode is normal

T1L33 = S1_M_alu_result[6] & XE1_readdata[1] # !S1_M_alu_result[6] & (RB1_readdata[1]) # !SB1L3;

--T1_registered_cpu_data_master_readdata[1] is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|registered_cpu_data_master_readdata[1]

--operation mode is normal

T1_registered_cpu_data_master_readdata[1]_lut_out = T1L244 & T1L274 & (KB1_za_data[1] # !NB1L17);

T1_registered_cpu_data_master_readdata[1] = DFFEAS(T1_registered_cpu_data_master_readdata[1]_lut_out, QC2__clk0, F1_data_out, , , , , , );

--T1L34 is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[1]~5330

--operation mode is normal

T1L34 = T1_registered_cpu_data_master_readdata[1] # !K1_cpu_data_master_requests_clock_0_in & (!CB1L2 # !UB1L9);

--T1L35 is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[1]~5331

--operation mode is normal

T1L35 = T1L209 & (Y1_internal_incoming_ext_ram_bus_data[1] # !Y1L78 & !Y1_cpu_data_master_requests_ext_ram_s1);

--T1_dbs_8_reg_segment_0[1] is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|dbs_8_reg_segment_0[1]

--operation mode is normal

T1_dbs_8_reg_segment_0[1]_lut_out = Y1_internal_incoming_ext_ram_bus_data[1];

T1_dbs_8_reg_segment_0[1] = DFFEAS(T1_dbs_8_reg_segment_0[1]_lut_out, QC2__clk0, F1_data_out, , T1L294, , , , );

--T1L36 is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[1]~5332

--operation mode is normal

T1L36 = T1L34 & T1L35 & (T1_dbs_8_reg_segment_0[1] # !Y1_cpu_data_master_requests_ext_flash_s1);

--T1L37 is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[1]~5333

--operation mode is normal

T1L37 = !T1L39 & (T1_registered_cpu_data_master_readdata[1] # !NB1L17 & !N1_cpu_data_master_requests_clock_1_in);

--T1L38 is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[1]~5334

--operation mode is normal

T1L38 = T1L32 & T1L33 & T1L36 & T1L37;

--DE1_data_to_cpu[1] is std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|data_to_cpu[1]

--operation mode is normal

DE1_data_to_cpu[1]_lut_out = !DE1L134 & (DE1L114 & DE1_endofpacketvalue_reg[1] # !DE1L114 & (DE1L132));

DE1_data_to_cpu[1] = DFFEAS(DE1_data_to_cpu[1]_lut_out, QC2__clk0, F1_data_out, , , , , , );

--FE1_q_a[1] is std_1c20:inst|epcs_controller:the_epcs_controller|altsyncram:the_boot_copier_rom|altsyncram_3h31:auto_generated|q_a[1]

--RAM Block Operation Mode: ROM

--Port A Depth: 128, Port A Width: 1

--Port A Logical Depth: 128, Port A Logical Width: 32

--Port A Input: Registered, Port A Output: Un-registered

FE1_q_a[1]_PORT_A_address = BUS(X1L14, X1L15, X1L16, X1L17, X1L18, X1L19, X1L20);

FE1_q_a[1]_PORT_A_address_reg = DFFE(FE1_q_a[1]_PORT_A_address, FE1_q_a[1]_clock_0, , , );

FE1_q_a[1]_clock_0 = QC2__clk0;

FE1_q_a[1]_PORT_A_data_out = MEMORY(, , FE1_q_a[1]_PORT_A_address_reg, , , , , , FE1_q_a[1]_clock_0, , , , , );

FE1_q_a[1] = FE1_q_a[1]_PORT_A_data_out[0];

--U1L124 is std_1c20:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_readdata~2416

--operation mode is normal

U1L124 = W1L1 & DE1_data_to_cpu[1] # !W1L1 & (FE1_q_a[1]);

--WC1L2 is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|readdata[1]~1371

--operation mode is normal

WC1L2 = AMPP_FUNCTION(FD1L3, JD1_internal_monitor_ready, CE1_q_a[1], V1L17);

--S1_E_wrctl_bstatus is std_1c20:inst|cpu:the_cpu|E_wrctl_bstatus

--operation mode is normal

S1_E_wrctl_bstatus = AMPP_FUNCTION(S1_E_iw[7], S1_E_ctrl_wrctl_inst, S1_E_iw[6], S1_E_iw[8]);

--S1_E_wrctl_estatus is std_1c20:inst|cpu:the_cpu|E_wrctl_estatus

--operation mode is normal

S1_E_wrctl_estatus = AMPP_FUNCTION(S1_E_iw[6], S1_E_ctrl_wrctl_inst, S1_E_iw[7], S1_E_iw[8]);

--FF1_state[11] is sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state[11]

--operation mode is normal

FF1_state[11] = AMPP_FUNCTION(A1L5, FF1_state[10], FF1_state[11], FF1_state[14], VCC, A1L7);

--FF1_state[9] is sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state[9]

--operation mode is normal

FF1_state[9] = AMPP_FUNCTION(A1L5, A1L7, FF1_state[2], VCC);

--FF1_tms_cnt[2] is sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|tms_cnt[2]

--operation mode is normal

FF1_tms_cnt[2] = AMPP_FUNCTION(A1L5, FF1_tms_cnt[2], FF1_tms_cnt[0], FF1_tms_cnt[1], VCC, !A1L7);

--FF1_tms_cnt[1] is sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|tms_cnt[1]

--operation mode is normal

FF1_tms_cnt[1] = AMPP_FUNCTION(A1L5, FF1_tms_cnt[0], FF1_tms_cnt[1], VCC, !A1L7);

--FF1_tms_cnt[0] is sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|tms_cnt[0]

--operation mode is normal

FF1_tms_cnt[0] = AMPP_FUNCTION(A1L5, A1L7, FF1_tms_cnt[0], VCC);

--FF1L19 is sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state~233

--operation mode is normal

FF1L19 = AMPP_FUNCTION(FF1_tms_cnt[2], FF1_tms_cnt[1], FF1_tms_cnt[0]);

--FF1_state[10] is sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state[10]

--operation mode is normal

FF1_state[10] = AMPP_FUNCTION(A1L5, FF1_state[9], A1L7, VCC);

--FF1_state[6] is sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state[6]

--operation mode is normal

FF1_state[6] = AMPP_FUNCTION(A1L5, FF1_state[5], FF1_state[6], VCC, A1L7);

--CF1_WORD_SR[2] is sld_hub:sld_hub_inst|sld_rom_sr:HUB_INFO_REG|WORD_SR[2]

--operation mode is normal

CF1_WORD_SR[2] = AMPP_FUNCTION(A1L5, CF1L12, CF1L13, CF1_WORD_SR[3], CF1_word_counter[2], VCC, CF1_clear_signal, FF1_state[4], CF1L21);

--CF1L15 is sld_hub:sld_hub_inst|sld_rom_sr:HUB_INFO_REG|Mux2~28

--operation mode is normal

CF1L15 = AMPP_FUNCTION(CF1_word_counter[0], CF1_word_counter[1], CF1_word_counter[2], CF1_word_counter[3]);

--CF1L1 is sld_hub:sld_hub_inst|sld_rom_sr:HUB_INFO_REG|Add0~72

--operation mode is normal

CF1L1 = AMPP_FUNCTION(CF1_word_counter[4], CF1L9);

--CF1L11 is sld_hub:sld_hub_inst|sld_rom_sr:HUB_INFO_REG|Equal0~43

--operation mode is normal

CF1L11 = AMPP_FUNCTION(CF1_word_counter[4], CF1_word_counter[0], CF1_word_counter[1], CF1_word_counter[2]);

--CF1L20 is sld_hub:sld_hub_inst|sld_rom_sr:HUB_INFO_REG|word_counter[0]~1278

--operation mode is normal

CF1L20 = AMPP_FUNCTION(CF1_clear_signal, FF1_state[3], C1_jtag_debug_mode_usr0, FF1_state[4]);

--CF1L2 is sld_hub:sld_hub_inst|sld_rom_sr:HUB_INFO_REG|Add0~74

--operation mode is arithmetic

CF1L2 = AMPP_FUNCTION(CF1_word_counter[0]);

--CF1L3 is sld_hub:sld_hub_inst|sld_rom_sr:HUB_INFO_REG|Add0~75

--operation mode is arithmetic

CF1L3 = AMPP_FUNCTION(CF1_word_counter[0]);

--CF1L4 is sld_hub:sld_hub_inst|sld_rom_sr:HUB_INFO_REG|Add0~76

--operation mode is arithmetic

CF1L4 = AMPP_FUNCTION(CF1_word_counter[1], CF1L3);

--CF1L5 is sld_hub:sld_hub_inst|sld_rom_sr:HUB_INFO_REG|Add0~77

--operation mode is arithmetic

CF1L5 = AMPP_FUNCTION(CF1_word_counter[1], CF1L3);

--CF1L6 is sld_hub:sld_hub_inst|sld_rom_sr:HUB_INFO_REG|Add0~78

--operation mode is arithmetic

CF1L6 = AMPP_FUNCTION(CF1_word_counter[2], CF1L5);

--CF1L7 is sld_hub:sld_hub_inst|sld_rom_sr:HUB_INFO_REG|Add0~79

--operation mode is arithmetic

CF1L7 = AMPP_FUNCTION(CF1_word_counter[2], CF1L5);

--CF1L8 is sld_hub:sld_hub_inst|sld_rom_sr:HUB_INFO_REG|Add0~80

--operation mode is arithmetic

CF1L8 = AMPP_FUNCTION(CF1_word_counter[3], CF1L7);

--CF1L9 is sld_hub:sld_hub_inst|sld_rom_sr:HUB_INFO_REG|Add0~81

--operation mode is arithmetic

CF1L9 = AMPP_FUNCTION(CF1_word_counter[3], CF1L7);

--SD1L120Q is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|ir_out[1]~reg0

--operation mode is normal

SD1L120Q = AMPP_FUNCTION(A1L5, S1_hbreak_enabled, !C1_CLR_SIGNAL);

--GD1_break_readreg[0] is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_break:the_cpu_nios2_oci_break|break_readreg[0]

--operation mode is normal

GD1_break_readreg[0] = AMPP_FUNCTION(QC2__clk0, SD1_internal_jdo1[0], SD1_internal_jdo1[36], SD1_internal_jdo1[37], SD1L189, !C1_CLR_SIGNAL, SD1L189);

--SD1L131 is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|Mux39~14

--operation mode is normal

SD1L131 = AMPP_FUNCTION(RD1_internal_MonDReg[0], SD1_ir[1], GD1_break_readreg[0], SD1_ir[0]);

--SD1_sr[2] is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|sr[2]

--operation mode is normal

SD1_sr[2] = AMPP_FUNCTION(A1L5, SD1L130, SD1_sr[3], SD1L144, SD1L142, !C1_CLR_SIGNAL, SD1L6);

--SD1L122 is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|Mux0~35

--operation mode is normal

SD1L122 = AMPP_FUNCTION(BF5_Q[0], BF5_Q[1]);

--SD1_internal_jdo1[25] is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|internal_jdo1[25]

--operation mode is normal

SD1_internal_jdo1[25] = AMPP_FUNCTION(A1L8, SD1_sr[25], VCC, SD1L145);

--JD1L7 is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_debug:the_cpu_nios2_oci_debug|internal_monitor_ready~121

--operation mode is normal

JD1L7 = AMPP_FUNCTION(JD1_internal_monitor_ready, SD1_internal_jdo1[34], SD1L190, SD1_internal_jdo1[25]);

--SD1_st_shiftdr is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|st_shiftdr

--operation mode is normal

SD1_st_shiftdr = AMPP_FUNCTION(A1L5, SD1L144, !A1L8);

--GE1_rvalid0 is std_1c20:inst|jtag_uart:the_jtag_uart|alt_jtag_atlantic:jtag_uart_alt_jtag_atlantic|rvalid0

--operation mode is normal

GE1_rvalid0 = AMPP_FUNCTION(QC2__clk0, GE1L19, GE1_user_saw_rvalid, GE1L2, GE1_read_req, F1_data_out);

--GE1L53 is std_1c20:inst|jtag_uart:the_jtag_uart|alt_jtag_atlantic:jtag_uart_alt_jtag_atlantic|td_shift[9]~3552

--operation mode is normal

GE1L53 = AMPP_FUNCTION(FF1_state[3], BF4_Q[0], FF1_state[4]);

--GE1_write_stalled is std_1c20:inst|jtag_uart:the_jtag_uart|alt_jtag_atlantic:jtag_uart_alt_jtag_atlantic|write_stalled

--operation mode is normal

GE1_write_stalled = AMPP_FUNCTION(A1L5, GE1_td_shift[10], GE1_write_stalled, BB1_t_dav, altera_internal_jtag, !C1_CLR_SIGNAL, GE1L72);

--GE1_td_shift[2] is std_1c20:inst|jtag_uart:the_jtag_uart|alt_jtag_atlantic:jtag_uart_alt_jtag_atlantic|td_shift[2]

--operation mode is normal

GE1_td_shift[2] = AMPP_FUNCTION(A1L5, GE1L53, GE1L63, GE1L56, !C1_CLR_SIGNAL, GE1L52);

--GE1L54 is std_1c20:inst|jtag_uart:the_jtag_uart|alt_jtag_atlantic:jtag_uart_alt_jtag_atlantic|td_shift[9]~3553

--operation mode is normal

GE1L54 = AMPP_FUNCTION(GE1_write_stalled, GE1_td_shift[2], GE1_count[9]);

--GE1_count[8] is std_1c20:inst|jtag_uart:the_jtag_uart|alt_jtag_atlantic:jtag_uart_alt_jtag_atlantic|count[8]

--operation mode is normal

GE1_count[8] = AMPP_FUNCTION(A1L5, FF1_state[4], GE1_count[7], !C1_CLR_SIGNAL, GE1L52);

--GE1L55 is std_1c20:inst|jtag_uart:the_jtag_uart|alt_jtag_atlantic:jtag_uart_alt_jtag_atlantic|td_shift[9]~3555

--operation mode is normal

GE1L55 = AMPP_FUNCTION(FF1_state[4], GE1_count[8], GE1L66, BF4_Q[0]);

--GE1L36 is std_1c20:inst|jtag_uart:the_jtag_uart|alt_jtag_atlantic:jtag_uart_alt_jtag_atlantic|state~198

--operation mode is normal

GE1L36 = AMPP_FUNCTION(FF1_state[3], BF4_Q[0], GE1_state);

--GE1_count[0] is std_1c20:inst|jtag_uart:the_jtag_uart|alt_jtag_atlantic:jtag_uart_alt_jtag_atlantic|count[0]

--operation mode is normal

GE1_count[0] = AMPP_FUNCTION(A1L5, FF1_state[4], GE1_count[9], !C1_CLR_SIGNAL, GE1L52);

--GE1_td_shift[10] is std_1c20:inst|jtag_uart:the_jtag_uart|alt_jtag_atlantic:jtag_uart_alt_jtag_atlantic|td_shift[10]

--operation mode is normal

GE1_td_shift[10] = AMPP_FUNCTION(A1L5, C1L11, !C1_CLR_SIGNAL, GE1L52);

--GE1_rdata[7] is std_1c20:inst|jtag_uart:the_jtag_uart|alt_jtag_atlantic:jtag_uart_alt_jtag_atlantic|rdata[7]

--operation mode is normal

GE1_rdata[7] = AMPP_FUNCTION(QC2__clk0, SE1_q_b[7], F1_data_out, GE1L18);

--GE1L69 is std_1c20:inst|jtag_uart:the_jtag_uart|alt_jtag_atlantic:jtag_uart_alt_jtag_atlantic|user_saw_rvalid~148

--operation mode is normal

GE1L69 = AMPP_FUNCTION(FF1_state[4], GE1_state, GE1L1, BF4_Q[0]);

--BF6_Q[0] is sld_hub:sld_hub_inst|sld_dffex:\GEN_SHADOW_IRF:2:S_IRF|Q[0]

--operation mode is normal

BF6_Q[0] = AMPP_FUNCTION(A1L5, BF3_Q[0], BF6_Q[0], BF8_Q[1], C1L9, !C1_CLR_SIGNAL);

--BF4L3 is sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:2:IRF|Q[0]~207

--operation mode is normal

BF4L3 = AMPP_FUNCTION(BF6_Q[0], BF3_Q[0], BF2_Q[0]);

--C1L27 is sld_hub:sld_hub_inst|IRF_ENABLE[2]~137

--operation mode is normal

C1L27 = AMPP_FUNCTION(C1L9, C1L25, BF8_Q[1], BF2_Q[0]);

--S1_E_src2_prelim[30] is std_1c20:inst|cpu:the_cpu|E_src2_prelim[30]

--operation mode is normal

S1_E_src2_prelim[30] = AMPP_FUNCTION(QC2__clk0, DD1_q_b[30], S1_W_wr_data[30], S1L1372, S1L396, F1_data_out, S1L392, S1_W_stall);

--S1L1370 is std_1c20:inst|cpu:the_cpu|M_wr_data_unfiltered[30]~3703

--operation mode is normal

S1L1370 = AMPP_FUNCTION(S1_M_shift_rot_result[30], S1_M_ctrl_shift_rot);

--S1_av_ld_data_aligned_or_div[30] is std_1c20:inst|cpu:the_cpu|av_ld_data_aligned_or_div[30]

--operation mode is normal

S1_av_ld_data_aligned_or_div[30] = AMPP_FUNCTION(QC2__clk0, S1_d_readdata_d1[30], S1_M_ctrl_ld_signed, S1L174, S1_M_iw[4], F1_data_out);

--S1_M_alu_result[30] is std_1c20:inst|cpu:the_cpu|M_alu_result[30]

--operation mode is normal

S1_M_alu_result[30] = AMPP_FUNCTION(QC2__clk0, S1L80, S1L538, A1L276, S1_E_ctrl_dst_data_sel_logic_result, F1_data_out, S1_E_ctrl_dst_data_sel_cmp, S1_E_ctrl_rdctl_inst, S1_W_stall);

--S1L1371 is std_1c20:inst|cpu:the_cpu|M_wr_data_unfiltered[30]~3704

--operation mode is normal

S1L1371 = AMPP_FUNCTION(S1_av_ld_data_aligned_or_div[30], S1_M_alu_result[30], S1_av_ld_or_div_done, S1_M_ctrl_shift_rot);

--S1L740 is std_1c20:inst|cpu:the_cpu|E_src2_reg[30]~476

--operation mode is normal

S1L740 = AMPP_FUNCTION(S1_E_src2_prelim[30], S1_E_src2_hazard_M, S1L1370, S1L1371);

--S1_E_src2_prelim[29] is std_1c20:inst|cpu:the_cpu|E_src2_prelim[29]

--operation mode is normal

S1_E_src2_prelim[29] = AMPP_FUNCTION(QC2__clk0, DD1_q_b[29], S1_W_wr_data[29], S1L1369, S1L396, F1_data_out, S1L392, S1_W_stall);

--S1_M_shift_rot_result[29] is std_1c20:inst|cpu:the_cpu|M_shift_rot_result[29]

--operation mode is normal

S1_M_shift_rot_result[29] = AMPP_FUNCTION(QC2__clk0, S1_M_shift_rot_result[28], S1_M_shift_rot_result[30], S1L598, S1_M_ctrl_shift_rot_right, F1_data_out, !S1_M_shift_rot_stall);

--S1L1367 is std_1c20:inst|cpu:the_cpu|M_wr_data_unfiltered[29]~3705

--operation mode is normal

S1L1367 = AMPP_FUNCTION(S1_M_shift_rot_result[29], S1_M_ctrl_shift_rot);

--S1_av_ld_data_aligned_or_div[29] is std_1c20:inst|cpu:the_cpu|av_ld_data_aligned_or_div[29]

--operation mode is normal

S1_av_ld_data_aligned_or_div[29] = AMPP_FUNCTION(QC2__clk0, S1_d_readdata_d1[29], S1_M_ctrl_ld_signed, S1L174, S1_M_iw[4], F1_data_out);

--S1_M_alu_result[29] is std_1c20:inst|cpu:the_cpu|M_alu_result[29]

--operation mode is normal

S1_M_alu_result[29] = AMPP_FUNCTION(QC2__clk0, S1L81, S1L537, A1L276, S1_E_ctrl_dst_data_sel_logic_result, F1_data_out, S1_E_ctrl_dst_data_sel_cmp, S1_E_ctrl_rdctl_inst, S1_W_stall);

--S1L1368 is std_1c20:inst|cpu:the_cpu|M_wr_data_unfiltered[29]~3706

--operation mode is normal

S1L1368 = AMPP_FUNCTION(S1_av_ld_data_aligned_or_div[29], S1_M_alu_result[29], S1_av_ld_or_div_done, S1_M_ctrl_shift_rot);

--S1L739 is std_1c20:inst|cpu:the_cpu|E_src2_reg[29]~477

--operation mode is normal

S1L739 = AMPP_FUNCTION(S1_E_src2_prelim[29], S1_E_src2_hazard_M, S1L1367, S1L1368);

--S1_E_src2_prelim[28] is std_1c20:inst|cpu:the_cpu|E_src2_prelim[28]

--operation mode is normal

S1_E_src2_prelim[28] = AMPP_FUNCTION(QC2__clk0, DD1_q_b[28], S1_W_wr_data[28], S1L1366, S1L396, F1_data_out, S1L392, S1_W_stall);

--S1L1364 is std_1c20:inst|cpu:the_cpu|M_wr_data_unfiltered[28]~3707

--operation mode is normal

S1L1364 = AMPP_FUNCTION(S1_M_shift_rot_result[28], S1_M_ctrl_shift_rot);

--S1_av_ld_data_aligned_or_div[28] is std_1c20:inst|cpu:the_cpu|av_ld_data_aligned_or_div[28]

--operation mode is normal

S1_av_ld_data_aligned_or_div[28] = AMPP_FUNCTION(QC2__clk0, S1_d_readdata_d1[28], S1_M_ctrl_ld_signed, S1L174, S1_M_iw[4], F1_data_out);

--S1_M_alu_result[28] is std_1c20:inst|cpu:the_cpu|M_alu_result[28]

--operation mode is normal

S1_M_alu_result[28] = AMPP_FUNCTION(QC2__clk0, S1L82, S1L536, A1L276, S1_E_ctrl_dst_data_sel_logic_result, F1_data_out, S1_E_ctrl_dst_data_sel_cmp, S1_E_ctrl_rdctl_inst, S1_W_stall);

--S1L1365 is std_1c20:inst|cpu:the_cpu|M_wr_data_unfiltered[28]~3708

--operation mode is normal

S1L1365 = AMPP_FUNCTION(S1_av_ld_data_aligned_or_div[28], S1_M_alu_result[28], S1_av_ld_or_div_done, S1_M_ctrl_shift_rot);

--S1L738 is std_1c20:inst|cpu:the_cpu|E_src2_reg[28]~478

--operation mode is normal

S1L738 = AMPP_FUNCTION(S1_E_src2_prelim[28], S1_E_src2_hazard_M, S1L1364, S1L1365);

--S1_E_src2_prelim[27] is std_1c20:inst|cpu:the_cpu|E_src2_prelim[27]

--operation mode is normal

S1_E_src2_prelim[27] = AMPP_FUNCTION(QC2__clk0, DD1_q_b[27], S1_W_wr_data[27], S1L1363, S1L396, F1_data_out, S1L392, S1_W_stall);

--S1L737 is std_1c20:inst|cpu:the_cpu|E_src2_reg[27]~479

--operation mode is normal

S1L737 = AMPP_FUNCTION(S1_E_src2_prelim[27], S1_E_src2_hazard_M, S1L1361, S1L1362);

--KB1L65 is std_1c20:inst|sdram:the_sdram|active_data[30]~6664

--operation mode is normal

KB1L65 = F1_data_out & KB1L395 & (KB1L423 # !KB1L393);

--KB1L66 is std_1c20:inst|sdram:the_sdram|active_data[30]~6665

--operation mode is normal

KB1L66 = KB1_m_state[0] & (KB1L393 & !KB1L554 # !KB1L393 & (KB1L396)) # !KB1_m_state[0] & (KB1L393);

--S1_E_iw[18] is std_1c20:inst|cpu:the_cpu|E_iw[18]

--operation mode is normal

S1_E_iw[18] = AMPP_FUNCTION(QC2__clk0, S1_D_iw[18], F1_data_out, S1_W_stall);

--S1_E_ctrl_jmp_direct is std_1c20:inst|cpu:the_cpu|E_ctrl_jmp_direct

--operation mode is normal

S1_E_ctrl_jmp_direct = AMPP_FUNCTION(QC2__clk0, S1L202, F1_data_out, S1_W_stall);

--S1L50 is std_1c20:inst|cpu:the_cpu|A_WE_StdLogicVector~14130

--operation mode is normal

S1L50 = AMPP_FUNCTION(S1_E_iw[18], S1_E_ctrl_jmp_direct, S1_E_extra_pc[12], S1L1271);

--S1_E_pc[12] is std_1c20:inst|cpu:the_cpu|E_pc[12]

--operation mode is normal

S1_E_pc[12] = AMPP_FUNCTION(QC2__clk0, S1_D_pc[12], F1_data_out, S1_W_stall);

--S1_E_ctrl_jmp_indirect is std_1c20:inst|cpu:the_cpu|E_ctrl_jmp_indirect

--operation mode is normal

S1_E_ctrl_jmp_indirect = AMPP_FUNCTION(QC2__clk0, S1L760, S1L763, S1L232, S1_D_iw[12], F1_data_out, S1_W_stall);

--S1_E_iw[22] is std_1c20:inst|cpu:the_cpu|E_iw[22]

--operation mode is normal

S1_E_iw[22] = AMPP_FUNCTION(QC2__clk0, S1_D_iw[22], F1_data_out, S1_W_stall);

--S1L51 is std_1c20:inst|cpu:the_cpu|A_WE_StdLogicVector~14131

--operation mode is normal

S1L51 = AMPP_FUNCTION(S1_E_iw[22], S1_E_ctrl_jmp_direct, S1_E_extra_pc[16], S1L1271);

--S1_E_pc[16] is std_1c20:inst|cpu:the_cpu|E_pc[16]

--operation mode is normal

S1_E_pc[16] = AMPP_FUNCTION(QC2__clk0, S1_D_pc[16], F1_data_out, S1_W_stall);

--S1_ic_tag_clr_valid_bits_nxt is std_1c20:inst|cpu:the_cpu|ic_tag_clr_valid_bits_nxt

--operation mode is normal

S1_ic_tag_clr_valid_bits_nxt = AMPP_FUNCTION(S1L1006, S1L248, S1L249, S1_reset_d1);

--S1_E_iw[9] is std_1c20:inst|cpu:the_cpu|E_iw[9]

--operation mode is normal

S1_E_iw[9] = AMPP_FUNCTION(QC2__clk0, S1_D_iw[9], F1_data_out, S1_W_stall);

--S1L52 is std_1c20:inst|cpu:the_cpu|A_WE_StdLogicVector~14132

--operation mode is normal

S1L52 = AMPP_FUNCTION(S1_E_iw[9], S1_E_extra_pc[3], S1L1271, S1_E_ctrl_jmp_direct);

--S1_E_pc[3] is std_1c20:inst|cpu:the_cpu|E_pc[3]

--operation mode is normal

S1_E_pc[3] = AMPP_FUNCTION(QC2__clk0, S1_D_pc[3], F1_data_out, S1_W_stall);

--S1_E_iw[10] is std_1c20:inst|cpu:the_cpu|E_iw[10]

--operation mode is normal

S1_E_iw[10] = AMPP_FUNCTION(QC2__clk0, S1_D_iw[10], F1_data_out, S1_W_stall);

--S1L53 is std_1c20:inst|cpu:the_cpu|A_WE_StdLogicVector~14133

--operation mode is normal

S1L53 = AMPP_FUNCTION(S1_E_iw[10], S1_E_ctrl_jmp_direct, S1_E_extra_pc[4], S1L1271);

--S1_E_pc[4] is std_1c20:inst|cpu:the_cpu|E_pc[4]

--operation mode is normal

S1_E_pc[4] = AMPP_FUNCTION(QC2__clk0, S1_D_pc[4], F1_data_out, S1_W_stall);

--S1L54 is std_1c20:inst|cpu:the_cpu|A_WE_StdLogicVector~14134

--operation mode is normal

S1L54 = AMPP_FUNCTION(S1_E_iw[11], S1_E_ctrl_jmp_direct, S1_E_extra_pc[5], S1L1271);

--S1_E_pc[5] is std_1c20:inst|cpu:the_cpu|E_pc[5]

--operation mode is normal

S1_E_pc[5] = AMPP_FUNCTION(QC2__clk0, S1_D_pc[5], F1_data_out, S1_W_stall);

--S1L55 is std_1c20:inst|cpu:the_cpu|A_WE_StdLogicVector~14135

--operation mode is normal

S1L55 = AMPP_FUNCTION(S1_E_iw[12], S1_E_ctrl_jmp_direct, S1_E_extra_pc[6], S1L1271);

--S1_E_pc[6] is std_1c20:inst|cpu:the_cpu|E_pc[6]

--operation mode is normal

S1_E_pc[6] = AMPP_FUNCTION(QC2__clk0, S1_D_pc[6], F1_data_out, S1_W_stall);

--S1L56 is std_1c20:inst|cpu:the_cpu|A_WE_StdLogicVector~14136

--operation mode is normal

S1L56 = AMPP_FUNCTION(S1_E_iw[13], S1_E_ctrl_jmp_direct, S1_E_extra_pc[7], S1L1271);

--S1_E_pc[7] is std_1c20:inst|cpu:the_cpu|E_pc[7]

--operation mode is normal

S1_E_pc[7] = AMPP_FUNCTION(QC2__clk0, S1_D_pc[7], F1_data_out, S1_W_stall);

--S1L57 is std_1c20:inst|cpu:the_cpu|A_WE_StdLogicVector~14137

--operation mode is normal

S1L57 = AMPP_FUNCTION(S1_E_iw[14], S1_E_ctrl_jmp_direct, S1_E_extra_pc[8], S1L1271);

--S1_E_pc[8] is std_1c20:inst|cpu:the_cpu|E_pc[8]

--operation mode is normal

S1_E_pc[8] = AMPP_FUNCTION(QC2__clk0, S1_D_pc[8], F1_data_out, S1_W_stall);

--S1L58 is std_1c20:inst|cpu:the_cpu|A_WE_StdLogicVector~14138

--operation mode is normal

S1L58 = AMPP_FUNCTION(S1_E_iw[15], S1_E_ctrl_jmp_direct, S1_E_extra_pc[9], S1L1271);

--S1_E_pc[9] is std_1c20:inst|cpu:the_cpu|E_pc[9]

--operation mode is normal

S1_E_pc[9] = AMPP_FUNCTION(QC2__clk0, S1_D_pc[9], F1_data_out, S1_W_stall);

--S1_E_iw[26] is std_1c20:inst|cpu:the_cpu|E_iw[26]

--operation mode is normal

S1_E_iw[26] = AMPP_FUNCTION(QC2__clk0, S1_D_iw[26], F1_data_out, S1_W_stall);

--S1L59 is std_1c20:inst|cpu:the_cpu|A_WE_StdLogicVector~14139

--operation mode is normal

S1L59 = AMPP_FUNCTION(S1_E_iw[26], S1_E_ctrl_jmp_direct, S1_E_extra_pc[20], S1L1271);

--S1_E_pc[20] is std_1c20:inst|cpu:the_cpu|E_pc[20]

--operation mode is normal

S1_E_pc[20] = AMPP_FUNCTION(QC2__clk0, S1_D_pc[20], F1_data_out, S1_W_stall);

--S1_E_iw[25] is std_1c20:inst|cpu:the_cpu|E_iw[25]

--operation mode is normal

S1_E_iw[25] = AMPP_FUNCTION(QC2__clk0, S1_D_iw[25], F1_data_out, S1_W_stall);

--S1L60 is std_1c20:inst|cpu:the_cpu|A_WE_StdLogicVector~14140

--operation mode is normal

S1L60 = AMPP_FUNCTION(S1_E_iw[25], S1_E_ctrl_jmp_direct, S1_E_extra_pc[19], S1L1271);

--S1_E_pc[19] is std_1c20:inst|cpu:the_cpu|E_pc[19]

--operation mode is normal

S1_E_pc[19] = AMPP_FUNCTION(QC2__clk0, S1_D_pc[19], F1_data_out, S1_W_stall);

--S1_E_iw[24] is std_1c20:inst|cpu:the_cpu|E_iw[24]

--operation mode is normal

S1_E_iw[24] = AMPP_FUNCTION(QC2__clk0, S1_D_iw[24], F1_data_out, S1_W_stall);

--S1L61 is std_1c20:inst|cpu:the_cpu|A_WE_StdLogicVector~14141

--operation mode is normal

S1L61 = AMPP_FUNCTION(S1_E_extra_pc[18], S1_E_ctrl_break);

--S1L62 is std_1c20:inst|cpu:the_cpu|A_WE_StdLogicVector~14142

--operation mode is normal

S1L62 = AMPP_FUNCTION(S1_E_iw[24], S1_E_ctrl_jmp_direct, S1L61, S1_E_ctrl_exception);

--S1_E_pc[18] is std_1c20:inst|cpu:the_cpu|E_pc[18]

--operation mode is normal

S1_E_pc[18] = AMPP_FUNCTION(QC2__clk0, S1_D_pc[18], F1_data_out, S1_W_stall);

--S1_E_iw[23] is std_1c20:inst|cpu:the_cpu|E_iw[23]

--operation mode is normal

S1_E_iw[23] = AMPP_FUNCTION(QC2__clk0, S1_D_iw[23], F1_data_out, S1_W_stall);

--S1L63 is std_1c20:inst|cpu:the_cpu|A_WE_StdLogicVector~14143

--operation mode is normal

S1L63 = AMPP_FUNCTION(S1_E_iw[23], S1_E_ctrl_jmp_direct, S1_E_extra_pc[17], S1L1271);

--S1_E_pc[17] is std_1c20:inst|cpu:the_cpu|E_pc[17]

--operation mode is normal

S1_E_pc[17] = AMPP_FUNCTION(QC2__clk0, S1_D_pc[17], F1_data_out, S1_W_stall);

--S1_E_iw[27] is std_1c20:inst|cpu:the_cpu|E_iw[27]

--operation mode is normal

S1_E_iw[27] = AMPP_FUNCTION(QC2__clk0, S1_D_iw[27], F1_data_out, S1_W_stall);

--S1L64 is std_1c20:inst|cpu:the_cpu|A_WE_StdLogicVector~14144

--operation mode is normal

S1L64 = AMPP_FUNCTION(S1_E_iw[27], S1_E_ctrl_jmp_direct, S1_E_extra_pc[21], S1L1271);

--S1_E_pc[21] is std_1c20:inst|cpu:the_cpu|E_pc[21]

--operation mode is normal

S1_E_pc[21] = AMPP_FUNCTION(QC2__clk0, S1_D_pc[21], F1_data_out, S1_W_stall);

--S1_E_iw[20] is std_1c20:inst|cpu:the_cpu|E_iw[20]

--operation mode is normal

S1_E_iw[20] = AMPP_FUNCTION(QC2__clk0, S1_D_iw[20], F1_data_out, S1_W_stall);

--S1L65 is std_1c20:inst|cpu:the_cpu|A_WE_StdLogicVector~14145

--operation mode is normal

S1L65 = AMPP_FUNCTION(S1_E_iw[20], S1_E_ctrl_jmp_direct, S1_E_extra_pc[14], S1L1271);

--S1_E_pc[14] is std_1c20:inst|cpu:the_cpu|E_pc[14]

--operation mode is normal

S1_E_pc[14] = AMPP_FUNCTION(QC2__clk0, S1_D_pc[14], F1_data_out, S1_W_stall);

--S1_E_iw[17] is std_1c20:inst|cpu:the_cpu|E_iw[17]

--operation mode is normal

S1_E_iw[17] = AMPP_FUNCTION(QC2__clk0, S1_D_iw[17], F1_data_out, S1_W_stall);

--S1L66 is std_1c20:inst|cpu:the_cpu|A_WE_StdLogicVector~14146

--operation mode is normal

S1L66 = AMPP_FUNCTION(S1_E_iw[17], S1_E_ctrl_jmp_direct, S1_E_extra_pc[11], S1L1271);

--S1_E_pc[11] is std_1c20:inst|cpu:the_cpu|E_pc[11]

--operation mode is normal

S1_E_pc[11] = AMPP_FUNCTION(QC2__clk0, S1_D_pc[11], F1_data_out, S1_W_stall);

--S1_E_iw[28] is std_1c20:inst|cpu:the_cpu|E_iw[28]

--operation mode is normal

S1_E_iw[28] = AMPP_FUNCTION(QC2__clk0, S1_D_iw[28], F1_data_out, S1_W_stall);

--S1L67 is std_1c20:inst|cpu:the_cpu|A_WE_StdLogicVector~14147

--operation mode is normal

S1L67 = AMPP_FUNCTION(S1_E_extra_pc[22], S1_E_ctrl_break);

--S1L68 is std_1c20:inst|cpu:the_cpu|A_WE_StdLogicVector~14148

--operation mode is normal

S1L68 = AMPP_FUNCTION(S1_E_iw[28], S1_E_ctrl_exception, S1L67, S1_E_ctrl_jmp_direct);

--S1_E_pc[22] is std_1c20:inst|cpu:the_cpu|E_pc[22]

--operation mode is normal

S1_E_pc[22] = AMPP_FUNCTION(QC2__clk0, S1_D_pc[22], F1_data_out, S1_W_stall);

--S1_E_iw[29] is std_1c20:inst|cpu:the_cpu|E_iw[29]

--operation mode is normal

S1_E_iw[29] = AMPP_FUNCTION(QC2__clk0, S1_D_iw[29], F1_data_out, S1_W_stall);

--S1L69 is std_1c20:inst|cpu:the_cpu|A_WE_StdLogicVector~14149

--operation mode is normal

S1L69 = AMPP_FUNCTION(S1_E_extra_pc[23], S1_E_ctrl_break);

--S1L70 is std_1c20:inst|cpu:the_cpu|A_WE_StdLogicVector~14150

--operation mode is normal

S1L70 = AMPP_FUNCTION(S1_E_iw[29], S1_E_ctrl_jmp_direct, S1L69, S1_E_ctrl_exception);

--S1_E_pc[23] is std_1c20:inst|cpu:the_cpu|E_pc[23]

--operation mode is normal

S1_E_pc[23] = AMPP_FUNCTION(QC2__clk0, S1_D_pc[23], F1_data_out, S1_W_stall);

--S1L71 is std_1c20:inst|cpu:the_cpu|A_WE_StdLogicVector~14151

--operation mode is normal

S1L71 = AMPP_FUNCTION(S1_E_extra_pc[15], S1_E_ctrl_break);

--S1L72 is std_1c20:inst|cpu:the_cpu|A_WE_StdLogicVector~14152

--operation mode is normal

S1L72 = AMPP_FUNCTION(S1_E_iw[21], S1_E_ctrl_jmp_direct, S1L71, S1_E_ctrl_exception);

--S1_E_pc[15] is std_1c20:inst|cpu:the_cpu|E_pc[15]

--operation mode is normal

S1_E_pc[15] = AMPP_FUNCTION(QC2__clk0, S1_D_pc[15], F1_data_out, S1_W_stall);

--S1_E_iw[19] is std_1c20:inst|cpu:the_cpu|E_iw[19]

--operation mode is normal

S1_E_iw[19] = AMPP_FUNCTION(QC2__clk0, S1_D_iw[19], F1_data_out, S1_W_stall);

--S1L73 is std_1c20:inst|cpu:the_cpu|A_WE_StdLogicVector~14153

--operation mode is normal

S1L73 = AMPP_FUNCTION(S1_E_iw[19], S1_E_ctrl_jmp_direct, S1_E_extra_pc[13], S1L1271);

--S1_E_pc[13] is std_1c20:inst|cpu:the_cpu|E_pc[13]

--operation mode is normal

S1_E_pc[13] = AMPP_FUNCTION(QC2__clk0, S1_D_pc[13], F1_data_out, S1_W_stall);

--S1L74 is std_1c20:inst|cpu:the_cpu|A_WE_StdLogicVector~14154

--operation mode is normal

S1L74 = AMPP_FUNCTION(S1_E_iw[16], S1_E_ctrl_jmp_direct, S1_E_extra_pc[10], S1L1271);

--S1_E_pc[10] is std_1c20:inst|cpu:the_cpu|E_pc[10]

--operation mode is normal

S1_E_pc[10] = AMPP_FUNCTION(QC2__clk0, S1_D_pc[10], F1_data_out, S1_W_stall);

--S1L1038 is std_1c20:inst|cpu:the_cpu|ic_fill_valid_bits_nxt[5]~321

--operation mode is normal

S1L1038 = AMPP_FUNCTION(S1L987, S1L990, S1L989, S1L988);

--S1L1042 is std_1c20:inst|cpu:the_cpu|ic_tag_clr_valid_bits_nxt~34

--operation mode is normal

S1L1042 = AMPP_FUNCTION(S1_M_valid_from_E, S1_M_ctrl_invalidate_i, S1_reset_d1);

--S1_ic_fill_valid_bits_en is std_1c20:inst|cpu:the_cpu|ic_fill_valid_bits_en

--operation mode is normal

S1_ic_fill_valid_bits_en = AMPP_FUNCTION(S1L1042, S1L248, S1L249, S1L986);

--S1L75 is std_1c20:inst|cpu:the_cpu|A_WE_StdLogicVector~14155

--operation mode is normal

S1L75 = AMPP_FUNCTION(S1_E_iw[8], S1_E_ctrl_jmp_direct, S1_E_extra_pc[2], S1L1271);

--S1_E_pc[2] is std_1c20:inst|cpu:the_cpu|E_pc[2]

--operation mode is normal

S1_E_pc[2] = AMPP_FUNCTION(QC2__clk0, S1_D_pc[2], F1_data_out, S1_W_stall);

--S1L1036 is std_1c20:inst|cpu:the_cpu|ic_fill_valid_bits_nxt[3]~323

--operation mode is normal

S1L1036 = AMPP_FUNCTION(S1L988, S1L987, S1L990, S1L989);

--S1L76 is std_1c20:inst|cpu:the_cpu|A_WE_StdLogicVector~14156

--operation mode is normal

S1L76 = AMPP_FUNCTION(S1_E_iw[7], S1_E_ctrl_jmp_direct, S1_E_extra_pc[1], S1L1271);

--S1_E_pc[1] is std_1c20:inst|cpu:the_cpu|E_pc[1]

--operation mode is normal

S1_E_pc[1] = AMPP_FUNCTION(QC2__clk0, S1_D_pc[1], F1_data_out, S1_W_stall);

--S1L1034 is std_1c20:inst|cpu:the_cpu|ic_fill_valid_bits_nxt[1]~325

--operation mode is normal

S1L1034 = AMPP_FUNCTION(S1L987, S1L990, S1L989, S1L988);

--S1L1039 is std_1c20:inst|cpu:the_cpu|ic_fill_valid_bits_nxt[7]~327

--operation mode is normal

S1L1039 = AMPP_FUNCTION(S1L988, S1L987, S1L990, S1L989);

--S1L1035 is std_1c20:inst|cpu:the_cpu|ic_fill_valid_bits_nxt[2]~329

--operation mode is normal

S1L1035 = AMPP_FUNCTION(S1L988, S1L990, S1L989, S1L987);

--S1L1037 is std_1c20:inst|cpu:the_cpu|ic_fill_valid_bits_nxt[4]~331

--operation mode is normal

S1L1037 = AMPP_FUNCTION(S1L990, S1L989, S1L988, S1L987);

--S1L1033 is std_1c20:inst|cpu:the_cpu|ic_fill_valid_bits_nxt[0]~333

--operation mode is normal

S1L1033 = AMPP_FUNCTION(S1L990, S1L989, S1L988, S1L987);

--S1L779 is std_1c20:inst|cpu:the_cpu|Equal158~63

--operation mode is normal

S1L779 = AMPP_FUNCTION(S1L988, S1L990, S1L989, S1L987);

--S1L77 is std_1c20:inst|cpu:the_cpu|A_WE_StdLogicVector~14157

--operation mode is normal

S1L77 = AMPP_FUNCTION(S1_E_iw[6], S1_E_ctrl_jmp_direct, S1_E_extra_pc[0], S1L1271);

--S1_E_pc[0] is std_1c20:inst|cpu:the_cpu|E_pc[0]

--operation mode is normal

S1_E_pc[0] = AMPP_FUNCTION(QC2__clk0, S1_D_pc[0], F1_data_out, S1_W_stall);

--U1L6 is std_1c20:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_read_but_no_slave_selected~56

--operation mode is normal

U1L6 = !NB1L18 & !V1L7 & !X1L6;

--U1L7 is std_1c20:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_read_but_no_slave_selected~57

--operation mode is normal

U1L7 = U1L6 & !Y1L84 & !Y1L82 & !Y1L83;

--Y1_cpu_instruction_master_read_data_valid_ext_flash_s1_shift_register[0] is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|cpu_instruction_master_read_data_valid_ext_flash_s1_shift_register[0]

--operation mode is normal

Y1_cpu_instruction_master_read_data_valid_ext_flash_s1_shift_register[0]_lut_out = U1L165 & Y1L88 & (Y1L21 # Y1L23);

Y1_cpu_instruction_master_read_data_valid_ext_flash_s1_shift_register[0] = DFFEAS(Y1_cpu_instruction_master_read_data_valid_ext_flash_s1_shift_register[0]_lut_out, QC2__clk0, F1_data_out, , , , , , );

--Y1_cpu_instruction_master_read_data_valid_lan91c111_s1_shift_register[0] is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|cpu_instruction_master_read_data_valid_lan91c111_s1_shift_register[0]

--operation mode is normal

Y1_cpu_instruction_master_read_data_valid_lan91c111_s1_shift_register[0]_lut_out = Y1L248 & Y1L95 & (Y1L9 # Y1L11);

Y1_cpu_instruction_master_read_data_valid_lan91c111_s1_shift_register[0] = DFFEAS(Y1_cpu_instruction_master_read_data_valid_lan91c111_s1_shift_register[0]_lut_out, QC2__clk0, F1_data_out, , , , , , );

--Y1_cpu_instruction_master_read_data_valid_ext_ram_s1_shift_register[0] is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|cpu_instruction_master_read_data_valid_ext_ram_s1_shift_register[0]

--operation mode is normal

Y1_cpu_instruction_master_read_data_valid_ext_ram_s1_shift_register[0]_lut_out = Y1L83;

Y1_cpu_instruction_master_read_data_valid_ext_ram_s1_shift_register[0] = DFFEAS(Y1_cpu_instruction_master_read_data_valid_ext_ram_s1_shift_register[0]_lut_out, QC2__clk0, F1_data_out, , , , , , );

--KB1_rd_valid[0] is std_1c20:inst|sdram:the_sdram|rd_valid[0]

--operation mode is normal

KB1_rd_valid[0]_lut_out = KB1_m_cmd[1] & (!KB1_m_cmd[2] & !KB1_m_cmd[0]);

KB1_rd_valid[0] = DFFEAS(KB1_rd_valid[0]_lut_out, QC2__clk0, F1_data_out, , , , , , );

--WE1_stage_3 is std_1c20:inst|sdram_s1_arbitrator:the_sdram_s1|rdv_fifo_for_cpu_instruction_master_to_sdram_s1_module:rdv_fifo_for_cpu_instruction_master_to_sdram_s1|stage_3

--operation mode is normal

WE1_stage_3_lut_out = WE1_full_4 & WE1_stage_4 # !WE1_full_4 & (NB1L18);

WE1_stage_3 = DFFEAS(WE1_stage_3_lut_out, QC2__clk0, VCC, , WE1L23, , , , );

--WE1_full_3 is std_1c20:inst|sdram_s1_arbitrator:the_sdram_s1|rdv_fifo_for_cpu_instruction_master_to_sdram_s1_module:rdv_fifo_for_cpu_instruction_master_to_sdram_s1|full_3

--operation mode is normal

WE1_full_3_lut_out = KB1_za_valid & (NB1L27 & WE1_full_2 # !NB1L27 & (WE1_full_4)) # !KB1_za_valid & WE1_full_2;

WE1_full_3 = DFFEAS(WE1_full_3_lut_out, QC2__clk0, F1_data_out, , VE1L13, , , , );

--WE1L24 is std_1c20:inst|sdram_s1_arbitrator:the_sdram_s1|rdv_fifo_for_cpu_instruction_master_to_sdram_s1_module:rdv_fifo_for_cpu_instruction_master_to_sdram_s1|process8~1

--operation mode is normal

WE1L24 = KB1_za_valid # NB1L27 & (!WE1_full_2);

--LC1_master_state[1] is std_1c20:inst|clock_1:the_clock_1|clock_1_master_FSM:master_FSM|master_state[1]

--operation mode is normal

LC1_master_state[1]_lut_out = !LC1_master_state[2] & (LC1L10 # LC1L2 & !LC1L3);

LC1_master_state[1] = DFFEAS(LC1_master_state[1]_lut_out, PLD_CLOCKINPUT[1], E1_data_out, , , , , , );

--LC1_master_state[2] is std_1c20:inst|clock_1:the_clock_1|clock_1_master_FSM:master_FSM|master_state[2]

--operation mode is normal

LC1_master_state[2]_lut_out = !LC1_master_state[0] & !LC1L9 & (MC4_data_in_d1 $ JC1_data_out);

LC1_master_state[2] = DFFEAS(LC1_master_state[2]_lut_out, PLD_CLOCKINPUT[1], E1_data_out, , , , , , );

--LC1_master_state[0] is std_1c20:inst|clock_1:the_clock_1|clock_1_master_FSM:master_FSM|master_state[0]

--operation mode is normal

LC1_master_state[0]_lut_out = !LC1L11 & (LC1_master_state[1] # !LC1_master_state[0] & !LC1L12);

LC1_master_state[0] = DFFEAS(LC1_master_state[0]_lut_out, PLD_CLOCKINPUT[1], E1_data_out, , , , , , );

--E1_data_out is std_1c20:inst|std_1c20_reset_PLD_CLOCKINPUT_domain_synch_module:std_1c20_reset_PLD_CLOCKINPUT_domain_synch|data_out

--operation mode is normal

E1_data_out_lut_out = E1_data_in_d1;

E1_data_out = DFFEAS(E1_data_out_lut_out, PLD_CLOCKINPUT[1], !B1L1, , , , , , );

--LC1L2 is std_1c20:inst|clock_1:the_clock_1|clock_1_master_FSM:master_FSM|internal_master_read_done~53

--operation mode is normal

LC1L2 = LC1_master_state[1] & LC1_master_state[0];

--R1_d1_reasons_to_wait is std_1c20:inst|connector_pll_s1_arbitrator:the_connector_pll_s1|d1_reasons_to_wait

--operation mode is normal

R1_d1_reasons_to_wait_lut_out = !LC1L3;

R1_d1_reasons_to_wait = DFFEAS(R1_d1_reasons_to_wait_lut_out, PLD_CLOCKINPUT[1], E1_data_out, , , , , , );

--LC1L3 is std_1c20:inst|clock_1:the_clock_1|clock_1_master_FSM:master_FSM|internal_master_read_done~54

--operation mode is normal

LC1L3 = R1_d1_reasons_to_wait # !LC1_master_state[1];

--CC1_master_state[1] is std_1c20:inst|clock_0:the_clock_0|clock_0_master_FSM:master_FSM|master_state[1]

--operation mode is normal

CC1_master_state[1]_lut_out = !CC1_master_state[2] & (CC1L10 # CC1L2 & !CC1L3);

CC1_master_state[1] = DFFEAS(CC1_master_state[1]_lut_out, PLD_CLKFB, D1_data_out, , , , , , );

--CC1_master_state[2] is std_1c20:inst|clock_0:the_clock_0|clock_0_master_FSM:master_FSM|master_state[2]

--operation mode is normal

CC1_master_state[2]_lut_out = !CC1_master_state[0] & !CC1L9 & (DC4_data_in_d1 $ AC1_data_out);

CC1_master_state[2] = DFFEAS(CC1_master_state[2]_lut_out, PLD_CLKFB, D1_data_out, , , , , , );

--CC1_master_state[0] is std_1c20:inst|clock_0:the_clock_0|clock_0_master_FSM:master_FSM|master_state[0]

--operation mode is normal

CC1_master_state[0]_lut_out = !CC1L11 & (CC1_master_state[1] # !CC1_master_state[0] & !CC1L12);

CC1_master_state[0] = DFFEAS(CC1_master_state[0]_lut_out, PLD_CLKFB, D1_data_out, , , , , , );

--D1_data_out is std_1c20:inst|std_1c20_reset_PLD_CLKFB_domain_synch_module:std_1c20_reset_PLD_CLKFB_domain_synch|data_out

--operation mode is normal

D1_data_out_lut_out = D1_data_in_d1;

D1_data_out = DFFEAS(D1_data_out_lut_out, PLD_CLKFB, !B1L1, , , , , , );

--CC1L2 is std_1c20:inst|clock_0:the_clock_0|clock_0_master_FSM:master_FSM|internal_master_read_done~53

--operation mode is normal

CC1L2 = CC1_master_state[1] & CC1_master_state[0];

--MB1_d1_reasons_to_wait is std_1c20:inst|sdram_pll_s1_arbitrator:the_sdram_pll_s1|d1_reasons_to_wait

--operation mode is normal

MB1_d1_reasons_to_wait_lut_out = !CC1L3;

MB1_d1_reasons_to_wait = DFFEAS(MB1_d1_reasons_to_wait_lut_out, PLD_CLKFB, D1_data_out, , , , , , );

--CC1L3 is std_1c20:inst|clock_0:the_clock_0|clock_0_master_FSM:master_FSM|internal_master_read_done~54

--operation mode is normal

CC1L3 = MB1_d1_reasons_to_wait # !CC1_master_state[1];

--VE1_stage_3 is std_1c20:inst|sdram_s1_arbitrator:the_sdram_s1|rdv_fifo_for_cpu_data_master_to_sdram_s1_module:rdv_fifo_for_cpu_data_master_to_sdram_s1|stage_3

--operation mode is normal

VE1_stage_3_lut_out = WE1_full_4 & VE1_stage_4 # !WE1_full_4 & (NB1L14);

VE1_stage_3 = DFFEAS(VE1_stage_3_lut_out, QC2__clk0, VCC, , WE1L23, , , , );

--GD1_break_readreg[21] is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_break:the_cpu_nios2_oci_break|break_readreg[21]

--operation mode is normal

GD1_break_readreg[21] = AMPP_FUNCTION(QC2__clk0, SD1_internal_jdo1[21], SD1_internal_jdo1[36], SD1_internal_jdo1[37], SD1L189, !C1_CLR_SIGNAL, SD1L189);

--SD1L20 is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|DRsize[0]~19989

--operation mode is normal

SD1L20 = AMPP_FUNCTION(GD1_break_readreg[21], RD1_internal_MonDReg[21], SD1_ir[1]);

--SD1L21 is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|DRsize[0]~19990

--operation mode is normal

SD1L21 = AMPP_FUNCTION(SD1L145, SD1L143, SD1L20, SD1_ir[0]);

--SD1_sr[23] is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|sr[23]

--operation mode is normal

SD1_sr[23] = AMPP_FUNCTION(A1L5, SD1L32, SD1_sr[24], SD1L9, SD1L33, !C1_CLR_SIGNAL, SD1L12);

--SD1L22 is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|DRsize[0]~19991

--operation mode is normal

SD1L22 = AMPP_FUNCTION(SD1L20, A1L4, SD1L145, SD1_ir[0]);

--KB1L142 is std_1c20:inst|sdram:the_sdram|i_refs[2]~287

--operation mode is normal

KB1L142 = F1_data_out & KB1_i_state[1] & !KB1_i_state[0] & !KB1_i_state[2];

--KB1L139 is std_1c20:inst|sdram:the_sdram|i_refs[0]~288

--operation mode is normal

KB1L139 = F1_data_out & (!KB1_i_state[0] & !KB1_i_state[2]);

--KB1L99 is std_1c20:inst|sdram:the_sdram|Add1~39

--operation mode is normal

KB1L99 = KB1_i_refs[0] & KB1_i_refs[1];

--ZE1L24 is std_1c20:inst|uart1:the_uart1|uart1_tx:the_uart1_tx|internal_tx_ready~40

--operation mode is normal

ZE1L24 = ZE1_do_load_shifter # !ZE1_internal_tx_ready;

--WB1_d1_reasons_to_wait is std_1c20:inst|uart1_s1_arbitrator:the_uart1_s1|d1_reasons_to_wait

--operation mode is normal

WB1_d1_reasons_to_wait_lut_out = !S1_M_alu_result[5] & !WB1_d1_reasons_to_wait & S1_M_alu_result[6] & SB1L2;

WB1_d1_reasons_to_wait = DFFEAS(WB1_d1_reasons_to_wait_lut_out, QC2__clk0, F1_data_out, , , , , , );

--ZE1L34 is std_1c20:inst|uart1:the_uart1|uart1_tx:the_uart1_tx|tx_wr_strobe_onset~35

--operation mode is normal

ZE1L34 = !S1_M_alu_result[5] & !WB1_d1_reasons_to_wait;

--ZE1L35 is std_1c20:inst|uart1:the_uart1|uart1_tx:the_uart1_tx|tx_wr_strobe_onset~36

--operation mode is normal

ZE1L35 = S1_M_alu_result[2] & S1_internal_d_write & !S1_M_alu_result[3] & !S1_M_alu_result[4];

--ZE1L29 is std_1c20:inst|uart1:the_uart1|uart1_tx:the_uart1_tx|process4~0

--operation mode is normal

ZE1L29 = ZE1_do_load_shifter # ZE1L21 & ZE1L22 & !ZE1_baud_rate_counter[8];

--U1_dbs_latent_8_reg_segment_1[0] is std_1c20:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|dbs_latent_8_reg_segment_1[0]

--operation mode is normal

U1_dbs_latent_8_reg_segment_1[0]_lut_out = Y1_internal_incoming_ext_ram_bus_data[0];

U1_dbs_latent_8_reg_segment_1[0] = DFFEAS(U1_dbs_latent_8_reg_segment_1[0]_lut_out, QC2__clk0, F1_data_out, , U1L176, , , , );

--U1L32 is std_1c20:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_readdata[8]~2417

--operation mode is normal

U1L32 = U1_dbs_latent_8_reg_segment_1[0] & (!KB1_za_data[8] & NB1_cpu_instruction_master_read_data_valid_sdram_s1) # !U1_dbs_latent_8_reg_segment_1[0] & (Y1_cpu_instruction_master_read_data_valid_ext_flash_s1_shift_register[1] # !KB1_za_data[8] & NB1_cpu_instruction_master_read_data_valid_sdram_s1);

--U1L33 is std_1c20:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_readdata[8]~2418

--operation mode is normal

U1L33 = !U1L32 & (Y1_internal_incoming_ext_ram_bus_data[8] # !Y1_cpu_instruction_master_read_data_valid_ext_ram_s1_shift_register[1] & !Y1_cpu_instruction_master_read_data_valid_lan91c111_s1_shift_register[1]);

--U1L34 is std_1c20:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_readdata[8]~2419

--operation mode is normal

U1L34 = U1L33 & (U1L119 # !X1_cpu_instruction_master_qualified_request_epcs_controller_epcs_control_port);

--S1L219 is std_1c20:inst|cpu:the_cpu|D_ctrl_exception~77

--operation mode is normal

S1L219 = AMPP_FUNCTION(S1_D_iw[16], S1_D_iw[15], S1_D_iw[14], S1_D_iw[13]);

--BB1L56 is std_1c20:inst|jtag_uart:the_jtag_uart|process2~48

--operation mode is normal

BB1L56 = S1_internal_d_write & UB1L9 & CB1L2 & BB1L54;

--BB1L46 is std_1c20:inst|jtag_uart:the_jtag_uart|ien_AE~19

--operation mode is normal

BB1L46 = S1_M_alu_result[2] & BB1L56;

--RE1_safe_q[5] is std_1c20:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_w:the_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_jf21:auto_generated|a_dpfifo_ml21:dpfifo|a_fefifo_7cf:fifo_state|cntr_9c7:count_usedw|safe_q[5]

--operation mode is normal

RE1_safe_q[5]_carry_eqn = RE1L10;

RE1_safe_q[5]_lut_out = RE1_safe_q[5] $ (RE1_safe_q[5]_carry_eqn);

RE1_safe_q[5] = DFFEAS(RE1_safe_q[5]_lut_out, QC2__clk0, F1_data_out, , NE1L1, , , , );

--RE1_safe_q[4] is std_1c20:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_w:the_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_jf21:auto_generated|a_dpfifo_ml21:dpfifo|a_fefifo_7cf:fifo_state|cntr_9c7:count_usedw|safe_q[4]

--operation mode is arithmetic

RE1_safe_q[4]_carry_eqn = RE1L8;

RE1_safe_q[4]_lut_out = RE1_safe_q[4] $ (!RE1_safe_q[4]_carry_eqn);

RE1_safe_q[4] = DFFEAS(RE1_safe_q[4]_lut_out, QC2__clk0, F1_data_out, , NE1L1, , , , );

--RE1L10 is std_1c20:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_w:the_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_jf21:auto_generated|a_dpfifo_ml21:dpfifo|a_fefifo_7cf:fifo_state|cntr_9c7:count_usedw|counter_cella4~COUT

--operation mode is arithmetic

RE1L10 = CARRY(!RE1L8 & (RE1_safe_q[4] $ !BB1_fifo_wr));

--RE1_safe_q[3] is std_1c20:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_w:the_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_jf21:auto_generated|a_dpfifo_ml21:dpfifo|a_fefifo_7cf:fifo_state|cntr_9c7:count_usedw|safe_q[3]

--operation mode is arithmetic

RE1_safe_q[3]_carry_eqn = RE1L6;

RE1_safe_q[3]_lut_out = RE1_safe_q[3] $ (RE1_safe_q[3]_carry_eqn);

RE1_safe_q[3] = DFFEAS(RE1_safe_q[3]_lut_out, QC2__clk0, F1_data_out, , NE1L1, , , , );

--RE1L8 is std_1c20:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_w:the_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_jf21:auto_generated|a_dpfifo_ml21:dpfifo|a_fefifo_7cf:fifo_state|cntr_9c7:count_usedw|counter_cella3~COUT

--operation mode is arithmetic

RE1L8 = CARRY(RE1_safe_q[3] $ BB1_fifo_wr # !RE1L6);

--RE1_safe_q[2] is std_1c20:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_w:the_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_jf21:auto_generated|a_dpfifo_ml21:dpfifo|a_fefifo_7cf:fifo_state|cntr_9c7:count_usedw|safe_q[2]

--operation mode is arithmetic

RE1_safe_q[2]_carry_eqn = RE1L4;

RE1_safe_q[2]_lut_out = RE1_safe_q[2] $ (!RE1_safe_q[2]_carry_eqn);

RE1_safe_q[2] = DFFEAS(RE1_safe_q[2]_lut_out, QC2__clk0, F1_data_out, , NE1L1, , , , );

--RE1L6 is std_1c20:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_w:the_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_jf21:auto_generated|a_dpfifo_ml21:dpfifo|a_fefifo_7cf:fifo_state|cntr_9c7:count_usedw|counter_cella2~COUT

--operation mode is arithmetic

RE1L6 = CARRY(!RE1L4 & (RE1_safe_q[2] $ !BB1_fifo_wr));

--RE1_safe_q[1] is std_1c20:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_w:the_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_jf21:auto_generated|a_dpfifo_ml21:dpfifo|a_fefifo_7cf:fifo_state|cntr_9c7:count_usedw|safe_q[1]

--operation mode is arithmetic

RE1_safe_q[1]_carry_eqn = RE1L2;

RE1_safe_q[1]_lut_out = RE1_safe_q[1] $ (RE1_safe_q[1]_carry_eqn);

RE1_safe_q[1] = DFFEAS(RE1_safe_q[1]_lut_out, QC2__clk0, F1_data_out, , NE1L1, , , , );

--RE1L4 is std_1c20:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_w:the_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_jf21:auto_generated|a_dpfifo_ml21:dpfifo|a_fefifo_7cf:fifo_state|cntr_9c7:count_usedw|counter_cella1~COUT

--operation mode is arithmetic

RE1L4 = CARRY(RE1_safe_q[1] $ BB1_fifo_wr # !RE1L2);

--BB1L50 is std_1c20:inst|jtag_uart:the_jtag_uart|LessThan0~96

--operation mode is normal

BB1L50 = RE1_safe_q[3] & (RE1_safe_q[0] # RE1_safe_q[2] # RE1_safe_q[1]);

--BB1L3 is std_1c20:inst|jtag_uart:the_jtag_uart|Add0~180

--operation mode is arithmetic

BB1L3_carry_eqn = BB1L14;

BB1L3 = NE2_b_full $ (BB1L3_carry_eqn);

--BB1L4 is std_1c20:inst|jtag_uart:the_jtag_uart|Add0~181

--operation mode is arithmetic

BB1L4 = CARRY(NE2_b_full & (!BB1L14));

--BB1L5 is std_1c20:inst|jtag_uart:the_jtag_uart|Add0~182

--operation mode is arithmetic

BB1L5_carry_eqn = BB1L10;

BB1L5 = RE2_safe_q[3] $ (BB1L5_carry_eqn);

--BB1L6 is std_1c20:inst|jtag_uart:the_jtag_uart|Add0~183

--operation mode is arithmetic

BB1L6 = CARRY(!RE2_safe_q[3] & (!BB1L10));

--BB1L7 is std_1c20:inst|jtag_uart:the_jtag_uart|Add0~184

--operation mode is arithmetic

BB1L7 = RE2_safe_q[1] $ RE2_safe_q[0];

--BB1L8 is std_1c20:inst|jtag_uart:the_jtag_uart|Add0~185

--operation mode is arithmetic

BB1L8 = CARRY(!RE2_safe_q[1] & !RE2_safe_q[0]);

--BB1L9 is std_1c20:inst|jtag_uart:the_jtag_uart|Add0~186

--operation mode is arithmetic

BB1L9_carry_eqn = BB1L8;

BB1L9 = RE2_safe_q[2] $ (!BB1L9_carry_eqn);

--BB1L10 is std_1c20:inst|jtag_uart:the_jtag_uart|Add0~187

--operation mode is arithmetic

BB1L10 = CARRY(RE2_safe_q[2] # !BB1L8);

--BB1L51 is std_1c20:inst|jtag_uart:the_jtag_uart|LessThan1~117

--operation mode is normal

BB1L51 = BB1L5 & (RE2_safe_q[0] # BB1L7 # BB1L9);

--BB1L11 is std_1c20:inst|jtag_uart:the_jtag_uart|Add0~188

--operation mode is arithmetic

BB1L11_carry_eqn = BB1L6;

BB1L11 = RE2_safe_q[4] $ (!BB1L11_carry_eqn);

--BB1L12 is std_1c20:inst|jtag_uart:the_jtag_uart|Add0~189

--operation mode is arithmetic

BB1L12 = CARRY(RE2_safe_q[4] # !BB1L6);

--BB1L13 is std_1c20:inst|jtag_uart:the_jtag_uart|Add0~190

--operation mode is arithmetic

BB1L13_carry_eqn = BB1L12;

BB1L13 = RE2_safe_q[5] $ (BB1L13_carry_eqn);

--BB1L14 is std_1c20:inst|jtag_uart:the_jtag_uart|Add0~191

--operation mode is arithmetic

BB1L14 = CARRY(!RE2_safe_q[5] & (!BB1L12));

--BB1L52 is std_1c20:inst|jtag_uart:the_jtag_uart|LessThan1~118

--operation mode is normal

BB1L52 = BB1L11 # BB1L13;

--BB1L15 is std_1c20:inst|jtag_uart:the_jtag_uart|Add0~192

--operation mode is normal

BB1L15_carry_eqn = BB1L4;

BB1L15 = !BB1L15_carry_eqn;

--GE1L39Q is std_1c20:inst|jtag_uart:the_jtag_uart|alt_jtag_atlantic:jtag_uart_alt_jtag_atlantic|t_pause~reg0

--operation mode is normal

GE1L39Q = AMPP_FUNCTION(QC2__clk0, GE1L2, GE1L38, GE1_jupdate1, GE1_jupdate2, F1_data_out);

--RB1_internal_counter[0] is std_1c20:inst|sys_clk_timer:the_sys_clk_timer|internal_counter[0]

--operation mode is arithmetic

RB1_internal_counter[0]_lut_out = !RB1_internal_counter[0];

RB1_internal_counter[0] = DFFEAS(RB1_internal_counter[0]_lut_out, QC2__clk0, F1_data_out, , RB1L156, RB1_period_l_register[0], , , RB1L157);

--RB1L58 is std_1c20:inst|sys_clk_timer:the_sys_clk_timer|internal_counter[0]~7696

--operation mode is arithmetic

RB1L58 = CARRY(!RB1_internal_counter[0]);

--RB1_internal_counter[1] is std_1c20:inst|sys_clk_timer:the_sys_clk_timer|internal_counter[1]

--operation mode is arithmetic

RB1_internal_counter[1]_carry_eqn = RB1L58;

RB1_internal_counter[1]_lut_out = RB1_internal_counter[1] $ (!RB1_internal_counter[1]_carry_eqn);

RB1_internal_counter[1] = DFFEAS(RB1_internal_counter[1]_lut_out, QC2__clk0, F1_data_out, , RB1L156, RB1_period_l_register[1], , , RB1L157);

--RB1L60 is std_1c20:inst|sys_clk_timer:the_sys_clk_timer|internal_counter[1]~7697

--operation mode is arithmetic

RB1L60 = CARRY(RB1_internal_counter[1] & (!RB1L58));

--RB1_internal_counter[2] is std_1c20:inst|sys_clk_timer:the_sys_clk_timer|internal_counter[2]

--operation mode is arithmetic

RB1_internal_counter[2]_carry_eqn = RB1L60;

RB1_internal_counter[2]_lut_out = RB1_internal_counter[2] $ (RB1_internal_counter[2]_carry_eqn);

RB1_internal_counter[2] = DFFEAS(RB1_internal_counter[2]_lut_out, QC2__clk0, F1_data_out, , RB1L156, RB1_period_l_register[2], , , RB1L157);

--RB1L62 is std_1c20:inst|sys_clk_timer:the_sys_clk_timer|internal_counter[2]~7698

--operation mode is arithmetic

RB1L62 = CARRY(!RB1L60 # !RB1_internal_counter[2]);

--RB1_internal_counter[3] is std_1c20:inst|sys_clk_timer:the_sys_clk_timer|internal_counter[3]

--operation mode is arithmetic

RB1_internal_counter[3]_carry_eqn = RB1L62;

RB1_internal_counter[3]_lut_out = RB1_internal_counter[3] $ (!RB1_internal_counter[3]_carry_eqn);

RB1_internal_counter[3] = DFFEAS(RB1_internal_counter[3]_lut_out, QC2__clk0, F1_data_out, , RB1L156, RB1_period_l_register[3], , , RB1L157);

--RB1L64 is std_1c20:inst|sys_clk_timer:the_sys_clk_timer|internal_counter[3]~7699

--operation mode is arithmetic

RB1L64 = CARRY(RB1_internal_counter[3] & (!RB1L62));

--RB1L45 is std_1c20:inst|sys_clk_timer:the_sys_clk_timer|Equal0~370

--operation mode is normal

RB1L45 = RB1_internal_counter[0] & RB1_internal_counter[1] & RB1_internal_counter[2] & RB1_internal_counter[3];

--RB1_internal_counter[4] is std_1c20:inst|sys_clk_timer:the_sys_clk_timer|internal_counter[4]

--operation mode is arithmetic

RB1_internal_counter[4]_carry_eqn = RB1L64;

RB1_internal_counter[4]_lut_out = RB1_internal_counter[4] $ (RB1_internal_counter[4]_carry_eqn);

RB1_internal_counter[4] = DFFEAS(RB1_internal_counter[4]_lut_out, QC2__clk0, F1_data_out, , RB1L156, RB1_period_l_register[4], , , RB1L157);

--RB1L66 is std_1c20:inst|sys_clk_timer:the_sys_clk_timer|internal_counter[4]~7700

--operation mode is arithmetic

RB1L66 = CARRY(!RB1L64 # !RB1_internal_counter[4]);

--RB1_internal_counter[5] is std_1c20:inst|sys_clk_timer:the_sys_clk_timer|internal_counter[5]

--operation mode is arithmetic

RB1_internal_counter[5]_carry_eqn = RB1L66;

RB1_internal_counter[5]_lut_out = RB1_internal_counter[5] $ (!RB1_internal_counter[5]_carry_eqn);

RB1_internal_counter[5] = DFFEAS(RB1_internal_counter[5]_lut_out, QC2__clk0, F1_data_out, , RB1L156, RB1_period_l_register[5], , , RB1L157);

--RB1L68 is std_1c20:inst|sys_clk_timer:the_sys_clk_timer|internal_counter[5]~7701

--operation mode is arithmetic

RB1L68 = CARRY(!RB1_internal_counter[5] & (!RB1L66));

--RB1_internal_counter[6] is std_1c20:inst|sys_clk_timer:the_sys_clk_timer|internal_counter[6]

--operation mode is arithmetic

RB1_internal_counter[6]_carry_eqn = RB1L68;

RB1_internal_counter[6]_lut_out = RB1_internal_counter[6] $ (RB1_internal_counter[6]_carry_eqn);

RB1_internal_counter[6] = DFFEAS(RB1_internal_counter[6]_lut_out, QC2__clk0, F1_data_out, , RB1L156, RB1_period_l_register[6], , , RB1L157);

--RB1L70 is std_1c20:inst|sys_clk_timer:the_sys_clk_timer|internal_counter[6]~7702

--operation mode is arithmetic

RB1L70 = CARRY(RB1_internal_counter[6] # !RB1L68);

--RB1_internal_counter[7] is std_1c20:inst|sys_clk_timer:the_sys_clk_timer|internal_counter[7]

--operation mode is arithmetic

RB1_internal_counter[7]_carry_eqn = RB1L70;

RB1_internal_counter[7]_lut_out = RB1_internal_counter[7] $ (!RB1_internal_counter[7]_carry_eqn);

RB1_internal_counter[7] = DFFEAS(RB1_internal_counter[7]_lut_out, QC2__clk0, F1_data_out, , RB1L156, RB1_period_l_register[7], , , RB1L157);

--RB1L72 is std_1c20:inst|sys_clk_timer:the_sys_clk_timer|internal_counter[7]~7703

--operation mode is arithmetic

RB1L72 = CARRY(!RB1_internal_counter[7] & (!RB1L70));

--RB1L46 is std_1c20:inst|sys_clk_timer:the_sys_clk_timer|Equal0~371

--operation mode is normal

RB1L46 = RB1_internal_counter[4] & !RB1_internal_counter[5] & !RB1_internal_counter[6] & !RB1_internal_counter[7];

--RB1_internal_counter[8] is std_1c20:inst|sys_clk_timer:the_sys_clk_timer|internal_counter[8]

--operation mode is arithmetic

RB1_internal_counter[8]_carry_eqn = RB1L72;

RB1_internal_counter[8]_lut_out = RB1_internal_counter[8] $ (RB1_internal_counter[8]_carry_eqn);

RB1_internal_counter[8] = DFFEAS(RB1_internal_counter[8]_lut_out, QC2__clk0, F1_data_out, , RB1L156, RB1_period_l_register[8], , , RB1L157);

--RB1L74 is std_1c20:inst|sys_clk_timer:the_sys_clk_timer|internal_counter[8]~7704

--operation mode is arithmetic

RB1L74 = CARRY(!RB1L72 # !RB1_internal_counter[8]);

--RB1_internal_counter[9] is std_1c20:inst|sys_clk_timer:the_sys_clk_timer|internal_counter[9]

--operation mode is arithmetic

RB1_internal_counter[9]_carry_eqn = RB1L74;

RB1_internal_counter[9]_lut_out = RB1_internal_counter[9] $ (!RB1_internal_counter[9]_carry_eqn);

RB1_internal_counter[9] = DFFEAS(RB1_internal_counter[9]_lut_out, QC2__clk0, F1_data_out, , RB1L156, RB1_period_l_register[9], , , RB1L157);

--RB1L76 is std_1c20:inst|sys_clk_timer:the_sys_clk_timer|internal_counter[9]~7705

--operation mode is arithmetic

RB1L76 = CARRY(!RB1_internal_counter[9] & (!RB1L74));

--RB1_internal_counter[10] is std_1c20:inst|sys_clk_timer:the_sys_clk_timer|internal_counter[10]

--operation mode is arithmetic

RB1_internal_counter[10]_carry_eqn = RB1L76;

RB1_internal_counter[10]_lut_out = RB1_internal_counter[10] $ (RB1_internal_counter[10]_carry_eqn);

RB1_internal_counter[10] = DFFEAS(RB1_internal_counter[10]_lut_out, QC2__clk0, F1_data_out, , RB1L156, RB1_period_l_register[10], , , RB1L157);

--RB1L78 is std_1c20:inst|sys_clk_timer:the_sys_clk_timer|internal_counter[10]~7706

--operation mode is arithmetic

RB1L78 = CARRY(RB1_internal_counter[10] # !RB1L76);

--RB1_internal_counter[11] is std_1c20:inst|sys_clk_timer:the_sys_clk_timer|internal_counter[11]

--operation mode is arithmetic

RB1_internal_counter[11]_carry_eqn = RB1L78;

RB1_internal_counter[11]_lut_out = RB1_internal_counter[11] $ (!RB1_internal_counter[11]_carry_eqn);

RB1_internal_counter[11] = DFFEAS(RB1_internal_counter[11]_lut_out, QC2__clk0, F1_data_out, , RB1L156, RB1_period_l_register[11], , , RB1L157);

--RB1L80 is std_1c20:inst|sys_clk_timer:the_sys_clk_timer|internal_counter[11]~7707

--operation mode is arithmetic

RB1L80 = CARRY(!RB1_internal_counter[11] & (!RB1L78));

--RB1L47 is std_1c20:inst|sys_clk_timer:the_sys_clk_timer|Equal0~372

--operation mode is normal

RB1L47 = RB1_internal_counter[8] & !RB1_internal_counter[9] & !RB1_internal_counter[10] & !RB1_internal_counter[11];

--RB1_internal_counter[13] is std_1c20:inst|sys_clk_timer:the_sys_clk_timer|internal_counter[13]

--operation mode is arithmetic

RB1_internal_counter[13]_carry_eqn = RB1L82;

RB1_internal_counter[13]_lut_out = RB1_internal_counter[13] $ (!RB1_internal_counter[13]_carry_eqn);

RB1_internal_counter[13] = DFFEAS(RB1_internal_counter[13]_lut_out, QC2__clk0, F1_data_out, , RB1L156, RB1_period_l_register[13], , , RB1L157);

--RB1L84 is std_1c20:inst|sys_clk_timer:the_sys_clk_timer|internal_counter[13]~7708

--operation mode is arithmetic

RB1L84 = CARRY(RB1_internal_counter[13] & (!RB1L82));

--RB1_internal_counter[15] is std_1c20:inst|sys_clk_timer:the_sys_clk_timer|internal_counter[15]

--operation mode is arithmetic

RB1_internal_counter[15]_carry_eqn = RB1L86;

RB1_internal_counter[15]_lut_out = RB1_internal_counter[15] $ (!RB1_internal_counter[15]_carry_eqn);

RB1_internal_counter[15] = DFFEAS(RB1_internal_counter[15]_lut_out, QC2__clk0, F1_data_out, , RB1L156, RB1_period_l_register[15], , , RB1L157);

--RB1L88 is std_1c20:inst|sys_clk_timer:the_sys_clk_timer|internal_counter[15]~7709

--operation mode is arithmetic

RB1L88 = CARRY(RB1_internal_counter[15] & (!RB1L86));

--RB1_internal_counter[12] is std_1c20:inst|sys_clk_timer:the_sys_clk_timer|internal_counter[12]

--operation mode is arithmetic

RB1_internal_counter[12]_carry_eqn = RB1L80;

RB1_internal_counter[12]_lut_out = RB1_internal_counter[12] $ (RB1_internal_counter[12]_carry_eqn);

RB1_internal_counter[12] = DFFEAS(RB1_internal_counter[12]_lut_out, QC2__clk0, F1_data_out, , RB1L156, RB1_period_l_register[12], , , RB1L157);

--RB1L82 is std_1c20:inst|sys_clk_timer:the_sys_clk_timer|internal_counter[12]~7710

--operation mode is arithmetic

RB1L82 = CARRY(RB1_internal_counter[12] # !RB1L80);

--RB1_internal_counter[14] is std_1c20:inst|sys_clk_timer:the_sys_clk_timer|internal_counter[14]

--operation mode is arithmetic

RB1_internal_counter[14]_carry_eqn = RB1L84;

RB1_internal_counter[14]_lut_out = RB1_internal_counter[14] $ (RB1_internal_counter[14]_carry_eqn);

RB1_internal_counter[14] = DFFEAS(RB1_internal_counter[14]_lut_out, QC2__clk0, F1_data_out, , RB1L156, RB1_period_l_register[14], , , RB1L157);

--RB1L86 is std_1c20:inst|sys_clk_timer:the_sys_clk_timer|internal_counter[14]~7711

--operation mode is arithmetic

RB1L86 = CARRY(RB1_internal_counter[14] # !RB1L84);

--RB1L48 is std_1c20:inst|sys_clk_timer:the_sys_clk_timer|Equal0~373

--operation mode is normal

RB1L48 = RB1_internal_counter[13] & RB1_internal_counter[15] & !RB1_internal_counter[12] & !RB1_internal_counter[14];

--RB1L49 is std_1c20:inst|sys_clk_timer:the_sys_clk_timer|Equal0~374

--operation mode is normal

RB1L49 = RB1L45 & RB1L46 & RB1L47 & RB1L48;

--RB1_internal_counter[16] is std_1c20:inst|sys_clk_timer:the_sys_clk_timer|internal_counter[16]

--operation mode is arithmetic

RB1_internal_counter[16]_carry_eqn = RB1L88;

RB1_internal_counter[16]_lut_out = RB1_internal_counter[16] $ (RB1_internal_counter[16]_carry_eqn);

RB1_internal_counter[16] = DFFEAS(RB1_internal_counter[16]_lut_out, QC2__clk0, F1_data_out, , RB1L156, RB1_period_h_register[0], , , RB1L157);

--RB1L90 is std_1c20:inst|sys_clk_timer:the_sys_clk_timer|internal_counter[16]~7712

--operation mode is arithmetic

RB1L90 = CARRY(!RB1L88 # !RB1_internal_counter[16]);

--RB1_internal_counter[17] is std_1c20:inst|sys_clk_timer:the_sys_clk_timer|internal_counter[17]

--operation mode is arithmetic

RB1_internal_counter[17]_carry_eqn = RB1L90;

RB1_internal_counter[17]_lut_out = RB1_internal_counter[17] $ (!RB1_internal_counter[17]_carry_eqn);

RB1_internal_counter[17] = DFFEAS(RB1_internal_counter[17]_lut_out, QC2__clk0, F1_data_out, , RB1L156, RB1_period_h_register[1], , , RB1L157);

--RB1L92 is std_1c20:inst|sys_clk_timer:the_sys_clk_timer|internal_counter[17]~7713

--operation mode is arithmetic

RB1L92 = CARRY(RB1_internal_counter[17] & (!RB1L90));

--RB1_internal_counter[18] is std_1c20:inst|sys_clk_timer:the_sys_clk_timer|internal_counter[18]

--operation mode is arithmetic

RB1_internal_counter[18]_carry_eqn = RB1L92;

RB1_internal_counter[18]_lut_out = RB1_internal_counter[18] $ (RB1_internal_counter[18]_carry_eqn);

RB1_internal_counter[18] = DFFEAS(RB1_internal_counter[18]_lut_out, QC2__clk0, F1_data_out, , RB1L156, RB1_period_h_register[2], , , RB1L157);

--RB1L94 is std_1c20:inst|sys_clk_timer:the_sys_clk_timer|internal_counter[18]~7714

--operation mode is arithmetic

RB1L94 = CARRY(!RB1L92 # !RB1_internal_counter[18]);

--RB1_internal_counter[19] is std_1c20:inst|sys_clk_timer:the_sys_clk_timer|internal_counter[19]

--operation mode is arithmetic

RB1_internal_counter[19]_carry_eqn = RB1L94;

RB1_internal_counter[19]_lut_out = RB1_internal_counter[19] $ (!RB1_internal_counter[19]_carry_eqn);

RB1_internal_counter[19] = DFFEAS(RB1_internal_counter[19]_lut_out, QC2__clk0, F1_data_out, , RB1L156, RB1_period_h_register[3], , , RB1L157);

--RB1L96 is std_1c20:inst|sys_clk_timer:the_sys_clk_timer|internal_counter[19]~7715

--operation mode is arithmetic

RB1L96 = CARRY(!RB1_internal_counter[19] & (!RB1L94));

--RB1L50 is std_1c20:inst|sys_clk_timer:the_sys_clk_timer|Equal0~375

--operation mode is normal

RB1L50 = RB1_internal_counter[16] & RB1_internal_counter[17] & RB1_internal_counter[18] & !RB1_internal_counter[19];

--RB1_internal_counter[20] is std_1c20:inst|sys_clk_timer:the_sys_clk_timer|internal_counter[20]

--operation mode is arithmetic

RB1_internal_counter[20]_carry_eqn = RB1L96;

RB1_internal_counter[20]_lut_out = RB1_internal_counter[20] $ (RB1_internal_counter[20]_carry_eqn);

RB1_internal_counter[20] = DFFEAS(RB1_internal_counter[20]_lut_out, QC2__clk0, F1_data_out, , RB1L156, RB1_period_h_register[4], , , RB1L157);

--RB1L98 is std_1c20:inst|sys_clk_timer:the_sys_clk_timer|internal_counter[20]~7716

--operation mode is arithmetic

RB1L98 = CARRY(RB1_internal_counter[20] # !RB1L96);

--RB1_internal_counter[21] is std_1c20:inst|sys_clk_timer:the_sys_clk_timer|internal_counter[21]

--operation mode is arithmetic

RB1_internal_counter[21]_carry_eqn = RB1L98;

RB1_internal_counter[21]_lut_out = RB1_internal_counter[21] $ (!RB1_internal_counter[21]_carry_eqn);

RB1_internal_counter[21] = DFFEAS(RB1_internal_counter[21]_lut_out, QC2__clk0, F1_data_out, , RB1L156, RB1_period_h_register[5], , , RB1L157);

--RB1L100 is std_1c20:inst|sys_clk_timer:the_sys_clk_timer|internal_counter[21]~7717

--operation mode is arithmetic

RB1L100 = CARRY(!RB1_internal_counter[21] & (!RB1L98));

--RB1_internal_counter[22] is std_1c20:inst|sys_clk_timer:the_sys_clk_timer|internal_counter[22]

--operation mode is arithmetic

RB1_internal_counter[22]_carry_eqn = RB1L100;

RB1_internal_counter[22]_lut_out = RB1_internal_counter[22] $ (RB1_internal_counter[22]_carry_eqn);

RB1_internal_counter[22] = DFFEAS(RB1_internal_counter[22]_lut_out, QC2__clk0, F1_data_out, , RB1L156, RB1_period_h_register[6], , , RB1L157);

--RB1L102 is std_1c20:inst|sys_clk_timer:the_sys_clk_timer|internal_counter[22]~7718

--operation mode is arithmetic

RB1L102 = CARRY(RB1_internal_counter[22] # !RB1L100);

--RB1_internal_counter[23] is std_1c20:inst|sys_clk_timer:the_sys_clk_timer|internal_counter[23]

--operation mode is arithmetic

RB1_internal_counter[23]_carry_eqn = RB1L102;

RB1_internal_counter[23]_lut_out = RB1_internal_counter[23] $ (!RB1_internal_counter[23]_carry_eqn);

RB1_internal_counter[23] = DFFEAS(RB1_internal_counter[23]_lut_out, QC2__clk0, F1_data_out, , RB1L156, RB1_period_h_register[7], , , RB1L157);

--RB1L104 is std_1c20:inst|sys_clk_timer:the_sys_clk_timer|internal_counter[23]~7719

--operation mode is arithmetic

RB1L104 = CARRY(!RB1_internal_counter[23] & (!RB1L102));

--RB1L51 is std_1c20:inst|sys_clk_timer:the_sys_clk_timer|Equal0~376

--operation mode is normal

RB1L51 = !RB1_internal_counter[20] & !RB1_internal_counter[21] & !RB1_internal_counter[22] & !RB1_internal_counter[23];

--RB1_internal_counter[24] is std_1c20:inst|sys_clk_timer:the_sys_clk_timer|internal_counter[24]

--operation mode is arithmetic

RB1_internal_counter[24]_carry_eqn = RB1L104;

RB1_internal_counter[24]_lut_out = RB1_internal_counter[24] $ (RB1_internal_counter[24]_carry_eqn);

RB1_internal_counter[24] = DFFEAS(RB1_internal_counter[24]_lut_out, QC2__clk0, F1_data_out, , RB1L156, RB1_period_h_register[8], , , RB1L157);

--RB1L106 is std_1c20:inst|sys_clk_timer:the_sys_clk_timer|internal_counter[24]~7720

--operation mode is arithmetic

RB1L106 = CARRY(RB1_internal_counter[24] # !RB1L104);

--RB1_internal_counter[25] is std_1c20:inst|sys_clk_timer:the_sys_clk_timer|internal_counter[25]

--operation mode is arithmetic

RB1_internal_counter[25]_carry_eqn = RB1L106;

RB1_internal_counter[25]_lut_out = RB1_internal_counter[25] $ (!RB1_internal_counter[25]_carry_eqn);

RB1_internal_counter[25] = DFFEAS(RB1_internal_counter[25]_lut_out, QC2__clk0, F1_data_out, , RB1L156, RB1_period_h_register[9], , , RB1L157);

--RB1L108 is std_1c20:inst|sys_clk_timer:the_sys_clk_timer|internal_counter[25]~7721

--operation mode is arithmetic

RB1L108 = CARRY(!RB1_internal_counter[25] & (!RB1L106));

--RB1_internal_counter[26] is std_1c20:inst|sys_clk_timer:the_sys_clk_timer|internal_counter[26]

--operation mode is arithmetic

RB1_internal_counter[26]_carry_eqn = RB1L108;

RB1_internal_counter[26]_lut_out = RB1_internal_counter[26] $ (RB1_internal_counter[26]_carry_eqn);

RB1_internal_counter[26] = DFFEAS(RB1_internal_counter[26]_lut_out, QC2__clk0, F1_data_out, , RB1L156, RB1_period_h_register[10], , , RB1L157);

--RB1L110 is std_1c20:inst|sys_clk_timer:the_sys_clk_timer|internal_counter[26]~7722

--operation mode is arithmetic

RB1L110 = CARRY(RB1_internal_counter[26] # !RB1L108);

--RB1_internal_counter[27] is std_1c20:inst|sys_clk_timer:the_sys_clk_timer|internal_counter[27]

--operation mode is arithmetic

RB1_internal_counter[27]_carry_eqn = RB1L110;

RB1_internal_counter[27]_lut_out = RB1_internal_counter[27] $ (!RB1_internal_counter[27]_carry_eqn);

RB1_internal_counter[27] = DFFEAS(RB1_internal_counter[27]_lut_out, QC2__clk0, F1_data_out, , RB1L156, RB1_period_h_register[11], , , RB1L157);

--RB1L112 is std_1c20:inst|sys_clk_timer:the_sys_clk_timer|internal_counter[27]~7723

--operation mode is arithmetic

RB1L112 = CARRY(!RB1_internal_counter[27] & (!RB1L110));

--RB1L52 is std_1c20:inst|sys_clk_timer:the_sys_clk_timer|Equal0~377

--operation mode is normal

RB1L52 = !RB1_internal_counter[24] & !RB1_internal_counter[25] & !RB1_internal_counter[26] & !RB1_internal_counter[27];

--RB1_internal_counter[28] is std_1c20:inst|sys_clk_timer:the_sys_clk_timer|internal_counter[28]

--operation mode is arithmetic

RB1_internal_counter[28]_carry_eqn = RB1L112;

RB1_internal_counter[28]_lut_out = RB1_internal_counter[28] $ (RB1_internal_counter[28]_carry_eqn);

RB1_internal_counter[28] = DFFEAS(RB1_internal_counter[28]_lut_out, QC2__clk0, F1_data_out, , RB1L156, RB1_period_h_register[12], , , RB1L157);

--RB1L114 is std_1c20:inst|sys_clk_timer:the_sys_clk_timer|internal_counter[28]~7724

--operation mode is arithmetic

RB1L114 = CARRY(RB1_internal_counter[28] # !RB1L112);

--RB1_internal_counter[29] is std_1c20:inst|sys_clk_timer:the_sys_clk_timer|internal_counter[29]

--operation mode is arithmetic

RB1_internal_counter[29]_carry_eqn = RB1L114;

RB1_internal_counter[29]_lut_out = RB1_internal_counter[29] $ (!RB1_internal_counter[29]_carry_eqn);

RB1_internal_counter[29] = DFFEAS(RB1_internal_counter[29]_lut_out, QC2__clk0, F1_data_out, , RB1L156, RB1_period_h_register[13], , , RB1L157);

--RB1L116 is std_1c20:inst|sys_clk_timer:the_sys_clk_timer|internal_counter[29]~7725

--operation mode is arithmetic

RB1L116 = CARRY(!RB1_internal_counter[29] & (!RB1L114));

--RB1_internal_counter[30] is std_1c20:inst|sys_clk_timer:the_sys_clk_timer|internal_counter[30]

--operation mode is arithmetic

RB1_internal_counter[30]_carry_eqn = RB1L116;

RB1_internal_counter[30]_lut_out = RB1_internal_counter[30] $ (RB1_internal_counter[30]_carry_eqn);

RB1_internal_counter[30] = DFFEAS(RB1_internal_counter[30]_lut_out, QC2__clk0, F1_data_out, , RB1L156, RB1_period_h_register[14], , , RB1L157);

--RB1L118 is std_1c20:inst|sys_clk_timer:the_sys_clk_timer|internal_counter[30]~7726

--operation mode is arithmetic

RB1L118 = CARRY(RB1_internal_counter[30] # !RB1L116);

--RB1_internal_counter[31] is std_1c20:inst|sys_clk_timer:the_sys_clk_timer|internal_counter[31]

--operation mode is normal

RB1_internal_counter[31]_carry_eqn = RB1L118;

RB1_internal_counter[31]_lut_out = RB1_internal_counter[31] $ (!RB1_internal_counter[31]_carry_eqn);

RB1_internal_counter[31] = DFFEAS(RB1_internal_counter[31]_lut_out, QC2__clk0, F1_data_out, , RB1L156, RB1_period_h_register[15], , , RB1L157);

--RB1L53 is std_1c20:inst|sys_clk_timer:the_sys_clk_timer|Equal0~378

--operation mode is normal

RB1L53 = !RB1_internal_counter[28] & !RB1_internal_counter[29] & !RB1_internal_counter[30] & !RB1_internal_counter[31];

--RB1L54 is std_1c20:inst|sys_clk_timer:the_sys_clk_timer|Equal0~379

--operation mode is normal

RB1L54 = RB1L50 & RB1L51 & RB1L52 & RB1L53;

--RB1_delayed_unxcounter_is_zeroxx0 is std_1c20:inst|sys_clk_timer:the_sys_clk_timer|delayed_unxcounter_is_zeroxx0

--operation mode is normal

RB1_delayed_unxcounter_is_zeroxx0_lut_out = RB1L49 & RB1L54;

RB1_delayed_unxcounter_is_zeroxx0 = DFFEAS(RB1_delayed_unxcounter_is_zeroxx0_lut_out, QC2__clk0, F1_data_out, , , , , , );

--RB1L211 is std_1c20:inst|sys_clk_timer:the_sys_clk_timer|timeout_occurred~41

--operation mode is normal

RB1L211 = RB1_timeout_occurred # RB1L49 & RB1L54 & !RB1_delayed_unxcounter_is_zeroxx0;

--U1_dbs_latent_8_reg_segment_0[7] is std_1c20:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|dbs_latent_8_reg_segment_0[7]

--operation mode is normal

U1_dbs_latent_8_reg_segment_0[7]_lut_out = Y1_internal_incoming_ext_ram_bus_data[7];

U1_dbs_latent_8_reg_segment_0[7] = DFFEAS(U1_dbs_latent_8_reg_segment_0[7]_lut_out, QC2__clk0, F1_data_out, , U1L175, , , , );

--U1L29 is std_1c20:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_readdata[7]~2421

--operation mode is normal

U1L29 = U1_dbs_latent_8_reg_segment_0[7] & (!KB1_za_data[7] & NB1_cpu_instruction_master_read_data_valid_sdram_s1) # !U1_dbs_latent_8_reg_segment_0[7] & (Y1_cpu_instruction_master_read_data_valid_ext_flash_s1_shift_register[1] # !KB1_za_data[7] & NB1_cpu_instruction_master_read_data_valid_sdram_s1);

--U1L30 is std_1c20:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_readdata[7]~2422

--operation mode is normal

U1L30 = !U1L29 & (Y1_internal_incoming_ext_ram_bus_data[7] # !Y1_cpu_instruction_master_read_data_valid_ext_ram_s1_shift_register[1] & !Y1_cpu_instruction_master_read_data_valid_lan91c111_s1_shift_register[1]);

--U1L31 is std_1c20:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_readdata[7]~2423

--operation mode is normal

U1L31 = U1L30 & (U1L114 # !X1_cpu_instruction_master_qualified_request_epcs_controller_epcs_control_port);

--U1L27 is std_1c20:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_readdata[6]~2425

--operation mode is normal

U1L27 = !Y1_internal_incoming_ext_ram_bus_data[6] & (Y1_cpu_instruction_master_read_data_valid_ext_ram_s1_shift_register[1] # Y1_cpu_instruction_master_read_data_valid_lan91c111_s1_shift_register[1]);

--U1_dbs_latent_8_reg_segment_0[6] is std_1c20:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|dbs_latent_8_reg_segment_0[6]

--operation mode is normal

U1_dbs_latent_8_reg_segment_0[6]_lut_out = Y1_internal_incoming_ext_ram_bus_data[6];

U1_dbs_latent_8_reg_segment_0[6] = DFFEAS(U1_dbs_latent_8_reg_segment_0[6]_lut_out, QC2__clk0, F1_data_out, , U1L175, , , , );

--U1L28 is std_1c20:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_readdata[6]~2426

--operation mode is normal

U1L28 = U1_dbs_latent_8_reg_segment_0[6] & (!KB1_za_data[6] & NB1_cpu_instruction_master_read_data_valid_sdram_s1) # !U1_dbs_latent_8_reg_segment_0[6] & (Y1_cpu_instruction_master_read_data_valid_ext_flash_s1_shift_register[1] # !KB1_za_data[6] & NB1_cpu_instruction_master_read_data_valid_sdram_s1);

--U1L21 is std_1c20:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_readdata[4]~2428

--operation mode is normal

U1L21 = !Y1_internal_incoming_ext_ram_bus_data[4] & (Y1_cpu_instruction_master_read_data_valid_ext_ram_s1_shift_register[1] # Y1_cpu_instruction_master_read_data_valid_lan91c111_s1_shift_register[1]);

--U1_dbs_latent_8_reg_segment_0[4] is std_1c20:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|dbs_latent_8_reg_segment_0[4]

--operation mode is normal

U1_dbs_latent_8_reg_segment_0[4]_lut_out = Y1_internal_incoming_ext_ram_bus_data[4];

U1_dbs_latent_8_reg_segment_0[4] = DFFEAS(U1_dbs_latent_8_reg_segment_0[4]_lut_out, QC2__clk0, F1_data_out, , U1L175, , , , );

--U1L22 is std_1c20:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_readdata[4]~2429

--operation mode is normal

U1L22 = U1_dbs_latent_8_reg_segment_0[4] & (!KB1_za_data[4] & NB1_cpu_instruction_master_read_data_valid_sdram_s1) # !U1_dbs_latent_8_reg_segment_0[4] & (Y1_cpu_instruction_master_read_data_valid_ext_flash_s1_shift_register[1] # !KB1_za_data[4] & NB1_cpu_instruction_master_read_data_valid_sdram_s1);

--U1L108 is std_1c20:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_readdata~47

--operation mode is normal

U1L108 = W1L1 & DE1_data_to_cpu[15] # !W1L1 & (FE1_q_a[15]) # !X1_cpu_instruction_master_qualified_request_epcs_controller_epcs_control_port;

--U1_dbs_latent_8_reg_segment_1[7] is std_1c20:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|dbs_latent_8_reg_segment_1[7]

--operation mode is normal

U1_dbs_latent_8_reg_segment_1[7]_lut_out = Y1_internal_incoming_ext_ram_bus_data[7];

U1_dbs_latent_8_reg_segment_1[7] = DFFEAS(U1_dbs_latent_8_reg_segment_1[7]_lut_out, QC2__clk0, F1_data_out, , U1L176, , , , );

--U1L111 is std_1c20:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_readdata~175

--operation mode is normal

U1L111 = U1_dbs_latent_8_reg_segment_1[7] # !Y1_cpu_instruction_master_read_data_valid_ext_flash_s1_shift_register[1];

--U1L51 is std_1c20:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_readdata[15]~2431

--operation mode is normal

U1L51 = U1L111 & (Y1_internal_incoming_ext_ram_bus_data[15] # !Y1_cpu_instruction_master_read_data_valid_lan91c111_s1_shift_register[1] & !Y1_cpu_instruction_master_read_data_valid_ext_ram_s1_shift_register[1]);

--U1L52 is std_1c20:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_readdata[15]~2432

--operation mode is normal

U1L52 = U1L108 & U1L51 & (KB1_za_data[15] # !NB1_cpu_instruction_master_read_data_valid_sdram_s1);

--U1L9 is std_1c20:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_readdata[0]~2434

--operation mode is normal

U1L9 = !Y1_internal_incoming_ext_ram_bus_data[0] & (Y1_cpu_instruction_master_read_data_valid_ext_ram_s1_shift_register[1] # Y1_cpu_instruction_master_read_data_valid_lan91c111_s1_shift_register[1]);

--U1_dbs_latent_8_reg_segment_0[0] is std_1c20:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|dbs_latent_8_reg_segment_0[0]

--operation mode is normal

U1_dbs_latent_8_reg_segment_0[0]_lut_out = Y1_internal_incoming_ext_ram_bus_data[0];

U1_dbs_latent_8_reg_segment_0[0] = DFFEAS(U1_dbs_latent_8_reg_segment_0[0]_lut_out, QC2__clk0, F1_data_out, , U1L175, , , , );

--KB1_za_data[0] is std_1c20:inst|sdram:the_sdram|za_data[0]

--operation mode is normal

KB1_za_data[0]_lut_out = A1L268;

KB1_za_data[0] = DFFEAS(KB1_za_data[0]_lut_out, QC2__clk0, F1_data_out, , , , , , );

--U1L10 is std_1c20:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_readdata[0]~2435

--operation mode is normal

U1L10 = U1_dbs_latent_8_reg_segment_0[0] & (!KB1_za_data[0] & NB1_cpu_instruction_master_read_data_valid_sdram_s1) # !U1_dbs_latent_8_reg_segment_0[0] & (Y1_cpu_instruction_master_read_data_valid_ext_flash_s1_shift_register[1] # !KB1_za_data[0] & NB1_cpu_instruction_master_read_data_valid_sdram_s1);

--U1L12 is std_1c20:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_readdata[1]~2437

--operation mode is normal

U1L12 = !Y1_internal_incoming_ext_ram_bus_data[1] & (Y1_cpu_instruction_master_read_data_valid_ext_ram_s1_shift_register[1] # Y1_cpu_instruction_master_read_data_valid_lan91c111_s1_shift_register[1]);

--U1_dbs_latent_8_reg_segment_0[1] is std_1c20:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|dbs_latent_8_reg_segment_0[1]

--operation mode is normal

U1_dbs_latent_8_reg_segment_0[1]_lut_out = Y1_internal_incoming_ext_ram_bus_data[1];

U1_dbs_latent_8_reg_segment_0[1] = DFFEAS(U1_dbs_latent_8_reg_segment_0[1]_lut_out, QC2__clk0, F1_data_out, , U1L175, , , , );

--KB1_za_data[1] is std_1c20:inst|sdram:the_sdram|za_data[1]

--operation mode is normal

KB1_za_data[1]_lut_out = A1L267;

KB1_za_data[1] = DFFEAS(KB1_za_data[1]_lut_out, QC2__clk0, F1_data_out, , , , , , );

--U1L13 is std_1c20:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_readdata[1]~2438

--operation mode is normal

U1L13 = U1_dbs_latent_8_reg_segment_0[1] & (!KB1_za_data[1] & NB1_cpu_instruction_master_read_data_valid_sdram_s1) # !U1_dbs_latent_8_reg_segment_0[1] & (Y1_cpu_instruction_master_read_data_valid_ext_flash_s1_shift_register[1] # !KB1_za_data[1] & NB1_cpu_instruction_master_read_data_valid_sdram_s1);

--U1L15 is std_1c20:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_readdata[2]~2440

--operation mode is normal

U1L15 = !Y1_internal_incoming_ext_ram_bus_data[2] & (Y1_cpu_instruction_master_read_data_valid_ext_ram_s1_shift_register[1] # Y1_cpu_instruction_master_read_data_valid_lan91c111_s1_shift_register[1]);

--U1_dbs_latent_8_reg_segment_0[2] is std_1c20:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|dbs_latent_8_reg_segment_0[2]

--operation mode is normal

U1_dbs_latent_8_reg_segment_0[2]_lut_out = Y1_internal_incoming_ext_ram_bus_data[2];

U1_dbs_latent_8_reg_segment_0[2] = DFFEAS(U1_dbs_latent_8_reg_segment_0[2]_lut_out, QC2__clk0, F1_data_out, , U1L175, , , , );

--U1L16 is std_1c20:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_readdata[2]~2441

--operation mode is normal

U1L16 = U1_dbs_latent_8_reg_segment_0[2] & (!KB1_za_data[2] & NB1_cpu_instruction_master_read_data_valid_sdram_s1) # !U1_dbs_latent_8_reg_segment_0[2] & (Y1_cpu_instruction_master_read_data_valid_ext_flash_s1_shift_register[1] # !KB1_za_data[2] & NB1_cpu_instruction_master_read_data_valid_sdram_s1);

--U1L18 is std_1c20:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_readdata[3]~2443

--operation mode is normal

U1L18 = !Y1_internal_incoming_ext_ram_bus_data[3] & (Y1_cpu_instruction_master_read_data_valid_ext_ram_s1_shift_register[1] # Y1_cpu_instruction_master_read_data_valid_lan91c111_s1_shift_register[1]);

--U1_dbs_latent_8_reg_segment_0[3] is std_1c20:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|dbs_latent_8_reg_segment_0[3]

--operation mode is normal

U1_dbs_latent_8_reg_segment_0[3]_lut_out = Y1_internal_incoming_ext_ram_bus_data[3];

U1_dbs_latent_8_reg_segment_0[3] = DFFEAS(U1_dbs_latent_8_reg_segment_0[3]_lut_out, QC2__clk0, F1_data_out, , U1L175, , , , );

--U1L19 is std_1c20:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_readdata[3]~2444

--operation mode is normal

U1L19 = U1_dbs_latent_8_reg_segment_0[3] & (!KB1_za_data[3] & NB1_cpu_instruction_master_read_data_valid_sdram_s1) # !U1_dbs_latent_8_reg_segment_0[3] & (Y1_cpu_instruction_master_read_data_valid_ext_flash_s1_shift_register[1] # !KB1_za_data[3] & NB1_cpu_instruction_master_read_data_valid_sdram_s1);

--U1L24 is std_1c20:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_readdata[5]~2446

--operation mode is normal

U1L24 = !Y1_internal_incoming_ext_ram_bus_data[5] & (Y1_cpu_instruction_master_read_data_valid_ext_ram_s1_shift_register[1] # Y1_cpu_instruction_master_read_data_valid_lan91c111_s1_shift_register[1]);

--U1_dbs_latent_8_reg_segment_0[5] is std_1c20:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|dbs_latent_8_reg_segment_0[5]

--operation mode is normal

U1_dbs_latent_8_reg_segment_0[5]_lut_out = Y1_internal_incoming_ext_ram_bus_data[5];

U1_dbs_latent_8_reg_segment_0[5] = DFFEAS(U1_dbs_latent_8_reg_segment_0[5]_lut_out, QC2__clk0, F1_data_out, , U1L175, , , , );

--U1L25 is std_1c20:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_readdata[5]~2447

--operation mode is normal

U1L25 = U1_dbs_latent_8_reg_segment_0[5] & (!KB1_za_data[5] & NB1_cpu_instruction_master_read_data_valid_sdram_s1) # !U1_dbs_latent_8_reg_segment_0[5] & (Y1_cpu_instruction_master_read_data_valid_ext_flash_s1_shift_register[1] # !KB1_za_data[5] & NB1_cpu_instruction_master_read_data_valid_sdram_s1);

--U1L86 is std_1c20:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_readdata[27]~2449

--operation mode is normal

U1L86 = Y1_cpu_instruction_master_read_data_valid_ext_flash_s1_shift_register[1] & (!KB1_za_data[27] & NB1_cpu_instruction_master_read_data_valid_sdram_s1 # !Y1_internal_incoming_ext_ram_bus_data[3]) # !Y1_cpu_instruction_master_read_data_valid_ext_flash_s1_shift_register[1] & (!KB1_za_data[27] & NB1_cpu_instruction_master_read_data_valid_sdram_s1);

--U1L87 is std_1c20:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_readdata[27]~2450

--operation mode is normal

U1L87 = !U1L86 & (Y1_internal_incoming_ext_ram_bus_data[27] # !Y1_cpu_instruction_master_read_data_valid_ext_ram_s1_shift_register[1] & !Y1_cpu_instruction_master_read_data_valid_lan91c111_s1_shift_register[1]);

--U1L88 is std_1c20:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_readdata[27]~2451

--operation mode is normal

U1L88 = U1L87 & (FE1_q_a[27] & !W1L1 # !X1_cpu_instruction_master_qualified_request_epcs_controller_epcs_control_port);

--U1L89 is std_1c20:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_readdata[28]~2453

--operation mode is normal

U1L89 = Y1_internal_incoming_ext_ram_bus_data[4] & (!KB1_za_data[28] & NB1_cpu_instruction_master_read_data_valid_sdram_s1) # !Y1_internal_incoming_ext_ram_bus_data[4] & (Y1_cpu_instruction_master_read_data_valid_ext_flash_s1_shift_register[1] # !KB1_za_data[28] & NB1_cpu_instruction_master_read_data_valid_sdram_s1);

--U1L90 is std_1c20:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_readdata[28]~2454

--operation mode is normal

U1L90 = !U1L89 & (Y1_internal_incoming_ext_ram_bus_data[28] # !Y1_cpu_instruction_master_read_data_valid_ext_ram_s1_shift_register[1] & !Y1_cpu_instruction_master_read_data_valid_lan91c111_s1_shift_register[1]);

--U1L91 is std_1c20:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_readdata[28]~2455

--operation mode is normal

U1L91 = U1L90 & (FE1_q_a[28] & !W1L1 # !X1_cpu_instruction_master_qualified_request_epcs_controller_epcs_control_port);

--U1L92 is std_1c20:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_readdata[29]~2457

--operation mode is normal

U1L92 = Y1_cpu_instruction_master_read_data_valid_ext_flash_s1_shift_register[1] & (!KB1_za_data[29] & NB1_cpu_instruction_master_read_data_valid_sdram_s1 # !Y1_internal_incoming_ext_ram_bus_data[5]) # !Y1_cpu_instruction_master_read_data_valid_ext_flash_s1_shift_register[1] & (!KB1_za_data[29] & NB1_cpu_instruction_master_read_data_valid_sdram_s1);

--U1L93 is std_1c20:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_readdata[29]~2458

--operation mode is normal

U1L93 = !U1L92 & (Y1_internal_incoming_ext_ram_bus_data[29] # !Y1_cpu_instruction_master_read_data_valid_ext_ram_s1_shift_register[1] & !Y1_cpu_instruction_master_read_data_valid_lan91c111_s1_shift_register[1]);

--U1L94 is std_1c20:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_readdata[29]~2459

--operation mode is normal

U1L94 = U1L93 & (FE1_q_a[29] & !W1L1 # !X1_cpu_instruction_master_qualified_request_epcs_controller_epcs_control_port);

--U1L95 is std_1c20:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_readdata[30]~2461

--operation mode is normal

U1L95 = Y1_internal_incoming_ext_ram_bus_data[6] & (!KB1_za_data[30] & NB1_cpu_instruction_master_read_data_valid_sdram_s1) # !Y1_internal_incoming_ext_ram_bus_data[6] & (Y1_cpu_instruction_master_read_data_valid_ext_flash_s1_shift_register[1] # !KB1_za_data[30] & NB1_cpu_instruction_master_read_data_valid_sdram_s1);

--U1L96 is std_1c20:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_readdata[30]~2462

--operation mode is normal

U1L96 = !U1L95 & (Y1_internal_incoming_ext_ram_bus_data[30] # !Y1_cpu_instruction_master_read_data_valid_ext_ram_s1_shift_register[1] & !Y1_cpu_instruction_master_read_data_valid_lan91c111_s1_shift_register[1]);

--U1L97 is std_1c20:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_readdata[30]~2463

--operation mode is normal

U1L97 = U1L96 & (FE1_q_a[30] & !W1L1 # !X1_cpu_instruction_master_qualified_request_epcs_controller_epcs_control_port);

--U1L98 is std_1c20:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_readdata[31]~2465

--operation mode is normal

U1L98 = Y1_cpu_instruction_master_read_data_valid_ext_flash_s1_shift_register[1] & (!KB1_za_data[31] & NB1_cpu_instruction_master_read_data_valid_sdram_s1 # !Y1_internal_incoming_ext_ram_bus_data[7]) # !Y1_cpu_instruction_master_read_data_valid_ext_flash_s1_shift_register[1] & (!KB1_za_data[31] & NB1_cpu_instruction_master_read_data_valid_sdram_s1);

--U1L99 is std_1c20:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_readdata[31]~2466

--operation mode is normal

U1L99 = !U1L98 & (Y1_internal_incoming_ext_ram_bus_data[31] # !Y1_cpu_instruction_master_read_data_valid_ext_ram_s1_shift_register[1] & !Y1_cpu_instruction_master_read_data_valid_lan91c111_s1_shift_register[1]);

--U1L100 is std_1c20:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_readdata[31]~2467

--operation mode is normal

U1L100 = U1L99 & (FE1_q_a[31] & !W1L1 # !X1_cpu_instruction_master_qualified_request_epcs_controller_epcs_control_port);

--YE1_delayed_unxrx_in_processxx3 is std_1c20:inst|uart1:the_uart1|uart1_rx:the_uart1_rx|delayed_unxrx_in_processxx3

--operation mode is normal

YE1_delayed_unxrx_in_processxx3_lut_out = YE1_unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[0];

YE1_delayed_unxrx_in_processxx3 = DFFEAS(YE1_delayed_unxrx_in_processxx3_lut_out, QC2__clk0, F1_data_out, , , , , , );

--YE1_unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[0] is std_1c20:inst|uart1:the_uart1|uart1_rx:the_uart1_rx|unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[0]

--operation mode is normal

YE1_unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[0]_lut_out = YE1_unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[1] # YE1_do_start_rx;

YE1_unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[0] = DFFEAS(YE1_unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[0]_lut_out, QC2__clk0, F1_data_out, , YE1L63, , , , );

--YE1_got_new_char is std_1c20:inst|uart1:the_uart1|uart1_rx:the_uart1_rx|got_new_char

--operation mode is normal

YE1_got_new_char = YE1_delayed_unxrx_in_processxx3 & (!YE1_unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[0]);

--YE1_unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[1] is std_1c20:inst|uart1:the_uart1|uart1_rx:the_uart1_rx|unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[1]

--operation mode is normal

YE1_unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[1]_lut_out = YE1_unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[2] # YE1_do_start_rx;

YE1_unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[1] = DFFEAS(YE1_unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[1]_lut_out, QC2__clk0, F1_data_out, , YE1L63, , , , );

--YE1_unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[8] is std_1c20:inst|uart1:the_uart1|uart1_rx:the_uart1_rx|unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[8]

--operation mode is normal

YE1_unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[8]_lut_out = YE1_unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[9] # YE1_do_start_rx;

YE1_unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[8] = DFFEAS(YE1_unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[8]_lut_out, QC2__clk0, F1_data_out, , YE1L63, , , , );

--YE1_unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[3] is std_1c20:inst|uart1:the_uart1|uart1_rx:the_uart1_rx|unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[3]

--operation mode is normal

YE1_unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[3]_lut_out = YE1_unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[4] # YE1_do_start_rx;

YE1_unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[3] = DFFEAS(YE1_unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[3]_lut_out, QC2__clk0, F1_data_out, , YE1L63, , , , );

--YE1L70 is std_1c20:inst|uart1:the_uart1|uart1_rx:the_uart1_rx|WideOr0~60

--operation mode is normal

YE1L70 = YE1_unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[0] # YE1_unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[1] # YE1_unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[8] # YE1_unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[3];

--YE1_unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[2] is std_1c20:inst|uart1:the_uart1|uart1_rx:the_uart1_rx|unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[2]

--operation mode is normal

YE1_unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[2]_lut_out = YE1_unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[3] # YE1_do_start_rx;

YE1_unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[2] = DFFEAS(YE1_unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[2]_lut_out, QC2__clk0, F1_data_out, , YE1L63, , , , );

--YE1_unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[4] is std_1c20:inst|uart1:the_uart1|uart1_rx:the_uart1_rx|unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[4]

--operation mode is normal

YE1_unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[4]_lut_out = YE1_unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[5] # YE1_do_start_rx;

YE1_unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[4] = DFFEAS(YE1_unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[4]_lut_out, QC2__clk0, F1_data_out, , YE1L63, , , , );

--YE1_unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[5] is std_1c20:inst|uart1:the_uart1|uart1_rx:the_uart1_rx|unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[5]

--operation mode is normal

YE1_unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[5]_lut_out = YE1_unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[6] # YE1_do_start_rx;

YE1_unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[5] = DFFEAS(YE1_unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[5]_lut_out, QC2__clk0, F1_data_out, , YE1L63, , , , );

--YE1_unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[6] is std_1c20:inst|uart1:the_uart1|uart1_rx:the_uart1_rx|unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[6]

--operation mode is normal

YE1_unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[6]_lut_out = YE1_unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[7] # YE1_do_start_rx;

YE1_unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[6] = DFFEAS(YE1_unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[6]_lut_out, QC2__clk0, F1_data_out, , YE1L63, , , , );

--YE1L71 is std_1c20:inst|uart1:the_uart1|uart1_rx:the_uart1_rx|WideOr0~61

--operation mode is normal

YE1L71 = YE1_unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[2] # YE1_unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[4] # YE1_unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[5] # YE1_unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[6];

--YE1_unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[7] is std_1c20:inst|uart1:the_uart1|uart1_rx:the_uart1_rx|unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[7]

--operation mode is normal

YE1_unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[7]_lut_out = YE1_unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[8] # YE1_do_start_rx;

YE1_unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[7] = DFFEAS(YE1_unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[7]_lut_out, QC2__clk0, F1_data_out, , YE1L63, , , , );

--YE1_unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[9] is std_1c20:inst|uart1:the_uart1|uart1_rx:the_uart1_rx|unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[9]

--operation mode is normal

YE1_unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[9]_lut_out = YE1_do_start_rx # YE1L1 & YE1_sync_rxd # !YE1L1 & (YE1_unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[9]);

YE1_unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[9] = DFFEAS(YE1_unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[9]_lut_out, QC2__clk0, F1_data_out, , , , , , );

--YE1L72 is std_1c20:inst|uart1:the_uart1|uart1_rx:the_uart1_rx|WideOr0~62

--operation mode is normal

YE1L72 = YE1L70 # YE1L71 # YE1_unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[7] # YE1_unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[9];

--RB1L209 is std_1c20:inst|sys_clk_timer:the_sys_clk_timer|snap_strobe~24

--operation mode is normal

RB1L209 = S1_M_alu_result[4] & RB1L7 & SB1_cpu_data_master_requests_sys_clk_timer_s1 & !S1_M_alu_result[3];

--M1_slave_readdata_p1[2] is std_1c20:inst|clock_1:the_clock_1|slave_readdata_p1[2]

--operation mode is normal

M1_slave_readdata_p1[2]_lut_out = M1_master_nativeaddress[0] & Q1_control_reg_out[2];

M1_slave_readdata_p1[2] = DFFEAS(M1_slave_readdata_p1[2]_lut_out, PLD_CLOCKINPUT[1], E1_data_out, , M1L22, , , , );

--J1_slave_readdata_p1[2] is std_1c20:inst|clock_0:the_clock_0|slave_readdata_p1[2]

--operation mode is normal

J1_slave_readdata_p1[2]_lut_out = J1_master_nativeaddress[0] & LB1_control_reg_out[2];

J1_slave_readdata_p1[2] = DFFEAS(J1_slave_readdata_p1[2]_lut_out, PLD_CLKFB, D1_data_out, , J1L22, , , , );

--GE1L37Q is std_1c20:inst|jtag_uart:the_jtag_uart|alt_jtag_atlantic:jtag_uart_alt_jtag_atlantic|t_ena~reg0

--operation mode is normal

GE1L37Q = AMPP_FUNCTION(QC2__clk0, GE1_read_write1, GE1_read_write2, GE1L37Q, GE1L38, F1_data_out);

--BB1_wr_rfifo is std_1c20:inst|jtag_uart:the_jtag_uart|wr_rfifo

--operation mode is normal

BB1_wr_rfifo = GE1L37Q & (!NE2_b_full);

--BB1L42 is std_1c20:inst|jtag_uart:the_jtag_uart|fifo_rd~34

--operation mode is normal

BB1L42 = S1_internal_d_read & (!S1_M_alu_result[2]);

--BB1L43 is std_1c20:inst|jtag_uart:the_jtag_uart|fifo_rd~35

--operation mode is normal

BB1L43 = UB1L9 & CB1L2 & BB1L54 & BB1L42;

--BB1L61 is std_1c20:inst|jtag_uart:the_jtag_uart|rvalid~26

--operation mode is normal

BB1L61 = NE2_b_non_empty & BB1L43;

--GE1_wdata[2] is std_1c20:inst|jtag_uart:the_jtag_uart|alt_jtag_atlantic:jtag_uart_alt_jtag_atlantic|wdata[2]

--operation mode is normal

GE1_wdata[2] = AMPP_FUNCTION(A1L5, GE1_td_shift[6], !C1_CLR_SIGNAL, GE1L74);

--QE4_safe_q[0] is std_1c20:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_r:the_jtag_uart_scfifo_r|scfifo:rfifo|scfifo_jf21:auto_generated|a_dpfifo_ml21:dpfifo|cntr_rd8:wr_ptr|safe_q[0]

--operation mode is arithmetic

QE4_safe_q[0]_lut_out = QE4_safe_q[0] $ BB1_wr_rfifo;

QE4_safe_q[0] = DFFEAS(QE4_safe_q[0]_lut_out, QC2__clk0, F1_data_out, , , , , , );

--QE4L2 is std_1c20:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_r:the_jtag_uart_scfifo_r|scfifo:rfifo|scfifo_jf21:auto_generated|a_dpfifo_ml21:dpfifo|cntr_rd8:wr_ptr|counter_cella0~COUT

--operation mode is arithmetic

QE4L2 = CARRY(QE4_safe_q[0]);

--QE4_safe_q[1] is std_1c20:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_r:the_jtag_uart_scfifo_r|scfifo:rfifo|scfifo_jf21:auto_generated|a_dpfifo_ml21:dpfifo|cntr_rd8:wr_ptr|safe_q[1]

--operation mode is arithmetic

QE4_safe_q[1]_carry_eqn = QE4L2;

QE4_safe_q[1]_lut_out = QE4_safe_q[1] $ (BB1_wr_rfifo & QE4_safe_q[1]_carry_eqn);

QE4_safe_q[1] = DFFEAS(QE4_safe_q[1]_lut_out, QC2__clk0, F1_data_out, , , , , , );

--QE4L4 is std_1c20:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_r:the_jtag_uart_scfifo_r|scfifo:rfifo|scfifo_jf21:auto_generated|a_dpfifo_ml21:dpfifo|cntr_rd8:wr_ptr|counter_cella1~COUT

--operation mode is arithmetic

QE4L4 = CARRY(!QE4L2 # !QE4_safe_q[1]);

--QE4_safe_q[2] is std_1c20:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_r:the_jtag_uart_scfifo_r|scfifo:rfifo|scfifo_jf21:auto_generated|a_dpfifo_ml21:dpfifo|cntr_rd8:wr_ptr|safe_q[2]

--operation mode is arithmetic

QE4_safe_q[2]_carry_eqn = QE4L4;

QE4_safe_q[2]_lut_out = QE4_safe_q[2] $ (BB1_wr_rfifo & !QE4_safe_q[2]_carry_eqn);

QE4_safe_q[2] = DFFEAS(QE4_safe_q[2]_lut_out, QC2__clk0, F1_data_out, , , , , , );

--QE4L6 is std_1c20:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_r:the_jtag_uart_scfifo_r|scfifo:rfifo|scfifo_jf21:auto_generated|a_dpfifo_ml21:dpfifo|cntr_rd8:wr_ptr|counter_cella2~COUT

--operation mode is arithmetic

QE4L6 = CARRY(QE4_safe_q[2] & (!QE4L4));

--QE4_safe_q[3] is std_1c20:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_r:the_jtag_uart_scfifo_r|scfifo:rfifo|scfifo_jf21:auto_generated|a_dpfifo_ml21:dpfifo|cntr_rd8:wr_ptr|safe_q[3]

--operation mode is arithmetic

QE4_safe_q[3]_carry_eqn = QE4L6;

QE4_safe_q[3]_lut_out = QE4_safe_q[3] $ (BB1_wr_rfifo & QE4_safe_q[3]_carry_eqn);

QE4_safe_q[3] = DFFEAS(QE4_safe_q[3]_lut_out, QC2__clk0, F1_data_out, , , , , , );

--QE4L8 is std_1c20:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_r:the_jtag_uart_scfifo_r|scfifo:rfifo|scfifo_jf21:auto_generated|a_dpfifo_ml21:dpfifo|cntr_rd8:wr_ptr|counter_cella3~COUT

--operation mode is arithmetic

QE4L8 = CARRY(!QE4L6 # !QE4_safe_q[3]);

--QE4_safe_q[4] is std_1c20:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_r:the_jtag_uart_scfifo_r|scfifo:rfifo|scfifo_jf21:auto_generated|a_dpfifo_ml21:dpfifo|cntr_rd8:wr_ptr|safe_q[4]

--operation mode is arithmetic

QE4_safe_q[4]_carry_eqn = QE4L8;

QE4_safe_q[4]_lut_out = QE4_safe_q[4] $ (BB1_wr_rfifo & !QE4_safe_q[4]_carry_eqn);

QE4_safe_q[4] = DFFEAS(QE4_safe_q[4]_lut_out, QC2__clk0, F1_data_out, , , , , , );

--QE4L10 is std_1c20:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_r:the_jtag_uart_scfifo_r|scfifo:rfifo|scfifo_jf21:auto_generated|a_dpfifo_ml21:dpfifo|cntr_rd8:wr_ptr|counter_cella4~COUT

--operation mode is arithmetic

QE4L10 = CARRY(QE4_safe_q[4] & (!QE4L8));

--QE4_safe_q[5] is std_1c20:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_r:the_jtag_uart_scfifo_r|scfifo:rfifo|scfifo_jf21:auto_generated|a_dpfifo_ml21:dpfifo|cntr_rd8:wr_ptr|safe_q[5]

--operation mode is normal

QE4_safe_q[5]_carry_eqn = QE4L10;

QE4_safe_q[5]_lut_out = QE4_safe_q[5] $ (BB1_wr_rfifo & QE4_safe_q[5]_carry_eqn);

QE4_safe_q[5] = DFFEAS(QE4_safe_q[5]_lut_out, QC2__clk0, F1_data_out, , , , , , );

--QE3_safe_q[0] is std_1c20:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_r:the_jtag_uart_scfifo_r|scfifo:rfifo|scfifo_jf21:auto_generated|a_dpfifo_ml21:dpfifo|cntr_rd8:rd_ptr_count|safe_q[0]

--operation mode is arithmetic

QE3_safe_q[0]_lut_out = QE3_safe_q[0] $ BB1L61;

QE3_safe_q[0] = DFFEAS(QE3_safe_q[0]_lut_out, QC2__clk0, F1_data_out, , , , , , );

--QE3L2 is std_1c20:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_r:the_jtag_uart_scfifo_r|scfifo:rfifo|scfifo_jf21:auto_generated|a_dpfifo_ml21:dpfifo|cntr_rd8:rd_ptr_count|counter_cella0~COUT

--operation mode is arithmetic

QE3L2 = CARRY(QE3_safe_q[0]);

--QE3_safe_q[1] is std_1c20:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_r:the_jtag_uart_scfifo_r|scfifo:rfifo|scfifo_jf21:auto_generated|a_dpfifo_ml21:dpfifo|cntr_rd8:rd_ptr_count|safe_q[1]

--operation mode is arithmetic

QE3_safe_q[1]_carry_eqn = QE3L2;

QE3_safe_q[1]_lut_out = QE3_safe_q[1] $ (BB1L61 & QE3_safe_q[1]_carry_eqn);

QE3_safe_q[1] = DFFEAS(QE3_safe_q[1]_lut_out, QC2__clk0, F1_data_out, , , , , , );

--QE3L4 is std_1c20:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_r:the_jtag_uart_scfifo_r|scfifo:rfifo|scfifo_jf21:auto_generated|a_dpfifo_ml21:dpfifo|cntr_rd8:rd_ptr_count|counter_cella1~COUT

--operation mode is arithmetic

QE3L4 = CARRY(!QE3L2 # !QE3_safe_q[1]);

--QE3_safe_q[2] is std_1c20:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_r:the_jtag_uart_scfifo_r|scfifo:rfifo|scfifo_jf21:auto_generated|a_dpfifo_ml21:dpfifo|cntr_rd8:rd_ptr_count|safe_q[2]

--operation mode is arithmetic

QE3_safe_q[2]_carry_eqn = QE3L4;

QE3_safe_q[2]_lut_out = QE3_safe_q[2] $ (BB1L61 & !QE3_safe_q[2]_carry_eqn);

QE3_safe_q[2] = DFFEAS(QE3_safe_q[2]_lut_out, QC2__clk0, F1_data_out, , , , , , );

--QE3L6 is std_1c20:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_r:the_jtag_uart_scfifo_r|scfifo:rfifo|scfifo_jf21:auto_generated|a_dpfifo_ml21:dpfifo|cntr_rd8:rd_ptr_count|counter_cella2~COUT

--operation mode is arithmetic

QE3L6 = CARRY(QE3_safe_q[2] & (!QE3L4));

--QE3_safe_q[3] is std_1c20:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_r:the_jtag_uart_scfifo_r|scfifo:rfifo|scfifo_jf21:auto_generated|a_dpfifo_ml21:dpfifo|cntr_rd8:rd_ptr_count|safe_q[3]

--operation mode is arithmetic

QE3_safe_q[3]_carry_eqn = QE3L6;

QE3_safe_q[3]_lut_out = QE3_safe_q[3] $ (BB1L61 & QE3_safe_q[3]_carry_eqn);

QE3_safe_q[3] = DFFEAS(QE3_safe_q[3]_lut_out, QC2__clk0, F1_data_out, , , , , , );

--QE3L8 is std_1c20:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_r:the_jtag_uart_scfifo_r|scfifo:rfifo|scfifo_jf21:auto_generated|a_dpfifo_ml21:dpfifo|cntr_rd8:rd_ptr_count|counter_cella3~COUT

--operation mode is arithmetic

QE3L8 = CARRY(!QE3L6 # !QE3_safe_q[3]);

--QE3_safe_q[4] is std_1c20:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_r:the_jtag_uart_scfifo_r|scfifo:rfifo|scfifo_jf21:auto_generated|a_dpfifo_ml21:dpfifo|cntr_rd8:rd_ptr_count|safe_q[4]

--operation mode is arithmetic

QE3_safe_q[4]_carry_eqn = QE3L8;

QE3_safe_q[4]_lut_out = QE3_safe_q[4] $ (BB1L61 & !QE3_safe_q[4]_carry_eqn);

QE3_safe_q[4] = DFFEAS(QE3_safe_q[4]_lut_out, QC2__clk0, F1_data_out, , , , , , );

--QE3L10 is std_1c20:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_r:the_jtag_uart_scfifo_r|scfifo:rfifo|scfifo_jf21:auto_generated|a_dpfifo_ml21:dpfifo|cntr_rd8:rd_ptr_count|counter_cella4~COUT

--operation mode is arithmetic

QE3L10 = CARRY(QE3_safe_q[4] & (!QE3L8));

--QE3_safe_q[5] is std_1c20:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_r:the_jtag_uart_scfifo_r|scfifo:rfifo|scfifo_jf21:auto_generated|a_dpfifo_ml21:dpfifo|cntr_rd8:rd_ptr_count|safe_q[5]

--operation mode is normal

QE3_safe_q[5]_carry_eqn = QE3L10;

QE3_safe_q[5]_lut_out = QE3_safe_q[5] $ (BB1L61 & QE3_safe_q[5]_carry_eqn);

QE3_safe_q[5] = DFFEAS(QE3_safe_q[5]_lut_out, QC2__clk0, F1_data_out, , , , , , );

--Z1L208 is std_1c20:inst|high_res_timer:the_high_res_timer|snap_strobe~18

--operation mode is normal

Z1L208 = S1_M_alu_result[4] & RB1L7 & AB1_cpu_data_master_requests_high_res_timer_s1 & !S1_M_alu_result[3];

--DE1_wr_strobe is std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|wr_strobe

--operation mode is normal

DE1_wr_strobe_lut_out = DE1L141;

DE1_wr_strobe = DFFEAS(DE1_wr_strobe_lut_out, QC2__clk0, F1_data_out, , , , , , );

--DE1_endofpacketvalue_wr_strobe is std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|endofpacketvalue_wr_strobe

--operation mode is normal

DE1_endofpacketvalue_wr_strobe = X1L15 & X1L16 & DE1_wr_strobe & !X1L14;

--DE1_epcs_slave_select_holding_reg[2] is std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|epcs_slave_select_holding_reg[2]

--operation mode is normal

DE1_epcs_slave_select_holding_reg[2]_lut_out = S1_M_st_data[2];

DE1_epcs_slave_select_holding_reg[2] = DFFEAS(DE1_epcs_slave_select_holding_reg[2]_lut_out, QC2__clk0, F1_data_out, , DE1_slaveselect_wr_strobe, , , , );

--DE1_write_shift_reg is std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|write_shift_reg

--operation mode is normal

DE1_write_shift_reg = DE1_tx_holding_primed & (!DE1_transmitting);

--DE1_control_wr_strobe is std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|control_wr_strobe

--operation mode is normal

DE1_control_wr_strobe = X1L14 & X1L15 & DE1_wr_strobe & !X1L16;

--DE1L142 is std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|process6~2

--operation mode is normal

DE1L142 = DE1_write_shift_reg # S1_M_st_data[10] & DE1_control_wr_strobe & !DE1_SSO_reg;

--DE1_shift_reg[2] is std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|shift_reg[2]

--operation mode is normal

DE1_shift_reg[2]_lut_out = DE1_SCLK_reg & DE1_shift_reg[1] # !DE1_SCLK_reg & (DE1L169);

DE1_shift_reg[2] = DFFEAS(DE1_shift_reg[2]_lut_out, QC2__clk0, F1_data_out, , , DE1L169, , , !DE1_slowcount[0]);

--DE1_slowcount[0] is std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|slowcount[0]

--operation mode is normal

DE1_slowcount[0]_lut_out = DE1_transmitting & (!DE1_slowcount[0]);

DE1_slowcount[0] = DFFEAS(DE1_slowcount[0]_lut_out, QC2__clk0, F1_data_out, , , , , , );

--DE1_state[4] is std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|state[4]

--operation mode is normal

DE1_state[4]_lut_out = DE1L16 & (!DE1L117 # !DE1_state[0] # !DE1_state[4]);

DE1_state[4] = DFFEAS(DE1_state[4]_lut_out, QC2__clk0, F1_data_out, , DE1L143, , , , );

--DE1_state[0] is std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|state[0]

--operation mode is normal

DE1_state[0]_lut_out = DE1L17;

DE1_state[0] = DFFEAS(DE1_state[0]_lut_out, QC2__clk0, F1_data_out, , DE1L143, , , , );

--DE1_state[1] is std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|state[1]

--operation mode is normal

DE1_state[1]_lut_out = DE1L19 & (!DE1L117 # !DE1_state[0] # !DE1_state[4]);

DE1_state[1] = DFFEAS(DE1_state[1]_lut_out, QC2__clk0, F1_data_out, , DE1L143, , , , );

--DE1_state[2] is std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|state[2]

--operation mode is normal

DE1_state[2]_lut_out = DE1L21;

DE1_state[2] = DFFEAS(DE1_state[2]_lut_out, QC2__clk0, F1_data_out, , DE1L143, , , , );

--DE1_state[3] is std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|state[3]

--operation mode is normal

DE1_state[3]_lut_out = DE1L23;

DE1_state[3] = DFFEAS(DE1_state[3]_lut_out, QC2__clk0, F1_data_out, , DE1L143, , , , );

--DE1L117 is std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|Equal9~103

--operation mode is normal

DE1L117 = !DE1_state[1] & !DE1_state[2] & !DE1_state[3];

--DE1L156 is std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|rx_holding_reg[7]~7

--operation mode is normal

DE1L156 = DE1_slowcount[0] & DE1_state[4] & DE1_state[0] & DE1L117;

--SD1L192 is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|take_action_ocimem_b~30

--operation mode is normal

SD1L192 = AMPP_FUNCTION(SD1_internal_jdo1[35], SD1_jxdr, SD1_ir[0], SD1_ir[1]);

--SD1_internal_jdo1[3] is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|internal_jdo1[3]

--operation mode is normal

SD1_internal_jdo1[3] = AMPP_FUNCTION(A1L8, SD1_sr[3], VCC, SD1L145);

--RD1_MonAReg[10] is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|MonAReg[10]

--operation mode is normal

RD1_MonAReg[10] = AMPP_FUNCTION(QC2__clk0, SD1_internal_jdo1[17], RD1L81, RD1L18, SD1L191, !C1_CLR_SIGNAL, SD1L193);

--RD1L28 is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|internal_MonDReg[1]~7326

--operation mode is normal

RD1L28 = AMPP_FUNCTION(CE1_q_b[0], RD1_MonAReg[10]);

--RD1_MonRd1 is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|MonRd1

--operation mode is normal

RD1_MonRd1 = AMPP_FUNCTION(QC2__clk0, RD1_MonRd, !C1_CLR_SIGNAL);

--RD1L29 is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|internal_MonDReg[1]~7328

--operation mode is normal

RD1L29 = AMPP_FUNCTION(SD1L192, RD1_MonRd1, SD1L190);

--RD1L19 is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|Equal0~98

--operation mode is normal

RD1L19 = AMPP_FUNCTION(RD1_MonAReg[2], RD1_MonAReg[3], RD1_MonAReg[4]);

--SD1_internal_jdo1[4] is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|internal_jdo1[4]

--operation mode is normal

SD1_internal_jdo1[4] = AMPP_FUNCTION(A1L8, SD1_sr[4], VCC, SD1L145);

--RD1L30 is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|internal_MonDReg[1]~7329

--operation mode is normal

RD1L30 = AMPP_FUNCTION(RD1_MonRd1, SD1L192);

--RD1L20 is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|Equal0~99

--operation mode is normal

RD1L20 = AMPP_FUNCTION(RD1_MonAReg[4], RD1_MonAReg[2], RD1_MonAReg[3]);

--SD1_internal_jdo1[5] is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|internal_jdo1[5]

--operation mode is normal

SD1_internal_jdo1[5] = AMPP_FUNCTION(A1L8, SD1_sr[5], VCC, SD1L145);

--RD1L1 is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|A_WE_StdLogicVector~140

--operation mode is normal

RD1L1 = AMPP_FUNCTION(RD1_MonAReg[2], RD1_MonAReg[4], RD1_MonAReg[3]);

--SD1_internal_jdo1[6] is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|internal_jdo1[6]

--operation mode is normal

SD1_internal_jdo1[6] = AMPP_FUNCTION(A1L8, SD1_sr[6], VCC, SD1L145);

--SD1_internal_jdo1[7] is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|internal_jdo1[7]

--operation mode is normal

SD1_internal_jdo1[7] = AMPP_FUNCTION(A1L8, SD1_sr[7], VCC, SD1L145);

--RD1L21 is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|Equal0~100

--operation mode is normal

RD1L21 = AMPP_FUNCTION(RD1_MonAReg[2], RD1_MonAReg[3], RD1_MonAReg[4]);

--SD1_internal_jdo1[8] is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|internal_jdo1[8]

--operation mode is normal

SD1_internal_jdo1[8] = AMPP_FUNCTION(A1L8, SD1_sr[8], VCC, SD1L145);

--SD1_internal_jdo1[9] is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|internal_jdo1[9]

--operation mode is normal

SD1_internal_jdo1[9] = AMPP_FUNCTION(A1L8, SD1_sr[9], VCC, SD1L145);

--SD1_internal_jdo1[10] is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|internal_jdo1[10]

--operation mode is normal

SD1_internal_jdo1[10] = AMPP_FUNCTION(A1L8, SD1_sr[10], VCC, SD1L145);

--SD1_internal_jdo1[26] is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|internal_jdo1[26]

--operation mode is normal

SD1_internal_jdo1[26] = AMPP_FUNCTION(A1L8, SD1_sr[26], VCC, SD1L145);

--RD1L2 is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|Add0~132

--operation mode is arithmetic

RD1L2 = AMPP_FUNCTION(RD1_MonAReg[2]);

--RD1L3 is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|Add0~133

--operation mode is arithmetic

RD1L3 = AMPP_FUNCTION(RD1_MonAReg[2]);

--RD1L73 is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|MonAReg~1144

--operation mode is normal

RD1L73 = AMPP_FUNCTION(RD1L2, RD1_MonAReg[2], SD1L192);

--SD1L193 is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|take_no_action_ocimem_a~20

--operation mode is normal

SD1L193 = AMPP_FUNCTION(SD1L190, SD1_internal_jdo1[34]);

--SD1_internal_jdo1[27] is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|internal_jdo1[27]

--operation mode is normal

SD1_internal_jdo1[27] = AMPP_FUNCTION(A1L8, SD1_sr[27], VCC, SD1L145);

--RD1L4 is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|Add0~134

--operation mode is arithmetic

RD1L4 = AMPP_FUNCTION(RD1_MonAReg[3], RD1L3);

--RD1L5 is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|Add0~135

--operation mode is arithmetic

RD1L5 = AMPP_FUNCTION(RD1_MonAReg[3], RD1L3);

--RD1L74 is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|MonAReg~1145

--operation mode is normal

RD1L74 = AMPP_FUNCTION(RD1L4, RD1_MonAReg[3], SD1L192);

--SD1_internal_jdo1[28] is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|internal_jdo1[28]

--operation mode is normal

SD1_internal_jdo1[28] = AMPP_FUNCTION(A1L8, SD1_sr[28], VCC, SD1L145);

--RD1L6 is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|Add0~136

--operation mode is arithmetic

RD1L6 = AMPP_FUNCTION(RD1_MonAReg[4], RD1L5);

--RD1L7 is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|Add0~137

--operation mode is arithmetic

RD1L7 = AMPP_FUNCTION(RD1_MonAReg[4], RD1L5);

--RD1L75 is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|MonAReg~1146

--operation mode is normal

RD1L75 = AMPP_FUNCTION(RD1L6, RD1_MonAReg[4], SD1L192);

--SD1_internal_jdo1[29] is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|internal_jdo1[29]

--operation mode is normal

SD1_internal_jdo1[29] = AMPP_FUNCTION(A1L8, SD1_sr[29], VCC, SD1L145);

--RD1L8 is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|Add0~138

--operation mode is arithmetic

RD1L8 = AMPP_FUNCTION(RD1_MonAReg[5], RD1L7);

--RD1L9 is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|Add0~139

--operation mode is arithmetic

RD1L9 = AMPP_FUNCTION(RD1_MonAReg[5], RD1L7);

--RD1L76 is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|MonAReg~1147

--operation mode is normal

RD1L76 = AMPP_FUNCTION(RD1L8, RD1_MonAReg[5], SD1L192);

--SD1_internal_jdo1[30] is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|internal_jdo1[30]

--operation mode is normal

SD1_internal_jdo1[30] = AMPP_FUNCTION(A1L8, SD1_sr[30], VCC, SD1L145);

--RD1L10 is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|Add0~140

--operation mode is arithmetic

RD1L10 = AMPP_FUNCTION(RD1_MonAReg[6], RD1L9);

--RD1L11 is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|Add0~141

--operation mode is arithmetic

RD1L11 = AMPP_FUNCTION(RD1_MonAReg[6], RD1L9);

--RD1L77 is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|MonAReg~1148

--operation mode is normal

RD1L77 = AMPP_FUNCTION(RD1L10, RD1_MonAReg[6], SD1L192);

--SD1_internal_jdo1[31] is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|internal_jdo1[31]

--operation mode is normal

SD1_internal_jdo1[31] = AMPP_FUNCTION(A1L8, SD1_sr[31], VCC, SD1L145);

--RD1L12 is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|Add0~142

--operation mode is arithmetic

RD1L12 = AMPP_FUNCTION(RD1_MonAReg[7], RD1L11);

--RD1L13 is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|Add0~143

--operation mode is arithmetic

RD1L13 = AMPP_FUNCTION(RD1_MonAReg[7], RD1L11);

--RD1L78 is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|MonAReg~1149

--operation mode is normal

RD1L78 = AMPP_FUNCTION(RD1L12, RD1_MonAReg[7], SD1L192);

--SD1_internal_jdo1[32] is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|internal_jdo1[32]

--operation mode is normal

SD1_internal_jdo1[32] = AMPP_FUNCTION(A1L8, SD1_sr[32], VCC, SD1L145);

--RD1L14 is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|Add0~144

--operation mode is arithmetic

RD1L14 = AMPP_FUNCTION(RD1_MonAReg[8], RD1L13);

--RD1L15 is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|Add0~145

--operation mode is arithmetic

RD1L15 = AMPP_FUNCTION(RD1_MonAReg[8], RD1L13);

--RD1L79 is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|MonAReg~1150

--operation mode is normal

RD1L79 = AMPP_FUNCTION(RD1L14, RD1_MonAReg[8], SD1L192);

--SD1_internal_jdo1[33] is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|internal_jdo1[33]

--operation mode is normal

SD1_internal_jdo1[33] = AMPP_FUNCTION(A1L8, SD1_sr[33], VCC, SD1L145);

--RD1L16 is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|Add0~146

--operation mode is arithmetic

RD1L16 = AMPP_FUNCTION(RD1_MonAReg[9], RD1L15);

--RD1L17 is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|Add0~147

--operation mode is arithmetic

RD1L17 = AMPP_FUNCTION(RD1_MonAReg[9], RD1L15);

--RD1L80 is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|MonAReg~1151

--operation mode is normal

RD1L80 = AMPP_FUNCTION(RD1L16, RD1_MonAReg[9], SD1L192);

--RD1L22 is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|Equal0~101

--operation mode is normal

RD1L22 = AMPP_FUNCTION(RD1_MonAReg[3], RD1_MonAReg[2], RD1_MonAReg[4]);

--SD1_internal_jdo1[24] is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|internal_jdo1[24]

--operation mode is normal

SD1_internal_jdo1[24] = AMPP_FUNCTION(A1L8, SD1_sr[24], VCC, SD1L145);

--U1_dbs_latent_8_reg_segment_1[4] is std_1c20:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|dbs_latent_8_reg_segment_1[4]

--operation mode is normal

U1_dbs_latent_8_reg_segment_1[4]_lut_out = Y1_internal_incoming_ext_ram_bus_data[4];

U1_dbs_latent_8_reg_segment_1[4] = DFFEAS(U1_dbs_latent_8_reg_segment_1[4]_lut_out, QC2__clk0, F1_data_out, , U1L176, , , , );

--U1L42 is std_1c20:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_readdata[12]~2469

--operation mode is normal

U1L42 = U1_dbs_latent_8_reg_segment_1[4] & (!KB1_za_data[12] & NB1_cpu_instruction_master_read_data_valid_sdram_s1) # !U1_dbs_latent_8_reg_segment_1[4] & (Y1_cpu_instruction_master_read_data_valid_ext_flash_s1_shift_register[1] # !KB1_za_data[12] & NB1_cpu_instruction_master_read_data_valid_sdram_s1);

--U1L43 is std_1c20:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_readdata[12]~2470

--operation mode is normal

U1L43 = !U1L42 & (Y1_internal_incoming_ext_ram_bus_data[12] # !Y1_cpu_instruction_master_read_data_valid_ext_ram_s1_shift_register[1] & !Y1_cpu_instruction_master_read_data_valid_lan91c111_s1_shift_register[1]);

--U1L44 is std_1c20:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_readdata[12]~2471

--operation mode is normal

U1L44 = U1L43 & (U1L117 # !X1_cpu_instruction_master_qualified_request_epcs_controller_epcs_control_port);

--U1_dbs_latent_8_reg_segment_1[5] is std_1c20:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|dbs_latent_8_reg_segment_1[5]

--operation mode is normal

U1_dbs_latent_8_reg_segment_1[5]_lut_out = Y1_internal_incoming_ext_ram_bus_data[5];

U1_dbs_latent_8_reg_segment_1[5] = DFFEAS(U1_dbs_latent_8_reg_segment_1[5]_lut_out, QC2__clk0, F1_data_out, , U1L176, , , , );

--U1L45 is std_1c20:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_readdata[13]~2473

--operation mode is normal

U1L45 = U1_dbs_latent_8_reg_segment_1[5] & (!KB1_za_data[13] & NB1_cpu_instruction_master_read_data_valid_sdram_s1) # !U1_dbs_latent_8_reg_segment_1[5] & (Y1_cpu_instruction_master_read_data_valid_ext_flash_s1_shift_register[1] # !KB1_za_data[13] & NB1_cpu_instruction_master_read_data_valid_sdram_s1);

--U1L46 is std_1c20:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_readdata[13]~2474

--operation mode is normal

U1L46 = !U1L45 & (Y1_internal_incoming_ext_ram_bus_data[13] # !Y1_cpu_instruction_master_read_data_valid_ext_ram_s1_shift_register[1] & !Y1_cpu_instruction_master_read_data_valid_lan91c111_s1_shift_register[1]);

--U1L47 is std_1c20:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_readdata[13]~2475

--operation mode is normal

U1L47 = U1L46 & (U1L116 # !X1_cpu_instruction_master_qualified_request_epcs_controller_epcs_control_port);

--U1_dbs_latent_8_reg_segment_1[3] is std_1c20:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|dbs_latent_8_reg_segment_1[3]

--operation mode is normal

U1_dbs_latent_8_reg_segment_1[3]_lut_out = Y1_internal_incoming_ext_ram_bus_data[3];

U1_dbs_latent_8_reg_segment_1[3] = DFFEAS(U1_dbs_latent_8_reg_segment_1[3]_lut_out, QC2__clk0, F1_data_out, , U1L176, , , , );

--U1L39 is std_1c20:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_readdata[11]~2477

--operation mode is normal

U1L39 = U1_dbs_latent_8_reg_segment_1[3] & (!KB1_za_data[11] & NB1_cpu_instruction_master_read_data_valid_sdram_s1) # !U1_dbs_latent_8_reg_segment_1[3] & (Y1_cpu_instruction_master_read_data_valid_ext_flash_s1_shift_register[1] # !KB1_za_data[11] & NB1_cpu_instruction_master_read_data_valid_sdram_s1);

--U1L40 is std_1c20:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_readdata[11]~2478

--operation mode is normal

U1L40 = !U1L39 & (Y1_internal_incoming_ext_ram_bus_data[11] # !Y1_cpu_instruction_master_read_data_valid_ext_ram_s1_shift_register[1] & !Y1_cpu_instruction_master_read_data_valid_lan91c111_s1_shift_register[1]);

--U1L41 is std_1c20:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_readdata[11]~2479

--operation mode is normal

U1L41 = U1L40 & (U1L118 # !X1_cpu_instruction_master_qualified_request_epcs_controller_epcs_control_port);

--U1_dbs_latent_8_reg_segment_1[6] is std_1c20:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|dbs_latent_8_reg_segment_1[6]

--operation mode is normal

U1_dbs_latent_8_reg_segment_1[6]_lut_out = Y1_internal_incoming_ext_ram_bus_data[6];

U1_dbs_latent_8_reg_segment_1[6] = DFFEAS(U1_dbs_latent_8_reg_segment_1[6]_lut_out, QC2__clk0, F1_data_out, , U1L176, , , , );

--U1L48 is std_1c20:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_readdata[14]~2481

--operation mode is normal

U1L48 = U1_dbs_latent_8_reg_segment_1[6] & (!KB1_za_data[14] & NB1_cpu_instruction_master_read_data_valid_sdram_s1) # !U1_dbs_latent_8_reg_segment_1[6] & (Y1_cpu_instruction_master_read_data_valid_ext_flash_s1_shift_register[1] # !KB1_za_data[14] & NB1_cpu_instruction_master_read_data_valid_sdram_s1);

--U1L49 is std_1c20:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_readdata[14]~2482

--operation mode is normal

U1L49 = !U1L48 & (Y1_internal_incoming_ext_ram_bus_data[14] # !Y1_cpu_instruction_master_read_data_valid_ext_ram_s1_shift_register[1] & !Y1_cpu_instruction_master_read_data_valid_lan91c111_s1_shift_register[1]);

--U1L50 is std_1c20:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_readdata[14]~2483

--operation mode is normal

U1L50 = U1L49 & (U1L115 # !X1_cpu_instruction_master_qualified_request_epcs_controller_epcs_control_port);

--U1_dbs_latent_8_reg_segment_2[5] is std_1c20:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|dbs_latent_8_reg_segment_2[5]

--operation mode is normal

U1_dbs_latent_8_reg_segment_2[5]_lut_out = Y1_internal_incoming_ext_ram_bus_data[5];

U1_dbs_latent_8_reg_segment_2[5] = DFFEAS(U1_dbs_latent_8_reg_segment_2[5]_lut_out, QC2__clk0, F1_data_out, , U1L177, , , , );

--U1L68 is std_1c20:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_readdata[21]~2485

--operation mode is normal

U1L68 = U1_dbs_latent_8_reg_segment_2[5] & (!KB1_za_data[21] & NB1_cpu_instruction_master_read_data_valid_sdram_s1) # !U1_dbs_latent_8_reg_segment_2[5] & (Y1_cpu_instruction_master_read_data_valid_ext_flash_s1_shift_register[1] # !KB1_za_data[21] & NB1_cpu_instruction_master_read_data_valid_sdram_s1);

--U1L69 is std_1c20:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_readdata[21]~2486

--operation mode is normal

U1L69 = !U1L68 & (Y1_internal_incoming_ext_ram_bus_data[21] # !Y1_cpu_instruction_master_read_data_valid_ext_ram_s1_shift_register[1] & !Y1_cpu_instruction_master_read_data_valid_lan91c111_s1_shift_register[1]);

--U1L70 is std_1c20:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_readdata[21]~2487

--operation mode is normal

U1L70 = U1L69 & (FE1_q_a[21] & !W1L1 # !X1_cpu_instruction_master_qualified_request_epcs_controller_epcs_control_port);

--U1_dbs_latent_8_reg_segment_2[0] is std_1c20:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|dbs_latent_8_reg_segment_2[0]

--operation mode is normal

U1_dbs_latent_8_reg_segment_2[0]_lut_out = Y1_internal_incoming_ext_ram_bus_data[0];

U1_dbs_latent_8_reg_segment_2[0] = DFFEAS(U1_dbs_latent_8_reg_segment_2[0]_lut_out, QC2__clk0, F1_data_out, , U1L177, , , , );

--U1L53 is std_1c20:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_readdata[16]~2489

--operation mode is normal

U1L53 = U1_dbs_latent_8_reg_segment_2[0] & (!KB1_za_data[16] & NB1_cpu_instruction_master_read_data_valid_sdram_s1) # !U1_dbs_latent_8_reg_segment_2[0] & (Y1_cpu_instruction_master_read_data_valid_ext_flash_s1_shift_register[1] # !KB1_za_data[16] & NB1_cpu_instruction_master_read_data_valid_sdram_s1);

--U1L54 is std_1c20:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_readdata[16]~2490

--operation mode is normal

U1L54 = !U1L53 & (Y1_internal_incoming_ext_ram_bus_data[16] # !Y1_cpu_instruction_master_read_data_valid_ext_ram_s1_shift_register[1] & !Y1_cpu_instruction_master_read_data_valid_lan91c111_s1_shift_register[1]);

--U1L55 is std_1c20:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_readdata[16]~2491

--operation mode is normal

U1L55 = U1L54 & (FE1_q_a[16] & !W1L1 # !X1_cpu_instruction_master_qualified_request_epcs_controller_epcs_control_port);

--Z1_period_l_register[0] is std_1c20:inst|high_res_timer:the_high_res_timer|period_l_register[0]

--operation mode is normal

Z1_period_l_register[0]_lut_out = !S1_M_st_data[0];

Z1_period_l_register[0] = DFFEAS(Z1_period_l_register[0]_lut_out, QC2__clk0, F1_data_out, , Z1_period_l_wr_strobe, , , , );

--Z1_force_reload is std_1c20:inst|high_res_timer:the_high_res_timer|force_reload

--operation mode is normal

Z1_force_reload_lut_out = S1_internal_d_write & !T1_internal_cpu_data_master_waitrequest & XE1L22 & AB1_cpu_data_master_requests_high_res_timer_s1;

Z1_force_reload = DFFEAS(Z1_force_reload_lut_out, QC2__clk0, F1_data_out, , , , , , );

--Z1L156 is std_1c20:inst|high_res_timer:the_high_res_timer|process0~1

--operation mode is normal

Z1L156 = Z1_force_reload # Z1L48 & Z1L53;

--Z1_counter_is_running is std_1c20:inst|high_res_timer:the_high_res_timer|counter_is_running

--operation mode is normal

Z1_counter_is_running_lut_out = Z1_control_wr_strobe & (S1_M_st_data[2] # Z1L9 & !S1_M_st_data[3]) # !Z1_control_wr_strobe & (Z1L9);

Z1_counter_is_running = DFFEAS(Z1_counter_is_running_lut_out, QC2__clk0, F1_data_out, , , , , , );

--Z1L155 is std_1c20:inst|high_res_timer:the_high_res_timer|process0~0

--operation mode is normal

Z1L155 = Z1_force_reload # Z1_counter_is_running;

--Z1_period_l_register[1] is std_1c20:inst|high_res_timer:the_high_res_timer|period_l_register[1]

--operation mode is normal

Z1_period_l_register[1]_lut_out = !S1_M_st_data[1];

Z1_period_l_register[1] = DFFEAS(Z1_period_l_register[1]_lut_out, QC2__clk0, F1_data_out, , Z1_period_l_wr_strobe, , , , );

--Z1_period_h_register[0] is std_1c20:inst|high_res_timer:the_high_res_timer|period_h_register[0]

--operation mode is normal

Z1_period_h_register[0]_lut_out = S1_M_st_data[0];

Z1_period_h_register[0] = DFFEAS(Z1_period_h_register[0]_lut_out, QC2__clk0, F1_data_out, , Z1_period_h_wr_strobe, , , , );

--Z1_period_h_register[1] is std_1c20:inst|high_res_timer:the_high_res_timer|period_h_register[1]

--operation mode is normal

Z1_period_h_register[1]_lut_out = S1_M_st_data[1];

Z1_period_h_register[1] = DFFEAS(Z1_period_h_register[1]_lut_out, QC2__clk0, F1_data_out, , Z1_period_h_wr_strobe, , , , );

--YE1L54 is std_1c20:inst|uart1:the_uart1|uart1_rx:the_uart1_rx|rx_overrun~45

--operation mode is normal

YE1L54 = YE1_internal_rx_char_ready & YE1_delayed_unxrx_in_processxx3 & (!YE1_unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[0]);

--M1_slave_readdata_p1[3] is std_1c20:inst|clock_1:the_clock_1|slave_readdata_p1[3]

--operation mode is normal

M1_slave_readdata_p1[3]_lut_out = M1_master_nativeaddress[0] & Q1_control_reg_out[3];

M1_slave_readdata_p1[3] = DFFEAS(M1_slave_readdata_p1[3]_lut_out, PLD_CLOCKINPUT[1], E1_data_out, , M1L22, , , , );

--J1_slave_readdata_p1[3] is std_1c20:inst|clock_0:the_clock_0|slave_readdata_p1[3]

--operation mode is normal

J1_slave_readdata_p1[3]_lut_out = J1_master_nativeaddress[0] & LB1_control_reg_out[3];

J1_slave_readdata_p1[3] = DFFEAS(J1_slave_readdata_p1[3]_lut_out, PLD_CLKFB, D1_data_out, , J1L22, , , , );

--GE1_wdata[3] is std_1c20:inst|jtag_uart:the_jtag_uart|alt_jtag_atlantic:jtag_uart_alt_jtag_atlantic|wdata[3]

--operation mode is normal

GE1_wdata[3] = AMPP_FUNCTION(A1L5, GE1_td_shift[7], !C1_CLR_SIGNAL, GE1L74);

--DE1_epcs_slave_select_holding_reg[3] is std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|epcs_slave_select_holding_reg[3]

--operation mode is normal

DE1_epcs_slave_select_holding_reg[3]_lut_out = S1_M_st_data[3];

DE1_epcs_slave_select_holding_reg[3] = DFFEAS(DE1_epcs_slave_select_holding_reg[3]_lut_out, QC2__clk0, F1_data_out, , DE1_slaveselect_wr_strobe, , , , );

--DE1_shift_reg[3] is std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|shift_reg[3]

--operation mode is normal

DE1_shift_reg[3]_lut_out = DE1_SCLK_reg & DE1_shift_reg[2] # !DE1_SCLK_reg & (DE1L170);

DE1_shift_reg[3] = DFFEAS(DE1_shift_reg[3]_lut_out, QC2__clk0, F1_data_out, , , DE1L170, , , !DE1_slowcount[0]);

--DE1_status_wr_strobe is std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|status_wr_strobe

--operation mode is normal

DE1_status_wr_strobe = X1L15 & DE1_wr_strobe & !X1L14 & !X1L16;

--U1L106 is std_1c20:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_readdata~41

--operation mode is normal

U1L106 = W1L1 & DE1_data_to_cpu[9] # !W1L1 & (FE1_q_a[9]) # !X1_cpu_instruction_master_qualified_request_epcs_controller_epcs_control_port;

--U1_dbs_latent_8_reg_segment_1[1] is std_1c20:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|dbs_latent_8_reg_segment_1[1]

--operation mode is normal

U1_dbs_latent_8_reg_segment_1[1]_lut_out = Y1_internal_incoming_ext_ram_bus_data[1];

U1_dbs_latent_8_reg_segment_1[1] = DFFEAS(U1_dbs_latent_8_reg_segment_1[1]_lut_out, QC2__clk0, F1_data_out, , U1L176, , , , );

--U1L109 is std_1c20:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_readdata~169

--operation mode is normal

U1L109 = U1_dbs_latent_8_reg_segment_1[1] # !Y1_cpu_instruction_master_read_data_valid_ext_flash_s1_shift_register[1];

--U1L35 is std_1c20:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_readdata[9]~2493

--operation mode is normal

U1L35 = U1L109 & (Y1_internal_incoming_ext_ram_bus_data[9] # !Y1_cpu_instruction_master_read_data_valid_lan91c111_s1_shift_register[1] & !Y1_cpu_instruction_master_read_data_valid_ext_ram_s1_shift_register[1]);

--U1L36 is std_1c20:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_readdata[9]~2494

--operation mode is normal

U1L36 = U1L106 & U1L35 & (KB1_za_data[9] # !NB1_cpu_instruction_master_read_data_valid_sdram_s1);

--CD1_q_b[31] is std_1c20:inst|cpu:the_cpu|cpu_register_bank_a_module:cpu_register_bank_a|altsyncram:the_altsyncram|altsyncram_3vd1:auto_generated|q_b[31]

--RAM Block Operation Mode: Simple Dual-Port

--Port A Depth: 32, Port A Width: 1, Port B Depth: 32, Port B Width: 1

--Port A Logical Depth: 32, Port A Logical Width: 32, Port B Logical Depth: 32, Port B Logical Width: 32

--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered

CD1_q_b[31] = AMPP_FUNCTION(GND, GND, QC2__clk0, QC2__clk0, !S1_M_wr_dst_reg, S1_W_stall, S1L1375, S1_M_dst_regnum[0], S1_M_dst_regnum[1], S1_M_dst_regnum[2], S1_M_dst_regnum[3], S1_M_dst_regnum[4], AD1_q_b[27], AD1_q_b[28], AD1_q_b[29], AD1_q_b[30], AD1_q_b[31]);

--S1_W_wr_data[31] is std_1c20:inst|cpu:the_cpu|W_wr_data[31]

--operation mode is normal

S1_W_wr_data[31] = AMPP_FUNCTION(QC2__clk0, S1L1375, F1_data_out, S1_W_stall);

--S1L78 is std_1c20:inst|cpu:the_cpu|A_WE_StdLogicVector~14158

--operation mode is normal

S1L78 = AMPP_FUNCTION(YC1_result[31], S1_E_ctrl_dst_data_sel_pc_plus_one);

--S1L539 is std_1c20:inst|cpu:the_cpu|E_logic_result[31]~15615

--operation mode is normal

S1L539 = AMPP_FUNCTION(S1_E_logic_op[1], S1L600, S1L666, S1_E_logic_op[0]);

--DD1_q_b[31] is std_1c20:inst|cpu:the_cpu|cpu_register_bank_b_module:cpu_register_bank_b|altsyncram:the_altsyncram|altsyncram_4vd1:auto_generated|q_b[31]

--RAM Block Operation Mode: Simple Dual-Port

--Port A Depth: 32, Port A Width: 1, Port B Depth: 32, Port B Width: 1

--Port A Logical Depth: 32, Port A Logical Width: 32, Port B Logical Depth: 32, Port B Logical Width: 32

--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered

DD1_q_b[31] = AMPP_FUNCTION(GND, GND, QC2__clk0, QC2__clk0, !S1_M_wr_dst_reg, S1_W_stall, S1L1375, S1_M_dst_regnum[0], S1_M_dst_regnum[1], S1_M_dst_regnum[2], S1_M_dst_regnum[3], S1_M_dst_regnum[4], AD1_q_b[22], AD1_q_b[23], AD1_q_b[24], AD1_q_b[25], AD1_q_b[26]);

--S1_E_src1_prelim[30] is std_1c20:inst|cpu:the_cpu|E_src1_prelim[30]

--operation mode is normal

S1_E_src1_prelim[30] = AMPP_FUNCTION(QC2__clk0, CD1_q_b[30], S1_W_wr_data[30], S1L1372, S1_D_src1_hazard_W, F1_data_out, S1_D_src1_hazard_M, S1_W_stall);

--S1L599 is std_1c20:inst|cpu:the_cpu|E_src1[30]~2044

--operation mode is normal

S1L599 = AMPP_FUNCTION(S1_E_src1_prelim[30], S1_E_src1_hazard_M, S1L1370, S1L1371);

--S1_E_src2_imm[30] is std_1c20:inst|cpu:the_cpu|E_src2_imm[30]

--operation mode is normal

S1_E_src2_imm[30] = AMPP_FUNCTION(QC2__clk0, S1_D_iw[20], S1_D_iw[21], S1L228, S1L238, F1_data_out, S1_W_stall);

--S1L665 is std_1c20:inst|cpu:the_cpu|E_src2[30]~1531

--operation mode is normal

S1L665 = AMPP_FUNCTION(S1_E_src2_imm[30], S1L740, S1_E_ctrl_src2_is_imm);

--XC1L7 is std_1c20:inst|cpu:the_cpu|cpu_test_bench:the_cpu_test_bench|Add0~565

--operation mode is arithmetic

XC1L7 = AMPP_FUNCTION(S1L598, S1L664, XC1L9);

--S1L203 is std_1c20:inst|cpu:the_cpu|D_ctrl_alu_signed_cmp~293

--operation mode is normal

S1L203 = AMPP_FUNCTION(S1_D_iw[14], S1_D_iw[15], S1_D_iw[16]);

--S1L204 is std_1c20:inst|cpu:the_cpu|D_ctrl_alu_signed_cmp~294

--operation mode is normal

S1L204 = AMPP_FUNCTION(S1L208, S1L768, S1L770, S1_D_iw[4]);

--YC1_result[29] is std_1c20:inst|cpu:the_cpu|lpm_add_sub:Add8|alt_stratix_add_sub:stratix_adder|result[29]

--operation mode is arithmetic

YC1_result[29] = AMPP_FUNCTION(S1L664, S1L598, YC1L59, S1_E_ctrl_alu_subtract);

--YC1L61 is std_1c20:inst|cpu:the_cpu|lpm_add_sub:Add8|alt_stratix_add_sub:stratix_adder|add_sub_cell[29]~COUT

--operation mode is arithmetic

YC1L61 = AMPP_FUNCTION(S1L664, S1L598, YC1L59, S1_E_ctrl_alu_subtract);

--GD1_break_readreg[18] is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_break:the_cpu_nios2_oci_break|break_readreg[18]

--operation mode is normal

GD1_break_readreg[18] = AMPP_FUNCTION(QC2__clk0, SD1_internal_jdo1[18], SD1_internal_jdo1[36], SD1_internal_jdo1[37], SD1L189, !C1_CLR_SIGNAL, SD1L189);

--SD1L23 is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|DRsize[0]~19993

--operation mode is normal

SD1L23 = AMPP_FUNCTION(GD1_break_readreg[18], RD1_internal_MonDReg[18], SD1_ir[1]);

--SD1L24 is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|DRsize[0]~19994

--operation mode is normal

SD1L24 = AMPP_FUNCTION(SD1L144, SD1_ir[1], SD1L23, SD1_ir[0]);

--GD1_break_readreg[17] is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_break:the_cpu_nios2_oci_break|break_readreg[17]

--operation mode is normal

GD1_break_readreg[17] = AMPP_FUNCTION(QC2__clk0, SD1_internal_jdo1[17], SD1_internal_jdo1[36], SD1_internal_jdo1[37], SD1L189, !C1_CLR_SIGNAL, SD1L189);

--SD1L25 is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|DRsize[0]~19996

--operation mode is normal

SD1L25 = AMPP_FUNCTION(GD1_break_readreg[17], RD1_internal_MonDReg[17], SD1_ir[1]);

--SD1L26 is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|DRsize[0]~19997

--operation mode is normal

SD1L26 = AMPP_FUNCTION(SD1L145, SD1L143, SD1L25, SD1_ir[0]);

--SD1L27 is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|DRsize[0]~19998

--operation mode is normal

SD1L27 = AMPP_FUNCTION(SD1L25, A1L4, SD1L145, SD1_ir[0]);

--SD1_internal_jdo1[36] is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|internal_jdo1[36]

--operation mode is normal

SD1_internal_jdo1[36] = AMPP_FUNCTION(A1L8, SD1_sr[36], VCC, SD1L145);

--SD1_internal_jdo1[37] is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|internal_jdo1[37]

--operation mode is normal

SD1_internal_jdo1[37] = AMPP_FUNCTION(A1L8, SD1_sr[37], VCC, SD1L145);

--SD1L189 is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|take_action_break_c~48

--operation mode is normal

SD1L189 = AMPP_FUNCTION(SD1_jxdr, SD1_ir[1], SD1_ir[0]);

--FF1_state[14] is sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state[14]

--operation mode is normal

FF1_state[14] = AMPP_FUNCTION(A1L5, A1L7, FF1_state[13], VCC);

--JD1L3 is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_debug:the_cpu_nios2_oci_debug|internal_monitor_error~106

--operation mode is normal

JD1L3 = AMPP_FUNCTION(JD1_internal_monitor_error, SD1_internal_jdo1[34], SD1L190, SD1_internal_jdo1[25]);

--SD1_sr[37] is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|sr[37]

--operation mode is normal

SD1_sr[37] = AMPP_FUNCTION(A1L5, altera_internal_jtag, SD1L28, A1L4, SD1L145, !C1_CLR_SIGNAL, SD1L30);

--SD1L28 is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|DRsize[0]~20000

--operation mode is normal

SD1L28 = AMPP_FUNCTION(SD1_ir[0], SD1_ir[1]);

--SD1L29 is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|DRsize[0]~20002

--operation mode is normal

SD1L29 = AMPP_FUNCTION(SD1_ir[0], SD1_ir[1]);

--SD1L30 is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|DRsize[0]~20003

--operation mode is normal

SD1L30 = AMPP_FUNCTION(SD1L144, SD1L142, SD1L29, SD1_st_updateir);

--C1L8 is sld_hub:sld_hub_inst|GEN_SHADOW_IRF~1

--operation mode is normal

C1L8 = AMPP_FUNCTION(BF8_Q[0], FF1_state[5], C1_OK_TO_UPDATE_IR_Q);

--NE2L5 is std_1c20:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_r:the_jtag_uart_scfifo_r|scfifo:rfifo|scfifo_jf21:auto_generated|a_dpfifo_ml21:dpfifo|a_fefifo_7cf:fifo_state|b_full~104

--operation mode is normal

NE2L5 = RE2_safe_q[3] & RE2_safe_q[0] & GE1L37Q & RE2_safe_q[4];

--NE2L6 is std_1c20:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_r:the_jtag_uart_scfifo_r|scfifo:rfifo|scfifo_jf21:auto_generated|a_dpfifo_ml21:dpfifo|a_fefifo_7cf:fifo_state|b_full~105

--operation mode is normal

NE2L6 = RE2_safe_q[2] & RE2_safe_q[1] & RE2_safe_q[5] & NE2L5;

--DE1_epcs_slave_select_holding_reg[15] is std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|epcs_slave_select_holding_reg[15]

--operation mode is normal

DE1_epcs_slave_select_holding_reg[15]_lut_out = S1_M_st_data[15];

DE1_epcs_slave_select_holding_reg[15] = DFFEAS(DE1_epcs_slave_select_holding_reg[15]_lut_out, QC2__clk0, F1_data_out, , DE1_slaveselect_wr_strobe, , , , );

--M1_slave_readdata_p1[15] is std_1c20:inst|clock_1:the_clock_1|slave_readdata_p1[15]

--operation mode is normal

M1_slave_readdata_p1[15]_lut_out = M1_master_nativeaddress[0] & Q1_control_reg_out[15];

M1_slave_readdata_p1[15] = DFFEAS(M1_slave_readdata_p1[15]_lut_out, PLD_CLOCKINPUT[1], E1_data_out, , M1L22, , , , );

--J1_slave_readdata_p1[15] is std_1c20:inst|clock_0:the_clock_0|slave_readdata_p1[15]

--operation mode is normal

J1_slave_readdata_p1[15]_lut_out = J1_master_nativeaddress[0] & LB1_control_reg_out[15];

J1_slave_readdata_p1[15] = DFFEAS(J1_slave_readdata_p1[15]_lut_out, PLD_CLKFB, D1_data_out, , J1L22, , , , );

--SD1_internal_jdo1[11] is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|internal_jdo1[11]

--operation mode is normal

SD1_internal_jdo1[11] = AMPP_FUNCTION(A1L8, SD1_sr[11], VCC, SD1L145);

--SD1_internal_jdo1[12] is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|internal_jdo1[12]

--operation mode is normal

SD1_internal_jdo1[12] = AMPP_FUNCTION(A1L8, SD1_sr[12], VCC, SD1L145);

--SD1_internal_jdo1[13] is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|internal_jdo1[13]

--operation mode is normal

SD1_internal_jdo1[13] = AMPP_FUNCTION(A1L8, SD1_sr[13], VCC, SD1L145);

--SD1_internal_jdo1[14] is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|internal_jdo1[14]

--operation mode is normal

SD1_internal_jdo1[14] = AMPP_FUNCTION(A1L8, SD1_sr[14], VCC, SD1L145);

--SD1_internal_jdo1[15] is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|internal_jdo1[15]

--operation mode is normal

SD1_internal_jdo1[15] = AMPP_FUNCTION(A1L8, SD1_sr[15], VCC, SD1L145);

--SD1_internal_jdo1[16] is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|internal_jdo1[16]

--operation mode is normal

SD1_internal_jdo1[16] = AMPP_FUNCTION(A1L8, SD1_sr[16], VCC, SD1L145);

--SD1_internal_jdo1[17] is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|internal_jdo1[17]

--operation mode is normal

SD1_internal_jdo1[17] = AMPP_FUNCTION(A1L8, SD1_sr[17], VCC, SD1L145);

--YE1L43 is std_1c20:inst|uart1:the_uart1|uart1_rx:the_uart1_rx|internal_rx_char_ready~34

--operation mode is normal

YE1L43 = YE1_internal_rx_char_ready # YE1_delayed_unxrx_in_processxx3 & (!YE1_unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[0]);

--YE1L55 is std_1c20:inst|uart1:the_uart1|uart1_rx:the_uart1_rx|rx_rd_strobe_onset~18

--operation mode is normal

YE1L55 = S1_internal_d_read & !S1_M_alu_result[2] & !S1_M_alu_result[3] & !S1_M_alu_result[4];

--M1_slave_readdata_p1[7] is std_1c20:inst|clock_1:the_clock_1|slave_readdata_p1[7]

--operation mode is normal

M1_slave_readdata_p1[7]_lut_out = M1_master_nativeaddress[0] & Q1_control_reg_out[7];

M1_slave_readdata_p1[7] = DFFEAS(M1_slave_readdata_p1[7]_lut_out, PLD_CLOCKINPUT[1], E1_data_out, , M1L22, , , , );

--J1_slave_readdata_p1[7] is std_1c20:inst|clock_0:the_clock_0|slave_readdata_p1[7]

--operation mode is normal

J1_slave_readdata_p1[7]_lut_out = J1_master_nativeaddress[0] & LB1_control_reg_out[7];

J1_slave_readdata_p1[7] = DFFEAS(J1_slave_readdata_p1[7]_lut_out, PLD_CLKFB, D1_data_out, , J1L22, , , , );

--GE1_wdata[7] is std_1c20:inst|jtag_uart:the_jtag_uart|alt_jtag_atlantic:jtag_uart_alt_jtag_atlantic|wdata[7]

--operation mode is normal

GE1_wdata[7] = AMPP_FUNCTION(A1L5, altera_internal_jtag, !C1_CLR_SIGNAL, GE1L74);

--DE1_epcs_slave_select_holding_reg[7] is std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|epcs_slave_select_holding_reg[7]

--operation mode is normal

DE1_epcs_slave_select_holding_reg[7]_lut_out = S1_M_st_data[7];

DE1_epcs_slave_select_holding_reg[7] = DFFEAS(DE1_epcs_slave_select_holding_reg[7]_lut_out, QC2__clk0, F1_data_out, , DE1_slaveselect_wr_strobe, , , , );

--DE1_shift_reg[7] is std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|shift_reg[7]

--operation mode is normal

DE1_shift_reg[7]_lut_out = DE1_SCLK_reg & DE1_shift_reg[6] # !DE1_SCLK_reg & (DE1L171);

DE1_shift_reg[7] = DFFEAS(DE1_shift_reg[7]_lut_out, QC2__clk0, F1_data_out, , , DE1L171, , , !DE1_slowcount[0]);

--DE1_data_rd_strobe is std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|data_rd_strobe

--operation mode is normal

DE1_data_rd_strobe_lut_out = DE1L130;

DE1_data_rd_strobe = DFFEAS(DE1_data_rd_strobe_lut_out, QC2__clk0, F1_data_out, , , , , , );

--U1_dbs_latent_8_reg_segment_2[6] is std_1c20:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|dbs_latent_8_reg_segment_2[6]

--operation mode is normal

U1_dbs_latent_8_reg_segment_2[6]_lut_out = Y1_internal_incoming_ext_ram_bus_data[6];

U1_dbs_latent_8_reg_segment_2[6] = DFFEAS(U1_dbs_latent_8_reg_segment_2[6]_lut_out, QC2__clk0, F1_data_out, , U1L177, , , , );

--U1L71 is std_1c20:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_readdata[22]~2496

--operation mode is normal

U1L71 = U1_dbs_latent_8_reg_segment_2[6] & (!KB1_za_data[22] & NB1_cpu_instruction_master_read_data_valid_sdram_s1) # !U1_dbs_latent_8_reg_segment_2[6] & (Y1_cpu_instruction_master_read_data_valid_ext_flash_s1_shift_register[1] # !KB1_za_data[22] & NB1_cpu_instruction_master_read_data_valid_sdram_s1);

--U1L72 is std_1c20:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_readdata[22]~2497

--operation mode is normal

U1L72 = !U1L71 & (Y1_internal_incoming_ext_ram_bus_data[22] # !Y1_cpu_instruction_master_read_data_valid_ext_ram_s1_shift_register[1] & !Y1_cpu_instruction_master_read_data_valid_lan91c111_s1_shift_register[1]);

--U1L73 is std_1c20:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_readdata[22]~2498

--operation mode is normal

U1L73 = U1L72 & (FE1_q_a[22] & !W1L1 # !X1_cpu_instruction_master_qualified_request_epcs_controller_epcs_control_port);

--U1_dbs_latent_8_reg_segment_2[7] is std_1c20:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|dbs_latent_8_reg_segment_2[7]

--operation mode is normal

U1_dbs_latent_8_reg_segment_2[7]_lut_out = Y1_internal_incoming_ext_ram_bus_data[7];

U1_dbs_latent_8_reg_segment_2[7] = DFFEAS(U1_dbs_latent_8_reg_segment_2[7]_lut_out, QC2__clk0, F1_data_out, , U1L177, , , , );

--U1L74 is std_1c20:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_readdata[23]~2500

--operation mode is normal

U1L74 = U1_dbs_latent_8_reg_segment_2[7] & (!KB1_za_data[23] & NB1_cpu_instruction_master_read_data_valid_sdram_s1) # !U1_dbs_latent_8_reg_segment_2[7] & (Y1_cpu_instruction_master_read_data_valid_ext_flash_s1_shift_register[1] # !KB1_za_data[23] & NB1_cpu_instruction_master_read_data_valid_sdram_s1);

--U1L75 is std_1c20:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_readdata[23]~2501

--operation mode is normal

U1L75 = !U1L74 & (Y1_internal_incoming_ext_ram_bus_data[23] # !Y1_cpu_instruction_master_read_data_valid_ext_ram_s1_shift_register[1] & !Y1_cpu_instruction_master_read_data_valid_lan91c111_s1_shift_register[1]);

--U1L76 is std_1c20:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_readdata[23]~2502

--operation mode is normal

U1L76 = U1L75 & (FE1_q_a[23] & !W1L1 # !X1_cpu_instruction_master_qualified_request_epcs_controller_epcs_control_port);

--U1L77 is std_1c20:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_readdata[24]~2504

--operation mode is normal

U1L77 = Y1_internal_incoming_ext_ram_bus_data[0] & (!KB1_za_data[24] & NB1_cpu_instruction_master_read_data_valid_sdram_s1) # !Y1_internal_incoming_ext_ram_bus_data[0] & (Y1_cpu_instruction_master_read_data_valid_ext_flash_s1_shift_register[1] # !KB1_za_data[24] & NB1_cpu_instruction_master_read_data_valid_sdram_s1);

--U1L78 is std_1c20:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_readdata[24]~2505

--operation mode is normal

U1L78 = !U1L77 & (Y1_internal_incoming_ext_ram_bus_data[24] # !Y1_cpu_instruction_master_read_data_valid_ext_ram_s1_shift_register[1] & !Y1_cpu_instruction_master_read_data_valid_lan91c111_s1_shift_register[1]);

--U1L79 is std_1c20:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_readdata[24]~2506

--operation mode is normal

U1L79 = U1L78 & (FE1_q_a[24] & !W1L1 # !X1_cpu_instruction_master_qualified_request_epcs_controller_epcs_control_port);

--U1L80 is std_1c20:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_readdata[25]~2508

--operation mode is normal

U1L80 = Y1_internal_incoming_ext_ram_bus_data[1] & (!KB1_za_data[25] & NB1_cpu_instruction_master_read_data_valid_sdram_s1) # !Y1_internal_incoming_ext_ram_bus_data[1] & (Y1_cpu_instruction_master_read_data_valid_ext_flash_s1_shift_register[1] # !KB1_za_data[25] & NB1_cpu_instruction_master_read_data_valid_sdram_s1);

--U1L81 is std_1c20:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_readdata[25]~2509

--operation mode is normal

U1L81 = !U1L80 & (Y1_internal_incoming_ext_ram_bus_data[25] # !Y1_cpu_instruction_master_read_data_valid_ext_ram_s1_shift_register[1] & !Y1_cpu_instruction_master_read_data_valid_lan91c111_s1_shift_register[1]);

--U1L82 is std_1c20:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_readdata[25]~2510

--operation mode is normal

U1L82 = U1L81 & (FE1_q_a[25] & !W1L1 # !X1_cpu_instruction_master_qualified_request_epcs_controller_epcs_control_port);

--U1L83 is std_1c20:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_readdata[26]~2512

--operation mode is normal

U1L83 = Y1_cpu_instruction_master_read_data_valid_ext_flash_s1_shift_register[1] & (!KB1_za_data[26] & NB1_cpu_instruction_master_read_data_valid_sdram_s1 # !Y1_internal_incoming_ext_ram_bus_data[2]) # !Y1_cpu_instruction_master_read_data_valid_ext_flash_s1_shift_register[1] & (!KB1_za_data[26] & NB1_cpu_instruction_master_read_data_valid_sdram_s1);

--U1L84 is std_1c20:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_readdata[26]~2513

--operation mode is normal

U1L84 = !U1L83 & (Y1_internal_incoming_ext_ram_bus_data[26] # !Y1_cpu_instruction_master_read_data_valid_ext_ram_s1_shift_register[1] & !Y1_cpu_instruction_master_read_data_valid_lan91c111_s1_shift_register[1]);

--U1L85 is std_1c20:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_readdata[26]~2514

--operation mode is normal

U1L85 = U1L84 & (FE1_q_a[26] & !W1L1 # !X1_cpu_instruction_master_qualified_request_epcs_controller_epcs_control_port);

--BB1_fifo_wr is std_1c20:inst|jtag_uart:the_jtag_uart|fifo_wr

--operation mode is normal

BB1_fifo_wr_lut_out = !S1_M_alu_result[2] & !NE1_b_full & (BB1L56);

BB1_fifo_wr = DFFEAS(BB1_fifo_wr_lut_out, QC2__clk0, F1_data_out, , , , , , );

--NE1_b_non_empty is std_1c20:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_w:the_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_jf21:auto_generated|a_dpfifo_ml21:dpfifo|a_fefifo_7cf:fifo_state|b_non_empty

--operation mode is normal

NE1_b_non_empty_lut_out = NE1_b_full # BB1_fifo_wr # NE1_b_non_empty & NE1L7;

NE1_b_non_empty = DFFEAS(NE1_b_non_empty_lut_out, QC2__clk0, F1_data_out, , , , , , );

--BB1_r_val is std_1c20:inst|jtag_uart:the_jtag_uart|r_val

--operation mode is normal

BB1_r_val_lut_out = BB1_rd_wfifo;

BB1_r_val = DFFEAS(BB1_r_val_lut_out, QC2__clk0, F1_data_out, , , , , , );

--GE1_r_ena1 is std_1c20:inst|jtag_uart:the_jtag_uart|alt_jtag_atlantic:jtag_uart_alt_jtag_atlantic|r_ena1

--operation mode is normal

GE1_r_ena1 = AMPP_FUNCTION(QC2__clk0, GE1L19, F1_data_out);

--BB1_rd_wfifo is std_1c20:inst|jtag_uart:the_jtag_uart|rd_wfifo

--operation mode is normal

BB1_rd_wfifo = NE1_b_non_empty & !GE1_rvalid0 & (!GE1_r_ena1 # !BB1_r_val);

--NE1L1 is std_1c20:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_w:the_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_jf21:auto_generated|a_dpfifo_ml21:dpfifo|a_fefifo_7cf:fifo_state|_~28

--operation mode is normal

NE1L1 = BB1_fifo_wr $ BB1_rd_wfifo;

--U1_dbs_latent_8_reg_segment_2[4] is std_1c20:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|dbs_latent_8_reg_segment_2[4]

--operation mode is normal

U1_dbs_latent_8_reg_segment_2[4]_lut_out = Y1_internal_incoming_ext_ram_bus_data[4];

U1_dbs_latent_8_reg_segment_2[4] = DFFEAS(U1_dbs_latent_8_reg_segment_2[4]_lut_out, QC2__clk0, F1_data_out, , U1L177, , , , );

--U1L65 is std_1c20:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_readdata[20]~2516

--operation mode is normal

U1L65 = U1_dbs_latent_8_reg_segment_2[4] & (!KB1_za_data[20] & NB1_cpu_instruction_master_read_data_valid_sdram_s1) # !U1_dbs_latent_8_reg_segment_2[4] & (Y1_cpu_instruction_master_read_data_valid_ext_flash_s1_shift_register[1] # !KB1_za_data[20] & NB1_cpu_instruction_master_read_data_valid_sdram_s1);

--U1L66 is std_1c20:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_readdata[20]~2517

--operation mode is normal

U1L66 = !U1L65 & (Y1_internal_incoming_ext_ram_bus_data[20] # !Y1_cpu_instruction_master_read_data_valid_ext_ram_s1_shift_register[1] & !Y1_cpu_instruction_master_read_data_valid_lan91c111_s1_shift_register[1]);

--U1L67 is std_1c20:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_readdata[20]~2518

--operation mode is normal

U1L67 = U1L66 & (FE1_q_a[20] & !W1L1 # !X1_cpu_instruction_master_qualified_request_epcs_controller_epcs_control_port);

--M1_slave_readdata_p1[14] is std_1c20:inst|clock_1:the_clock_1|slave_readdata_p1[14]

--operation mode is normal

M1_slave_readdata_p1[14]_lut_out = M1_master_nativeaddress[0] & Q1_control_reg_out[14];

M1_slave_readdata_p1[14] = DFFEAS(M1_slave_readdata_p1[14]_lut_out, PLD_CLOCKINPUT[1], E1_data_out, , M1L22, , , , );

--J1_slave_readdata_p1[14] is std_1c20:inst|clock_0:the_clock_0|slave_readdata_p1[14]

--operation mode is normal

J1_slave_readdata_p1[14]_lut_out = J1_master_nativeaddress[0] & LB1_control_reg_out[14];

J1_slave_readdata_p1[14] = DFFEAS(J1_slave_readdata_p1[14]_lut_out, PLD_CLKFB, D1_data_out, , J1L22, , , , );

--DE1_epcs_slave_select_holding_reg[14] is std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|epcs_slave_select_holding_reg[14]

--operation mode is normal

DE1_epcs_slave_select_holding_reg[14]_lut_out = S1_M_st_data[14];

DE1_epcs_slave_select_holding_reg[14] = DFFEAS(DE1_epcs_slave_select_holding_reg[14]_lut_out, QC2__clk0, F1_data_out, , DE1_slaveselect_wr_strobe, , , , );

--U1_dbs_latent_8_reg_segment_2[3] is std_1c20:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|dbs_latent_8_reg_segment_2[3]

--operation mode is normal

U1_dbs_latent_8_reg_segment_2[3]_lut_out = Y1_internal_incoming_ext_ram_bus_data[3];

U1_dbs_latent_8_reg_segment_2[3] = DFFEAS(U1_dbs_latent_8_reg_segment_2[3]_lut_out, QC2__clk0, F1_data_out, , U1L177, , , , );

--U1L62 is std_1c20:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_readdata[19]~2520

--operation mode is normal

U1L62 = U1_dbs_latent_8_reg_segment_2[3] & (!KB1_za_data[19] & NB1_cpu_instruction_master_read_data_valid_sdram_s1) # !U1_dbs_latent_8_reg_segment_2[3] & (Y1_cpu_instruction_master_read_data_valid_ext_flash_s1_shift_register[1] # !KB1_za_data[19] & NB1_cpu_instruction_master_read_data_valid_sdram_s1);

--U1L63 is std_1c20:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_readdata[19]~2521

--operation mode is normal

U1L63 = !U1L62 & (Y1_internal_incoming_ext_ram_bus_data[19] # !Y1_cpu_instruction_master_read_data_valid_ext_ram_s1_shift_register[1] & !Y1_cpu_instruction_master_read_data_valid_lan91c111_s1_shift_register[1]);

--U1L64 is std_1c20:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_readdata[19]~2522

--operation mode is normal

U1L64 = U1L63 & (FE1_q_a[19] & !W1L1 # !X1_cpu_instruction_master_qualified_request_epcs_controller_epcs_control_port);

--M1_slave_readdata_p1[13] is std_1c20:inst|clock_1:the_clock_1|slave_readdata_p1[13]

--operation mode is normal

M1_slave_readdata_p1[13]_lut_out = M1_master_nativeaddress[0] & Q1_control_reg_out[13];

M1_slave_readdata_p1[13] = DFFEAS(M1_slave_readdata_p1[13]_lut_out, PLD_CLOCKINPUT[1], E1_data_out, , M1L22, , , , );

--J1_slave_readdata_p1[13] is std_1c20:inst|clock_0:the_clock_0|slave_readdata_p1[13]

--operation mode is normal

J1_slave_readdata_p1[13]_lut_out = J1_master_nativeaddress[0] & LB1_control_reg_out[13];

J1_slave_readdata_p1[13] = DFFEAS(J1_slave_readdata_p1[13]_lut_out, PLD_CLKFB, D1_data_out, , J1L22, , , , );

--NE1L3 is std_1c20:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_w:the_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_jf21:auto_generated|a_dpfifo_ml21:dpfifo|a_fefifo_7cf:fifo_state|b_full~134

--operation mode is normal

NE1L3 = RE1_safe_q[0] & RE1_safe_q[3] & RE1_safe_q[2] & RE1_safe_q[1];

--NE1L4 is std_1c20:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_w:the_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_jf21:auto_generated|a_dpfifo_ml21:dpfifo|a_fefifo_7cf:fifo_state|b_full~135

--operation mode is normal

NE1L4 = RE1_safe_q[5] & RE1_safe_q[4] & BB1_fifo_wr & NE1_b_non_empty;

--DE1_epcs_slave_select_holding_reg[13] is std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|epcs_slave_select_holding_reg[13]

--operation mode is normal

DE1_epcs_slave_select_holding_reg[13]_lut_out = S1_M_st_data[13];

DE1_epcs_slave_select_holding_reg[13] = DFFEAS(DE1_epcs_slave_select_holding_reg[13]_lut_out, QC2__clk0, F1_data_out, , DE1_slaveselect_wr_strobe, , , , );

--U1_dbs_latent_8_reg_segment_2[2] is std_1c20:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|dbs_latent_8_reg_segment_2[2]

--operation mode is normal

U1_dbs_latent_8_reg_segment_2[2]_lut_out = Y1_internal_incoming_ext_ram_bus_data[2];

U1_dbs_latent_8_reg_segment_2[2] = DFFEAS(U1_dbs_latent_8_reg_segment_2[2]_lut_out, QC2__clk0, F1_data_out, , U1L177, , , , );

--U1L59 is std_1c20:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_readdata[18]~2524

--operation mode is normal

U1L59 = U1_dbs_latent_8_reg_segment_2[2] & (!KB1_za_data[18] & NB1_cpu_instruction_master_read_data_valid_sdram_s1) # !U1_dbs_latent_8_reg_segment_2[2] & (Y1_cpu_instruction_master_read_data_valid_ext_flash_s1_shift_register[1] # !KB1_za_data[18] & NB1_cpu_instruction_master_read_data_valid_sdram_s1);

--U1L60 is std_1c20:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_readdata[18]~2525

--operation mode is normal

U1L60 = !U1L59 & (Y1_internal_incoming_ext_ram_bus_data[18] # !Y1_cpu_instruction_master_read_data_valid_ext_ram_s1_shift_register[1] & !Y1_cpu_instruction_master_read_data_valid_lan91c111_s1_shift_register[1]);

--U1L61 is std_1c20:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_readdata[18]~2526

--operation mode is normal

U1L61 = U1L60 & (FE1_q_a[18] & !W1L1 # !X1_cpu_instruction_master_qualified_request_epcs_controller_epcs_control_port);

--M1_slave_readdata_p1[12] is std_1c20:inst|clock_1:the_clock_1|slave_readdata_p1[12]

--operation mode is normal

M1_slave_readdata_p1[12]_lut_out = M1_master_nativeaddress[0] & Q1_control_reg_out[12];

M1_slave_readdata_p1[12] = DFFEAS(M1_slave_readdata_p1[12]_lut_out, PLD_CLOCKINPUT[1], E1_data_out, , M1L22, , , , );

--J1_slave_readdata_p1[12] is std_1c20:inst|clock_0:the_clock_0|slave_readdata_p1[12]

--operation mode is normal

J1_slave_readdata_p1[12]_lut_out = J1_master_nativeaddress[0] & LB1_control_reg_out[12];

J1_slave_readdata_p1[12] = DFFEAS(J1_slave_readdata_p1[12]_lut_out, PLD_CLKFB, D1_data_out, , J1L22, , , , );

--NE2L8 is std_1c20:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_r:the_jtag_uart_scfifo_r|scfifo:rfifo|scfifo_jf21:auto_generated|a_dpfifo_ml21:dpfifo|a_fefifo_7cf:fifo_state|b_non_empty~100

--operation mode is normal

NE2L8 = NE2_b_full # GE1L37Q & (!NE2_b_non_empty);

--NE2L2 is std_1c20:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_r:the_jtag_uart_scfifo_r|scfifo:rfifo|scfifo_jf21:auto_generated|a_dpfifo_ml21:dpfifo|a_fefifo_7cf:fifo_state|_~85

--operation mode is normal

NE2L2 = RE2_safe_q[5] # RE2_safe_q[1] # RE2_safe_q[4] # !RE2_safe_q[0];

--NE2L3 is std_1c20:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_r:the_jtag_uart_scfifo_r|scfifo:rfifo|scfifo_jf21:auto_generated|a_dpfifo_ml21:dpfifo|a_fefifo_7cf:fifo_state|_~86

--operation mode is normal

NE2L3 = RE2_safe_q[2] # RE2_safe_q[3] # BB1_wr_rfifo # NE2L2;

--DE1_epcs_slave_select_holding_reg[12] is std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|epcs_slave_select_holding_reg[12]

--operation mode is normal

DE1_epcs_slave_select_holding_reg[12]_lut_out = S1_M_st_data[12];

DE1_epcs_slave_select_holding_reg[12] = DFFEAS(DE1_epcs_slave_select_holding_reg[12]_lut_out, QC2__clk0, F1_data_out, , DE1_slaveselect_wr_strobe, , , , );

--BB1L39 is std_1c20:inst|jtag_uart:the_jtag_uart|Add1~314

--operation mode is arithmetic

BB1L39 = CARRY(!RE1_safe_q[0]);

--S1_E_src1_prelim[28] is std_1c20:inst|cpu:the_cpu|E_src1_prelim[28]

--operation mode is normal

S1_E_src1_prelim[28] = AMPP_FUNCTION(QC2__clk0, CD1_q_b[28], S1_W_wr_data[28], S1L1366, S1_D_src1_hazard_W, F1_data_out, S1_D_src1_hazard_M, S1_W_stall);

--S1L597 is std_1c20:inst|cpu:the_cpu|E_src1[28]~2045

--operation mode is normal

S1L597 = AMPP_FUNCTION(S1_E_src1_prelim[28], S1_E_src1_hazard_M, S1L1364, S1L1365);

--CD1_q_b[27] is std_1c20:inst|cpu:the_cpu|cpu_register_bank_a_module:cpu_register_bank_a|altsyncram:the_altsyncram|altsyncram_3vd1:auto_generated|q_b[27]

--RAM Block Operation Mode: Simple Dual-Port

--Port A Depth: 32, Port A Width: 1, Port B Depth: 32, Port B Width: 1

--Port A Logical Depth: 32, Port A Logical Width: 32, Port B Logical Depth: 32, Port B Logical Width: 32

--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered

CD1_q_b[27] = AMPP_FUNCTION(GND, GND, QC2__clk0, QC2__clk0, !S1_M_wr_dst_reg, S1_W_stall, S1L1363, S1_M_dst_regnum[0], S1_M_dst_regnum[1], S1_M_dst_regnum[2], S1_M_dst_regnum[3], S1_M_dst_regnum[4], AD1_q_b[27], AD1_q_b[28], AD1_q_b[29], AD1_q_b[30], AD1_q_b[31]);

--S1_W_wr_data[27] is std_1c20:inst|cpu:the_cpu|W_wr_data[27]

--operation mode is normal

S1_W_wr_data[27] = AMPP_FUNCTION(QC2__clk0, S1L1363, F1_data_out, S1_W_stall);

--YC1_result[27] is std_1c20:inst|cpu:the_cpu|lpm_add_sub:Add8|alt_stratix_add_sub:stratix_adder|result[27]

--operation mode is arithmetic

YC1_result[27] = AMPP_FUNCTION(S1L662, S1L596, YC1L55, S1_E_ctrl_alu_subtract);

--YC1L57 is std_1c20:inst|cpu:the_cpu|lpm_add_sub:Add8|alt_stratix_add_sub:stratix_adder|add_sub_cell[27]~COUT

--operation mode is arithmetic

YC1L57 = AMPP_FUNCTION(S1L662, S1L596, YC1L55, S1_E_ctrl_alu_subtract);

--S1L79 is std_1c20:inst|cpu:the_cpu|A_WE_StdLogicVector~14159

--operation mode is normal

S1L79 = AMPP_FUNCTION(YC1_result[27], S1_E_ctrl_dst_data_sel_pc_plus_one);

--S1_E_src2_imm[27] is std_1c20:inst|cpu:the_cpu|E_src2_imm[27]

--operation mode is normal

S1_E_src2_imm[27] = AMPP_FUNCTION(QC2__clk0, S1_D_iw[17], S1_D_iw[21], S1L228, S1L238, F1_data_out, S1_W_stall);

--S1L662 is std_1c20:inst|cpu:the_cpu|E_src2[27]~1532

--operation mode is normal

S1L662 = AMPP_FUNCTION(S1_E_src2_imm[27], S1L737, S1_E_ctrl_src2_is_imm);

--S1L535 is std_1c20:inst|cpu:the_cpu|E_logic_result[27]~15616

--operation mode is normal

S1L535 = AMPP_FUNCTION(S1_E_logic_op[1], S1L596, S1L662, S1_E_logic_op[0]);

--DD1_q_b[26] is std_1c20:inst|cpu:the_cpu|cpu_register_bank_b_module:cpu_register_bank_b|altsyncram:the_altsyncram|altsyncram_4vd1:auto_generated|q_b[26]

--RAM Block Operation Mode: Simple Dual-Port

--Port A Depth: 32, Port A Width: 1, Port B Depth: 32, Port B Width: 1

--Port A Logical Depth: 32, Port A Logical Width: 32, Port B Logical Depth: 32, Port B Logical Width: 32

--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered

DD1_q_b[26] = AMPP_FUNCTION(GND, GND, QC2__clk0, QC2__clk0, !S1_M_wr_dst_reg, S1_W_stall, S1L1360, S1_M_dst_regnum[0], S1_M_dst_regnum[1], S1_M_dst_regnum[2], S1_M_dst_regnum[3], S1_M_dst_regnum[4], AD1_q_b[22], AD1_q_b[23], AD1_q_b[24], AD1_q_b[25], AD1_q_b[26]);

--U1L107 is std_1c20:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_readdata~42

--operation mode is normal

U1L107 = W1L1 & DE1_data_to_cpu[10] # !W1L1 & (FE1_q_a[10]) # !X1_cpu_instruction_master_qualified_request_epcs_controller_epcs_control_port;

--U1_dbs_latent_8_reg_segment_1[2] is std_1c20:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|dbs_latent_8_reg_segment_1[2]

--operation mode is normal

U1_dbs_latent_8_reg_segment_1[2]_lut_out = Y1_internal_incoming_ext_ram_bus_data[2];

U1_dbs_latent_8_reg_segment_1[2] = DFFEAS(U1_dbs_latent_8_reg_segment_1[2]_lut_out, QC2__clk0, F1_data_out, , U1L176, , , , );

--U1L110 is std_1c20:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_readdata~170

--operation mode is normal

U1L110 = U1_dbs_latent_8_reg_segment_1[2] # !Y1_cpu_instruction_master_read_data_valid_ext_flash_s1_shift_register[1];

--U1L37 is std_1c20:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_readdata[10]~2528

--operation mode is normal

U1L37 = U1L110 & (Y1_internal_incoming_ext_ram_bus_data[10] # !Y1_cpu_instruction_master_read_data_valid_lan91c111_s1_shift_register[1] & !Y1_cpu_instruction_master_read_data_valid_ext_ram_s1_shift_register[1]);

--U1L38 is std_1c20:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_readdata[10]~2529

--operation mode is normal

U1L38 = U1L107 & U1L37 & (KB1_za_data[10] # !NB1_cpu_instruction_master_read_data_valid_sdram_s1);

--U1_dbs_latent_8_reg_segment_2[1] is std_1c20:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|dbs_latent_8_reg_segment_2[1]

--operation mode is normal

U1_dbs_latent_8_reg_segment_2[1]_lut_out = Y1_internal_incoming_ext_ram_bus_data[1];

U1_dbs_latent_8_reg_segment_2[1] = DFFEAS(U1_dbs_latent_8_reg_segment_2[1]_lut_out, QC2__clk0, F1_data_out, , U1L177, , , , );

--U1L56 is std_1c20:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_readdata[17]~2531

--operation mode is normal

U1L56 = U1_dbs_latent_8_reg_segment_2[1] & (!KB1_za_data[17] & NB1_cpu_instruction_master_read_data_valid_sdram_s1) # !U1_dbs_latent_8_reg_segment_2[1] & (Y1_cpu_instruction_master_read_data_valid_ext_flash_s1_shift_register[1] # !KB1_za_data[17] & NB1_cpu_instruction_master_read_data_valid_sdram_s1);

--U1L57 is std_1c20:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_readdata[17]~2532

--operation mode is normal

U1L57 = !U1L56 & (Y1_internal_incoming_ext_ram_bus_data[17] # !Y1_cpu_instruction_master_read_data_valid_ext_ram_s1_shift_register[1] & !Y1_cpu_instruction_master_read_data_valid_lan91c111_s1_shift_register[1]);

--U1L58 is std_1c20:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_readdata[17]~2533

--operation mode is normal

U1L58 = U1L57 & (FE1_q_a[17] & !W1L1 # !X1_cpu_instruction_master_qualified_request_epcs_controller_epcs_control_port);

--J1_slave_readdata_p1[11] is std_1c20:inst|clock_0:the_clock_0|slave_readdata_p1[11]

--operation mode is normal

J1_slave_readdata_p1[11]_lut_out = J1_master_nativeaddress[0] & LB1_control_reg_out[11];

J1_slave_readdata_p1[11] = DFFEAS(J1_slave_readdata_p1[11]_lut_out, PLD_CLKFB, D1_data_out, , J1L22, , , , );

--M1_slave_readdata_p1[11] is std_1c20:inst|clock_1:the_clock_1|slave_readdata_p1[11]

--operation mode is normal

M1_slave_readdata_p1[11]_lut_out = M1_master_nativeaddress[0] & Q1_control_reg_out[11];

M1_slave_readdata_p1[11] = DFFEAS(M1_slave_readdata_p1[11]_lut_out, PLD_CLOCKINPUT[1], E1_data_out, , M1L22, , , , );

--DE1_epcs_slave_select_holding_reg[11] is std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|epcs_slave_select_holding_reg[11]

--operation mode is normal

DE1_epcs_slave_select_holding_reg[11]_lut_out = S1_M_st_data[11];

DE1_epcs_slave_select_holding_reg[11] = DFFEAS(DE1_epcs_slave_select_holding_reg[11]_lut_out, QC2__clk0, F1_data_out, , DE1_slaveselect_wr_strobe, , , , );

--DE1_epcs_slave_select_holding_reg[10] is std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|epcs_slave_select_holding_reg[10]

--operation mode is normal

DE1_epcs_slave_select_holding_reg[10]_lut_out = S1_M_st_data[10];

DE1_epcs_slave_select_holding_reg[10] = DFFEAS(DE1_epcs_slave_select_holding_reg[10]_lut_out, QC2__clk0, F1_data_out, , DE1_slaveselect_wr_strobe, , , , );

--M1_slave_readdata_p1[10] is std_1c20:inst|clock_1:the_clock_1|slave_readdata_p1[10]

--operation mode is normal

M1_slave_readdata_p1[10]_lut_out = M1_master_nativeaddress[0] & Q1_control_reg_out[10];

M1_slave_readdata_p1[10] = DFFEAS(M1_slave_readdata_p1[10]_lut_out, PLD_CLOCKINPUT[1], E1_data_out, , M1L22, , , , );

--J1_slave_readdata_p1[10] is std_1c20:inst|clock_0:the_clock_0|slave_readdata_p1[10]

--operation mode is normal

J1_slave_readdata_p1[10]_lut_out = J1_master_nativeaddress[0] & LB1_control_reg_out[10];

J1_slave_readdata_p1[10] = DFFEAS(J1_slave_readdata_p1[10]_lut_out, PLD_CLKFB, D1_data_out, , J1L22, , , , );

--BB1L2 is std_1c20:inst|jtag_uart:the_jtag_uart|ac~75

--operation mode is normal

BB1L2 = GE1L39Q # GE1L37Q;

--DE1_epcs_slave_select_holding_reg[9] is std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|epcs_slave_select_holding_reg[9]

--operation mode is normal

DE1_epcs_slave_select_holding_reg[9]_lut_out = S1_M_st_data[9];

DE1_epcs_slave_select_holding_reg[9] = DFFEAS(DE1_epcs_slave_select_holding_reg[9]_lut_out, QC2__clk0, F1_data_out, , DE1_slaveselect_wr_strobe, , , , );

--DE1_rd_strobe is std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|rd_strobe

--operation mode is normal

DE1_rd_strobe_lut_out = DE1_p1_rd_strobe;

DE1_rd_strobe = DFFEAS(DE1_rd_strobe_lut_out, QC2__clk0, F1_data_out, , , , , , );

--DE1_p1_rd_strobe is std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|p1_rd_strobe

--operation mode is normal

DE1_p1_rd_strobe = W1L1 & !DE1_rd_strobe & (X1L9 # X1L28);

--DE1L130 is std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|p1_data_rd_strobe~25

--operation mode is normal

DE1L130 = DE1_p1_rd_strobe & !X1L14 & !X1L15 & !X1L16;

--DE1L138 is std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|p1_data_wr_strobe~22

--operation mode is normal

DE1L138 = X1L14 & DE1L141 & !X1L15 & !X1L16;

--DE1L65 is std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|EOP~153

--operation mode is normal

DE1L65 = S1_M_st_data[4] & DE1_endofpacketvalue_reg[4] & (S1_M_st_data[2] $ !DE1_endofpacketvalue_reg[2]) # !S1_M_st_data[4] & !DE1_endofpacketvalue_reg[4] & (S1_M_st_data[2] $ !DE1_endofpacketvalue_reg[2]);

--DE1_endofpacketvalue_reg[0] is std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|endofpacketvalue_reg[0]

--operation mode is normal

DE1_endofpacketvalue_reg[0]_lut_out = S1_M_st_data[0];

DE1_endofpacketvalue_reg[0] = DFFEAS(DE1_endofpacketvalue_reg[0]_lut_out, QC2__clk0, F1_data_out, , DE1_endofpacketvalue_wr_strobe, , , , );

--DE1L66 is std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|EOP~154

--operation mode is normal

DE1L66 = S1_M_st_data[7] & DE1_endofpacketvalue_reg[7] & (S1_M_st_data[0] $ !DE1_endofpacketvalue_reg[0]) # !S1_M_st_data[7] & !DE1_endofpacketvalue_reg[7] & (S1_M_st_data[0] $ !DE1_endofpacketvalue_reg[0]);

--DE1L67 is std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|EOP~155

--operation mode is normal

DE1L67 = S1_M_st_data[6] & DE1_endofpacketvalue_reg[6] & (S1_M_st_data[3] $ !DE1_endofpacketvalue_reg[3]) # !S1_M_st_data[6] & !DE1_endofpacketvalue_reg[6] & (S1_M_st_data[3] $ !DE1_endofpacketvalue_reg[3]);

--DE1_endofpacketvalue_reg[1] is std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|endofpacketvalue_reg[1]

--operation mode is normal

DE1_endofpacketvalue_reg[1]_lut_out = S1_M_st_data[1];

DE1_endofpacketvalue_reg[1] = DFFEAS(DE1_endofpacketvalue_reg[1]_lut_out, QC2__clk0, F1_data_out, , DE1_endofpacketvalue_wr_strobe, , , , );

--DE1L68 is std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|EOP~156

--operation mode is normal

DE1L68 = S1_M_st_data[5] & DE1_endofpacketvalue_reg[5] & (S1_M_st_data[1] $ !DE1_endofpacketvalue_reg[1]) # !S1_M_st_data[5] & !DE1_endofpacketvalue_reg[5] & (S1_M_st_data[1] $ !DE1_endofpacketvalue_reg[1]);

--DE1L69 is std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|EOP~157

--operation mode is normal

DE1L69 = DE1L65 & DE1L66 & DE1L67 & DE1L68;

--DE1L70 is std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|EOP~158

--operation mode is normal

DE1L70 = DE1_endofpacketvalue_reg[2] & DE1_rx_holding_reg[2] & (DE1_endofpacketvalue_reg[4] $ !DE1_rx_holding_reg[4]) # !DE1_endofpacketvalue_reg[2] & !DE1_rx_holding_reg[2] & (DE1_endofpacketvalue_reg[4] $ !DE1_rx_holding_reg[4]);

--DE1_rx_holding_reg[0] is std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|rx_holding_reg[0]

--operation mode is normal

DE1_rx_holding_reg[0]_lut_out = DE1_shift_reg[0];

DE1_rx_holding_reg[0] = DFFEAS(DE1_rx_holding_reg[0]_lut_out, QC2__clk0, F1_data_out, , DE1L156, , , , );

--DE1L71 is std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|EOP~159

--operation mode is normal

DE1L71 = DE1_endofpacketvalue_reg[7] & DE1_rx_holding_reg[7] & (DE1_endofpacketvalue_reg[0] $ !DE1_rx_holding_reg[0]) # !DE1_endofpacketvalue_reg[7] & !DE1_rx_holding_reg[7] & (DE1_endofpacketvalue_reg[0] $ !DE1_rx_holding_reg[0]);

--DE1L72 is std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|EOP~160

--operation mode is normal

DE1L72 = DE1_endofpacketvalue_reg[3] & DE1_rx_holding_reg[3] & (DE1_endofpacketvalue_reg[6] $ !DE1_rx_holding_reg[6]) # !DE1_endofpacketvalue_reg[3] & !DE1_rx_holding_reg[3] & (DE1_endofpacketvalue_reg[6] $ !DE1_rx_holding_reg[6]);

--DE1_rx_holding_reg[1] is std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|rx_holding_reg[1]

--operation mode is normal

DE1_rx_holding_reg[1]_lut_out = DE1_shift_reg[1];

DE1_rx_holding_reg[1] = DFFEAS(DE1_rx_holding_reg[1]_lut_out, QC2__clk0, F1_data_out, , DE1L156, , , , );

--DE1L73 is std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|EOP~161

--operation mode is normal

DE1L73 = DE1_rx_holding_reg[5] & DE1_endofpacketvalue_reg[5] & (DE1_endofpacketvalue_reg[1] $ !DE1_rx_holding_reg[1]) # !DE1_rx_holding_reg[5] & !DE1_endofpacketvalue_reg[5] & (DE1_endofpacketvalue_reg[1] $ !DE1_rx_holding_reg[1]);

--DE1L74 is std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|EOP~162

--operation mode is normal

DE1L74 = DE1L70 & DE1L71 & DE1L72 & DE1L73;

--DE1L75 is std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|EOP~163

--operation mode is normal

DE1L75 = DE1L130 & (DE1L74 # DE1L138 & DE1L69) # !DE1L130 & DE1L138 & DE1L69;

--DE1L76 is std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|EOP~164

--operation mode is normal

DE1L76 = !DE1_endofpacketvalue_reg[15] & !DE1_endofpacketvalue_reg[11];

--DE1L77 is std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|EOP~165

--operation mode is normal

DE1L77 = !DE1_endofpacketvalue_reg[12] & !DE1_endofpacketvalue_reg[10] & !DE1_endofpacketvalue_reg[9] & !DE1_endofpacketvalue_reg[8];

--DE1L78 is std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|EOP~166

--operation mode is normal

DE1L78 = DE1L76 & DE1L77 & !DE1_endofpacketvalue_reg[14] & !DE1_endofpacketvalue_reg[13];

--M1_slave_readdata_p1[9] is std_1c20:inst|clock_1:the_clock_1|slave_readdata_p1[9]

--operation mode is normal

M1_slave_readdata_p1[9]_lut_out = M1_master_nativeaddress[0] & Q1_control_reg_out[9];

M1_slave_readdata_p1[9] = DFFEAS(M1_slave_readdata_p1[9]_lut_out, PLD_CLOCKINPUT[1], E1_data_out, , M1L22, , , , );

--J1_slave_readdata_p1[9] is std_1c20:inst|clock_0:the_clock_0|slave_readdata_p1[9]

--operation mode is normal

J1_slave_readdata_p1[9]_lut_out = J1_master_nativeaddress[0] & LB1_control_reg_out[9];

J1_slave_readdata_p1[9] = DFFEAS(J1_slave_readdata_p1[9]_lut_out, PLD_CLKFB, D1_data_out, , J1L22, , , , );

--YE1L40 is std_1c20:inst|uart1:the_uart1|uart1_rx:the_uart1_rx|framing_error~100

--operation mode is normal

YE1L40 = YE1_framing_error # YE1_got_new_char & YE1L72 & !YE1_unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[9];

--ZE1L31 is std_1c20:inst|uart1:the_uart1|uart1_tx:the_uart1_tx|tx_overrun~45

--operation mode is normal

ZE1L31 = ZE1L33 & ZE1_internal_tx_ready & ZE1L34 & ZE1L35;

--M1_slave_readdata_p1[8] is std_1c20:inst|clock_1:the_clock_1|slave_readdata_p1[8]

--operation mode is normal

M1_slave_readdata_p1[8]_lut_out = M1_master_nativeaddress[0] & Q1_control_reg_out[8];

M1_slave_readdata_p1[8] = DFFEAS(M1_slave_readdata_p1[8]_lut_out, PLD_CLOCKINPUT[1], E1_data_out, , M1L22, , , , );

--J1_slave_readdata_p1[8] is std_1c20:inst|clock_0:the_clock_0|slave_readdata_p1[8]

--operation mode is normal

J1_slave_readdata_p1[8]_lut_out = J1_master_nativeaddress[0] & LB1_control_reg_out[8];

J1_slave_readdata_p1[8] = DFFEAS(J1_slave_readdata_p1[8]_lut_out, PLD_CLKFB, D1_data_out, , J1L22, , , , );

--DE1_epcs_slave_select_holding_reg[8] is std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|epcs_slave_select_holding_reg[8]

--operation mode is normal

DE1_epcs_slave_select_holding_reg[8]_lut_out = S1_M_st_data[8];

DE1_epcs_slave_select_holding_reg[8] = DFFEAS(DE1_epcs_slave_select_holding_reg[8]_lut_out, QC2__clk0, F1_data_out, , DE1_slaveselect_wr_strobe, , , , );

--DE1_data_wr_strobe is std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|data_wr_strobe

--operation mode is normal

DE1_data_wr_strobe_lut_out = DE1L138;

DE1_data_wr_strobe = DFFEAS(DE1_data_wr_strobe_lut_out, QC2__clk0, F1_data_out, , , , , , );

--M1_slave_readdata_p1[6] is std_1c20:inst|clock_1:the_clock_1|slave_readdata_p1[6]

--operation mode is normal

M1_slave_readdata_p1[6]_lut_out = M1_master_nativeaddress[0] & Q1_control_reg_out[6];

M1_slave_readdata_p1[6] = DFFEAS(M1_slave_readdata_p1[6]_lut_out, PLD_CLOCKINPUT[1], E1_data_out, , M1L22, , , , );

--J1_slave_readdata_p1[6] is std_1c20:inst|clock_0:the_clock_0|slave_readdata_p1[6]

--operation mode is normal

J1_slave_readdata_p1[6]_lut_out = J1_master_nativeaddress[0] & LB1_control_reg_out[6];

J1_slave_readdata_p1[6] = DFFEAS(J1_slave_readdata_p1[6]_lut_out, PLD_CLKFB, D1_data_out, , J1L22, , , , );

--GE1_wdata[6] is std_1c20:inst|jtag_uart:the_jtag_uart|alt_jtag_atlantic:jtag_uart_alt_jtag_atlantic|wdata[6]

--operation mode is normal

GE1_wdata[6] = AMPP_FUNCTION(A1L5, GE1_td_shift[10], !C1_CLR_SIGNAL, GE1L74);

--DE1_epcs_slave_select_holding_reg[6] is std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|epcs_slave_select_holding_reg[6]

--operation mode is normal

DE1_epcs_slave_select_holding_reg[6]_lut_out = S1_M_st_data[6];

DE1_epcs_slave_select_holding_reg[6] = DFFEAS(DE1_epcs_slave_select_holding_reg[6]_lut_out, QC2__clk0, F1_data_out, , DE1_slaveselect_wr_strobe, , , , );

--DE1_shift_reg[6] is std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|shift_reg[6]

--operation mode is normal

DE1_shift_reg[6]_lut_out = DE1_SCLK_reg & DE1_shift_reg[5] # !DE1_SCLK_reg & (DE1L172);

DE1_shift_reg[6] = DFFEAS(DE1_shift_reg[6]_lut_out, QC2__clk0, F1_data_out, , , DE1L172, , , !DE1_slowcount[0]);

--DE1L118 is std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|Equal9~104

--operation mode is normal

DE1L118 = DE1_state[0] & !DE1_state[1] & !DE1_state[2] & !DE1_state[3];

--M1_slave_readdata_p1[4] is std_1c20:inst|clock_1:the_clock_1|slave_readdata_p1[4]

--operation mode is normal

M1_slave_readdata_p1[4]_lut_out = M1_master_nativeaddress[0] & Q1_control_reg_out[4];

M1_slave_readdata_p1[4] = DFFEAS(M1_slave_readdata_p1[4]_lut_out, PLD_CLOCKINPUT[1], E1_data_out, , M1L22, , , , );

--J1_slave_readdata_p1[4] is std_1c20:inst|clock_0:the_clock_0|slave_readdata_p1[4]

--operation mode is normal

J1_slave_readdata_p1[4]_lut_out = J1_master_nativeaddress[0] & LB1_control_reg_out[4];

J1_slave_readdata_p1[4] = DFFEAS(J1_slave_readdata_p1[4]_lut_out, PLD_CLKFB, D1_data_out, , J1L22, , , , );

--GE1_wdata[4] is std_1c20:inst|jtag_uart:the_jtag_uart|alt_jtag_atlantic:jtag_uart_alt_jtag_atlantic|wdata[4]

--operation mode is normal

GE1_wdata[4] = AMPP_FUNCTION(A1L5, GE1_td_shift[8], !C1_CLR_SIGNAL, GE1L74);

--DE1_epcs_slave_select_holding_reg[4] is std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|epcs_slave_select_holding_reg[4]

--operation mode is normal

DE1_epcs_slave_select_holding_reg[4]_lut_out = S1_M_st_data[4];

DE1_epcs_slave_select_holding_reg[4] = DFFEAS(DE1_epcs_slave_select_holding_reg[4]_lut_out, QC2__clk0, F1_data_out, , DE1_slaveselect_wr_strobe, , , , );

--DE1_shift_reg[4] is std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|shift_reg[4]

--operation mode is normal

DE1_shift_reg[4]_lut_out = DE1_SCLK_reg & DE1_shift_reg[3] # !DE1_SCLK_reg & (DE1L173);

DE1_shift_reg[4] = DFFEAS(DE1_shift_reg[4]_lut_out, QC2__clk0, F1_data_out, , , DE1L173, , , !DE1_slowcount[0]);

--M1_slave_readdata_p1[5] is std_1c20:inst|clock_1:the_clock_1|slave_readdata_p1[5]

--operation mode is normal

M1_slave_readdata_p1[5]_lut_out = M1_master_nativeaddress[0] & Q1_control_reg_out[5];

M1_slave_readdata_p1[5] = DFFEAS(M1_slave_readdata_p1[5]_lut_out, PLD_CLOCKINPUT[1], E1_data_out, , M1L22, , , , );

--J1_slave_readdata_p1[5] is std_1c20:inst|clock_0:the_clock_0|slave_readdata_p1[5]

--operation mode is normal

J1_slave_readdata_p1[5]_lut_out = J1_master_nativeaddress[0] & LB1_control_reg_out[5];

J1_slave_readdata_p1[5] = DFFEAS(J1_slave_readdata_p1[5]_lut_out, PLD_CLKFB, D1_data_out, , J1L22, , , , );

--GE1_wdata[5] is std_1c20:inst|jtag_uart:the_jtag_uart|alt_jtag_atlantic:jtag_uart_alt_jtag_atlantic|wdata[5]

--operation mode is normal

GE1_wdata[5] = AMPP_FUNCTION(A1L5, GE1_td_shift[9], !C1_CLR_SIGNAL, GE1L74);

--DE1_epcs_slave_select_holding_reg[5] is std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|epcs_slave_select_holding_reg[5]

--operation mode is normal

DE1_epcs_slave_select_holding_reg[5]_lut_out = S1_M_st_data[5];

DE1_epcs_slave_select_holding_reg[5] = DFFEAS(DE1_epcs_slave_select_holding_reg[5]_lut_out, QC2__clk0, F1_data_out, , DE1_slaveselect_wr_strobe, , , , );

--DE1_shift_reg[5] is std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|shift_reg[5]

--operation mode is normal

DE1_shift_reg[5]_lut_out = DE1_SCLK_reg & DE1_shift_reg[4] # !DE1_SCLK_reg & (DE1L174);

DE1_shift_reg[5] = DFFEAS(DE1_shift_reg[5]_lut_out, QC2__clk0, F1_data_out, , , DE1L174, , , !DE1_slowcount[0]);

--XE1L23 is std_1c20:inst|uart1:the_uart1|uart1_regs:the_uart1_regs|Equal1~124

--operation mode is normal

XE1L23 = S1_M_alu_result[2] & S1_M_alu_result[4] & (!S1_M_alu_result[3]);

--Z1_counter_snapshot[16] is std_1c20:inst|high_res_timer:the_high_res_timer|counter_snapshot[16]

--operation mode is normal

Z1_counter_snapshot[16]_lut_out = Z1_internal_counter[16];

Z1_counter_snapshot[16] = DFFEAS(Z1_counter_snapshot[16]_lut_out, QC2__clk0, F1_data_out, , Z1L208, , , , );

--Z1L157 is std_1c20:inst|high_res_timer:the_high_res_timer|read_mux_out[0]~1289

--operation mode is normal

Z1L157 = XE1L15 & (Z1_period_h_register[0] # XE1L23 & Z1_counter_snapshot[16]) # !XE1L15 & XE1L23 & Z1_counter_snapshot[16];

--Z1L158 is std_1c20:inst|high_res_timer:the_high_res_timer|read_mux_out[0]~1290

--operation mode is normal

Z1L158 = Z1_control_register[0] & (XE1L18 # Z1_timeout_occurred & XE1L21) # !Z1_control_register[0] & Z1_timeout_occurred & XE1L21;

--Z1_counter_snapshot[0] is std_1c20:inst|high_res_timer:the_high_res_timer|counter_snapshot[0]

--operation mode is normal

Z1_counter_snapshot[0]_lut_out = !Z1_internal_counter[0];

Z1_counter_snapshot[0] = DFFEAS(Z1_counter_snapshot[0]_lut_out, QC2__clk0, F1_data_out, , Z1L208, , , , );

--Z1L159 is std_1c20:inst|high_res_timer:the_high_res_timer|read_mux_out[0]~1291

--operation mode is normal

Z1L159 = XE1L19 & (Z1_counter_snapshot[0] # XE1L20 & !Z1_period_l_register[0]) # !XE1L19 & (XE1L20 & !Z1_period_l_register[0]);

--RB1_counter_snapshot[16] is std_1c20:inst|sys_clk_timer:the_sys_clk_timer|counter_snapshot[16]

--operation mode is normal

RB1_counter_snapshot[16]_lut_out = !RB1_internal_counter[16];

RB1_counter_snapshot[16] = DFFEAS(RB1_counter_snapshot[16]_lut_out, QC2__clk0, F1_data_out, , RB1L209, , , , );

--RB1_period_h_register[0] is std_1c20:inst|sys_clk_timer:the_sys_clk_timer|period_h_register[0]

--operation mode is normal

RB1_period_h_register[0]_lut_out = !S1_M_st_data[0];

RB1_period_h_register[0] = DFFEAS(RB1_period_h_register[0]_lut_out, QC2__clk0, F1_data_out, , RB1_period_h_wr_strobe, , , , );

--RB1L158 is std_1c20:inst|sys_clk_timer:the_sys_clk_timer|read_mux_out[0]~1278

--operation mode is normal

RB1L158 = XE1L23 & (RB1_counter_snapshot[16] # XE1L15 & !RB1_period_h_register[0]) # !XE1L23 & (XE1L15 & !RB1_period_h_register[0]);

--RB1L159 is std_1c20:inst|sys_clk_timer:the_sys_clk_timer|read_mux_out[0]~1279

--operation mode is normal

RB1L159 = XE1L18 & (RB1_control_register[0] # RB1_timeout_occurred & XE1L21) # !XE1L18 & RB1_timeout_occurred & XE1L21;

--RB1_counter_snapshot[0] is std_1c20:inst|sys_clk_timer:the_sys_clk_timer|counter_snapshot[0]

--operation mode is normal

RB1_counter_snapshot[0]_lut_out = !RB1_internal_counter[0];

RB1_counter_snapshot[0] = DFFEAS(RB1_counter_snapshot[0]_lut_out, QC2__clk0, F1_data_out, , RB1L209, , , , );

--RB1_period_l_register[0] is std_1c20:inst|sys_clk_timer:the_sys_clk_timer|period_l_register[0]

--operation mode is normal

RB1_period_l_register[0]_lut_out = !S1_M_st_data[0];

RB1_period_l_register[0] = DFFEAS(RB1_period_l_register[0]_lut_out, QC2__clk0, F1_data_out, , RB1_period_l_wr_strobe, , , , );

--RB1L160 is std_1c20:inst|sys_clk_timer:the_sys_clk_timer|read_mux_out[0]~1280

--operation mode is normal

RB1L160 = XE1L19 & (RB1_counter_snapshot[0] # XE1L20 & !RB1_period_l_register[0]) # !XE1L19 & (XE1L20 & !RB1_period_l_register[0]);

--G1L27 is std_1c20:inst|button_pio:the_button_pio|read_mux_out[0]~380

--operation mode is normal

G1L27 = S1_M_alu_result[2] & G1_edge_capture[0] # !S1_M_alu_result[2] & (G1_irq_mask[0]);

--XE1_control_reg[0] is std_1c20:inst|uart1:the_uart1|uart1_regs:the_uart1_regs|control_reg[0]

--operation mode is normal

XE1_control_reg[0]_lut_out = S1_M_st_data[0];

XE1_control_reg[0] = DFFEAS(XE1_control_reg[0]_lut_out, QC2__clk0, F1_data_out, , XE1L14, , , , );

--YE1_rx_data[0] is std_1c20:inst|uart1:the_uart1|uart1_rx:the_uart1_rx|rx_data[0]

--operation mode is normal

YE1_rx_data[0]_lut_out = YE1_unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[1];

YE1_rx_data[0] = DFFEAS(YE1_rx_data[0]_lut_out, QC2__clk0, F1_data_out, , YE1_got_new_char, , , , );

--XE1L49 is std_1c20:inst|uart1:the_uart1|uart1_regs:the_uart1_regs|selected_read_data[0]~695

--operation mode is normal

XE1L49 = !S1_M_alu_result[3] & (S1_M_alu_result[2] & XE1_internal_tx_data[0] # !S1_M_alu_result[2] & (YE1_rx_data[0]));

--M1_slave_readdata[0] is std_1c20:inst|clock_1:the_clock_1|slave_readdata[0]

--operation mode is normal

M1_slave_readdata[0]_lut_out = M1_slave_readdata_p1[0];

M1_slave_readdata[0] = DFFEAS(M1_slave_readdata[0]_lut_out, QC2__clk0, F1_data_out, , , , , , );

--J1_slave_readdata[0] is std_1c20:inst|clock_0:the_clock_0|slave_readdata[0]

--operation mode is normal

J1_slave_readdata[0]_lut_out = J1_slave_readdata_p1[0];

J1_slave_readdata[0] = DFFEAS(J1_slave_readdata[0]_lut_out, QC2__clk0, F1_data_out, , , , , , );

--T1L243 is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|p1_registered_cpu_data_master_readdata[0]~2086

--operation mode is normal

T1L243 = S1_M_alu_result[5] & M1_slave_readdata[0] # !S1_M_alu_result[5] & (J1_slave_readdata[0]) # !K1L6;

--SE2_q_b[0] is std_1c20:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_r:the_jtag_uart_scfifo_r|scfifo:rfifo|scfifo_jf21:auto_generated|a_dpfifo_ml21:dpfifo|dpram_j921:FIFOram|altsyncram_nll1:altsyncram1|q_b[0]

--RAM Block Operation Mode: Simple Dual-Port

--Port A Depth: 64, Port A Width: 1, Port B Depth: 64, Port B Width: 1

--Port A Logical Depth: 64, Port A Logical Width: 8, Port B Logical Depth: 64, Port B Logical Width: 8

--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered

SE2_q_b[0]_PORT_A_data_in = GE1_wdata[0];

SE2_q_b[0]_PORT_A_data_in_reg = DFFE(SE2_q_b[0]_PORT_A_data_in, SE2_q_b[0]_clock_0, , , SE2_q_b[0]_clock_enable_0);

SE2_q_b[0]_PORT_A_address = BUS(QE4_safe_q[0], QE4_safe_q[1], QE4_safe_q[2], QE4_safe_q[3], QE4_safe_q[4], QE4_safe_q[5]);

SE2_q_b[0]_PORT_A_address_reg = DFFE(SE2_q_b[0]_PORT_A_address, SE2_q_b[0]_clock_0, , , SE2_q_b[0]_clock_enable_0);

SE2_q_b[0]_PORT_B_address = BUS(QE3_safe_q[0], QE3_safe_q[1], QE3_safe_q[2], QE3_safe_q[3], QE3_safe_q[4], QE3_safe_q[5]);

SE2_q_b[0]_PORT_B_address_reg = DFFE(SE2_q_b[0]_PORT_B_address, SE2_q_b[0]_clock_1, , , SE2_q_b[0]_clock_enable_1);

SE2_q_b[0]_PORT_A_write_enable = VCC;

SE2_q_b[0]_PORT_A_write_enable_reg = DFFE(SE2_q_b[0]_PORT_A_write_enable, SE2_q_b[0]_clock_0, , , SE2_q_b[0]_clock_enable_0);

SE2_q_b[0]_PORT_B_read_enable = VCC;

SE2_q_b[0]_PORT_B_read_enable_reg = DFFE(SE2_q_b[0]_PORT_B_read_enable, SE2_q_b[0]_clock_1, , , SE2_q_b[0]_clock_enable_1);

SE2_q_b[0]_clock_0 = QC2__clk0;

SE2_q_b[0]_clock_1 = QC2__clk0;

SE2_q_b[0]_clock_enable_0 = BB1_wr_rfifo;

SE2_q_b[0]_clock_enable_1 = BB1L61;

SE2_q_b[0]_PORT_B_data_out = MEMORY(SE2_q_b[0]_PORT_A_data_in_reg, , SE2_q_b[0]_PORT_A_address_reg, SE2_q_b[0]_PORT_B_address_reg, SE2_q_b[0]_PORT_A_write_enable_reg, SE2_q_b[0]_PORT_B_read_enable_reg, , , SE2_q_b[0]_clock_0, SE2_q_b[0]_clock_1, SE2_q_b[0]_clock_enable_0, SE2_q_b[0]_clock_enable_1, , );

SE2_q_b[0] = SE2_q_b[0]_PORT_B_data_out[0];

--T1L289 is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|p1_registered_cpu_data_master_readdata~2087

--operation mode is normal

T1L289 = BB1_read_0 & SE2_q_b[0] # !BB1_read_0 & (BB1_ien_AF);

--T1L273 is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|p1_registered_cpu_data_master_readdata~49

--operation mode is normal

T1L273 = T1L289 # !CB1L2 # !UB1L9;

--DE1_epcs_slave_select_reg[0] is std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|epcs_slave_select_reg[0]

--operation mode is normal

DE1_epcs_slave_select_reg[0]_lut_out = DE1_epcs_slave_select_holding_reg[0];

DE1_epcs_slave_select_reg[0] = DFFEAS(DE1_epcs_slave_select_reg[0]_lut_out, QC2__clk0, F1_data_out, , DE1L142, , , , );

--DE1L131 is std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|p1_data_to_cpu[0]~873

--operation mode is normal

DE1L131 = DE1L113 & (!DE1_epcs_slave_select_reg[0]) # !DE1L113 & DE1_rx_holding_reg[0];

--Z1_counter_snapshot[17] is std_1c20:inst|high_res_timer:the_high_res_timer|counter_snapshot[17]

--operation mode is normal

Z1_counter_snapshot[17]_lut_out = Z1_internal_counter[17];

Z1_counter_snapshot[17] = DFFEAS(Z1_counter_snapshot[17]_lut_out, QC2__clk0, F1_data_out, , Z1L208, , , , );

--Z1L160 is std_1c20:inst|high_res_timer:the_high_res_timer|read_mux_out[1]~1292

--operation mode is normal

Z1L160 = XE1L15 & (Z1_period_h_register[1] # XE1L23 & Z1_counter_snapshot[17]) # !XE1L15 & XE1L23 & Z1_counter_snapshot[17];

--Z1_control_register[1] is std_1c20:inst|high_res_timer:the_high_res_timer|control_register[1]

--operation mode is normal

Z1_control_register[1]_lut_out = S1_M_st_data[1];

Z1_control_register[1] = DFFEAS(Z1_control_register[1]_lut_out, QC2__clk0, F1_data_out, , Z1_control_wr_strobe, , , , );

--Z1L161 is std_1c20:inst|high_res_timer:the_high_res_timer|read_mux_out[1]~1293

--operation mode is normal

Z1L161 = XE1L18 & (Z1_control_register[1] # XE1L21 & Z1_counter_is_running) # !XE1L18 & XE1L21 & Z1_counter_is_running;

--Z1_counter_snapshot[1] is std_1c20:inst|high_res_timer:the_high_res_timer|counter_snapshot[1]

--operation mode is normal

Z1_counter_snapshot[1]_lut_out = !Z1_internal_counter[1];

Z1_counter_snapshot[1] = DFFEAS(Z1_counter_snapshot[1]_lut_out, QC2__clk0, F1_data_out, , Z1L208, , , , );

--Z1L162 is std_1c20:inst|high_res_timer:the_high_res_timer|read_mux_out[1]~1294

--operation mode is normal

Z1L162 = XE1L19 & (Z1_counter_snapshot[1] # XE1L20 & !Z1_period_l_register[1]) # !XE1L19 & (XE1L20 & !Z1_period_l_register[1]);

--G1L28 is std_1c20:inst|button_pio:the_button_pio|read_mux_out[1]~382

--operation mode is normal

G1L28 = S1_M_alu_result[2] & G1_edge_capture[1] # !S1_M_alu_result[2] & (G1_irq_mask[1]);

--XE1L50 is std_1c20:inst|uart1:the_uart1|uart1_regs:the_uart1_regs|selected_read_data[1]~697

--operation mode is normal

XE1L50 = S1_M_alu_result[3] & (XE1_control_reg[1]) # !S1_M_alu_result[3] & XE1_internal_tx_data[1];

--YE1_rx_data[1] is std_1c20:inst|uart1:the_uart1|uart1_rx:the_uart1_rx|rx_data[1]

--operation mode is normal

YE1_rx_data[1]_lut_out = YE1_unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[2];

YE1_rx_data[1] = DFFEAS(YE1_rx_data[1]_lut_out, QC2__clk0, F1_data_out, , YE1_got_new_char, , , , );

--XE1L51 is std_1c20:inst|uart1:the_uart1|uart1_regs:the_uart1_regs|selected_read_data[1]~698

--operation mode is normal

XE1L51 = S1_M_alu_result[3] & YE1_framing_error # !S1_M_alu_result[3] & (YE1_rx_data[1]);

--RB1_counter_snapshot[17] is std_1c20:inst|sys_clk_timer:the_sys_clk_timer|counter_snapshot[17]

--operation mode is normal

RB1_counter_snapshot[17]_lut_out = !RB1_internal_counter[17];

RB1_counter_snapshot[17] = DFFEAS(RB1_counter_snapshot[17]_lut_out, QC2__clk0, F1_data_out, , RB1L209, , , , );

--RB1_period_h_register[1] is std_1c20:inst|sys_clk_timer:the_sys_clk_timer|period_h_register[1]

--operation mode is normal

RB1_period_h_register[1]_lut_out = !S1_M_st_data[1];

RB1_period_h_register[1] = DFFEAS(RB1_period_h_register[1]_lut_out, QC2__clk0, F1_data_out, , RB1_period_h_wr_strobe, , , , );

--RB1L161 is std_1c20:inst|sys_clk_timer:the_sys_clk_timer|read_mux_out[1]~1281

--operation mode is normal

RB1L161 = XE1L23 & (RB1_counter_snapshot[17] # XE1L15 & !RB1_period_h_register[1]) # !XE1L23 & (XE1L15 & !RB1_period_h_register[1]);

--RB1_counter_is_running is std_1c20:inst|sys_clk_timer:the_sys_clk_timer|counter_is_running

--operation mode is normal

RB1_counter_is_running_lut_out = RB1_control_wr_strobe & (S1_M_st_data[2] # RB1L10 & !S1_M_st_data[3]) # !RB1_control_wr_strobe & (RB1L10);

RB1_counter_is_running = DFFEAS(RB1_counter_is_running_lut_out, QC2__clk0, F1_data_out, , , , , , );

--RB1_control_register[1] is std_1c20:inst|sys_clk_timer:the_sys_clk_timer|control_register[1]

--operation mode is normal

RB1_control_register[1]_lut_out = S1_M_st_data[1];

RB1_control_register[1] = DFFEAS(RB1_control_register[1]_lut_out, QC2__clk0, F1_data_out, , RB1_control_wr_strobe, , , , );

--RB1L162 is std_1c20:inst|sys_clk_timer:the_sys_clk_timer|read_mux_out[1]~1282

--operation mode is normal

RB1L162 = XE1L18 & (RB1_control_register[1] # XE1L21 & RB1_counter_is_running) # !XE1L18 & XE1L21 & RB1_counter_is_running;

--RB1_counter_snapshot[1] is std_1c20:inst|sys_clk_timer:the_sys_clk_timer|counter_snapshot[1]

--operation mode is normal

RB1_counter_snapshot[1]_lut_out = !RB1_internal_counter[1];

RB1_counter_snapshot[1] = DFFEAS(RB1_counter_snapshot[1]_lut_out, QC2__clk0, F1_data_out, , RB1L209, , , , );

--RB1_period_l_register[1] is std_1c20:inst|sys_clk_timer:the_sys_clk_timer|period_l_register[1]

--operation mode is normal

RB1_period_l_register[1]_lut_out = !S1_M_st_data[1];

RB1_period_l_register[1] = DFFEAS(RB1_period_l_register[1]_lut_out, QC2__clk0, F1_data_out, , RB1_period_l_wr_strobe, , , , );

--RB1L163 is std_1c20:inst|sys_clk_timer:the_sys_clk_timer|read_mux_out[1]~1283

--operation mode is normal

RB1L163 = XE1L19 & (RB1_counter_snapshot[1] # XE1L20 & !RB1_period_l_register[1]) # !XE1L19 & (XE1L20 & !RB1_period_l_register[1]);

--M1_slave_readdata[1] is std_1c20:inst|clock_1:the_clock_1|slave_readdata[1]

--operation mode is normal

M1_slave_readdata[1]_lut_out = M1_slave_readdata_p1[1];

M1_slave_readdata[1] = DFFEAS(M1_slave_readdata[1]_lut_out, QC2__clk0, F1_data_out, , , , , , );

--J1_slave_readdata[1] is std_1c20:inst|clock_0:the_clock_0|slave_readdata[1]

--operation mode is normal

J1_slave_readdata[1]_lut_out = J1_slave_readdata_p1[1];

J1_slave_readdata[1] = DFFEAS(J1_slave_readdata[1]_lut_out, QC2__clk0, F1_data_out, , , , , , );

--T1L244 is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|p1_registered_cpu_data_master_readdata[1]~2089

--operation mode is normal

T1L244 = S1_M_alu_result[5] & M1_slave_readdata[1] # !S1_M_alu_result[5] & (J1_slave_readdata[1]) # !K1L6;

--SE2_q_b[1] is std_1c20:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_r:the_jtag_uart_scfifo_r|scfifo:rfifo|scfifo_jf21:auto_generated|a_dpfifo_ml21:dpfifo|dpram_j921:FIFOram|altsyncram_nll1:altsyncram1|q_b[1]

--RAM Block Operation Mode: Simple Dual-Port

--Port A Depth: 64, Port A Width: 1, Port B Depth: 64, Port B Width: 1

--Port A Logical Depth: 64, Port A Logical Width: 8, Port B Logical Depth: 64, Port B Logical Width: 8

--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered

SE2_q_b[1]_PORT_A_data_in = GE1_wdata[1];

SE2_q_b[1]_PORT_A_data_in_reg = DFFE(SE2_q_b[1]_PORT_A_data_in, SE2_q_b[1]_clock_0, , , SE2_q_b[1]_clock_enable_0);

SE2_q_b[1]_PORT_A_address = BUS(QE4_safe_q[0], QE4_safe_q[1], QE4_safe_q[2], QE4_safe_q[3], QE4_safe_q[4], QE4_safe_q[5]);

SE2_q_b[1]_PORT_A_address_reg = DFFE(SE2_q_b[1]_PORT_A_address, SE2_q_b[1]_clock_0, , , SE2_q_b[1]_clock_enable_0);

SE2_q_b[1]_PORT_B_address = BUS(QE3_safe_q[0], QE3_safe_q[1], QE3_safe_q[2], QE3_safe_q[3], QE3_safe_q[4], QE3_safe_q[5]);

SE2_q_b[1]_PORT_B_address_reg = DFFE(SE2_q_b[1]_PORT_B_address, SE2_q_b[1]_clock_1, , , SE2_q_b[1]_clock_enable_1);

SE2_q_b[1]_PORT_A_write_enable = VCC;

SE2_q_b[1]_PORT_A_write_enable_reg = DFFE(SE2_q_b[1]_PORT_A_write_enable, SE2_q_b[1]_clock_0, , , SE2_q_b[1]_clock_enable_0);

SE2_q_b[1]_PORT_B_read_enable = VCC;

SE2_q_b[1]_PORT_B_read_enable_reg = DFFE(SE2_q_b[1]_PORT_B_read_enable, SE2_q_b[1]_clock_1, , , SE2_q_b[1]_clock_enable_1);

SE2_q_b[1]_clock_0 = QC2__clk0;

SE2_q_b[1]_clock_1 = QC2__clk0;

SE2_q_b[1]_clock_enable_0 = BB1_wr_rfifo;

SE2_q_b[1]_clock_enable_1 = BB1L61;

SE2_q_b[1]_PORT_B_data_out = MEMORY(SE2_q_b[1]_PORT_A_data_in_reg, , SE2_q_b[1]_PORT_A_address_reg, SE2_q_b[1]_PORT_B_address_reg, SE2_q_b[1]_PORT_A_write_enable_reg, SE2_q_b[1]_PORT_B_read_enable_reg, , , SE2_q_b[1]_clock_0, SE2_q_b[1]_clock_1, SE2_q_b[1]_clock_enable_0, SE2_q_b[1]_clock_enable_1, , );

SE2_q_b[1] = SE2_q_b[1]_PORT_B_data_out[0];

--T1L290 is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|p1_registered_cpu_data_master_readdata~2090

--operation mode is normal

T1L290 = BB1_read_0 & SE2_q_b[1] # !BB1_read_0 & (BB1_ien_AE);

--T1L274 is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|p1_registered_cpu_data_master_readdata~50

--operation mode is normal

T1L274 = T1L290 # !CB1L2 # !UB1L9;

--DE1_epcs_slave_select_reg[1] is std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|epcs_slave_select_reg[1]

--operation mode is normal

DE1_epcs_slave_select_reg[1]_lut_out = DE1_epcs_slave_select_holding_reg[1];

DE1_epcs_slave_select_reg[1] = DFFEAS(DE1_epcs_slave_select_reg[1]_lut_out, QC2__clk0, F1_data_out, , DE1L142, , , , );

--DE1L132 is std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|p1_data_to_cpu[1]~875

--operation mode is normal

DE1L132 = DE1L113 & DE1_epcs_slave_select_reg[1] # !DE1L113 & (DE1_rx_holding_reg[1]);

--CF1L12 is sld_hub:sld_hub_inst|sld_rom_sr:HUB_INFO_REG|Mux1~67

--operation mode is normal

CF1L12 = AMPP_FUNCTION(CF1_word_counter[0], CF1_word_counter[1], CF1_word_counter[4], CF1_word_counter[3]);

--CF1L13 is sld_hub:sld_hub_inst|sld_rom_sr:HUB_INFO_REG|Mux1~68

--operation mode is normal

CF1L13 = AMPP_FUNCTION(CF1_word_counter[4], CF1_word_counter[1], CF1_word_counter[0], CF1_word_counter[3]);

--CF1_WORD_SR[3] is sld_hub:sld_hub_inst|sld_rom_sr:HUB_INFO_REG|WORD_SR[3]

--operation mode is normal

CF1_WORD_SR[3] = AMPP_FUNCTION(A1L5, altera_internal_jtag, CF1L14, FF1_state[4], CF1_clear_signal, VCC, CF1L21);

--SD1_internal_jdo1[0] is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|internal_jdo1[0]

--operation mode is normal

SD1_internal_jdo1[0] = AMPP_FUNCTION(A1L8, SD1_sr[0], VCC, SD1L145);

--GD1_break_readreg[1] is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_break:the_cpu_nios2_oci_break|break_readreg[1]

--operation mode is normal

GD1_break_readreg[1] = AMPP_FUNCTION(QC2__clk0, SD1_internal_jdo1[1], SD1_internal_jdo1[36], SD1_internal_jdo1[37], SD1L189, !C1_CLR_SIGNAL, SD1L189);

--SD1L130 is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|Mux38~14

--operation mode is normal

SD1L130 = AMPP_FUNCTION(RD1_internal_MonDReg[1], SD1_ir[1], GD1_break_readreg[1], SD1_ir[0]);

--SD1_sr[3] is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|sr[3]

--operation mode is normal

SD1_sr[3] = AMPP_FUNCTION(A1L5, SD1L129, SD1_sr[4], SD1L144, SD1L142, !C1_CLR_SIGNAL, SD1L6);

--SD1_sr[25] is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|sr[25]

--operation mode is normal

SD1_sr[25] = AMPP_FUNCTION(A1L5, SD1L70, SD1_sr[26], SD1L35, SD1L34, !C1_CLR_SIGNAL, SD1L12);

--GE1L19 is std_1c20:inst|jtag_uart:the_jtag_uart|alt_jtag_atlantic:jtag_uart_alt_jtag_atlantic|r_ena~1

--operation mode is normal

GE1L19 = AMPP_FUNCTION(GE1_rvalid0, BB1_r_val, GE1_r_ena1);

--GE1_read_write1 is std_1c20:inst|jtag_uart:the_jtag_uart|alt_jtag_atlantic:jtag_uart_alt_jtag_atlantic|read_write1

--operation mode is normal

GE1_read_write1 = AMPP_FUNCTION(QC2__clk0, GE1_read_write, F1_data_out);

--GE1_read_write2 is std_1c20:inst|jtag_uart:the_jtag_uart|alt_jtag_atlantic:jtag_uart_alt_jtag_atlantic|read_write2

--operation mode is normal

GE1_read_write2 = AMPP_FUNCTION(QC2__clk0, GE1_read_write1, F1_data_out);

--GE1L2 is std_1c20:inst|jtag_uart:the_jtag_uart|alt_jtag_atlantic:jtag_uart_alt_jtag_atlantic|always2~2

--operation mode is normal

GE1L2 = AMPP_FUNCTION(GE1_read_write1, GE1_read_write2);

--GE1_read_req is std_1c20:inst|jtag_uart:the_jtag_uart|alt_jtag_atlantic:jtag_uart_alt_jtag_atlantic|read_req

--operation mode is normal

GE1_read_req = AMPP_FUNCTION(A1L5, GE1_td_shift[9], !C1_CLR_SIGNAL, GE1L72);

--GE1L72 is std_1c20:inst|jtag_uart:the_jtag_uart|alt_jtag_atlantic:jtag_uart_alt_jtag_atlantic|wdata[0]~7

--operation mode is normal

GE1L72 = AMPP_FUNCTION(GE1_count[1], GE1L69);

--GE1_rdata[0] is std_1c20:inst|jtag_uart:the_jtag_uart|alt_jtag_atlantic:jtag_uart_alt_jtag_atlantic|rdata[0]

--operation mode is normal

GE1_rdata[0] = AMPP_FUNCTION(QC2__clk0, SE1_q_b[0], F1_data_out, GE1L18);

--GE1_td_shift[3] is std_1c20:inst|jtag_uart:the_jtag_uart|alt_jtag_atlantic:jtag_uart_alt_jtag_atlantic|td_shift[3]

--operation mode is normal

GE1_td_shift[3] = AMPP_FUNCTION(A1L5, FF1_state[4], GE1L57, BF4_Q[0], GE1L62, !C1_CLR_SIGNAL, GE1L52);

--GE1L56 is std_1c20:inst|jtag_uart:the_jtag_uart|alt_jtag_atlantic:jtag_uart_alt_jtag_atlantic|td_shift[9]~3557

--operation mode is normal

GE1L56 = AMPP_FUNCTION(GE1_rdata[0], GE1_td_shift[3], GE1_count[9]);

--GE1_count[7] is std_1c20:inst|jtag_uart:the_jtag_uart|alt_jtag_atlantic:jtag_uart_alt_jtag_atlantic|count[7]

--operation mode is normal

GE1_count[7] = AMPP_FUNCTION(A1L5, FF1_state[4], GE1_count[6], !C1_CLR_SIGNAL, GE1L52);

--SE1_q_b[7] is std_1c20:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_w:the_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_jf21:auto_generated|a_dpfifo_ml21:dpfifo|dpram_j921:FIFOram|altsyncram_nll1:altsyncram1|q_b[7]

--RAM Block Operation Mode: Simple Dual-Port

--Port A Depth: 64, Port A Width: 1, Port B Depth: 64, Port B Width: 1

--Port A Logical Depth: 64, Port A Logical Width: 8, Port B Logical Depth: 64, Port B Logical Width: 8

--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered

SE1_q_b[7]_PORT_A_data_in = S1_M_st_data[7];

SE1_q_b[7]_PORT_A_data_in_reg = DFFE(SE1_q_b[7]_PORT_A_data_in, SE1_q_b[7]_clock_0, , , SE1_q_b[7]_clock_enable_0);

SE1_q_b[7]_PORT_A_address = BUS(QE2_safe_q[0], QE2_safe_q[1], QE2_safe_q[2], QE2_safe_q[3], QE2_safe_q[4], QE2_safe_q[5]);

SE1_q_b[7]_PORT_A_address_reg = DFFE(SE1_q_b[7]_PORT_A_address, SE1_q_b[7]_clock_0, , , SE1_q_b[7]_clock_enable_0);

SE1_q_b[7]_PORT_B_address = BUS(QE1_safe_q[0], QE1_safe_q[1], QE1_safe_q[2], QE1_safe_q[3], QE1_safe_q[4], QE1_safe_q[5]);

SE1_q_b[7]_PORT_B_address_reg = DFFE(SE1_q_b[7]_PORT_B_address, SE1_q_b[7]_clock_1, , , SE1_q_b[7]_clock_enable_1);

SE1_q_b[7]_PORT_A_write_enable = VCC;

SE1_q_b[7]_PORT_A_write_enable_reg = DFFE(SE1_q_b[7]_PORT_A_write_enable, SE1_q_b[7]_clock_0, , , SE1_q_b[7]_clock_enable_0);

SE1_q_b[7]_PORT_B_read_enable = VCC;

SE1_q_b[7]_PORT_B_read_enable_reg = DFFE(SE1_q_b[7]_PORT_B_read_enable, SE1_q_b[7]_clock_1, , , SE1_q_b[7]_clock_enable_1);

SE1_q_b[7]_clock_0 = QC2__clk0;

SE1_q_b[7]_clock_1 = QC2__clk0;

SE1_q_b[7]_clock_enable_0 = BB1_fifo_wr;

SE1_q_b[7]_clock_enable_1 = BB1_rd_wfifo;

SE1_q_b[7]_PORT_B_data_out = MEMORY(SE1_q_b[7]_PORT_A_data_in_reg, , SE1_q_b[7]_PORT_A_address_reg, SE1_q_b[7]_PORT_B_address_reg, SE1_q_b[7]_PORT_A_write_enable_reg, SE1_q_b[7]_PORT_B_read_enable_reg, , , SE1_q_b[7]_clock_0, SE1_q_b[7]_clock_1, SE1_q_b[7]_clock_enable_0, SE1_q_b[7]_clock_enable_1, , );

SE1_q_b[7] = SE1_q_b[7]_PORT_B_data_out[0];

--GE1L18 is std_1c20:inst|jtag_uart:the_jtag_uart|alt_jtag_atlantic:jtag_uart_alt_jtag_atlantic|r_ena~0

--operation mode is normal

GE1L18 = AMPP_FUNCTION(BB1_r_val, GE1_r_ena1);

--DD1_q_b[30] is std_1c20:inst|cpu:the_cpu|cpu_register_bank_b_module:cpu_register_bank_b|altsyncram:the_altsyncram|altsyncram_4vd1:auto_generated|q_b[30]

--RAM Block Operation Mode: Simple Dual-Port

--Port A Depth: 32, Port A Width: 1, Port B Depth: 32, Port B Width: 1

--Port A Logical Depth: 32, Port A Logical Width: 32, Port B Logical Depth: 32, Port B Logical Width: 32

--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered

DD1_q_b[30] = AMPP_FUNCTION(GND, GND, QC2__clk0, QC2__clk0, !S1_M_wr_dst_reg, S1_W_stall, S1L1372, S1_M_dst_regnum[0], S1_M_dst_regnum[1], S1_M_dst_regnum[2], S1_M_dst_regnum[3], S1_M_dst_regnum[4], AD1_q_b[22], AD1_q_b[23], AD1_q_b[24], AD1_q_b[25], AD1_q_b[26]);

--S1_W_wr_data[30] is std_1c20:inst|cpu:the_cpu|W_wr_data[30]

--operation mode is normal

S1_W_wr_data[30] = AMPP_FUNCTION(QC2__clk0, S1L1372, F1_data_out, S1_W_stall);

--S1L80 is std_1c20:inst|cpu:the_cpu|A_WE_StdLogicVector~14160

--operation mode is normal

S1L80 = AMPP_FUNCTION(YC1_result[30], S1_E_ctrl_dst_data_sel_pc_plus_one);

--S1L538 is std_1c20:inst|cpu:the_cpu|E_logic_result[30]~15617

--operation mode is normal

S1L538 = AMPP_FUNCTION(S1_E_logic_op[1], S1L599, S1L665, S1_E_logic_op[0]);

--DD1_q_b[29] is std_1c20:inst|cpu:the_cpu|cpu_register_bank_b_module:cpu_register_bank_b|altsyncram:the_altsyncram|altsyncram_4vd1:auto_generated|q_b[29]

--RAM Block Operation Mode: Simple Dual-Port

--Port A Depth: 32, Port A Width: 1, Port B Depth: 32, Port B Width: 1

--Port A Logical Depth: 32, Port A Logical Width: 32, Port B Logical Depth: 32, Port B Logical Width: 32

--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered

DD1_q_b[29] = AMPP_FUNCTION(GND, GND, QC2__clk0, QC2__clk0, !S1_M_wr_dst_reg, S1_W_stall, S1L1369, S1_M_dst_regnum[0], S1_M_dst_regnum[1], S1_M_dst_regnum[2], S1_M_dst_regnum[3], S1_M_dst_regnum[4], AD1_q_b[22], AD1_q_b[23], AD1_q_b[24], AD1_q_b[25], AD1_q_b[26]);

--S1_W_wr_data[29] is std_1c20:inst|cpu:the_cpu|W_wr_data[29]

--operation mode is normal

S1_W_wr_data[29] = AMPP_FUNCTION(QC2__clk0, S1L1369, F1_data_out, S1_W_stall);

--S1_E_src1_prelim[29] is std_1c20:inst|cpu:the_cpu|E_src1_prelim[29]

--operation mode is normal

S1_E_src1_prelim[29] = AMPP_FUNCTION(QC2__clk0, CD1_q_b[29], S1_W_wr_data[29], S1L1369, S1_D_src1_hazard_W, F1_data_out, S1_D_src1_hazard_M, S1_W_stall);

--S1L598 is std_1c20:inst|cpu:the_cpu|E_src1[29]~2046

--operation mode is normal

S1L598 = AMPP_FUNCTION(S1_E_src1_prelim[29], S1_E_src1_hazard_M, S1L1367, S1L1368);

--S1L81 is std_1c20:inst|cpu:the_cpu|A_WE_StdLogicVector~14161

--operation mode is normal

S1L81 = AMPP_FUNCTION(YC1_result[29], S1_E_ctrl_dst_data_sel_pc_plus_one);

--S1_E_src2_imm[29] is std_1c20:inst|cpu:the_cpu|E_src2_imm[29]

--operation mode is normal

S1_E_src2_imm[29] = AMPP_FUNCTION(QC2__clk0, S1_D_iw[19], S1_D_iw[21], S1L228, S1L238, F1_data_out, S1_W_stall);

--S1L664 is std_1c20:inst|cpu:the_cpu|E_src2[29]~1533

--operation mode is normal

S1L664 = AMPP_FUNCTION(S1_E_src2_imm[29], S1L739, S1_E_ctrl_src2_is_imm);

--S1L537 is std_1c20:inst|cpu:the_cpu|E_logic_result[29]~15618

--operation mode is normal

S1L537 = AMPP_FUNCTION(S1_E_logic_op[1], S1L598, S1L664, S1_E_logic_op[0]);

--DD1_q_b[28] is std_1c20:inst|cpu:the_cpu|cpu_register_bank_b_module:cpu_register_bank_b|altsyncram:the_altsyncram|altsyncram_4vd1:auto_generated|q_b[28]

--RAM Block Operation Mode: Simple Dual-Port

--Port A Depth: 32, Port A Width: 1, Port B Depth: 32, Port B Width: 1

--Port A Logical Depth: 32, Port A Logical Width: 32, Port B Logical Depth: 32, Port B Logical Width: 32

--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered

DD1_q_b[28] = AMPP_FUNCTION(GND, GND, QC2__clk0, QC2__clk0, !S1_M_wr_dst_reg, S1_W_stall, S1L1366, S1_M_dst_regnum[0], S1_M_dst_regnum[1], S1_M_dst_regnum[2], S1_M_dst_regnum[3], S1_M_dst_regnum[4], AD1_q_b[22], AD1_q_b[23], AD1_q_b[24], AD1_q_b[25], AD1_q_b[26]);

--S1_W_wr_data[28] is std_1c20:inst|cpu:the_cpu|W_wr_data[28]

--operation mode is normal

S1_W_wr_data[28] = AMPP_FUNCTION(QC2__clk0, S1L1366, F1_data_out, S1_W_stall);

--YC1_result[28] is std_1c20:inst|cpu:the_cpu|lpm_add_sub:Add8|alt_stratix_add_sub:stratix_adder|result[28]

--operation mode is arithmetic

YC1_result[28] = AMPP_FUNCTION(S1L663, S1L597, YC1L57, S1_E_ctrl_alu_subtract);

--YC1L59 is std_1c20:inst|cpu:the_cpu|lpm_add_sub:Add8|alt_stratix_add_sub:stratix_adder|add_sub_cell[28]~COUT

--operation mode is arithmetic

YC1L59 = AMPP_FUNCTION(S1L663, S1L597, YC1L57, S1_E_ctrl_alu_subtract);

--S1L82 is std_1c20:inst|cpu:the_cpu|A_WE_StdLogicVector~14162

--operation mode is normal

S1L82 = AMPP_FUNCTION(YC1_result[28], S1_E_ctrl_dst_data_sel_pc_plus_one);

--S1_E_src2_imm[28] is std_1c20:inst|cpu:the_cpu|E_src2_imm[28]

--operation mode is normal

S1_E_src2_imm[28] = AMPP_FUNCTION(QC2__clk0, S1_D_iw[18], S1_D_iw[21], S1L228, S1L238, F1_data_out, S1_W_stall);

--S1L663 is std_1c20:inst|cpu:the_cpu|E_src2[28]~1534

--operation mode is normal

S1L663 = AMPP_FUNCTION(S1_E_src2_imm[28], S1L738, S1_E_ctrl_src2_is_imm);

--S1L536 is std_1c20:inst|cpu:the_cpu|E_logic_result[28]~15619

--operation mode is normal

S1L536 = AMPP_FUNCTION(S1_E_logic_op[1], S1L597, S1L663, S1_E_logic_op[0]);

--DD1_q_b[27] is std_1c20:inst|cpu:the_cpu|cpu_register_bank_b_module:cpu_register_bank_b|altsyncram:the_altsyncram|altsyncram_4vd1:auto_generated|q_b[27]

--RAM Block Operation Mode: Simple Dual-Port

--Port A Depth: 32, Port A Width: 1, Port B Depth: 32, Port B Width: 1

--Port A Logical Depth: 32, Port A Logical Width: 32, Port B Logical Depth: 32, Port B Logical Width: 32

--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered

DD1_q_b[27] = AMPP_FUNCTION(GND, GND, QC2__clk0, QC2__clk0, !S1_M_wr_dst_reg, S1_W_stall, S1L1363, S1_M_dst_regnum[0], S1_M_dst_regnum[1], S1_M_dst_regnum[2], S1_M_dst_regnum[3], S1_M_dst_regnum[4], AD1_q_b[22], AD1_q_b[23], AD1_q_b[24], AD1_q_b[25], AD1_q_b[26]);

--WE1_stage_4 is std_1c20:inst|sdram_s1_arbitrator:the_sdram_s1|rdv_fifo_for_cpu_instruction_master_to_sdram_s1_module:rdv_fifo_for_cpu_instruction_master_to_sdram_s1|stage_4

--operation mode is normal

WE1_stage_4_lut_out = WE1_full_5 & WE1_stage_5 # !WE1_full_5 & (NB1L18);

WE1_stage_4 = DFFEAS(WE1_stage_4_lut_out, QC2__clk0, VCC, , WE1L22, , , , );

--WE1_full_4 is std_1c20:inst|sdram_s1_arbitrator:the_sdram_s1|rdv_fifo_for_cpu_instruction_master_to_sdram_s1_module:rdv_fifo_for_cpu_instruction_master_to_sdram_s1|full_4

--operation mode is normal

WE1_full_4_lut_out = KB1_za_valid & (NB1L27 & WE1_full_3 # !NB1L27 & (WE1_full_5)) # !KB1_za_valid & WE1_full_3;

WE1_full_4 = DFFEAS(WE1_full_4_lut_out, QC2__clk0, F1_data_out, , VE1L13, , , , );

--WE1L23 is std_1c20:inst|sdram_s1_arbitrator:the_sdram_s1|rdv_fifo_for_cpu_instruction_master_to_sdram_s1_module:rdv_fifo_for_cpu_instruction_master_to_sdram_s1|process6~1

--operation mode is normal

WE1L23 = KB1_za_valid # NB1L27 & (!WE1_full_3);

--MC3_data_in_d1 is std_1c20:inst|clock_1:the_clock_1|clock_1_edge_to_pulse:read_request_edge_to_pulse|data_in_d1

--operation mode is normal

MC3_data_in_d1_lut_out = HC1_data_out;

MC3_data_in_d1 = DFFEAS(MC3_data_in_d1_lut_out, PLD_CLOCKINPUT[1], E1_data_out, , , , , , );

--HC1_data_out is std_1c20:inst|clock_1:the_clock_1|clock_1_slave_read_request_sync_module:clock_1_slave_read_request_sync|data_out

--operation mode is normal

HC1_data_out_lut_out = HC1_data_in_d1;

HC1_data_out = DFFEAS(HC1_data_out_lut_out, PLD_CLOCKINPUT[1], E1_data_out, , , , , , );

--LC1L10 is std_1c20:inst|clock_1:the_clock_1|clock_1_master_FSM:master_FSM|Mux1~126

--operation mode is normal

LC1L10 = !LC1_master_state[1] & !LC1_master_state[0] & (MC3_data_in_d1 $ HC1_data_out);

--MC4_data_in_d1 is std_1c20:inst|clock_1:the_clock_1|clock_1_edge_to_pulse:write_request_edge_to_pulse|data_in_d1

--operation mode is normal

MC4_data_in_d1_lut_out = JC1_data_out;

MC4_data_in_d1 = DFFEAS(MC4_data_in_d1_lut_out, PLD_CLOCKINPUT[1], E1_data_out, , , , , , );

--JC1_data_out is std_1c20:inst|clock_1:the_clock_1|clock_1_slave_write_request_sync_module:clock_1_slave_write_request_sync|data_out

--operation mode is normal

JC1_data_out_lut_out = JC1_data_in_d1;

JC1_data_out = DFFEAS(JC1_data_out_lut_out, PLD_CLOCKINPUT[1], E1_data_out, , , , , , );

--LC1L9 is std_1c20:inst|clock_1:the_clock_1|clock_1_master_FSM:master_FSM|Mux0~178

--operation mode is normal

LC1L9 = LC1_master_state[2] # LC1_master_state[1] # MC3_data_in_d1 $ HC1_data_out;

--LC1L11 is std_1c20:inst|clock_1:the_clock_1|clock_1_master_FSM:master_FSM|Mux2~236

--operation mode is normal

LC1L11 = LC1_master_state[2] # LC1_master_state[1] & (R1_d1_reasons_to_wait # !LC1_master_state[0]);

--LC1L12 is std_1c20:inst|clock_1:the_clock_1|clock_1_master_FSM:master_FSM|Mux2~237

--operation mode is normal

LC1L12 = MC3_data_in_d1 & HC1_data_out & (MC4_data_in_d1 $ !JC1_data_out) # !MC3_data_in_d1 & !HC1_data_out & (MC4_data_in_d1 $ !JC1_data_out);

--E1_data_in_d1 is std_1c20:inst|std_1c20_reset_PLD_CLOCKINPUT_domain_synch_module:std_1c20_reset_PLD_CLOCKINPUT_domain_synch|data_in_d1

--operation mode is normal

E1_data_in_d1_lut_out = VCC;

E1_data_in_d1 = DFFEAS(E1_data_in_d1_lut_out, PLD_CLOCKINPUT[1], !B1L1, , , , , , );

--DC3_data_in_d1 is std_1c20:inst|clock_0:the_clock_0|clock_0_edge_to_pulse:read_request_edge_to_pulse|data_in_d1

--operation mode is normal

DC3_data_in_d1_lut_out = ZB1_data_out;

DC3_data_in_d1 = DFFEAS(DC3_data_in_d1_lut_out, PLD_CLKFB, D1_data_out, , , , , , );

--ZB1_data_out is std_1c20:inst|clock_0:the_clock_0|clock_0_slave_read_request_sync_module:clock_0_slave_read_request_sync|data_out

--operation mode is normal

ZB1_data_out_lut_out = ZB1_data_in_d1;

ZB1_data_out = DFFEAS(ZB1_data_out_lut_out, PLD_CLKFB, D1_data_out, , , , , , );

--CC1L10 is std_1c20:inst|clock_0:the_clock_0|clock_0_master_FSM:master_FSM|Mux1~126

--operation mode is normal

CC1L10 = !CC1_master_state[1] & !CC1_master_state[0] & (DC3_data_in_d1 $ ZB1_data_out);

--DC4_data_in_d1 is std_1c20:inst|clock_0:the_clock_0|clock_0_edge_to_pulse:write_request_edge_to_pulse|data_in_d1

--operation mode is normal

DC4_data_in_d1_lut_out = AC1_data_out;

DC4_data_in_d1 = DFFEAS(DC4_data_in_d1_lut_out, PLD_CLKFB, D1_data_out, , , , , , );

--AC1_data_out is std_1c20:inst|clock_0:the_clock_0|clock_0_slave_write_request_sync_module:clock_0_slave_write_request_sync|data_out

--operation mode is normal

AC1_data_out_lut_out = AC1_data_in_d1;

AC1_data_out = DFFEAS(AC1_data_out_lut_out, PLD_CLKFB, D1_data_out, , , , , , );

--CC1L9 is std_1c20:inst|clock_0:the_clock_0|clock_0_master_FSM:master_FSM|Mux0~173

--operation mode is normal

CC1L9 = CC1_master_state[2] # CC1_master_state[1] # DC3_data_in_d1 $ ZB1_data_out;

--CC1L11 is std_1c20:inst|clock_0:the_clock_0|clock_0_master_FSM:master_FSM|Mux2~236

--operation mode is normal

CC1L11 = CC1_master_state[2] # CC1_master_state[1] & (MB1_d1_reasons_to_wait # !CC1_master_state[0]);

--CC1L12 is std_1c20:inst|clock_0:the_clock_0|clock_0_master_FSM:master_FSM|Mux2~237

--operation mode is normal

CC1L12 = DC3_data_in_d1 & ZB1_data_out & (DC4_data_in_d1 $ !AC1_data_out) # !DC3_data_in_d1 & !ZB1_data_out & (DC4_data_in_d1 $ !AC1_data_out);

--D1_data_in_d1 is std_1c20:inst|std_1c20_reset_PLD_CLKFB_domain_synch_module:std_1c20_reset_PLD_CLKFB_domain_synch|data_in_d1

--operation mode is normal

D1_data_in_d1_lut_out = VCC;

D1_data_in_d1 = DFFEAS(D1_data_in_d1_lut_out, PLD_CLKFB, !B1L1, , , , , , );

--VE1_stage_4 is std_1c20:inst|sdram_s1_arbitrator:the_sdram_s1|rdv_fifo_for_cpu_data_master_to_sdram_s1_module:rdv_fifo_for_cpu_data_master_to_sdram_s1|stage_4

--operation mode is normal

VE1_stage_4_lut_out = WE1_full_5 & VE1_stage_5 # !WE1_full_5 & (NB1L14);

VE1_stage_4 = DFFEAS(VE1_stage_4_lut_out, QC2__clk0, VCC, , WE1L22, , , , );

--GD1_break_readreg[22] is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_break:the_cpu_nios2_oci_break|break_readreg[22]

--operation mode is normal

GD1_break_readreg[22] = AMPP_FUNCTION(QC2__clk0, SD1_internal_jdo1[22], SD1_internal_jdo1[36], SD1_internal_jdo1[37], SD1L189, !C1_CLR_SIGNAL, SD1L189);

--SD1L31 is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|DRsize[0]~20005

--operation mode is normal

SD1L31 = AMPP_FUNCTION(GD1_break_readreg[22], RD1_internal_MonDReg[22], SD1_ir[1]);

--SD1L32 is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|DRsize[0]~20006

--operation mode is normal

SD1L32 = AMPP_FUNCTION(SD1L145, SD1L143, SD1L31, SD1_ir[0]);

--SD1_sr[24] is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|sr[24]

--operation mode is normal

SD1_sr[24] = AMPP_FUNCTION(A1L5, SD1L37, SD1_sr[25], SD1L9, SD1L38, !C1_CLR_SIGNAL, SD1L12);

--SD1L33 is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|DRsize[0]~20007

--operation mode is normal

SD1L33 = AMPP_FUNCTION(SD1L31, A1L4, SD1L145, SD1_ir[0]);

--U1L176 is std_1c20:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|process3~0

--operation mode is normal

U1L176 = U1_cpu_instruction_master_dbs_rdv_counter[0] & Y1_cpu_instruction_master_read_data_valid_ext_flash_s1_shift_register[1] & (!U1_cpu_instruction_master_dbs_rdv_counter[1]);

--GE1_write_valid is std_1c20:inst|jtag_uart:the_jtag_uart|alt_jtag_atlantic:jtag_uart_alt_jtag_atlantic|write_valid

--operation mode is normal

GE1_write_valid = AMPP_FUNCTION(A1L5, GE1_td_shift[10], !C1_CLR_SIGNAL, GE1L72);

--GE1L38 is std_1c20:inst|jtag_uart:the_jtag_uart|alt_jtag_atlantic:jtag_uart_alt_jtag_atlantic|t_pause~74

--operation mode is normal

GE1L38 = AMPP_FUNCTION(BB1_t_dav, GE1_write_stalled, GE1_write_valid);

--GE1_jupdate1 is std_1c20:inst|jtag_uart:the_jtag_uart|alt_jtag_atlantic:jtag_uart_alt_jtag_atlantic|jupdate1

--operation mode is normal

GE1_jupdate1 = AMPP_FUNCTION(QC2__clk0, GE1_jupdate, F1_data_out);

--GE1_jupdate2 is std_1c20:inst|jtag_uart:the_jtag_uart|alt_jtag_atlantic:jtag_uart_alt_jtag_atlantic|jupdate2

--operation mode is normal

GE1_jupdate2 = AMPP_FUNCTION(QC2__clk0, GE1_jupdate1, F1_data_out);

--RB1_force_reload is std_1c20:inst|sys_clk_timer:the_sys_clk_timer|force_reload

--operation mode is normal

RB1_force_reload_lut_out = S1_internal_d_write & !T1_internal_cpu_data_master_waitrequest & XE1L22 & SB1_cpu_data_master_requests_sys_clk_timer_s1;

RB1_force_reload = DFFEAS(RB1_force_reload_lut_out, QC2__clk0, F1_data_out, , , , , , );

--RB1L157 is std_1c20:inst|sys_clk_timer:the_sys_clk_timer|process0~1

--operation mode is normal

RB1L157 = RB1_force_reload # RB1L49 & RB1L54;

--RB1L156 is std_1c20:inst|sys_clk_timer:the_sys_clk_timer|process0~0

--operation mode is normal

RB1L156 = RB1_counter_is_running # RB1_force_reload;

--U1L175 is std_1c20:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|process2~0

--operation mode is normal

U1L175 = Y1_cpu_instruction_master_read_data_valid_ext_flash_s1_shift_register[1] & (!U1_cpu_instruction_master_dbs_rdv_counter[1] & !U1_cpu_instruction_master_dbs_rdv_counter[0]);

--YE1_do_start_rx is std_1c20:inst|uart1:the_uart1|uart1_rx:the_uart1_rx|do_start_rx

--operation mode is normal

YE1_do_start_rx_lut_out = YE1_delayed_unxsync_rxdxx2 & (!YE1_unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[0] & !YE1_sync_rxd);

YE1_do_start_rx = DFFEAS(YE1_do_start_rx_lut_out, QC2__clk0, F1_data_out, , , , , , );

--YE1_baud_clk_en is std_1c20:inst|uart1:the_uart1|uart1_rx:the_uart1_rx|baud_clk_en

--operation mode is normal

YE1_baud_clk_en_lut_out = YE1L36 & YE1L37 & !YE1_rxd_edge & !YE1_baud_rate_counter[8];

YE1_baud_clk_en = DFFEAS(YE1_baud_clk_en_lut_out, QC2__clk0, F1_data_out, , , , , , );

--YE1L63 is std_1c20:inst|uart1:the_uart1|uart1_rx:the_uart1_rx|unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[3]~7355

--operation mode is normal

YE1L63 = YE1_do_start_rx # YE1_unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[0] & YE1_baud_clk_en;

--YE1_sync_rxd is std_1c20:inst|uart1:the_uart1|uart1_rx:the_uart1_rx|sync_rxd

--operation mode is normal

YE1_sync_rxd_lut_out = YE1_d1_source_rxd;

YE1_sync_rxd = DFFEAS(YE1_sync_rxd_lut_out, QC2__clk0, F1_data_out, , , , , , );

--YE1L1 is std_1c20:inst|uart1:the_uart1|uart1_rx:the_uart1_rx|A_WE_StdLogicVector~26

--operation mode is normal

YE1L1 = YE1_unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[0] & YE1_baud_clk_en;

--M1_master_nativeaddress[0] is std_1c20:inst|clock_1:the_clock_1|master_nativeaddress[0]

--operation mode is normal

M1_master_nativeaddress[0]_lut_out = M1_slave_nativeaddress_d1[0];

M1_master_nativeaddress[0] = DFFEAS(M1_master_nativeaddress[0]_lut_out, PLD_CLOCKINPUT[1], E1_data_out, , , , , , );

--Q1_control_reg_out[2] is std_1c20:inst|connector_pll:the_connector_pll|control_reg_out[2]

--operation mode is normal

Q1_control_reg_out[2]_lut_out = M1_master_writedata[2];

Q1_control_reg_out[2] = DFFEAS(Q1_control_reg_out[2]_lut_out, PLD_CLOCKINPUT[1], E1_data_out, , Q1L1, , , , );

--M1L22 is std_1c20:inst|clock_1:the_clock_1|process0~11

--operation mode is normal

M1L22 = LC1_master_state[1] & R1_d1_reasons_to_wait;

--J1_master_nativeaddress[0] is std_1c20:inst|clock_0:the_clock_0|master_nativeaddress[0]

--operation mode is normal

J1_master_nativeaddress[0]_lut_out = J1_slave_nativeaddress_d1[0];

J1_master_nativeaddress[0] = DFFEAS(J1_master_nativeaddress[0]_lut_out, PLD_CLKFB, D1_data_out, , , , , , );

--LB1_control_reg_out[2] is std_1c20:inst|sdram_pll:the_sdram_pll|control_reg_out[2]

--operation mode is normal

LB1_control_reg_out[2]_lut_out = J1_master_writedata[2];

LB1_control_reg_out[2] = DFFEAS(LB1_control_reg_out[2]_lut_out, PLD_CLKFB, D1_data_out, , LB1L1, , , , );

--J1L22 is std_1c20:inst|clock_0:the_clock_0|process0~11

--operation mode is normal

J1L22 = CC1_master_state[1] & MB1_d1_reasons_to_wait;

--GE1_td_shift[6] is std_1c20:inst|jtag_uart:the_jtag_uart|alt_jtag_atlantic:jtag_uart_alt_jtag_atlantic|td_shift[6]

--operation mode is normal

GE1_td_shift[6] = AMPP_FUNCTION(A1L5, GE1L53, GE1L63, GE1L58, !C1_CLR_SIGNAL, GE1L52);

--GE1L74 is std_1c20:inst|jtag_uart:the_jtag_uart|alt_jtag_atlantic:jtag_uart_alt_jtag_atlantic|wdata[1]~6

--operation mode is normal

GE1L74 = AMPP_FUNCTION(GE1_count[8], GE1L69);

--DE1_slaveselect_wr_strobe is std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|slaveselect_wr_strobe

--operation mode is normal

DE1_slaveselect_wr_strobe = X1L14 & X1L16 & DE1_wr_strobe & !X1L15;

--DE1_shift_reg[1] is std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|shift_reg[1]

--operation mode is normal

DE1_shift_reg[1]_lut_out = DE1_SCLK_reg & DE1_shift_reg[0] # !DE1_SCLK_reg & (DE1L175);

DE1_shift_reg[1] = DFFEAS(DE1_shift_reg[1]_lut_out, QC2__clk0, F1_data_out, , , DE1L175, , , !DE1_slowcount[0]);

--DE1_tx_holding_reg[2] is std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|tx_holding_reg[2]

--operation mode is normal

DE1_tx_holding_reg[2]_lut_out = S1_M_st_data[2];

DE1_tx_holding_reg[2] = DFFEAS(DE1_tx_holding_reg[2]_lut_out, QC2__clk0, F1_data_out, , DE1_write_tx_holding, , , , );

--DE1_SCLK_reg is std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|SCLK_reg

--operation mode is normal

DE1_SCLK_reg_lut_out = DE1_slowcount[0] & (DE1_SCLK_reg & (!DE1L159) # !DE1_SCLK_reg & !DE1L158 & DE1L159) # !DE1_slowcount[0] & DE1_SCLK_reg;

DE1_SCLK_reg = DFFEAS(DE1_SCLK_reg_lut_out, QC2__clk0, F1_data_out, , , , , , );

--DE1L16 is std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|Add1~72

--operation mode is normal

DE1L16_carry_eqn = DE1L24;

DE1L16 = DE1_state[4] $ (!DE1L16_carry_eqn);

--DE1_stateZero is std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|stateZero

--operation mode is normal

DE1_stateZero_lut_out = !DE1L117 # !DE1_state[0] # !DE1_state[4];

DE1_stateZero = DFFEAS(DE1_stateZero_lut_out, QC2__clk0, F1_data_out, , DE1L143, , , , );

--DE1L143 is std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|process11~0

--operation mode is normal

DE1L143 = DE1_transmitting & DE1_slowcount[0];

--DE1L17 is std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|Add1~74

--operation mode is arithmetic

DE1L17 = !DE1_state[0];

--DE1L18 is std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|Add1~75

--operation mode is arithmetic

DE1L18 = CARRY(DE1_state[0]);

--DE1L19 is std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|Add1~76

--operation mode is arithmetic

DE1L19_carry_eqn = DE1L18;

DE1L19 = DE1_state[1] $ (DE1L19_carry_eqn);

--DE1L20 is std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|Add1~77

--operation mode is arithmetic

DE1L20 = CARRY(!DE1L18 # !DE1_state[1]);

--DE1L21 is std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|Add1~78

--operation mode is arithmetic

DE1L21_carry_eqn = DE1L20;

DE1L21 = DE1_state[2] $ (!DE1L21_carry_eqn);

--DE1L22 is std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|Add1~79

--operation mode is arithmetic

DE1L22 = CARRY(DE1_state[2] & (!DE1L20));

--DE1L23 is std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|Add1~80

--operation mode is arithmetic

DE1L23_carry_eqn = DE1L22;

DE1L23 = DE1_state[3] $ (DE1L23_carry_eqn);

--DE1L24 is std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|Add1~81

--operation mode is arithmetic

DE1L24 = CARRY(!DE1L22 # !DE1_state[3]);

--RD1L18 is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|Add0~148

--operation mode is normal

RD1L18 = AMPP_FUNCTION(RD1_MonAReg[10], RD1L17);

--RD1L81 is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|MonAReg~1152

--operation mode is normal

RD1L81 = AMPP_FUNCTION(RD1L18, RD1_MonAReg[10], SD1L192);

--RD1_MonRd is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|MonRd

--operation mode is normal

RD1_MonRd = AMPP_FUNCTION(QC2__clk0, SD1L190, RD1_MonRd, SD1L192, RD1L84, !C1_CLR_SIGNAL);

--SD1_sr[4] is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|sr[4]

--operation mode is normal

SD1_sr[4] = AMPP_FUNCTION(A1L5, SD1L128, SD1_sr[5], SD1L144, SD1L142, !C1_CLR_SIGNAL, SD1L6);

--SD1_sr[5] is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|sr[5]

--operation mode is normal

SD1_sr[5] = AMPP_FUNCTION(A1L5, SD1L127, SD1_sr[6], SD1L144, SD1L142, !C1_CLR_SIGNAL, SD1L6);

--SD1_sr[6] is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|sr[6]

--operation mode is normal

SD1_sr[6] = AMPP_FUNCTION(A1L5, SD1_sr[7], SD1L126, SD1L142, SD1L144, !C1_CLR_SIGNAL, SD1L6);

--SD1_sr[7] is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|sr[7]

--operation mode is normal

SD1_sr[7] = AMPP_FUNCTION(A1L5, SD1_sr[8], altera_internal_jtag, SD1L125, SD1L139, !C1_CLR_SIGNAL, SD1L144, SD1L6);

--SD1_sr[8] is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|sr[8]

--operation mode is normal

SD1_sr[8] = AMPP_FUNCTION(A1L5, SD1L124, SD1_sr[9], SD1L144, SD1L142, !C1_CLR_SIGNAL, SD1L6);

--SD1_sr[9] is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|sr[9]

--operation mode is normal

SD1_sr[9] = AMPP_FUNCTION(A1L5, SD1L39, SD1_sr[10], SD1L144, SD1L142, !C1_CLR_SIGNAL, SD1L6);

--SD1_sr[10] is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|sr[10]

--operation mode is normal

SD1_sr[10] = AMPP_FUNCTION(A1L5, SD1L40, SD1_sr[11], SD1L144, SD1L142, !C1_CLR_SIGNAL, SD1L6);

--SD1_sr[26] is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|sr[26]

--operation mode is normal

SD1_sr[26] = AMPP_FUNCTION(A1L5, SD1L42, SD1_sr[27], SD1L9, SD1L43, !C1_CLR_SIGNAL, SD1L12);

--SD1_sr[27] is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|sr[27]

--operation mode is normal

SD1_sr[27] = AMPP_FUNCTION(A1L5, SD1L45, SD1_sr[28], SD1L9, SD1L46, !C1_CLR_SIGNAL, SD1L12);

--SD1_sr[28] is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|sr[28]

--operation mode is normal

SD1_sr[28] = AMPP_FUNCTION(A1L5, SD1L70, SD1_sr[29], SD1L48, SD1L47, !C1_CLR_SIGNAL, SD1L12);

--SD1_sr[29] is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|sr[29]

--operation mode is normal

SD1_sr[29] = AMPP_FUNCTION(A1L5, SD1L50, SD1_sr[30], SD1L9, SD1L51, !C1_CLR_SIGNAL, SD1L12);

--SD1_sr[30] is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|sr[30]

--operation mode is normal

SD1_sr[30] = AMPP_FUNCTION(A1L5, SD1_sr[31], SD1L70, SD1L52, SD1L53, !C1_CLR_SIGNAL, SD1L12);

--SD1_sr[31] is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|sr[31]

--operation mode is normal

SD1_sr[31] = AMPP_FUNCTION(A1L5, SD1L54, SD1L137, SD1L71, SD1_ir[1], !C1_CLR_SIGNAL, !SD1_ir[0], SD1L12);

--SD1_sr[32] is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|sr[32]

--operation mode is normal

SD1_sr[32] = AMPP_FUNCTION(A1L5, SD1L57, SD1_sr[33], SD1L9, SD1L58, !C1_CLR_SIGNAL, SD1L12);

--SD1_sr[33] is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|sr[33]

--operation mode is normal

SD1_sr[33] = AMPP_FUNCTION(A1L5, SD1_sr[34], SD1L59, SD1L142, SD1L17, !C1_CLR_SIGNAL, SD1L12);

--U1L177 is std_1c20:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|process4~0

--operation mode is normal

U1L177 = U1_cpu_instruction_master_dbs_rdv_counter[1] & Y1_cpu_instruction_master_read_data_valid_ext_flash_s1_shift_register[1] & (!U1_cpu_instruction_master_dbs_rdv_counter[0]);

--Z1L8 is std_1c20:inst|high_res_timer:the_high_res_timer|counter_is_running~93

--operation mode is normal

Z1L8 = Z1_counter_is_running & (!Z1_force_reload);

--Z1L9 is std_1c20:inst|high_res_timer:the_high_res_timer|counter_is_running~94

--operation mode is normal

Z1L9 = Z1L8 & (Z1_control_register[1] # !Z1L53 # !Z1L48);

--Q1_control_reg_out[3] is std_1c20:inst|connector_pll:the_connector_pll|control_reg_out[3]

--operation mode is normal

Q1_control_reg_out[3]_lut_out = M1_master_writedata[3];

Q1_control_reg_out[3] = DFFEAS(Q1_control_reg_out[3]_lut_out, PLD_CLOCKINPUT[1], E1_data_out, , Q1L1, , , , );

--LB1_control_reg_out[3] is std_1c20:inst|sdram_pll:the_sdram_pll|control_reg_out[3]

--operation mode is normal

LB1_control_reg_out[3]_lut_out = J1_master_writedata[3];

LB1_control_reg_out[3] = DFFEAS(LB1_control_reg_out[3]_lut_out, PLD_CLKFB, D1_data_out, , LB1L1, , , , );

--GE1_td_shift[7] is std_1c20:inst|jtag_uart:the_jtag_uart|alt_jtag_atlantic:jtag_uart_alt_jtag_atlantic|td_shift[7]

--operation mode is normal

GE1_td_shift[7] = AMPP_FUNCTION(A1L5, FF1_state[4], GE1L59, BF4_Q[0], GE1L62, !C1_CLR_SIGNAL, GE1L52);

--DE1_tx_holding_reg[3] is std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|tx_holding_reg[3]

--operation mode is normal

DE1_tx_holding_reg[3]_lut_out = S1_M_st_data[3];

DE1_tx_holding_reg[3] = DFFEAS(DE1_tx_holding_reg[3]_lut_out, QC2__clk0, F1_data_out, , DE1_write_tx_holding, , , , );

--CD1_q_b[30] is std_1c20:inst|cpu:the_cpu|cpu_register_bank_a_module:cpu_register_bank_a|altsyncram:the_altsyncram|altsyncram_3vd1:auto_generated|q_b[30]

--RAM Block Operation Mode: Simple Dual-Port

--Port A Depth: 32, Port A Width: 1, Port B Depth: 32, Port B Width: 1

--Port A Logical Depth: 32, Port A Logical Width: 32, Port B Logical Depth: 32, Port B Logical Width: 32

--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered

CD1_q_b[30] = AMPP_FUNCTION(GND, GND, QC2__clk0, QC2__clk0, !S1_M_wr_dst_reg, S1_W_stall, S1L1372, S1_M_dst_regnum[0], S1_M_dst_regnum[1], S1_M_dst_regnum[2], S1_M_dst_regnum[3], S1_M_dst_regnum[4], AD1_q_b[27], AD1_q_b[28], AD1_q_b[29], AD1_q_b[30], AD1_q_b[31]);

--XC1L9 is std_1c20:inst|cpu:the_cpu|cpu_test_bench:the_cpu_test_bench|Add0~567

--operation mode is arithmetic

XC1L9 = AMPP_FUNCTION(S1L597, S1L663, XC1L11);

--FF1_state[13] is sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state[13]

--operation mode is normal

FF1_state[13] = AMPP_FUNCTION(A1L5, FF1_state[12], FF1_state[13], VCC, A1L7);

--Q1_control_reg_out[15] is std_1c20:inst|connector_pll:the_connector_pll|control_reg_out[15]

--operation mode is normal

Q1_control_reg_out[15]_lut_out = M1_master_writedata[15];

Q1_control_reg_out[15] = DFFEAS(Q1_control_reg_out[15]_lut_out, PLD_CLOCKINPUT[1], E1_data_out, , Q1L1, , , , );

--LB1_control_reg_out[15] is std_1c20:inst|sdram_pll:the_sdram_pll|control_reg_out[15]

--operation mode is normal

LB1_control_reg_out[15]_lut_out = J1_master_writedata[15];

LB1_control_reg_out[15] = DFFEAS(LB1_control_reg_out[15]_lut_out, PLD_CLKFB, D1_data_out, , LB1L1, , , , );

--SD1_sr[11] is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|sr[11]

--operation mode is normal

SD1_sr[11] = AMPP_FUNCTION(A1L5, SD1L60, SD1_sr[12], SD1L144, SD1L142, !C1_CLR_SIGNAL, SD1L6);

--SD1_sr[12] is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|sr[12]

--operation mode is normal

SD1_sr[12] = AMPP_FUNCTION(A1L5, SD1L61, SD1_sr[13], SD1L144, SD1L142, !C1_CLR_SIGNAL, SD1L6);

--SD1_sr[13] is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|sr[13]

--operation mode is normal

SD1_sr[13] = AMPP_FUNCTION(A1L5, SD1L62, SD1_sr[14], SD1L144, SD1L142, !C1_CLR_SIGNAL, SD1L6);

--SD1_sr[14] is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|sr[14]

--operation mode is normal

SD1_sr[14] = AMPP_FUNCTION(A1L5, SD1_sr[15], SD1L63, SD1L142, SD1L144, !C1_CLR_SIGNAL, SD1L6);

--SD1_sr[15] is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|sr[15]

--operation mode is normal

SD1_sr[15] = AMPP_FUNCTION(A1L5, SD1_sr[16], altera_internal_jtag, SD1L123, SD1L138, !C1_CLR_SIGNAL, SD1L144, SD1L6);

--SD1_sr[16] is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|sr[16]

--operation mode is normal

SD1_sr[16] = AMPP_FUNCTION(A1L5, SD1L65, SD1_sr[17], SD1L9, SD1L66, !C1_CLR_SIGNAL, SD1L12);

--SD1_sr[17] is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|sr[17]

--operation mode is normal

SD1_sr[17] = AMPP_FUNCTION(A1L5, SD1L68, SD1_sr[18], SD1L9, SD1L69, !C1_CLR_SIGNAL, SD1L12);

--Q1_control_reg_out[7] is std_1c20:inst|connector_pll:the_connector_pll|control_reg_out[7]

--operation mode is normal

Q1_control_reg_out[7]_lut_out = M1_master_writedata[7];

Q1_control_reg_out[7] = DFFEAS(Q1_control_reg_out[7]_lut_out, PLD_CLOCKINPUT[1], E1_data_out, , Q1L1, , , , );

--LB1_control_reg_out[7] is std_1c20:inst|sdram_pll:the_sdram_pll|control_reg_out[7]

--operation mode is normal

LB1_control_reg_out[7]_lut_out = J1_master_writedata[7];

LB1_control_reg_out[7] = DFFEAS(LB1_control_reg_out[7]_lut_out, PLD_CLKFB, D1_data_out, , LB1L1, , , , );

--DE1_tx_holding_reg[7] is std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|tx_holding_reg[7]

--operation mode is normal

DE1_tx_holding_reg[7]_lut_out = S1_M_st_data[7];

DE1_tx_holding_reg[7] = DFFEAS(DE1_tx_holding_reg[7]_lut_out, QC2__clk0, F1_data_out, , DE1_write_tx_holding, , , , );

--NE1L6 is std_1c20:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_w:the_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_jf21:auto_generated|a_dpfifo_ml21:dpfifo|a_fefifo_7cf:fifo_state|b_non_empty~141

--operation mode is normal

NE1L6 = RE1_safe_q[2] # RE1_safe_q[1] # RE1_safe_q[5] # RE1_safe_q[4];

--NE1L7 is std_1c20:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_w:the_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_jf21:auto_generated|a_dpfifo_ml21:dpfifo|a_fefifo_7cf:fifo_state|b_non_empty~142

--operation mode is normal

NE1L7 = RE1_safe_q[3] # NE1L6 # !BB1_rd_wfifo # !RE1_safe_q[0];

--Q1_control_reg_out[14] is std_1c20:inst|connector_pll:the_connector_pll|control_reg_out[14]

--operation mode is normal

Q1_control_reg_out[14]_lut_out = M1_master_writedata[14];

Q1_control_reg_out[14] = DFFEAS(Q1_control_reg_out[14]_lut_out, PLD_CLOCKINPUT[1], E1_data_out, , Q1L1, , , , );

--LB1_control_reg_out[14] is std_1c20:inst|sdram_pll:the_sdram_pll|control_reg_out[14]

--operation mode is normal

LB1_control_reg_out[14]_lut_out = J1_master_writedata[14];

LB1_control_reg_out[14] = DFFEAS(LB1_control_reg_out[14]_lut_out, PLD_CLKFB, D1_data_out, , LB1L1, , , , );

--Q1_control_reg_out[13] is std_1c20:inst|connector_pll:the_connector_pll|control_reg_out[13]

--operation mode is normal

Q1_control_reg_out[13]_lut_out = M1_master_writedata[13];

Q1_control_reg_out[13] = DFFEAS(Q1_control_reg_out[13]_lut_out, PLD_CLOCKINPUT[1], E1_data_out, , Q1L1, , , , );

--LB1_control_reg_out[13] is std_1c20:inst|sdram_pll:the_sdram_pll|control_reg_out[13]

--operation mode is normal

LB1_control_reg_out[13]_lut_out = J1_master_writedata[13];

LB1_control_reg_out[13] = DFFEAS(LB1_control_reg_out[13]_lut_out, PLD_CLKFB, D1_data_out, , LB1L1, , , , );

--Q1_control_reg_out[12] is std_1c20:inst|connector_pll:the_connector_pll|control_reg_out[12]

--operation mode is normal

Q1_control_reg_out[12]_lut_out = M1_master_writedata[12];

Q1_control_reg_out[12] = DFFEAS(Q1_control_reg_out[12]_lut_out, PLD_CLOCKINPUT[1], E1_data_out, , Q1L1, , , , );

--LB1_control_reg_out[12] is std_1c20:inst|sdram_pll:the_sdram_pll|control_reg_out[12]

--operation mode is normal

LB1_control_reg_out[12]_lut_out = J1_master_writedata[12];

LB1_control_reg_out[12] = DFFEAS(LB1_control_reg_out[12]_lut_out, PLD_CLKFB, D1_data_out, , LB1L1, , , , );

--CD1_q_b[28] is std_1c20:inst|cpu:the_cpu|cpu_register_bank_a_module:cpu_register_bank_a|altsyncram:the_altsyncram|altsyncram_3vd1:auto_generated|q_b[28]

--RAM Block Operation Mode: Simple Dual-Port

--Port A Depth: 32, Port A Width: 1, Port B Depth: 32, Port B Width: 1

--Port A Logical Depth: 32, Port A Logical Width: 32, Port B Logical Depth: 32, Port B Logical Width: 32

--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered

CD1_q_b[28] = AMPP_FUNCTION(GND, GND, QC2__clk0, QC2__clk0, !S1_M_wr_dst_reg, S1_W_stall, S1L1366, S1_M_dst_regnum[0], S1_M_dst_regnum[1], S1_M_dst_regnum[2], S1_M_dst_regnum[3], S1_M_dst_regnum[4], AD1_q_b[27], AD1_q_b[28], AD1_q_b[29], AD1_q_b[30], AD1_q_b[31]);

--LB1_control_reg_out[11] is std_1c20:inst|sdram_pll:the_sdram_pll|control_reg_out[11]

--operation mode is normal

LB1_control_reg_out[11]_lut_out = J1_master_writedata[11];

LB1_control_reg_out[11] = DFFEAS(LB1_control_reg_out[11]_lut_out, PLD_CLKFB, D1_data_out, , LB1L1, , , , );

--Q1_control_reg_out[11] is std_1c20:inst|connector_pll:the_connector_pll|control_reg_out[11]

--operation mode is normal

Q1_control_reg_out[11]_lut_out = M1_master_writedata[11];

Q1_control_reg_out[11] = DFFEAS(Q1_control_reg_out[11]_lut_out, PLD_CLOCKINPUT[1], E1_data_out, , Q1L1, , , , );

--Q1_control_reg_out[10] is std_1c20:inst|connector_pll:the_connector_pll|control_reg_out[10]

--operation mode is normal

Q1_control_reg_out[10]_lut_out = M1_master_writedata[10];

Q1_control_reg_out[10] = DFFEAS(Q1_control_reg_out[10]_lut_out, PLD_CLOCKINPUT[1], E1_data_out, , Q1L1, , , , );

--LB1_control_reg_out[10] is std_1c20:inst|sdram_pll:the_sdram_pll|control_reg_out[10]

--operation mode is normal

LB1_control_reg_out[10]_lut_out = J1_master_writedata[10];

LB1_control_reg_out[10] = DFFEAS(LB1_control_reg_out[10]_lut_out, PLD_CLKFB, D1_data_out, , LB1L1, , , , );

--DE1_shift_reg[0] is std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|shift_reg[0]

--operation mode is normal

DE1_shift_reg[0]_lut_out = DE1_SCLK_reg & DE1_MISO_reg # !DE1_SCLK_reg & (DE1L176);

DE1_shift_reg[0] = DFFEAS(DE1_shift_reg[0]_lut_out, QC2__clk0, F1_data_out, , , DE1L176, , , !DE1_slowcount[0]);

--Q1_control_reg_out[9] is std_1c20:inst|connector_pll:the_connector_pll|control_reg_out[9]

--operation mode is normal

Q1_control_reg_out[9]_lut_out = M1_master_writedata[9];

Q1_control_reg_out[9] = DFFEAS(Q1_control_reg_out[9]_lut_out, PLD_CLOCKINPUT[1], E1_data_out, , Q1L1, , , , );

--LB1_control_reg_out[9] is std_1c20:inst|sdram_pll:the_sdram_pll|control_reg_out[9]

--operation mode is normal

LB1_control_reg_out[9]_lut_out = J1_master_writedata[9];

LB1_control_reg_out[9] = DFFEAS(LB1_control_reg_out[9]_lut_out, PLD_CLKFB, D1_data_out, , LB1L1, , , , );

--Q1_control_reg_out[8] is std_1c20:inst|connector_pll:the_connector_pll|control_reg_out[8]

--operation mode is normal

Q1_control_reg_out[8]_lut_out = M1_master_writedata[8];

Q1_control_reg_out[8] = DFFEAS(Q1_control_reg_out[8]_lut_out, PLD_CLOCKINPUT[1], E1_data_out, , Q1L1, , , , );

--LB1_control_reg_out[8] is std_1c20:inst|sdram_pll:the_sdram_pll|control_reg_out[8]

--operation mode is normal

LB1_control_reg_out[8]_lut_out = J1_master_writedata[8];

LB1_control_reg_out[8] = DFFEAS(LB1_control_reg_out[8]_lut_out, PLD_CLKFB, D1_data_out, , LB1L1, , , , );

--Q1_control_reg_out[6] is std_1c20:inst|connector_pll:the_connector_pll|control_reg_out[6]

--operation mode is normal

Q1_control_reg_out[6]_lut_out = M1_master_writedata[6];

Q1_control_reg_out[6] = DFFEAS(Q1_control_reg_out[6]_lut_out, PLD_CLOCKINPUT[1], E1_data_out, , Q1L1, , , , );

--LB1_control_reg_out[6] is std_1c20:inst|sdram_pll:the_sdram_pll|control_reg_out[6]

--operation mode is normal

LB1_control_reg_out[6]_lut_out = J1_master_writedata[6];

LB1_control_reg_out[6] = DFFEAS(LB1_control_reg_out[6]_lut_out, PLD_CLKFB, D1_data_out, , LB1L1, , , , );

--DE1_tx_holding_reg[6] is std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|tx_holding_reg[6]

--operation mode is normal

DE1_tx_holding_reg[6]_lut_out = S1_M_st_data[6];

DE1_tx_holding_reg[6] = DFFEAS(DE1_tx_holding_reg[6]_lut_out, QC2__clk0, F1_data_out, , DE1_write_tx_holding, , , , );

--Q1_control_reg_out[4] is std_1c20:inst|connector_pll:the_connector_pll|control_reg_out[4]

--operation mode is normal

Q1_control_reg_out[4]_lut_out = M1_master_writedata[4];

Q1_control_reg_out[4] = DFFEAS(Q1_control_reg_out[4]_lut_out, PLD_CLOCKINPUT[1], E1_data_out, , Q1L1, , , , );

--LB1_control_reg_out[4] is std_1c20:inst|sdram_pll:the_sdram_pll|control_reg_out[4]

--operation mode is normal

LB1_control_reg_out[4]_lut_out = J1_master_writedata[4];

LB1_control_reg_out[4] = DFFEAS(LB1_control_reg_out[4]_lut_out, PLD_CLKFB, D1_data_out, , LB1L1, , , , );

--GE1_td_shift[8] is std_1c20:inst|jtag_uart:the_jtag_uart|alt_jtag_atlantic:jtag_uart_alt_jtag_atlantic|td_shift[8]

--operation mode is normal

GE1_td_shift[8] = AMPP_FUNCTION(A1L5, GE1_td_shift[9], GE1_rdata[6], GE1_count[9], !C1_CLR_SIGNAL, !FF1_state[4], GE1L52);

--DE1_tx_holding_reg[4] is std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|tx_holding_reg[4]

--operation mode is normal

DE1_tx_holding_reg[4]_lut_out = S1_M_st_data[4];

DE1_tx_holding_reg[4] = DFFEAS(DE1_tx_holding_reg[4]_lut_out, QC2__clk0, F1_data_out, , DE1_write_tx_holding, , , , );

--Q1_control_reg_out[5] is std_1c20:inst|connector_pll:the_connector_pll|control_reg_out[5]

--operation mode is normal

Q1_control_reg_out[5]_lut_out = M1_master_writedata[5];

Q1_control_reg_out[5] = DFFEAS(Q1_control_reg_out[5]_lut_out, PLD_CLOCKINPUT[1], E1_data_out, , Q1L1, , , , );

--LB1_control_reg_out[5] is std_1c20:inst|sdram_pll:the_sdram_pll|control_reg_out[5]

--operation mode is normal

LB1_control_reg_out[5]_lut_out = J1_master_writedata[5];

LB1_control_reg_out[5] = DFFEAS(LB1_control_reg_out[5]_lut_out, PLD_CLKFB, D1_data_out, , LB1L1, , , , );

--DE1_tx_holding_reg[5] is std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|tx_holding_reg[5]

--operation mode is normal

DE1_tx_holding_reg[5]_lut_out = S1_M_st_data[5];

DE1_tx_holding_reg[5] = DFFEAS(DE1_tx_holding_reg[5]_lut_out, QC2__clk0, F1_data_out, , DE1_write_tx_holding, , , , );

--M1_slave_readdata_p1[0] is std_1c20:inst|clock_1:the_clock_1|slave_readdata_p1[0]

--operation mode is normal

M1_slave_readdata_p1[0]_lut_out = M1_master_nativeaddress[0] & Q1_control_reg_out[0];

M1_slave_readdata_p1[0] = DFFEAS(M1_slave_readdata_p1[0]_lut_out, PLD_CLOCKINPUT[1], E1_data_out, , M1L22, , , , );

--J1_slave_readdata_p1[0] is std_1c20:inst|clock_0:the_clock_0|slave_readdata_p1[0]

--operation mode is normal

J1_slave_readdata_p1[0]_lut_out = J1_master_nativeaddress[0] & LB1_control_reg_out[0];

J1_slave_readdata_p1[0] = DFFEAS(J1_slave_readdata_p1[0]_lut_out, PLD_CLKFB, D1_data_out, , J1L22, , , , );

--GE1_wdata[0] is std_1c20:inst|jtag_uart:the_jtag_uart|alt_jtag_atlantic:jtag_uart_alt_jtag_atlantic|wdata[0]

--operation mode is normal

GE1_wdata[0] = AMPP_FUNCTION(A1L5, altera_internal_jtag, !C1_CLR_SIGNAL, GE1L72);

--DE1_epcs_slave_select_holding_reg[0] is std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|epcs_slave_select_holding_reg[0]

--operation mode is normal

DE1_epcs_slave_select_holding_reg[0]_lut_out = !S1_M_st_data[0];

DE1_epcs_slave_select_holding_reg[0] = DFFEAS(DE1_epcs_slave_select_holding_reg[0]_lut_out, QC2__clk0, F1_data_out, , DE1_slaveselect_wr_strobe, , , , );

--RB1L9 is std_1c20:inst|sys_clk_timer:the_sys_clk_timer|counter_is_running~93

--operation mode is normal

RB1L9 = RB1_counter_is_running & (!RB1_force_reload);

--RB1L10 is std_1c20:inst|sys_clk_timer:the_sys_clk_timer|counter_is_running~94

--operation mode is normal

RB1L10 = RB1L9 & (RB1_control_register[1] # !RB1L54 # !RB1L49);

--M1_slave_readdata_p1[1] is std_1c20:inst|clock_1:the_clock_1|slave_readdata_p1[1]

--operation mode is normal

M1_slave_readdata_p1[1]_lut_out = !Q1_control_reg_out[1] & (M1_master_nativeaddress[0]);

M1_slave_readdata_p1[1] = DFFEAS(M1_slave_readdata_p1[1]_lut_out, PLD_CLOCKINPUT[1], E1_data_out, , M1L22, , , , );

--J1_slave_readdata_p1[1] is std_1c20:inst|clock_0:the_clock_0|slave_readdata_p1[1]

--operation mode is normal

J1_slave_readdata_p1[1]_lut_out = !LB1_control_reg_out[1] & (J1_master_nativeaddress[0]);

J1_slave_readdata_p1[1] = DFFEAS(J1_slave_readdata_p1[1]_lut_out, PLD_CLKFB, D1_data_out, , J1L22, , , , );

--GE1_wdata[1] is std_1c20:inst|jtag_uart:the_jtag_uart|alt_jtag_atlantic:jtag_uart_alt_jtag_atlantic|wdata[1]

--operation mode is normal

GE1_wdata[1] = AMPP_FUNCTION(A1L5, GE1_td_shift[5], !C1_CLR_SIGNAL, GE1L74);

--DE1_epcs_slave_select_holding_reg[1] is std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|epcs_slave_select_holding_reg[1]

--operation mode is normal

DE1_epcs_slave_select_holding_reg[1]_lut_out = S1_M_st_data[1];

DE1_epcs_slave_select_holding_reg[1] = DFFEAS(DE1_epcs_slave_select_holding_reg[1]_lut_out, QC2__clk0, F1_data_out, , DE1_slaveselect_wr_strobe, , , , );

--CF1L14 is sld_hub:sld_hub_inst|sld_rom_sr:HUB_INFO_REG|Mux1~69

--operation mode is normal

CF1L14 = AMPP_FUNCTION(CF1_word_counter[1], CF1_word_counter[0], CF1_word_counter[3]);

--SD1_internal_jdo1[1] is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|internal_jdo1[1]

--operation mode is normal

SD1_internal_jdo1[1] = AMPP_FUNCTION(A1L8, SD1_sr[1], VCC, SD1L145);

--GD1_break_readreg[2] is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_break:the_cpu_nios2_oci_break|break_readreg[2]

--operation mode is normal

GD1_break_readreg[2] = AMPP_FUNCTION(QC2__clk0, SD1_internal_jdo1[2], SD1_internal_jdo1[36], SD1_internal_jdo1[37], SD1L189, !C1_CLR_SIGNAL, SD1L189);

--SD1L129 is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|Mux37~14

--operation mode is normal

SD1L129 = AMPP_FUNCTION(RD1_internal_MonDReg[2], SD1_ir[1], GD1_break_readreg[2], SD1_ir[0]);

--GD1_break_readreg[24] is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_break:the_cpu_nios2_oci_break|break_readreg[24]

--operation mode is normal

GD1_break_readreg[24] = AMPP_FUNCTION(QC2__clk0, SD1_internal_jdo1[24], SD1_internal_jdo1[36], SD1_internal_jdo1[37], SD1L189, !C1_CLR_SIGNAL, SD1L189);

--SD1L34 is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|DRsize[0]~20011

--operation mode is normal

SD1L34 = AMPP_FUNCTION(GD1_break_readreg[24], RD1_internal_MonDReg[24], SD1_ir[1]);

--SD1L35 is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|DRsize[0]~20012

--operation mode is normal

SD1L35 = AMPP_FUNCTION(SD1L144, SD1_ir[1], SD1L34, SD1_ir[0]);

--GE1_read_write is std_1c20:inst|jtag_uart:the_jtag_uart|alt_jtag_atlantic:jtag_uart_alt_jtag_atlantic|read_write

--operation mode is normal

GE1_read_write = AMPP_FUNCTION(A1L5, GE1_read_write, !C1_CLR_SIGNAL, GE1L74);

--SE1_q_b[0] is std_1c20:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_w:the_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_jf21:auto_generated|a_dpfifo_ml21:dpfifo|dpram_j921:FIFOram|altsyncram_nll1:altsyncram1|q_b[0]

--RAM Block Operation Mode: Simple Dual-Port

--Port A Depth: 64, Port A Width: 1, Port B Depth: 64, Port B Width: 1

--Port A Logical Depth: 64, Port A Logical Width: 8, Port B Logical Depth: 64, Port B Logical Width: 8

--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered

SE1_q_b[0]_PORT_A_data_in = S1_M_st_data[0];

SE1_q_b[0]_PORT_A_data_in_reg = DFFE(SE1_q_b[0]_PORT_A_data_in, SE1_q_b[0]_clock_0, , , SE1_q_b[0]_clock_enable_0);

SE1_q_b[0]_PORT_A_address = BUS(QE2_safe_q[0], QE2_safe_q[1], QE2_safe_q[2], QE2_safe_q[3], QE2_safe_q[4], QE2_safe_q[5]);

SE1_q_b[0]_PORT_A_address_reg = DFFE(SE1_q_b[0]_PORT_A_address, SE1_q_b[0]_clock_0, , , SE1_q_b[0]_clock_enable_0);

SE1_q_b[0]_PORT_B_address = BUS(QE1_safe_q[0], QE1_safe_q[1], QE1_safe_q[2], QE1_safe_q[3], QE1_safe_q[4], QE1_safe_q[5]);

SE1_q_b[0]_PORT_B_address_reg = DFFE(SE1_q_b[0]_PORT_B_address, SE1_q_b[0]_clock_1, , , SE1_q_b[0]_clock_enable_1);

SE1_q_b[0]_PORT_A_write_enable = VCC;

SE1_q_b[0]_PORT_A_write_enable_reg = DFFE(SE1_q_b[0]_PORT_A_write_enable, SE1_q_b[0]_clock_0, , , SE1_q_b[0]_clock_enable_0);

SE1_q_b[0]_PORT_B_read_enable = VCC;

SE1_q_b[0]_PORT_B_read_enable_reg = DFFE(SE1_q_b[0]_PORT_B_read_enable, SE1_q_b[0]_clock_1, , , SE1_q_b[0]_clock_enable_1);

SE1_q_b[0]_clock_0 = QC2__clk0;

SE1_q_b[0]_clock_1 = QC2__clk0;

SE1_q_b[0]_clock_enable_0 = BB1_fifo_wr;

SE1_q_b[0]_clock_enable_1 = BB1_rd_wfifo;

SE1_q_b[0]_PORT_B_data_out = MEMORY(SE1_q_b[0]_PORT_A_data_in_reg, , SE1_q_b[0]_PORT_A_address_reg, SE1_q_b[0]_PORT_B_address_reg, SE1_q_b[0]_PORT_A_write_enable_reg, SE1_q_b[0]_PORT_B_read_enable_reg, , , SE1_q_b[0]_clock_0, SE1_q_b[0]_clock_1, SE1_q_b[0]_clock_enable_0, SE1_q_b[0]_clock_enable_1, , );

SE1_q_b[0] = SE1_q_b[0]_PORT_B_data_out[0];

--GE1_rdata[1] is std_1c20:inst|jtag_uart:the_jtag_uart|alt_jtag_atlantic:jtag_uart_alt_jtag_atlantic|rdata[1]

--operation mode is normal

GE1_rdata[1] = AMPP_FUNCTION(QC2__clk0, SE1_q_b[1], F1_data_out, GE1L18);

--GE1_td_shift[4] is std_1c20:inst|jtag_uart:the_jtag_uart|alt_jtag_atlantic:jtag_uart_alt_jtag_atlantic|td_shift[4]

--operation mode is normal

GE1_td_shift[4] = AMPP_FUNCTION(A1L5, FF1_state[4], GE1L60, BF4_Q[0], GE1L62, !C1_CLR_SIGNAL, GE1L52);

--GE1L57 is std_1c20:inst|jtag_uart:the_jtag_uart|alt_jtag_atlantic:jtag_uart_alt_jtag_atlantic|td_shift[9]~3561

--operation mode is normal

GE1L57 = AMPP_FUNCTION(GE1_rdata[1], GE1_td_shift[4], GE1_count[9]);

--GE1_count[6] is std_1c20:inst|jtag_uart:the_jtag_uart|alt_jtag_atlantic:jtag_uart_alt_jtag_atlantic|count[6]

--operation mode is normal

GE1_count[6] = AMPP_FUNCTION(A1L5, FF1_state[4], GE1_count[5], !C1_CLR_SIGNAL, GE1L52);

--QE2_safe_q[0] is std_1c20:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_w:the_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_jf21:auto_generated|a_dpfifo_ml21:dpfifo|cntr_rd8:wr_ptr|safe_q[0]

--operation mode is arithmetic

QE2_safe_q[0]_lut_out = QE2_safe_q[0] $ BB1_fifo_wr;

QE2_safe_q[0] = DFFEAS(QE2_safe_q[0]_lut_out, QC2__clk0, F1_data_out, , , , , , );

--QE2L2 is std_1c20:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_w:the_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_jf21:auto_generated|a_dpfifo_ml21:dpfifo|cntr_rd8:wr_ptr|counter_cella0~COUT

--operation mode is arithmetic

QE2L2 = CARRY(QE2_safe_q[0]);

--QE2_safe_q[1] is std_1c20:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_w:the_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_jf21:auto_generated|a_dpfifo_ml21:dpfifo|cntr_rd8:wr_ptr|safe_q[1]

--operation mode is arithmetic

QE2_safe_q[1]_carry_eqn = QE2L2;

QE2_safe_q[1]_lut_out = QE2_safe_q[1] $ (BB1_fifo_wr & QE2_safe_q[1]_carry_eqn);

QE2_safe_q[1] = DFFEAS(QE2_safe_q[1]_lut_out, QC2__clk0, F1_data_out, , , , , , );

--QE2L4 is std_1c20:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_w:the_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_jf21:auto_generated|a_dpfifo_ml21:dpfifo|cntr_rd8:wr_ptr|counter_cella1~COUT

--operation mode is arithmetic

QE2L4 = CARRY(!QE2L2 # !QE2_safe_q[1]);

--QE2_safe_q[2] is std_1c20:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_w:the_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_jf21:auto_generated|a_dpfifo_ml21:dpfifo|cntr_rd8:wr_ptr|safe_q[2]

--operation mode is arithmetic

QE2_safe_q[2]_carry_eqn = QE2L4;

QE2_safe_q[2]_lut_out = QE2_safe_q[2] $ (BB1_fifo_wr & !QE2_safe_q[2]_carry_eqn);

QE2_safe_q[2] = DFFEAS(QE2_safe_q[2]_lut_out, QC2__clk0, F1_data_out, , , , , , );

--QE2L6 is std_1c20:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_w:the_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_jf21:auto_generated|a_dpfifo_ml21:dpfifo|cntr_rd8:wr_ptr|counter_cella2~COUT

--operation mode is arithmetic

QE2L6 = CARRY(QE2_safe_q[2] & (!QE2L4));

--QE2_safe_q[3] is std_1c20:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_w:the_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_jf21:auto_generated|a_dpfifo_ml21:dpfifo|cntr_rd8:wr_ptr|safe_q[3]

--operation mode is arithmetic

QE2_safe_q[3]_carry_eqn = QE2L6;

QE2_safe_q[3]_lut_out = QE2_safe_q[3] $ (BB1_fifo_wr & QE2_safe_q[3]_carry_eqn);

QE2_safe_q[3] = DFFEAS(QE2_safe_q[3]_lut_out, QC2__clk0, F1_data_out, , , , , , );

--QE2L8 is std_1c20:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_w:the_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_jf21:auto_generated|a_dpfifo_ml21:dpfifo|cntr_rd8:wr_ptr|counter_cella3~COUT

--operation mode is arithmetic

QE2L8 = CARRY(!QE2L6 # !QE2_safe_q[3]);

--QE2_safe_q[4] is std_1c20:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_w:the_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_jf21:auto_generated|a_dpfifo_ml21:dpfifo|cntr_rd8:wr_ptr|safe_q[4]

--operation mode is arithmetic

QE2_safe_q[4]_carry_eqn = QE2L8;

QE2_safe_q[4]_lut_out = QE2_safe_q[4] $ (BB1_fifo_wr & !QE2_safe_q[4]_carry_eqn);

QE2_safe_q[4] = DFFEAS(QE2_safe_q[4]_lut_out, QC2__clk0, F1_data_out, , , , , , );

--QE2L10 is std_1c20:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_w:the_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_jf21:auto_generated|a_dpfifo_ml21:dpfifo|cntr_rd8:wr_ptr|counter_cella4~COUT

--operation mode is arithmetic

QE2L10 = CARRY(QE2_safe_q[4] & (!QE2L8));

--QE2_safe_q[5] is std_1c20:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_w:the_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_jf21:auto_generated|a_dpfifo_ml21:dpfifo|cntr_rd8:wr_ptr|safe_q[5]

--operation mode is normal

QE2_safe_q[5]_carry_eqn = QE2L10;

QE2_safe_q[5]_lut_out = QE2_safe_q[5] $ (BB1_fifo_wr & QE2_safe_q[5]_carry_eqn);

QE2_safe_q[5] = DFFEAS(QE2_safe_q[5]_lut_out, QC2__clk0, F1_data_out, , , , , , );

--QE1_safe_q[0] is std_1c20:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_w:the_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_jf21:auto_generated|a_dpfifo_ml21:dpfifo|cntr_rd8:rd_ptr_count|safe_q[0]

--operation mode is arithmetic

QE1_safe_q[0]_lut_out = QE1_safe_q[0] $ BB1_rd_wfifo;

QE1_safe_q[0] = DFFEAS(QE1_safe_q[0]_lut_out, QC2__clk0, F1_data_out, , , , , , );

--QE1L2 is std_1c20:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_w:the_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_jf21:auto_generated|a_dpfifo_ml21:dpfifo|cntr_rd8:rd_ptr_count|counter_cella0~COUT

--operation mode is arithmetic

QE1L2 = CARRY(QE1_safe_q[0]);

--QE1_safe_q[1] is std_1c20:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_w:the_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_jf21:auto_generated|a_dpfifo_ml21:dpfifo|cntr_rd8:rd_ptr_count|safe_q[1]

--operation mode is arithmetic

QE1_safe_q[1]_carry_eqn = QE1L2;

QE1_safe_q[1]_lut_out = QE1_safe_q[1] $ (BB1_rd_wfifo & QE1_safe_q[1]_carry_eqn);

QE1_safe_q[1] = DFFEAS(QE1_safe_q[1]_lut_out, QC2__clk0, F1_data_out, , , , , , );

--QE1L4 is std_1c20:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_w:the_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_jf21:auto_generated|a_dpfifo_ml21:dpfifo|cntr_rd8:rd_ptr_count|counter_cella1~COUT

--operation mode is arithmetic

QE1L4 = CARRY(!QE1L2 # !QE1_safe_q[1]);

--QE1_safe_q[2] is std_1c20:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_w:the_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_jf21:auto_generated|a_dpfifo_ml21:dpfifo|cntr_rd8:rd_ptr_count|safe_q[2]

--operation mode is arithmetic

QE1_safe_q[2]_carry_eqn = QE1L4;

QE1_safe_q[2]_lut_out = QE1_safe_q[2] $ (BB1_rd_wfifo & !QE1_safe_q[2]_carry_eqn);

QE1_safe_q[2] = DFFEAS(QE1_safe_q[2]_lut_out, QC2__clk0, F1_data_out, , , , , , );

--QE1L6 is std_1c20:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_w:the_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_jf21:auto_generated|a_dpfifo_ml21:dpfifo|cntr_rd8:rd_ptr_count|counter_cella2~COUT

--operation mode is arithmetic

QE1L6 = CARRY(QE1_safe_q[2] & (!QE1L4));

--QE1_safe_q[3] is std_1c20:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_w:the_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_jf21:auto_generated|a_dpfifo_ml21:dpfifo|cntr_rd8:rd_ptr_count|safe_q[3]

--operation mode is arithmetic

QE1_safe_q[3]_carry_eqn = QE1L6;

QE1_safe_q[3]_lut_out = QE1_safe_q[3] $ (BB1_rd_wfifo & QE1_safe_q[3]_carry_eqn);

QE1_safe_q[3] = DFFEAS(QE1_safe_q[3]_lut_out, QC2__clk0, F1_data_out, , , , , , );

--QE1L8 is std_1c20:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_w:the_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_jf21:auto_generated|a_dpfifo_ml21:dpfifo|cntr_rd8:rd_ptr_count|counter_cella3~COUT

--operation mode is arithmetic

QE1L8 = CARRY(!QE1L6 # !QE1_safe_q[3]);

--QE1_safe_q[4] is std_1c20:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_w:the_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_jf21:auto_generated|a_dpfifo_ml21:dpfifo|cntr_rd8:rd_ptr_count|safe_q[4]

--operation mode is arithmetic

QE1_safe_q[4]_carry_eqn = QE1L8;

QE1_safe_q[4]_lut_out = QE1_safe_q[4] $ (BB1_rd_wfifo & !QE1_safe_q[4]_carry_eqn);

QE1_safe_q[4] = DFFEAS(QE1_safe_q[4]_lut_out, QC2__clk0, F1_data_out, , , , , , );

--QE1L10 is std_1c20:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_w:the_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_jf21:auto_generated|a_dpfifo_ml21:dpfifo|cntr_rd8:rd_ptr_count|counter_cella4~COUT

--operation mode is arithmetic

QE1L10 = CARRY(QE1_safe_q[4] & (!QE1L8));

--QE1_safe_q[5] is std_1c20:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_w:the_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_jf21:auto_generated|a_dpfifo_ml21:dpfifo|cntr_rd8:rd_ptr_count|safe_q[5]

--operation mode is normal

QE1_safe_q[5]_carry_eqn = QE1L10;

QE1_safe_q[5]_lut_out = QE1_safe_q[5] $ (BB1_rd_wfifo & QE1_safe_q[5]_carry_eqn);

QE1_safe_q[5] = DFFEAS(QE1_safe_q[5]_lut_out, QC2__clk0, F1_data_out, , , , , , );

--CD1_q_b[29] is std_1c20:inst|cpu:the_cpu|cpu_register_bank_a_module:cpu_register_bank_a|altsyncram:the_altsyncram|altsyncram_3vd1:auto_generated|q_b[29]

--RAM Block Operation Mode: Simple Dual-Port

--Port A Depth: 32, Port A Width: 1, Port B Depth: 32, Port B Width: 1

--Port A Logical Depth: 32, Port A Logical Width: 32, Port B Logical Depth: 32, Port B Logical Width: 32

--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered

CD1_q_b[29] = AMPP_FUNCTION(GND, GND, QC2__clk0, QC2__clk0, !S1_M_wr_dst_reg, S1_W_stall, S1L1369, S1_M_dst_regnum[0], S1_M_dst_regnum[1], S1_M_dst_regnum[2], S1_M_dst_regnum[3], S1_M_dst_regnum[4], AD1_q_b[27], AD1_q_b[28], AD1_q_b[29], AD1_q_b[30], AD1_q_b[31]);

--WE1_stage_5 is std_1c20:inst|sdram_s1_arbitrator:the_sdram_s1|rdv_fifo_for_cpu_instruction_master_to_sdram_s1_module:rdv_fifo_for_cpu_instruction_master_to_sdram_s1|stage_5

--operation mode is normal

WE1_stage_5_lut_out = WE1_full_6 & WE1_stage_6 # !WE1_full_6 & (NB1L18);

WE1_stage_5 = DFFEAS(WE1_stage_5_lut_out, QC2__clk0, VCC, , WE1L21, , , , );

--WE1_full_5 is std_1c20:inst|sdram_s1_arbitrator:the_sdram_s1|rdv_fifo_for_cpu_instruction_master_to_sdram_s1_module:rdv_fifo_for_cpu_instruction_master_to_sdram_s1|full_5

--operation mode is normal

WE1_full_5_lut_out = KB1_za_valid & (NB1L27 & WE1_full_4 # !NB1L27 & (WE1_full_6)) # !KB1_za_valid & WE1_full_4;

WE1_full_5 = DFFEAS(WE1_full_5_lut_out, QC2__clk0, F1_data_out, , VE1L13, , , , );

--WE1L22 is std_1c20:inst|sdram_s1_arbitrator:the_sdram_s1|rdv_fifo_for_cpu_instruction_master_to_sdram_s1_module:rdv_fifo_for_cpu_instruction_master_to_sdram_s1|process4~1

--operation mode is normal

WE1L22 = KB1_za_valid # NB1L27 & (!WE1_full_4);

--HC1_data_in_d1 is std_1c20:inst|clock_1:the_clock_1|clock_1_slave_read_request_sync_module:clock_1_slave_read_request_sync|data_in_d1

--operation mode is normal

HC1_data_in_d1_lut_out = NC1_internal_slave_read_request;

HC1_data_in_d1 = DFFEAS(HC1_data_in_d1_lut_out, PLD_CLOCKINPUT[1], E1_data_out, , , , , , );

--JC1_data_in_d1 is std_1c20:inst|clock_1:the_clock_1|clock_1_slave_write_request_sync_module:clock_1_slave_write_request_sync|data_in_d1

--operation mode is normal

JC1_data_in_d1_lut_out = NC1_internal_slave_write_request;

JC1_data_in_d1 = DFFEAS(JC1_data_in_d1_lut_out, PLD_CLOCKINPUT[1], E1_data_out, , , , , , );

--ZB1_data_in_d1 is std_1c20:inst|clock_0:the_clock_0|clock_0_slave_read_request_sync_module:clock_0_slave_read_request_sync|data_in_d1

--operation mode is normal

ZB1_data_in_d1_lut_out = EC1_internal_slave_read_request;

ZB1_data_in_d1 = DFFEAS(ZB1_data_in_d1_lut_out, PLD_CLKFB, D1_data_out, , , , , , );

--AC1_data_in_d1 is std_1c20:inst|clock_0:the_clock_0|clock_0_slave_write_request_sync_module:clock_0_slave_write_request_sync|data_in_d1

--operation mode is normal

AC1_data_in_d1_lut_out = EC1_internal_slave_write_request;

AC1_data_in_d1 = DFFEAS(AC1_data_in_d1_lut_out, PLD_CLKFB, D1_data_out, , , , , , );

--VE1_stage_5 is std_1c20:inst|sdram_s1_arbitrator:the_sdram_s1|rdv_fifo_for_cpu_data_master_to_sdram_s1_module:rdv_fifo_for_cpu_data_master_to_sdram_s1|stage_5

--operation mode is normal

VE1_stage_5_lut_out = WE1_full_6 & VE1_stage_6 # !WE1_full_6 & (NB1L14);

VE1_stage_5 = DFFEAS(VE1_stage_5_lut_out, QC2__clk0, VCC, , WE1L21, , , , );

--GD1_break_readreg[23] is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_break:the_cpu_nios2_oci_break|break_readreg[23]

--operation mode is normal

GD1_break_readreg[23] = AMPP_FUNCTION(QC2__clk0, SD1_internal_jdo1[23], SD1_internal_jdo1[36], SD1_internal_jdo1[37], SD1L189, !C1_CLR_SIGNAL, SD1L189);

--SD1L36 is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|DRsize[0]~20014

--operation mode is normal

SD1L36 = AMPP_FUNCTION(GD1_break_readreg[23], RD1_internal_MonDReg[23], SD1_ir[1]);

--SD1L37 is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|DRsize[0]~20015

--operation mode is normal

SD1L37 = AMPP_FUNCTION(SD1L145, SD1L143, SD1L36, SD1_ir[0]);

--SD1L38 is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|DRsize[0]~20016

--operation mode is normal

SD1L38 = AMPP_FUNCTION(SD1L36, A1L4, SD1L145, SD1_ir[0]);

--GE1_jupdate is std_1c20:inst|jtag_uart:the_jtag_uart|alt_jtag_atlantic:jtag_uart_alt_jtag_atlantic|jupdate

--operation mode is normal

GE1_jupdate = AMPP_FUNCTION(!A1L5, GE1_jupdate, BF4_Q[0], FF1_state[8], GE1L1, !C1_CLR_SIGNAL);

--YE1_delayed_unxsync_rxdxx2 is std_1c20:inst|uart1:the_uart1|uart1_rx:the_uart1_rx|delayed_unxsync_rxdxx2

--operation mode is normal

YE1_delayed_unxsync_rxdxx2_lut_out = YE1_sync_rxd;

YE1_delayed_unxsync_rxdxx2 = DFFEAS(YE1_delayed_unxsync_rxdxx2_lut_out, QC2__clk0, F1_data_out, , , , , , );

--YE1_baud_rate_counter[0] is std_1c20:inst|uart1:the_uart1|uart1_rx:the_uart1_rx|baud_rate_counter[0]

--operation mode is normal

YE1_baud_rate_counter[0]_lut_out = YE1_baud_rate_counter[0] & (YE1_sync_rxd $ YE1_delayed_unxsync_rxdxx2) # !YE1_baud_rate_counter[0] & (YE1_sync_rxd $ YE1_delayed_unxsync_rxdxx2 # !YE1L38);

YE1_baud_rate_counter[0] = DFFEAS(YE1_baud_rate_counter[0]_lut_out, QC2__clk0, F1_data_out, , , , , , );

--YE1_baud_rate_counter[1] is std_1c20:inst|uart1:the_uart1|uart1_rx:the_uart1_rx|baud_rate_counter[1]

--operation mode is normal

YE1_baud_rate_counter[1]_lut_out = YE1L2 & (YE1_sync_rxd $ !YE1_delayed_unxsync_rxdxx2) # !YE1L2 & YE1L38 & (YE1_sync_rxd $ !YE1_delayed_unxsync_rxdxx2);

YE1_baud_rate_counter[1] = DFFEAS(YE1_baud_rate_counter[1]_lut_out, QC2__clk0, F1_data_out, , , , , , );

--YE1_baud_rate_counter[2] is std_1c20:inst|uart1:the_uart1|uart1_rx:the_uart1_rx|baud_rate_counter[2]

--operation mode is normal

YE1_baud_rate_counter[2]_lut_out = YE1L4 & !YE1L38 & (YE1_sync_rxd $ !YE1_delayed_unxsync_rxdxx2);

YE1_baud_rate_counter[2] = DFFEAS(YE1_baud_rate_counter[2]_lut_out, QC2__clk0, F1_data_out, , , , , , );

--YE1_baud_rate_counter[3] is std_1c20:inst|uart1:the_uart1|uart1_rx:the_uart1_rx|baud_rate_counter[3]

--operation mode is normal

YE1_baud_rate_counter[3]_lut_out = YE1L6 & (YE1_sync_rxd $ YE1_delayed_unxsync_rxdxx2 # !YE1L38) # !YE1L6 & (YE1_sync_rxd $ YE1_delayed_unxsync_rxdxx2);

YE1_baud_rate_counter[3] = DFFEAS(YE1_baud_rate_counter[3]_lut_out, QC2__clk0, F1_data_out, , , , , , );

--YE1L36 is std_1c20:inst|uart1:the_uart1|uart1_rx:the_uart1_rx|Equal0~170

--operation mode is normal

YE1L36 = !YE1_baud_rate_counter[0] & !YE1_baud_rate_counter[1] & !YE1_baud_rate_counter[2] & !YE1_baud_rate_counter[3];

--YE1_baud_rate_counter[4] is std_1c20:inst|uart1:the_uart1|uart1_rx:the_uart1_rx|baud_rate_counter[4]

--operation mode is normal

YE1_baud_rate_counter[4]_lut_out = YE1L8 # YE1L38 # YE1_sync_rxd $ YE1_delayed_unxsync_rxdxx2;

YE1_baud_rate_counter[4] = DFFEAS(YE1_baud_rate_counter[4]_lut_out, QC2__clk0, F1_data_out, , , , , , );

--YE1_baud_rate_counter[5] is std_1c20:inst|uart1:the_uart1|uart1_rx:the_uart1_rx|baud_rate_counter[5]

--operation mode is normal

YE1_baud_rate_counter[5]_lut_out = YE1L10 & (YE1_sync_rxd $ !YE1_delayed_unxsync_rxdxx2) # !YE1L10 & YE1L38 & (YE1_sync_rxd $ !YE1_delayed_unxsync_rxdxx2);

YE1_baud_rate_counter[5] = DFFEAS(YE1_baud_rate_counter[5]_lut_out, QC2__clk0, F1_data_out, , , , , , );

--YE1_baud_rate_counter[6] is std_1c20:inst|uart1:the_uart1|uart1_rx:the_uart1_rx|baud_rate_counter[6]

--operation mode is normal

YE1_baud_rate_counter[6]_lut_out = YE1L12 & (YE1_sync_rxd $ YE1_delayed_unxsync_rxdxx2 # !YE1L38) # !YE1L12 & (YE1_sync_rxd $ YE1_delayed_unxsync_rxdxx2);

YE1_baud_rate_counter[6] = DFFEAS(YE1_baud_rate_counter[6]_lut_out, QC2__clk0, F1_data_out, , , , , , );

--YE1_baud_rate_counter[7] is std_1c20:inst|uart1:the_uart1|uart1_rx:the_uart1_rx|baud_rate_counter[7]

--operation mode is normal

YE1_baud_rate_counter[7]_lut_out = YE1L14 # YE1L38 # YE1_sync_rxd $ YE1_delayed_unxsync_rxdxx2;

YE1_baud_rate_counter[7] = DFFEAS(YE1_baud_rate_counter[7]_lut_out, QC2__clk0, F1_data_out, , , , , , );

--YE1L37 is std_1c20:inst|uart1:the_uart1|uart1_rx:the_uart1_rx|Equal0~171

--operation mode is normal

YE1L37 = !YE1_baud_rate_counter[4] & !YE1_baud_rate_counter[5] & !YE1_baud_rate_counter[6] & !YE1_baud_rate_counter[7];

--YE1_rxd_edge is std_1c20:inst|uart1:the_uart1|uart1_rx:the_uart1_rx|rxd_edge

--operation mode is normal

YE1_rxd_edge = YE1_sync_rxd $ YE1_delayed_unxsync_rxdxx2;

--YE1_baud_rate_counter[8] is std_1c20:inst|uart1:the_uart1|uart1_rx:the_uart1_rx|baud_rate_counter[8]

--operation mode is normal

YE1_baud_rate_counter[8]_lut_out = YE1L16 & (YE1_sync_rxd $ !YE1_delayed_unxsync_rxdxx2) # !YE1L16 & YE1L38 & (YE1_sync_rxd $ !YE1_delayed_unxsync_rxdxx2);

YE1_baud_rate_counter[8] = DFFEAS(YE1_baud_rate_counter[8]_lut_out, QC2__clk0, F1_data_out, , , , , , );

--YE1_d1_source_rxd is std_1c20:inst|uart1:the_uart1|uart1_rx:the_uart1_rx|d1_source_rxd

--operation mode is normal

YE1_d1_source_rxd_lut_out = rxd_to_the_uart1;

YE1_d1_source_rxd = DFFEAS(YE1_d1_source_rxd_lut_out, QC2__clk0, F1_data_out, , , , , , );

--M1_slave_nativeaddress_d1[0] is std_1c20:inst|clock_1:the_clock_1|slave_nativeaddress_d1[0]

--operation mode is normal

M1_slave_nativeaddress_d1[0]_lut_out = S1_M_alu_result[2];

M1_slave_nativeaddress_d1[0] = DFFEAS(M1_slave_nativeaddress_d1[0]_lut_out, QC2__clk0, F1_data_out, , , , , , );

--M1_master_writedata[2] is std_1c20:inst|clock_1:the_clock_1|master_writedata[2]

--operation mode is normal

M1_master_writedata[2]_lut_out = M1_slave_writedata_d1[2];

M1_master_writedata[2] = DFFEAS(M1_master_writedata[2]_lut_out, PLD_CLOCKINPUT[1], E1_data_out, , , , , , );

--M1_master_nativeaddress[1] is std_1c20:inst|clock_1:the_clock_1|master_nativeaddress[1]

--operation mode is normal

M1_master_nativeaddress[1]_lut_out = M1_slave_nativeaddress_d1[1];

M1_master_nativeaddress[1] = DFFEAS(M1_master_nativeaddress[1]_lut_out, PLD_CLOCKINPUT[1], E1_data_out, , , , , , );

--M1_master_nativeaddress[2] is std_1c20:inst|clock_1:the_clock_1|master_nativeaddress[2]

--operation mode is normal

M1_master_nativeaddress[2]_lut_out = M1_slave_nativeaddress_d1[2];

M1_master_nativeaddress[2] = DFFEAS(M1_master_nativeaddress[2]_lut_out, PLD_CLOCKINPUT[1], E1_data_out, , , , , , );

--Q1L1 is std_1c20:inst|connector_pll:the_connector_pll|control_reg_en~18

--operation mode is normal

Q1L1 = !M1_master_nativeaddress[1] & !M1_master_nativeaddress[2] & LC1_master_state[2] & M1_master_nativeaddress[0];

--J1_slave_nativeaddress_d1[0] is std_1c20:inst|clock_0:the_clock_0|slave_nativeaddress_d1[0]

--operation mode is normal

J1_slave_nativeaddress_d1[0]_lut_out = S1_M_alu_result[2];

J1_slave_nativeaddress_d1[0] = DFFEAS(J1_slave_nativeaddress_d1[0]_lut_out, QC2__clk0, F1_data_out, , , , , , );

--J1_master_writedata[2] is std_1c20:inst|clock_0:the_clock_0|master_writedata[2]

--operation mode is normal

J1_master_writedata[2]_lut_out = J1_slave_writedata_d1[2];

J1_master_writedata[2] = DFFEAS(J1_master_writedata[2]_lut_out, PLD_CLKFB, D1_data_out, , , , , , );

--J1_master_nativeaddress[1] is std_1c20:inst|clock_0:the_clock_0|master_nativeaddress[1]

--operation mode is normal

J1_master_nativeaddress[1]_lut_out = J1_slave_nativeaddress_d1[1];

J1_master_nativeaddress[1] = DFFEAS(J1_master_nativeaddress[1]_lut_out, PLD_CLKFB, D1_data_out, , , , , , );

--J1_master_nativeaddress[2] is std_1c20:inst|clock_0:the_clock_0|master_nativeaddress[2]

--operation mode is normal

J1_master_nativeaddress[2]_lut_out = J1_slave_nativeaddress_d1[2];

J1_master_nativeaddress[2] = DFFEAS(J1_master_nativeaddress[2]_lut_out, PLD_CLKFB, D1_data_out, , , , , , );

--LB1L1 is std_1c20:inst|sdram_pll:the_sdram_pll|control_reg_en~18

--operation mode is normal

LB1L1 = !J1_master_nativeaddress[1] & !J1_master_nativeaddress[2] & CC1_master_state[2] & J1_master_nativeaddress[0];

--GE1_rdata[4] is std_1c20:inst|jtag_uart:the_jtag_uart|alt_jtag_atlantic:jtag_uart_alt_jtag_atlantic|rdata[4]

--operation mode is normal

GE1_rdata[4] = AMPP_FUNCTION(QC2__clk0, SE1_q_b[4], F1_data_out, GE1L18);

--GE1L58 is std_1c20:inst|jtag_uart:the_jtag_uart|alt_jtag_atlantic:jtag_uart_alt_jtag_atlantic|td_shift[9]~3564

--operation mode is normal

GE1L58 = AMPP_FUNCTION(GE1_rdata[4], GE1_td_shift[7], GE1_count[9]);

--DE1_tx_holding_reg[1] is std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|tx_holding_reg[1]

--operation mode is normal

DE1_tx_holding_reg[1]_lut_out = S1_M_st_data[1];

DE1_tx_holding_reg[1] = DFFEAS(DE1_tx_holding_reg[1]_lut_out, QC2__clk0, F1_data_out, , DE1_write_tx_holding, , , , );

--DE1_write_tx_holding is std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|write_tx_holding

--operation mode is normal

DE1_write_tx_holding = DE1_data_wr_strobe & (!DE1_transmitting # !DE1_tx_holding_primed);

--DE1L158 is std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|SCLK_reg~289

--operation mode is normal

DE1L158 = DE1L117 & (DE1_state[4] $ !DE1_state[0]);

--RD1L84 is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|MonRd~104

--operation mode is normal

RD1L84 = AMPP_FUNCTION(V1L26, JD1_resetrequest);

--GD1_break_readreg[3] is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_break:the_cpu_nios2_oci_break|break_readreg[3]

--operation mode is normal

GD1_break_readreg[3] = AMPP_FUNCTION(QC2__clk0, SD1_internal_jdo1[3], SD1_internal_jdo1[36], SD1_internal_jdo1[37], SD1L189, !C1_CLR_SIGNAL, SD1L189);

--SD1L128 is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|Mux36~14

--operation mode is normal

SD1L128 = AMPP_FUNCTION(RD1_internal_MonDReg[3], SD1_ir[1], GD1_break_readreg[3], SD1_ir[0]);

--GD1_break_readreg[4] is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_break:the_cpu_nios2_oci_break|break_readreg[4]

--operation mode is normal

GD1_break_readreg[4] = AMPP_FUNCTION(QC2__clk0, SD1_internal_jdo1[4], SD1_internal_jdo1[36], SD1_internal_jdo1[37], SD1L189, !C1_CLR_SIGNAL, SD1L189);

--SD1L127 is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|Mux35~14

--operation mode is normal

SD1L127 = AMPP_FUNCTION(RD1_internal_MonDReg[4], SD1_ir[1], GD1_break_readreg[4], SD1_ir[0]);

--GD1_break_readreg[5] is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_break:the_cpu_nios2_oci_break|break_readreg[5]

--operation mode is normal

GD1_break_readreg[5] = AMPP_FUNCTION(QC2__clk0, SD1_internal_jdo1[5], SD1_internal_jdo1[36], SD1_internal_jdo1[37], SD1L189, !C1_CLR_SIGNAL, SD1L189);

--SD1L126 is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|Mux34~14

--operation mode is normal

SD1L126 = AMPP_FUNCTION(RD1_internal_MonDReg[5], SD1_ir[1], GD1_break_readreg[5], SD1_ir[0]);

--GD1_break_readreg[6] is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_break:the_cpu_nios2_oci_break|break_readreg[6]

--operation mode is normal

GD1_break_readreg[6] = AMPP_FUNCTION(QC2__clk0, SD1_internal_jdo1[6], SD1_internal_jdo1[36], SD1_internal_jdo1[37], SD1L189, !C1_CLR_SIGNAL, SD1L189);

--SD1L125 is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|Mux33~12

--operation mode is normal

SD1L125 = AMPP_FUNCTION(RD1_internal_MonDReg[6], SD1_ir[1], GD1_break_readreg[6], SD1_ir[0]);

--SD1L139 is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|Mux44~43

--operation mode is normal

SD1L139 = AMPP_FUNCTION(SD1_DRsize[0], SD1L73Q);

--GD1_break_readreg[7] is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_break:the_cpu_nios2_oci_break|break_readreg[7]

--operation mode is normal

GD1_break_readreg[7] = AMPP_FUNCTION(QC2__clk0, SD1_internal_jdo1[7], SD1_internal_jdo1[36], SD1_internal_jdo1[37], SD1L189, !C1_CLR_SIGNAL, SD1L189);

--SD1L124 is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|Mux32~14

--operation mode is normal

SD1L124 = AMPP_FUNCTION(RD1_internal_MonDReg[7], SD1_ir[1], GD1_break_readreg[7], SD1_ir[0]);

--GD1_break_readreg[8] is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_break:the_cpu_nios2_oci_break|break_readreg[8]

--operation mode is normal

GD1_break_readreg[8] = AMPP_FUNCTION(QC2__clk0, SD1_internal_jdo1[8], SD1_internal_jdo1[36], SD1_internal_jdo1[37], SD1L189, !C1_CLR_SIGNAL, SD1L189);

--SD1L39 is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|DRsize[0]~20022

--operation mode is normal

SD1L39 = AMPP_FUNCTION(GD1_break_readreg[8], RD1_internal_MonDReg[8], SD1_ir[1], SD1_ir[0]);

--GD1_break_readreg[9] is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_break:the_cpu_nios2_oci_break|break_readreg[9]

--operation mode is normal

GD1_break_readreg[9] = AMPP_FUNCTION(QC2__clk0, SD1_internal_jdo1[9], SD1_internal_jdo1[36], SD1_internal_jdo1[37], SD1L189, !C1_CLR_SIGNAL, SD1L189);

--SD1L40 is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|DRsize[0]~20024

--operation mode is normal

SD1L40 = AMPP_FUNCTION(GD1_break_readreg[9], RD1_internal_MonDReg[9], SD1_ir[1], SD1_ir[0]);

--GD1_break_readreg[25] is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_break:the_cpu_nios2_oci_break|break_readreg[25]

--operation mode is normal

GD1_break_readreg[25] = AMPP_FUNCTION(QC2__clk0, SD1_internal_jdo1[25], SD1_internal_jdo1[36], SD1_internal_jdo1[37], SD1L189, !C1_CLR_SIGNAL, SD1L189);

--SD1L41 is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|DRsize[0]~20026

--operation mode is normal

SD1L41 = AMPP_FUNCTION(GD1_break_readreg[25], RD1_internal_MonDReg[25], SD1_ir[1]);

--SD1L42 is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|DRsize[0]~20027

--operation mode is normal

SD1L42 = AMPP_FUNCTION(SD1L145, SD1L143, SD1L41, SD1_ir[0]);

--SD1L43 is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|DRsize[0]~20028

--operation mode is normal

SD1L43 = AMPP_FUNCTION(SD1L41, A1L4, SD1L145, SD1_ir[0]);

--GD1_break_readreg[26] is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_break:the_cpu_nios2_oci_break|break_readreg[26]

--operation mode is normal

GD1_break_readreg[26] = AMPP_FUNCTION(QC2__clk0, SD1_internal_jdo1[26], SD1_internal_jdo1[36], SD1_internal_jdo1[37], SD1L189, !C1_CLR_SIGNAL, SD1L189);

--SD1L44 is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|DRsize[0]~20030

--operation mode is normal

SD1L44 = AMPP_FUNCTION(GD1_break_readreg[26], RD1_internal_MonDReg[26], SD1_ir[1]);

--SD1L45 is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|DRsize[0]~20031

--operation mode is normal

SD1L45 = AMPP_FUNCTION(SD1L145, SD1L143, SD1L44, SD1_ir[0]);

--SD1L46 is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|DRsize[0]~20032

--operation mode is normal

SD1L46 = AMPP_FUNCTION(SD1L44, A1L4, SD1L145, SD1_ir[0]);

--GD1_break_readreg[27] is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_break:the_cpu_nios2_oci_break|break_readreg[27]

--operation mode is normal

GD1_break_readreg[27] = AMPP_FUNCTION(QC2__clk0, SD1_internal_jdo1[27], SD1_internal_jdo1[36], SD1_internal_jdo1[37], SD1L189, !C1_CLR_SIGNAL, SD1L189);

--SD1L47 is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|DRsize[0]~20034

--operation mode is normal

SD1L47 = AMPP_FUNCTION(GD1_break_readreg[27], RD1_internal_MonDReg[27], SD1_ir[1]);

--SD1L48 is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|DRsize[0]~20035

--operation mode is normal

SD1L48 = AMPP_FUNCTION(SD1L144, SD1_ir[1], SD1L47, SD1_ir[0]);

--GD1_break_readreg[28] is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_break:the_cpu_nios2_oci_break|break_readreg[28]

--operation mode is normal

GD1_break_readreg[28] = AMPP_FUNCTION(QC2__clk0, SD1_internal_jdo1[28], SD1_internal_jdo1[36], SD1_internal_jdo1[37], SD1L189, !C1_CLR_SIGNAL, SD1L189);

--SD1L49 is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|DRsize[0]~20037

--operation mode is normal

SD1L49 = AMPP_FUNCTION(GD1_break_readreg[28], RD1_internal_MonDReg[28], SD1_ir[1]);

--SD1L50 is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|DRsize[0]~20038

--operation mode is normal

SD1L50 = AMPP_FUNCTION(SD1L145, SD1L143, SD1L49, SD1_ir[0]);

--SD1L51 is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|DRsize[0]~20039

--operation mode is normal

SD1L51 = AMPP_FUNCTION(SD1L49, A1L4, SD1L145, SD1_ir[0]);

--GD1_break_readreg[29] is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_break:the_cpu_nios2_oci_break|break_readreg[29]

--operation mode is normal

GD1_break_readreg[29] = AMPP_FUNCTION(QC2__clk0, SD1_internal_jdo1[29], SD1_internal_jdo1[36], SD1_internal_jdo1[37], SD1L189, !C1_CLR_SIGNAL, SD1L189);

--SD1L52 is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|DRsize[0]~20041

--operation mode is normal

SD1L52 = AMPP_FUNCTION(GD1_break_readreg[29], RD1_internal_MonDReg[29], SD1_ir[1]);

--SD1L53 is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|DRsize[0]~20042

--operation mode is normal

SD1L53 = AMPP_FUNCTION(SD1L144, SD1_ir[1], SD1L52, SD1_ir[0]);

--SD1L135 is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|Mux42~97

--operation mode is normal

SD1L135 = AMPP_FUNCTION(altera_internal_jtag, SD1_DRsize[1], SD1_DRsize[0], SD1_DRsize[2]);

--SD1L136 is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|Mux42~98

--operation mode is normal

SD1L136 = AMPP_FUNCTION(SD1_sr[32], SD1_DRsize[2], SD1_DRsize[1], SD1_DRsize[0]);

--SD1L54 is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|DRsize[0]~20044

--operation mode is normal

SD1L54 = AMPP_FUNCTION(A1L4, SD1L145, SD1L135, SD1L136);

--SD1L137 is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|Mux42~99

--operation mode is normal

SD1L137 = AMPP_FUNCTION(SD1L135, SD1L136);

--GD1_break_readreg[30] is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_break:the_cpu_nios2_oci_break|break_readreg[30]

--operation mode is normal

GD1_break_readreg[30] = AMPP_FUNCTION(QC2__clk0, SD1_internal_jdo1[30], SD1_internal_jdo1[36], SD1_internal_jdo1[37], SD1L189, !C1_CLR_SIGNAL, SD1L189);

--SD1L55 is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|DRsize[0]~20045

--operation mode is normal

SD1L55 = AMPP_FUNCTION(GD1_break_readreg[30], RD1_internal_MonDReg[30], SD1_ir[1]);

--GD1_break_readreg[31] is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_break:the_cpu_nios2_oci_break|break_readreg[31]

--operation mode is normal

GD1_break_readreg[31] = AMPP_FUNCTION(QC2__clk0, SD1_internal_jdo1[31], SD1_internal_jdo1[36], SD1_internal_jdo1[37], SD1L189, !C1_CLR_SIGNAL, SD1L189);

--SD1L56 is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|DRsize[0]~20046

--operation mode is normal

SD1L56 = AMPP_FUNCTION(GD1_break_readreg[31], RD1_internal_MonDReg[31], SD1_ir[1]);

--SD1L57 is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|DRsize[0]~20047

--operation mode is normal

SD1L57 = AMPP_FUNCTION(SD1L145, SD1L143, SD1L56, SD1_ir[0]);

--SD1L58 is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|DRsize[0]~20048

--operation mode is normal

SD1L58 = AMPP_FUNCTION(SD1L56, A1L4, SD1L145, SD1_ir[0]);

--JD1_internal_resetlatch is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_debug:the_cpu_nios2_oci_debug|internal_resetlatch

--operation mode is normal

JD1_internal_resetlatch = AMPP_FUNCTION(QC2__clk0, SD1_internal_jdo1[24], SD1L191, JD1_internal_resetlatch, JD1L9, VCC);

--SD1L59 is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|DRsize[0]~20050

--operation mode is normal

SD1L59 = AMPP_FUNCTION(JD1_internal_resetlatch, SD1_ir[0], SD1_ir[1]);

--M1_master_writedata[3] is std_1c20:inst|clock_1:the_clock_1|master_writedata[3]

--operation mode is normal

M1_master_writedata[3]_lut_out = M1_slave_writedata_d1[3];

M1_master_writedata[3] = DFFEAS(M1_master_writedata[3]_lut_out, PLD_CLOCKINPUT[1], E1_data_out, , , , , , );

--J1_master_writedata[3] is std_1c20:inst|clock_0:the_clock_0|master_writedata[3]

--operation mode is normal

J1_master_writedata[3]_lut_out = J1_slave_writedata_d1[3];

J1_master_writedata[3] = DFFEAS(J1_master_writedata[3]_lut_out, PLD_CLKFB, D1_data_out, , , , , , );

--GE1_rdata[5] is std_1c20:inst|jtag_uart:the_jtag_uart|alt_jtag_atlantic:jtag_uart_alt_jtag_atlantic|rdata[5]

--operation mode is normal

GE1_rdata[5] = AMPP_FUNCTION(QC2__clk0, SE1_q_b[5], F1_data_out, GE1L18);

--GE1L59 is std_1c20:inst|jtag_uart:the_jtag_uart|alt_jtag_atlantic:jtag_uart_alt_jtag_atlantic|td_shift[9]~3566

--operation mode is normal

GE1L59 = AMPP_FUNCTION(GE1_rdata[5], GE1_td_shift[8], GE1_count[9]);

--XC1L11 is std_1c20:inst|cpu:the_cpu|cpu_test_bench:the_cpu_test_bench|Add0~569

--operation mode is arithmetic

XC1L11 = AMPP_FUNCTION(S1L596, S1L662, XC1L13);

--M1_master_writedata[15] is std_1c20:inst|clock_1:the_clock_1|master_writedata[15]

--operation mode is normal

M1_master_writedata[15]_lut_out = M1_slave_writedata_d1[15];

M1_master_writedata[15] = DFFEAS(M1_master_writedata[15]_lut_out, PLD_CLOCKINPUT[1], E1_data_out, , , , , , );

--J1_master_writedata[15] is std_1c20:inst|clock_0:the_clock_0|master_writedata[15]

--operation mode is normal

J1_master_writedata[15]_lut_out = J1_slave_writedata_d1[15];

J1_master_writedata[15] = DFFEAS(J1_master_writedata[15]_lut_out, PLD_CLKFB, D1_data_out, , , , , , );

--GD1_break_readreg[10] is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_break:the_cpu_nios2_oci_break|break_readreg[10]

--operation mode is normal

GD1_break_readreg[10] = AMPP_FUNCTION(QC2__clk0, SD1_internal_jdo1[10], SD1_internal_jdo1[36], SD1_internal_jdo1[37], SD1L189, !C1_CLR_SIGNAL, SD1L189);

--SD1L60 is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|DRsize[0]~20052

--operation mode is normal

SD1L60 = AMPP_FUNCTION(GD1_break_readreg[10], RD1_internal_MonDReg[10], SD1_ir[1], SD1_ir[0]);

--GD1_break_readreg[11] is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_break:the_cpu_nios2_oci_break|break_readreg[11]

--operation mode is normal

GD1_break_readreg[11] = AMPP_FUNCTION(QC2__clk0, SD1_internal_jdo1[11], SD1_internal_jdo1[36], SD1_internal_jdo1[37], SD1L189, !C1_CLR_SIGNAL, SD1L189);

--SD1L61 is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|DRsize[0]~20054

--operation mode is normal

SD1L61 = AMPP_FUNCTION(GD1_break_readreg[11], RD1_internal_MonDReg[11], SD1_ir[1], SD1_ir[0]);

--GD1_break_readreg[12] is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_break:the_cpu_nios2_oci_break|break_readreg[12]

--operation mode is normal

GD1_break_readreg[12] = AMPP_FUNCTION(QC2__clk0, SD1_internal_jdo1[12], SD1_internal_jdo1[36], SD1_internal_jdo1[37], SD1L189, !C1_CLR_SIGNAL, SD1L189);

--SD1L62 is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|DRsize[0]~20056

--operation mode is normal

SD1L62 = AMPP_FUNCTION(GD1_break_readreg[12], RD1_internal_MonDReg[12], SD1_ir[1], SD1_ir[0]);

--GD1_break_readreg[13] is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_break:the_cpu_nios2_oci_break|break_readreg[13]

--operation mode is normal

GD1_break_readreg[13] = AMPP_FUNCTION(QC2__clk0, SD1_internal_jdo1[13], SD1_internal_jdo1[36], SD1_internal_jdo1[37], SD1L189, !C1_CLR_SIGNAL, SD1L189);

--SD1L63 is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|DRsize[0]~20058

--operation mode is normal

SD1L63 = AMPP_FUNCTION(GD1_break_readreg[13], RD1_internal_MonDReg[13], SD1_ir[1], SD1_ir[0]);

--GD1_break_readreg[14] is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_break:the_cpu_nios2_oci_break|break_readreg[14]

--operation mode is normal

GD1_break_readreg[14] = AMPP_FUNCTION(QC2__clk0, SD1_internal_jdo1[14], SD1_internal_jdo1[36], SD1_internal_jdo1[37], SD1L189, !C1_CLR_SIGNAL, SD1L189);

--SD1L123 is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|Mux25~52

--operation mode is normal

SD1L123 = AMPP_FUNCTION(GD1_break_readreg[14], RD1_internal_MonDReg[14], SD1_ir[1], SD1_ir[0]);

--SD1L138 is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|Mux43~45

--operation mode is normal

SD1L138 = AMPP_FUNCTION(SD1_DRsize[1], SD1_DRsize[2], SD1_DRsize[0]);

--GD1_break_readreg[15] is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_break:the_cpu_nios2_oci_break|break_readreg[15]

--operation mode is normal

GD1_break_readreg[15] = AMPP_FUNCTION(QC2__clk0, SD1_internal_jdo1[15], SD1_internal_jdo1[36], SD1_internal_jdo1[37], SD1L189, !C1_CLR_SIGNAL, SD1L189);

--SD1L64 is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|DRsize[0]~20060

--operation mode is normal

SD1L64 = AMPP_FUNCTION(GD1_break_readreg[15], RD1_internal_MonDReg[15], SD1_ir[1]);

--SD1L65 is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|DRsize[0]~20061

--operation mode is normal

SD1L65 = AMPP_FUNCTION(SD1L145, SD1L143, SD1L64, SD1_ir[0]);

--SD1L66 is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|DRsize[0]~20062

--operation mode is normal

SD1L66 = AMPP_FUNCTION(SD1L64, A1L4, SD1L145, SD1_ir[0]);

--GD1_break_readreg[16] is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_break:the_cpu_nios2_oci_break|break_readreg[16]

--operation mode is normal

GD1_break_readreg[16] = AMPP_FUNCTION(QC2__clk0, SD1_internal_jdo1[16], SD1_internal_jdo1[36], SD1_internal_jdo1[37], SD1L189, !C1_CLR_SIGNAL, SD1L189);

--SD1L67 is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|DRsize[0]~20064

--operation mode is normal

SD1L67 = AMPP_FUNCTION(GD1_break_readreg[16], RD1_internal_MonDReg[16], SD1_ir[1]);

--SD1L68 is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|DRsize[0]~20065

--operation mode is normal

SD1L68 = AMPP_FUNCTION(SD1L145, SD1L143, SD1L67, SD1_ir[0]);

--SD1L69 is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|DRsize[0]~20066

--operation mode is normal

SD1L69 = AMPP_FUNCTION(SD1L67, A1L4, SD1L145, SD1_ir[0]);

--M1_master_writedata[7] is std_1c20:inst|clock_1:the_clock_1|master_writedata[7]

--operation mode is normal

M1_master_writedata[7]_lut_out = M1_slave_writedata_d1[7];

M1_master_writedata[7] = DFFEAS(M1_master_writedata[7]_lut_out, PLD_CLOCKINPUT[1], E1_data_out, , , , , , );

--J1_master_writedata[7] is std_1c20:inst|clock_0:the_clock_0|master_writedata[7]

--operation mode is normal

J1_master_writedata[7]_lut_out = J1_slave_writedata_d1[7];

J1_master_writedata[7] = DFFEAS(J1_master_writedata[7]_lut_out, PLD_CLKFB, D1_data_out, , , , , , );

--M1_master_writedata[14] is std_1c20:inst|clock_1:the_clock_1|master_writedata[14]

--operation mode is normal

M1_master_writedata[14]_lut_out = M1_slave_writedata_d1[14];

M1_master_writedata[14] = DFFEAS(M1_master_writedata[14]_lut_out, PLD_CLOCKINPUT[1], E1_data_out, , , , , , );

--J1_master_writedata[14] is std_1c20:inst|clock_0:the_clock_0|master_writedata[14]

--operation mode is normal

J1_master_writedata[14]_lut_out = J1_slave_writedata_d1[14];

J1_master_writedata[14] = DFFEAS(J1_master_writedata[14]_lut_out, PLD_CLKFB, D1_data_out, , , , , , );

--M1_master_writedata[13] is std_1c20:inst|clock_1:the_clock_1|master_writedata[13]

--operation mode is normal

M1_master_writedata[13]_lut_out = M1_slave_writedata_d1[13];

M1_master_writedata[13] = DFFEAS(M1_master_writedata[13]_lut_out, PLD_CLOCKINPUT[1], E1_data_out, , , , , , );

--J1_master_writedata[13] is std_1c20:inst|clock_0:the_clock_0|master_writedata[13]

--operation mode is normal

J1_master_writedata[13]_lut_out = J1_slave_writedata_d1[13];

J1_master_writedata[13] = DFFEAS(J1_master_writedata[13]_lut_out, PLD_CLKFB, D1_data_out, , , , , , );

--M1_master_writedata[12] is std_1c20:inst|clock_1:the_clock_1|master_writedata[12]

--operation mode is normal

M1_master_writedata[12]_lut_out = M1_slave_writedata_d1[12];

M1_master_writedata[12] = DFFEAS(M1_master_writedata[12]_lut_out, PLD_CLOCKINPUT[1], E1_data_out, , , , , , );

--J1_master_writedata[12] is std_1c20:inst|clock_0:the_clock_0|master_writedata[12]

--operation mode is normal

J1_master_writedata[12]_lut_out = J1_slave_writedata_d1[12];

J1_master_writedata[12] = DFFEAS(J1_master_writedata[12]_lut_out, PLD_CLKFB, D1_data_out, , , , , , );

--J1_master_writedata[11] is std_1c20:inst|clock_0:the_clock_0|master_writedata[11]

--operation mode is normal

J1_master_writedata[11]_lut_out = J1_slave_writedata_d1[11];

J1_master_writedata[11] = DFFEAS(J1_master_writedata[11]_lut_out, PLD_CLKFB, D1_data_out, , , , , , );

--M1_master_writedata[11] is std_1c20:inst|clock_1:the_clock_1|master_writedata[11]

--operation mode is normal

M1_master_writedata[11]_lut_out = M1_slave_writedata_d1[11];

M1_master_writedata[11] = DFFEAS(M1_master_writedata[11]_lut_out, PLD_CLOCKINPUT[1], E1_data_out, , , , , , );

--M1_master_writedata[10] is std_1c20:inst|clock_1:the_clock_1|master_writedata[10]

--operation mode is normal

M1_master_writedata[10]_lut_out = M1_slave_writedata_d1[10];

M1_master_writedata[10] = DFFEAS(M1_master_writedata[10]_lut_out, PLD_CLOCKINPUT[1], E1_data_out, , , , , , );

--J1_master_writedata[10] is std_1c20:inst|clock_0:the_clock_0|master_writedata[10]

--operation mode is normal

J1_master_writedata[10]_lut_out = J1_slave_writedata_d1[10];

J1_master_writedata[10] = DFFEAS(J1_master_writedata[10]_lut_out, PLD_CLKFB, D1_data_out, , , , , , );

--DE1_MISO_reg is std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|MISO_reg

--operation mode is normal

DE1_MISO_reg_lut_out = DE1_slowcount[0] & (DE1_SCLK_reg & DE1_MISO_reg # !DE1_SCLK_reg & (EE1_internal_data0out)) # !DE1_slowcount[0] & DE1_MISO_reg;

DE1_MISO_reg = DFFEAS(DE1_MISO_reg_lut_out, QC2__clk0, F1_data_out, , , , , , );

--DE1_tx_holding_reg[0] is std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|tx_holding_reg[0]

--operation mode is normal

DE1_tx_holding_reg[0]_lut_out = S1_M_st_data[0];

DE1_tx_holding_reg[0] = DFFEAS(DE1_tx_holding_reg[0]_lut_out, QC2__clk0, F1_data_out, , DE1_write_tx_holding, , , , );

--M1_master_writedata[9] is std_1c20:inst|clock_1:the_clock_1|master_writedata[9]

--operation mode is normal

M1_master_writedata[9]_lut_out = M1_slave_writedata_d1[9];

M1_master_writedata[9] = DFFEAS(M1_master_writedata[9]_lut_out, PLD_CLOCKINPUT[1], E1_data_out, , , , , , );

--J1_master_writedata[9] is std_1c20:inst|clock_0:the_clock_0|master_writedata[9]

--operation mode is normal

J1_master_writedata[9]_lut_out = J1_slave_writedata_d1[9];

J1_master_writedata[9] = DFFEAS(J1_master_writedata[9]_lut_out, PLD_CLKFB, D1_data_out, , , , , , );

--M1_master_writedata[8] is std_1c20:inst|clock_1:the_clock_1|master_writedata[8]

--operation mode is normal

M1_master_writedata[8]_lut_out = M1_slave_writedata_d1[8];

M1_master_writedata[8] = DFFEAS(M1_master_writedata[8]_lut_out, PLD_CLOCKINPUT[1], E1_data_out, , , , , , );

--J1_master_writedata[8] is std_1c20:inst|clock_0:the_clock_0|master_writedata[8]

--operation mode is normal

J1_master_writedata[8]_lut_out = J1_slave_writedata_d1[8];

J1_master_writedata[8] = DFFEAS(J1_master_writedata[8]_lut_out, PLD_CLKFB, D1_data_out, , , , , , );

--M1_master_writedata[6] is std_1c20:inst|clock_1:the_clock_1|master_writedata[6]

--operation mode is normal

M1_master_writedata[6]_lut_out = M1_slave_writedata_d1[6];

M1_master_writedata[6] = DFFEAS(M1_master_writedata[6]_lut_out, PLD_CLOCKINPUT[1], E1_data_out, , , , , , );

--J1_master_writedata[6] is std_1c20:inst|clock_0:the_clock_0|master_writedata[6]

--operation mode is normal

J1_master_writedata[6]_lut_out = J1_slave_writedata_d1[6];

J1_master_writedata[6] = DFFEAS(J1_master_writedata[6]_lut_out, PLD_CLKFB, D1_data_out, , , , , , );

--M1_master_writedata[4] is std_1c20:inst|clock_1:the_clock_1|master_writedata[4]

--operation mode is normal

M1_master_writedata[4]_lut_out = M1_slave_writedata_d1[4];

M1_master_writedata[4] = DFFEAS(M1_master_writedata[4]_lut_out, PLD_CLOCKINPUT[1], E1_data_out, , , , , , );

--J1_master_writedata[4] is std_1c20:inst|clock_0:the_clock_0|master_writedata[4]

--operation mode is normal

J1_master_writedata[4]_lut_out = J1_slave_writedata_d1[4];

J1_master_writedata[4] = DFFEAS(J1_master_writedata[4]_lut_out, PLD_CLKFB, D1_data_out, , , , , , );

--GE1_rdata[6] is std_1c20:inst|jtag_uart:the_jtag_uart|alt_jtag_atlantic:jtag_uart_alt_jtag_atlantic|rdata[6]

--operation mode is normal

GE1_rdata[6] = AMPP_FUNCTION(QC2__clk0, SE1_q_b[6], F1_data_out, GE1L18);

--M1_master_writedata[5] is std_1c20:inst|clock_1:the_clock_1|master_writedata[5]

--operation mode is normal

M1_master_writedata[5]_lut_out = M1_slave_writedata_d1[5];

M1_master_writedata[5] = DFFEAS(M1_master_writedata[5]_lut_out, PLD_CLOCKINPUT[1], E1_data_out, , , , , , );

--J1_master_writedata[5] is std_1c20:inst|clock_0:the_clock_0|master_writedata[5]

--operation mode is normal

J1_master_writedata[5]_lut_out = J1_slave_writedata_d1[5];

J1_master_writedata[5] = DFFEAS(J1_master_writedata[5]_lut_out, PLD_CLKFB, D1_data_out, , , , , , );

--Q1_control_reg_out[0] is std_1c20:inst|connector_pll:the_connector_pll|control_reg_out[0]

--operation mode is normal

Q1_control_reg_out[0]_lut_out = M1_master_writedata[0];

Q1_control_reg_out[0] = DFFEAS(Q1_control_reg_out[0]_lut_out, PLD_CLOCKINPUT[1], E1_data_out, , Q1L1, , , , );

--LB1_control_reg_out[0] is std_1c20:inst|sdram_pll:the_sdram_pll|control_reg_out[0]

--operation mode is normal

LB1_control_reg_out[0]_lut_out = J1_master_writedata[0];

LB1_control_reg_out[0] = DFFEAS(LB1_control_reg_out[0]_lut_out, PLD_CLKFB, D1_data_out, , LB1L1, , , , );

--Q1_control_reg_out[1] is std_1c20:inst|connector_pll:the_connector_pll|control_reg_out[1]

--operation mode is normal

Q1_control_reg_out[1]_lut_out = !M1_master_writedata[1];

Q1_control_reg_out[1] = DFFEAS(Q1_control_reg_out[1]_lut_out, PLD_CLOCKINPUT[1], E1_data_out, , Q1L1, , , , );

--LB1_control_reg_out[1] is std_1c20:inst|sdram_pll:the_sdram_pll|control_reg_out[1]

--operation mode is normal

LB1_control_reg_out[1]_lut_out = !J1_master_writedata[1];

LB1_control_reg_out[1] = DFFEAS(LB1_control_reg_out[1]_lut_out, PLD_CLKFB, D1_data_out, , LB1L1, , , , );

--GE1_td_shift[5] is std_1c20:inst|jtag_uart:the_jtag_uart|alt_jtag_atlantic:jtag_uart_alt_jtag_atlantic|td_shift[5]

--operation mode is normal

GE1_td_shift[5] = AMPP_FUNCTION(A1L5, GE1L53, GE1L63, GE1L61, !C1_CLR_SIGNAL, GE1L52);

--SD1_internal_jdo1[2] is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|internal_jdo1[2]

--operation mode is normal

SD1_internal_jdo1[2] = AMPP_FUNCTION(A1L8, SD1_sr[2], VCC, SD1L145);

--SE1_q_b[1] is std_1c20:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_w:the_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_jf21:auto_generated|a_dpfifo_ml21:dpfifo|dpram_j921:FIFOram|altsyncram_nll1:altsyncram1|q_b[1]

--RAM Block Operation Mode: Simple Dual-Port

--Port A Depth: 64, Port A Width: 1, Port B Depth: 64, Port B Width: 1

--Port A Logical Depth: 64, Port A Logical Width: 8, Port B Logical Depth: 64, Port B Logical Width: 8

--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered

SE1_q_b[1]_PORT_A_data_in = S1_M_st_data[1];

SE1_q_b[1]_PORT_A_data_in_reg = DFFE(SE1_q_b[1]_PORT_A_data_in, SE1_q_b[1]_clock_0, , , SE1_q_b[1]_clock_enable_0);

SE1_q_b[1]_PORT_A_address = BUS(QE2_safe_q[0], QE2_safe_q[1], QE2_safe_q[2], QE2_safe_q[3], QE2_safe_q[4], QE2_safe_q[5]);

SE1_q_b[1]_PORT_A_address_reg = DFFE(SE1_q_b[1]_PORT_A_address, SE1_q_b[1]_clock_0, , , SE1_q_b[1]_clock_enable_0);

SE1_q_b[1]_PORT_B_address = BUS(QE1_safe_q[0], QE1_safe_q[1], QE1_safe_q[2], QE1_safe_q[3], QE1_safe_q[4], QE1_safe_q[5]);

SE1_q_b[1]_PORT_B_address_reg = DFFE(SE1_q_b[1]_PORT_B_address, SE1_q_b[1]_clock_1, , , SE1_q_b[1]_clock_enable_1);

SE1_q_b[1]_PORT_A_write_enable = VCC;

SE1_q_b[1]_PORT_A_write_enable_reg = DFFE(SE1_q_b[1]_PORT_A_write_enable, SE1_q_b[1]_clock_0, , , SE1_q_b[1]_clock_enable_0);

SE1_q_b[1]_PORT_B_read_enable = VCC;

SE1_q_b[1]_PORT_B_read_enable_reg = DFFE(SE1_q_b[1]_PORT_B_read_enable, SE1_q_b[1]_clock_1, , , SE1_q_b[1]_clock_enable_1);

SE1_q_b[1]_clock_0 = QC2__clk0;

SE1_q_b[1]_clock_1 = QC2__clk0;

SE1_q_b[1]_clock_enable_0 = BB1_fifo_wr;

SE1_q_b[1]_clock_enable_1 = BB1_rd_wfifo;

SE1_q_b[1]_PORT_B_data_out = MEMORY(SE1_q_b[1]_PORT_A_data_in_reg, , SE1_q_b[1]_PORT_A_address_reg, SE1_q_b[1]_PORT_B_address_reg, SE1_q_b[1]_PORT_A_write_enable_reg, SE1_q_b[1]_PORT_B_read_enable_reg, , , SE1_q_b[1]_clock_0, SE1_q_b[1]_clock_1, SE1_q_b[1]_clock_enable_0, SE1_q_b[1]_clock_enable_1, , );

SE1_q_b[1] = SE1_q_b[1]_PORT_B_data_out[0];

--GE1_rdata[2] is std_1c20:inst|jtag_uart:the_jtag_uart|alt_jtag_atlantic:jtag_uart_alt_jtag_atlantic|rdata[2]

--operation mode is normal

GE1_rdata[2] = AMPP_FUNCTION(QC2__clk0, SE1_q_b[2], F1_data_out, GE1L18);

--GE1L60 is std_1c20:inst|jtag_uart:the_jtag_uart|alt_jtag_atlantic:jtag_uart_alt_jtag_atlantic|td_shift[9]~3568

--operation mode is normal

GE1L60 = AMPP_FUNCTION(GE1_rdata[2], GE1_td_shift[5], GE1_count[9]);

--GE1_count[5] is std_1c20:inst|jtag_uart:the_jtag_uart|alt_jtag_atlantic:jtag_uart_alt_jtag_atlantic|count[5]

--operation mode is normal

GE1_count[5] = AMPP_FUNCTION(A1L5, FF1_state[4], GE1_count[4], !C1_CLR_SIGNAL, GE1L52);

--WE1_stage_6 is std_1c20:inst|sdram_s1_arbitrator:the_sdram_s1|rdv_fifo_for_cpu_instruction_master_to_sdram_s1_module:rdv_fifo_for_cpu_instruction_master_to_sdram_s1|stage_6

--operation mode is normal

WE1_stage_6_lut_out = NB1L18;

WE1_stage_6 = DFFEAS(WE1_stage_6_lut_out, QC2__clk0, VCC, , WE1L20, , , , );

--WE1_full_6 is std_1c20:inst|sdram_s1_arbitrator:the_sdram_s1|rdv_fifo_for_cpu_instruction_master_to_sdram_s1_module:rdv_fifo_for_cpu_instruction_master_to_sdram_s1|full_6

--operation mode is normal

WE1_full_6_lut_out = WE1_full_5 & (NB1L27 # !KB1_za_valid);

WE1_full_6 = DFFEAS(WE1_full_6_lut_out, QC2__clk0, F1_data_out, , VE1L13, , , , );

--WE1L21 is std_1c20:inst|sdram_s1_arbitrator:the_sdram_s1|rdv_fifo_for_cpu_instruction_master_to_sdram_s1_module:rdv_fifo_for_cpu_instruction_master_to_sdram_s1|process2~1

--operation mode is normal

WE1L21 = KB1_za_valid # NB1L27 & (!WE1_full_5);

--NC1_internal_slave_read_request is std_1c20:inst|clock_1:the_clock_1|clock_1_slave_FSM:slave_FSM|internal_slave_read_request

--operation mode is normal

NC1_internal_slave_read_request_lut_out = NC1_internal_slave_read_request $ (N1L1 & NC1L2);

NC1_internal_slave_read_request = DFFEAS(NC1_internal_slave_read_request_lut_out, QC2__clk0, F1_data_out, , , , , , );

--NC1_internal_slave_write_request is std_1c20:inst|clock_1:the_clock_1|clock_1_slave_FSM:slave_FSM|internal_slave_write_request

--operation mode is normal

NC1_internal_slave_write_request_lut_out = NC1_internal_slave_write_request $ (NC1L4 & NC1L2);

NC1_internal_slave_write_request = DFFEAS(NC1_internal_slave_write_request_lut_out, QC2__clk0, F1_data_out, , , , , , );

--EC1_internal_slave_read_request is std_1c20:inst|clock_0:the_clock_0|clock_0_slave_FSM:slave_FSM|internal_slave_read_request

--operation mode is normal

EC1_internal_slave_read_request_lut_out = EC1_internal_slave_read_request $ (K1L1 & EC1L2);

EC1_internal_slave_read_request = DFFEAS(EC1_internal_slave_read_request_lut_out, QC2__clk0, F1_data_out, , , , , , );

--EC1_internal_slave_write_request is std_1c20:inst|clock_0:the_clock_0|clock_0_slave_FSM:slave_FSM|internal_slave_write_request

--operation mode is normal

EC1_internal_slave_write_request_lut_out = EC1_internal_slave_write_request $ (EC1L4 & EC1L2);

EC1_internal_slave_write_request = DFFEAS(EC1_internal_slave_write_request_lut_out, QC2__clk0, F1_data_out, , , , , , );

--VE1_stage_6 is std_1c20:inst|sdram_s1_arbitrator:the_sdram_s1|rdv_fifo_for_cpu_data_master_to_sdram_s1_module:rdv_fifo_for_cpu_data_master_to_sdram_s1|stage_6

--operation mode is normal

VE1_stage_6_lut_out = NB1L14;

VE1_stage_6 = DFFEAS(VE1_stage_6_lut_out, QC2__clk0, VCC, , WE1L20, , , , );

--YE1L38 is std_1c20:inst|uart1:the_uart1|uart1_rx:the_uart1_rx|Equal0~172

--operation mode is normal

YE1L38 = YE1L36 & YE1L37 & (!YE1_baud_rate_counter[8]);

--YE1L2 is std_1c20:inst|uart1:the_uart1|uart1_rx:the_uart1_rx|Add0~168

--operation mode is arithmetic

YE1L2_carry_eqn = YE1L18;

YE1L2 = YE1_baud_rate_counter[1] $ (!YE1L2_carry_eqn);

--YE1L3 is std_1c20:inst|uart1:the_uart1|uart1_rx:the_uart1_rx|Add0~169

--operation mode is arithmetic

YE1L3 = CARRY(!YE1_baud_rate_counter[1] & (!YE1L18));

--YE1L4 is std_1c20:inst|uart1:the_uart1|uart1_rx:the_uart1_rx|Add0~170

--operation mode is arithmetic

YE1L4_carry_eqn = YE1L3;

YE1L4 = YE1_baud_rate_counter[2] $ (YE1L4_carry_eqn);

--YE1L5 is std_1c20:inst|uart1:the_uart1|uart1_rx:the_uart1_rx|Add0~171

--operation mode is arithmetic

YE1L5 = CARRY(YE1_baud_rate_counter[2] # !YE1L3);

--YE1L6 is std_1c20:inst|uart1:the_uart1|uart1_rx:the_uart1_rx|Add0~172

--operation mode is arithmetic

YE1L6_carry_eqn = YE1L5;

YE1L6 = YE1_baud_rate_counter[3] $ (!YE1L6_carry_eqn);

--YE1L7 is std_1c20:inst|uart1:the_uart1|uart1_rx:the_uart1_rx|Add0~173

--operation mode is arithmetic

YE1L7 = CARRY(!YE1_baud_rate_counter[3] & (!YE1L5));

--YE1L8 is std_1c20:inst|uart1:the_uart1|uart1_rx:the_uart1_rx|Add0~174

--operation mode is arithmetic

YE1L8_carry_eqn = YE1L7;

YE1L8 = YE1_baud_rate_counter[4] $ (YE1L8_carry_eqn);

--YE1L9 is std_1c20:inst|uart1:the_uart1|uart1_rx:the_uart1_rx|Add0~175

--operation mode is arithmetic

YE1L9 = CARRY(YE1_baud_rate_counter[4] # !YE1L7);

--YE1L10 is std_1c20:inst|uart1:the_uart1|uart1_rx:the_uart1_rx|Add0~176

--operation mode is arithmetic

YE1L10_carry_eqn = YE1L9;

YE1L10 = YE1_baud_rate_counter[5] $ (!YE1L10_carry_eqn);

--YE1L11 is std_1c20:inst|uart1:the_uart1|uart1_rx:the_uart1_rx|Add0~177

--operation mode is arithmetic

YE1L11 = CARRY(!YE1_baud_rate_counter[5] & (!YE1L9));

--YE1L12 is std_1c20:inst|uart1:the_uart1|uart1_rx:the_uart1_rx|Add0~178

--operation mode is arithmetic

YE1L12_carry_eqn = YE1L11;

YE1L12 = YE1_baud_rate_counter[6] $ (YE1L12_carry_eqn);

--YE1L13 is std_1c20:inst|uart1:the_uart1|uart1_rx:the_uart1_rx|Add0~179

--operation mode is arithmetic

YE1L13 = CARRY(YE1_baud_rate_counter[6] # !YE1L11);

--YE1L14 is std_1c20:inst|uart1:the_uart1|uart1_rx:the_uart1_rx|Add0~180

--operation mode is arithmetic

YE1L14_carry_eqn = YE1L13;

YE1L14 = YE1_baud_rate_counter[7] $ (!YE1L14_carry_eqn);

--YE1L15 is std_1c20:inst|uart1:the_uart1|uart1_rx:the_uart1_rx|Add0~181

--operation mode is arithmetic

YE1L15 = CARRY(!YE1_baud_rate_counter[7] & (!YE1L13));

--YE1L16 is std_1c20:inst|uart1:the_uart1|uart1_rx:the_uart1_rx|Add0~182

--operation mode is normal

YE1L16_carry_eqn = YE1L15;

YE1L16 = YE1_baud_rate_counter[8] $ (YE1L16_carry_eqn);

--M1_slave_writedata_d1[2] is std_1c20:inst|clock_1:the_clock_1|slave_writedata_d1[2]

--operation mode is normal

M1_slave_writedata_d1[2]_lut_out = S1_M_st_data[2];

M1_slave_writedata_d1[2] = DFFEAS(M1_slave_writedata_d1[2]_lut_out, QC2__clk0, F1_data_out, , , , , , );

--M1_slave_nativeaddress_d1[1] is std_1c20:inst|clock_1:the_clock_1|slave_nativeaddress_d1[1]

--operation mode is normal

M1_slave_nativeaddress_d1[1]_lut_out = S1_M_alu_result[3];

M1_slave_nativeaddress_d1[1] = DFFEAS(M1_slave_nativeaddress_d1[1]_lut_out, QC2__clk0, F1_data_out, , , , , , );

--M1_slave_nativeaddress_d1[2] is std_1c20:inst|clock_1:the_clock_1|slave_nativeaddress_d1[2]

--operation mode is normal

M1_slave_nativeaddress_d1[2]_lut_out = S1_M_alu_result[4];

M1_slave_nativeaddress_d1[2] = DFFEAS(M1_slave_nativeaddress_d1[2]_lut_out, QC2__clk0, F1_data_out, , , , , , );

--J1_slave_writedata_d1[2] is std_1c20:inst|clock_0:the_clock_0|slave_writedata_d1[2]

--operation mode is normal

J1_slave_writedata_d1[2]_lut_out = S1_M_st_data[2];

J1_slave_writedata_d1[2] = DFFEAS(J1_slave_writedata_d1[2]_lut_out, QC2__clk0, F1_data_out, , , , , , );

--J1_slave_nativeaddress_d1[1] is std_1c20:inst|clock_0:the_clock_0|slave_nativeaddress_d1[1]

--operation mode is normal

J1_slave_nativeaddress_d1[1]_lut_out = S1_M_alu_result[3];

J1_slave_nativeaddress_d1[1] = DFFEAS(J1_slave_nativeaddress_d1[1]_lut_out, QC2__clk0, F1_data_out, , , , , , );

--J1_slave_nativeaddress_d1[2] is std_1c20:inst|clock_0:the_clock_0|slave_nativeaddress_d1[2]

--operation mode is normal

J1_slave_nativeaddress_d1[2]_lut_out = S1_M_alu_result[4];

J1_slave_nativeaddress_d1[2] = DFFEAS(J1_slave_nativeaddress_d1[2]_lut_out, QC2__clk0, F1_data_out, , , , , , );

--SE1_q_b[4] is std_1c20:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_w:the_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_jf21:auto_generated|a_dpfifo_ml21:dpfifo|dpram_j921:FIFOram|altsyncram_nll1:altsyncram1|q_b[4]

--RAM Block Operation Mode: Simple Dual-Port

--Port A Depth: 64, Port A Width: 1, Port B Depth: 64, Port B Width: 1

--Port A Logical Depth: 64, Port A Logical Width: 8, Port B Logical Depth: 64, Port B Logical Width: 8

--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered

SE1_q_b[4]_PORT_A_data_in = S1_M_st_data[4];

SE1_q_b[4]_PORT_A_data_in_reg = DFFE(SE1_q_b[4]_PORT_A_data_in, SE1_q_b[4]_clock_0, , , SE1_q_b[4]_clock_enable_0);

SE1_q_b[4]_PORT_A_address = BUS(QE2_safe_q[0], QE2_safe_q[1], QE2_safe_q[2], QE2_safe_q[3], QE2_safe_q[4], QE2_safe_q[5]);

SE1_q_b[4]_PORT_A_address_reg = DFFE(SE1_q_b[4]_PORT_A_address, SE1_q_b[4]_clock_0, , , SE1_q_b[4]_clock_enable_0);

SE1_q_b[4]_PORT_B_address = BUS(QE1_safe_q[0], QE1_safe_q[1], QE1_safe_q[2], QE1_safe_q[3], QE1_safe_q[4], QE1_safe_q[5]);

SE1_q_b[4]_PORT_B_address_reg = DFFE(SE1_q_b[4]_PORT_B_address, SE1_q_b[4]_clock_1, , , SE1_q_b[4]_clock_enable_1);

SE1_q_b[4]_PORT_A_write_enable = VCC;

SE1_q_b[4]_PORT_A_write_enable_reg = DFFE(SE1_q_b[4]_PORT_A_write_enable, SE1_q_b[4]_clock_0, , , SE1_q_b[4]_clock_enable_0);

SE1_q_b[4]_PORT_B_read_enable = VCC;

SE1_q_b[4]_PORT_B_read_enable_reg = DFFE(SE1_q_b[4]_PORT_B_read_enable, SE1_q_b[4]_clock_1, , , SE1_q_b[4]_clock_enable_1);

SE1_q_b[4]_clock_0 = QC2__clk0;

SE1_q_b[4]_clock_1 = QC2__clk0;

SE1_q_b[4]_clock_enable_0 = BB1_fifo_wr;

SE1_q_b[4]_clock_enable_1 = BB1_rd_wfifo;

SE1_q_b[4]_PORT_B_data_out = MEMORY(SE1_q_b[4]_PORT_A_data_in_reg, , SE1_q_b[4]_PORT_A_address_reg, SE1_q_b[4]_PORT_B_address_reg, SE1_q_b[4]_PORT_A_write_enable_reg, SE1_q_b[4]_PORT_B_read_enable_reg, , , SE1_q_b[4]_clock_0, SE1_q_b[4]_clock_1, SE1_q_b[4]_clock_enable_0, SE1_q_b[4]_clock_enable_1, , );

SE1_q_b[4] = SE1_q_b[4]_PORT_B_data_out[0];

--JD1L9 is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_debug:the_cpu_nios2_oci_debug|internal_resetlatch~185

--operation mode is normal

JD1L9 = AMPP_FUNCTION(C1_CLR_SIGNAL, F1_data_out, JD1_internal_resetlatch);

--M1_slave_writedata_d1[3] is std_1c20:inst|clock_1:the_clock_1|slave_writedata_d1[3]

--operation mode is normal

M1_slave_writedata_d1[3]_lut_out = S1_M_st_data[3];

M1_slave_writedata_d1[3] = DFFEAS(M1_slave_writedata_d1[3]_lut_out, QC2__clk0, F1_data_out, , , , , , );

--J1_slave_writedata_d1[3] is std_1c20:inst|clock_0:the_clock_0|slave_writedata_d1[3]

--operation mode is normal

J1_slave_writedata_d1[3]_lut_out = S1_M_st_data[3];

J1_slave_writedata_d1[3] = DFFEAS(J1_slave_writedata_d1[3]_lut_out, QC2__clk0, F1_data_out, , , , , , );

--SE1_q_b[5] is std_1c20:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_w:the_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_jf21:auto_generated|a_dpfifo_ml21:dpfifo|dpram_j921:FIFOram|altsyncram_nll1:altsyncram1|q_b[5]

--RAM Block Operation Mode: Simple Dual-Port

--Port A Depth: 64, Port A Width: 1, Port B Depth: 64, Port B Width: 1

--Port A Logical Depth: 64, Port A Logical Width: 8, Port B Logical Depth: 64, Port B Logical Width: 8

--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered

SE1_q_b[5]_PORT_A_data_in = S1_M_st_data[5];

SE1_q_b[5]_PORT_A_data_in_reg = DFFE(SE1_q_b[5]_PORT_A_data_in, SE1_q_b[5]_clock_0, , , SE1_q_b[5]_clock_enable_0);

SE1_q_b[5]_PORT_A_address = BUS(QE2_safe_q[0], QE2_safe_q[1], QE2_safe_q[2], QE2_safe_q[3], QE2_safe_q[4], QE2_safe_q[5]);

SE1_q_b[5]_PORT_A_address_reg = DFFE(SE1_q_b[5]_PORT_A_address, SE1_q_b[5]_clock_0, , , SE1_q_b[5]_clock_enable_0);

SE1_q_b[5]_PORT_B_address = BUS(QE1_safe_q[0], QE1_safe_q[1], QE1_safe_q[2], QE1_safe_q[3], QE1_safe_q[4], QE1_safe_q[5]);

SE1_q_b[5]_PORT_B_address_reg = DFFE(SE1_q_b[5]_PORT_B_address, SE1_q_b[5]_clock_1, , , SE1_q_b[5]_clock_enable_1);

SE1_q_b[5]_PORT_A_write_enable = VCC;

SE1_q_b[5]_PORT_A_write_enable_reg = DFFE(SE1_q_b[5]_PORT_A_write_enable, SE1_q_b[5]_clock_0, , , SE1_q_b[5]_clock_enable_0);

SE1_q_b[5]_PORT_B_read_enable = VCC;

SE1_q_b[5]_PORT_B_read_enable_reg = DFFE(SE1_q_b[5]_PORT_B_read_enable, SE1_q_b[5]_clock_1, , , SE1_q_b[5]_clock_enable_1);

SE1_q_b[5]_clock_0 = QC2__clk0;

SE1_q_b[5]_clock_1 = QC2__clk0;

SE1_q_b[5]_clock_enable_0 = BB1_fifo_wr;

SE1_q_b[5]_clock_enable_1 = BB1_rd_wfifo;

SE1_q_b[5]_PORT_B_data_out = MEMORY(SE1_q_b[5]_PORT_A_data_in_reg, , SE1_q_b[5]_PORT_A_address_reg, SE1_q_b[5]_PORT_B_address_reg, SE1_q_b[5]_PORT_A_write_enable_reg, SE1_q_b[5]_PORT_B_read_enable_reg, , , SE1_q_b[5]_clock_0, SE1_q_b[5]_clock_1, SE1_q_b[5]_clock_enable_0, SE1_q_b[5]_clock_enable_1, , );

SE1_q_b[5] = SE1_q_b[5]_PORT_B_data_out[0];

--XC1L13 is std_1c20:inst|cpu:the_cpu|cpu_test_bench:the_cpu_test_bench|Add0~571

--operation mode is arithmetic

XC1L13 = AMPP_FUNCTION(S1L595, S1L661, XC1L15);

--M1_slave_writedata_d1[15] is std_1c20:inst|clock_1:the_clock_1|slave_writedata_d1[15]

--operation mode is normal

M1_slave_writedata_d1[15]_lut_out = S1_M_st_data[15];

M1_slave_writedata_d1[15] = DFFEAS(M1_slave_writedata_d1[15]_lut_out, QC2__clk0, F1_data_out, , , , , , );

--J1_slave_writedata_d1[15] is std_1c20:inst|clock_0:the_clock_0|slave_writedata_d1[15]

--operation mode is normal

J1_slave_writedata_d1[15]_lut_out = S1_M_st_data[15];

J1_slave_writedata_d1[15] = DFFEAS(J1_slave_writedata_d1[15]_lut_out, QC2__clk0, F1_data_out, , , , , , );

--M1_slave_writedata_d1[7] is std_1c20:inst|clock_1:the_clock_1|slave_writedata_d1[7]

--operation mode is normal

M1_slave_writedata_d1[7]_lut_out = S1_M_st_data[7];

M1_slave_writedata_d1[7] = DFFEAS(M1_slave_writedata_d1[7]_lut_out, QC2__clk0, F1_data_out, , , , , , );

--J1_slave_writedata_d1[7] is std_1c20:inst|clock_0:the_clock_0|slave_writedata_d1[7]

--operation mode is normal

J1_slave_writedata_d1[7]_lut_out = S1_M_st_data[7];

J1_slave_writedata_d1[7] = DFFEAS(J1_slave_writedata_d1[7]_lut_out, QC2__clk0, F1_data_out, , , , , , );

--M1_slave_writedata_d1[14] is std_1c20:inst|clock_1:the_clock_1|slave_writedata_d1[14]

--operation mode is normal

M1_slave_writedata_d1[14]_lut_out = S1_M_st_data[14];

M1_slave_writedata_d1[14] = DFFEAS(M1_slave_writedata_d1[14]_lut_out, QC2__clk0, F1_data_out, , , , , , );

--J1_slave_writedata_d1[14] is std_1c20:inst|clock_0:the_clock_0|slave_writedata_d1[14]

--operation mode is normal

J1_slave_writedata_d1[14]_lut_out = S1_M_st_data[14];

J1_slave_writedata_d1[14] = DFFEAS(J1_slave_writedata_d1[14]_lut_out, QC2__clk0, F1_data_out, , , , , , );

--M1_slave_writedata_d1[13] is std_1c20:inst|clock_1:the_clock_1|slave_writedata_d1[13]

--operation mode is normal

M1_slave_writedata_d1[13]_lut_out = S1_M_st_data[13];

M1_slave_writedata_d1[13] = DFFEAS(M1_slave_writedata_d1[13]_lut_out, QC2__clk0, F1_data_out, , , , , , );

--J1_slave_writedata_d1[13] is std_1c20:inst|clock_0:the_clock_0|slave_writedata_d1[13]

--operation mode is normal

J1_slave_writedata_d1[13]_lut_out = S1_M_st_data[13];

J1_slave_writedata_d1[13] = DFFEAS(J1_slave_writedata_d1[13]_lut_out, QC2__clk0, F1_data_out, , , , , , );

--M1_slave_writedata_d1[12] is std_1c20:inst|clock_1:the_clock_1|slave_writedata_d1[12]

--operation mode is normal

M1_slave_writedata_d1[12]_lut_out = S1_M_st_data[12];

M1_slave_writedata_d1[12] = DFFEAS(M1_slave_writedata_d1[12]_lut_out, QC2__clk0, F1_data_out, , , , , , );

--J1_slave_writedata_d1[12] is std_1c20:inst|clock_0:the_clock_0|slave_writedata_d1[12]

--operation mode is normal

J1_slave_writedata_d1[12]_lut_out = S1_M_st_data[12];

J1_slave_writedata_d1[12] = DFFEAS(J1_slave_writedata_d1[12]_lut_out, QC2__clk0, F1_data_out, , , , , , );

--J1_slave_writedata_d1[11] is std_1c20:inst|clock_0:the_clock_0|slave_writedata_d1[11]

--operation mode is normal

J1_slave_writedata_d1[11]_lut_out = S1_M_st_data[11];

J1_slave_writedata_d1[11] = DFFEAS(J1_slave_writedata_d1[11]_lut_out, QC2__clk0, F1_data_out, , , , , , );

--M1_slave_writedata_d1[11] is std_1c20:inst|clock_1:the_clock_1|slave_writedata_d1[11]

--operation mode is normal

M1_slave_writedata_d1[11]_lut_out = S1_M_st_data[11];

M1_slave_writedata_d1[11] = DFFEAS(M1_slave_writedata_d1[11]_lut_out, QC2__clk0, F1_data_out, , , , , , );

--M1_slave_writedata_d1[10] is std_1c20:inst|clock_1:the_clock_1|slave_writedata_d1[10]

--operation mode is normal

M1_slave_writedata_d1[10]_lut_out = S1_M_st_data[10];

M1_slave_writedata_d1[10] = DFFEAS(M1_slave_writedata_d1[10]_lut_out, QC2__clk0, F1_data_out, , , , , , );

--J1_slave_writedata_d1[10] is std_1c20:inst|clock_0:the_clock_0|slave_writedata_d1[10]

--operation mode is normal

J1_slave_writedata_d1[10]_lut_out = S1_M_st_data[10];

J1_slave_writedata_d1[10] = DFFEAS(J1_slave_writedata_d1[10]_lut_out, QC2__clk0, F1_data_out, , , , , , );

--EE1_internal_data0out is std_1c20:inst|epcs_controller:the_epcs_controller|tornado_epcs_controller_atom:the_tornado_epcs_controller_atom|internal_data0out

EE1_internal_data0out = ASMIBLOCK(DE1_SCLK_reg, DE1L180, DE1_shift_reg[7], GND).DATA0OUT;

--M1_slave_writedata_d1[9] is std_1c20:inst|clock_1:the_clock_1|slave_writedata_d1[9]

--operation mode is normal

M1_slave_writedata_d1[9]_lut_out = S1_M_st_data[9];

M1_slave_writedata_d1[9] = DFFEAS(M1_slave_writedata_d1[9]_lut_out, QC2__clk0, F1_data_out, , , , , , );

--J1_slave_writedata_d1[9] is std_1c20:inst|clock_0:the_clock_0|slave_writedata_d1[9]

--operation mode is normal

J1_slave_writedata_d1[9]_lut_out = S1_M_st_data[9];

J1_slave_writedata_d1[9] = DFFEAS(J1_slave_writedata_d1[9]_lut_out, QC2__clk0, F1_data_out, , , , , , );

--M1_slave_writedata_d1[8] is std_1c20:inst|clock_1:the_clock_1|slave_writedata_d1[8]

--operation mode is normal

M1_slave_writedata_d1[8]_lut_out = S1_M_st_data[8];

M1_slave_writedata_d1[8] = DFFEAS(M1_slave_writedata_d1[8]_lut_out, QC2__clk0, F1_data_out, , , , , , );

--J1_slave_writedata_d1[8] is std_1c20:inst|clock_0:the_clock_0|slave_writedata_d1[8]

--operation mode is normal

J1_slave_writedata_d1[8]_lut_out = S1_M_st_data[8];

J1_slave_writedata_d1[8] = DFFEAS(J1_slave_writedata_d1[8]_lut_out, QC2__clk0, F1_data_out, , , , , , );

--M1_slave_writedata_d1[6] is std_1c20:inst|clock_1:the_clock_1|slave_writedata_d1[6]

--operation mode is normal

M1_slave_writedata_d1[6]_lut_out = S1_M_st_data[6];

M1_slave_writedata_d1[6] = DFFEAS(M1_slave_writedata_d1[6]_lut_out, QC2__clk0, F1_data_out, , , , , , );

--J1_slave_writedata_d1[6] is std_1c20:inst|clock_0:the_clock_0|slave_writedata_d1[6]

--operation mode is normal

J1_slave_writedata_d1[6]_lut_out = S1_M_st_data[6];

J1_slave_writedata_d1[6] = DFFEAS(J1_slave_writedata_d1[6]_lut_out, QC2__clk0, F1_data_out, , , , , , );

--M1_slave_writedata_d1[4] is std_1c20:inst|clock_1:the_clock_1|slave_writedata_d1[4]

--operation mode is normal

M1_slave_writedata_d1[4]_lut_out = S1_M_st_data[4];

M1_slave_writedata_d1[4] = DFFEAS(M1_slave_writedata_d1[4]_lut_out, QC2__clk0, F1_data_out, , , , , , );

--J1_slave_writedata_d1[4] is std_1c20:inst|clock_0:the_clock_0|slave_writedata_d1[4]

--operation mode is normal

J1_slave_writedata_d1[4]_lut_out = S1_M_st_data[4];

J1_slave_writedata_d1[4] = DFFEAS(J1_slave_writedata_d1[4]_lut_out, QC2__clk0, F1_data_out, , , , , , );

--SE1_q_b[6] is std_1c20:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_w:the_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_jf21:auto_generated|a_dpfifo_ml21:dpfifo|dpram_j921:FIFOram|altsyncram_nll1:altsyncram1|q_b[6]

--RAM Block Operation Mode: Simple Dual-Port

--Port A Depth: 64, Port A Width: 1, Port B Depth: 64, Port B Width: 1

--Port A Logical Depth: 64, Port A Logical Width: 8, Port B Logical Depth: 64, Port B Logical Width: 8

--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered

SE1_q_b[6]_PORT_A_data_in = S1_M_st_data[6];

SE1_q_b[6]_PORT_A_data_in_reg = DFFE(SE1_q_b[6]_PORT_A_data_in, SE1_q_b[6]_clock_0, , , SE1_q_b[6]_clock_enable_0);

SE1_q_b[6]_PORT_A_address = BUS(QE2_safe_q[0], QE2_safe_q[1], QE2_safe_q[2], QE2_safe_q[3], QE2_safe_q[4], QE2_safe_q[5]);

SE1_q_b[6]_PORT_A_address_reg = DFFE(SE1_q_b[6]_PORT_A_address, SE1_q_b[6]_clock_0, , , SE1_q_b[6]_clock_enable_0);

SE1_q_b[6]_PORT_B_address = BUS(QE1_safe_q[0], QE1_safe_q[1], QE1_safe_q[2], QE1_safe_q[3], QE1_safe_q[4], QE1_safe_q[5]);

SE1_q_b[6]_PORT_B_address_reg = DFFE(SE1_q_b[6]_PORT_B_address, SE1_q_b[6]_clock_1, , , SE1_q_b[6]_clock_enable_1);

SE1_q_b[6]_PORT_A_write_enable = VCC;

SE1_q_b[6]_PORT_A_write_enable_reg = DFFE(SE1_q_b[6]_PORT_A_write_enable, SE1_q_b[6]_clock_0, , , SE1_q_b[6]_clock_enable_0);

SE1_q_b[6]_PORT_B_read_enable = VCC;

SE1_q_b[6]_PORT_B_read_enable_reg = DFFE(SE1_q_b[6]_PORT_B_read_enable, SE1_q_b[6]_clock_1, , , SE1_q_b[6]_clock_enable_1);

SE1_q_b[6]_clock_0 = QC2__clk0;

SE1_q_b[6]_clock_1 = QC2__clk0;

SE1_q_b[6]_clock_enable_0 = BB1_fifo_wr;

SE1_q_b[6]_clock_enable_1 = BB1_rd_wfifo;

SE1_q_b[6]_PORT_B_data_out = MEMORY(SE1_q_b[6]_PORT_A_data_in_reg, , SE1_q_b[6]_PORT_A_address_reg, SE1_q_b[6]_PORT_B_address_reg, SE1_q_b[6]_PORT_A_write_enable_reg, SE1_q_b[6]_PORT_B_read_enable_reg, , , SE1_q_b[6]_clock_0, SE1_q_b[6]_clock_1, SE1_q_b[6]_clock_enable_0, SE1_q_b[6]_clock_enable_1, , );

SE1_q_b[6] = SE1_q_b[6]_PORT_B_data_out[0];

--M1_slave_writedata_d1[5] is std_1c20:inst|clock_1:the_clock_1|slave_writedata_d1[5]

--operation mode is normal

M1_slave_writedata_d1[5]_lut_out = S1_M_st_data[5];

M1_slave_writedata_d1[5] = DFFEAS(M1_slave_writedata_d1[5]_lut_out, QC2__clk0, F1_data_out, , , , , , );

--J1_slave_writedata_d1[5] is std_1c20:inst|clock_0:the_clock_0|slave_writedata_d1[5]

--operation mode is normal

J1_slave_writedata_d1[5]_lut_out = S1_M_st_data[5];

J1_slave_writedata_d1[5] = DFFEAS(J1_slave_writedata_d1[5]_lut_out, QC2__clk0, F1_data_out, , , , , , );

--M1_master_writedata[0] is std_1c20:inst|clock_1:the_clock_1|master_writedata[0]

--operation mode is normal

M1_master_writedata[0]_lut_out = M1_slave_writedata_d1[0];

M1_master_writedata[0] = DFFEAS(M1_master_writedata[0]_lut_out, PLD_CLOCKINPUT[1], E1_data_out, , , , , , );

--J1_master_writedata[0] is std_1c20:inst|clock_0:the_clock_0|master_writedata[0]

--operation mode is normal

J1_master_writedata[0]_lut_out = J1_slave_writedata_d1[0];

J1_master_writedata[0] = DFFEAS(J1_master_writedata[0]_lut_out, PLD_CLKFB, D1_data_out, , , , , , );

--M1_master_writedata[1] is std_1c20:inst|clock_1:the_clock_1|master_writedata[1]

--operation mode is normal

M1_master_writedata[1]_lut_out = M1_slave_writedata_d1[1];

M1_master_writedata[1] = DFFEAS(M1_master_writedata[1]_lut_out, PLD_CLOCKINPUT[1], E1_data_out, , , , , , );

--J1_master_writedata[1] is std_1c20:inst|clock_0:the_clock_0|master_writedata[1]

--operation mode is normal

J1_master_writedata[1]_lut_out = J1_slave_writedata_d1[1];

J1_master_writedata[1] = DFFEAS(J1_master_writedata[1]_lut_out, PLD_CLKFB, D1_data_out, , , , , , );

--GE1_rdata[3] is std_1c20:inst|jtag_uart:the_jtag_uart|alt_jtag_atlantic:jtag_uart_alt_jtag_atlantic|rdata[3]

--operation mode is normal

GE1_rdata[3] = AMPP_FUNCTION(QC2__clk0, SE1_q_b[3], F1_data_out, GE1L18);

--GE1L61 is std_1c20:inst|jtag_uart:the_jtag_uart|alt_jtag_atlantic:jtag_uart_alt_jtag_atlantic|td_shift[9]~3571

--operation mode is normal

GE1L61 = AMPP_FUNCTION(GE1_rdata[3], GE1_td_shift[6], GE1_count[9]);

--SE1_q_b[2] is std_1c20:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_w:the_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_jf21:auto_generated|a_dpfifo_ml21:dpfifo|dpram_j921:FIFOram|altsyncram_nll1:altsyncram1|q_b[2]

--RAM Block Operation Mode: Simple Dual-Port

--Port A Depth: 64, Port A Width: 1, Port B Depth: 64, Port B Width: 1

--Port A Logical Depth: 64, Port A Logical Width: 8, Port B Logical Depth: 64, Port B Logical Width: 8

--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered

SE1_q_b[2]_PORT_A_data_in = S1_M_st_data[2];

SE1_q_b[2]_PORT_A_data_in_reg = DFFE(SE1_q_b[2]_PORT_A_data_in, SE1_q_b[2]_clock_0, , , SE1_q_b[2]_clock_enable_0);

SE1_q_b[2]_PORT_A_address = BUS(QE2_safe_q[0], QE2_safe_q[1], QE2_safe_q[2], QE2_safe_q[3], QE2_safe_q[4], QE2_safe_q[5]);

SE1_q_b[2]_PORT_A_address_reg = DFFE(SE1_q_b[2]_PORT_A_address, SE1_q_b[2]_clock_0, , , SE1_q_b[2]_clock_enable_0);

SE1_q_b[2]_PORT_B_address = BUS(QE1_safe_q[0], QE1_safe_q[1], QE1_safe_q[2], QE1_safe_q[3], QE1_safe_q[4], QE1_safe_q[5]);

SE1_q_b[2]_PORT_B_address_reg = DFFE(SE1_q_b[2]_PORT_B_address, SE1_q_b[2]_clock_1, , , SE1_q_b[2]_clock_enable_1);

SE1_q_b[2]_PORT_A_write_enable = VCC;

SE1_q_b[2]_PORT_A_write_enable_reg = DFFE(SE1_q_b[2]_PORT_A_write_enable, SE1_q_b[2]_clock_0, , , SE1_q_b[2]_clock_enable_0);

SE1_q_b[2]_PORT_B_read_enable = VCC;

SE1_q_b[2]_PORT_B_read_enable_reg = DFFE(SE1_q_b[2]_PORT_B_read_enable, SE1_q_b[2]_clock_1, , , SE1_q_b[2]_clock_enable_1);

SE1_q_b[2]_clock_0 = QC2__clk0;

SE1_q_b[2]_clock_1 = QC2__clk0;

SE1_q_b[2]_clock_enable_0 = BB1_fifo_wr;

SE1_q_b[2]_clock_enable_1 = BB1_rd_wfifo;

SE1_q_b[2]_PORT_B_data_out = MEMORY(SE1_q_b[2]_PORT_A_data_in_reg, , SE1_q_b[2]_PORT_A_address_reg, SE1_q_b[2]_PORT_B_address_reg, SE1_q_b[2]_PORT_A_write_enable_reg, SE1_q_b[2]_PORT_B_read_enable_reg, , , SE1_q_b[2]_clock_0, SE1_q_b[2]_clock_1, SE1_q_b[2]_clock_enable_0, SE1_q_b[2]_clock_enable_1, , );

SE1_q_b[2] = SE1_q_b[2]_PORT_B_data_out[0];

--GE1_count[4] is std_1c20:inst|jtag_uart:the_jtag_uart|alt_jtag_atlantic:jtag_uart_alt_jtag_atlantic|count[4]

--operation mode is normal

GE1_count[4] = AMPP_FUNCTION(A1L5, FF1_state[4], GE1_count[3], !C1_CLR_SIGNAL, GE1L52);

--WE1L20 is std_1c20:inst|sdram_s1_arbitrator:the_sdram_s1|rdv_fifo_for_cpu_instruction_master_to_sdram_s1_module:rdv_fifo_for_cpu_instruction_master_to_sdram_s1|process0~1

--operation mode is normal

WE1L20 = KB1_za_valid # NB1L27 & (!WE1_full_6);

--NC1L2 is std_1c20:inst|clock_1:the_clock_1|clock_1_slave_FSM:slave_FSM|internal_slave_read_request~33

--operation mode is normal

NC1L2 = !NC1_slave_state[2] & !NC1_slave_state[1] & !NC1_slave_state[0];

--EC1L2 is std_1c20:inst|clock_0:the_clock_0|clock_0_slave_FSM:slave_FSM|internal_slave_read_request~33

--operation mode is normal

EC1L2 = !EC1_slave_state[2] & !EC1_slave_state[1] & !EC1_slave_state[0];

--YE1L18 is std_1c20:inst|uart1:the_uart1|uart1_rx:the_uart1_rx|Add0~185

--operation mode is arithmetic

YE1L18 = CARRY(YE1_baud_rate_counter[0]);

--XC1L15 is std_1c20:inst|cpu:the_cpu|cpu_test_bench:the_cpu_test_bench|Add0~573

--operation mode is arithmetic

XC1L15 = AMPP_FUNCTION(S1L594, S1L660, XC1L17);

--DE1L180 is std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|SS_n~16

--operation mode is normal

DE1L180 = DE1_epcs_slave_select_reg[0] # !DE1_SSO_reg & (!DE1_stateZero # !DE1_transmitting);

--M1_slave_writedata_d1[0] is std_1c20:inst|clock_1:the_clock_1|slave_writedata_d1[0]

--operation mode is normal

M1_slave_writedata_d1[0]_lut_out = S1_M_st_data[0];

M1_slave_writedata_d1[0] = DFFEAS(M1_slave_writedata_d1[0]_lut_out, QC2__clk0, F1_data_out, , , , , , );

--J1_slave_writedata_d1[0] is std_1c20:inst|clock_0:the_clock_0|slave_writedata_d1[0]

--operation mode is normal

J1_slave_writedata_d1[0]_lut_out = S1_M_st_data[0];

J1_slave_writedata_d1[0] = DFFEAS(J1_slave_writedata_d1[0]_lut_out, QC2__clk0, F1_data_out, , , , , , );

--M1_slave_writedata_d1[1] is std_1c20:inst|clock_1:the_clock_1|slave_writedata_d1[1]

--operation mode is normal

M1_slave_writedata_d1[1]_lut_out = S1_M_st_data[1];

M1_slave_writedata_d1[1] = DFFEAS(M1_slave_writedata_d1[1]_lut_out, QC2__clk0, F1_data_out, , , , , , );

--J1_slave_writedata_d1[1] is std_1c20:inst|clock_0:the_clock_0|slave_writedata_d1[1]

--operation mode is normal

J1_slave_writedata_d1[1]_lut_out = S1_M_st_data[1];

J1_slave_writedata_d1[1] = DFFEAS(J1_slave_writedata_d1[1]_lut_out, QC2__clk0, F1_data_out, , , , , , );

--SE1_q_b[3] is std_1c20:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_w:the_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_jf21:auto_generated|a_dpfifo_ml21:dpfifo|dpram_j921:FIFOram|altsyncram_nll1:altsyncram1|q_b[3]

--RAM Block Operation Mode: Simple Dual-Port

--Port A Depth: 64, Port A Width: 1, Port B Depth: 64, Port B Width: 1

--Port A Logical Depth: 64, Port A Logical Width: 8, Port B Logical Depth: 64, Port B Logical Width: 8

--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered

SE1_q_b[3]_PORT_A_data_in = S1_M_st_data[3];

SE1_q_b[3]_PORT_A_data_in_reg = DFFE(SE1_q_b[3]_PORT_A_data_in, SE1_q_b[3]_clock_0, , , SE1_q_b[3]_clock_enable_0);

SE1_q_b[3]_PORT_A_address = BUS(QE2_safe_q[0], QE2_safe_q[1], QE2_safe_q[2], QE2_safe_q[3], QE2_safe_q[4], QE2_safe_q[5]);

SE1_q_b[3]_PORT_A_address_reg = DFFE(SE1_q_b[3]_PORT_A_address, SE1_q_b[3]_clock_0, , , SE1_q_b[3]_clock_enable_0);

SE1_q_b[3]_PORT_B_address = BUS(QE1_safe_q[0], QE1_safe_q[1], QE1_safe_q[2], QE1_safe_q[3], QE1_safe_q[4], QE1_safe_q[5]);

SE1_q_b[3]_PORT_B_address_reg = DFFE(SE1_q_b[3]_PORT_B_address, SE1_q_b[3]_clock_1, , , SE1_q_b[3]_clock_enable_1);

SE1_q_b[3]_PORT_A_write_enable = VCC;

SE1_q_b[3]_PORT_A_write_enable_reg = DFFE(SE1_q_b[3]_PORT_A_write_enable, SE1_q_b[3]_clock_0, , , SE1_q_b[3]_clock_enable_0);

SE1_q_b[3]_PORT_B_read_enable = VCC;

SE1_q_b[3]_PORT_B_read_enable_reg = DFFE(SE1_q_b[3]_PORT_B_read_enable, SE1_q_b[3]_clock_1, , , SE1_q_b[3]_clock_enable_1);

SE1_q_b[3]_clock_0 = QC2__clk0;

SE1_q_b[3]_clock_1 = QC2__clk0;

SE1_q_b[3]_clock_enable_0 = BB1_fifo_wr;

SE1_q_b[3]_clock_enable_1 = BB1_rd_wfifo;

SE1_q_b[3]_PORT_B_data_out = MEMORY(SE1_q_b[3]_PORT_A_data_in_reg, , SE1_q_b[3]_PORT_A_address_reg, SE1_q_b[3]_PORT_B_address_reg, SE1_q_b[3]_PORT_A_write_enable_reg, SE1_q_b[3]_PORT_B_read_enable_reg, , , SE1_q_b[3]_clock_0, SE1_q_b[3]_clock_1, SE1_q_b[3]_clock_enable_0, SE1_q_b[3]_clock_enable_1, , );

SE1_q_b[3] = SE1_q_b[3]_PORT_B_data_out[0];

--GE1_count[3] is std_1c20:inst|jtag_uart:the_jtag_uart|alt_jtag_atlantic:jtag_uart_alt_jtag_atlantic|count[3]

--operation mode is normal

GE1_count[3] = AMPP_FUNCTION(A1L5, FF1_state[4], GE1_count[2], !C1_CLR_SIGNAL, GE1L52);

--XC1L17 is std_1c20:inst|cpu:the_cpu|cpu_test_bench:the_cpu_test_bench|Add0~575

--operation mode is arithmetic

XC1L17 = AMPP_FUNCTION(S1L593, S1L659, XC1L19);

--GE1_count[2] is std_1c20:inst|jtag_uart:the_jtag_uart|alt_jtag_atlantic:jtag_uart_alt_jtag_atlantic|count[2]

--operation mode is normal

GE1_count[2] = AMPP_FUNCTION(A1L5, FF1_state[4], GE1_count[1], !C1_CLR_SIGNAL, GE1L52);

--XC1L19 is std_1c20:inst|cpu:the_cpu|cpu_test_bench:the_cpu_test_bench|Add0~577

--operation mode is arithmetic

XC1L19 = AMPP_FUNCTION(S1L592, S1L658, XC1L21);

--XC1L21 is std_1c20:inst|cpu:the_cpu|cpu_test_bench:the_cpu_test_bench|Add0~579

--operation mode is arithmetic

XC1L21 = AMPP_FUNCTION(S1L591, S1L657, XC1L23);

--XC1L23 is std_1c20:inst|cpu:the_cpu|cpu_test_bench:the_cpu_test_bench|Add0~581

--operation mode is arithmetic

XC1L23 = AMPP_FUNCTION(S1L590, S1L656, XC1L25);

--XC1L25 is std_1c20:inst|cpu:the_cpu|cpu_test_bench:the_cpu_test_bench|Add0~583

--operation mode is arithmetic

XC1L25 = AMPP_FUNCTION(S1L589, S1L655, XC1L27);

--XC1L27 is std_1c20:inst|cpu:the_cpu|cpu_test_bench:the_cpu_test_bench|Add0~585

--operation mode is arithmetic

XC1L27 = AMPP_FUNCTION(S1L588, S1L654, XC1L29);

--XC1L29 is std_1c20:inst|cpu:the_cpu|cpu_test_bench:the_cpu_test_bench|Add0~587

--operation mode is arithmetic

XC1L29 = AMPP_FUNCTION(S1L587, S1L653, XC1L31);

--XC1L31 is std_1c20:inst|cpu:the_cpu|cpu_test_bench:the_cpu_test_bench|Add0~589

--operation mode is arithmetic

XC1L31 = AMPP_FUNCTION(S1L586, S1L652, XC1L33);

--XC1L33 is std_1c20:inst|cpu:the_cpu|cpu_test_bench:the_cpu_test_bench|Add0~591

--operation mode is arithmetic

XC1L33 = AMPP_FUNCTION(S1L585, S1L651, XC1L35);

--XC1L35 is std_1c20:inst|cpu:the_cpu|cpu_test_bench:the_cpu_test_bench|Add0~593

--operation mode is arithmetic

XC1L35 = AMPP_FUNCTION(S1L584, S1L650, XC1L37);

--XC1L37 is std_1c20:inst|cpu:the_cpu|cpu_test_bench:the_cpu_test_bench|Add0~595

--operation mode is arithmetic

XC1L37 = AMPP_FUNCTION(S1L583, S1L649, XC1L39);

--XC1L39 is std_1c20:inst|cpu:the_cpu|cpu_test_bench:the_cpu_test_bench|Add0~597

--operation mode is arithmetic

XC1L39 = AMPP_FUNCTION(S1L582, S1L648, XC1L41);

--XC1L41 is std_1c20:inst|cpu:the_cpu|cpu_test_bench:the_cpu_test_bench|Add0~599

--operation mode is arithmetic

XC1L41 = AMPP_FUNCTION(S1L581, S1L647, XC1L43);

--XC1L43 is std_1c20:inst|cpu:the_cpu|cpu_test_bench:the_cpu_test_bench|Add0~601

--operation mode is arithmetic

XC1L43 = AMPP_FUNCTION(S1L580, S1L646, XC1L45);

--XC1L45 is std_1c20:inst|cpu:the_cpu|cpu_test_bench:the_cpu_test_bench|Add0~603

--operation mode is arithmetic

XC1L45 = AMPP_FUNCTION(S1L579, S1L645, XC1L47);

--XC1L47 is std_1c20:inst|cpu:the_cpu|cpu_test_bench:the_cpu_test_bench|Add0~605

--operation mode is arithmetic

XC1L47 = AMPP_FUNCTION(S1L578, S1L644, XC1L49);

--XC1L49 is std_1c20:inst|cpu:the_cpu|cpu_test_bench:the_cpu_test_bench|Add0~607

--operation mode is arithmetic

XC1L49 = AMPP_FUNCTION(S1L577, S1L643, XC1L51);

--XC1L51 is std_1c20:inst|cpu:the_cpu|cpu_test_bench:the_cpu_test_bench|Add0~609

--operation mode is arithmetic

XC1L51 = AMPP_FUNCTION(S1L576, S1L642, XC1L53);

--XC1L53 is std_1c20:inst|cpu:the_cpu|cpu_test_bench:the_cpu_test_bench|Add0~611

--operation mode is arithmetic

XC1L53 = AMPP_FUNCTION(S1L575, S1L641, XC1L55);

--XC1L55 is std_1c20:inst|cpu:the_cpu|cpu_test_bench:the_cpu_test_bench|Add0~613

--operation mode is arithmetic

XC1L55 = AMPP_FUNCTION(S1L574, S1L640, XC1L57);

--XC1L57 is std_1c20:inst|cpu:the_cpu|cpu_test_bench:the_cpu_test_bench|Add0~615

--operation mode is arithmetic

XC1L57 = AMPP_FUNCTION(S1L573, S1L639, XC1L59);

--XC1L59 is std_1c20:inst|cpu:the_cpu|cpu_test_bench:the_cpu_test_bench|Add0~617

--operation mode is arithmetic

XC1L59 = AMPP_FUNCTION(S1L572, S1L638, XC1L61);

--XC1L61 is std_1c20:inst|cpu:the_cpu|cpu_test_bench:the_cpu_test_bench|Add0~619

--operation mode is arithmetic

XC1L61 = AMPP_FUNCTION(S1L571, S1L637, XC1L63);

--XC1L63 is std_1c20:inst|cpu:the_cpu|cpu_test_bench:the_cpu_test_bench|Add0~621

--operation mode is arithmetic

XC1L63 = AMPP_FUNCTION(S1L570, S1L636, XC1L65);

--XC1L65 is std_1c20:inst|cpu:the_cpu|cpu_test_bench:the_cpu_test_bench|Add0~623

--operation mode is arithmetic

XC1L65 = AMPP_FUNCTION(S1L569, S1L635);

--EB1L30 is std_1c20:inst|lcd_display_control_slave_arbitrator:the_lcd_display_control_slave|LessThan0~94

--operation mode is normal

EB1L30 = !EB1_lcd_display_control_slave_wait_counter[5] & !EB1_lcd_display_control_slave_wait_counter[4] & EB1L28;

--DB1L5 is std_1c20:inst|lcd_display:the_lcd_display|LCD_E~451

--operation mode is normal

DB1L5 = EB1_lcd_display_control_slave_wait_counter[4] & (EB1_lcd_display_control_slave_wait_counter[3] & DB1L2) # !EB1_lcd_display_control_slave_wait_counter[4] & !EB1_lcd_display_control_slave_wait_counter[5] & (!DB1L2 # !EB1_lcd_display_control_slave_wait_counter[3]);

--Y1L74 is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|cpu_data_master_requests_ext_flash_s1~344

--operation mode is normal

Y1L74 = !S1_M_alu_result[24] & !S1_M_alu_result[23] & (S1_internal_d_write # S1_internal_d_read);

--KB1L171 is std_1c20:inst|sdram:the_sdram|m_cmd~58

--operation mode is normal

KB1L171 = KB1_f_pop & (KB1L554 # !TE1_entries[0] & !TE1_entries[1]);

--KB1L266 is std_1c20:inst|sdram:the_sdram|Mux19~1741

--operation mode is normal

KB1L266 = !KB1_m_state[4] & !KB1_m_state[3] & !KB1_init_done & KB1_i_cmd[1];

--S1_W_stall is std_1c20:inst|cpu:the_cpu|W_stall

--operation mode is normal

S1_W_stall = AMPP_FUNCTION(S1_internal_d_write, T1_internal_cpu_data_master_waitrequest, S1L1385);

--KB1_f_select is std_1c20:inst|sdram:the_sdram|f_select

--operation mode is normal

KB1_f_select = KB1_f_pop & !KB1L554 & (TE1_entries[0] # TE1_entries[1]);

--KB1L455 is std_1c20:inst|sdram:the_sdram|Mux108~1499

--operation mode is normal

KB1L455 = KB1L451 # KB1_m_addr[7] & (KB1_m_state[4] $ !KB1_m_state[3]);

--KB1L462 is std_1c20:inst|sdram:the_sdram|Mux109~1371

--operation mode is normal

KB1L462 = KB1L459 # KB1_m_addr[6] & (KB1_m_state[4] $ !KB1_m_state[3]);

--KB1L469 is std_1c20:inst|sdram:the_sdram|Mux110~1395

--operation mode is normal

KB1L469 = KB1L466 # KB1_m_addr[5] & (KB1_m_state[4] $ !KB1_m_state[3]);

--KB1L476 is std_1c20:inst|sdram:the_sdram|Mux111~1322

--operation mode is normal

KB1L476 = KB1L473 # KB1_m_addr[4] & (KB1_m_state[4] $ !KB1_m_state[3]);

--KB1L483 is std_1c20:inst|sdram:the_sdram|Mux112~1354

--operation mode is normal

KB1L483 = KB1L480 # KB1_m_addr[3] & (KB1_m_state[4] $ !KB1_m_state[3]);

--KB1L490 is std_1c20:inst|sdram:the_sdram|Mux113~1354

--operation mode is normal

KB1L490 = KB1L487 # KB1_m_addr[2] & (KB1_m_state[4] $ !KB1_m_state[3]);

--KB1L497 is std_1c20:inst|sdram:the_sdram|Mux114~1354

--operation mode is normal

KB1L497 = KB1L494 # KB1_m_addr[1] & (KB1_m_state[4] $ !KB1_m_state[3]);

--KB1L504 is std_1c20:inst|sdram:the_sdram|Mux115~1354

--operation mode is normal

KB1L504 = KB1L501 # KB1_m_addr[0] & (KB1_m_state[4] $ !KB1_m_state[3]);

--KB1L511 is std_1c20:inst|sdram:the_sdram|Mux118~1221

--operation mode is normal

KB1L511 = !KB1_m_state[5] & !KB1_m_state[6] & KB1L278 & !KB1_m_state[8];

--K1L7 is std_1c20:inst|clock_0_in_arbitrator:the_clock_0_in|cpu_data_master_requests_clock_0_in~538

--operation mode is normal

K1L7 = !S1_M_alu_result[11] & (S1_internal_d_write # S1_internal_d_read);

--NB1L17 is std_1c20:inst|sdram_s1_arbitrator:the_sdram_s1|cpu_data_master_requests_sdram_s1~561

--operation mode is normal

NB1L17 = S1_M_alu_result[24] & !S1_M_alu_result[25] & (S1_internal_d_write # S1_internal_d_read);

--U1L134 is std_1c20:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_run~174

--operation mode is normal

U1L134 = !NB1L24 & (TE1_entries[0] # !TE1_entries[1]) # !NB1L21;

--S1_D_ic_fill_starting is std_1c20:inst|cpu:the_cpu|D_ic_fill_starting

--operation mode is normal

S1_D_ic_fill_starting = AMPP_FUNCTION(S1_ic_fill_active, S1_M_pipe_flush, S1L248);

--Y1_ext_flash_s1_in_a_read_cycle is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_flash_s1_in_a_read_cycle

--operation mode is normal

Y1_ext_flash_s1_in_a_read_cycle = Y1L66 # U1L165 & (Y1L21 # Y1L23);

--WE1L36 is std_1c20:inst|sdram_s1_arbitrator:the_sdram_s1|rdv_fifo_for_cpu_instruction_master_to_sdram_s1_module:rdv_fifo_for_cpu_instruction_master_to_sdram_s1|updated_one_count~71

--operation mode is normal

WE1L36 = NB1L18 & (TE1_entries[0] # !TE1_entries[1]);

--WE1L5 is std_1c20:inst|sdram_s1_arbitrator:the_sdram_s1|rdv_fifo_for_cpu_instruction_master_to_sdram_s1_module:rdv_fifo_for_cpu_instruction_master_to_sdram_s1|A_WE_StdLogicVector~1217

--operation mode is normal

WE1L5 = WE1_how_many_ones[1] & WE1_how_many_ones[0] & (!WE1_stage_0 # !KB1_za_valid) # !WE1_how_many_ones[1] & KB1_za_valid & WE1_stage_0 & !WE1_how_many_ones[0];

--WE1L6 is std_1c20:inst|sdram_s1_arbitrator:the_sdram_s1|rdv_fifo_for_cpu_instruction_master_to_sdram_s1_module:rdv_fifo_for_cpu_instruction_master_to_sdram_s1|A_WE_StdLogicVector~1218

--operation mode is normal

WE1L6 = WE1L36 $ WE1_how_many_ones[0] $ (KB1_za_valid & WE1_stage_0);

--Y1L246 is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|lan91c111_s1_counter_load_value~116

--operation mode is normal

Y1L246 = !Y1_d1_ext_ram_bus_avalon_slave_end_xfer & !Y1L194 & S1_internal_d_write & Y1L52;

--KB1L283 is std_1c20:inst|sdram:the_sdram|Mux24~1470

--operation mode is normal

KB1L283 = !KB1_m_count[2] & !KB1_m_count[1] & KB1L281 & KB1L282;

--KB1L275 is std_1c20:inst|sdram:the_sdram|Mux22~1326

--operation mode is normal

KB1L275 = KB1_m_state[0] & (!KB1_m_state[2] & !KB1L574 # !KB1_m_state[8]);

--KB1L276 is std_1c20:inst|sdram:the_sdram|Mux22~1327

--operation mode is normal

KB1L276 = KB1_m_state[2] & !KB1_m_count[2] & !KB1_m_count[1] & KB1_m_next[1];

--KB1L309 is std_1c20:inst|sdram:the_sdram|Mux28~1636

--operation mode is normal

KB1L309 = KB1_m_count[2] # KB1_m_count[1] # KB1_m_next[1] # !KB1L379;

--KB1L294 is std_1c20:inst|sdram:the_sdram|Mux26~1237

--operation mode is normal

KB1L294 = !KB1L554 & !KB1_refresh_request & (TE1_entries[0] # TE1_entries[1]);

--KB1L298 is std_1c20:inst|sdram:the_sdram|Mux27~1234

--operation mode is normal

KB1L298 = KB1_m_state[0] & !KB1_m_state[2] & KB1L547 & !KB1_m_state[8];

--TE1L62 is std_1c20:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_0[56]~56

--operation mode is normal

TE1L62 = KB1L237 & !TE1_wr_address & (TE1_entries[0] # !TE1_entries[1]);

--TE1L123 is std_1c20:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_1[56]~56

--operation mode is normal

TE1L123 = KB1L237 & TE1_wr_address & (TE1_entries[0] # !TE1_entries[1]);

--KB1L221 is std_1c20:inst|sdram:the_sdram|m_next~848

--operation mode is normal

KB1L221 = KB1_refresh_request & !KB1L554 & (TE1_entries[0] # TE1_entries[1]);

--KB1L222 is std_1c20:inst|sdram:the_sdram|m_next~849

--operation mode is normal

KB1L222 = KB1_refresh_request # KB1L554 & (TE1_entries[0] # TE1_entries[1]);

--KB1L335 is std_1c20:inst|sdram:the_sdram|Mux36~1276

--operation mode is normal

KB1L335 = KB1_m_next[3] & (KB1_m_state[4] $ !KB1_m_state[3] # !KB1L221);

--KB1L328 is std_1c20:inst|sdram:the_sdram|Mux35~1206

--operation mode is normal

KB1L328 = KB1_m_next[4] & (KB1_m_state[4] $ !KB1_m_state[3] # !KB1L221);

--XE1L14 is std_1c20:inst|uart1:the_uart1|uart1_regs:the_uart1_regs|control_wr_strobe~27

--operation mode is normal

XE1L14 = S1_M_alu_result[2] & S1_M_alu_result[3] & !S1_M_alu_result[4] & XE1L13;

--S1L1288 is std_1c20:inst|cpu:the_cpu|M_wr_data_unfiltered[2]~3709

--operation mode is normal

S1L1288 = AMPP_FUNCTION(S1_M_shift_rot_result[2], S1_M_ctrl_shift_rot, S1L1287);

--S1L233 is std_1c20:inst|cpu:the_cpu|D_ctrl_jmp_indirect~46

--operation mode is normal

S1L233 = AMPP_FUNCTION(S1_D_iw[4], S1_D_iw[5], S1L760, S1_D_iw[12]);

--S1L1291 is std_1c20:inst|cpu:the_cpu|M_wr_data_unfiltered[3]~3710

--operation mode is normal

S1L1291 = AMPP_FUNCTION(S1_M_shift_rot_result[3], S1_M_ctrl_shift_rot, S1L1290);

--S1_E_hbreak_req is std_1c20:inst|cpu:the_cpu|E_hbreak_req

--operation mode is normal

S1_E_hbreak_req = AMPP_FUNCTION(S1_E_iw[13], S1_E_iw[14], S1L926, S1L479);

--S1L83 is std_1c20:inst|cpu:the_cpu|A_WE_StdLogic~280

--operation mode is normal

S1L83 = AMPP_FUNCTION(S1_internal_d_write, T1_internal_cpu_data_master_waitrequest, S1L1385, S1L751);

--S1L1348 is std_1c20:inst|cpu:the_cpu|M_wr_data_unfiltered[22]~3711

--operation mode is normal

S1L1348 = AMPP_FUNCTION(S1_M_shift_rot_result[22], S1_M_ctrl_shift_rot, S1L1347);

--S1L1345 is std_1c20:inst|cpu:the_cpu|M_wr_data_unfiltered[21]~3712

--operation mode is normal

S1L1345 = AMPP_FUNCTION(S1_M_shift_rot_result[21], S1_M_ctrl_shift_rot, S1L1344);

--S1L1339 is std_1c20:inst|cpu:the_cpu|M_wr_data_unfiltered[19]~3713

--operation mode is normal

S1L1339 = AMPP_FUNCTION(S1_M_shift_rot_result[19], S1_M_ctrl_shift_rot, S1L1338);

--S1L1336 is std_1c20:inst|cpu:the_cpu|M_wr_data_unfiltered[18]~3714

--operation mode is normal

S1L1336 = AMPP_FUNCTION(S1_M_shift_rot_result[18], S1_M_ctrl_shift_rot, S1L1335);

--S1L1354 is std_1c20:inst|cpu:the_cpu|M_wr_data_unfiltered[24]~3715

--operation mode is normal

S1L1354 = AMPP_FUNCTION(S1_M_shift_rot_result[24], S1_M_ctrl_shift_rot, S1L1353);

--S1L1330 is std_1c20:inst|cpu:the_cpu|M_wr_data_unfiltered[16]~3716

--operation mode is normal

S1L1330 = AMPP_FUNCTION(S1_M_shift_rot_result[16], S1_M_ctrl_shift_rot, S1L1329);

--S1L1327 is std_1c20:inst|cpu:the_cpu|M_wr_data_unfiltered[15]~3717

--operation mode is normal

S1L1327 = AMPP_FUNCTION(S1_M_shift_rot_result[15], S1_M_ctrl_shift_rot, S1L1326);

--S1L1324 is std_1c20:inst|cpu:the_cpu|M_wr_data_unfiltered[14]~3718

--operation mode is normal

S1L1324 = AMPP_FUNCTION(S1_M_shift_rot_result[14], S1_M_ctrl_shift_rot, S1L1323);

--S1L1321 is std_1c20:inst|cpu:the_cpu|M_wr_data_unfiltered[13]~3719

--operation mode is normal

S1L1321 = AMPP_FUNCTION(S1_M_shift_rot_result[13], S1_M_ctrl_shift_rot, S1L1320);

--S1L1318 is std_1c20:inst|cpu:the_cpu|M_wr_data_unfiltered[12]~3720

--operation mode is normal

S1L1318 = AMPP_FUNCTION(S1_M_shift_rot_result[12], S1_M_ctrl_shift_rot, S1L1317);

--S1L1333 is std_1c20:inst|cpu:the_cpu|M_wr_data_unfiltered[17]~3721

--operation mode is normal

S1L1333 = AMPP_FUNCTION(S1_M_shift_rot_result[17], S1_M_ctrl_shift_rot, S1L1332);

--S1L1357 is std_1c20:inst|cpu:the_cpu|M_wr_data_unfiltered[25]~3722

--operation mode is normal

S1L1357 = AMPP_FUNCTION(S1_M_shift_rot_result[25], S1_M_ctrl_shift_rot, S1L1356);

--S1L1342 is std_1c20:inst|cpu:the_cpu|M_wr_data_unfiltered[20]~3723

--operation mode is normal

S1L1342 = AMPP_FUNCTION(S1_M_shift_rot_result[20], S1_M_ctrl_shift_rot, S1L1341);

--S1L1351 is std_1c20:inst|cpu:the_cpu|M_wr_data_unfiltered[23]~3724

--operation mode is normal

S1L1351 = AMPP_FUNCTION(S1_M_shift_rot_result[23], S1_M_ctrl_shift_rot, S1L1350);

--S1L1315 is std_1c20:inst|cpu:the_cpu|M_wr_data_unfiltered[11]~3725

--operation mode is normal

S1L1315 = AMPP_FUNCTION(S1_M_shift_rot_result[11], S1_M_ctrl_shift_rot, S1L1314);

--S1L1312 is std_1c20:inst|cpu:the_cpu|M_wr_data_unfiltered[10]~3726

--operation mode is normal

S1L1312 = AMPP_FUNCTION(S1_M_shift_rot_result[10], S1_M_ctrl_shift_rot, S1L1311);

--S1L1309 is std_1c20:inst|cpu:the_cpu|M_wr_data_unfiltered[9]~3727

--operation mode is normal

S1L1309 = AMPP_FUNCTION(S1_M_shift_rot_result[9], S1_M_ctrl_shift_rot, S1L1308);

--S1L1306 is std_1c20:inst|cpu:the_cpu|M_wr_data_unfiltered[8]~3728

--operation mode is normal

S1L1306 = AMPP_FUNCTION(S1_M_shift_rot_result[8], S1_M_ctrl_shift_rot, S1L1305);

--S1L1303 is std_1c20:inst|cpu:the_cpu|M_wr_data_unfiltered[7]~3729

--operation mode is normal

S1L1303 = AMPP_FUNCTION(S1_M_shift_rot_result[7], S1_M_ctrl_shift_rot, S1L1302);

--S1L1300 is std_1c20:inst|cpu:the_cpu|M_wr_data_unfiltered[6]~3730

--operation mode is normal

S1L1300 = AMPP_FUNCTION(S1_M_shift_rot_result[6], S1_M_ctrl_shift_rot, S1L1299);

--S1L1294 is std_1c20:inst|cpu:the_cpu|M_wr_data_unfiltered[4]~3731

--operation mode is normal

S1L1294 = AMPP_FUNCTION(S1_M_shift_rot_result[4], S1_M_ctrl_shift_rot, S1L1293);

--S1L1297 is std_1c20:inst|cpu:the_cpu|M_wr_data_unfiltered[5]~3732

--operation mode is normal

S1L1297 = AMPP_FUNCTION(S1_M_shift_rot_result[5], S1_M_ctrl_shift_rot, S1L1296);

--S1L1285 is std_1c20:inst|cpu:the_cpu|M_wr_data_unfiltered[1]~3733

--operation mode is normal

S1L1285 = AMPP_FUNCTION(S1_M_shift_rot_result[1], S1_M_ctrl_shift_rot, S1L1284);

--S1L1282 is std_1c20:inst|cpu:the_cpu|M_wr_data_unfiltered[0]~3734

--operation mode is normal

S1L1282 = AMPP_FUNCTION(S1_M_shift_rot_result[0], S1_M_ctrl_shift_rot, S1L1281);

--V1L24 is std_1c20:inst|cpu_jtag_debug_module_arbitrator:the_cpu_jtag_debug_module|cpu_jtag_debug_module_arb_addend[1]~749

--operation mode is normal

V1L24 = V1_cpu_jtag_debug_module_arb_addend[1] & !V1_cpu_instruction_master_qualified_request_cpu_jtag_debug_module & (!K1L3 # !V1L6);

--V1L21 is std_1c20:inst|cpu_jtag_debug_module_arbitrator:the_cpu_jtag_debug_module|cpu_jtag_debug_module_arb_addend[0]~750

--operation mode is normal

V1L21 = !V1_cpu_instruction_master_qualified_request_cpu_jtag_debug_module & !V1_cpu_jtag_debug_module_arb_addend[0] & (!K1L3 # !V1L6);

--X1L9 is std_1c20:inst|epcs_controller_epcs_control_port_arbitrator:the_epcs_controller_epcs_control_port|cpu_instruction_master_read_data_valid_epcs_controller_epcs_control_port~18

--operation mode is normal

X1L9 = X1L12 & !V1L36 & X1_cpu_instruction_master_granted_epcs_controller_epcs_control_port & !S1_ic_fill_tag[5];

--X1L25 is std_1c20:inst|epcs_controller_epcs_control_port_arbitrator:the_epcs_controller_epcs_control_port|epcs_controller_epcs_control_port_arb_addend[1]~741

--operation mode is normal

X1L25 = X1L27 & (X1L2) # !X1L27 & (X1L6 # X1_epcs_controller_epcs_control_port_saved_chosen_master_vector[0] & !X1L2);

--X1L23 is std_1c20:inst|epcs_controller_epcs_control_port_arbitrator:the_epcs_controller_epcs_control_port|epcs_controller_epcs_control_port_arb_addend[0]~742

--operation mode is normal

X1L23 = X1L6 & (X1L27) # !X1L6 & !X1L27 & (X1L2 # !X1_epcs_controller_epcs_control_port_saved_chosen_master_vector[0]);

--VE1L5 is std_1c20:inst|sdram_s1_arbitrator:the_sdram_s1|rdv_fifo_for_cpu_data_master_to_sdram_s1_module:rdv_fifo_for_cpu_data_master_to_sdram_s1|A_WE_StdLogicVector~1210

--operation mode is normal

VE1L5 = VE1_how_many_ones[1] & VE1_how_many_ones[0] & (!VE1_stage_0 # !KB1_za_valid) # !VE1_how_many_ones[1] & KB1_za_valid & VE1_stage_0 & !VE1_how_many_ones[0];

--VE1L6 is std_1c20:inst|sdram_s1_arbitrator:the_sdram_s1|rdv_fifo_for_cpu_data_master_to_sdram_s1_module:rdv_fifo_for_cpu_data_master_to_sdram_s1|A_WE_StdLogicVector~1211

--operation mode is normal

VE1L6 = VE1L21 $ VE1_how_many_ones[0] $ (KB1_za_valid & VE1_stage_0);

--NB1L74 is std_1c20:inst|sdram_s1_arbitrator:the_sdram_s1|sdram_s1_end_xfer~20

--operation mode is normal

NB1L74 = TE1_entries[1] & !TE1_entries[0] & KB1L237;

--N1L1 is std_1c20:inst|clock_1_in_arbitrator:the_clock_1_in|clock_1_in_read~33

--operation mode is normal

N1L1 = !T1_internal_cpu_data_master_waitrequest & (S1_internal_d_read & N1_cpu_data_master_requests_clock_1_in);

--K1L1 is std_1c20:inst|clock_0_in_arbitrator:the_clock_0_in|clock_0_in_read~33

--operation mode is normal

K1L1 = !T1_internal_cpu_data_master_waitrequest & (S1_internal_d_read & K1_cpu_data_master_requests_clock_0_in);

--KB1L364 is std_1c20:inst|sdram:the_sdram|Mux40~1482

--operation mode is normal

KB1L364 = !KB1_m_state[4] & !KB1_m_state[3] & KB1L350;

--KB1L377 is std_1c20:inst|sdram:the_sdram|Mux41~1479

--operation mode is normal

KB1L377 = KB1_m_state[0] & !KB1_m_state[3] & KB1L350;

--KB1L378 is std_1c20:inst|sdram:the_sdram|Mux41~1480

--operation mode is normal

KB1L378 = KB1_m_count[1] & (!KB1L350 # !KB1_refresh_request # !KB1_init_done);

--H1_cpu_data_master_requests_button_pio_s1 is std_1c20:inst|button_pio_s1_arbitrator:the_button_pio_s1|cpu_data_master_requests_button_pio_s1

--operation mode is normal

H1_cpu_data_master_requests_button_pio_s1 = S1_M_alu_result[6] & !S1_M_alu_result[4] & S1_M_alu_result[5] & SB1L2;

--UB1_cpu_data_master_granted_sysid_control_slave is std_1c20:inst|sysid_control_slave_arbitrator:the_sysid_control_slave|cpu_data_master_granted_sysid_control_slave

--operation mode is normal

UB1_cpu_data_master_granted_sysid_control_slave = S1_M_alu_result[3] & S1_M_alu_result[4] & S1_internal_d_read & UB1L9;

--T1L112 is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[10]~5336

--operation mode is normal

T1L112 = T1L100 & (S1_M_alu_result[5] # !SB1L2 # !S1_M_alu_result[6]);

--T1L75 is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[5]~5337

--operation mode is normal

T1L75 = T1L59 & (S1_M_alu_result[2] # !UB1L10 # !UB1L9);

--CF1L21 is sld_hub:sld_hub_inst|sld_rom_sr:HUB_INFO_REG|word_counter[0]~1282

--operation mode is normal

CF1L21 = AMPP_FUNCTION(FF1_state[8], C1_jtag_debug_mode_usr1, FF1L18, C1_jtag_debug_mode_usr0);

--C1L5 is sld_hub:sld_hub_inst|comb~99

--operation mode is normal

C1L5 = AMPP_FUNCTION(altera_internal_jtag, BF3_Q[6], A1L7, C1L4);

--SD1L142 is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|process2~2

--operation mode is normal

SD1L142 = AMPP_FUNCTION(A1L4, SD1_in_between_shiftdr_and_updatedr, SD1L145);

--GE1L62 is std_1c20:inst|jtag_uart:the_jtag_uart|alt_jtag_atlantic:jtag_uart_alt_jtag_atlantic|td_shift[9]~3577

--operation mode is normal

GE1L62 = AMPP_FUNCTION(GE1_state, GE1_count[1], GE1_td_shift[9], GE1_user_saw_rvalid);

--HB1L3 is std_1c20:inst|reconfig_request_pio:the_reconfig_request_pio|process2~28

--operation mode is normal

HB1L3 = S1_internal_d_write & !T1_internal_cpu_data_master_waitrequest & S1_M_alu_result[5] & JB1L3;

--NB1L72 is std_1c20:inst|sdram_s1_arbitrator:the_sdram_s1|sdram_s1_arb_winner~0

--operation mode is normal

NB1L72 = NB1_WideOr1 & (!NB1L13 & !NB1L69 # !NB1_sdram_s1_slavearbiterlockenable);

--NB1L57 is std_1c20:inst|sdram_s1_arbitrator:the_sdram_s1|sdram_s1_arb_counter_enable~45

--operation mode is normal

NB1L57 = NB1L56 & (TE1_entries[0] # !KB1L237 # !TE1_entries[1]);

--S1L822 is std_1c20:inst|cpu:the_cpu|F_ic_tag_rd_addr_nxt[0]~4256

--operation mode is normal

S1L822 = AMPP_FUNCTION(S1_D_kill, S1_D_inst_ram_hit, S1L820, S1_D_pc[3]);

--S1L825 is std_1c20:inst|cpu:the_cpu|F_ic_tag_rd_addr_nxt[1]~4257

--operation mode is normal

S1L825 = AMPP_FUNCTION(S1_D_kill, S1_D_inst_ram_hit, S1L823, S1_D_pc[4]);

--S1L828 is std_1c20:inst|cpu:the_cpu|F_ic_tag_rd_addr_nxt[2]~4258

--operation mode is normal

S1L828 = AMPP_FUNCTION(S1_D_kill, S1_D_inst_ram_hit, S1L826, S1_D_pc[5]);

--S1L831 is std_1c20:inst|cpu:the_cpu|F_ic_tag_rd_addr_nxt[3]~4259

--operation mode is normal

S1L831 = AMPP_FUNCTION(S1_D_kill, S1_D_inst_ram_hit, S1L829, S1_D_pc[6]);

--S1L834 is std_1c20:inst|cpu:the_cpu|F_ic_tag_rd_addr_nxt[4]~4260

--operation mode is normal

S1L834 = AMPP_FUNCTION(S1_D_kill, S1_D_inst_ram_hit, S1L832, S1_D_pc[7]);

--S1L837 is std_1c20:inst|cpu:the_cpu|F_ic_tag_rd_addr_nxt[5]~4261

--operation mode is normal

S1L837 = AMPP_FUNCTION(S1_D_kill, S1_D_inst_ram_hit, S1L835, S1_D_pc[8]);

--S1L840 is std_1c20:inst|cpu:the_cpu|F_ic_tag_rd_addr_nxt[6]~4262

--operation mode is normal

S1L840 = AMPP_FUNCTION(S1_D_kill, S1_D_inst_ram_hit, S1L838, S1_D_pc[9]);

--S1L796 is std_1c20:inst|cpu:the_cpu|F_ic_data_rd_addr_nxt[2]~1824

--operation mode is normal

S1L796 = AMPP_FUNCTION(S1_D_kill, S1_D_inst_ram_hit, S1L794, S1_D_pc[2]);

--S1L793 is std_1c20:inst|cpu:the_cpu|F_ic_data_rd_addr_nxt[1]~1825

--operation mode is normal

S1L793 = AMPP_FUNCTION(S1_D_kill, S1_D_inst_ram_hit, S1L791, S1_D_pc[1]);

--S1L790 is std_1c20:inst|cpu:the_cpu|F_ic_data_rd_addr_nxt[0]~1826

--operation mode is normal

S1L790 = AMPP_FUNCTION(S1_D_kill, S1_D_inst_ram_hit, S1L788, S1_D_pc[0]);

--XE1L64 is std_1c20:inst|uart1:the_uart1|uart1_regs:the_uart1_regs|tx_wr_strobe~14

--operation mode is normal

XE1L64 = S1_M_alu_result[2] & !S1_M_alu_result[3] & !S1_M_alu_result[4] & XE1L13;

--S1L1276 is std_1c20:inst|cpu:the_cpu|M_status_reg_pie~161

--operation mode is normal

S1L1276 = AMPP_FUNCTION(S1_E_ctrl_break, S1_E_ctrl_exception, S1L543, S1_E_wrctl_status);

--S1L1277 is std_1c20:inst|cpu:the_cpu|M_status_reg_pie~162

--operation mode is normal

S1L1277 = AMPP_FUNCTION(S1_E_ctrl_break, S1_E_ctrl_exception, S1L752, S1_W_stall);

--T1L294 is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|process3~0

--operation mode is normal

T1L294 = !T1_internal_cpu_data_master_dbs_address[1] & !T1_internal_cpu_data_master_dbs_address[0] & T1L293;

--DE1L134 is std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|p1_data_to_cpu[2]~877

--operation mode is normal

DE1L134 = !X1L16 & (X1L2 & S1_M_alu_result[3] # !X1L2 & (S1_ic_fill_ap_offset[1]));

--RD1L62 is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|module_input6~27

--operation mode is normal

RD1L62 = AMPP_FUNCTION(S1_internal_d_write, S1_hbreak_enabled, V1L4, S1_M_alu_result[10]);

--Z1_control_wr_strobe is std_1c20:inst|high_res_timer:the_high_res_timer|control_wr_strobe

--operation mode is normal

Z1_control_wr_strobe = S1_internal_d_write & !T1_internal_cpu_data_master_waitrequest & AB1_cpu_data_master_requests_high_res_timer_s1 & XE1L18;

--S1L1360 is std_1c20:inst|cpu:the_cpu|M_wr_data_unfiltered[26]~3735

--operation mode is normal

S1L1360 = AMPP_FUNCTION(S1_M_shift_rot_result[26], S1_M_ctrl_shift_rot, S1L1359);

--T1L281 is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|p1_registered_cpu_data_master_readdata~58

--operation mode is normal

T1L281 = BB1_ien_AE & BB1_fifo_AE # !CB1L2 # !UB1L9;

--T1L39 is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[1]~5338

--operation mode is normal

T1L39 = JB1L3 & (S1_M_alu_result[5] # !A1L140);

--S1L1278 is std_1c20:inst|cpu:the_cpu|M_status_reg_pie~163

--operation mode is normal

S1L1278 = AMPP_FUNCTION(S1_internal_d_write, T1_internal_cpu_data_master_waitrequest, S1L1385, S1L752);

--RB1_control_wr_strobe is std_1c20:inst|sys_clk_timer:the_sys_clk_timer|control_wr_strobe

--operation mode is normal

RB1_control_wr_strobe = S1_internal_d_write & !T1_internal_cpu_data_master_waitrequest & SB1_cpu_data_master_requests_sys_clk_timer_s1 & XE1L18;

--YE1L31 is std_1c20:inst|uart1:the_uart1|uart1_rx:the_uart1_rx|break_detect~48

--operation mode is normal

YE1L31 = YE1_break_detect # YE1_delayed_unxrx_in_processxx3 & !YE1_unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[0] & !YE1L72;

--RB1_period_h_wr_strobe is std_1c20:inst|sys_clk_timer:the_sys_clk_timer|period_h_wr_strobe

--operation mode is normal

RB1_period_h_wr_strobe = S1_internal_d_write & !T1_internal_cpu_data_master_waitrequest & XE1L15 & SB1_cpu_data_master_requests_sys_clk_timer_s1;

--RB1_period_l_wr_strobe is std_1c20:inst|sys_clk_timer:the_sys_clk_timer|period_l_wr_strobe

--operation mode is normal

RB1_period_l_wr_strobe = S1_internal_d_write & !T1_internal_cpu_data_master_waitrequest & SB1_cpu_data_master_requests_sys_clk_timer_s1 & XE1L20;

--Z1_period_h_wr_strobe is std_1c20:inst|high_res_timer:the_high_res_timer|period_h_wr_strobe

--operation mode is normal

Z1_period_h_wr_strobe = S1_internal_d_write & !T1_internal_cpu_data_master_waitrequest & XE1L15 & AB1_cpu_data_master_requests_high_res_timer_s1;

--Z1_period_l_wr_strobe is std_1c20:inst|high_res_timer:the_high_res_timer|period_l_wr_strobe

--operation mode is normal

Z1_period_l_wr_strobe = S1_internal_d_write & !T1_internal_cpu_data_master_waitrequest & AB1_cpu_data_master_requests_high_res_timer_s1 & XE1L20;

--NE2L1 is std_1c20:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_r:the_jtag_uart_scfifo_r|scfifo:rfifo|scfifo_jf21:auto_generated|a_dpfifo_ml21:dpfifo|a_fefifo_7cf:fifo_state|_~28

--operation mode is normal

NE2L1 = GE1L37Q & (NE2_b_full $ (!BB1L43 # !NE2_b_non_empty)) # !GE1L37Q & (NE2_b_non_empty & BB1L43);

--S1L1375 is std_1c20:inst|cpu:the_cpu|M_wr_data_unfiltered[31]~3736

--operation mode is normal

S1L1375 = AMPP_FUNCTION(S1_M_shift_rot_result[31], S1_M_ctrl_shift_rot, S1L1374);

--S1L205 is std_1c20:inst|cpu:the_cpu|D_ctrl_alu_signed_cmp~296

--operation mode is normal

S1L205 = AMPP_FUNCTION(S1_D_iw[4], S1_D_iw[5], S1L206, S1_D_iw[11]);

--SD1L70 is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|DRsize[0]~20068

--operation mode is normal

SD1L70 = AMPP_FUNCTION(A1L4, SD1_in_between_shiftdr_and_updatedr, SD1L145, SD1_ir[0]);

--S1L1363 is std_1c20:inst|cpu:the_cpu|M_wr_data_unfiltered[27]~3737

--operation mode is normal

S1L1363 = AMPP_FUNCTION(S1_M_shift_rot_result[27], S1_M_ctrl_shift_rot, S1L1362);

--DE1L141 is std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|p1_wr_strobe~42

--operation mode is normal

DE1L141 = S1_internal_d_write & X1L2 & W1L1 & !DE1_wr_strobe;

--S1L1372 is std_1c20:inst|cpu:the_cpu|M_wr_data_unfiltered[30]~3738

--operation mode is normal

S1L1372 = AMPP_FUNCTION(S1_M_shift_rot_result[30], S1_M_ctrl_shift_rot, S1L1371);

--S1L1369 is std_1c20:inst|cpu:the_cpu|M_wr_data_unfiltered[29]~3739

--operation mode is normal

S1L1369 = AMPP_FUNCTION(S1_M_shift_rot_result[29], S1_M_ctrl_shift_rot, S1L1368);

--S1L1366 is std_1c20:inst|cpu:the_cpu|M_wr_data_unfiltered[28]~3740

--operation mode is normal

S1L1366 = AMPP_FUNCTION(S1_M_shift_rot_result[28], S1_M_ctrl_shift_rot, S1L1365);

--DE1L169 is std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|shift_reg~616

--operation mode is normal

DE1L169 = DE1_tx_holding_primed & (DE1_transmitting & (DE1_shift_reg[2]) # !DE1_transmitting & DE1_tx_holding_reg[2]) # !DE1_tx_holding_primed & (DE1_shift_reg[2]);

--DE1L170 is std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|shift_reg~617

--operation mode is normal

DE1L170 = DE1_tx_holding_primed & (DE1_transmitting & (DE1_shift_reg[3]) # !DE1_transmitting & DE1_tx_holding_reg[3]) # !DE1_tx_holding_primed & (DE1_shift_reg[3]);

--DE1L171 is std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|shift_reg~618

--operation mode is normal

DE1L171 = DE1_tx_holding_primed & (DE1_transmitting & (DE1_shift_reg[7]) # !DE1_transmitting & DE1_tx_holding_reg[7]) # !DE1_tx_holding_primed & (DE1_shift_reg[7]);

--DE1L172 is std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|shift_reg~619

--operation mode is normal

DE1L172 = DE1_tx_holding_primed & (DE1_transmitting & (DE1_shift_reg[6]) # !DE1_transmitting & DE1_tx_holding_reg[6]) # !DE1_tx_holding_primed & (DE1_shift_reg[6]);

--DE1L173 is std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|shift_reg~620

--operation mode is normal

DE1L173 = DE1_tx_holding_primed & (DE1_transmitting & (DE1_shift_reg[4]) # !DE1_transmitting & DE1_tx_holding_reg[4]) # !DE1_tx_holding_primed & (DE1_shift_reg[4]);

--DE1L174 is std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|shift_reg~621

--operation mode is normal

DE1L174 = DE1_tx_holding_primed & (DE1_transmitting & (DE1_shift_reg[5]) # !DE1_transmitting & DE1_tx_holding_reg[5]) # !DE1_tx_holding_primed & (DE1_shift_reg[5]);

--DE1L175 is std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|shift_reg~622

--operation mode is normal

DE1L175 = DE1_tx_holding_primed & (DE1_transmitting & (DE1_shift_reg[1]) # !DE1_transmitting & DE1_tx_holding_reg[1]) # !DE1_tx_holding_primed & (DE1_shift_reg[1]);

--DE1L159 is std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|SCLK_reg~291

--operation mode is normal

DE1L159 = DE1_state[4] & (DE1_transmitting # DE1_state[0] & DE1L117) # !DE1_state[4] & DE1_transmitting & (DE1_state[0] # !DE1L117);

--SD1L71 is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|DRsize[0]~20069

--operation mode is normal

SD1L71 = AMPP_FUNCTION(SD1L135, SD1L136, SD1L55, SD1L144);

--DE1L176 is std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|shift_reg~623

--operation mode is normal

DE1L176 = DE1_tx_holding_primed & (DE1_transmitting & (DE1_shift_reg[0]) # !DE1_transmitting & DE1_tx_holding_reg[0]) # !DE1_tx_holding_primed & (DE1_shift_reg[0]);

--S1L220 is std_1c20:inst|cpu:the_cpu|D_ctrl_flush_pipe_always~577

--operation mode is normal

S1L220 = AMPP_FUNCTION(S1_D_iw[0], S1_D_iw[2], S1_D_iw[5]);

--S1L226 is std_1c20:inst|cpu:the_cpu|D_ctrl_flush_pipe_always~588

--operation mode is normal

S1L226 = AMPP_FUNCTION(S1L220, S1_D_iw[4], S1_D_iw[3], S1_D_iw[1]);

--GE1L63 is std_1c20:inst|jtag_uart:the_jtag_uart|alt_jtag_atlantic:jtag_uart_alt_jtag_atlantic|td_shift[9]~3578

--operation mode is normal

GE1L63 = AMPP_FUNCTION(GE1L51, GE1_state, FF1_state[4], BF4_Q[0]);

--GE1L51 is std_1c20:inst|jtag_uart:the_jtag_uart|alt_jtag_atlantic:jtag_uart_alt_jtag_atlantic|td_shift[9]~3539

--operation mode is normal

GE1L51 = AMPP_FUNCTION(GE1_user_saw_rvalid, GE1_td_shift[9], GE1_count[1]);

--S1L398 is std_1c20:inst|cpu:the_cpu|D_wr_dst_reg~94

--operation mode is normal

S1L398 = AMPP_FUNCTION(S1_D_iw[2], S1_D_iw[1], S1_D_iw[0]);

--S1L399 is std_1c20:inst|cpu:the_cpu|D_wr_dst_reg~95

--operation mode is normal

S1L399 = AMPP_FUNCTION(S1_D_iw[0], S1_D_iw[1], S1_D_iw[2]);

--S1L215 is std_1c20:inst|cpu:the_cpu|D_ctrl_br~23

--operation mode is normal

S1L215 = AMPP_FUNCTION(S1_D_iw[1], S1_D_iw[2], S1_D_iw[0]);

--S1L397 is std_1c20:inst|cpu:the_cpu|D_wr_dst_reg~91

--operation mode is normal

S1L397 = AMPP_FUNCTION(S1_D_iw[2], S1_D_iw[1], S1_D_iw[0]);

--S1L400 is std_1c20:inst|cpu:the_cpu|D_wr_dst_reg~96

--operation mode is normal

S1L400 = AMPP_FUNCTION(S1L397, S1_D_issue, S1_M_pipe_flush);

--KB1L389 is std_1c20:inst|sdram:the_sdram|Mux42~1491

--operation mode is normal

KB1L389 = KB1_m_state[3] & KB1_m_count[0] & (KB1_m_state[4] # !KB1L383) # !KB1_m_state[3] & (KB1_m_count[0] # KB1L383 # !KB1_m_state[4]);

--KB1L390 is std_1c20:inst|sdram:the_sdram|Mux42~1492

--operation mode is normal

KB1L390 = KB1L389 & (KB1_m_state[3] # KB1_m_state[4] # KB1L387);

--A1L276 is ~GND

--operation mode is normal

A1L276 = GND;

--PLD_CLKFB is PLD_CLKFB

--operation mode is input

PLD_CLKFB = INPUT();

--PLD_CLOCKINPUT[1] is PLD_CLOCKINPUT[1]

--operation mode is input

PLD_CLOCKINPUT[1] = INPUT();

--PLD_CLEAR_N is PLD_CLEAR_N

--operation mode is input

PLD_CLEAR_N = INPUT();

--in_port_to_the_button_pio[2] is in_port_to_the_button_pio[2]

--operation mode is input

in_port_to_the_button_pio[2] = INPUT();

--in_port_to_the_button_pio[3] is in_port_to_the_button_pio[3]

--operation mode is input

in_port_to_the_button_pio[3] = INPUT();

--irq_from_the_lan91c111 is irq_from_the_lan91c111

--operation mode is input

irq_from_the_lan91c111 = INPUT();

--in_port_to_the_button_pio[1] is in_port_to_the_button_pio[1]

--operation mode is input

in_port_to_the_button_pio[1] = INPUT();

--in_port_to_the_button_pio[0] is in_port_to_the_button_pio[0]

--operation mode is input

in_port_to_the_button_pio[0] = INPUT();

--rxd_to_the_uart1 is rxd_to_the_uart1

--operation mode is input

rxd_to_the_uart1 = INPUT();

--SDRAM_CLK is SDRAM_CLK

--operation mode is output

SDRAM_CLK = OUTPUT(QC2__extclk0);

--PLD_CLKOUT is PLD_CLKOUT

--operation mode is output

PLD_CLKOUT = OUTPUT(QC1__extclk0);

--ENET_ADS_N is ENET_ADS_N

--operation mode is output

ENET_ADS_N = OUTPUT(GND);

--ENET_AEN is ENET_AEN

--operation mode is output

ENET_AEN = OUTPUT(GND);

--ior_n_to_the_lan91c111 is ior_n_to_the_lan91c111

--operation mode is output

ior_n_to_the_lan91c111 = OUTPUT(!Y1_ior_n_to_the_lan91c111);

--write_n_to_the_ext_flash is write_n_to_the_ext_flash

--operation mode is output

write_n_to_the_ext_flash = OUTPUT(!Y1_write_n_to_the_ext_flash);

--iow_n_to_the_lan91c111 is iow_n_to_the_lan91c111

--operation mode is output

iow_n_to_the_lan91c111 = OUTPUT(!Y1_iow_n_to_the_lan91c111);

--read_n_to_the_ext_flash is read_n_to_the_ext_flash

--operation mode is output

read_n_to_the_ext_flash = OUTPUT(!Y1_read_n_to_the_ext_flash);

--read_n_to_the_ext_ram is read_n_to_the_ext_ram

--operation mode is output

read_n_to_the_ext_ram = OUTPUT(!Y1_read_n_to_the_ext_ram);

--select_n_to_the_ext_flash is select_n_to_the_ext_flash

--operation mode is output

select_n_to_the_ext_flash = OUTPUT(!Y1_select_n_to_the_ext_flash);

--select_n_to_the_ext_ram is select_n_to_the_ext_ram

--operation mode is output

select_n_to_the_ext_ram = OUTPUT(!Y1_select_n_to_the_ext_ram);

--write_n_to_the_ext_ram is write_n_to_the_ext_ram

--operation mode is output

write_n_to_the_ext_ram = OUTPUT(!Y1L304);

--zs_cas_n_from_the_sdram is zs_cas_n_from_the_sdram

--operation mode is output

zs_cas_n_from_the_sdram = OUTPUT(!KB1_m_cmd[1]);

--zs_cke_from_the_sdram is zs_cke_from_the_sdram

--operation mode is output

zs_cke_from_the_sdram = OUTPUT(VCC);

--zs_cs_n_from_the_sdram is zs_cs_n_from_the_sdram

--operation mode is output

zs_cs_n_from_the_sdram = OUTPUT(!KB1_m_cmd[3]);

--zs_ras_n_from_the_sdram is zs_ras_n_from_the_sdram

--operation mode is output

zs_ras_n_from_the_sdram = OUTPUT(!KB1_m_cmd[2]);

--zs_we_n_from_the_sdram is zs_we_n_from_the_sdram

--operation mode is output

zs_we_n_from_the_sdram = OUTPUT(!KB1_m_cmd[0]);

--txd_from_the_uart1 is txd_from_the_uart1

--operation mode is output

txd_from_the_uart1 = OUTPUT(!ZE1_txd);

--LCD_RW_from_the_lcd_display is LCD_RW_from_the_lcd_display

--operation mode is output

LCD_RW_from_the_lcd_display = OUTPUT(S1_M_alu_result[2]);

--LCD_RS_from_the_lcd_display is LCD_RS_from_the_lcd_display

--operation mode is output

LCD_RS_from_the_lcd_display = OUTPUT(S1_M_alu_result[3]);

--LCD_E_from_the_lcd_display is LCD_E_from_the_lcd_display

--operation mode is output

LCD_E_from_the_lcd_display = OUTPUT(DB1L4);

--be_n_to_the_ext_ram[3] is be_n_to_the_ext_ram[3]

--operation mode is output

be_n_to_the_ext_ram[3] = OUTPUT(!Y1_be_n_to_the_ext_ram[3]);

--be_n_to_the_ext_ram[2] is be_n_to_the_ext_ram[2]

--operation mode is output

be_n_to_the_ext_ram[2] = OUTPUT(!Y1_be_n_to_the_ext_ram[2]);

--be_n_to_the_ext_ram[1] is be_n_to_the_ext_ram[1]

--operation mode is output

be_n_to_the_ext_ram[1] = OUTPUT(!Y1_be_n_to_the_ext_ram[1]);

--be_n_to_the_ext_ram[0] is be_n_to_the_ext_ram[0]

--operation mode is output

be_n_to_the_ext_ram[0] = OUTPUT(!Y1_be_n_to_the_ext_ram[0]);

--byteenablen_to_the_lan91c111[3] is byteenablen_to_the_lan91c111[3]

--operation mode is output

byteenablen_to_the_lan91c111[3] = OUTPUT(!Y1_byteenablen_to_the_lan91c111[3]);

--byteenablen_to_the_lan91c111[2] is byteenablen_to_the_lan91c111[2]

--operation mode is output

byteenablen_to_the_lan91c111[2] = OUTPUT(!Y1_byteenablen_to_the_lan91c111[2]);

--byteenablen_to_the_lan91c111[1] is byteenablen_to_the_lan91c111[1]

--operation mode is output

byteenablen_to_the_lan91c111[1] = OUTPUT(!Y1_byteenablen_to_the_lan91c111[1]);

--byteenablen_to_the_lan91c111[0] is byteenablen_to_the_lan91c111[0]

--operation mode is output

byteenablen_to_the_lan91c111[0] = OUTPUT(!Y1_byteenablen_to_the_lan91c111[0]);

--ext_ram_bus_address[22] is ext_ram_bus_address[22]

--operation mode is output

ext_ram_bus_address[22] = OUTPUT(Y1_ext_ram_bus_address[22]);

--ext_ram_bus_address[21] is ext_ram_bus_address[21]

--operation mode is output

ext_ram_bus_address[21] = OUTPUT(Y1_ext_ram_bus_address[21]);

--ext_ram_bus_address[20] is ext_ram_bus_address[20]

--operation mode is output

ext_ram_bus_address[20] = OUTPUT(Y1_ext_ram_bus_address[20]);

--ext_ram_bus_address[19] is ext_ram_bus_address[19]

--operation mode is output

ext_ram_bus_address[19] = OUTPUT(Y1_ext_ram_bus_address[19]);

--ext_ram_bus_address[18] is ext_ram_bus_address[18]

--operation mode is output

ext_ram_bus_address[18] = OUTPUT(Y1_ext_ram_bus_address[18]);

--ext_ram_bus_address[17] is ext_ram_bus_address[17]

--operation mode is output

ext_ram_bus_address[17] = OUTPUT(Y1_ext_ram_bus_address[17]);

--ext_ram_bus_address[16] is ext_ram_bus_address[16]

--operation mode is output

ext_ram_bus_address[16] = OUTPUT(Y1_ext_ram_bus_address[16]);

--ext_ram_bus_address[15] is ext_ram_bus_address[15]

--operation mode is output

ext_ram_bus_address[15] = OUTPUT(Y1_ext_ram_bus_address[15]);

--ext_ram_bus_address[14] is ext_ram_bus_address[14]

--operation mode is output

ext_ram_bus_address[14] = OUTPUT(Y1_ext_ram_bus_address[14]);

--ext_ram_bus_address[13] is ext_ram_bus_address[13]

--operation mode is output

ext_ram_bus_address[13] = OUTPUT(Y1_ext_ram_bus_address[13]);

--ext_ram_bus_address[12] is ext_ram_bus_address[12]

--operation mode is output

ext_ram_bus_address[12] = OUTPUT(Y1_ext_ram_bus_address[12]);

--ext_ram_bus_address[11] is ext_ram_bus_address[11]

--operation mode is output

ext_ram_bus_address[11] = OUTPUT(Y1_ext_ram_bus_address[11]);

--ext_ram_bus_address[10] is ext_ram_bus_address[10]

--operation mode is output

ext_ram_bus_address[10] = OUTPUT(Y1_ext_ram_bus_address[10]);

--ext_ram_bus_address[9] is ext_ram_bus_address[9]

--operation mode is output

ext_ram_bus_address[9] = OUTPUT(Y1_ext_ram_bus_address[9]);

--ext_ram_bus_address[8] is ext_ram_bus_address[8]

--operation mode is output

ext_ram_bus_address[8] = OUTPUT(Y1_ext_ram_bus_address[8]);

--ext_ram_bus_address[7] is ext_ram_bus_address[7]

--operation mode is output

ext_ram_bus_address[7] = OUTPUT(Y1_ext_ram_bus_address[7]);

--ext_ram_bus_address[6] is ext_ram_bus_address[6]

--operation mode is output

ext_ram_bus_address[6] = OUTPUT(Y1_ext_ram_bus_address[6]);

--ext_ram_bus_address[5] is ext_ram_bus_address[5]

--operation mode is output

ext_ram_bus_address[5] = OUTPUT(Y1_ext_ram_bus_address[5]);

--ext_ram_bus_address[4] is ext_ram_bus_address[4]

--operation mode is output

ext_ram_bus_address[4] = OUTPUT(Y1_ext_ram_bus_address[4]);

--ext_ram_bus_address[3] is ext_ram_bus_address[3]

--operation mode is output

ext_ram_bus_address[3] = OUTPUT(Y1_ext_ram_bus_address[3]);

--ext_ram_bus_address[2] is ext_ram_bus_address[2]

--operation mode is output

ext_ram_bus_address[2] = OUTPUT(Y1_ext_ram_bus_address[2]);

--ext_ram_bus_address[1] is ext_ram_bus_address[1]

--operation mode is output

ext_ram_bus_address[1] = OUTPUT(Y1_ext_ram_bus_address[1]);

--ext_ram_bus_address[0] is ext_ram_bus_address[0]

--operation mode is output

ext_ram_bus_address[0] = OUTPUT(Y1_ext_ram_bus_address[0]);

--out_port_from_the_led_pio[7] is out_port_from_the_led_pio[7]

--operation mode is output

out_port_from_the_led_pio[7] = OUTPUT(FB1_data_out[7]);

--out_port_from_the_led_pio[6] is out_port_from_the_led_pio[6]

--operation mode is output

out_port_from_the_led_pio[6] = OUTPUT(FB1_data_out[6]);

--out_port_from_the_led_pio[5] is out_port_from_the_led_pio[5]

--operation mode is output

out_port_from_the_led_pio[5] = OUTPUT(FB1_data_out[5]);

--out_port_from_the_led_pio[4] is out_port_from_the_led_pio[4]

--operation mode is output

out_port_from_the_led_pio[4] = OUTPUT(FB1_data_out[4]);

--out_port_from_the_led_pio[3] is out_port_from_the_led_pio[3]

--operation mode is output

out_port_from_the_led_pio[3] = OUTPUT(FB1_data_out[3]);

--out_port_from_the_led_pio[2] is out_port_from_the_led_pio[2]

--operation mode is output

out_port_from_the_led_pio[2] = OUTPUT(FB1_data_out[2]);

--out_port_from_the_led_pio[1] is out_port_from_the_led_pio[1]

--operation mode is output

out_port_from_the_led_pio[1] = OUTPUT(FB1_data_out[1]);

--out_port_from_the_led_pio[0] is out_port_from_the_led_pio[0]

--operation mode is output

out_port_from_the_led_pio[0] = OUTPUT(FB1_data_out[0]);

--out_port_from_the_seven_seg_pio[15] is out_port_from_the_seven_seg_pio[15]

--operation mode is output

out_port_from_the_seven_seg_pio[15] = OUTPUT(PB1_data_out[15]);

--out_port_from_the_seven_seg_pio[14] is out_port_from_the_seven_seg_pio[14]

--operation mode is output

out_port_from_the_seven_seg_pio[14] = OUTPUT(PB1_data_out[14]);

--out_port_from_the_seven_seg_pio[13] is out_port_from_the_seven_seg_pio[13]

--operation mode is output

out_port_from_the_seven_seg_pio[13] = OUTPUT(PB1_data_out[13]);

--out_port_from_the_seven_seg_pio[12] is out_port_from_the_seven_seg_pio[12]

--operation mode is output

out_port_from_the_seven_seg_pio[12] = OUTPUT(PB1_data_out[12]);

--out_port_from_the_seven_seg_pio[11] is out_port_from_the_seven_seg_pio[11]

--operation mode is output

out_port_from_the_seven_seg_pio[11] = OUTPUT(PB1_data_out[11]);

--out_port_from_the_seven_seg_pio[10] is out_port_from_the_seven_seg_pio[10]

--operation mode is output

out_port_from_the_seven_seg_pio[10] = OUTPUT(PB1_data_out[10]);

--out_port_from_the_seven_seg_pio[9] is out_port_from_the_seven_seg_pio[9]

--operation mode is output

out_port_from_the_seven_seg_pio[9] = OUTPUT(PB1_data_out[9]);

--out_port_from_the_seven_seg_pio[8] is out_port_from_the_seven_seg_pio[8]

--operation mode is output

out_port_from_the_seven_seg_pio[8] = OUTPUT(PB1_data_out[8]);

--out_port_from_the_seven_seg_pio[7] is out_port_from_the_seven_seg_pio[7]

--operation mode is output

out_port_from_the_seven_seg_pio[7] = OUTPUT(PB1_data_out[7]);

--out_port_from_the_seven_seg_pio[6] is out_port_from_the_seven_seg_pio[6]

--operation mode is output

out_port_from_the_seven_seg_pio[6] = OUTPUT(PB1_data_out[6]);

--out_port_from_the_seven_seg_pio[5] is out_port_from_the_seven_seg_pio[5]

--operation mode is output

out_port_from_the_seven_seg_pio[5] = OUTPUT(PB1_data_out[5]);

--out_port_from_the_seven_seg_pio[4] is out_port_from_the_seven_seg_pio[4]

--operation mode is output

out_port_from_the_seven_seg_pio[4] = OUTPUT(PB1_data_out[4]);

--out_port_from_the_seven_seg_pio[3] is out_port_from_the_seven_seg_pio[3]

--operation mode is output

out_port_from_the_seven_seg_pio[3] = OUTPUT(PB1_data_out[3]);

--out_port_from_the_seven_seg_pio[2] is out_port_from_the_seven_seg_pio[2]

--operation mode is output

out_port_from_the_seven_seg_pio[2] = OUTPUT(PB1_data_out[2]);

--out_port_from_the_seven_seg_pio[1] is out_port_from_the_seven_seg_pio[1]

--operation mode is output

out_port_from_the_seven_seg_pio[1] = OUTPUT(PB1_data_out[1]);

--out_port_from_the_seven_seg_pio[0] is out_port_from_the_seven_seg_pio[0]

--operation mode is output

out_port_from_the_seven_seg_pio[0] = OUTPUT(PB1_data_out[0]);

--zs_addr_from_the_sdram[11] is zs_addr_from_the_sdram[11]

--operation mode is output

zs_addr_from_the_sdram[11] = OUTPUT(KB1_m_addr[11]);

--zs_addr_from_the_sdram[10] is zs_addr_from_the_sdram[10]

--operation mode is output

zs_addr_from_the_sdram[10] = OUTPUT(KB1_m_addr[10]);

--zs_addr_from_the_sdram[9] is zs_addr_from_the_sdram[9]

--operation mode is output

zs_addr_from_the_sdram[9] = OUTPUT(KB1_m_addr[9]);

--zs_addr_from_the_sdram[8] is zs_addr_from_the_sdram[8]

--operation mode is output

zs_addr_from_the_sdram[8] = OUTPUT(KB1_m_addr[8]);

--zs_addr_from_the_sdram[7] is zs_addr_from_the_sdram[7]

--operation mode is output

zs_addr_from_the_sdram[7] = OUTPUT(KB1_m_addr[7]);

--zs_addr_from_the_sdram[6] is zs_addr_from_the_sdram[6]

--operation mode is output

zs_addr_from_the_sdram[6] = OUTPUT(KB1_m_addr[6]);

--zs_addr_from_the_sdram[5] is zs_addr_from_the_sdram[5]

--operation mode is output

zs_addr_from_the_sdram[5] = OUTPUT(KB1_m_addr[5]);

--zs_addr_from_the_sdram[4] is zs_addr_from_the_sdram[4]

--operation mode is output

zs_addr_from_the_sdram[4] = OUTPUT(KB1_m_addr[4]);

--zs_addr_from_the_sdram[3] is zs_addr_from_the_sdram[3]

--operation mode is output

zs_addr_from_the_sdram[3] = OUTPUT(KB1_m_addr[3]);

--zs_addr_from_the_sdram[2] is zs_addr_from_the_sdram[2]

--operation mode is output

zs_addr_from_the_sdram[2] = OUTPUT(KB1_m_addr[2]);

--zs_addr_from_the_sdram[1] is zs_addr_from_the_sdram[1]

--operation mode is output

zs_addr_from_the_sdram[1] = OUTPUT(KB1_m_addr[1]);

--zs_addr_from_the_sdram[0] is zs_addr_from_the_sdram[0]

--operation mode is output

zs_addr_from_the_sdram[0] = OUTPUT(KB1_m_addr[0]);

--zs_ba_from_the_sdram[1] is zs_ba_from_the_sdram[1]

--operation mode is output

zs_ba_from_the_sdram[1] = OUTPUT(KB1_m_bank[1]);

--zs_ba_from_the_sdram[0] is zs_ba_from_the_sdram[0]

--operation mode is output

zs_ba_from_the_sdram[0] = OUTPUT(KB1_m_bank[0]);

--zs_dqm_from_the_sdram[3] is zs_dqm_from_the_sdram[3]

--operation mode is output

zs_dqm_from_the_sdram[3] = OUTPUT(KB1_m_dqm[3]);

--zs_dqm_from_the_sdram[2] is zs_dqm_from_the_sdram[2]

--operation mode is output

zs_dqm_from_the_sdram[2] = OUTPUT(KB1_m_dqm[2]);

--zs_dqm_from_the_sdram[1] is zs_dqm_from_the_sdram[1]

--operation mode is output

zs_dqm_from_the_sdram[1] = OUTPUT(KB1_m_dqm[1]);

--zs_dqm_from_the_sdram[0] is zs_dqm_from_the_sdram[0]

--operation mode is output

zs_dqm_from_the_sdram[0] = OUTPUT(KB1_m_dqm[0]);

--A1L20 is bidir_port_to_and_from_the_reconfig_request_pio~0

--operation mode is bidir

A1L20 = bidir_port_to_and_from_the_reconfig_request_pio;

--bidir_port_to_and_from_the_reconfig_request_pio is bidir_port_to_and_from_the_reconfig_request_pio

--operation mode is bidir

bidir_port_to_and_from_the_reconfig_request_pio_tri_out = TRI(HB1_data_out, HB1_data_dir);

bidir_port_to_and_from_the_reconfig_request_pio = BIDIR(bidir_port_to_and_from_the_reconfig_request_pio_tri_out);

--A1L85 is ext_ram_bus_data~0

--operation mode is bidir

A1L85 = ext_ram_bus_data[31];

--ext_ram_bus_data[31] is ext_ram_bus_data[31]

--operation mode is bidir

ext_ram_bus_data[31]_tri_out = TRI(Y1_d1_outgoing_ext_ram_bus_data[31], Y1_d1_in_a_write_cycle);

ext_ram_bus_data[31] = BIDIR(ext_ram_bus_data[31]_tri_out);

--A1L86 is ext_ram_bus_data~1

--operation mode is bidir

A1L86 = ext_ram_bus_data[30];

--ext_ram_bus_data[30] is ext_ram_bus_data[30]

--operation mode is bidir

ext_ram_bus_data[30]_tri_out = TRI(Y1_d1_outgoing_ext_ram_bus_data[30], Y1_d1_in_a_write_cycle);

ext_ram_bus_data[30] = BIDIR(ext_ram_bus_data[30]_tri_out);

--A1L87 is ext_ram_bus_data~2

--operation mode is bidir

A1L87 = ext_ram_bus_data[29];

--ext_ram_bus_data[29] is ext_ram_bus_data[29]

--operation mode is bidir

ext_ram_bus_data[29]_tri_out = TRI(Y1_d1_outgoing_ext_ram_bus_data[29], Y1_d1_in_a_write_cycle);

ext_ram_bus_data[29] = BIDIR(ext_ram_bus_data[29]_tri_out);

--A1L88 is ext_ram_bus_data~3

--operation mode is bidir

A1L88 = ext_ram_bus_data[28];

--ext_ram_bus_data[28] is ext_ram_bus_data[28]

--operation mode is bidir

ext_ram_bus_data[28]_tri_out = TRI(Y1_d1_outgoing_ext_ram_bus_data[28], Y1_d1_in_a_write_cycle);

ext_ram_bus_data[28] = BIDIR(ext_ram_bus_data[28]_tri_out);

--A1L89 is ext_ram_bus_data~4

--operation mode is bidir

A1L89 = ext_ram_bus_data[27];

--ext_ram_bus_data[27] is ext_ram_bus_data[27]

--operation mode is bidir

ext_ram_bus_data[27]_tri_out = TRI(Y1_d1_outgoing_ext_ram_bus_data[27], Y1_d1_in_a_write_cycle);

ext_ram_bus_data[27] = BIDIR(ext_ram_bus_data[27]_tri_out);

--A1L90 is ext_ram_bus_data~5

--operation mode is bidir

A1L90 = ext_ram_bus_data[26];

--ext_ram_bus_data[26] is ext_ram_bus_data[26]

--operation mode is bidir

ext_ram_bus_data[26]_tri_out = TRI(Y1_d1_outgoing_ext_ram_bus_data[26], Y1_d1_in_a_write_cycle);

ext_ram_bus_data[26] = BIDIR(ext_ram_bus_data[26]_tri_out);

--A1L91 is ext_ram_bus_data~6

--operation mode is bidir

A1L91 = ext_ram_bus_data[25];

--ext_ram_bus_data[25] is ext_ram_bus_data[25]

--operation mode is bidir

ext_ram_bus_data[25]_tri_out = TRI(Y1_d1_outgoing_ext_ram_bus_data[25], Y1_d1_in_a_write_cycle);

ext_ram_bus_data[25] = BIDIR(ext_ram_bus_data[25]_tri_out);

--A1L92 is ext_ram_bus_data~7

--operation mode is bidir

A1L92 = ext_ram_bus_data[24];

--ext_ram_bus_data[24] is ext_ram_bus_data[24]

--operation mode is bidir

ext_ram_bus_data[24]_tri_out = TRI(Y1_d1_outgoing_ext_ram_bus_data[24], Y1_d1_in_a_write_cycle);

ext_ram_bus_data[24] = BIDIR(ext_ram_bus_data[24]_tri_out);

--A1L93 is ext_ram_bus_data~8

--operation mode is bidir

A1L93 = ext_ram_bus_data[23];

--ext_ram_bus_data[23] is ext_ram_bus_data[23]

--operation mode is bidir

ext_ram_bus_data[23]_tri_out = TRI(Y1_d1_outgoing_ext_ram_bus_data[23], Y1_d1_in_a_write_cycle);

ext_ram_bus_data[23] = BIDIR(ext_ram_bus_data[23]_tri_out);

--A1L94 is ext_ram_bus_data~9

--operation mode is bidir

A1L94 = ext_ram_bus_data[22];

--ext_ram_bus_data[22] is ext_ram_bus_data[22]

--operation mode is bidir

ext_ram_bus_data[22]_tri_out = TRI(Y1_d1_outgoing_ext_ram_bus_data[22], Y1_d1_in_a_write_cycle);

ext_ram_bus_data[22] = BIDIR(ext_ram_bus_data[22]_tri_out);

--A1L95 is ext_ram_bus_data~10

--operation mode is bidir

A1L95 = ext_ram_bus_data[21];

--ext_ram_bus_data[21] is ext_ram_bus_data[21]

--operation mode is bidir

ext_ram_bus_data[21]_tri_out = TRI(Y1_d1_outgoing_ext_ram_bus_data[21], Y1_d1_in_a_write_cycle);

ext_ram_bus_data[21] = BIDIR(ext_ram_bus_data[21]_tri_out);

--A1L96 is ext_ram_bus_data~11

--operation mode is bidir

A1L96 = ext_ram_bus_data[20];

--ext_ram_bus_data[20] is ext_ram_bus_data[20]

--operation mode is bidir

ext_ram_bus_data[20]_tri_out = TRI(Y1_d1_outgoing_ext_ram_bus_data[20], Y1_d1_in_a_write_cycle);

ext_ram_bus_data[20] = BIDIR(ext_ram_bus_data[20]_tri_out);

--A1L97 is ext_ram_bus_data~12

--operation mode is bidir

A1L97 = ext_ram_bus_data[19];

--ext_ram_bus_data[19] is ext_ram_bus_data[19]

--operation mode is bidir

ext_ram_bus_data[19]_tri_out = TRI(Y1_d1_outgoing_ext_ram_bus_data[19], Y1_d1_in_a_write_cycle);

ext_ram_bus_data[19] = BIDIR(ext_ram_bus_data[19]_tri_out);

--A1L98 is ext_ram_bus_data~13

--operation mode is bidir

A1L98 = ext_ram_bus_data[18];

--ext_ram_bus_data[18] is ext_ram_bus_data[18]

--operation mode is bidir

ext_ram_bus_data[18]_tri_out = TRI(Y1_d1_outgoing_ext_ram_bus_data[18], Y1_d1_in_a_write_cycle);

ext_ram_bus_data[18] = BIDIR(ext_ram_bus_data[18]_tri_out);

--A1L99 is ext_ram_bus_data~14

--operation mode is bidir

A1L99 = ext_ram_bus_data[17];

--ext_ram_bus_data[17] is ext_ram_bus_data[17]

--operation mode is bidir

ext_ram_bus_data[17]_tri_out = TRI(Y1_d1_outgoing_ext_ram_bus_data[17], Y1_d1_in_a_write_cycle);

ext_ram_bus_data[17] = BIDIR(ext_ram_bus_data[17]_tri_out);

--A1L100 is ext_ram_bus_data~15

--operation mode is bidir

A1L100 = ext_ram_bus_data[16];

--ext_ram_bus_data[16] is ext_ram_bus_data[16]

--operation mode is bidir

ext_ram_bus_data[16]_tri_out = TRI(Y1_d1_outgoing_ext_ram_bus_data[16], Y1_d1_in_a_write_cycle);

ext_ram_bus_data[16] = BIDIR(ext_ram_bus_data[16]_tri_out);

--A1L101 is ext_ram_bus_data~16

--operation mode is bidir

A1L101 = ext_ram_bus_data[15];

--ext_ram_bus_data[15] is ext_ram_bus_data[15]

--operation mode is bidir

ext_ram_bus_data[15]_tri_out = TRI(Y1_d1_outgoing_ext_ram_bus_data[15], Y1_d1_in_a_write_cycle);

ext_ram_bus_data[15] = BIDIR(ext_ram_bus_data[15]_tri_out);

--A1L102 is ext_ram_bus_data~17

--operation mode is bidir

A1L102 = ext_ram_bus_data[14];

--ext_ram_bus_data[14] is ext_ram_bus_data[14]

--operation mode is bidir

ext_ram_bus_data[14]_tri_out = TRI(Y1_d1_outgoing_ext_ram_bus_data[14], Y1_d1_in_a_write_cycle);

ext_ram_bus_data[14] = BIDIR(ext_ram_bus_data[14]_tri_out);

--A1L103 is ext_ram_bus_data~18

--operation mode is bidir

A1L103 = ext_ram_bus_data[13];

--ext_ram_bus_data[13] is ext_ram_bus_data[13]

--operation mode is bidir

ext_ram_bus_data[13]_tri_out = TRI(Y1_d1_outgoing_ext_ram_bus_data[13], Y1_d1_in_a_write_cycle);

ext_ram_bus_data[13] = BIDIR(ext_ram_bus_data[13]_tri_out);

--A1L104 is ext_ram_bus_data~19

--operation mode is bidir

A1L104 = ext_ram_bus_data[12];

--ext_ram_bus_data[12] is ext_ram_bus_data[12]

--operation mode is bidir

ext_ram_bus_data[12]_tri_out = TRI(Y1_d1_outgoing_ext_ram_bus_data[12], Y1_d1_in_a_write_cycle);

ext_ram_bus_data[12] = BIDIR(ext_ram_bus_data[12]_tri_out);

--A1L105 is ext_ram_bus_data~20

--operation mode is bidir

A1L105 = ext_ram_bus_data[11];

--ext_ram_bus_data[11] is ext_ram_bus_data[11]

--operation mode is bidir

ext_ram_bus_data[11]_tri_out = TRI(Y1_d1_outgoing_ext_ram_bus_data[11], Y1_d1_in_a_write_cycle);

ext_ram_bus_data[11] = BIDIR(ext_ram_bus_data[11]_tri_out);

--A1L106 is ext_ram_bus_data~21

--operation mode is bidir

A1L106 = ext_ram_bus_data[10];

--ext_ram_bus_data[10] is ext_ram_bus_data[10]

--operation mode is bidir

ext_ram_bus_data[10]_tri_out = TRI(Y1_d1_outgoing_ext_ram_bus_data[10], Y1_d1_in_a_write_cycle);

ext_ram_bus_data[10] = BIDIR(ext_ram_bus_data[10]_tri_out);

--A1L107 is ext_ram_bus_data~22

--operation mode is bidir

A1L107 = ext_ram_bus_data[9];

--ext_ram_bus_data[9] is ext_ram_bus_data[9]

--operation mode is bidir

ext_ram_bus_data[9]_tri_out = TRI(Y1_d1_outgoing_ext_ram_bus_data[9], Y1_d1_in_a_write_cycle);

ext_ram_bus_data[9] = BIDIR(ext_ram_bus_data[9]_tri_out);

--A1L108 is ext_ram_bus_data~23

--operation mode is bidir

A1L108 = ext_ram_bus_data[8];

--ext_ram_bus_data[8] is ext_ram_bus_data[8]

--operation mode is bidir

ext_ram_bus_data[8]_tri_out = TRI(Y1_d1_outgoing_ext_ram_bus_data[8], Y1_d1_in_a_write_cycle);

ext_ram_bus_data[8] = BIDIR(ext_ram_bus_data[8]_tri_out);

--A1L109 is ext_ram_bus_data~24

--operation mode is bidir

A1L109 = ext_ram_bus_data[7];

--ext_ram_bus_data[7] is ext_ram_bus_data[7]

--operation mode is bidir

ext_ram_bus_data[7]_tri_out = TRI(Y1_d1_outgoing_ext_ram_bus_data[7], Y1_d1_in_a_write_cycle);

ext_ram_bus_data[7] = BIDIR(ext_ram_bus_data[7]_tri_out);

--A1L110 is ext_ram_bus_data~25

--operation mode is bidir

A1L110 = ext_ram_bus_data[6];

--ext_ram_bus_data[6] is ext_ram_bus_data[6]

--operation mode is bidir

ext_ram_bus_data[6]_tri_out = TRI(Y1_d1_outgoing_ext_ram_bus_data[6], Y1_d1_in_a_write_cycle);

ext_ram_bus_data[6] = BIDIR(ext_ram_bus_data[6]_tri_out);

--A1L111 is ext_ram_bus_data~26

--operation mode is bidir

A1L111 = ext_ram_bus_data[5];

--ext_ram_bus_data[5] is ext_ram_bus_data[5]

--operation mode is bidir

ext_ram_bus_data[5]_tri_out = TRI(Y1_d1_outgoing_ext_ram_bus_data[5], Y1_d1_in_a_write_cycle);

ext_ram_bus_data[5] = BIDIR(ext_ram_bus_data[5]_tri_out);

--A1L112 is ext_ram_bus_data~27

--operation mode is bidir

A1L112 = ext_ram_bus_data[4];

--ext_ram_bus_data[4] is ext_ram_bus_data[4]

--operation mode is bidir

ext_ram_bus_data[4]_tri_out = TRI(Y1_d1_outgoing_ext_ram_bus_data[4], Y1_d1_in_a_write_cycle);

ext_ram_bus_data[4] = BIDIR(ext_ram_bus_data[4]_tri_out);

--A1L113 is ext_ram_bus_data~28

--operation mode is bidir

A1L113 = ext_ram_bus_data[3];

--ext_ram_bus_data[3] is ext_ram_bus_data[3]

--operation mode is bidir

ext_ram_bus_data[3]_tri_out = TRI(Y1_d1_outgoing_ext_ram_bus_data[3], Y1_d1_in_a_write_cycle);

ext_ram_bus_data[3] = BIDIR(ext_ram_bus_data[3]_tri_out);

--A1L114 is ext_ram_bus_data~29

--operation mode is bidir

A1L114 = ext_ram_bus_data[2];

--ext_ram_bus_data[2] is ext_ram_bus_data[2]

--operation mode is bidir

ext_ram_bus_data[2]_tri_out = TRI(Y1_d1_outgoing_ext_ram_bus_data[2], Y1_d1_in_a_write_cycle);

ext_ram_bus_data[2] = BIDIR(ext_ram_bus_data[2]_tri_out);

--A1L115 is ext_ram_bus_data~30

--operation mode is bidir

A1L115 = ext_ram_bus_data[1];

--ext_ram_bus_data[1] is ext_ram_bus_data[1]

--operation mode is bidir

ext_ram_bus_data[1]_tri_out = TRI(Y1_d1_outgoing_ext_ram_bus_data[1], Y1_d1_in_a_write_cycle);

ext_ram_bus_data[1] = BIDIR(ext_ram_bus_data[1]_tri_out);

--A1L116 is ext_ram_bus_data~31

--operation mode is bidir

A1L116 = ext_ram_bus_data[0];

--ext_ram_bus_data[0] is ext_ram_bus_data[0]

--operation mode is bidir

ext_ram_bus_data[0]_tri_out = TRI(Y1_d1_outgoing_ext_ram_bus_data[0], Y1_d1_in_a_write_cycle);

ext_ram_bus_data[0] = BIDIR(ext_ram_bus_data[0]_tri_out);

--A1L134 is LCD_data_to_and_from_the_lcd_display~0

--operation mode is bidir

A1L134 = LCD_data_to_and_from_the_lcd_display[7];

--LCD_data_to_and_from_the_lcd_display[7] is LCD_data_to_and_from_the_lcd_display[7]

--operation mode is bidir

LCD_data_to_and_from_the_lcd_display[7]_tri_out = TRI(S1_M_st_data[7], !S1_M_alu_result[2]);

LCD_data_to_and_from_the_lcd_display[7] = BIDIR(LCD_data_to_and_from_the_lcd_display[7]_tri_out);

--A1L135 is LCD_data_to_and_from_the_lcd_display~1

--operation mode is bidir

A1L135 = LCD_data_to_and_from_the_lcd_display[6];

--LCD_data_to_and_from_the_lcd_display[6] is LCD_data_to_and_from_the_lcd_display[6]

--operation mode is bidir

LCD_data_to_and_from_the_lcd_display[6]_tri_out = TRI(S1_M_st_data[6], !S1_M_alu_result[2]);

LCD_data_to_and_from_the_lcd_display[6] = BIDIR(LCD_data_to_and_from_the_lcd_display[6]_tri_out);

--A1L136 is LCD_data_to_and_from_the_lcd_display~2

--operation mode is bidir

A1L136 = LCD_data_to_and_from_the_lcd_display[5];

--LCD_data_to_and_from_the_lcd_display[5] is LCD_data_to_and_from_the_lcd_display[5]

--operation mode is bidir

LCD_data_to_and_from_the_lcd_display[5]_tri_out = TRI(S1_M_st_data[5], !S1_M_alu_result[2]);

LCD_data_to_and_from_the_lcd_display[5] = BIDIR(LCD_data_to_and_from_the_lcd_display[5]_tri_out);

--A1L137 is LCD_data_to_and_from_the_lcd_display~3

--operation mode is bidir

A1L137 = LCD_data_to_and_from_the_lcd_display[4];

--LCD_data_to_and_from_the_lcd_display[4] is LCD_data_to_and_from_the_lcd_display[4]

--operation mode is bidir

LCD_data_to_and_from_the_lcd_display[4]_tri_out = TRI(S1_M_st_data[4], !S1_M_alu_result[2]);

LCD_data_to_and_from_the_lcd_display[4] = BIDIR(LCD_data_to_and_from_the_lcd_display[4]_tri_out);

--A1L138 is LCD_data_to_and_from_the_lcd_display~4

--operation mode is bidir

A1L138 = LCD_data_to_and_from_the_lcd_display[3];

--LCD_data_to_and_from_the_lcd_display[3] is LCD_data_to_and_from_the_lcd_display[3]

--operation mode is bidir

LCD_data_to_and_from_the_lcd_display[3]_tri_out = TRI(S1_M_st_data[3], !S1_M_alu_result[2]);

LCD_data_to_and_from_the_lcd_display[3] = BIDIR(LCD_data_to_and_from_the_lcd_display[3]_tri_out);

--A1L139 is LCD_data_to_and_from_the_lcd_display~5

--operation mode is bidir

A1L139 = LCD_data_to_and_from_the_lcd_display[2];

--LCD_data_to_and_from_the_lcd_display[2] is LCD_data_to_and_from_the_lcd_display[2]

--operation mode is bidir

LCD_data_to_and_from_the_lcd_display[2]_tri_out = TRI(S1_M_st_data[2], !S1_M_alu_result[2]);

LCD_data_to_and_from_the_lcd_display[2] = BIDIR(LCD_data_to_and_from_the_lcd_display[2]_tri_out);

--A1L140 is LCD_data_to_and_from_the_lcd_display~6

--operation mode is bidir

A1L140 = LCD_data_to_and_from_the_lcd_display[1];

--LCD_data_to_and_from_the_lcd_display[1] is LCD_data_to_and_from_the_lcd_display[1]

--operation mode is bidir

LCD_data_to_and_from_the_lcd_display[1]_tri_out = TRI(S1_M_st_data[1], !S1_M_alu_result[2]);

LCD_data_to_and_from_the_lcd_display[1] = BIDIR(LCD_data_to_and_from_the_lcd_display[1]_tri_out);

--A1L141 is LCD_data_to_and_from_the_lcd_display~7

--operation mode is bidir

A1L141 = LCD_data_to_and_from_the_lcd_display[0];

--LCD_data_to_and_from_the_lcd_display[0] is LCD_data_to_and_from_the_lcd_display[0]

--operation mode is bidir

LCD_data_to_and_from_the_lcd_display[0]_tri_out = TRI(S1_M_st_data[0], !S1_M_alu_result[2]);

LCD_data_to_and_from_the_lcd_display[0] = BIDIR(LCD_data_to_and_from_the_lcd_display[0]_tri_out);

--A1L237 is zs_dq_to_and_from_the_sdram~0

--operation mode is bidir

A1L237 = zs_dq_to_and_from_the_sdram[31];

--zs_dq_to_and_from_the_sdram[31] is zs_dq_to_and_from_the_sdram[31]

--operation mode is bidir

zs_dq_to_and_from_the_sdram[31]_tri_out = TRI(KB1_m_data[31], KB1_oe);

zs_dq_to_and_from_the_sdram[31] = BIDIR(zs_dq_to_and_from_the_sdram[31]_tri_out);

--A1L238 is zs_dq_to_and_from_the_sdram~1

--operation mode is bidir

A1L238 = zs_dq_to_and_from_the_sdram[30];

--zs_dq_to_and_from_the_sdram[30] is zs_dq_to_and_from_the_sdram[30]

--operation mode is bidir

zs_dq_to_and_from_the_sdram[30]_tri_out = TRI(KB1_m_data[30], KB1_oe);

zs_dq_to_and_from_the_sdram[30] = BIDIR(zs_dq_to_and_from_the_sdram[30]_tri_out);

--A1L239 is zs_dq_to_and_from_the_sdram~2

--operation mode is bidir

A1L239 = zs_dq_to_and_from_the_sdram[29];

--zs_dq_to_and_from_the_sdram[29] is zs_dq_to_and_from_the_sdram[29]

--operation mode is bidir

zs_dq_to_and_from_the_sdram[29]_tri_out = TRI(KB1_m_data[29], KB1_oe);

zs_dq_to_and_from_the_sdram[29] = BIDIR(zs_dq_to_and_from_the_sdram[29]_tri_out);

--A1L240 is zs_dq_to_and_from_the_sdram~3

--operation mode is bidir

A1L240 = zs_dq_to_and_from_the_sdram[28];

--zs_dq_to_and_from_the_sdram[28] is zs_dq_to_and_from_the_sdram[28]

--operation mode is bidir

zs_dq_to_and_from_the_sdram[28]_tri_out = TRI(KB1_m_data[28], KB1_oe);

zs_dq_to_and_from_the_sdram[28] = BIDIR(zs_dq_to_and_from_the_sdram[28]_tri_out);

--A1L241 is zs_dq_to_and_from_the_sdram~4

--operation mode is bidir

A1L241 = zs_dq_to_and_from_the_sdram[27];

--zs_dq_to_and_from_the_sdram[27] is zs_dq_to_and_from_the_sdram[27]

--operation mode is bidir

zs_dq_to_and_from_the_sdram[27]_tri_out = TRI(KB1_m_data[27], KB1_oe);

zs_dq_to_and_from_the_sdram[27] = BIDIR(zs_dq_to_and_from_the_sdram[27]_tri_out);

--A1L242 is zs_dq_to_and_from_the_sdram~5

--operation mode is bidir

A1L242 = zs_dq_to_and_from_the_sdram[26];

--zs_dq_to_and_from_the_sdram[26] is zs_dq_to_and_from_the_sdram[26]

--operation mode is bidir

zs_dq_to_and_from_the_sdram[26]_tri_out = TRI(KB1_m_data[26], KB1_oe);

zs_dq_to_and_from_the_sdram[26] = BIDIR(zs_dq_to_and_from_the_sdram[26]_tri_out);

--A1L243 is zs_dq_to_and_from_the_sdram~6

--operation mode is bidir

A1L243 = zs_dq_to_and_from_the_sdram[25];

--zs_dq_to_and_from_the_sdram[25] is zs_dq_to_and_from_the_sdram[25]

--operation mode is bidir

zs_dq_to_and_from_the_sdram[25]_tri_out = TRI(KB1_m_data[25], KB1_oe);

zs_dq_to_and_from_the_sdram[25] = BIDIR(zs_dq_to_and_from_the_sdram[25]_tri_out);

--A1L244 is zs_dq_to_and_from_the_sdram~7

--operation mode is bidir

A1L244 = zs_dq_to_and_from_the_sdram[24];

--zs_dq_to_and_from_the_sdram[24] is zs_dq_to_and_from_the_sdram[24]

--operation mode is bidir

zs_dq_to_and_from_the_sdram[24]_tri_out = TRI(KB1_m_data[24], KB1_oe);

zs_dq_to_and_from_the_sdram[24] = BIDIR(zs_dq_to_and_from_the_sdram[24]_tri_out);

--A1L245 is zs_dq_to_and_from_the_sdram~8

--operation mode is bidir

A1L245 = zs_dq_to_and_from_the_sdram[23];

--zs_dq_to_and_from_the_sdram[23] is zs_dq_to_and_from_the_sdram[23]

--operation mode is bidir

zs_dq_to_and_from_the_sdram[23]_tri_out = TRI(KB1_m_data[23], KB1_oe);

zs_dq_to_and_from_the_sdram[23] = BIDIR(zs_dq_to_and_from_the_sdram[23]_tri_out);

--A1L246 is zs_dq_to_and_from_the_sdram~9

--operation mode is bidir

A1L246 = zs_dq_to_and_from_the_sdram[22];

--zs_dq_to_and_from_the_sdram[22] is zs_dq_to_and_from_the_sdram[22]

--operation mode is bidir

zs_dq_to_and_from_the_sdram[22]_tri_out = TRI(KB1_m_data[22], KB1_oe);

zs_dq_to_and_from_the_sdram[22] = BIDIR(zs_dq_to_and_from_the_sdram[22]_tri_out);

--A1L247 is zs_dq_to_and_from_the_sdram~10

--operation mode is bidir

A1L247 = zs_dq_to_and_from_the_sdram[21];

--zs_dq_to_and_from_the_sdram[21] is zs_dq_to_and_from_the_sdram[21]

--operation mode is bidir

zs_dq_to_and_from_the_sdram[21]_tri_out = TRI(KB1_m_data[21], KB1_oe);

zs_dq_to_and_from_the_sdram[21] = BIDIR(zs_dq_to_and_from_the_sdram[21]_tri_out);

--A1L248 is zs_dq_to_and_from_the_sdram~11

--operation mode is bidir

A1L248 = zs_dq_to_and_from_the_sdram[20];

--zs_dq_to_and_from_the_sdram[20] is zs_dq_to_and_from_the_sdram[20]

--operation mode is bidir

zs_dq_to_and_from_the_sdram[20]_tri_out = TRI(KB1_m_data[20], KB1_oe);

zs_dq_to_and_from_the_sdram[20] = BIDIR(zs_dq_to_and_from_the_sdram[20]_tri_out);

--A1L249 is zs_dq_to_and_from_the_sdram~12

--operation mode is bidir

A1L249 = zs_dq_to_and_from_the_sdram[19];

--zs_dq_to_and_from_the_sdram[19] is zs_dq_to_and_from_the_sdram[19]

--operation mode is bidir

zs_dq_to_and_from_the_sdram[19]_tri_out = TRI(KB1_m_data[19], KB1_oe);

zs_dq_to_and_from_the_sdram[19] = BIDIR(zs_dq_to_and_from_the_sdram[19]_tri_out);

--A1L250 is zs_dq_to_and_from_the_sdram~13

--operation mode is bidir

A1L250 = zs_dq_to_and_from_the_sdram[18];

--zs_dq_to_and_from_the_sdram[18] is zs_dq_to_and_from_the_sdram[18]

--operation mode is bidir

zs_dq_to_and_from_the_sdram[18]_tri_out = TRI(KB1_m_data[18], KB1_oe);

zs_dq_to_and_from_the_sdram[18] = BIDIR(zs_dq_to_and_from_the_sdram[18]_tri_out);

--A1L251 is zs_dq_to_and_from_the_sdram~14

--operation mode is bidir

A1L251 = zs_dq_to_and_from_the_sdram[17];

--zs_dq_to_and_from_the_sdram[17] is zs_dq_to_and_from_the_sdram[17]

--operation mode is bidir

zs_dq_to_and_from_the_sdram[17]_tri_out = TRI(KB1_m_data[17], KB1_oe);

zs_dq_to_and_from_the_sdram[17] = BIDIR(zs_dq_to_and_from_the_sdram[17]_tri_out);

--A1L252 is zs_dq_to_and_from_the_sdram~15

--operation mode is bidir

A1L252 = zs_dq_to_and_from_the_sdram[16];

--zs_dq_to_and_from_the_sdram[16] is zs_dq_to_and_from_the_sdram[16]

--operation mode is bidir

zs_dq_to_and_from_the_sdram[16]_tri_out = TRI(KB1_m_data[16], KB1_oe);

zs_dq_to_and_from_the_sdram[16] = BIDIR(zs_dq_to_and_from_the_sdram[16]_tri_out);

--A1L253 is zs_dq_to_and_from_the_sdram~16

--operation mode is bidir

A1L253 = zs_dq_to_and_from_the_sdram[15];

--zs_dq_to_and_from_the_sdram[15] is zs_dq_to_and_from_the_sdram[15]

--operation mode is bidir

zs_dq_to_and_from_the_sdram[15]_tri_out = TRI(KB1_m_data[15], KB1_oe);

zs_dq_to_and_from_the_sdram[15] = BIDIR(zs_dq_to_and_from_the_sdram[15]_tri_out);

--A1L254 is zs_dq_to_and_from_the_sdram~17

--operation mode is bidir

A1L254 = zs_dq_to_and_from_the_sdram[14];

--zs_dq_to_and_from_the_sdram[14] is zs_dq_to_and_from_the_sdram[14]

--operation mode is bidir

zs_dq_to_and_from_the_sdram[14]_tri_out = TRI(KB1_m_data[14], KB1_oe);

zs_dq_to_and_from_the_sdram[14] = BIDIR(zs_dq_to_and_from_the_sdram[14]_tri_out);

--A1L255 is zs_dq_to_and_from_the_sdram~18

--operation mode is bidir

A1L255 = zs_dq_to_and_from_the_sdram[13];

--zs_dq_to_and_from_the_sdram[13] is zs_dq_to_and_from_the_sdram[13]

--operation mode is bidir

zs_dq_to_and_from_the_sdram[13]_tri_out = TRI(KB1_m_data[13], KB1_oe);

zs_dq_to_and_from_the_sdram[13] = BIDIR(zs_dq_to_and_from_the_sdram[13]_tri_out);

--A1L256 is zs_dq_to_and_from_the_sdram~19

--operation mode is bidir

A1L256 = zs_dq_to_and_from_the_sdram[12];

--zs_dq_to_and_from_the_sdram[12] is zs_dq_to_and_from_the_sdram[12]

--operation mode is bidir

zs_dq_to_and_from_the_sdram[12]_tri_out = TRI(KB1_m_data[12], KB1_oe);

zs_dq_to_and_from_the_sdram[12] = BIDIR(zs_dq_to_and_from_the_sdram[12]_tri_out);

--A1L257 is zs_dq_to_and_from_the_sdram~20

--operation mode is bidir

A1L257 = zs_dq_to_and_from_the_sdram[11];

--zs_dq_to_and_from_the_sdram[11] is zs_dq_to_and_from_the_sdram[11]

--operation mode is bidir

zs_dq_to_and_from_the_sdram[11]_tri_out = TRI(KB1_m_data[11], KB1_oe);

zs_dq_to_and_from_the_sdram[11] = BIDIR(zs_dq_to_and_from_the_sdram[11]_tri_out);

--A1L258 is zs_dq_to_and_from_the_sdram~21

--operation mode is bidir

A1L258 = zs_dq_to_and_from_the_sdram[10];

--zs_dq_to_and_from_the_sdram[10] is zs_dq_to_and_from_the_sdram[10]

--operation mode is bidir

zs_dq_to_and_from_the_sdram[10]_tri_out = TRI(KB1_m_data[10], KB1_oe);

zs_dq_to_and_from_the_sdram[10] = BIDIR(zs_dq_to_and_from_the_sdram[10]_tri_out);

--A1L259 is zs_dq_to_and_from_the_sdram~22

--operation mode is bidir

A1L259 = zs_dq_to_and_from_the_sdram[9];

--zs_dq_to_and_from_the_sdram[9] is zs_dq_to_and_from_the_sdram[9]

--operation mode is bidir

zs_dq_to_and_from_the_sdram[9]_tri_out = TRI(KB1_m_data[9], KB1_oe);

zs_dq_to_and_from_the_sdram[9] = BIDIR(zs_dq_to_and_from_the_sdram[9]_tri_out);

--A1L260 is zs_dq_to_and_from_the_sdram~23

--operation mode is bidir

A1L260 = zs_dq_to_and_from_the_sdram[8];

--zs_dq_to_and_from_the_sdram[8] is zs_dq_to_and_from_the_sdram[8]

--operation mode is bidir

zs_dq_to_and_from_the_sdram[8]_tri_out = TRI(KB1_m_data[8], KB1_oe);

zs_dq_to_and_from_the_sdram[8] = BIDIR(zs_dq_to_and_from_the_sdram[8]_tri_out);

--A1L261 is zs_dq_to_and_from_the_sdram~24

--operation mode is bidir

A1L261 = zs_dq_to_and_from_the_sdram[7];

--zs_dq_to_and_from_the_sdram[7] is zs_dq_to_and_from_the_sdram[7]

--operation mode is bidir

zs_dq_to_and_from_the_sdram[7]_tri_out = TRI(KB1_m_data[7], KB1_oe);

zs_dq_to_and_from_the_sdram[7] = BIDIR(zs_dq_to_and_from_the_sdram[7]_tri_out);

--A1L262 is zs_dq_to_and_from_the_sdram~25

--operation mode is bidir

A1L262 = zs_dq_to_and_from_the_sdram[6];

--zs_dq_to_and_from_the_sdram[6] is zs_dq_to_and_from_the_sdram[6]

--operation mode is bidir

zs_dq_to_and_from_the_sdram[6]_tri_out = TRI(KB1_m_data[6], KB1_oe);

zs_dq_to_and_from_the_sdram[6] = BIDIR(zs_dq_to_and_from_the_sdram[6]_tri_out);

--A1L263 is zs_dq_to_and_from_the_sdram~26

--operation mode is bidir

A1L263 = zs_dq_to_and_from_the_sdram[5];

--zs_dq_to_and_from_the_sdram[5] is zs_dq_to_and_from_the_sdram[5]

--operation mode is bidir

zs_dq_to_and_from_the_sdram[5]_tri_out = TRI(KB1_m_data[5], KB1_oe);

zs_dq_to_and_from_the_sdram[5] = BIDIR(zs_dq_to_and_from_the_sdram[5]_tri_out);

--A1L264 is zs_dq_to_and_from_the_sdram~27

--operation mode is bidir

A1L264 = zs_dq_to_and_from_the_sdram[4];

--zs_dq_to_and_from_the_sdram[4] is zs_dq_to_and_from_the_sdram[4]

--operation mode is bidir

zs_dq_to_and_from_the_sdram[4]_tri_out = TRI(KB1_m_data[4], KB1_oe);

zs_dq_to_and_from_the_sdram[4] = BIDIR(zs_dq_to_and_from_the_sdram[4]_tri_out);

--A1L265 is zs_dq_to_and_from_the_sdram~28

--operation mode is bidir

A1L265 = zs_dq_to_and_from_the_sdram[3];

--zs_dq_to_and_from_the_sdram[3] is zs_dq_to_and_from_the_sdram[3]

--operation mode is bidir

zs_dq_to_and_from_the_sdram[3]_tri_out = TRI(KB1_m_data[3], KB1_oe);

zs_dq_to_and_from_the_sdram[3] = BIDIR(zs_dq_to_and_from_the_sdram[3]_tri_out);

--A1L266 is zs_dq_to_and_from_the_sdram~29

--operation mode is bidir

A1L266 = zs_dq_to_and_from_the_sdram[2];

--zs_dq_to_and_from_the_sdram[2] is zs_dq_to_and_from_the_sdram[2]

--operation mode is bidir

zs_dq_to_and_from_the_sdram[2]_tri_out = TRI(KB1_m_data[2], KB1_oe);

zs_dq_to_and_from_the_sdram[2] = BIDIR(zs_dq_to_and_from_the_sdram[2]_tri_out);

--A1L267 is zs_dq_to_and_from_the_sdram~30

--operation mode is bidir

A1L267 = zs_dq_to_and_from_the_sdram[1];

--zs_dq_to_and_from_the_sdram[1] is zs_dq_to_and_from_the_sdram[1]

--operation mode is bidir

zs_dq_to_and_from_the_sdram[1]_tri_out = TRI(KB1_m_data[1], KB1_oe);

zs_dq_to_and_from_the_sdram[1] = BIDIR(zs_dq_to_and_from_the_sdram[1]_tri_out);

--A1L268 is zs_dq_to_and_from_the_sdram~31

--operation mode is bidir

A1L268 = zs_dq_to_and_from_the_sdram[0];

--zs_dq_to_and_from_the_sdram[0] is zs_dq_to_and_from_the_sdram[0]

--operation mode is bidir

zs_dq_to_and_from_the_sdram[0]_tri_out = TRI(KB1_m_data[0], KB1_oe);

zs_dq_to_and_from_the_sdram[0] = BIDIR(zs_dq_to_and_from_the_sdram[0]_tri_out);

--S1L979 is std_1c20:inst|cpu:the_cpu|ic_fill_ap_offset[0]~$wirecell

--operation mode is normal

S1L979 = AMPP_FUNCTION(S1_ic_fill_ap_offset[0]);