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-- and other software and tools, and its AMPP partner logic
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--QC2__clk0 is std_1c20:inst|sdram_pll:the_sdram_pll|altpllsdram_pll:the_pll|altpll:altpll_component|_clk0 at PLL_2

QC2__clk0 = PLL.CLK0(.FBIN(), .ENA(), .CLKSWITCH(), .ARESET(), .PFDENA(), .SCANCLK(), .SCANACLR(), .SCANDATA(), .COMPARATOR(), .INCLK(PLD_CLKFB), .INCLK(), .CLKENA(), .CLKENA(), .CLKENA(), .CLKENA(), .CLKENA(), .CLKENA(), .EXTCLKENA(), .EXTCLKENA(), .EXTCLKENA(), .EXTCLKENA());

--QC2__extclk0 is std_1c20:inst|sdram_pll:the_sdram_pll|altpllsdram_pll:the_pll|altpll:altpll_component|_extclk0 at PLL_2

QC2__extclk0 = PLL.EXTCLK0(.FBIN(), .ENA(), .CLKSWITCH(), .ARESET(), .PFDENA(), .SCANCLK(), .SCANACLR(), .SCANDATA(), .COMPARATOR(), .INCLK(PLD_CLKFB), .INCLK(), .CLKENA(), .CLKENA(), .CLKENA(), .CLKENA(), .CLKENA(), .CLKENA(), .EXTCLKENA(), .EXTCLKENA(), .EXTCLKENA(), .EXTCLKENA());

--QC1__extclk0 is std_1c20:inst|connector_pll:the_connector_pll|altpllconnector_pll:the_pll|altpll:altpll_component|_extclk0 at PLL_1

QC1__extclk0 = PLL.EXTCLK0(.FBIN(), .ENA(), .CLKSWITCH(), .ARESET(), .PFDENA(), .SCANCLK(), .SCANACLR(), .SCANDATA(), .COMPARATOR(), .INCLK(PLD_CLOCKINPUT[1]), .INCLK(), .CLKENA(), .CLKENA(), .CLKENA(), .CLKENA(), .CLKENA(), .CLKENA(), .EXTCLKENA(), .EXTCLKENA(), .EXTCLKENA(), .EXTCLKENA());

--Y1L862 is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ior_n_to_the_lan91c111~COMB_OUT at LC_X30_Y26_N6

--operation mode is normal

Y1L862 = !Y1_ext_ram_bus_avalon_slave_begins_xfer & (Y1L742 # Y1L739 & S1_internal_d_read);

--Y1L1033 is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|write_n_to_the_ext_flash~COMB_OUT at LC_X31_Y27_N1

--operation mode is normal

Y1L1033 = !Y1_ext_ram_bus_avalon_slave_begins_xfer & Y1L372 & (Y1L396Q $ !Y1L1010);

--Y1L867 is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|iow_n_to_the_lan91c111~COMB_OUT at LC_X31_Y26_N2

--operation mode is normal

Y1L867 = Y1L112 & Y1L865 & (Y1L28 # Y1L31);

--Y1L1017 is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|read_n_to_the_ext_flash~COMB_OUT at LC_X30_Y27_N1

--operation mode is normal

Y1L1017 = !Y1_ext_ram_bus_avalon_slave_begins_xfer & !Y1L396Q & (Y1L770 # Y1L122);

--Y1L1022 is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|read_n_to_the_ext_ram~COMB_OUT at LC_X31_Y22_N2

--operation mode is normal

Y1L1022 = Y1L1020 # Y1L1007 & (Y1L49 # Y1L46);

--Y1L1026 is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|select_n_to_the_ext_ram~COMB_OUT at LC_X31_Y23_N1

--operation mode is normal

Y1L1026 = Y1L799 # Y1L104 & (Y1L51 # Y1L53);

--Y1L1035 is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|write_n_to_the_ext_ram_local~4 at LC_X32_Y22_N8

--operation mode is normal

Y1L1035 = S1_internal_d_write & Y1L104 & (Y1L51 # Y1L53);

--Y1_write_n_to_the_ext_ram_local is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|write_n_to_the_ext_ram_local at LC_X32_Y22_N8

--operation mode is normal

Y1_write_n_to_the_ext_ram_local = DFFEAS(Y1L1035, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--Y1L1040 is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|write_n_to_the_ext_ram~0 at LC_X43_Y22_N9

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

Y1_write_n_to_the_ext_ram_mask_qfbk = Y1_write_n_to_the_ext_ram_mask;

Y1L1040 = Y1_write_n_to_the_ext_ram_local & (!Y1_write_n_to_the_ext_ram_mask_qfbk);

--Y1_write_n_to_the_ext_ram_mask is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|write_n_to_the_ext_ram_mask at LC_X43_Y22_N9

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

Y1_write_n_to_the_ext_ram_mask = DFFEAS(Y1L1040, !GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , Y1_write_n_to_the_ext_ram_local, , , VCC);

--KB1L237 is std_1c20:inst|sdram:the_sdram|m_cmd[1]~COMB_OUT at LC_X13_Y21_N8

--operation mode is normal

KB1L237 = !KB1L502 & (KB1_m_state[7] & KB1L503 # !KB1_m_state[7] & (KB1L505));

--KB1L235Q is std_1c20:inst|sdram:the_sdram|m_cmd[1]~_Duplicate_1 at LC_X13_Y21_N8

--operation mode is normal

KB1L235Q = DFFEAS(KB1L237, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--KB1L245 is std_1c20:inst|sdram:the_sdram|m_cmd[3]~COMB_OUT at LC_X13_Y25_N2

--operation mode is normal

KB1L245 = KB1_m_state[7] & KB1L496 & KB1L497 # !KB1_m_state[7] & (!KB1L495);

--KB1L241 is std_1c20:inst|sdram:the_sdram|m_cmd[2]~COMB_OUT at LC_X13_Y24_N1

--operation mode is normal

KB1L241 = !KB1L499 & !KB1L498 & (KB1L501 # !KB1L500);

--KB1L240Q is std_1c20:inst|sdram:the_sdram|m_cmd[2]~_Duplicate_1 at LC_X13_Y24_N1

--operation mode is normal

KB1L240Q = DFFEAS(KB1L241, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--KB1L232 is std_1c20:inst|sdram:the_sdram|m_cmd[0]~COMB_OUT at LC_X12_Y25_N7

--operation mode is normal

KB1L232 = KB1L507 & KB1L509 & (!KB1L246 # !KB1L508);

--KB1L231Q is std_1c20:inst|sdram:the_sdram|m_cmd[0]~_Duplicate_1 at LC_X12_Y25_N7

--operation mode is normal

KB1L231Q = DFFEAS(KB1L232, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--ZE1_txd is std_1c20:inst|uart1:the_uart1|uart1_tx:the_uart1_tx|txd at LC_X48_Y25_N8

--operation mode is normal

ZE1_txd_lut_out = XE1_control_reg[9] # ZE1_pre_txd;

ZE1_txd = DFFEAS(ZE1_txd_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--S1L1682 is std_1c20:inst|cpu:the_cpu|internal_d_read~68 at LC_X33_Y18_N4

--operation mode is normal

S1L1682 = AMPP_FUNCTION(S1_W_stall, S1L1160, S1_E_ctrl_ld, S1L435);

--S1_internal_d_read is std_1c20:inst|cpu:the_cpu|internal_d_read at LC_X33_Y18_N4

--operation mode is normal

S1_internal_d_read = AMPP_FUNCTION(QC2__clk0, S1_W_stall, S1L1160, S1_E_ctrl_ld, S1L435, F1_data_out);

--S1_M_alu_result[19] is std_1c20:inst|cpu:the_cpu|M_alu_result[19] at LC_X29_Y20_N6

--operation mode is normal

S1_M_alu_result[19] = AMPP_FUNCTION(QC2__clk0, S1L9, S1_E_ctrl_dst_data_sel_logic_result, A1L277, S1L809, F1_data_out, S1_E_ctrl_dst_data_sel_cmp, S1_E_ctrl_rdctl_inst, S1_W_stall);

--S1_M_alu_result[18] is std_1c20:inst|cpu:the_cpu|M_alu_result[18] at LC_X29_Y20_N4

--operation mode is normal

S1_M_alu_result[18] = AMPP_FUNCTION(QC2__clk0, S1L808, S1_E_ctrl_dst_data_sel_logic_result, A1L277, S1L10, F1_data_out, S1_E_ctrl_dst_data_sel_cmp, S1_E_ctrl_rdctl_inst, S1_W_stall);

--UB1L2 is std_1c20:inst|sysid_control_slave_arbitrator:the_sysid_control_slave|cpu_data_master_granted_sysid_control_slave~150 at LC_X33_Y21_N8

--operation mode is normal

UB1L2 = !S1L1779Q & !S1L1776Q & !S1L1800Q & !S1L1816Q;

--S1_M_alu_result[16] is std_1c20:inst|cpu:the_cpu|M_alu_result[16] at LC_X29_Y20_N9

--operation mode is normal

S1_M_alu_result[16] = AMPP_FUNCTION(QC2__clk0, S1L806, S1_E_ctrl_dst_data_sel_logic_result, A1L277, S1L12, F1_data_out, S1_E_ctrl_dst_data_sel_cmp, S1_E_ctrl_rdctl_inst, S1_W_stall);

--S1_M_alu_result[15] is std_1c20:inst|cpu:the_cpu|M_alu_result[15] at LC_X33_Y17_N6

--operation mode is normal

S1_M_alu_result[15] = AMPP_FUNCTION(QC2__clk0, S1_E_ctrl_dst_data_sel_logic_result, S1L13, A1L277, S1L805, F1_data_out, S1_E_ctrl_dst_data_sel_cmp, S1_E_ctrl_rdctl_inst, S1_W_stall);

--S1_M_alu_result[14] is std_1c20:inst|cpu:the_cpu|M_alu_result[14] at LC_X33_Y17_N2

--operation mode is normal

S1_M_alu_result[14] = AMPP_FUNCTION(QC2__clk0, S1L804, S1L14, A1L277, S1_E_ctrl_dst_data_sel_logic_result, F1_data_out, S1_E_ctrl_dst_data_sel_cmp, S1_E_ctrl_rdctl_inst, S1_W_stall);

--UB1L3 is std_1c20:inst|sysid_control_slave_arbitrator:the_sysid_control_slave|cpu_data_master_granted_sysid_control_slave~151 at LC_X33_Y21_N4

--operation mode is normal

UB1L3 = !S1L1762Q & !S1L1866Q & !S1_M_alu_result[16] & !S1_M_alu_result[15];

--S1_M_alu_result[13] is std_1c20:inst|cpu:the_cpu|M_alu_result[13] at LC_X33_Y17_N8

--operation mode is normal

S1_M_alu_result[13] = AMPP_FUNCTION(QC2__clk0, S1L803, S1_E_ctrl_dst_data_sel_logic_result, A1L277, S1L15, F1_data_out, S1_E_ctrl_dst_data_sel_cmp, S1_E_ctrl_rdctl_inst, S1_W_stall);

--S1_M_alu_result[12] is std_1c20:inst|cpu:the_cpu|M_alu_result[12] at LC_X33_Y17_N5

--operation mode is normal

S1_M_alu_result[12] = AMPP_FUNCTION(QC2__clk0, S1L802, S1_E_ctrl_dst_data_sel_logic_result, A1L277, S1L16, F1_data_out, S1_E_ctrl_dst_data_sel_cmp, S1_E_ctrl_rdctl_inst, S1_W_stall);

--UB1L4 is std_1c20:inst|sysid_control_slave_arbitrator:the_sysid_control_slave|cpu_data_master_granted_sysid_control_slave~152 at LC_X37_Y25_N0

--operation mode is normal

UB1L4 = !S1_M_alu_result[12] & !S1_M_alu_result[13];

--S1_M_alu_result[17] is std_1c20:inst|cpu:the_cpu|M_alu_result[17] at LC_X29_Y20_N7

--operation mode is normal

S1_M_alu_result[17] = AMPP_FUNCTION(QC2__clk0, S1L807, S1_E_ctrl_dst_data_sel_logic_result, A1L277, S1L17, F1_data_out, S1_E_ctrl_dst_data_sel_cmp, S1_E_ctrl_rdctl_inst, S1_W_stall);

--V1L8 is std_1c20:inst|cpu_jtag_debug_module_arbitrator:the_cpu_jtag_debug_module|cpu_data_master_requests_cpu_jtag_debug_module~274 at LC_X34_Y21_N9

--operation mode is normal

V1L8 = S1L1773Q & S1L1782Q & !T1L448Q & S1L207Q;

--UB1L5 is std_1c20:inst|sysid_control_slave_arbitrator:the_sysid_control_slave|cpu_data_master_granted_sysid_control_slave~153 at LC_X37_Y25_N6

--operation mode is normal

UB1L5 = UB1L2 & UB1L3 & V1L8 & UB1L4;

--S1_M_alu_result[11] is std_1c20:inst|cpu:the_cpu|M_alu_result[11] at LC_X33_Y17_N9

--operation mode is normal

S1_M_alu_result[11] = AMPP_FUNCTION(QC2__clk0, S1L801, S1_E_ctrl_dst_data_sel_logic_result, A1L277, S1L21, F1_data_out, S1_E_ctrl_dst_data_sel_cmp, S1_E_ctrl_rdctl_inst, S1_W_stall);

--S1_M_alu_result[10] is std_1c20:inst|cpu:the_cpu|M_alu_result[10] at LC_X37_Y20_N0

--operation mode is normal

S1_M_alu_result[10] = AMPP_FUNCTION(QC2__clk0, S1_E_ctrl_dst_data_sel_logic_result, S1L22, A1L277, S1L800, F1_data_out, S1_E_ctrl_dst_data_sel_cmp, S1_E_ctrl_rdctl_inst, S1_W_stall);

--S1_M_alu_result[9] is std_1c20:inst|cpu:the_cpu|M_alu_result[9] at LC_X37_Y20_N7

--operation mode is normal

S1_M_alu_result[9] = AMPP_FUNCTION(QC2__clk0, S1_E_ctrl_dst_data_sel_logic_result, S1L799, A1L277, S1L23, F1_data_out, S1_E_ctrl_dst_data_sel_cmp, S1_E_ctrl_rdctl_inst, S1_W_stall);

--S1_M_alu_result[8] is std_1c20:inst|cpu:the_cpu|M_alu_result[8] at LC_X33_Y18_N6

--operation mode is normal

S1_M_alu_result[8] = AMPP_FUNCTION(QC2__clk0, S1_E_ctrl_dst_data_sel_logic_result, S1L798, A1L277, S1L24, F1_data_out, S1_E_ctrl_dst_data_sel_cmp, S1_E_ctrl_rdctl_inst, S1_W_stall);

--UB1L6 is std_1c20:inst|sysid_control_slave_arbitrator:the_sysid_control_slave|cpu_data_master_granted_sysid_control_slave~154 at LC_X37_Y20_N4

--operation mode is normal

UB1L6 = !S1_M_alu_result[9] & S1_M_alu_result[11] & !S1_M_alu_result[8] & !S1L1756Q;

--S1_M_alu_result[7] is std_1c20:inst|cpu:the_cpu|M_alu_result[7] at LC_X35_Y17_N5

--operation mode is normal

S1_M_alu_result[7] = AMPP_FUNCTION(QC2__clk0, S1_E_ctrl_dst_data_sel_logic_result, S1L797, A1L277, S1L25, F1_data_out, S1_E_ctrl_dst_data_sel_cmp, S1_E_ctrl_rdctl_inst, S1_W_stall);

--UB1L7 is std_1c20:inst|sysid_control_slave_arbitrator:the_sysid_control_slave|cpu_data_master_granted_sysid_control_slave~155 at LC_X42_Y25_N9

--operation mode is normal

UB1L7 = !S1_M_alu_result[6] & S1_M_alu_result[7];

--S1L1685 is std_1c20:inst|cpu:the_cpu|internal_d_write~66 at LC_X33_Y21_N6

--operation mode is normal

S1L1685 = AMPP_FUNCTION(S1L2514, RB1L7, S1_E_ctrl_st, S1L1160);

--S1_internal_d_write is std_1c20:inst|cpu:the_cpu|internal_d_write at LC_X33_Y21_N6

--operation mode is normal

S1_internal_d_write = AMPP_FUNCTION(QC2__clk0, S1L2514, RB1L7, S1_E_ctrl_st, S1L1160, F1_data_out);

--JB1L2 is std_1c20:inst|reconfig_request_pio_s1_arbitrator:the_reconfig_request_pio_s1|cpu_data_master_requests_reconfig_request_pio_s1~48 at LC_X42_Y25_N3

--operation mode is normal

JB1L2 = !S1L1738Q & (S1_internal_d_read # S1_internal_d_write);

--JB1L3 is std_1c20:inst|reconfig_request_pio_s1_arbitrator:the_reconfig_request_pio_s1|cpu_data_master_requests_reconfig_request_pio_s1~49 at LC_X42_Y25_N7

--operation mode is normal

JB1L3 = UB1L5 & UB1L6 & UB1L7 & JB1L2;

--EB1_lcd_display_control_slave_wait_counter[1] is std_1c20:inst|lcd_display_control_slave_arbitrator:the_lcd_display_control_slave|lcd_display_control_slave_wait_counter[1] at LC_X35_Y21_N9

--operation mode is normal

EB1_lcd_display_control_slave_wait_counter[1]_lut_out = EB1L1 & !EB1L21 & (!EB1L22 # !S1L1686Q);

EB1_lcd_display_control_slave_wait_counter[1] = DFFEAS(EB1_lcd_display_control_slave_wait_counter[1]_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--EB1_lcd_display_control_slave_wait_counter[0] is std_1c20:inst|lcd_display_control_slave_arbitrator:the_lcd_display_control_slave|lcd_display_control_slave_wait_counter[0] at LC_X36_Y21_N6

--operation mode is normal

EB1_lcd_display_control_slave_wait_counter[0]_lut_out = EB1L25 # !EB1_lcd_display_control_slave_wait_counter[0] & EB1L23 & !EB1L21;

EB1_lcd_display_control_slave_wait_counter[0] = DFFEAS(EB1_lcd_display_control_slave_wait_counter[0]_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--EB1_lcd_display_control_slave_wait_counter[3] is std_1c20:inst|lcd_display_control_slave_arbitrator:the_lcd_display_control_slave|lcd_display_control_slave_wait_counter[3] at LC_X35_Y21_N0

--operation mode is normal

EB1_lcd_display_control_slave_wait_counter[3]_lut_out = !EB1L25 & (!EB1L21 & EB1L7 # !EB1L23);

EB1_lcd_display_control_slave_wait_counter[3] = DFFEAS(EB1_lcd_display_control_slave_wait_counter[3]_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--EB1_lcd_display_control_slave_wait_counter[2] is std_1c20:inst|lcd_display_control_slave_arbitrator:the_lcd_display_control_slave|lcd_display_control_slave_wait_counter[2] at LC_X35_Y20_N1

--operation mode is normal

EB1_lcd_display_control_slave_wait_counter[2]_lut_out = EB1L25 # EB1L11 & !EB1L21 & EB1L23;

EB1_lcd_display_control_slave_wait_counter[2] = DFFEAS(EB1_lcd_display_control_slave_wait_counter[2]_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--EB1L36 is std_1c20:inst|lcd_display_control_slave_arbitrator:the_lcd_display_control_slave|LessThan0~92 at LC_X35_Y22_N6

--operation mode is normal

EB1L36 = !EB1_lcd_display_control_slave_wait_counter[0] & !EB1_lcd_display_control_slave_wait_counter[1] # !EB1_lcd_display_control_slave_wait_counter[2] # !EB1_lcd_display_control_slave_wait_counter[3];

--EB1_lcd_display_control_slave_wait_counter[5] is std_1c20:inst|lcd_display_control_slave_arbitrator:the_lcd_display_control_slave|lcd_display_control_slave_wait_counter[5] at LC_X35_Y21_N7

--operation mode is normal

EB1_lcd_display_control_slave_wait_counter[5]_lut_out = EB1L25 # EB1L14 & !EB1L21 & EB1L23;

EB1_lcd_display_control_slave_wait_counter[5] = DFFEAS(EB1_lcd_display_control_slave_wait_counter[5]_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--EB1_lcd_display_control_slave_wait_counter[4] is std_1c20:inst|lcd_display_control_slave_arbitrator:the_lcd_display_control_slave|lcd_display_control_slave_wait_counter[4] at LC_X35_Y21_N8

--operation mode is normal

EB1_lcd_display_control_slave_wait_counter[4]_lut_out = !EB1L25 & (!EB1L21 & EB1L15 # !EB1L23);

EB1_lcd_display_control_slave_wait_counter[4] = DFFEAS(EB1_lcd_display_control_slave_wait_counter[4]_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--EB1L37 is std_1c20:inst|lcd_display_control_slave_arbitrator:the_lcd_display_control_slave|LessThan0~93 at LC_X35_Y22_N8

--operation mode is normal

EB1L37 = !EB1_lcd_display_control_slave_wait_counter[5] & !EB1_lcd_display_control_slave_wait_counter[4];

--DB1L1 is std_1c20:inst|lcd_display:the_lcd_display|LCD_E~447 at LC_X36_Y21_N9

--operation mode is normal

DB1L1 = JB1L3 & !S1_M_alu_result[5] & EB1L38 & S1_internal_d_read;

--EB1L24 is std_1c20:inst|lcd_display_control_slave_arbitrator:the_lcd_display_control_slave|lcd_display_control_slave_in_a_write_cycle~48 at LC_X36_Y25_N5

--operation mode is normal

EB1L24 = EB1L27 & UB1L7 & JB1L2 & UB1L5;

--DB1L2 is std_1c20:inst|lcd_display:the_lcd_display|LCD_E~448 at LC_X35_Y22_N0

--operation mode is normal

DB1L2 = EB1_lcd_display_control_slave_wait_counter[2] & (EB1_lcd_display_control_slave_wait_counter[1] # EB1_lcd_display_control_slave_wait_counter[0] # EB1_lcd_display_control_slave_wait_counter[4]) # !EB1_lcd_display_control_slave_wait_counter[2] & EB1_lcd_display_control_slave_wait_counter[1] & (EB1_lcd_display_control_slave_wait_counter[4]);

--DB1L3 is std_1c20:inst|lcd_display:the_lcd_display|LCD_E~449 at LC_X35_Y22_N4

--operation mode is normal

DB1L3 = !EB1_lcd_display_control_slave_wait_counter[5] & S1L2149Q & !DB1L5;

--EB1_d1_reasons_to_wait is std_1c20:inst|lcd_display_control_slave_arbitrator:the_lcd_display_control_slave|d1_reasons_to_wait at LC_X36_Y21_N7

--operation mode is normal

EB1_d1_reasons_to_wait_lut_out = !S1_M_alu_result[5] & JB1L3 & (!EB1L21 # !EB1_d1_reasons_to_wait);

EB1_d1_reasons_to_wait = DFFEAS(EB1_d1_reasons_to_wait_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--EB1L22 is std_1c20:inst|lcd_display_control_slave_arbitrator:the_lcd_display_control_slave|lcd_display_control_slave_begintransfer~46 at LC_X36_Y21_N3

--operation mode is normal

EB1L22 = !S1_M_alu_result[5] & !EB1_d1_reasons_to_wait & JB1L3;

--DB1L4 is std_1c20:inst|lcd_display:the_lcd_display|LCD_E~450 at LC_X36_Y21_N2

--operation mode is normal

DB1L4 = !EB1L22 & (DB1L1 # EB1L24 & DB1L3);

--Y1L69 is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|be_n_to_the_ext_ram[3]~COMB_OUT at LC_X31_Y22_N7

--operation mode is normal

Y1L69 = S1L2177Q # !Y1L53 & !Y1L51 # !Y1L104;

--Y1L66 is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|be_n_to_the_ext_ram[2]~COMB_OUT at LC_X31_Y22_N8

--operation mode is normal

Y1L66 = S1L2168Q # !Y1L53 & !Y1L51 # !Y1L104;

--Y1L63 is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|be_n_to_the_ext_ram[1]~COMB_OUT at LC_X31_Y22_N0

--operation mode is normal

Y1L63 = S1L2158Q # !Y1L51 & !Y1L53 # !Y1L104;

--Y1L60 is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|be_n_to_the_ext_ram[0]~COMB_OUT at LC_X30_Y22_N9

--operation mode is normal

Y1L60 = S1L2149Q # !Y1L53 & !Y1L51 # !Y1L104;

--Y1L82 is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|byteenablen_to_the_lan91c111[3]~COMB_OUT at LC_X31_Y26_N9

--operation mode is normal

Y1L82 = S1L2177Q # !Y1L28 & !Y1L31 # !Y1L112;

--Y1L79 is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|byteenablen_to_the_lan91c111[2]~COMB_OUT at LC_X31_Y22_N5

--operation mode is normal

Y1L79 = S1L2168Q # !Y1L28 & !Y1L31 # !Y1L112;

--Y1L76 is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|byteenablen_to_the_lan91c111[1]~COMB_OUT at LC_X31_Y22_N4

--operation mode is normal

Y1L76 = S1L2158Q # !Y1L28 & !Y1L31 # !Y1L112;

--Y1L73 is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|byteenablen_to_the_lan91c111[0]~COMB_OUT at LC_X31_Y26_N8

--operation mode is normal

Y1L73 = S1L2149Q # !Y1L28 & !Y1L31 # !Y1L112;

--Y1L498 is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_address[22]~COMB_OUT at LC_X25_Y23_N9

--operation mode is normal

Y1L498 = Y1L1001 & (Y1L494 # Y1L492 & !Y1L916);

--Y1L489 is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_address[21]~COMB_OUT at LC_X28_Y23_N4

--operation mode is normal

Y1L489 = Y1L1001 & (Y1L485 # !Y1L916 & Y1L483);

--S1_ic_fill_tag[7] is std_1c20:inst|cpu:the_cpu|ic_fill_tag[7] at LC_X25_Y23_N0

--operation mode is normal

S1_ic_fill_tag[7] = AMPP_FUNCTION(QC2__clk0, S1_D_pc[17], F1_data_out, S1_D_ic_fill_starting);

--S1_ic_fill_tag[6] is std_1c20:inst|cpu:the_cpu|ic_fill_tag[6] at LC_X25_Y23_N3

--operation mode is normal

S1_ic_fill_tag[6] = AMPP_FUNCTION(QC2__clk0, S1_D_pc[16], F1_data_out, S1_D_ic_fill_starting);

--Y1L471 is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_address[17]~COMB_OUT at LC_X29_Y24_N6

--operation mode is normal

Y1L471 = !Y1L465 & (Y1L463 $ (Y1L916 & Y1L461));

--Y1L458 is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_address[16]~COMB_OUT at LC_X29_Y24_N1

--operation mode is normal

Y1L458 = Y1L736 # Y1L2 & (S1_M_alu_result[16]) # !Y1L2 & S1L1587Q;

--Y1L455 is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_address[15]~COMB_OUT at LC_X29_Y24_N4

--operation mode is normal

Y1L455 = Y1L2 & (S1_M_alu_result[15]) # !Y1L2 & (Y1L736 & (S1_M_alu_result[15]) # !Y1L736 & S1L1583Q);

--Y1L452 is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_address[14]~COMB_OUT at LC_X28_Y25_N4

--operation mode is normal

Y1L452 = Y1L739 & S1L1762Q # !Y1L739 & (Y1L2 & S1L1762Q # !Y1L2 & (S1L1580Q));

--Y1L445 is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_address[12]~COMB_OUT at LC_X28_Y25_N9

--operation mode is normal

Y1L445 = Y1L737 & S1_M_alu_result[12] # !Y1L737 & (Y1L2 & S1_M_alu_result[12] # !Y1L2 & (S1L1568Q));

--S1_ic_fill_line[6] is std_1c20:inst|cpu:the_cpu|ic_fill_line[6] at LC_X26_Y20_N8

--operation mode is normal

S1_ic_fill_line[6] = AMPP_FUNCTION(QC2__clk0, S1L1679, F1_data_out);

--Y1L440 is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_address[10]~COMB_OUT at LC_X24_Y26_N9

--operation mode is normal

Y1L440 = Y1L2 & (S1L1756Q) # !Y1L2 & (Y1L739 & (S1L1756Q) # !Y1L739 & S1_ic_fill_line[5]);

--Y1L433 is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_address[8]~COMB_OUT at LC_X28_Y23_N9

--operation mode is normal

Y1L433 = Y1L2 & (S1_M_alu_result[8]) # !Y1L2 & (Y1L736 & (S1_M_alu_result[8]) # !Y1L736 & S1_ic_fill_line[3]);

--Y1L430 is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_address[7]~COMB_OUT at LC_X28_Y23_N1

--operation mode is normal

Y1L430 = Y1L2 & S1_M_alu_result[7] # !Y1L2 & (Y1L736 & S1_M_alu_result[7] # !Y1L736 & (S1_ic_fill_line[2]));

--Y1L427 is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_address[6]~COMB_OUT at LC_X29_Y24_N7

--operation mode is normal

Y1L427 = Y1L736 & S1_M_alu_result[6] # !Y1L736 & (Y1L2 & S1_M_alu_result[6] # !Y1L2 & (S1_ic_fill_line[1]));

--Y1L424 is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_address[5]~COMB_OUT at LC_X25_Y23_N7

--operation mode is normal

Y1L424 = Y1L736 & (S1_M_alu_result[5]) # !Y1L736 & (Y1L2 & (S1_M_alu_result[5]) # !Y1L2 & S1_ic_fill_line[0]);

--Y1L421 is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_address[4]~COMB_OUT at LC_X28_Y26_N4

--operation mode is normal

Y1L421 = Y1L2 & (S1_M_alu_result[4]) # !Y1L2 & (Y1L739 & (S1_M_alu_result[4]) # !Y1L739 & S1_ic_fill_ap_offset[2]);

--Y1L418 is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_address[3]~COMB_OUT at LC_X28_Y25_N5

--operation mode is normal

Y1L418 = Y1L737 & S1_M_alu_result[3] # !Y1L737 & (Y1L2 & S1_M_alu_result[3] # !Y1L2 & (S1_ic_fill_ap_offset[1]));

--Y1L415 is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_address[2]~COMB_OUT at LC_X28_Y25_N3

--operation mode is normal

Y1L415 = Y1L737 & S1_M_alu_result[2] # !Y1L737 & (Y1L2 & S1_M_alu_result[2] # !Y1L2 & (S1_ic_fill_ap_offset[0]));

--Y1L412 is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_address[1]~COMB_OUT at LC_X29_Y23_N1

--operation mode is normal

Y1L412 = Y1L999 & (Y1L1001 # S1_M_alu_result[1] & Y1L996) # !Y1L999 & S1_M_alu_result[1] & (Y1L996);

--Y1L409 is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_address[0]~COMB_OUT at LC_X28_Y23_N8

--operation mode is normal

Y1L409 = S1_M_alu_result[0] & (Y1L996 # Y1L1001 & Y1L997) # !S1_M_alu_result[0] & Y1L1001 & (Y1L997);

--FB1_data_out[7] is std_1c20:inst|led_pio:the_led_pio|data_out[7] at LC_X48_Y30_N1

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

FB1_data_out[7]_lut_out = GND;

FB1_data_out[7] = DFFEAS(FB1_data_out[7]_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , FB1L10, S1_M_st_data[7], , , VCC);

--FB1_data_out[6] is std_1c20:inst|led_pio:the_led_pio|data_out[6] at LC_X48_Y30_N3

--operation mode is normal

FB1_data_out[6]_lut_out = S1_M_st_data[6];

FB1_data_out[6] = DFFEAS(FB1_data_out[6]_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , FB1L10, , , , );

--FB1_data_out[5] is std_1c20:inst|led_pio:the_led_pio|data_out[5] at LC_X48_Y30_N8

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

FB1_data_out[5]_lut_out = GND;

FB1_data_out[5] = DFFEAS(FB1_data_out[5]_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , FB1L10, S1_M_st_data[5], , , VCC);

--FB1_data_out[4] is std_1c20:inst|led_pio:the_led_pio|data_out[4] at LC_X48_Y30_N6

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

FB1_data_out[4]_lut_out = GND;

FB1_data_out[4] = DFFEAS(FB1_data_out[4]_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , FB1L10, S1_M_st_data[4], , , VCC);

--FB1_data_out[3] is std_1c20:inst|led_pio:the_led_pio|data_out[3] at LC_X48_Y30_N2

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

FB1_data_out[3]_lut_out = GND;

FB1_data_out[3] = DFFEAS(FB1_data_out[3]_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , FB1L10, S1_M_st_data[3], , , VCC);

--FB1_data_out[2] is std_1c20:inst|led_pio:the_led_pio|data_out[2] at LC_X48_Y30_N9

--operation mode is normal

FB1_data_out[2]_lut_out = S1_M_st_data[2];

FB1_data_out[2] = DFFEAS(FB1_data_out[2]_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , FB1L10, , , , );

--FB1_data_out[1] is std_1c20:inst|led_pio:the_led_pio|data_out[1] at LC_X48_Y30_N0

--operation mode is normal

FB1_data_out[1]_lut_out = S1_M_st_data[1];

FB1_data_out[1] = DFFEAS(FB1_data_out[1]_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , FB1L10, , , , );

--FB1_data_out[0] is std_1c20:inst|led_pio:the_led_pio|data_out[0] at LC_X48_Y30_N7

--operation mode is normal

FB1_data_out[0]_lut_out = S1_M_st_data[0];

FB1_data_out[0] = DFFEAS(FB1_data_out[0]_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , FB1L10, , , , );

--PB1_data_out[15] is std_1c20:inst|seven_seg_pio:the_seven_seg_pio|data_out[15] at LC_X22_Y17_N5

--operation mode is normal

PB1_data_out[15]_lut_out = S1L2319Q;

PB1_data_out[15] = DFFEAS(PB1_data_out[15]_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , PB1L18, , , , );

--PB1_data_out[14] is std_1c20:inst|seven_seg_pio:the_seven_seg_pio|data_out[14] at LC_X22_Y17_N2

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

PB1_data_out[14]_lut_out = GND;

PB1_data_out[14] = DFFEAS(PB1_data_out[14]_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , PB1L18, S1L2313Q, , , VCC);

--PB1_data_out[13] is std_1c20:inst|seven_seg_pio:the_seven_seg_pio|data_out[13] at LC_X25_Y21_N2

--operation mode is normal

PB1_data_out[13]_lut_out = S1L2307Q;

PB1_data_out[13] = DFFEAS(PB1_data_out[13]_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , PB1L18, , , , );

--PB1_data_out[12] is std_1c20:inst|seven_seg_pio:the_seven_seg_pio|data_out[12] at LC_X22_Y17_N8

--operation mode is normal

PB1_data_out[12]_lut_out = S1L2301Q;

PB1_data_out[12] = DFFEAS(PB1_data_out[12]_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , PB1L18, , , , );

--PB1_data_out[11] is std_1c20:inst|seven_seg_pio:the_seven_seg_pio|data_out[11] at LC_X22_Y17_N4

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

PB1_data_out[11]_lut_out = GND;

PB1_data_out[11] = DFFEAS(PB1_data_out[11]_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , PB1L18, S1L2294Q, , , VCC);

--PB1_data_out[10] is std_1c20:inst|seven_seg_pio:the_seven_seg_pio|data_out[10] at LC_X23_Y17_N2

--operation mode is normal

PB1_data_out[10]_lut_out = S1L2288Q;

PB1_data_out[10] = DFFEAS(PB1_data_out[10]_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , PB1L18, , , , );

--PB1_data_out[9] is std_1c20:inst|seven_seg_pio:the_seven_seg_pio|data_out[9] at LC_X23_Y17_N6

--operation mode is normal

PB1_data_out[9]_lut_out = S1L2281Q;

PB1_data_out[9] = DFFEAS(PB1_data_out[9]_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , PB1L18, , , , );

--PB1_data_out[8] is std_1c20:inst|seven_seg_pio:the_seven_seg_pio|data_out[8] at LC_X22_Y17_N6

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

PB1_data_out[8]_lut_out = GND;

PB1_data_out[8] = DFFEAS(PB1_data_out[8]_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , PB1L18, S1L2275Q, , , VCC);

--PB1_data_out[7] is std_1c20:inst|seven_seg_pio:the_seven_seg_pio|data_out[7] at LC_X23_Y17_N9

--operation mode is normal

PB1_data_out[7]_lut_out = S1_M_st_data[7];

PB1_data_out[7] = DFFEAS(PB1_data_out[7]_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , PB1L18, , , , );

--PB1_data_out[6] is std_1c20:inst|seven_seg_pio:the_seven_seg_pio|data_out[6] at LC_X23_Y17_N1

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

PB1_data_out[6]_lut_out = GND;

PB1_data_out[6] = DFFEAS(PB1_data_out[6]_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , PB1L18, S1_M_st_data[6], , , VCC);

--PB1_data_out[5] is std_1c20:inst|seven_seg_pio:the_seven_seg_pio|data_out[5] at LC_X23_Y17_N5

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

PB1_data_out[5]_lut_out = GND;

PB1_data_out[5] = DFFEAS(PB1_data_out[5]_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , PB1L18, S1_M_st_data[5], , , VCC);

--PB1_data_out[4] is std_1c20:inst|seven_seg_pio:the_seven_seg_pio|data_out[4] at LC_X23_Y17_N8

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

PB1_data_out[4]_lut_out = GND;

PB1_data_out[4] = DFFEAS(PB1_data_out[4]_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , PB1L18, S1_M_st_data[4], , , VCC);

--PB1_data_out[3] is std_1c20:inst|seven_seg_pio:the_seven_seg_pio|data_out[3] at LC_X23_Y17_N0

--operation mode is normal

PB1_data_out[3]_lut_out = S1_M_st_data[3];

PB1_data_out[3] = DFFEAS(PB1_data_out[3]_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , PB1L18, , , , );

--PB1_data_out[2] is std_1c20:inst|seven_seg_pio:the_seven_seg_pio|data_out[2] at LC_X23_Y17_N4

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

PB1_data_out[2]_lut_out = GND;

PB1_data_out[2] = DFFEAS(PB1_data_out[2]_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , PB1L18, S1_M_st_data[2], , , VCC);

--PB1_data_out[1] is std_1c20:inst|seven_seg_pio:the_seven_seg_pio|data_out[1] at LC_X23_Y17_N7

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

PB1_data_out[1]_lut_out = GND;

PB1_data_out[1] = DFFEAS(PB1_data_out[1]_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , PB1L18, S1_M_st_data[1], , , VCC);

--PB1_data_out[0] is std_1c20:inst|seven_seg_pio:the_seven_seg_pio|data_out[0] at LC_X23_Y17_N3

--operation mode is normal

PB1_data_out[0]_lut_out = S1_M_st_data[0];

PB1_data_out[0] = DFFEAS(PB1_data_out[0]_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , PB1L18, , , , );

--KB1L218 is std_1c20:inst|sdram:the_sdram|m_addr[11]~COMB_OUT at LC_X11_Y20_N7

--operation mode is normal

KB1L218 = KB1L713 & KB1L217Q # !KB1L713 & (KB1L711 # KB1L217Q & KB1L712);

--KB1L217Q is std_1c20:inst|sdram:the_sdram|m_addr[11]~_Duplicate_1 at LC_X11_Y20_N7

--operation mode is normal

KB1L217Q = DFFEAS(KB1L218, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--KB1L214 is std_1c20:inst|sdram:the_sdram|m_addr[10]~COMB_OUT at LC_X11_Y20_N6

--operation mode is normal

KB1L214 = KB1L713 & (KB1L213Q) # !KB1L713 & (KB1L718 # KB1L712 & KB1L213Q);

--KB1L213Q is std_1c20:inst|sdram:the_sdram|m_addr[10]~_Duplicate_1 at LC_X11_Y20_N6

--operation mode is normal

KB1L213Q = DFFEAS(KB1L214, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--KB1L210 is std_1c20:inst|sdram:the_sdram|m_addr[9]~COMB_OUT at LC_X13_Y20_N8

--operation mode is normal

KB1L210 = KB1L713 & (KB1L209Q) # !KB1L713 & (KB1L723 # KB1L712 & KB1L209Q);

--KB1L209Q is std_1c20:inst|sdram:the_sdram|m_addr[9]~_Duplicate_1 at LC_X13_Y20_N8

--operation mode is normal

KB1L209Q = DFFEAS(KB1L210, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--KB1L206 is std_1c20:inst|sdram:the_sdram|m_addr[8]~COMB_OUT at LC_X11_Y20_N1

--operation mode is normal

KB1L206 = KB1L713 & KB1L205Q # !KB1L713 & (KB1L728 # KB1L205Q & KB1L712);

--KB1L205Q is std_1c20:inst|sdram:the_sdram|m_addr[8]~_Duplicate_1 at LC_X11_Y20_N1

--operation mode is normal

KB1L205Q = DFFEAS(KB1L206, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--KB1L202 is std_1c20:inst|sdram:the_sdram|m_addr[7]~COMB_OUT at LC_X14_Y21_N6

--operation mode is normal

KB1L202 = KB1L713 & KB1L200Q # !KB1L713 & (KB1L735 # KB1L200Q & KB1_m_state[6]);

--KB1L200Q is std_1c20:inst|sdram:the_sdram|m_addr[7]~_Duplicate_1 at LC_X14_Y21_N6

--operation mode is normal

KB1L200Q = DFFEAS(KB1L202, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--KB1L197 is std_1c20:inst|sdram:the_sdram|m_addr[6]~COMB_OUT at LC_X12_Y20_N9

--operation mode is normal

KB1L197 = KB1L759 # !KB1_m_state[6] & !KB1L713 & KB1L764;

--KB1L195Q is std_1c20:inst|sdram:the_sdram|m_addr[6]~_Duplicate_1 at LC_X12_Y20_N9

--operation mode is normal

KB1L195Q = DFFEAS(KB1L197, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--KB1L192 is std_1c20:inst|sdram:the_sdram|m_addr[5]~COMB_OUT at LC_X12_Y20_N5

--operation mode is normal

KB1L192 = KB1L786 # !KB1_m_state[6] & !KB1L713 & KB1L791;

--KB1L190Q is std_1c20:inst|sdram:the_sdram|m_addr[5]~_Duplicate_1 at LC_X12_Y20_N5

--operation mode is normal

KB1L190Q = DFFEAS(KB1L192, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--KB1L187 is std_1c20:inst|sdram:the_sdram|m_addr[4]~COMB_OUT at LC_X12_Y20_N6

--operation mode is normal

KB1L187 = KB1L814 # !KB1_m_state[6] & !KB1L713 & KB1L819;

--KB1L185Q is std_1c20:inst|sdram:the_sdram|m_addr[4]~_Duplicate_1 at LC_X12_Y20_N6

--operation mode is normal

KB1L185Q = DFFEAS(KB1L187, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--KB1L182 is std_1c20:inst|sdram:the_sdram|m_addr[3]~COMB_OUT at LC_X13_Y19_N6

--operation mode is normal

KB1L182 = KB1L843 # !KB1_m_state[6] & !KB1L713 & KB1L848;

--KB1L180Q is std_1c20:inst|sdram:the_sdram|m_addr[3]~_Duplicate_1 at LC_X13_Y19_N6

--operation mode is normal

KB1L180Q = DFFEAS(KB1L182, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--KB1L177 is std_1c20:inst|sdram:the_sdram|m_addr[2]~COMB_OUT at LC_X12_Y18_N3

--operation mode is normal

KB1L177 = KB1L868 # !KB1L713 & !KB1_m_state[6] & KB1L873;

--KB1L175Q is std_1c20:inst|sdram:the_sdram|m_addr[2]~_Duplicate_1 at LC_X12_Y18_N3

--operation mode is normal

KB1L175Q = DFFEAS(KB1L177, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--KB1L172 is std_1c20:inst|sdram:the_sdram|m_addr[1]~COMB_OUT at LC_X14_Y19_N3

--operation mode is normal

KB1L172 = KB1L892 # !KB1_m_state[6] & !KB1L713 & KB1L897;

--KB1L170Q is std_1c20:inst|sdram:the_sdram|m_addr[1]~_Duplicate_1 at LC_X14_Y19_N3

--operation mode is normal

KB1L170Q = DFFEAS(KB1L172, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--KB1L167 is std_1c20:inst|sdram:the_sdram|m_addr[0]~COMB_OUT at LC_X13_Y18_N6

--operation mode is normal

KB1L167 = KB1L918 # !KB1_m_state[6] & !KB1L713 & KB1L923;

--KB1L165Q is std_1c20:inst|sdram:the_sdram|m_addr[0]~_Duplicate_1 at LC_X13_Y18_N6

--operation mode is normal

KB1L165Q = DFFEAS(KB1L167, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--KB1L227 is std_1c20:inst|sdram:the_sdram|m_bank[1]~COMB_OUT at LC_X18_Y22_N1

--operation mode is normal

KB1L227 = KB1L943 & (KB1L948 & (KB1L942) # !KB1L948 & KB1L226Q) # !KB1L943 & KB1L226Q;

--KB1L226Q is std_1c20:inst|sdram:the_sdram|m_bank[1]~_Duplicate_1 at LC_X18_Y22_N1

--operation mode is normal

KB1L226Q = DFFEAS(KB1L227, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--KB1L223 is std_1c20:inst|sdram:the_sdram|m_bank[0]~COMB_OUT at LC_X18_Y22_N8

--operation mode is normal

KB1L223 = KB1L948 & (KB1L943 & (KB1L944) # !KB1L943 & KB1L222Q) # !KB1L948 & KB1L222Q;

--KB1L222Q is std_1c20:inst|sdram:the_sdram|m_bank[0]~_Duplicate_1 at LC_X18_Y22_N8

--operation mode is normal

KB1L222Q = DFFEAS(KB1L223, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--KB1L428 is std_1c20:inst|sdram:the_sdram|m_dqm[3]~COMB_OUT at LC_X18_Y21_N2

--operation mode is normal

KB1L428 = KB1L948 & (KB1L943 & (KB1L980) # !KB1L943 & KB1L427Q) # !KB1L948 & KB1L427Q;

--KB1L427Q is std_1c20:inst|sdram:the_sdram|m_dqm[3]~_Duplicate_1 at LC_X18_Y21_N2

--operation mode is normal

KB1L427Q = DFFEAS(KB1L428, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--KB1L424 is std_1c20:inst|sdram:the_sdram|m_dqm[2]~COMB_OUT at LC_X18_Y21_N6

--operation mode is normal

KB1L424 = KB1L943 & (KB1L948 & (KB1L981) # !KB1L948 & KB1L423Q) # !KB1L943 & KB1L423Q;

--KB1L423Q is std_1c20:inst|sdram:the_sdram|m_dqm[2]~_Duplicate_1 at LC_X18_Y21_N6

--operation mode is normal

KB1L423Q = DFFEAS(KB1L424, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--KB1L420 is std_1c20:inst|sdram:the_sdram|m_dqm[1]~COMB_OUT at LC_X18_Y21_N9

--operation mode is normal

KB1L420 = KB1L948 & (KB1L943 & (KB1L982) # !KB1L943 & KB1L419Q) # !KB1L948 & KB1L419Q;

--KB1L419Q is std_1c20:inst|sdram:the_sdram|m_dqm[1]~_Duplicate_1 at LC_X18_Y21_N9

--operation mode is normal

KB1L419Q = DFFEAS(KB1L420, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--KB1L416 is std_1c20:inst|sdram:the_sdram|m_dqm[0]~COMB_OUT at LC_X13_Y21_N6

--operation mode is normal

KB1L416 = KB1L943 & (KB1L948 & (KB1L983) # !KB1L948 & KB1L415Q) # !KB1L943 & KB1L415Q;

--KB1L415Q is std_1c20:inst|sdram:the_sdram|m_dqm[0]~_Duplicate_1 at LC_X13_Y21_N6

--operation mode is normal

KB1L415Q = DFFEAS(KB1L416, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--A1L6 is altera_internal_jtag~TDO at JTAG_X1_Y16_N1

A1L6 = STRATIX_ELA(altera_reserved_tms, altera_reserved_tck, altera_reserved_tdi, , , C1L19);

--A1L7 is altera_internal_jtag~TMSUTAP at JTAG_X1_Y16_N1

A1L7 = STRATIX_ELA(altera_reserved_tms, altera_reserved_tck, altera_reserved_tdi, , , C1L19);

--A1L5 is altera_internal_jtag~TCKUTAP at JTAG_X1_Y16_N1

A1L5 = STRATIX_ELA(altera_reserved_tms, altera_reserved_tck, altera_reserved_tdi, , , C1L19);

--altera_internal_jtag is altera_internal_jtag at JTAG_X1_Y16_N1

altera_internal_jtag = STRATIX_ELA(altera_reserved_tms, altera_reserved_tck, altera_reserved_tdi, , , C1L19);

--A1L4 is altera_internal_jtag~SHIFTUSER at JTAG_X1_Y16_N1

A1L4 = STRATIX_ELA(altera_reserved_tms, altera_reserved_tck, altera_reserved_tdi, , , C1L19);

--A1L8 is altera_internal_jtag~UPDATEUSER at JTAG_X1_Y16_N1

A1L8 = STRATIX_ELA(altera_reserved_tms, altera_reserved_tck, altera_reserved_tdi, , , C1L19);

--A1L3 is altera_internal_jtag~RUNIDLEUSER at JTAG_X1_Y16_N1

A1L3 = STRATIX_ELA(altera_reserved_tms, altera_reserved_tck, altera_reserved_tdi, , , C1L19);

--Y1L870 is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|lan91c111_s1_in_a_read_cycle~60 at LC_X28_Y22_N4

--operation mode is normal

Y1L870 = S1L1589Q & !S1L1597Q & S1L1616Q & S1L1574Q;

--Y1L966Q is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|last_cycle_cpu_instruction_master_granted_slave_lan91c111_s1~4 at LC_X28_Y22_N4

--operation mode is normal

Y1L966Q = DFFEAS(Y1L870, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--Y1L813 is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_avalon_slave_slavearbiterlockenable~194 at LC_X32_Y21_N3

--operation mode is normal

Y1L813 = Y1L817Q & (Y1L206Q & (Y1L814Q) # !Y1L206Q & Y1L816Q) # !Y1L817Q & (Y1L814Q);

--Y1L814Q is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_avalon_slave_slavearbiterlockenable~195 at LC_X32_Y21_N3

--operation mode is normal

Y1L814Q = DFFEAS(Y1L813, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--QB1L1 is std_1c20:inst|seven_seg_pio_s1_arbitrator:the_seven_seg_pio_s1|internal_cpu_data_master_requests_seven_seg_pio_s1~0 at LC_X33_Y20_N7

--operation mode is normal

QB1L1 = S1L1682 # S1L1685;

--S1L1686Q is std_1c20:inst|cpu:the_cpu|internal_d_write~67 at LC_X33_Y20_N7

--operation mode is normal

S1L1686Q = AMPP_FUNCTION(QC2__clk0, S1L1682, S1L1685, F1_data_out);

--Y1L143 is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|cpu_data_master_requests_ext_ram_s1~338 at LC_X33_Y21_N1

--operation mode is normal

Y1L143 = S1L207Q & !S1L1800Q & (!S1L1816Q);

--Y1L911Q is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|last_cycle_cpu_data_master_granted_slave_ext_ram_s1~5 at LC_X33_Y21_N1

--operation mode is normal

Y1L911Q = DFFEAS(Y1L143, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--Y1L919Q is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|last_cycle_cpu_data_master_granted_slave_ext_ram_s1~12 at LC_X32_Y20_N3

--operation mode is normal

Y1L919Q_lut_out = Y1L711 & (Y1L927) # !Y1L711 & (Y1L929 & Y1L803 # !Y1L929 & (Y1L927));

Y1L919Q = DFFEAS(Y1L919Q_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--Y1L88 is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|cpu_data_master_continuerequest~3 at LC_X31_Y20_N2

--operation mode is normal

Y1L88 = Y1L919Q & S1L1688Q & !S1L1782Q & S1L209Q;

--Y1L896 is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|last_cycle_cpu_data_master_granted_slave_ext_flash_s1~3 at LC_X32_Y23_N6

--operation mode is normal

Y1L896 = Y1L899Q & (Y1L778Q # !Y1L970Q & Y1L897Q);

--Y1L897Q is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|last_cycle_cpu_data_master_granted_slave_ext_flash_s1~4 at LC_X32_Y23_N6

--operation mode is normal

Y1L897Q = DFFEAS(Y1L896, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--Y1_cpu_data_master_requests_ext_flash_s1 is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|cpu_data_master_requests_ext_flash_s1 at LC_X34_Y22_N2

--operation mode is normal

Y1_cpu_data_master_requests_ext_flash_s1 = S1L1686Q & !S1L1866Q & !S1L207Q & !T1L448Q;

--Y1L899Q is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|last_cycle_cpu_data_master_granted_slave_ext_flash_s1~5 at LC_X34_Y22_N2

--operation mode is normal

Y1L899Q = DFFEAS(Y1_cpu_data_master_requests_ext_flash_s1, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--Y1L786Q is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_avalon_slave_saved_chosen_master_vector[3]~747 at LC_X33_Y20_N8

--operation mode is normal

Y1L786Q_lut_out = !S1L1871 & !S1L1851 & Y1L92 & !T1L449;

Y1L786Q = DFFEAS(Y1L786Q_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--Y1L932 is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|last_cycle_cpu_data_master_granted_slave_lan91c111_s1~3 at LC_X30_Y21_N6

--operation mode is normal

Y1L932 = Y1L935Q & (Y1L749Q # !Y1L970Q & Y1L933Q);

--Y1L933Q is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|last_cycle_cpu_data_master_granted_slave_lan91c111_s1~4 at LC_X30_Y21_N6

--operation mode is normal

Y1L933Q = DFFEAS(Y1L932, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--Y1L145 is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|cpu_data_master_requests_lan91c111_s1~349 at LC_X29_Y20_N1

--operation mode is normal

Y1L145 = S1_M_alu_result[16] & !S1_M_alu_result[18] & !S1_M_alu_result[17] & !S1_M_alu_result[19];

--Y1L146 is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|cpu_data_master_requests_lan91c111_s1~350 at LC_X30_Y21_N7

--operation mode is normal

Y1L146 = S1L209Q & Y1L145 & S1L1688Q & S1L1782Q;

--Y1L935Q is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|last_cycle_cpu_data_master_granted_slave_lan91c111_s1~5 at LC_X30_Y21_N7

--operation mode is normal

Y1L935Q = DFFEAS(Y1L146, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--Y1L89 is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|cpu_data_master_continuerequest~103 at LC_X30_Y23_N1

--operation mode is normal

Y1L89 = Y1L786Q # Y1L88 # Y1L145 & Y1L939;

--U1L228 is std_1c20:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|internal_cpu_instruction_master_latency_counter[0]~26 at LC_X26_Y22_N6

--operation mode is normal

U1L228 = U1L232 & (!U1L170 # !U1L230 # !U1L257);

--U1_internal_cpu_instruction_master_latency_counter[0] is std_1c20:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|internal_cpu_instruction_master_latency_counter[0] at LC_X26_Y22_N6

--operation mode is normal

U1_internal_cpu_instruction_master_latency_counter[0] = DFFEAS(U1L228, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--U1L235 is std_1c20:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|internal_cpu_instruction_master_latency_counter[1]~22 at LC_X29_Y22_N1

--operation mode is normal

U1L235 = S1L1501 & (S1L1499 & (U1L244) # !S1L1499 & U1L245) # !S1L1501 & U1L245;

--U1L238Q is std_1c20:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|internal_cpu_instruction_master_latency_counter[1]~25 at LC_X29_Y22_N1

--operation mode is normal

U1L238Q = DFFEAS(U1L235, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--S1L1506Q is std_1c20:inst|cpu:the_cpu|ic_fill_ap_cnt[0]~64 at LC_X29_Y22_N8

--operation mode is normal

S1L1506Q = AMPP_FUNCTION(QC2__clk0, U1L228, U1L15, WE1L11, U1L235, F1_data_out);

--Y1L874 is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|lan91c111_s1_in_a_read_cycle~61 at LC_X30_Y23_N3

--operation mode is normal

Y1L874 = !S1L1506Q & S1L1602Q & (!Y1L89 # !Y1L820Q);

--Y1L24 is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|Add2~307 at LC_X30_Y23_N4

--operation mode is arithmetic

Y1L24 = CARRY(!Y1L5 & !Y1L874);

--Y1L25 is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|Add2~308 at LC_X30_Y22_N0

--operation mode is arithmetic

Y1L25_carry_eqn = Y1L52;

Y1L25 = Y1L25_carry_eqn $ (!Y1L824 & S1L1602Q);

--Y1L26 is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|Add2~309 at LC_X30_Y22_N0

--operation mode is arithmetic

Y1L26_cout_0 = !Y1L52 & (Y1L824 # !S1L1602Q);

Y1L26 = CARRY(Y1L26_cout_0);

--Y1L27 is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|Add2~309COUT1_733 at LC_X30_Y22_N0

--operation mode is arithmetic

Y1L27_cout_1 = !Y1L52 & (Y1L824 # !S1L1602Q);

Y1L27 = CARRY(Y1L27_cout_1);

--Y1L177 is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|cpu_instruction_master_granted_lan91c111_s1~80 at LC_X32_Y24_N3

--operation mode is normal

Y1L177 = Y1L874 & (Y1L25 # !Y1L5);

--Y1L731Q is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_avalon_slave_saved_chosen_master_vector[0]~669 at LC_X32_Y24_N3

--operation mode is normal

Y1L731Q = DFFEAS(Y1L177, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--Y1L136 is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|cpu_data_master_read_data_valid_lan91c111_s1_shift_register[0]~15 at LC_X32_Y24_N0

--operation mode is normal

Y1L136 = Y1L188 & Y1L736 & S1_internal_d_read;

--Y1_cpu_data_master_read_data_valid_lan91c111_s1_shift_register[0] is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|cpu_data_master_read_data_valid_lan91c111_s1_shift_register[0] at LC_X32_Y24_N0

--operation mode is normal

Y1_cpu_data_master_read_data_valid_lan91c111_s1_shift_register[0] = DFFEAS(Y1L136, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--Y1_cpu_data_master_read_data_valid_lan91c111_s1_shift_register[1] is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|cpu_data_master_read_data_valid_lan91c111_s1_shift_register[1] at LC_X31_Y20_N6

--operation mode is normal

Y1_cpu_data_master_read_data_valid_lan91c111_s1_shift_register[1]_lut_out = S1L1682 & (Y1L136 # Y1_cpu_data_master_read_data_valid_lan91c111_s1_shift_register[0]);

Y1_cpu_data_master_read_data_valid_lan91c111_s1_shift_register[1] = DFFEAS(Y1_cpu_data_master_read_data_valid_lan91c111_s1_shift_register[1]_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--Y1L955 is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|last_cycle_cpu_instruction_master_granted_slave_ext_ram_s1~3 at LC_X28_Y21_N8

--operation mode is normal

Y1L955 = Y1L958Q & (Y1L795Q # Y1L956Q & !Y1L970Q);

--Y1L956Q is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|last_cycle_cpu_instruction_master_granted_slave_ext_ram_s1~4 at LC_X28_Y21_N8

--operation mode is normal

Y1L956Q = DFFEAS(Y1L955, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--Y1L193 is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|cpu_instruction_master_requests_ext_flash_s1~35 at LC_X27_Y22_N3

--operation mode is normal

Y1L193 = !S1L1636Q & S1L1574Q & !S1L1633Q;

--Y1L151 is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|cpu_instruction_master_continuerequest~3 at LC_X27_Y21_N9

--operation mode is normal

Y1L151 = Y1L1005 & S1L1575 & Y1L161 & !Y1L163;

--S1L1624Q is std_1c20:inst|cpu:the_cpu|ic_fill_tag[9]~106 at LC_X27_Y21_N9

--operation mode is normal

S1L1624Q = AMPP_FUNCTION(QC2__clk0, Y1L1005, S1L1575, Y1L161, Y1L163, F1_data_out);

--Y1L945 is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|last_cycle_cpu_instruction_master_granted_slave_ext_flash_s1~3 at LC_X28_Y24_N5

--operation mode is normal

Y1L945 = Y1L948Q & (Y1L766Q # Y1L946Q & !Y1L970Q);

--Y1L946Q is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|last_cycle_cpu_instruction_master_granted_slave_ext_flash_s1~4 at LC_X28_Y24_N5

--operation mode is normal

Y1L946Q = DFFEAS(Y1L945, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--Y1L194 is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|cpu_instruction_master_requests_ext_flash_s1~36 at LC_X27_Y22_N1

--operation mode is normal

Y1L194 = S1L1574Q & !S1L1633Q & !S1L1642Q & !S1L1636Q;

--Y1L948Q is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|last_cycle_cpu_instruction_master_granted_slave_ext_flash_s1~5 at LC_X27_Y22_N1

--operation mode is normal

Y1L948Q = DFFEAS(Y1L194, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--Y1L150 is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|cpu_instruction_master_continuerequest~1 at LC_X27_Y21_N2

--operation mode is normal

Y1L150 = S1L1575 & Y1L165 & (Y1L169 # Y1L167);

--S1L1625Q is std_1c20:inst|cpu:the_cpu|ic_fill_tag[9]~107 at LC_X27_Y21_N2

--operation mode is normal

S1L1625Q = AMPP_FUNCTION(QC2__clk0, Y1L169, S1L1575, Y1L165, Y1L167, F1_data_out);

--Y1L965 is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|last_cycle_cpu_instruction_master_granted_slave_lan91c111_s1~3 at LC_X31_Y22_N3

--operation mode is normal

Y1L965 = Y1L966Q & (Y1L733Q # !Y1L970Q & Y1L968Q);

--Y1L968Q is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|last_cycle_cpu_instruction_master_granted_slave_lan91c111_s1~5 at LC_X31_Y22_N3

--operation mode is normal

Y1L968Q = DFFEAS(Y1L965, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--S1L1629Q is std_1c20:inst|cpu:the_cpu|ic_fill_tag[9]~157 at LC_X30_Y21_N9

--operation mode is normal

S1L1629Q = AMPP_FUNCTION(QC2__clk0, Y1L150, Y1L969, Y1L151, Y1L967, F1_data_out);

--Y1L28 is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|Add2~310 at LC_X30_Y23_N5

--operation mode is arithmetic

Y1L28_carry_eqn = Y1L24;

Y1L28 = Y1L599 $ Y1L111 $ !Y1L28_carry_eqn;

--Y1L29 is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|Add2~311 at LC_X30_Y23_N5

--operation mode is arithmetic

Y1L29_cout_0 = Y1L599 & Y1L111 & !Y1L24 # !Y1L599 & (Y1L111 # !Y1L24);

Y1L29 = CARRY(Y1L29_cout_0);

--Y1L30 is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|Add2~311COUT1_725 at LC_X30_Y23_N5

--operation mode is arithmetic

Y1L30_cout_1 = Y1L599 & Y1L111 & !Y1L24 # !Y1L599 & (Y1L111 # !Y1L24);

Y1L30 = CARRY(Y1L30_cout_1);

--Y1L31 is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|Add2~312 at LC_X30_Y22_N1

--operation mode is arithmetic

Y1L31_carry_eqn = (!Y1L52 & Y1L26) # (Y1L52 & Y1L27);

Y1L31 = Y1L112 $ !Y1L31_carry_eqn;

--Y1L32 is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|Add2~313 at LC_X30_Y22_N1

--operation mode is arithmetic

Y1L32_cout_0 = Y1L112 # !Y1L26;

Y1L32 = CARRY(Y1L32_cout_0);

--Y1L33 is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|Add2~313COUT1_735 at LC_X30_Y22_N1

--operation mode is arithmetic

Y1L33_cout_1 = Y1L112 # !Y1L27;

Y1L33 = CARRY(Y1L33_cout_1);

--Y1L97 is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|cpu_data_master_granted_lan91c111_s1~149 at LC_X33_Y26_N1

--operation mode is normal

Y1L97 = Y1L112 & (Y1L28 # Y1L31);

--Y1L747Q is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_avalon_slave_saved_chosen_master_vector[1]~660 at LC_X33_Y26_N1

--operation mode is normal

Y1L747Q = DFFEAS(Y1L97, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--T1_internal_cpu_data_master_dbs_address[1] is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|internal_cpu_data_master_dbs_address[1] at LC_X33_Y26_N4

--operation mode is normal

T1_internal_cpu_data_master_dbs_address[1]_lut_out = T1_internal_cpu_data_master_dbs_address[1] $ (S1L1689Q & T1L524 & T1_internal_cpu_data_master_dbs_address[0]);

T1_internal_cpu_data_master_dbs_address[1] = DFFEAS(T1_internal_cpu_data_master_dbs_address[1]_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--T1_internal_cpu_data_master_dbs_address[0] is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|internal_cpu_data_master_dbs_address[0] at LC_X24_Y29_N2

--operation mode is normal

T1_internal_cpu_data_master_dbs_address[0]_lut_out = T1_internal_cpu_data_master_dbs_address[0] $ (T1L440 & (T1L523) # !T1L440 & T1L438);

T1_internal_cpu_data_master_dbs_address[0] = DFFEAS(T1_internal_cpu_data_master_dbs_address[0]_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--Y1L83 is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|cpu_data_master_byteenable_ext_flash_s1~310 at LC_X29_Y21_N6

--operation mode is normal

Y1L83 = T1L453 & (T1L441 & S1L2180 # !T1L441 & (S1L2171));

--T1L445Q is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|internal_cpu_data_master_dbs_address[1]~55 at LC_X29_Y21_N6

--operation mode is normal

T1L445Q = DFFEAS(Y1L83, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--Y1L85 is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|cpu_data_master_byteenable_ext_flash_s1~311 at LC_X29_Y21_N4

--operation mode is normal

Y1L85 = !T1L453 & (T1L441 & S1L2161 # !T1L441 & (S1L2152));

--S1L2162Q is std_1c20:inst|cpu:the_cpu|M_mem_byte_en[1]~132 at LC_X29_Y21_N4

--operation mode is normal

S1L2162Q = AMPP_FUNCTION(QC2__clk0, T1L441, S1L2161, S1L2152, T1L453, F1_data_out);

--T1L456 is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|internal_cpu_data_master_no_byte_enables_and_last_term~4 at LC_X29_Y21_N9

--operation mode is normal

T1L456 = S1_internal_d_write & T1_internal_cpu_data_master_dbs_address[1] & !S1L2177Q & T1_internal_cpu_data_master_dbs_address[0];

--T1_internal_cpu_data_master_no_byte_enables_and_last_term is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|internal_cpu_data_master_no_byte_enables_and_last_term at LC_X29_Y21_N9

--operation mode is normal

T1_internal_cpu_data_master_no_byte_enables_and_last_term = DFFEAS(T1L456, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--T1L452Q is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|internal_cpu_data_master_dbs_address[1]~81 at LC_X29_Y21_N7

--operation mode is normal

T1L452Q_lut_out = S1L1685 & (T1L456 # !Y1L85 & !Y1L83);

T1L452Q = DFFEAS(T1L452Q_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--Y1L119 is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|cpu_data_master_read_data_valid_ext_flash_s1_shift_register[0]~24 at LC_X32_Y24_N9

--operation mode is normal

Y1L119 = Y1L118 & Y1L122 & (Y1L653Q # Y1L718);

--Y1_cpu_data_master_read_data_valid_ext_flash_s1_shift_register[0] is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|cpu_data_master_read_data_valid_ext_flash_s1_shift_register[0] at LC_X32_Y24_N9

--operation mode is normal

Y1_cpu_data_master_read_data_valid_ext_flash_s1_shift_register[0] = DFFEAS(Y1L119, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--Y1_cpu_data_master_read_data_valid_ext_flash_s1_shift_register[1] is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|cpu_data_master_read_data_valid_ext_flash_s1_shift_register[1] at LC_X32_Y24_N7

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

Y1_cpu_data_master_read_data_valid_ext_flash_s1_shift_register[1]_lut_out = Y1L900 & (!Y1_cpu_data_master_read_data_valid_ext_flash_s1_shift_register[0] & !Y1L119 # !S1L1682);

Y1_cpu_data_master_read_data_valid_ext_flash_s1_shift_register[1] = DFFEAS(Y1_cpu_data_master_read_data_valid_ext_flash_s1_shift_register[1]_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , Y1_cpu_data_master_read_data_valid_ext_flash_s1_shift_register[0], , , VCC);

--Y1L100 is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|cpu_data_master_qualified_request_ext_flash_s1~151 at LC_X29_Y21_N5

--operation mode is normal

Y1L100 = S1L210Q & !T1L452Q & (!Y1L820Q # !S1L1629Q);

--Y1L125 is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|cpu_data_master_read_data_valid_ext_ram_s1_shift_register[0]~21 at LC_X33_Y25_N6

--operation mode is normal

Y1L125 = Y1L130 & Y1L104 & (Y1L53 # Y1L51);

--Y1_cpu_data_master_read_data_valid_ext_ram_s1_shift_register[0] is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|cpu_data_master_read_data_valid_ext_ram_s1_shift_register[0] at LC_X33_Y25_N6

--operation mode is normal

Y1_cpu_data_master_read_data_valid_ext_ram_s1_shift_register[0] = DFFEAS(Y1L125, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--Y1_cpu_data_master_read_data_valid_ext_ram_s1_shift_register[1] is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|cpu_data_master_read_data_valid_ext_ram_s1_shift_register[1] at LC_X33_Y25_N2

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

Y1_cpu_data_master_read_data_valid_ext_ram_s1_shift_register[1]_lut_out = S1L1682 & (Y1L125 # Y1_cpu_data_master_read_data_valid_ext_ram_s1_shift_register[0]);

Y1_cpu_data_master_read_data_valid_ext_ram_s1_shift_register[1] = DFFEAS(Y1_cpu_data_master_read_data_valid_ext_ram_s1_shift_register[1]_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , Y1_cpu_data_master_read_data_valid_ext_ram_s1_shift_register[0], , , VCC);

--S1L1797Q is std_1c20:inst|cpu:the_cpu|M_alu_result[20]~470 at LC_X31_Y21_N9

--operation mode is normal

S1L1797Q = AMPP_FUNCTION(QC2__clk0, S1L1803, S1L208, S1L1817, Y1L106, F1_data_out);

--T1L458 is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|internal_cpu_data_master_waitrequest~25 at LC_X32_Y22_N3

--operation mode is normal

T1L458 = !T1L8 & T1L468 & T1L464 & !T1L466;

--T1_internal_cpu_data_master_waitrequest is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|internal_cpu_data_master_waitrequest at LC_X32_Y22_N3

--operation mode is normal

T1_internal_cpu_data_master_waitrequest = DFFEAS(T1L458, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--Y1L1036Q is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|write_n_to_the_ext_ram_local~13 at LC_X32_Y22_N9

--operation mode is normal

Y1L1036Q_lut_out = S1L1685 & (Y1L1035 # T1L458);

Y1L1036Q = DFFEAS(Y1L1036Q_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--Y1L104 is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|cpu_data_master_qualified_request_ext_ram_s1~142 at LC_X31_Y21_N4

--operation mode is normal

Y1L104 = S1L1797Q & !Y1L1036Q & (!Y1L819Q # !S1L1629Q);

--T1L1 is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|A_WE_StdLogicVector~1427 at LC_X30_Y26_N0

--operation mode is normal

T1L1 = !Y1L104 & (!Y1L100 & !Y1L112);

--Y1L1005 is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|p1_read_n_to_the_ext_ram~61 at LC_X28_Y21_N6

--operation mode is normal

Y1L1005 = !S1L1609Q & Y1L193 & (S1L1618Q);

--Y1L958Q is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|last_cycle_cpu_instruction_master_granted_slave_ext_ram_s1~5 at LC_X28_Y21_N6

--operation mode is normal

Y1L958Q = DFFEAS(Y1L1005, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--Y1L1007 is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|p1_read_n_to_the_ext_ram~62 at LC_X30_Y23_N2

--operation mode is normal

Y1L1007 = !S1L1506Q & S1L1640Q & (!Y1L89 # !Y1L820Q);

--U1L223 is std_1c20:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|internal_cpu_instruction_master_dbs_address[1]~49 at LC_X30_Y23_N0

--operation mode is normal

U1L223 = !S1L1506Q & S1L1507Q & (!Y1L89 # !Y1L820Q);

--Y1L718 is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_avalon_slave_begins_xfer~61 at LC_X30_Y26_N1

--operation mode is normal

Y1L718 = !U1L223 & T1L1 & !Y1L1007 & !Y1L874;

--Y1_ext_ram_bus_avalon_slave_begins_xfer is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_avalon_slave_begins_xfer at LC_X30_Y26_N9

--operation mode is normal

Y1_ext_ram_bus_avalon_slave_begins_xfer = !Y1L653Q & (Y1L874 # !Y1L720 # !T1L1);

--Y1L34 is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|Add2~314 at LC_X30_Y23_N7

--operation mode is arithmetic

Y1L34_carry_eqn = (!Y1L24 & Y1L41) # (Y1L24 & Y1L42);

Y1L34 = Y1L623 $ Y1L100 $ !Y1L34_carry_eqn;

--Y1L35 is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|Add2~315 at LC_X30_Y23_N7

--operation mode is arithmetic

Y1L35_cout_0 = Y1L623 & Y1L100 & !Y1L41 # !Y1L623 & (Y1L100 # !Y1L41);

Y1L35 = CARRY(Y1L35_cout_0);

--Y1L36 is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|Add2~315COUT1_729 at LC_X30_Y23_N7

--operation mode is arithmetic

Y1L36_cout_1 = Y1L623 & Y1L100 & !Y1L42 # !Y1L623 & (Y1L100 # !Y1L42);

Y1L36 = CARRY(Y1L36_cout_1);

--Y1L37 is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|Add2~316 at LC_X30_Y22_N3

--operation mode is arithmetic

Y1L37_carry_eqn = (!Y1L52 & Y1L44) # (Y1L52 & Y1L45);

Y1L37 = Y1L100 $ !Y1L37_carry_eqn;

--Y1L38 is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|Add2~317 at LC_X30_Y22_N3

--operation mode is arithmetic

Y1L38_cout_0 = Y1L100 # !Y1L44;

Y1L38 = CARRY(Y1L38_cout_0);

--Y1L39 is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|Add2~317COUT1_739 at LC_X30_Y22_N3

--operation mode is arithmetic

Y1L39_cout_1 = Y1L100 # !Y1L45;

Y1L39 = CARRY(Y1L39_cout_1);

--Y1L372 is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_flash_s1_counter_load_value[1]~166 at LC_X29_Y25_N6

--operation mode is normal

Y1L372 = Y1L100 & S1_internal_d_write & (Y1L37 # Y1L34);

--Y1L197Q is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_ext_ram_bus_avalon_slave_end_xfer~3 at LC_X29_Y25_N6

--operation mode is normal

Y1L197Q = DFFEAS(Y1L372, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--Y1L396Q is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_flash_s1_wait_counter[3]~86 at LC_X31_Y27_N5

--operation mode is normal

Y1L396Q_lut_out = Y1L403 # Y1_ext_ram_bus_avalon_slave_begins_xfer & (Y1L372 # !Y1L405);

Y1L396Q = DFFEAS(Y1L396Q_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--Y1L387Q is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_flash_s1_wait_counter[2]~91 at LC_X30_Y27_N9

--operation mode is normal

Y1L387Q_lut_out = Y1L393 & (!Y1L372 & Y1L391 # !Y1_ext_ram_bus_avalon_slave_begins_xfer);

Y1L387Q = DFFEAS(Y1L387Q_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--Y1_ext_flash_s1_wait_counter[1] is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_flash_s1_wait_counter[1] at LC_X31_Y27_N2

--operation mode is normal

Y1_ext_flash_s1_wait_counter[1]_lut_out = Y1_ext_ram_bus_avalon_slave_begins_xfer & !Y1L204 & (Y1L373 # Y1L372) # !Y1_ext_ram_bus_avalon_slave_begins_xfer & Y1L373;

Y1_ext_flash_s1_wait_counter[1] = DFFEAS(Y1_ext_flash_s1_wait_counter[1]_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--Y1L1010 is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|p1_write_n_to_the_ext_flash~116 at LC_X31_Y27_N4

--operation mode is normal

Y1L1010 = !Y1_ext_flash_s1_wait_counter[1] & (!Y1L387Q);

--Y1L397Q is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_flash_s1_wait_counter[3]~87 at LC_X31_Y27_N4

--operation mode is normal

Y1L397Q = DFFEAS(Y1L1010, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--Y1L880Q is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|lan91c111_s1_wait_counter[0]~115 at LC_X32_Y26_N3

--operation mode is normal

Y1L880Q_lut_out = !Y1L879Q & (Y1L885Q # Y1L878Q # !Y1L880Q);

Y1L880Q = DFFEAS(Y1L880Q_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--Y1_lan91c111_s1_wait_counter[3] is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|lan91c111_s1_wait_counter[3] at LC_X32_Y27_N3

--operation mode is normal

Y1_lan91c111_s1_wait_counter[3]_lut_out = Y1L54 # Y1_ext_ram_bus_avalon_slave_begins_xfer & (Y1L725 # Y1L177);

Y1_lan91c111_s1_wait_counter[3] = DFFEAS(Y1_lan91c111_s1_wait_counter[3]_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--Y1L889 is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|lan91c111_s1_wait_counter[2]~107 at LC_X32_Y27_N0

--operation mode is normal

Y1L889 = !Y1L893Q & Y1L891Q & (Y1L892Q $ Y1L890Q);

--Y1L890Q is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|lan91c111_s1_wait_counter[2]~108 at LC_X32_Y27_N0

--operation mode is normal

Y1L890Q = DFFEAS(Y1L889, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--Y1L882 is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|lan91c111_s1_wait_counter[1]~100 at LC_X32_Y27_N2

--operation mode is normal

Y1L882 = Y1L886Q & (Y1L884Q & (Y1L883Q) # !Y1L884Q & !Y1L885Q & !Y1L883Q);

--Y1L884Q is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|lan91c111_s1_wait_counter[1]~102 at LC_X32_Y27_N2

--operation mode is normal

Y1L884Q = DFFEAS(Y1L882, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--Y1L976 is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|LessThan1~90 at LC_X32_Y27_N1

--operation mode is normal

Y1L976 = Y1L882 # Y1_lan91c111_s1_wait_counter[3] # Y1L978 # Y1L889;

--Y1L891Q is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|lan91c111_s1_wait_counter[2]~109 at LC_X32_Y27_N1

--operation mode is normal

Y1L891Q = DFFEAS(Y1L976, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--Y1L122 is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|cpu_data_master_read_data_valid_ext_flash_s1_shift_register_in~19 at LC_X29_Y24_N8

--operation mode is normal

Y1L122 = S1_internal_d_read & Y1L100 & (Y1L37 # Y1L34);

--Y1L40 is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|Add2~318 at LC_X30_Y23_N6

--operation mode is arithmetic

Y1L40_carry_eqn = (!Y1L24 & Y1L29) # (Y1L24 & Y1L30);

Y1L40 = Y1L610 $ U1L223 $ Y1L40_carry_eqn;

--Y1L41 is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|Add2~319 at LC_X30_Y23_N6

--operation mode is arithmetic

Y1L41_cout_0 = Y1L610 & (!Y1L29 # !U1L223) # !Y1L610 & !U1L223 & !Y1L29;

Y1L41 = CARRY(Y1L41_cout_0);

--Y1L42 is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|Add2~319COUT1_727 at LC_X30_Y23_N6

--operation mode is arithmetic

Y1L42_cout_1 = Y1L610 & (!Y1L30 # !U1L223) # !Y1L610 & !U1L223 & !Y1L30;

Y1L42 = CARRY(Y1L42_cout_1);

--Y1L43 is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|Add2~320 at LC_X30_Y22_N2

--operation mode is arithmetic

Y1L43_carry_eqn = (!Y1L52 & Y1L32) # (Y1L52 & Y1L33);

Y1L43 = Y1L43_carry_eqn $ (!Y1L824 & S1L1507Q);

--Y1L44 is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|Add2~321 at LC_X30_Y22_N2

--operation mode is arithmetic

Y1L44_cout_0 = !Y1L32 & (Y1L824 # !S1L1507Q);

Y1L44 = CARRY(Y1L44_cout_0);

--Y1L45 is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|Add2~321COUT1_737 at LC_X30_Y22_N2

--operation mode is arithmetic

Y1L45_cout_1 = !Y1L33 & (Y1L824 # !S1L1507Q);

Y1L45 = CARRY(Y1L45_cout_1);

--Y1L175 is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|cpu_instruction_master_granted_ext_flash_s1~46 at LC_X26_Y23_N1

--operation mode is normal

Y1L175 = U1L223 & (Y1L43 # Y1L40);

--Y1L763Q is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_avalon_slave_saved_chosen_master_vector[2]~666 at LC_X26_Y23_N1

--operation mode is normal

Y1L763Q = DFFEAS(Y1L175, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--Y1L46 is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|Add2~322 at LC_X30_Y23_N8

--operation mode is arithmetic

Y1L46_carry_eqn = (!Y1L24 & Y1L35) # (Y1L24 & Y1L36);

Y1L46 = Y1L1007 $ Y1L642 $ Y1L46_carry_eqn;

--Y1L47 is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|Add2~323 at LC_X30_Y23_N8

--operation mode is arithmetic

Y1L47_cout_0 = Y1L1007 & Y1L642 & !Y1L35 # !Y1L1007 & (Y1L642 # !Y1L35);

Y1L47 = CARRY(Y1L47_cout_0);

--Y1L48 is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|Add2~323COUT1_731 at LC_X30_Y23_N8

--operation mode is arithmetic

Y1L48_cout_1 = Y1L1007 & Y1L642 & !Y1L36 # !Y1L1007 & (Y1L642 # !Y1L36);

Y1L48 = CARRY(Y1L48_cout_1);

--Y1L49 is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|Add2~324 at LC_X30_Y22_N4

--operation mode is arithmetic

Y1L49_carry_eqn = (!Y1L52 & Y1L38) # (Y1L52 & Y1L39);

Y1L49 = Y1L49_carry_eqn $ (!Y1L824 & S1L1640Q);

--Y1L50 is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|Add2~325 at LC_X30_Y22_N4

--operation mode is arithmetic

Y1L50 = CARRY(!Y1L39 & (Y1L824 # !S1L1640Q));

--Y1L176 is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|cpu_instruction_master_granted_ext_ram_s1~39 at LC_X27_Y22_N7

--operation mode is normal

Y1L176 = Y1L1007 & (Y1L46 # Y1L49);

--Y1L793Q is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_avalon_slave_saved_chosen_master_vector[4]~663 at LC_X27_Y22_N7

--operation mode is normal

Y1L793Q = DFFEAS(Y1L176, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--Y1L51 is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|Add2~326 at LC_X30_Y23_N9

--operation mode is arithmetic

Y1L51_carry_eqn = (!Y1L24 & Y1L47) # (Y1L24 & Y1L48);

Y1L51 = Y1L104 $ Y1L671 $ !Y1L51_carry_eqn;

--Y1L52 is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|Add2~327 at LC_X30_Y23_N9

--operation mode is arithmetic

Y1L52 = CARRY(Y1L104 & (!Y1L48 # !Y1L671) # !Y1L104 & !Y1L671 & !Y1L48);

--Y1L53 is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|Add2~328 at LC_X30_Y22_N5

--operation mode is normal

Y1L53_carry_eqn = Y1L50;

Y1L53 = Y1L53_carry_eqn $ !Y1L104;

--Y1L96 is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|cpu_data_master_granted_ext_ram_s1~90 at LC_X32_Y22_N5

--operation mode is normal

Y1L96 = Y1L104 & (Y1L51 # Y1L53);

--Y1L804Q is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_avalon_slave_saved_chosen_master_vector[5]~653 at LC_X32_Y22_N5

--operation mode is normal

Y1L804Q = DFFEAS(Y1L96, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--Y1L998 is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|p1_ext_ram_bus_address[1]~3405 at LC_X29_Y23_N8

--operation mode is normal

Y1L998 = !Y1L770 & (!Y1L34 & !Y1L37 # !Y1L100);

--KB1_m_state[6] is std_1c20:inst|sdram:the_sdram|m_state[6] at LC_X12_Y22_N3

--operation mode is normal

KB1_m_state[6]_lut_out = KB1L519 # KB1L539 & (KB1L520 # KB1L523);

KB1_m_state[6] = DFFEAS(KB1_m_state[6]_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--KB1_m_state[1] is std_1c20:inst|sdram:the_sdram|m_state[1] at LC_X12_Y22_N5

--operation mode is normal

KB1_m_state[1]_lut_out = KB1L551 # KB1L552 & (KB1L525 # KB1L554);

KB1_m_state[1] = DFFEAS(KB1_m_state[1]_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--KB1_m_state[8] is std_1c20:inst|sdram:the_sdram|m_state[8] at LC_X15_Y22_N3

--operation mode is normal

KB1_m_state[8]_lut_out = KB1_m_state[8] $ (KB1L984 & KB1L515 & KB1L514);

KB1_m_state[8] = DFFEAS(KB1_m_state[8]_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--KB1_m_state[5] is std_1c20:inst|sdram:the_sdram|m_state[5] at LC_X12_Y22_N0

--operation mode is normal

KB1_m_state[5]_lut_out = KB1L527 # KB1L524 & (KB1L528 # KB1L525);

KB1_m_state[5] = DFFEAS(KB1_m_state[5]_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--KB1_m_state[2] is std_1c20:inst|sdram:the_sdram|m_state[2] at LC_X13_Y24_N5

--operation mode is normal

KB1_m_state[2]_lut_out = KB1L540 # KB1L541 & (KB1L548 # KB1L545);

KB1_m_state[2] = DFFEAS(KB1_m_state[2]_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--KB1L705 is std_1c20:inst|sdram:the_sdram|Mux104~1605 at LC_X11_Y23_N3

--operation mode is normal

KB1L705 = !KB1_m_state[8] & !KB1_m_state[2] & !KB1_m_state[5];

--KB1L502 is std_1c20:inst|sdram:the_sdram|Mux19~1736 at LC_X12_Y21_N4

--operation mode is normal

KB1L502 = KB1_m_state[1] # KB1_m_state[6] # !KB1L705;

--KB1_m_state[7] is std_1c20:inst|sdram:the_sdram|m_state[7] at LC_X13_Y25_N3

--operation mode is normal

KB1_m_state[7]_lut_out = KB1L517 # KB1_m_state[7] & (!KB1L497 # !KB1L496);

KB1_m_state[7] = DFFEAS(KB1_m_state[7]_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--KB1_m_state[4] is std_1c20:inst|sdram:the_sdram|m_state[4] at LC_X14_Y25_N4

--operation mode is normal

KB1_m_state[4]_lut_out = KB1L529 # KB1L984 & KB1L646 & KB1L533;

KB1_m_state[4] = DFFEAS(KB1_m_state[4]_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--KB1_m_state[3] is std_1c20:inst|sdram:the_sdram|m_state[3] at LC_X14_Y25_N2

--operation mode is normal

KB1_m_state[3]_lut_out = KB1L535 # KB1L984 & KB1L537 & KB1L536;

KB1_m_state[3] = DFFEAS(KB1_m_state[3]_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--KB1_m_state[0] is std_1c20:inst|sdram:the_sdram|m_state[0] at LC_X15_Y22_N5

--operation mode is normal

KB1_m_state[0]_lut_out = !KB1L555 & (KB1_m_state[0] # KB1L30 & !KB1L1011);

KB1_m_state[0] = DFFEAS(KB1_m_state[0]_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--KB1L503 is std_1c20:inst|sdram:the_sdram|Mux19~1737 at LC_X13_Y21_N9

--operation mode is normal

KB1L503 = KB1_m_state[0] & (!KB1_m_state[4] & !KB1_m_state[3] # !KB1_m_state[7]);

--KB1_f_pop is std_1c20:inst|sdram:the_sdram|f_pop at LC_X16_Y22_N9

--operation mode is normal

KB1_f_pop_lut_out = KB1L673 & (KB1L675 # KB1L544 & KB1_m_state[0]);

KB1_f_pop = DFFEAS(KB1_f_pop_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--TE1_rd_address is std_1c20:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|rd_address at LC_X17_Y22_N0

--operation mode is normal

TE1_rd_address_lut_out = TE1_rd_address $ (KB1_f_pop & !KB1L991 & TE1L152);

TE1_rd_address = DFFEAS(TE1_rd_address_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--KB1_active_addr[9] is std_1c20:inst|sdram:the_sdram|active_addr[9] at LC_X17_Y21_N0

--operation mode is normal

KB1_active_addr[9]_lut_out = KB1L676 & (F1_data_out & KB1L703 # !F1_data_out & (KB1_active_addr[9])) # !KB1L676 & (KB1_active_addr[9]);

KB1_active_addr[9] = DFFEAS(KB1_active_addr[9]_lut_out, GLOBAL(QC2__clk0), VCC, , , , , , );

--TE1_entry_0[45] is std_1c20:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_0[45] at LC_X18_Y23_N6

--operation mode is normal

TE1_entry_0[45]_lut_out = NB1L20 & S1_M_alu_result[11] # !NB1L20 & (S1L1559Q);

TE1_entry_0[45] = DFFEAS(TE1_entry_0[45]_lut_out, GLOBAL(QC2__clk0), VCC, , TE1L84, , , , );

--KB1_active_addr[8] is std_1c20:inst|sdram:the_sdram|active_addr[8] at LC_X18_Y22_N3

--operation mode is normal

KB1_active_addr[8]_lut_out = KB1L14 & (KB1L12 & TE1L198 # !KB1L12 & (KB1_active_addr[8])) # !KB1L14 & (KB1_active_addr[8]);

KB1_active_addr[8] = DFFEAS(KB1_active_addr[8]_lut_out, GLOBAL(QC2__clk0), VCC, , , , , , );

--TE1_entry_0[44] is std_1c20:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_0[44] at LC_X17_Y23_N0

--operation mode is normal

TE1_entry_0[44]_lut_out = NB1L20 & (S1L1756Q) # !NB1L20 & S1_ic_fill_line[5];

TE1_entry_0[44] = DFFEAS(TE1_entry_0[44]_lut_out, GLOBAL(QC2__clk0), VCC, , TE1L84, , , , );

--KB1_active_addr[14] is std_1c20:inst|sdram:the_sdram|active_addr[14] at LC_X17_Y21_N7

--operation mode is normal

KB1_active_addr[14]_lut_out = KB1L676 & (F1_data_out & (KB1L691) # !F1_data_out & KB1_active_addr[14]) # !KB1L676 & (KB1_active_addr[14]);

KB1_active_addr[14] = DFFEAS(KB1_active_addr[14]_lut_out, GLOBAL(QC2__clk0), VCC, , , , , , );

--TE1_entry_0[50] is std_1c20:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_0[50] at LC_X18_Y23_N3

--operation mode is normal

TE1_entry_0[50]_lut_out = NB1L20 & S1_M_alu_result[16] # !NB1L20 & (S1L1587Q);

TE1_entry_0[50] = DFFEAS(TE1_entry_0[50]_lut_out, GLOBAL(QC2__clk0), VCC, , TE1L84, , , , );

--KB1_active_addr[13] is std_1c20:inst|sdram:the_sdram|active_addr[13] at LC_X16_Y20_N2

--operation mode is normal

KB1_active_addr[13]_lut_out = KB1L676 & (F1_data_out & (KB1L693) # !F1_data_out & KB1_active_addr[13]) # !KB1L676 & KB1_active_addr[13];

KB1_active_addr[13] = DFFEAS(KB1_active_addr[13]_lut_out, GLOBAL(QC2__clk0), VCC, , , , , , );

--TE1_entry_0[49] is std_1c20:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_0[49] at LC_X18_Y23_N5

--operation mode is normal

TE1_entry_0[49]_lut_out = NB1L20 & S1_M_alu_result[15] # !NB1L20 & (S1L1583Q);

TE1_entry_0[49] = DFFEAS(TE1_entry_0[49]_lut_out, GLOBAL(QC2__clk0), VCC, , TE1L84, , , , );

--KB1L987 is std_1c20:inst|sdram:the_sdram|pending~245 at LC_X18_Y23_N8

--operation mode is normal

KB1L987 = TE1L66 # TE1L50 # TE1L63 # TE1L53;

--KB1_active_addr[11] is std_1c20:inst|sdram:the_sdram|active_addr[11] at LC_X16_Y20_N1

--operation mode is normal

KB1_active_addr[11]_lut_out = KB1L676 & (F1_data_out & (KB1L697) # !F1_data_out & KB1_active_addr[11]) # !KB1L676 & KB1_active_addr[11];

KB1_active_addr[11] = DFFEAS(KB1_active_addr[11]_lut_out, GLOBAL(QC2__clk0), VCC, , , , , , );

--TE1_entry_0[47] is std_1c20:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_0[47] at LC_X21_Y21_N3

--operation mode is normal

TE1_entry_0[47]_lut_out = NB1L20 & S1_M_alu_result[13] # !NB1L20 & (S1L1577Q);

TE1_entry_0[47] = DFFEAS(TE1_entry_0[47]_lut_out, GLOBAL(QC2__clk0), VCC, , TE1L84, , , , );

--KB1_active_addr[21] is std_1c20:inst|sdram:the_sdram|active_addr[21] at LC_X18_Y22_N6

--operation mode is normal

KB1_active_addr[21]_lut_out = KB1L12 & (KB1L14 & TE1L199 # !KB1L14 & (KB1_active_addr[21])) # !KB1L12 & (KB1_active_addr[21]);

KB1_active_addr[21] = DFFEAS(KB1_active_addr[21]_lut_out, GLOBAL(QC2__clk0), VCC, , , , , , );

--KB1L114 is std_1c20:inst|sdram:the_sdram|Equal3~79 at LC_X17_Y22_N3

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

TE1_entry_0[57]_qfbk = TE1_entry_0[57];

KB1L114 = KB1_active_addr[21] $ (TE1_rd_address & TE1_entry_1[57] # !TE1_rd_address & (TE1_entry_0[57]_qfbk));

--TE1_entry_0[57] is std_1c20:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_0[57] at LC_X17_Y22_N3

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

TE1_entry_0[57] = DFFEAS(KB1L114, GLOBAL(QC2__clk0), VCC, , TE1L84, NB1L60, , , VCC);

--KB1_active_addr[16] is std_1c20:inst|sdram:the_sdram|active_addr[16] at LC_X17_Y21_N5

--operation mode is normal

KB1_active_addr[16]_lut_out = F1_data_out & (KB1L676 & (KB1L687) # !KB1L676 & KB1_active_addr[16]) # !F1_data_out & KB1_active_addr[16];

KB1_active_addr[16] = DFFEAS(KB1_active_addr[16]_lut_out, GLOBAL(QC2__clk0), VCC, , , , , , );

--TE1_entry_0[52] is std_1c20:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_0[52] at LC_X21_Y21_N6

--operation mode is normal

TE1_entry_0[52]_lut_out = NB1L20 & (S1_M_alu_result[18]) # !NB1L20 & S1_ic_fill_tag[6];

TE1_entry_0[52] = DFFEAS(TE1_entry_0[52]_lut_out, GLOBAL(QC2__clk0), VCC, , TE1L84, , , , );

--KB1_active_addr[15] is std_1c20:inst|sdram:the_sdram|active_addr[15] at LC_X16_Y20_N6

--operation mode is normal

KB1_active_addr[15]_lut_out = KB1L676 & (F1_data_out & (KB1L689) # !F1_data_out & KB1_active_addr[15]) # !KB1L676 & KB1_active_addr[15];

KB1_active_addr[15] = DFFEAS(KB1_active_addr[15]_lut_out, GLOBAL(QC2__clk0), VCC, , , , , , );

--TE1_entry_0[51] is std_1c20:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_0[51] at LC_X18_Y20_N7

--operation mode is normal

TE1_entry_0[51]_lut_out = NB1L20 & (S1_M_alu_result[17]) # !NB1L20 & S1L1593Q;

TE1_entry_0[51] = DFFEAS(TE1_entry_0[51]_lut_out, GLOBAL(QC2__clk0), VCC, , TE1L84, , , , );

--KB1L988 is std_1c20:inst|sdram:the_sdram|pending~246 at LC_X17_Y22_N5

--operation mode is normal

KB1L988 = TE1L59 # KB1L114 # TE1L72 # TE1L69;

--KB1_active_addr[17] is std_1c20:inst|sdram:the_sdram|active_addr[17] at LC_X16_Y20_N9

--operation mode is normal

KB1_active_addr[17]_lut_out = F1_data_out & (KB1L676 & (KB1L685) # !KB1L676 & KB1_active_addr[17]) # !F1_data_out & KB1_active_addr[17];

KB1_active_addr[17] = DFFEAS(KB1_active_addr[17]_lut_out, GLOBAL(QC2__clk0), VCC, , , , , , );

--TE1_entry_0[53] is std_1c20:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_0[53] at LC_X17_Y20_N9

--operation mode is normal

TE1_entry_0[53]_lut_out = NB1L20 & (S1_M_alu_result[19]) # !NB1L20 & S1_ic_fill_tag[7];

TE1_entry_0[53] = DFFEAS(TE1_entry_0[53]_lut_out, GLOBAL(QC2__clk0), VCC, , TE1L84, , , , );

--KB1_active_addr[10] is std_1c20:inst|sdram:the_sdram|active_addr[10] at LC_X16_Y20_N0

--operation mode is normal

KB1_active_addr[10]_lut_out = KB1L676 & (F1_data_out & (KB1L699) # !F1_data_out & KB1_active_addr[10]) # !KB1L676 & KB1_active_addr[10];

KB1_active_addr[10] = DFFEAS(KB1_active_addr[10]_lut_out, GLOBAL(QC2__clk0), VCC, , , , , , );

--TE1_entry_0[46] is std_1c20:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_0[46] at LC_X17_Y20_N0

--operation mode is normal

TE1_entry_0[46]_lut_out = NB1L20 & (S1_M_alu_result[12]) # !NB1L20 & S1L1568Q;

TE1_entry_0[46] = DFFEAS(TE1_entry_0[46]_lut_out, GLOBAL(QC2__clk0), VCC, , TE1L84, , , , );

--TE1_entry_0[58] is std_1c20:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_0[58] at LC_X17_Y21_N9

--operation mode is normal

TE1_entry_0[58]_lut_out = !NB1_sdram_s1_in_a_write_cycle;

TE1_entry_0[58] = DFFEAS(TE1_entry_0[58]_lut_out, GLOBAL(QC2__clk0), VCC, , TE1L84, , , , );

--TE1_entry_1[58] is std_1c20:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_1[58] at LC_X16_Y21_N9

--operation mode is normal

TE1_entry_1[58]_lut_out = !NB1_sdram_s1_in_a_write_cycle;

TE1_entry_1[58] = DFFEAS(TE1_entry_1[58]_lut_out, GLOBAL(QC2__clk0), VCC, , TE1L148, , , , );

--KB1_active_rnw is std_1c20:inst|sdram:the_sdram|active_rnw at LC_X16_Y21_N1

--operation mode is normal

KB1_active_rnw_lut_out = KB1L14 & (KB1L12 & (TE1L200) # !KB1L12 & KB1_active_rnw) # !KB1L14 & KB1_active_rnw;

KB1_active_rnw = DFFEAS(KB1_active_rnw_lut_out, GLOBAL(QC2__clk0), VCC, , , , , , );

--KB1L1012 is std_1c20:inst|sdram:the_sdram|rnw_match~0 at LC_X16_Y21_N8

--operation mode is normal

KB1L1012 = KB1_active_rnw $ (TE1_rd_address & TE1_entry_1[58] # !TE1_rd_address & (TE1_entry_0[58]));

--KB1_active_addr[20] is std_1c20:inst|sdram:the_sdram|active_addr[20] at LC_X16_Y20_N5

--operation mode is normal

KB1_active_addr[20]_lut_out = KB1L676 & (F1_data_out & (KB1L679) # !F1_data_out & KB1_active_addr[20]) # !KB1L676 & KB1_active_addr[20];

KB1_active_addr[20] = DFFEAS(KB1_active_addr[20]_lut_out, GLOBAL(QC2__clk0), VCC, , , , , , );

--TE1_entry_0[56] is std_1c20:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_0[56] at LC_X17_Y20_N2

--operation mode is normal

TE1_entry_0[56]_lut_out = NB1L20 & S1L1816Q # !NB1L20 & (S1_ic_fill_tag[10]);

TE1_entry_0[56] = DFFEAS(TE1_entry_0[56]_lut_out, GLOBAL(QC2__clk0), VCC, , TE1L84, , , , );

--KB1L989 is std_1c20:inst|sdram:the_sdram|pending~247 at LC_X17_Y20_N4

--operation mode is normal

KB1L989 = TE1L85 # TE1L75 # KB1L1012 # TE1L56;

--KB1_active_addr[18] is std_1c20:inst|sdram:the_sdram|active_addr[18] at LC_X13_Y20_N3

--operation mode is normal

KB1_active_addr[18]_lut_out = F1_data_out & (KB1L676 & KB1L683 # !KB1L676 & (KB1_active_addr[18])) # !F1_data_out & (KB1_active_addr[18]);

KB1_active_addr[18] = DFFEAS(KB1_active_addr[18]_lut_out, GLOBAL(QC2__clk0), VCC, , , , , , );

--TE1_entry_0[54] is std_1c20:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_0[54] at LC_X18_Y20_N4

--operation mode is normal

TE1_entry_0[54]_lut_out = NB1L20 & (S1L1782Q) # !NB1L20 & S1L1609Q;

TE1_entry_0[54] = DFFEAS(TE1_entry_0[54]_lut_out, GLOBAL(QC2__clk0), VCC, , TE1L84, , , , );

--KB1_active_addr[12] is std_1c20:inst|sdram:the_sdram|active_addr[12] at LC_X13_Y20_N9

--operation mode is normal

KB1_active_addr[12]_lut_out = F1_data_out & (KB1L676 & (KB1L695) # !KB1L676 & KB1_active_addr[12]) # !F1_data_out & KB1_active_addr[12];

KB1_active_addr[12] = DFFEAS(KB1_active_addr[12]_lut_out, GLOBAL(QC2__clk0), VCC, , , , , , );

--KB1L125 is std_1c20:inst|sdram:the_sdram|Equal4~481 at LC_X17_Y22_N7

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

TE1_entry_0[48]_qfbk = TE1_entry_0[48];

KB1L125 = KB1_active_addr[12] $ (TE1_rd_address & (TE1_entry_1[48]) # !TE1_rd_address & TE1_entry_0[48]_qfbk);

--TE1_entry_0[48] is std_1c20:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_0[48] at LC_X17_Y22_N7

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

TE1_entry_0[48] = DFFEAS(KB1L125, GLOBAL(QC2__clk0), VCC, , TE1L84, NB1L51, , , VCC);

--KB1_active_cs_n is std_1c20:inst|sdram:the_sdram|active_cs_n at LC_X15_Y22_N8

--operation mode is normal

KB1_active_cs_n_lut_out = KB1L32 & (KB1_refresh_request # !TE1L152 & KB1_active_cs_n) # !KB1L32 & (KB1_active_cs_n);

KB1_active_cs_n = DFFEAS(KB1_active_cs_n_lut_out, GLOBAL(QC2__clk0), VCC, , , , , , );

--KB1_active_addr[19] is std_1c20:inst|sdram:the_sdram|active_addr[19] at LC_X21_Y22_N6

--operation mode is normal

KB1_active_addr[19]_lut_out = F1_data_out & (KB1L676 & (KB1L681) # !KB1L676 & KB1_active_addr[19]) # !F1_data_out & (KB1_active_addr[19]);

KB1_active_addr[19] = DFFEAS(KB1_active_addr[19]_lut_out, GLOBAL(QC2__clk0), VCC, , , , , , );

--TE1_entry_0[55] is std_1c20:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_0[55] at LC_X22_Y22_N4

--operation mode is normal

TE1_entry_0[55]_lut_out = NB1L20 & S1L1800Q # !NB1L20 & (S1_ic_fill_tag[9]);

TE1_entry_0[55] = DFFEAS(TE1_entry_0[55]_lut_out, GLOBAL(QC2__clk0), VCC, , TE1L84, , , , );

--KB1L990 is std_1c20:inst|sdram:the_sdram|pending~248 at LC_X17_Y22_N1

--operation mode is normal

KB1L990 = TE1L78 # TE1L81 # KB1L125 # KB1_active_cs_n;

--KB1L991 is std_1c20:inst|sdram:the_sdram|pending~249 at LC_X17_Y22_N4

--operation mode is normal

KB1L991 = KB1L990 # KB1L989 # KB1L987 # KB1L988;

--TE1_entries[0] is std_1c20:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entries[0] at LC_X21_Y22_N3

--operation mode is normal

TE1_entries[0]_lut_out = KB1_f_select $ (TE1_entries[0] & (!KB1L477) # !TE1_entries[0] & !TE1_entries[1] & KB1L477);

TE1_entries[0] = DFFEAS(TE1_entries[0]_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--TE1_entries[1] is std_1c20:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entries[1] at LC_X21_Y22_N7

--operation mode is normal

TE1_entries[1]_lut_out = TE1_entries[0] & (TE1_entries[1] $ (KB1L477 & !KB1_f_select)) # !TE1_entries[0] & (TE1_entries[1] & (!KB1_f_select) # !TE1_entries[1] & !KB1L477 & KB1_f_select);

TE1_entries[1] = DFFEAS(TE1_entries[1]_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--TE1L152 is std_1c20:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|Equal1~96 at LC_X17_Y23_N9

--operation mode is normal

TE1L152 = TE1_entries[1] # TE1_entries[0];

--KB1L504 is std_1c20:inst|sdram:the_sdram|Mux19~1738 at LC_X13_Y21_N4

--operation mode is normal

KB1L504 = KB1_m_state[3] $ KB1_m_state[4];

--KB1_init_done is std_1c20:inst|sdram:the_sdram|init_done at LC_X11_Y22_N7

--operation mode is normal

KB1_init_done_lut_out = KB1_init_done # !KB1_i_state[1] & KB1_i_state[2] & KB1_i_state[0];

KB1_init_done = DFFEAS(KB1_init_done_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--KB1_i_cmd[1] is std_1c20:inst|sdram:the_sdram|i_cmd[1] at LC_X11_Y22_N4

--operation mode is normal

KB1_i_cmd[1]_lut_out = KB1_i_state[2] # KB1_i_state[1] & !KB1_i_state[0];

KB1_i_cmd[1] = DFFEAS(KB1_i_cmd[1]_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , KB1L138, , , , );

--KB1L505 is std_1c20:inst|sdram:the_sdram|Mux19~1739 at LC_X13_Y21_N7

--operation mode is normal

KB1L505 = KB1L503 & (KB1L504 & !KB1L246) # !KB1L503 & KB1L506;

--KB1_i_cmd[3] is std_1c20:inst|sdram:the_sdram|i_cmd[3] at LC_X11_Y22_N3

--operation mode is normal

KB1_i_cmd[3]_lut_out = KB1_i_state[2] # KB1_i_state[1] # KB1_i_state[0];

KB1_i_cmd[3] = DFFEAS(KB1_i_cmd[3]_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , KB1L138, , , , );

--KB1_refresh_request is std_1c20:inst|sdram:the_sdram|refresh_request at LC_X12_Y25_N1

--operation mode is normal

KB1_refresh_request_lut_out = KB1_init_done & !KB1_ack_refresh_request & (KB1_refresh_request # KB1L112);

KB1_refresh_request = DFFEAS(KB1_refresh_request_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--KB1L485 is std_1c20:inst|sdram:the_sdram|Mux17~1836 at LC_X12_Y25_N8

--operation mode is normal

KB1L485 = KB1_init_done & !KB1_refresh_request # !KB1_init_done & (!KB1_i_cmd[3]);

--KB1L486 is std_1c20:inst|sdram:the_sdram|Mux17~1837 at LC_X12_Y22_N4

--operation mode is normal

KB1L486 = !KB1_m_state[8] & !KB1_m_state[1] & !KB1_m_state[3] & !KB1_m_state[5];

--KB1L487 is std_1c20:inst|sdram:the_sdram|Mux17~1838 at LC_X12_Y25_N9

--operation mode is normal

KB1L487 = KB1_m_state[4] & (!KB1L486 # !KB1_m_state[0]) # !KB1_m_state[4] & !KB1_m_state[0] & (KB1L485 # !KB1L486);

--KB1L488 is std_1c20:inst|sdram:the_sdram|Mux17~1839 at LC_X13_Y24_N6

--operation mode is normal

KB1L488 = KB1_m_state[1] & !KB1_m_state[5] & !KB1_m_state[8] & !KB1_m_state[3] # !KB1_m_state[1] & (KB1_m_state[5] & !KB1_m_state[8] & !KB1_m_state[3] # !KB1_m_state[5] & (KB1_m_state[8] $ KB1_m_state[3]));

--KB1L489 is std_1c20:inst|sdram:the_sdram|Mux17~1840 at LC_X13_Y25_N7

--operation mode is normal

KB1L489 = KB1_m_state[0] & (KB1_active_cs_n # !KB1_m_state[4] & !KB1L488);

--KB1L490 is std_1c20:inst|sdram:the_sdram|Mux17~1841 at LC_X13_Y25_N0

--operation mode is normal

KB1L490 = !KB1_m_state[6] & !KB1_m_state[2] & (KB1L487 # KB1L489);

--KB1L491 is std_1c20:inst|sdram:the_sdram|Mux17~1842 at LC_X13_Y25_N4

--operation mode is normal

KB1L491 = !KB1_m_state[2] & KB1_m_state[0] & (KB1_refresh_request # !KB1_active_cs_n);

--KB1L492 is std_1c20:inst|sdram:the_sdram|Mux17~1843 at LC_X13_Y25_N5

--operation mode is normal

KB1L492 = KB1_m_state[6] & (KB1_m_state[4] # !KB1L486 # !KB1L491);

--KB1_m_next[7] is std_1c20:inst|sdram:the_sdram|m_next[7] at LC_X14_Y24_N3

--operation mode is normal

KB1_m_next[7]_lut_out = KB1_m_state[8] & KB1_m_next[7] & (KB1L561 # !KB1L607) # !KB1_m_state[8] & (KB1L561);

KB1_m_next[7] = DFFEAS(KB1_m_next[7]_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , KB1L608, , , , );

--KB1_m_next[0] is std_1c20:inst|sdram:the_sdram|m_next[0] at LC_X14_Y24_N5

--operation mode is normal

KB1_m_next[0]_lut_out = KB1_m_state[8] & KB1_m_next[0] & (KB1L613 # !KB1L607) # !KB1_m_state[8] & (!KB1L613);

KB1_m_next[0] = DFFEAS(KB1_m_next[0]_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , KB1L608, , , , );

--KB1_m_next[1] is std_1c20:inst|sdram:the_sdram|m_next[1] at LC_X14_Y23_N1

--operation mode is normal

KB1_m_next[1]_lut_out = KB1_m_state[8] & KB1_m_next[1] & (KB1L596 # !KB1L607) # !KB1_m_state[8] & (KB1L596);

KB1_m_next[1] = DFFEAS(KB1_m_next[1]_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , KB1L608, , , , );

--KB1_m_next[3] is std_1c20:inst|sdram:the_sdram|m_next[3] at LC_X16_Y24_N8

--operation mode is normal

KB1_m_next[3]_lut_out = !KB1L449 & (KB1L444 # KB1_m_next[3] & !KB1L442);

KB1_m_next[3] = DFFEAS(KB1_m_next[3]_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , KB1L608, , , , );

--KB1_m_next[4] is std_1c20:inst|sdram:the_sdram|m_next[4] at LC_X16_Y23_N8

--operation mode is normal

KB1_m_next[4]_lut_out = !KB1L449 & (KB1L459 # KB1_m_next[4] & !KB1L457);

KB1_m_next[4] = DFFEAS(KB1_m_next[4]_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , KB1L608, , , , );

--KB1L127 is std_1c20:inst|sdram:the_sdram|Equal5~52 at LC_X14_Y24_N0

--operation mode is normal

KB1L127 = !KB1_m_next[3] & !KB1_m_next[1] & !KB1_m_next[4] & KB1_m_next[0];

--KB1L493 is std_1c20:inst|sdram:the_sdram|Mux17~1844 at LC_X14_Y25_N5

--operation mode is normal

KB1L493 = !KB1_m_state[4] & KB1_m_state[0] & KB1L486;

--KB1L494 is std_1c20:inst|sdram:the_sdram|Mux17~1845 at LC_X14_Y25_N0

--operation mode is normal

KB1L494 = KB1_active_cs_n & (!KB1L127 # !KB1_m_next[7]) # !KB1L493;

--KB1L495 is std_1c20:inst|sdram:the_sdram|Mux17~1846 at LC_X13_Y25_N1

--operation mode is normal

KB1L495 = KB1L492 # KB1L490 # KB1_m_state[2] & KB1L494;

--KB1L496 is std_1c20:inst|sdram:the_sdram|Mux17~1847 at LC_X13_Y25_N6

--operation mode is normal

KB1L496 = KB1_m_state[0] & !KB1_m_state[2];

--KB1L497 is std_1c20:inst|sdram:the_sdram|Mux17~1848 at LC_X13_Y25_N9

--operation mode is normal

KB1L497 = !KB1_m_state[6] & !KB1_m_state[4] & (KB1L486);

--KB1_i_cmd[2] is std_1c20:inst|sdram:the_sdram|i_cmd[2] at LC_X11_Y22_N5

--operation mode is normal

KB1_i_cmd[2]_lut_out = KB1_i_state[2] # KB1_i_state[1] $ KB1_i_state[0];

KB1_i_cmd[2] = DFFEAS(KB1_i_cmd[2]_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , KB1L138, , , , );

--KB1L524 is std_1c20:inst|sdram:the_sdram|Mux25~1259 at LC_X12_Y22_N8

--operation mode is normal

KB1L524 = !KB1_m_state[7] & !KB1_m_state[1] & (!KB1_m_state[6]);

--KB1L498 is std_1c20:inst|sdram:the_sdram|Mux18~1364 at LC_X11_Y22_N9

--operation mode is normal

KB1L498 = !KB1_m_state[0] & (KB1_init_done # !KB1L524 # !KB1_i_cmd[2]);

--KB1L539 is std_1c20:inst|sdram:the_sdram|Mux28~1625 at LC_X12_Y21_N1

--operation mode is normal

KB1L539 = !KB1_m_state[1] & !KB1_m_state[7];

--KB1L499 is std_1c20:inst|sdram:the_sdram|Mux18~1365 at LC_X12_Y21_N3

--operation mode is normal

KB1L499 = KB1_m_state[6] & !KB1L539 # !KB1L857 # !KB1L705;

--KB1L500 is std_1c20:inst|sdram:the_sdram|Mux18~1366 at LC_X13_Y24_N3

--operation mode is normal

KB1L500 = KB1_m_state[0] & !KB1_m_state[6];

--KB1L501 is std_1c20:inst|sdram:the_sdram|Mux18~1367 at LC_X13_Y24_N0

--operation mode is normal

KB1L501 = KB1_m_state[7] $ (KB1_m_state[1]);

--KB1L507 is std_1c20:inst|sdram:the_sdram|Mux20~1315 at LC_X12_Y25_N6

--operation mode is normal

KB1L507 = !KB1_m_state[2] & (!KB1_m_state[7] & KB1L486);

--KB1L508 is std_1c20:inst|sdram:the_sdram|Mux20~1316 at LC_X12_Y25_N4

--operation mode is normal

KB1L508 = KB1_m_state[4] # !KB1_m_state[0] & KB1_init_done;

--KB1_i_cmd[0] is std_1c20:inst|sdram:the_sdram|i_cmd[0] at LC_X11_Y22_N6

--operation mode is normal

KB1_i_cmd[0]_lut_out = KB1_i_state[2] # !KB1_i_state[1] & KB1_i_state[0];

KB1_i_cmd[0] = DFFEAS(KB1_i_cmd[0]_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , KB1L138, , , , );

--KB1L509 is std_1c20:inst|sdram:the_sdram|Mux20~1317 at LC_X12_Y25_N5

--operation mode is normal

KB1L509 = KB1_m_state[0] & (KB1L508 $ KB1_m_state[6]) # !KB1_m_state[0] & KB1_i_cmd[0] & !KB1L508 & !KB1_m_state[6];

--XE1_control_reg[9] is std_1c20:inst|uart1:the_uart1|uart1_regs:the_uart1_regs|control_reg[9] at LC_X48_Y23_N9

--operation mode is normal

XE1_control_reg[9]_lut_out = S1L2281Q;

XE1_control_reg[9] = DFFEAS(XE1_control_reg[9]_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , XE1L14, , , , );

--ZE1_pre_txd is std_1c20:inst|uart1:the_uart1|uart1_tx:the_uart1_tx|pre_txd at LC_X48_Y25_N3

--operation mode is normal

ZE1_pre_txd_lut_out = !ZE1_unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out[0] & (ZE1_pre_txd # !ZE1L37);

ZE1_pre_txd = DFFEAS(ZE1_pre_txd_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--S1_E_control_rd_data_without_mmu_regs[2] is std_1c20:inst|cpu:the_cpu|E_control_rd_data_without_mmu_regs[2] at LC_X36_Y19_N9

--operation mode is normal

S1_E_control_rd_data_without_mmu_regs[2] = AMPP_FUNCTION(QC2__clk0, S1L2101Q, S1_D_iw[8], S1_M_ipending_reg[2], S1L273, F1_data_out, S1_W_stall);

--S1_E_logic_op[1] is std_1c20:inst|cpu:the_cpu|E_logic_op[1] at LC_X32_Y14_N6

--operation mode is normal

S1_E_logic_op[1] = AMPP_FUNCTION(QC2__clk0, S1_D_iw[5], S1L1168, S1_D_iw[4], S1_D_iw[15], F1_data_out, S1_W_stall);

--S1_E_src1_prelim[2] is std_1c20:inst|cpu:the_cpu|E_src1_prelim[2] at LC_X43_Y16_N7

--operation mode is normal

S1_E_src1_prelim[2] = AMPP_FUNCTION(QC2__clk0, CD1_q_b[2], S1_W_wr_data[2], S1L2398, S1_D_src1_hazard_W, F1_data_out, S1_D_src1_hazard_M, S1_W_stall);

--S1L887 is std_1c20:inst|cpu:the_cpu|E_src1_hazard_M~11 at LC_X34_Y15_N7

--operation mode is normal

S1L887 = AMPP_FUNCTION(S1L275, S1L649, S1L648, S1L1163);

--S1_M_shift_rot_result[2] is std_1c20:inst|cpu:the_cpu|M_shift_rot_result[2] at LC_X40_Y18_N0

--operation mode is normal

S1_M_shift_rot_result[2] = AMPP_FUNCTION(QC2__clk0, S1_M_shift_rot_result[3], S1_M_shift_rot_result[1], S1L853, S1_M_ctrl_shift_rot_right, F1_data_out, !S1_M_shift_rot_stall);

--S1L2396 is std_1c20:inst|cpu:the_cpu|M_wr_data_unfiltered[2]~3645 at LC_X39_Y15_N8

--operation mode is normal

S1L2396 = AMPP_FUNCTION(S1L2056Q, S1_M_shift_rot_result[2]);

--S1_av_ld_data_aligned_or_div[2] is std_1c20:inst|cpu:the_cpu|av_ld_data_aligned_or_div[2] at LC_X39_Y19_N0

--operation mode is normal

S1_av_ld_data_aligned_or_div[2] = AMPP_FUNCTION(QC2__clk0, S1L577, T1_cpu_data_master_readdata[2], S1L162, S1_M_ld_align_sh16, F1_data_out, S1_M_ld_align_sh8);

--S1L2397 is std_1c20:inst|cpu:the_cpu|M_wr_data_unfiltered[2]~3646 at LC_X39_Y15_N5

--operation mode is normal

S1L2397 = AMPP_FUNCTION(S1_av_ld_or_div_done, S1L1726Q, S1L2056Q, S1_av_ld_data_aligned_or_div[2]);

--S1L853 is std_1c20:inst|cpu:the_cpu|E_src1[2]~2015 at LC_X39_Y15_N9

--operation mode is normal

S1L853 = AMPP_FUNCTION(S1_E_src1_prelim[2], S1L2397, S1L886Q, S1L2396);

--S1_E_src2_imm[2] is std_1c20:inst|cpu:the_cpu|E_src2_imm[2] at LC_X39_Y15_N0

--operation mode is normal

S1_E_src2_imm[2] = AMPP_FUNCTION(QC2__clk0, S1_D_iw[5], S1L300, S1_D_iw[8], S1_D_iw[2], F1_data_out, S1_W_stall);

--S1L2292 is std_1c20:inst|cpu:the_cpu|M_st_data[10]~COMBOUT at LC_X37_Y15_N2

--operation mode is normal

S1L2292 = AMPP_FUNCTION(S1L1152, S1L2290, S1L1185);

--S1_E_ctrl_src2_is_imm is std_1c20:inst|cpu:the_cpu|E_ctrl_src2_is_imm at LC_X40_Y16_N9

--operation mode is normal

S1_E_ctrl_src2_is_imm = AMPP_FUNCTION(QC2__clk0, S1_D_iw[11], S1L308, S1L307, F1_data_out, S1_W_stall);

--S1L932 is std_1c20:inst|cpu:the_cpu|E_src2[2]~1503 at LC_X39_Y15_N3

--operation mode is normal

S1L932 = AMPP_FUNCTION(S1L936, S1L934, S1L2522);

--S1_E_logic_op[0] is std_1c20:inst|cpu:the_cpu|E_logic_op[0] at LC_X31_Y14_N0

--operation mode is normal

S1_E_logic_op[0] = AMPP_FUNCTION(QC2__clk0, S1_D_iw[14], S1L1168, S1_D_iw[3], S1L1171, F1_data_out, S1_W_stall);

--S1L1 is std_1c20:inst|cpu:the_cpu|A_WE_StdLogicVector~14080 at LC_X35_Y16_N1

--operation mode is normal

S1L1 = AMPP_FUNCTION(S1L853, S1_E_logic_op[0], S1_E_logic_op[1], S1L932);

--S1_E_extra_pc[0] is std_1c20:inst|cpu:the_cpu|E_extra_pc[0] at LC_X31_Y18_N4

--operation mode is normal

S1_E_extra_pc[0] = AMPP_FUNCTION(QC2__clk0, S1_D_br_taken_waddr_partial[0], S1_D_iw[21], S1_D_pc_plus_one[0], S1L287, F1_data_out, S1_W_stall);

--YC1_result[2] is std_1c20:inst|cpu:the_cpu|lpm_add_sub:Add8|alt_stratix_add_sub:stratix_adder|result[2] at LC_X36_Y16_N2

--operation mode is arithmetic

YC1_result[2] = AMPP_FUNCTION(S1L932, S1L853, YC1L6, YC1L7, S1_E_ctrl_alu_subtract);

--YC1L9 is std_1c20:inst|cpu:the_cpu|lpm_add_sub:Add8|alt_stratix_add_sub:stratix_adder|add_sub_cell[2]~COUT at LC_X36_Y16_N2

--operation mode is arithmetic

YC1L9 = AMPP_FUNCTION(S1L932, S1L853, YC1L6, S1_E_ctrl_alu_subtract);

--YC1L10 is std_1c20:inst|cpu:the_cpu|lpm_add_sub:Add8|alt_stratix_add_sub:stratix_adder|add_sub_cell[2]~COUTCOUT1_1299 at LC_X36_Y16_N2

--operation mode is arithmetic

YC1L10 = AMPP_FUNCTION(S1L932, S1L853, YC1L7, S1_E_ctrl_alu_subtract);

--S1_E_ctrl_dst_data_sel_pc_plus_one is std_1c20:inst|cpu:the_cpu|E_ctrl_dst_data_sel_pc_plus_one at LC_X31_Y14_N1

--operation mode is normal

S1_E_ctrl_dst_data_sel_pc_plus_one = AMPP_FUNCTION(QC2__clk0, S1L275, S1L1181, S1L1173, S1L291, F1_data_out, S1_W_stall);

--S1L2 is std_1c20:inst|cpu:the_cpu|A_WE_StdLogicVector~14081 at LC_X33_Y19_N2

--operation mode is normal

S1L2 = AMPP_FUNCTION(S1_E_extra_pc[0], S1_E_ctrl_dst_data_sel_pc_plus_one, YC1_result[2]);

--S1_E_ctrl_dst_data_sel_logic_result is std_1c20:inst|cpu:the_cpu|E_ctrl_dst_data_sel_logic_result at LC_X31_Y14_N4

--operation mode is normal

S1_E_ctrl_dst_data_sel_logic_result = AMPP_FUNCTION(QC2__clk0, S1_D_iw[16], S1_D_iw[11], S1L290, S1L1180, F1_data_out, S1_W_stall);

--S1L3 is std_1c20:inst|cpu:the_cpu|A_WE_StdLogicVector~14082 at LC_X33_Y19_N9

--operation mode is normal

S1L3 = AMPP_FUNCTION(S1_E_ctrl_dst_data_sel_logic_result, S1L2, S1L1);

--S1_E_ctrl_rdctl_inst is std_1c20:inst|cpu:the_cpu|E_ctrl_rdctl_inst at LC_X32_Y14_N9

--operation mode is normal

S1_E_ctrl_rdctl_inst = AMPP_FUNCTION(QC2__clk0, S1_D_iw[11], S1_D_iw[15], S1L1182, S1L1180, F1_data_out, S1_W_stall);

--S1_E_ctrl_dst_data_sel_cmp is std_1c20:inst|cpu:the_cpu|E_ctrl_dst_data_sel_cmp at LC_X30_Y13_N2

--operation mode is normal

S1_E_ctrl_dst_data_sel_cmp = AMPP_FUNCTION(QC2__clk0, S1_D_iw[11], S1L279, S1L1171, S1L289, F1_data_out, S1_W_stall);

--S1_M_alu_result[2] is std_1c20:inst|cpu:the_cpu|M_alu_result[2] at LC_X33_Y19_N0

--operation mode is normal

S1_M_alu_result[2] = AMPP_FUNCTION(QC2__clk0, S1L1722, S1L1724, S1L2, S1L1, F1_data_out, S1_W_stall);

--S1_M_shift_rot_stall is std_1c20:inst|cpu:the_cpu|M_shift_rot_stall at LC_X38_Y13_N2

--operation mode is normal

S1_M_shift_rot_stall = AMPP_FUNCTION(QC2__clk0, S1L1195, S1L132, S1L2256, S1L1192, F1_data_out);

--S1L2514 is std_1c20:inst|cpu:the_cpu|W_stall~21 at LC_X34_Y18_N8

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

S1L2514 = AMPP_FUNCTION(S1L235Q, S1_M_valid_from_E, S1_M_shift_rot_stall);

--S1_M_ctrl_ld is std_1c20:inst|cpu:the_cpu|M_ctrl_ld at LC_X34_Y18_N8

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

S1_M_ctrl_ld = AMPP_FUNCTION(QC2__clk0, S1_E_ctrl_ld, F1_data_out, GND, S1_W_stall);

--RB1L7 is std_1c20:inst|sys_clk_timer:the_sys_clk_timer|control_wr_strobe~42 at LC_X34_Y18_N5

--operation mode is normal

RB1L7 = S1_internal_d_write & !T1_internal_cpu_data_master_waitrequest;

--S1_E_control_rd_data_without_mmu_regs[3] is std_1c20:inst|cpu:the_cpu|E_control_rd_data_without_mmu_regs[3] at LC_X36_Y19_N6

--operation mode is normal

S1_E_control_rd_data_without_mmu_regs[3] = AMPP_FUNCTION(QC2__clk0, S1_M_ipending_reg[3], S1_D_iw[8], S1L2104Q, S1L273, F1_data_out, S1_W_stall);

--S1_E_src1_prelim[3] is std_1c20:inst|cpu:the_cpu|E_src1_prelim[3] at LC_X42_Y16_N4

--operation mode is normal

S1_E_src1_prelim[3] = AMPP_FUNCTION(QC2__clk0, S1_W_wr_data[3], S1_D_src1_hazard_W, S1L2401, CD1_q_b[3], F1_data_out, S1_D_src1_hazard_M, S1_W_stall);

--S1_M_shift_rot_result[3] is std_1c20:inst|cpu:the_cpu|M_shift_rot_result[3] at LC_X40_Y18_N7

--operation mode is normal

S1_M_shift_rot_result[3] = AMPP_FUNCTION(QC2__clk0, S1_M_shift_rot_result[4], S1_M_shift_rot_result[2], S1L854, S1_M_ctrl_shift_rot_right, F1_data_out, !S1_M_shift_rot_stall);

--S1L2399 is std_1c20:inst|cpu:the_cpu|M_wr_data_unfiltered[3]~3647 at LC_X39_Y16_N3

--operation mode is normal

S1L2399 = AMPP_FUNCTION(S1L2056Q, S1_M_shift_rot_result[3]);

--S1_av_ld_data_aligned_or_div[3] is std_1c20:inst|cpu:the_cpu|av_ld_data_aligned_or_div[3] at LC_X40_Y20_N4

--operation mode is normal

S1_av_ld_data_aligned_or_div[3] = AMPP_FUNCTION(QC2__clk0, S1L582, T1_cpu_data_master_readdata[3], S1L164, S1_M_ld_align_sh16, F1_data_out, S1_M_ld_align_sh8);

--S1L2400 is std_1c20:inst|cpu:the_cpu|M_wr_data_unfiltered[3]~3648 at LC_X39_Y16_N9

--operation mode is normal

S1L2400 = AMPP_FUNCTION(S1_av_ld_or_div_done, S1L2056Q, S1_av_ld_data_aligned_or_div[3], S1_M_alu_result[3]);

--S1L854 is std_1c20:inst|cpu:the_cpu|E_src1[3]~2016 at LC_X39_Y16_N4

--operation mode is normal

S1L854 = AMPP_FUNCTION(S1L886Q, S1_E_src1_prelim[3], S1L2400, S1L2399);

--S1_E_src2_imm[3] is std_1c20:inst|cpu:the_cpu|E_src2_imm[3] at LC_X39_Y16_N7

--operation mode is normal

S1_E_src2_imm[3] = AMPP_FUNCTION(QC2__clk0, S1_D_iw[2], S1_D_iw[5], S1L300, S1_D_iw[9], F1_data_out, S1_W_stall);

--S1L2299 is std_1c20:inst|cpu:the_cpu|M_st_data[11]~COMBOUT at LC_X42_Y15_N6

--operation mode is normal

S1L2299 = AMPP_FUNCTION(S1L1185, S1L2296, S1L1153);

--S1L937 is std_1c20:inst|cpu:the_cpu|E_src2[3]~1504 at LC_X39_Y16_N8

--operation mode is normal

S1L937 = AMPP_FUNCTION(S1L939, S1L941, S1L2525);

--S1L4 is std_1c20:inst|cpu:the_cpu|A_WE_StdLogicVector~14083 at LC_X35_Y16_N2

--operation mode is normal

S1L4 = AMPP_FUNCTION(S1L937, S1L854, S1_E_logic_op[1], S1_E_logic_op[0]);

--S1_E_extra_pc[1] is std_1c20:inst|cpu:the_cpu|E_extra_pc[1] at LC_X30_Y18_N2

--operation mode is normal

S1_E_extra_pc[1] = AMPP_FUNCTION(QC2__clk0, S1_D_iw[21], S1_D_br_taken_waddr_partial[1], S1L287, S1_D_pc_plus_one[1], F1_data_out, S1_W_stall);

--YC1_result[3] is std_1c20:inst|cpu:the_cpu|lpm_add_sub:Add8|alt_stratix_add_sub:stratix_adder|result[3] at LC_X36_Y16_N3

--operation mode is arithmetic

YC1_result[3] = AMPP_FUNCTION(S1L937, S1L854, YC1L9, YC1L10, S1_E_ctrl_alu_subtract);

--YC1L12 is std_1c20:inst|cpu:the_cpu|lpm_add_sub:Add8|alt_stratix_add_sub:stratix_adder|add_sub_cell[3]~COUT at LC_X36_Y16_N3

--operation mode is arithmetic

YC1L12 = AMPP_FUNCTION(S1L937, S1L854, YC1L9, S1_E_ctrl_alu_subtract);

--YC1L13 is std_1c20:inst|cpu:the_cpu|lpm_add_sub:Add8|alt_stratix_add_sub:stratix_adder|add_sub_cell[3]~COUTCOUT1_1301 at LC_X36_Y16_N3

--operation mode is arithmetic

YC1L13 = AMPP_FUNCTION(S1L937, S1L854, YC1L10, S1_E_ctrl_alu_subtract);

--S1L5 is std_1c20:inst|cpu:the_cpu|A_WE_StdLogicVector~14084 at LC_X36_Y18_N2

--operation mode is normal

S1L5 = AMPP_FUNCTION(S1_E_extra_pc[1], YC1_result[3], S1_E_ctrl_dst_data_sel_pc_plus_one);

--S1L6 is std_1c20:inst|cpu:the_cpu|A_WE_StdLogicVector~14085 at LC_X36_Y19_N2

--operation mode is normal

S1L6 = AMPP_FUNCTION(S1_E_ctrl_dst_data_sel_logic_result, S1L4, S1L5);

--S1_M_alu_result[3] is std_1c20:inst|cpu:the_cpu|M_alu_result[3] at LC_X36_Y19_N7

--operation mode is normal

S1_M_alu_result[3] = AMPP_FUNCTION(QC2__clk0, S1L1729, S1L4, S1L1731, S1L5, F1_data_out, S1_W_stall);

--S1L435 is std_1c20:inst|cpu:the_cpu|d_read_nxt~0 at LC_X33_Y18_N3

--operation mode is normal

S1L435 = AMPP_FUNCTION(S1_internal_d_read, T1_internal_cpu_data_master_waitrequest);

--S1_E_valid_from_D is std_1c20:inst|cpu:the_cpu|E_valid_from_D at LC_X30_Y14_N2

--operation mode is normal

S1_E_valid_from_D = AMPP_FUNCTION(QC2__clk0, S1_M_pipe_flush, S1L343, F1_data_out, S1_W_stall);

--S1_M_pipe_flush is std_1c20:inst|cpu:the_cpu|M_pipe_flush at LC_X30_Y18_N8

--operation mode is normal

S1_M_pipe_flush = AMPP_FUNCTION(QC2__clk0, S1_E_iw[21], S1L2212, S1L697, S1L2214, F1_data_out, S1_W_stall);

--S1L1159 is std_1c20:inst|cpu:the_cpu|E_valid~34 at LC_X30_Y18_N0

--operation mode is normal

S1L1159 = AMPP_FUNCTION(S1_M_pipe_flush, S1_E_valid_from_D);

--S1_E_iw[5] is std_1c20:inst|cpu:the_cpu|E_iw[5] at LC_X32_Y18_N4

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

S1_E_iw[5] = AMPP_FUNCTION(QC2__clk0, S1_D_iw[5], F1_data_out, GND, S1_W_stall);

--S1L822 is std_1c20:inst|cpu:the_cpu|E_op_eret~72 at LC_X31_Y15_N0

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

S1L822 = AMPP_FUNCTION(S1_E_iw[3], S1_E_iw[12], S1_E_iw[5]);

--S1_E_iw[4] is std_1c20:inst|cpu:the_cpu|E_iw[4] at LC_X31_Y15_N0

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

S1_E_iw[4] = AMPP_FUNCTION(QC2__clk0, S1_D_iw[4], F1_data_out, GND, S1_W_stall);

--S1_E_iw[2] is std_1c20:inst|cpu:the_cpu|E_iw[2] at LC_X27_Y15_N6

--operation mode is normal

S1_E_iw[2] = AMPP_FUNCTION(QC2__clk0, S1_D_iw[2], F1_data_out, S1_W_stall);

--S1_E_iw[0] is std_1c20:inst|cpu:the_cpu|E_iw[0] at LC_X27_Y15_N5

--operation mode is normal

S1_E_iw[0] = AMPP_FUNCTION(QC2__clk0, S1_D_iw[0], F1_data_out, S1_W_stall);

--S1L823 is std_1c20:inst|cpu:the_cpu|E_op_eret~73 at LC_X27_Y15_N9

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

S1L823 = AMPP_FUNCTION(S1_E_iw[2], S1_E_iw[0]);

--S1_E_iw[1] is std_1c20:inst|cpu:the_cpu|E_iw[1] at LC_X27_Y15_N9

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

S1_E_iw[1] = AMPP_FUNCTION(QC2__clk0, S1_D_iw[1], F1_data_out, GND, S1_W_stall);

--S1L760 is std_1c20:inst|cpu:the_cpu|E_hbreak_req~68 at LC_X30_Y15_N7

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

S1L760 = AMPP_FUNCTION(S1_M_pipe_flush, S1_E_iw[15], S1_E_valid_from_D);

--S1_E_iw[16] is std_1c20:inst|cpu:the_cpu|E_iw[16] at LC_X30_Y15_N7

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

S1_E_iw[16] = AMPP_FUNCTION(QC2__clk0, S1_D_iw[16], F1_data_out, GND, S1_W_stall);

--S1L761 is std_1c20:inst|cpu:the_cpu|E_hbreak_req~69 at LC_X30_Y15_N1

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

S1L761 = AMPP_FUNCTION(S1L760, S1L822, S1L823);

--S1_E_iw[11] is std_1c20:inst|cpu:the_cpu|E_iw[11] at LC_X30_Y15_N1

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

S1_E_iw[11] = AMPP_FUNCTION(QC2__clk0, S1_D_iw[11], F1_data_out, GND, S1_W_stall);

--S1L762 is std_1c20:inst|cpu:the_cpu|E_hbreak_req~70 at LC_X30_Y15_N0

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

S1L762 = AMPP_FUNCTION(S1_E_iw[14]);

--S1_E_iw[13] is std_1c20:inst|cpu:the_cpu|E_iw[13] at LC_X30_Y15_N0

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

S1_E_iw[13] = AMPP_FUNCTION(QC2__clk0, S1_D_iw[13], F1_data_out, GND, S1_W_stall);

--JD1_jtag_break is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_debug:the_cpu_nios2_oci_debug|jtag_break at LC_X44_Y18_N6

--operation mode is normal

JD1_jtag_break = AMPP_FUNCTION(QC2__clk0, JD1_jtag_break, F1_data_out, JD1L1, JD1_probepresent, !C1_CLR_SIGNAL, SD1L190);

--S1_latched_oci_tb_hbreak_req is std_1c20:inst|cpu:the_cpu|latched_oci_tb_hbreak_req at LC_X44_Y18_N2

--operation mode is normal

S1_latched_oci_tb_hbreak_req = AMPP_FUNCTION(QC2__clk0, S1_latched_oci_tb_hbreak_req, S1_hbreak_enabled, S1L1356, S1L1159, F1_data_out);

--S1_hbreak_enabled is std_1c20:inst|cpu:the_cpu|hbreak_enabled at LC_X34_Y18_N2

--operation mode is normal

S1_hbreak_enabled = AMPP_FUNCTION(QC2__clk0, S1L1355, S1L1354, S1_hbreak_enabled, S1L1351, F1_data_out);

--S1_wait_for_one_post_bret_inst is std_1c20:inst|cpu:the_cpu|wait_for_one_post_bret_inst at LC_X44_Y18_N5

--operation mode is normal

S1_wait_for_one_post_bret_inst = AMPP_FUNCTION(QC2__clk0, S1_hbreak_enabled, S1_wait_for_one_post_bret_inst, FD1_internal_oci_single_step_mode1, S1L83, F1_data_out);

--S1L1356 is std_1c20:inst|cpu:the_cpu|hbreak_req~32 at LC_X44_Y18_N4

--operation mode is normal

S1L1356 = AMPP_FUNCTION(S1_latched_oci_tb_hbreak_req, S1_wait_for_one_post_bret_inst, S1_hbreak_enabled, JD1_jtag_break);

--S1L1160 is std_1c20:inst|cpu:the_cpu|E_valid~35 at LC_X34_Y18_N4

--operation mode is normal

S1L1160 = AMPP_FUNCTION(S1L2389, S1L1356, S1L823, S1L1159);

--S1_M_valid_from_E is std_1c20:inst|cpu:the_cpu|M_valid_from_E at LC_X34_Y18_N4

--operation mode is normal

S1_M_valid_from_E = AMPP_FUNCTION(QC2__clk0, S1L2389, S1L1356, S1L823, S1L1159, F1_data_out, S1_W_stall);

--S1_E_ctrl_ld is std_1c20:inst|cpu:the_cpu|E_ctrl_ld at LC_X31_Y15_N8

--operation mode is normal

S1_E_ctrl_ld = AMPP_FUNCTION(QC2__clk0, S1_D_iw[2], S1_D_iw[1], S1_D_iw[0], S1_D_iw[4], F1_data_out, S1_W_stall);

--S1_E_extra_pc[20] is std_1c20:inst|cpu:the_cpu|E_extra_pc[20] at LC_X30_Y17_N4

--operation mode is normal

S1_E_extra_pc[20] = AMPP_FUNCTION(QC2__clk0, S1_D_iw[21], S1L287, S1_D_pc_plus_one[20], S1L84, F1_data_out, S1_W_stall);

--YC1_result[22] is std_1c20:inst|cpu:the_cpu|lpm_add_sub:Add8|alt_stratix_add_sub:stratix_adder|result[22] at LC_X36_Y14_N2

--operation mode is arithmetic

YC1_result[22] = AMPP_FUNCTION(S1L1025, S1L875, YC1L57, YC1L62, YC1L63, S1_E_ctrl_alu_subtract);

--YC1L65 is std_1c20:inst|cpu:the_cpu|lpm_add_sub:Add8|alt_stratix_add_sub:stratix_adder|add_sub_cell[22]~COUT at LC_X36_Y14_N2

--operation mode is arithmetic

YC1L65 = AMPP_FUNCTION(S1L1025, S1L875, YC1L62, S1_E_ctrl_alu_subtract);

--YC1L66 is std_1c20:inst|cpu:the_cpu|lpm_add_sub:Add8|alt_stratix_add_sub:stratix_adder|add_sub_cell[22]~COUTCOUT1_1331 at LC_X36_Y14_N2

--operation mode is arithmetic

YC1L66 = AMPP_FUNCTION(S1L1025, S1L875, YC1L63, S1_E_ctrl_alu_subtract);

--S1_E_src1_prelim[22] is std_1c20:inst|cpu:the_cpu|E_src1_prelim[22] at LC_X42_Y16_N8

--operation mode is normal

S1_E_src1_prelim[22] = AMPP_FUNCTION(QC2__clk0, S1_W_wr_data[22], S1_D_src1_hazard_W, S1L2458, CD1_q_b[22], F1_data_out, S1_D_src1_hazard_M, S1_W_stall);

--S1_M_shift_rot_result[22] is std_1c20:inst|cpu:the_cpu|M_shift_rot_result[22] at LC_X40_Y14_N0

--operation mode is normal

S1_M_shift_rot_result[22] = AMPP_FUNCTION(QC2__clk0, S1_M_shift_rot_result[23], S1_M_shift_rot_result[21], S1L875, S1_M_ctrl_shift_rot_right, F1_data_out, !S1_M_shift_rot_stall);

--S1L2456 is std_1c20:inst|cpu:the_cpu|M_wr_data_unfiltered[22]~3649 at LC_X42_Y16_N3

--operation mode is normal

S1L2456 = AMPP_FUNCTION(S1L2062Q, S1_M_shift_rot_result[22]);

--S1L194 is std_1c20:inst|cpu:the_cpu|av_ld_data_aligned_or_div[22]~68 at LC_X41_Y18_N9

--operation mode is normal

S1L194 = AMPP_FUNCTION(S1_M_ctrl_ld_signed, S1_M_iw[4], S1L597, S1L239);

--S1_av_ld_data_aligned_or_div[22] is std_1c20:inst|cpu:the_cpu|av_ld_data_aligned_or_div[22] at LC_X41_Y18_N9

--operation mode is normal

S1_av_ld_data_aligned_or_div[22] = AMPP_FUNCTION(QC2__clk0, S1_M_ctrl_ld_signed, S1_M_iw[4], S1L597, S1L239, F1_data_out);

--S1L195Q is std_1c20:inst|cpu:the_cpu|av_ld_data_aligned_or_div[22]~69 at LC_X42_Y16_N9

--operation mode is normal

S1L195Q = AMPP_FUNCTION(QC2__clk0, S1L2063, S1_av_ld_aligning_data, S1L194, S1L1819, F1_data_out);

--S1L875 is std_1c20:inst|cpu:the_cpu|E_src1[22]~2017 at LC_X42_Y16_N2

--operation mode is normal

S1L875 = AMPP_FUNCTION(S1L195Q, S1_E_src1_prelim[22], S1L886Q, S1L2456);

--S1_E_src2_imm[22] is std_1c20:inst|cpu:the_cpu|E_src2_imm[22] at LC_X39_Y14_N9

--operation mode is normal

S1_E_src2_imm[22] = AMPP_FUNCTION(QC2__clk0, S1_D_iw[21], S1L301, S1_D_iw[12], S1L311, F1_data_out, S1_W_stall);

--S1L2358 is std_1c20:inst|cpu:the_cpu|M_st_data[22]~COMBOUT at LC_X42_Y17_N6

--operation mode is normal

S1L2358 = AMPP_FUNCTION(S1L2314, S1L2356, S1_E_iw[4]);

--S1L1025 is std_1c20:inst|cpu:the_cpu|E_src2[22]~1505 at LC_X43_Y14_N1

--operation mode is normal

S1L1025 = AMPP_FUNCTION(S1L2458, S1L1027, S1L1029);

--S1_E_extra_pc[19] is std_1c20:inst|cpu:the_cpu|E_extra_pc[19] at LC_X29_Y17_N3

--operation mode is normal

S1_E_extra_pc[19] = AMPP_FUNCTION(QC2__clk0, S1_D_pc_plus_one[19], S1_D_iw[21], S1L86, S1L287, F1_data_out, S1_W_stall);

--YC1_result[21] is std_1c20:inst|cpu:the_cpu|lpm_add_sub:Add8|alt_stratix_add_sub:stratix_adder|result[21] at LC_X36_Y14_N1

--operation mode is arithmetic

YC1_result[21] = AMPP_FUNCTION(S1L1020, S1L874, YC1L57, YC1L59, YC1L60, S1_E_ctrl_alu_subtract);

--YC1L62 is std_1c20:inst|cpu:the_cpu|lpm_add_sub:Add8|alt_stratix_add_sub:stratix_adder|add_sub_cell[21]~COUT at LC_X36_Y14_N1

--operation mode is arithmetic

YC1L62 = AMPP_FUNCTION(S1L1020, S1L874, YC1L59, S1_E_ctrl_alu_subtract);

--YC1L63 is std_1c20:inst|cpu:the_cpu|lpm_add_sub:Add8|alt_stratix_add_sub:stratix_adder|add_sub_cell[21]~COUTCOUT1_1329 at LC_X36_Y14_N1

--operation mode is arithmetic

YC1L63 = AMPP_FUNCTION(S1L1020, S1L874, YC1L60, S1_E_ctrl_alu_subtract);

--S1_E_src1_prelim[21] is std_1c20:inst|cpu:the_cpu|E_src1_prelim[21] at LC_X42_Y16_N5

--operation mode is normal

S1_E_src1_prelim[21] = AMPP_FUNCTION(QC2__clk0, S1_W_wr_data[21], S1_D_src1_hazard_W, S1L2455, CD1_q_b[21], F1_data_out, S1_D_src1_hazard_M, S1_W_stall);

--S1_M_shift_rot_result[21] is std_1c20:inst|cpu:the_cpu|M_shift_rot_result[21] at LC_X40_Y14_N2

--operation mode is normal

S1_M_shift_rot_result[21] = AMPP_FUNCTION(QC2__clk0, S1_M_ctrl_shift_rot_right, S1_M_shift_rot_result[22], S1L874, S1_M_shift_rot_result[20], F1_data_out, !S1_M_shift_rot_stall);

--S1L2453 is std_1c20:inst|cpu:the_cpu|M_wr_data_unfiltered[21]~3651 at LC_X42_Y14_N5

--operation mode is normal

S1L2453 = AMPP_FUNCTION(S1_M_shift_rot_result[21], S1L2062Q);

--S1L190 is std_1c20:inst|cpu:the_cpu|av_ld_data_aligned_or_div[21]~66 at LC_X41_Y19_N9

--operation mode is normal

S1L190 = AMPP_FUNCTION(S1_M_iw[4], S1L592, S1_M_ctrl_ld_signed, S1L239);

--S1L191Q is std_1c20:inst|cpu:the_cpu|av_ld_data_aligned_or_div[21]~108 at LC_X41_Y19_N9

--operation mode is normal

S1L191Q = AMPP_FUNCTION(QC2__clk0, S1_M_iw[4], S1L592, S1_M_ctrl_ld_signed, S1L239, F1_data_out);

--S1L192Q is std_1c20:inst|cpu:the_cpu|av_ld_data_aligned_or_div[21]~127 at LC_X35_Y18_N4

--operation mode is normal

S1L192Q = AMPP_FUNCTION(QC2__clk0, S1_av_ld_aligning_data, S1L190, S1L2063, S1L1803, F1_data_out);

--S1L874 is std_1c20:inst|cpu:the_cpu|E_src1[21]~2018 at LC_X42_Y14_N4

--operation mode is normal

S1L874 = AMPP_FUNCTION(S1_E_src1_prelim[21], S1L886Q, S1L192Q, S1L2453);

--S1_E_src2_imm[21] is std_1c20:inst|cpu:the_cpu|E_src2_imm[21] at LC_X41_Y14_N3

--operation mode is normal

S1_E_src2_imm[21] = AMPP_FUNCTION(QC2__clk0, S1_D_iw[21], S1L311, S1L301, S1_D_iw[11], F1_data_out, S1_W_stall);

--S1L2353 is std_1c20:inst|cpu:the_cpu|M_st_data[21]~COMBOUT at LC_X43_Y18_N1

--operation mode is normal

S1L2353 = AMPP_FUNCTION(S1L2309, S1L2351, S1_E_iw[4]);

--S1L1020 is std_1c20:inst|cpu:the_cpu|E_src2[21]~1506 at LC_X41_Y14_N7

--operation mode is normal

S1L1020 = AMPP_FUNCTION(S1L1022, S1L2455, S1L1024);

--S1_E_extra_pc[17] is std_1c20:inst|cpu:the_cpu|E_extra_pc[17] at LC_X29_Y17_N7

--operation mode is normal

S1_E_extra_pc[17] = AMPP_FUNCTION(QC2__clk0, S1L89, S1_D_pc_plus_one[17], S1_D_iw[21], S1L287, F1_data_out, S1_W_stall);

--YC1_result[19] is std_1c20:inst|cpu:the_cpu|lpm_add_sub:Add8|alt_stratix_add_sub:stratix_adder|result[19] at LC_X36_Y15_N9

--operation mode is arithmetic

YC1_result[19] = AMPP_FUNCTION(S1L1007, S1L872, YC1L43, YC1L54, YC1L55, S1_E_ctrl_alu_subtract);

--YC1L57 is std_1c20:inst|cpu:the_cpu|lpm_add_sub:Add8|alt_stratix_add_sub:stratix_adder|add_sub_cell[19]~COUT at LC_X36_Y15_N9

--operation mode is arithmetic

YC1L57 = AMPP_FUNCTION(S1L1007, S1L872, YC1L43, YC1L54, YC1L55, S1_E_ctrl_alu_subtract);

--S1L9 is std_1c20:inst|cpu:the_cpu|A_WE_StdLogicVector~14088 at LC_X33_Y18_N0

--operation mode is normal

S1L9 = AMPP_FUNCTION(S1_E_ctrl_dst_data_sel_pc_plus_one, S1_E_extra_pc[17], YC1_result[19]);

--S1_E_src1_prelim[19] is std_1c20:inst|cpu:the_cpu|E_src1_prelim[19] at LC_X44_Y15_N0

--operation mode is normal

S1_E_src1_prelim[19] = AMPP_FUNCTION(QC2__clk0, CD1_q_b[19], S1_W_wr_data[19], S1L2449, S1_D_src1_hazard_W, F1_data_out, S1_D_src1_hazard_M, S1_W_stall);

--S1_M_shift_rot_result[19] is std_1c20:inst|cpu:the_cpu|M_shift_rot_result[19] at LC_X40_Y14_N7

--operation mode is normal

S1_M_shift_rot_result[19] = AMPP_FUNCTION(QC2__clk0, S1_M_ctrl_shift_rot_right, S1_M_shift_rot_result[18], S1L872, S1_M_shift_rot_result[20], F1_data_out, !S1_M_shift_rot_stall);

--S1L2447 is std_1c20:inst|cpu:the_cpu|M_wr_data_unfiltered[19]~3653 at LC_X40_Y15_N4

--operation mode is normal

S1L2447 = AMPP_FUNCTION(S1L2062Q, S1_M_shift_rot_result[19]);

--S1_av_ld_data_aligned_or_div[19] is std_1c20:inst|cpu:the_cpu|av_ld_data_aligned_or_div[19] at LC_X41_Y18_N1

--operation mode is normal

S1_av_ld_data_aligned_or_div[19] = AMPP_FUNCTION(QC2__clk0, S1_M_ctrl_ld_signed, S1_M_iw[4], S1L582, S1L239, F1_data_out);

--S1L2448 is std_1c20:inst|cpu:the_cpu|M_wr_data_unfiltered[19]~3654 at LC_X41_Y18_N0

--operation mode is normal

S1L2448 = AMPP_FUNCTION(S1_av_ld_data_aligned_or_div[19], S1L236Q, S1L1779Q, S1L2062Q);

--S1L872 is std_1c20:inst|cpu:the_cpu|E_src1[19]~2019 at LC_X40_Y15_N2

--operation mode is normal

S1L872 = AMPP_FUNCTION(S1L886Q, S1L2447, S1_E_src1_prelim[19], S1L2448);

--S1_E_src2_imm[19] is std_1c20:inst|cpu:the_cpu|E_src2_imm[19] at LC_X40_Y15_N6

--operation mode is normal

S1_E_src2_imm[19] = AMPP_FUNCTION(QC2__clk0, S1_D_iw[9], S1_D_iw[21], S1L301, S1L311, F1_data_out, S1_W_stall);

--S1L2343 is std_1c20:inst|cpu:the_cpu|M_st_data[19]~COMBOUT at LC_X43_Y18_N7

--operation mode is normal

S1L2343 = AMPP_FUNCTION(S1_E_iw[4], S1L2341, S1L2295);

--S1L1007 is std_1c20:inst|cpu:the_cpu|E_src2[19]~1507 at LC_X40_Y15_N8

--operation mode is normal

S1L1007 = AMPP_FUNCTION(S1L1014, S1L1012, S1L2447, S1L2448);

--S1L809 is std_1c20:inst|cpu:the_cpu|E_logic_result[19]~15597 at LC_X34_Y16_N8

--operation mode is normal

S1L809 = AMPP_FUNCTION(S1_E_logic_op[1], S1_E_logic_op[0], S1L872, S1L1007);

--S1_E_extra_pc[16] is std_1c20:inst|cpu:the_cpu|E_extra_pc[16] at LC_X28_Y17_N9

--operation mode is normal

S1_E_extra_pc[16] = AMPP_FUNCTION(QC2__clk0, S1_D_iw[21], S1_D_pc_plus_one[16], S1L287, S1L92, F1_data_out, S1_W_stall);

--YC1_result[18] is std_1c20:inst|cpu:the_cpu|lpm_add_sub:Add8|alt_stratix_add_sub:stratix_adder|result[18] at LC_X36_Y15_N8

--operation mode is arithmetic

YC1_result[18] = AMPP_FUNCTION(S1L998, S1L871, YC1L43, YC1L51, YC1L52, S1_E_ctrl_alu_subtract);

--YC1L54 is std_1c20:inst|cpu:the_cpu|lpm_add_sub:Add8|alt_stratix_add_sub:stratix_adder|add_sub_cell[18]~COUT at LC_X36_Y15_N8

--operation mode is arithmetic

YC1L54 = AMPP_FUNCTION(S1L998, S1L871, YC1L51, S1_E_ctrl_alu_subtract);

--YC1L55 is std_1c20:inst|cpu:the_cpu|lpm_add_sub:Add8|alt_stratix_add_sub:stratix_adder|add_sub_cell[18]~COUTCOUT1_1325 at LC_X36_Y15_N8

--operation mode is arithmetic

YC1L55 = AMPP_FUNCTION(S1L998, S1L871, YC1L52, S1_E_ctrl_alu_subtract);

--S1L10 is std_1c20:inst|cpu:the_cpu|A_WE_StdLogicVector~14089 at LC_X31_Y16_N8

--operation mode is normal

S1L10 = AMPP_FUNCTION(S1_E_ctrl_dst_data_sel_pc_plus_one, S1_E_extra_pc[16], YC1_result[18]);

--S1_E_src1_prelim[18] is std_1c20:inst|cpu:the_cpu|E_src1_prelim[18] at LC_X44_Y15_N2

--operation mode is normal

S1_E_src1_prelim[18] = AMPP_FUNCTION(QC2__clk0, CD1_q_b[18], S1_W_wr_data[18], S1L2446, S1_D_src1_hazard_W, F1_data_out, S1_D_src1_hazard_M, S1_W_stall);

--S1_M_shift_rot_result[18] is std_1c20:inst|cpu:the_cpu|M_shift_rot_result[18] at LC_X40_Y14_N5

--operation mode is normal

S1_M_shift_rot_result[18] = AMPP_FUNCTION(QC2__clk0, S1_M_shift_rot_result[19], S1_M_shift_rot_result[17], S1L871, S1_M_ctrl_shift_rot_right, F1_data_out, !S1_M_shift_rot_stall);

--S1L2444 is std_1c20:inst|cpu:the_cpu|M_wr_data_unfiltered[18]~3655 at LC_X40_Y14_N9

--operation mode is normal

S1L2444 = AMPP_FUNCTION(S1_M_shift_rot_result[18], S1L2062Q);

--S1_av_ld_data_aligned_or_div[18] is std_1c20:inst|cpu:the_cpu|av_ld_data_aligned_or_div[18] at LC_X41_Y18_N8

--operation mode is normal

S1_av_ld_data_aligned_or_div[18] = AMPP_FUNCTION(QC2__clk0, S1L577, S1_M_iw[4], S1_M_ctrl_ld_signed, S1L239, F1_data_out);

--S1L2445 is std_1c20:inst|cpu:the_cpu|M_wr_data_unfiltered[18]~3656 at LC_X41_Y18_N4

--operation mode is normal

S1L2445 = AMPP_FUNCTION(S1L1776Q, S1L2062Q, S1_av_ld_data_aligned_or_div[18], S1L236Q);

--S1L871 is std_1c20:inst|cpu:the_cpu|E_src1[18]~2020 at LC_X40_Y14_N3

--operation mode is normal

S1L871 = AMPP_FUNCTION(S1L886Q, S1_E_src1_prelim[18], S1L2444, S1L2445);

--S1_E_src2_imm[18] is std_1c20:inst|cpu:the_cpu|E_src2_imm[18] at LC_X40_Y15_N7

--operation mode is normal

S1_E_src2_imm[18] = AMPP_FUNCTION(QC2__clk0, S1L311, S1_D_iw[8], S1L301, S1_D_iw[21], F1_data_out, S1_W_stall);

--S1L2338 is std_1c20:inst|cpu:the_cpu|M_st_data[18]~COMBOUT at LC_X41_Y15_N2

--operation mode is normal

S1L2338 = AMPP_FUNCTION(S1_E_iw[4], S1L2290, S1L2336);

--S1L998 is std_1c20:inst|cpu:the_cpu|E_src2[18]~1508 at LC_X41_Y15_N4

--operation mode is normal

S1L998 = AMPP_FUNCTION(S1L1006, S1L1004, S1L2445, S1L1002);

--S1L808 is std_1c20:inst|cpu:the_cpu|E_logic_result[18]~15598 at LC_X35_Y18_N2

--operation mode is normal

S1L808 = AMPP_FUNCTION(S1_E_logic_op[1], S1L998, S1L871, S1_E_logic_op[0]);

--S1_E_extra_pc[22] is std_1c20:inst|cpu:the_cpu|E_extra_pc[22] at LC_X30_Y17_N6

--operation mode is normal

S1_E_extra_pc[22] = AMPP_FUNCTION(QC2__clk0, S1_D_iw[21], S1L287, S1L95, S1_D_pc_plus_one[22], F1_data_out, S1_W_stall);

--YC1_result[24] is std_1c20:inst|cpu:the_cpu|lpm_add_sub:Add8|alt_stratix_add_sub:stratix_adder|result[24] at LC_X36_Y14_N4

--operation mode is arithmetic

YC1_result[24] = AMPP_FUNCTION(S1L1035, S1L877, YC1L57, YC1L68, YC1L69, S1_E_ctrl_alu_subtract);

--YC1L71 is std_1c20:inst|cpu:the_cpu|lpm_add_sub:Add8|alt_stratix_add_sub:stratix_adder|add_sub_cell[24]~COUT at LC_X36_Y14_N4

--operation mode is arithmetic

YC1L71 = AMPP_FUNCTION(S1L1035, S1L877, YC1L57, YC1L68, YC1L69, S1_E_ctrl_alu_subtract);

--S1_E_src2_imm[24] is std_1c20:inst|cpu:the_cpu|E_src2_imm[24] at LC_X38_Y14_N2

--operation mode is normal

S1_E_src2_imm[24] = AMPP_FUNCTION(QC2__clk0, S1_D_iw[21], S1_D_iw[14], S1L311, S1L301, F1_data_out, S1_W_stall);

--S1_E_src2_prelim[24] is std_1c20:inst|cpu:the_cpu|E_src2_prelim[24] at LC_X43_Y17_N4

--operation mode is normal

S1_E_src2_prelim[24] = AMPP_FUNCTION(QC2__clk0, S1_W_wr_data[24], S1L668, S1L2464, DD1_q_b[24], F1_data_out, S1L664, S1_W_stall);

--S1_E_src2_hazard_M is std_1c20:inst|cpu:the_cpu|E_src2_hazard_M at LC_X40_Y16_N5

--operation mode is normal

S1_E_src2_hazard_M = AMPP_FUNCTION(QC2__clk0, S1_E_dst_regnum[2], S1L660, S1_D_iw[24], S1L1163, F1_data_out, S1_W_stall);

--S1_M_shift_rot_result[24] is std_1c20:inst|cpu:the_cpu|M_shift_rot_result[24] at LC_X40_Y14_N6

--operation mode is normal

S1_M_shift_rot_result[24] = AMPP_FUNCTION(QC2__clk0, S1_M_shift_rot_result[23], S1_M_shift_rot_result[25], S1L877, S1_M_ctrl_shift_rot_right, F1_data_out, !S1_M_shift_rot_stall);

--S1L2462 is std_1c20:inst|cpu:the_cpu|M_wr_data_unfiltered[24]~3657 at LC_X43_Y17_N1

--operation mode is normal

S1L2462 = AMPP_FUNCTION(S1_M_shift_rot_result[24], S1L2062Q);

--S1L201 is std_1c20:inst|cpu:the_cpu|av_ld_data_aligned_or_div[24]~72 at LC_X41_Y20_N0

--operation mode is normal

S1L201 = AMPP_FUNCTION(S1_M_iw[4], S1L239, S1L607, S1_M_ctrl_ld_signed);

--S1L202Q is std_1c20:inst|cpu:the_cpu|av_ld_data_aligned_or_div[24]~106 at LC_X41_Y20_N0

--operation mode is normal

S1L202Q = AMPP_FUNCTION(QC2__clk0, S1_M_iw[4], S1L239, S1L607, S1_M_ctrl_ld_signed, F1_data_out);

--S1L203Q is std_1c20:inst|cpu:the_cpu|av_ld_data_aligned_or_div[24]~130 at LC_X42_Y21_N3

--operation mode is normal

S1L203Q = AMPP_FUNCTION(QC2__clk0, S1_av_ld_aligning_data, S1L201, S1L2063, S1L1867, F1_data_out);

--S1L1142 is std_1c20:inst|cpu:the_cpu|E_src2_reg[24]~472 at LC_X43_Y17_N3

--operation mode is normal

S1L1142 = AMPP_FUNCTION(S1L203Q, S1_E_src2_hazard_M, S1_E_src2_prelim[24], S1L2462);

--S1L1035 is std_1c20:inst|cpu:the_cpu|E_src2[24]~1509 at LC_X43_Y17_N2

--operation mode is normal

S1L1035 = AMPP_FUNCTION(S1_E_src2_imm[24], S1L1037, S1L1039, S1L2462);

--S1_E_src1_prelim[24] is std_1c20:inst|cpu:the_cpu|E_src1_prelim[24] at LC_X44_Y17_N2

--operation mode is normal

S1_E_src1_prelim[24] = AMPP_FUNCTION(QC2__clk0, CD1_q_b[24], S1_W_wr_data[24], S1L2464, S1_D_src1_hazard_W, F1_data_out, S1_D_src1_hazard_M, S1_W_stall);

--S1L877 is std_1c20:inst|cpu:the_cpu|E_src1[24]~2021 at LC_X43_Y17_N0

--operation mode is normal

S1L877 = AMPP_FUNCTION(S1L203Q, S1L886Q, S1_E_src1_prelim[24], S1L2462);

--S1_E_extra_pc[14] is std_1c20:inst|cpu:the_cpu|E_extra_pc[14] at LC_X28_Y16_N0

--operation mode is normal

S1_E_extra_pc[14] = AMPP_FUNCTION(QC2__clk0, S1_D_pc_plus_one[14], S1L98, S1_D_iw[21], S1L287, F1_data_out, S1_W_stall);

--YC1_result[16] is std_1c20:inst|cpu:the_cpu|lpm_add_sub:Add8|alt_stratix_add_sub:stratix_adder|result[16] at LC_X36_Y15_N6

--operation mode is arithmetic

YC1_result[16] = AMPP_FUNCTION(S1L980, S1L869, YC1L43, YC1L45, YC1L46, S1_E_ctrl_alu_subtract);

--YC1L48 is std_1c20:inst|cpu:the_cpu|lpm_add_sub:Add8|alt_stratix_add_sub:stratix_adder|add_sub_cell[16]~COUT at LC_X36_Y15_N6

--operation mode is arithmetic

YC1L48 = AMPP_FUNCTION(S1L980, S1L869, YC1L45, S1_E_ctrl_alu_subtract);

--YC1L49 is std_1c20:inst|cpu:the_cpu|lpm_add_sub:Add8|alt_stratix_add_sub:stratix_adder|add_sub_cell[16]~COUTCOUT1_1321 at LC_X36_Y15_N6

--operation mode is arithmetic

YC1L49 = AMPP_FUNCTION(S1L980, S1L869, YC1L46, S1_E_ctrl_alu_subtract);

--S1L12 is std_1c20:inst|cpu:the_cpu|A_WE_StdLogicVector~14091 at LC_X32_Y17_N3

--operation mode is normal

S1L12 = AMPP_FUNCTION(S1_E_ctrl_dst_data_sel_pc_plus_one, S1_E_extra_pc[14], YC1_result[16]);

--S1_E_src1_prelim[16] is std_1c20:inst|cpu:the_cpu|E_src1_prelim[16] at LC_X43_Y16_N1

--operation mode is normal

S1_E_src1_prelim[16] = AMPP_FUNCTION(QC2__clk0, CD1_q_b[16], S1_W_wr_data[16], S1L2440, S1_D_src1_hazard_W, F1_data_out, S1_D_src1_hazard_M, S1_W_stall);

--S1_M_shift_rot_result[16] is std_1c20:inst|cpu:the_cpu|M_shift_rot_result[16] at LC_X40_Y14_N8

--operation mode is normal

S1_M_shift_rot_result[16] = AMPP_FUNCTION(QC2__clk0, S1_M_ctrl_shift_rot_right, S1_M_shift_rot_result[17], S1L869, S1_M_shift_rot_result[15], F1_data_out, !S1_M_shift_rot_stall);

--S1_av_ld_data_aligned_or_div[16] is std_1c20:inst|cpu:the_cpu|av_ld_data_aligned_or_div[16] at LC_X43_Y19_N6

--operation mode is normal

S1_av_ld_data_aligned_or_div[16] = AMPP_FUNCTION(QC2__clk0, S1_M_iw[4], S1L239, S1_M_ctrl_ld_signed, S1L567, F1_data_out);

--S1L2439 is std_1c20:inst|cpu:the_cpu|M_wr_data_unfiltered[16]~3660 at LC_X43_Y15_N7

--operation mode is normal

S1L2439 = AMPP_FUNCTION(S1_av_ld_data_aligned_or_div[16], S1L2062Q, S1L1768Q, S1L236Q);

--S1L869 is std_1c20:inst|cpu:the_cpu|E_src1[16]~2022 at LC_X43_Y15_N1

--operation mode is normal

S1L869 = AMPP_FUNCTION(S1_E_src1_prelim[16], S1L886Q, S1L2439, S1L984);

--S1_E_src2_imm[16] is std_1c20:inst|cpu:the_cpu|E_src2_imm[16] at LC_X40_Y15_N5

--operation mode is normal

S1_E_src2_imm[16] = AMPP_FUNCTION(QC2__clk0, S1_D_iw[6], S1_D_iw[21], S1L301, S1L311, F1_data_out, S1_W_stall);

--S1L2328 is std_1c20:inst|cpu:the_cpu|M_st_data[16]~COMBOUT at LC_X43_Y16_N4

--operation mode is normal

S1L2328 = AMPP_FUNCTION(S1L2326, S1L2277, S1_E_iw[4]);

--S1L980 is std_1c20:inst|cpu:the_cpu|E_src2[16]~1510 at LC_X43_Y15_N8

--operation mode is normal

S1L980 = AMPP_FUNCTION(S1L984, S1L988, S1L986, S1L2439);

--S1L806 is std_1c20:inst|cpu:the_cpu|E_logic_result[16]~15600 at LC_X34_Y16_N7

--operation mode is normal

S1L806 = AMPP_FUNCTION(S1_E_logic_op[1], S1L869, S1_E_logic_op[0], S1L980);

--S1_E_extra_pc[13] is std_1c20:inst|cpu:the_cpu|E_extra_pc[13] at LC_X28_Y18_N2

--operation mode is normal

S1_E_extra_pc[13] = AMPP_FUNCTION(QC2__clk0, S1_D_pc_plus_one[13], S1_D_iw[21], S1L101, S1L287, F1_data_out, S1_W_stall);

--YC1_result[15] is std_1c20:inst|cpu:the_cpu|lpm_add_sub:Add8|alt_stratix_add_sub:stratix_adder|result[15] at LC_X36_Y15_N5

--operation mode is arithmetic

YC1_result[15] = AMPP_FUNCTION(S1L979, S1L868, YC1L43, S1_E_ctrl_alu_subtract);

--YC1L45 is std_1c20:inst|cpu:the_cpu|lpm_add_sub:Add8|alt_stratix_add_sub:stratix_adder|add_sub_cell[15]~COUT at LC_X36_Y15_N5

--operation mode is arithmetic

YC1L45 = AMPP_FUNCTION(S1L979, S1L868, S1_E_ctrl_alu_subtract);

--YC1L46 is std_1c20:inst|cpu:the_cpu|lpm_add_sub:Add8|alt_stratix_add_sub:stratix_adder|add_sub_cell[15]~COUTCOUT1_1319 at LC_X36_Y15_N5

--operation mode is arithmetic

YC1L46 = AMPP_FUNCTION(S1L979, S1L868, S1_E_ctrl_alu_subtract);

--S1L13 is std_1c20:inst|cpu:the_cpu|A_WE_StdLogicVector~14092 at LC_X35_Y17_N2

--operation mode is normal

S1L13 = AMPP_FUNCTION(S1_E_ctrl_dst_data_sel_pc_plus_one, S1_E_extra_pc[13], YC1_result[15]);

--S1_E_src2_imm[15] is std_1c20:inst|cpu:the_cpu|E_src2_imm[15] at LC_X38_Y17_N7

--operation mode is normal

S1_E_src2_imm[15] = AMPP_FUNCTION(QC2__clk0, S1_D_iw[2], S1L300, S1_D_iw[21], S1_D_iw[5], F1_data_out, S1_W_stall);

--S1_E_src2_prelim[15] is std_1c20:inst|cpu:the_cpu|E_src2_prelim[15] at LC_X38_Y17_N8

--operation mode is normal

S1_E_src2_prelim[15] = AMPP_FUNCTION(QC2__clk0, S1L668, S1_W_wr_data[15], S1L2437, DD1_q_b[15], F1_data_out, S1L664, S1_W_stall);

--S1_M_shift_rot_result[15] is std_1c20:inst|cpu:the_cpu|M_shift_rot_result[15] at LC_X37_Y17_N3

--operation mode is normal

S1_M_shift_rot_result[15] = AMPP_FUNCTION(QC2__clk0, S1_M_shift_rot_result[16], S1_M_shift_rot_result[14], S1L868, S1_M_ctrl_shift_rot_right, F1_data_out, !S1_M_shift_rot_stall);

--S1L2435 is std_1c20:inst|cpu:the_cpu|M_wr_data_unfiltered[15]~3661 at LC_X38_Y17_N3

--operation mode is normal

S1L2435 = AMPP_FUNCTION(S1L2056Q, S1_M_shift_rot_result[15]);

--S1_av_ld_data_aligned_or_div[15] is std_1c20:inst|cpu:the_cpu|av_ld_data_aligned_or_div[15] at LC_X38_Y19_N6

--operation mode is normal

S1_av_ld_data_aligned_or_div[15] = AMPP_FUNCTION(QC2__clk0, S1L642, S1L563, S1_av_fill_bit, S1_M_ld_align_sh16, F1_data_out, S1L1186);

--S1L2436 is std_1c20:inst|cpu:the_cpu|M_wr_data_unfiltered[15]~3662 at LC_X38_Y17_N5

--operation mode is normal

S1L2436 = AMPP_FUNCTION(S1L235Q, S1L2056Q, S1_av_ld_data_aligned_or_div[15], S1L1765Q);

--S1L1157 is std_1c20:inst|cpu:the_cpu|E_sth_data[15]~472 at LC_X38_Y17_N6

--operation mode is normal

S1L1157 = AMPP_FUNCTION(S1_E_src2_hazard_M, S1L2435, S1_E_src2_prelim[15], S1L2436);

--S1L979 is std_1c20:inst|cpu:the_cpu|E_src2[15]~1511 at LC_X38_Y17_N2

--operation mode is normal

S1L979 = AMPP_FUNCTION(S1_E_ctrl_src2_is_imm, S1_E_src2_imm[15], S1L1157);

--S1_E_src1_prelim[15] is std_1c20:inst|cpu:the_cpu|E_src1_prelim[15] at LC_X42_Y17_N3

--operation mode is normal

S1_E_src1_prelim[15] = AMPP_FUNCTION(QC2__clk0, S1_W_wr_data[15], CD1_q_b[15], S1L2437, S1_D_src1_hazard_W, F1_data_out, S1_D_src1_hazard_M, S1_W_stall);

--S1L868 is std_1c20:inst|cpu:the_cpu|E_src1[15]~2023 at LC_X38_Y17_N1

--operation mode is normal

S1L868 = AMPP_FUNCTION(S1L886Q, S1L2436, S1_E_src1_prelim[15], S1L2435);

--S1L805 is std_1c20:inst|cpu:the_cpu|E_logic_result[15]~15601 at LC_X34_Y17_N9

--operation mode is normal

S1L805 = AMPP_FUNCTION(S1_E_logic_op[0], S1L868, S1L979, S1_E_logic_op[1]);

--S1_E_extra_pc[12] is std_1c20:inst|cpu:the_cpu|E_extra_pc[12] at LC_X28_Y18_N0

--operation mode is normal

S1_E_extra_pc[12] = AMPP_FUNCTION(QC2__clk0, S1L104, S1_D_iw[21], S1_D_pc_plus_one[12], S1L287, F1_data_out, S1_W_stall);

--YC1_result[14] is std_1c20:inst|cpu:the_cpu|lpm_add_sub:Add8|alt_stratix_add_sub:stratix_adder|result[14] at LC_X36_Y15_N4

--operation mode is arithmetic

YC1_result[14] = AMPP_FUNCTION(S1L974, S1L867, YC1L29, YC1L40, YC1L41, S1_E_ctrl_alu_subtract);

--YC1L43 is std_1c20:inst|cpu:the_cpu|lpm_add_sub:Add8|alt_stratix_add_sub:stratix_adder|add_sub_cell[14]~COUT at LC_X36_Y15_N4

--operation mode is arithmetic

YC1L43 = AMPP_FUNCTION(S1L974, S1L867, YC1L29, YC1L40, YC1L41, S1_E_ctrl_alu_subtract);

--S1L14 is std_1c20:inst|cpu:the_cpu|A_WE_StdLogicVector~14093 at LC_X33_Y17_N0

--operation mode is normal

S1L14 = AMPP_FUNCTION(S1_E_extra_pc[12], S1_E_ctrl_dst_data_sel_pc_plus_one, YC1_result[14]);

--S1_E_src2_imm[14] is std_1c20:inst|cpu:the_cpu|E_src2_imm[14] at LC_X38_Y17_N4

--operation mode is normal

S1_E_src2_imm[14] = AMPP_FUNCTION(QC2__clk0, S1_D_iw[2], S1_D_iw[5], S1_D_iw[20], S1L300, F1_data_out, S1_W_stall);

--S1_E_src2_prelim[14] is std_1c20:inst|cpu:the_cpu|E_src2_prelim[14] at LC_X43_Y17_N6

--operation mode is normal

S1_E_src2_prelim[14] = AMPP_FUNCTION(QC2__clk0, S1_W_wr_data[14], S1L668, S1L2434, DD1_q_b[14], F1_data_out, S1L664, S1_W_stall);

--S1_M_shift_rot_result[14] is std_1c20:inst|cpu:the_cpu|M_shift_rot_result[14] at LC_X39_Y17_N3

--operation mode is normal

S1_M_shift_rot_result[14] = AMPP_FUNCTION(QC2__clk0, S1_M_shift_rot_result[15], S1_M_shift_rot_result[13], S1L867, S1_M_ctrl_shift_rot_right, F1_data_out, !S1_M_shift_rot_stall);

--S1L2432 is std_1c20:inst|cpu:the_cpu|M_wr_data_unfiltered[14]~3663 at LC_X39_Y17_N1

--operation mode is normal

S1L2432 = AMPP_FUNCTION(S1L2062Q, S1_M_shift_rot_result[14]);

--S1_av_ld_data_aligned_or_div[14] is std_1c20:inst|cpu:the_cpu|av_ld_data_aligned_or_div[14] at LC_X40_Y19_N9

--operation mode is normal

S1_av_ld_data_aligned_or_div[14] = AMPP_FUNCTION(QC2__clk0, S1_M_ld_align_sh16, S1L557, S1_av_fill_bit, S1L637, F1_data_out, S1L1186);

--S1L2433 is std_1c20:inst|cpu:the_cpu|M_wr_data_unfiltered[14]~3664 at LC_X40_Y17_N8

--operation mode is normal

S1L2433 = AMPP_FUNCTION(S1L2062Q, S1L236Q, S1L1762Q, S1_av_ld_data_aligned_or_div[14]);

--S1L1156 is std_1c20:inst|cpu:the_cpu|E_sth_data[14]~473 at LC_X39_Y17_N4

--operation mode is normal

S1L1156 = AMPP_FUNCTION(S1_E_src2_prelim[14], S1L2432, S1_E_src2_hazard_M, S1L2433);

--S1L974 is std_1c20:inst|cpu:the_cpu|E_src2[14]~1512 at LC_X39_Y17_N5

--operation mode is normal

S1L974 = AMPP_FUNCTION(S1L2432, S1_E_src2_imm[14], S1L976, S1L978);

--S1_E_src1_prelim[14] is std_1c20:inst|cpu:the_cpu|E_src1_prelim[14] at LC_X44_Y17_N6

--operation mode is normal

S1_E_src1_prelim[14] = AMPP_FUNCTION(QC2__clk0, S1_W_wr_data[14], CD1_q_b[14], S1L2434, S1_D_src1_hazard_W, F1_data_out, S1_D_src1_hazard_M, S1_W_stall);

--S1L867 is std_1c20:inst|cpu:the_cpu|E_src1[14]~2024 at LC_X39_Y17_N2

--operation mode is normal

S1L867 = AMPP_FUNCTION(S1L2433, S1_E_src1_prelim[14], S1L886Q, S1L2432);

--S1L804 is std_1c20:inst|cpu:the_cpu|E_logic_result[14]~15602 at LC_X34_Y17_N1

--operation mode is normal

S1L804 = AMPP_FUNCTION(S1_E_logic_op[0], S1L974, S1L867, S1_E_logic_op[1]);

--S1_E_extra_pc[11] is std_1c20:inst|cpu:the_cpu|E_extra_pc[11] at LC_X28_Y18_N1

--operation mode is normal

S1_E_extra_pc[11] = AMPP_FUNCTION(QC2__clk0, S1L287, S1_D_pc_plus_one[11], S1L107, S1_D_iw[21], F1_data_out, S1_W_stall);

--YC1_result[13] is std_1c20:inst|cpu:the_cpu|lpm_add_sub:Add8|alt_stratix_add_sub:stratix_adder|result[13] at LC_X36_Y15_N3

--operation mode is arithmetic

YC1_result[13] = AMPP_FUNCTION(S1L967, S1L866, YC1L29, YC1L37, YC1L38, S1_E_ctrl_alu_subtract);

--YC1L40 is std_1c20:inst|cpu:the_cpu|lpm_add_sub:Add8|alt_stratix_add_sub:stratix_adder|add_sub_cell[13]~COUT at LC_X36_Y15_N3

--operation mode is arithmetic

YC1L40 = AMPP_FUNCTION(S1L967, S1L866, YC1L37, S1_E_ctrl_alu_subtract);

--YC1L41 is std_1c20:inst|cpu:the_cpu|lpm_add_sub:Add8|alt_stratix_add_sub:stratix_adder|add_sub_cell[13]~COUTCOUT1_1317 at LC_X36_Y15_N3

--operation mode is arithmetic

YC1L41 = AMPP_FUNCTION(S1L967, S1L866, YC1L38, S1_E_ctrl_alu_subtract);

--S1L15 is std_1c20:inst|cpu:the_cpu|A_WE_StdLogicVector~14094 at LC_X32_Y17_N6

--operation mode is normal

S1L15 = AMPP_FUNCTION(S1_E_ctrl_dst_data_sel_pc_plus_one, YC1_result[13], S1_E_extra_pc[11]);

--S1_E_src2_imm[13] is std_1c20:inst|cpu:the_cpu|E_src2_imm[13] at LC_X37_Y18_N2

--operation mode is normal

S1_E_src2_imm[13] = AMPP_FUNCTION(QC2__clk0, S1_D_iw[5], S1L300, S1_D_iw[2], S1_D_iw[19], F1_data_out, S1_W_stall);

--S1_E_src2_prelim[13] is std_1c20:inst|cpu:the_cpu|E_src2_prelim[13] at LC_X37_Y19_N6

--operation mode is normal

S1_E_src2_prelim[13] = AMPP_FUNCTION(QC2__clk0, S1_W_wr_data[13], S1L668, S1L2431, DD1_q_b[13], F1_data_out, S1L664, S1_W_stall);

--S1_M_shift_rot_result[13] is std_1c20:inst|cpu:the_cpu|M_shift_rot_result[13] at LC_X37_Y17_N6

--operation mode is normal

S1_M_shift_rot_result[13] = AMPP_FUNCTION(QC2__clk0, S1_M_shift_rot_result[12], S1_M_shift_rot_result[14], S1L866, S1_M_ctrl_shift_rot_right, F1_data_out, !S1_M_shift_rot_stall);

--S1L2429 is std_1c20:inst|cpu:the_cpu|M_wr_data_unfiltered[13]~3665 at LC_X37_Y19_N9

--operation mode is normal

S1L2429 = AMPP_FUNCTION(S1L2056Q, S1_M_shift_rot_result[13]);

--S1L172 is std_1c20:inst|cpu:the_cpu|av_ld_data_aligned_or_div[13]~COMBOUT at LC_X38_Y19_N5

--operation mode is normal

S1L172 = AMPP_FUNCTION(S1L632, S1L551, S1_M_ld_align_sh16);

--S1_av_ld_data_aligned_or_div[13] is std_1c20:inst|cpu:the_cpu|av_ld_data_aligned_or_div[13] at LC_X38_Y19_N5

--operation mode is normal

S1_av_ld_data_aligned_or_div[13] = AMPP_FUNCTION(QC2__clk0, S1L632, S1L551, S1_av_fill_bit, S1_M_ld_align_sh16, F1_data_out, S1L1186);

--S1L2430 is std_1c20:inst|cpu:the_cpu|M_wr_data_unfiltered[13]~3666 at LC_X37_Y19_N4

--operation mode is normal

S1L2430 = AMPP_FUNCTION(S1L2056Q, S1_av_ld_data_aligned_or_div[13], S1L235Q, S1_M_alu_result[13]);

--S1L1155 is std_1c20:inst|cpu:the_cpu|E_sth_data[13]~474 at LC_X37_Y19_N7

--operation mode is normal

S1L1155 = AMPP_FUNCTION(S1_E_src2_prelim[13], S1L2430, S1L2429, S1_E_src2_hazard_M);

--S1L967 is std_1c20:inst|cpu:the_cpu|E_src2[13]~1513 at LC_X37_Y19_N1

--operation mode is normal

S1L967 = AMPP_FUNCTION(S1L973, S1L2430, S1L2429, S1L971);

--S1_E_src1_prelim[13] is std_1c20:inst|cpu:the_cpu|E_src1_prelim[13] at LC_X38_Y18_N1

--operation mode is normal

S1_E_src1_prelim[13] = AMPP_FUNCTION(QC2__clk0, S1_W_wr_data[13], S1_D_src1_hazard_W, S1L2431, CD1_q_b[13], F1_data_out, S1_D_src1_hazard_M, S1_W_stall);

--S1L866 is std_1c20:inst|cpu:the_cpu|E_src1[13]~2025 at LC_X37_Y19_N3

--operation mode is normal

S1L866 = AMPP_FUNCTION(S1L2429, S1_E_src1_prelim[13], S1L2430, S1L886Q);

--S1L803 is std_1c20:inst|cpu:the_cpu|E_logic_result[13]~15603 at LC_X34_Y17_N8

--operation mode is normal

S1L803 = AMPP_FUNCTION(S1_E_logic_op[0], S1L866, S1L967, S1_E_logic_op[1]);

--S1_E_extra_pc[10] is std_1c20:inst|cpu:the_cpu|E_extra_pc[10] at LC_X30_Y18_N9

--operation mode is normal

S1_E_extra_pc[10] = AMPP_FUNCTION(QC2__clk0, S1_D_pc_plus_one[10], S1_D_iw[21], S1L287, S1L110, F1_data_out, S1_W_stall);

--YC1_result[12] is std_1c20:inst|cpu:the_cpu|lpm_add_sub:Add8|alt_stratix_add_sub:stratix_adder|result[12] at LC_X36_Y15_N2

--operation mode is arithmetic

YC1_result[12] = AMPP_FUNCTION(S1L966, S1L865, YC1L29, YC1L34, YC1L35, S1_E_ctrl_alu_subtract);

--YC1L37 is std_1c20:inst|cpu:the_cpu|lpm_add_sub:Add8|alt_stratix_add_sub:stratix_adder|add_sub_cell[12]~COUT at LC_X36_Y15_N2

--operation mode is arithmetic

YC1L37 = AMPP_FUNCTION(S1L966, S1L865, YC1L34, S1_E_ctrl_alu_subtract);

--YC1L38 is std_1c20:inst|cpu:the_cpu|lpm_add_sub:Add8|alt_stratix_add_sub:stratix_adder|add_sub_cell[12]~COUTCOUT1_1315 at LC_X36_Y15_N2

--operation mode is arithmetic

YC1L38 = AMPP_FUNCTION(S1L966, S1L865, YC1L35, S1_E_ctrl_alu_subtract);

--S1L16 is std_1c20:inst|cpu:the_cpu|A_WE_StdLogicVector~14095 at LC_X33_Y17_N4

--operation mode is normal

S1L16 = AMPP_FUNCTION(S1_E_ctrl_dst_data_sel_pc_plus_one, S1_E_extra_pc[10], YC1_result[12]);

--S1_E_src2_imm[12] is std_1c20:inst|cpu:the_cpu|E_src2_imm[12] at LC_X38_Y17_N9

--operation mode is normal

S1_E_src2_imm[12] = AMPP_FUNCTION(QC2__clk0, S1_D_iw[2], S1_D_iw[5], S1_D_iw[18], S1L300, F1_data_out, S1_W_stall);

--S1_E_src2_prelim[12] is std_1c20:inst|cpu:the_cpu|E_src2_prelim[12] at LC_X41_Y17_N2

--operation mode is normal

S1_E_src2_prelim[12] = AMPP_FUNCTION(QC2__clk0, DD1_q_b[12], S1L668, S1L2428, S1_W_wr_data[12], F1_data_out, S1L664, S1_W_stall);

--S1_M_shift_rot_result[12] is std_1c20:inst|cpu:the_cpu|M_shift_rot_result[12] at LC_X37_Y17_N0

--operation mode is normal

S1_M_shift_rot_result[12] = AMPP_FUNCTION(QC2__clk0, S1_M_shift_rot_result[11], S1_M_shift_rot_result[13], S1L865, S1_M_ctrl_shift_rot_right, F1_data_out, !S1_M_shift_rot_stall);

--S1L2426 is std_1c20:inst|cpu:the_cpu|M_wr_data_unfiltered[12]~3667 at LC_X40_Y17_N0

--operation mode is normal

S1L2426 = AMPP_FUNCTION(S1_M_shift_rot_result[12], S1L2062Q);

--S1L169 is std_1c20:inst|cpu:the_cpu|av_ld_data_aligned_or_div[12]~COMBOUT at LC_X40_Y19_N5

--operation mode is normal

S1L169 = AMPP_FUNCTION(S1L545, S1L627, S1_M_ld_align_sh16);

--S1_av_ld_data_aligned_or_div[12] is std_1c20:inst|cpu:the_cpu|av_ld_data_aligned_or_div[12] at LC_X40_Y19_N5

--operation mode is normal

S1_av_ld_data_aligned_or_div[12] = AMPP_FUNCTION(QC2__clk0, S1L545, S1L627, S1_av_fill_bit, S1_M_ld_align_sh16, F1_data_out, S1L1186);

--S1L2427 is std_1c20:inst|cpu:the_cpu|M_wr_data_unfiltered[12]~3668 at LC_X40_Y17_N9

--operation mode is normal

S1L2427 = AMPP_FUNCTION(S1L2062Q, S1_av_ld_data_aligned_or_div[12], S1L236Q, S1_M_alu_result[12]);

--S1L1154 is std_1c20:inst|cpu:the_cpu|E_sth_data[12]~475 at LC_X40_Y17_N1

--operation mode is normal

S1L1154 = AMPP_FUNCTION(S1_E_src2_prelim[12], S1_E_src2_hazard_M, S1L2427, S1L2426);

--S1L966 is std_1c20:inst|cpu:the_cpu|E_src2[12]~1514 at LC_X40_Y17_N2

--operation mode is normal

S1L966 = AMPP_FUNCTION(S1_E_ctrl_src2_is_imm, S1_E_src2_imm[12], S1L1154);

--S1_E_src1_prelim[12] is std_1c20:inst|cpu:the_cpu|E_src1_prelim[12] at LC_X42_Y17_N4

--operation mode is normal

S1_E_src1_prelim[12] = AMPP_FUNCTION(QC2__clk0, S1_W_wr_data[12], CD1_q_b[12], S1L2428, S1_D_src1_hazard_W, F1_data_out, S1_D_src1_hazard_M, S1_W_stall);

--S1L865 is std_1c20:inst|cpu:the_cpu|E_src1[12]~2026 at LC_X40_Y17_N3

--operation mode is normal

S1L865 = AMPP_FUNCTION(S1L2427, S1L2426, S1_E_src1_prelim[12], S1L886Q);

--S1L802 is std_1c20:inst|cpu:the_cpu|E_logic_result[12]~15604 at LC_X34_Y17_N3

--operation mode is normal

S1L802 = AMPP_FUNCTION(S1_E_logic_op[0], S1L966, S1L865, S1_E_logic_op[1]);

--S1_E_extra_pc[15] is std_1c20:inst|cpu:the_cpu|E_extra_pc[15] at LC_X30_Y18_N4

--operation mode is normal

S1_E_extra_pc[15] = AMPP_FUNCTION(QC2__clk0, S1_D_iw[21], S1L112, S1L287, S1_D_pc_plus_one[15], F1_data_out, S1_W_stall);

--YC1_result[17] is std_1c20:inst|cpu:the_cpu|lpm_add_sub:Add8|alt_stratix_add_sub:stratix_adder|result[17] at LC_X36_Y15_N7

--operation mode is arithmetic

YC1_result[17] = AMPP_FUNCTION(S1L989, S1L870, YC1L43, YC1L48, YC1L49, S1_E_ctrl_alu_subtract);

--YC1L51 is std_1c20:inst|cpu:the_cpu|lpm_add_sub:Add8|alt_stratix_add_sub:stratix_adder|add_sub_cell[17]~COUT at LC_X36_Y15_N7

--operation mode is arithmetic

YC1L51 = AMPP_FUNCTION(S1L989, S1L870, YC1L48, S1_E_ctrl_alu_subtract);

--YC1L52 is std_1c20:inst|cpu:the_cpu|lpm_add_sub:Add8|alt_stratix_add_sub:stratix_adder|add_sub_cell[17]~COUTCOUT1_1323 at LC_X36_Y15_N7

--operation mode is arithmetic

YC1L52 = AMPP_FUNCTION(S1L989, S1L870, YC1L49, S1_E_ctrl_alu_subtract);

--S1L17 is std_1c20:inst|cpu:the_cpu|A_WE_StdLogicVector~14096 at LC_X33_Y18_N7

--operation mode is normal

S1L17 = AMPP_FUNCTION(S1_E_extra_pc[15], YC1_result[17], S1_E_ctrl_dst_data_sel_pc_plus_one);

--S1_E_src1_prelim[17] is std_1c20:inst|cpu:the_cpu|E_src1_prelim[17] at LC_X44_Y15_N7

--operation mode is normal

S1_E_src1_prelim[17] = AMPP_FUNCTION(QC2__clk0, S1_W_wr_data[17], CD1_q_b[17], S1L2443, S1_D_src1_hazard_W, F1_data_out, S1_D_src1_hazard_M, S1_W_stall);

--S1_M_shift_rot_result[17] is std_1c20:inst|cpu:the_cpu|M_shift_rot_result[17] at LC_X40_Y14_N4

--operation mode is normal

S1_M_shift_rot_result[17] = AMPP_FUNCTION(QC2__clk0, S1_M_ctrl_shift_rot_right, S1_M_shift_rot_result[18], S1L870, S1_M_shift_rot_result[16], F1_data_out, !S1_M_shift_rot_stall);

--S1L2441 is std_1c20:inst|cpu:the_cpu|M_wr_data_unfiltered[17]~3669 at LC_X42_Y14_N8

--operation mode is normal

S1L2441 = AMPP_FUNCTION(S1_M_shift_rot_result[17], S1L2062Q);

--S1_av_ld_data_aligned_or_div[17] is std_1c20:inst|cpu:the_cpu|av_ld_data_aligned_or_div[17] at LC_X41_Y18_N6

--operation mode is normal

S1_av_ld_data_aligned_or_div[17] = AMPP_FUNCTION(QC2__clk0, S1L239, S1L572, S1_M_ctrl_ld_signed, S1_M_iw[4], F1_data_out);

--S1L2442 is std_1c20:inst|cpu:the_cpu|M_wr_data_unfiltered[17]~3670 at LC_X41_Y18_N3

--operation mode is normal

S1L2442 = AMPP_FUNCTION(S1_av_ld_data_aligned_or_div[17], S1L236Q, S1L1773Q, S1L2062Q);

--S1L870 is std_1c20:inst|cpu:the_cpu|E_src1[17]~2027 at LC_X41_Y15_N6

--operation mode is normal

S1L870 = AMPP_FUNCTION(S1L886Q, S1_E_src1_prelim[17], S1L2441, S1L2442);

--S1_E_src2_imm[17] is std_1c20:inst|cpu:the_cpu|E_src2_imm[17] at LC_X41_Y14_N0

--operation mode is normal

S1_E_src2_imm[17] = AMPP_FUNCTION(QC2__clk0, S1_D_iw[21], S1_D_iw[7], S1L301, S1L311, F1_data_out, S1_W_stall);

--S1L2333 is std_1c20:inst|cpu:the_cpu|M_st_data[17]~COMBOUT at LC_X43_Y18_N6

--operation mode is normal

S1L2333 = AMPP_FUNCTION(S1_E_iw[4], S1L2282, S1L2331);

--S1L989 is std_1c20:inst|cpu:the_cpu|E_src2[17]~1515 at LC_X41_Y14_N5

--operation mode is normal

S1L989 = AMPP_FUNCTION(S1L993, S1L997, S1L995, S1L2442);

--S1L807 is std_1c20:inst|cpu:the_cpu|E_logic_result[17]~15605 at LC_X34_Y17_N6

--operation mode is normal

S1L807 = AMPP_FUNCTION(S1_E_logic_op[1], S1L989, S1L870, S1_E_logic_op[0]);

--S1_E_extra_pc[23] is std_1c20:inst|cpu:the_cpu|E_extra_pc[23] at LC_X28_Y17_N8

--operation mode is normal

S1_E_extra_pc[23] = AMPP_FUNCTION(QC2__clk0, S1_D_pc_plus_one[23], S1_D_iw[21], S1L287, S1L114, F1_data_out, S1_W_stall);

--YC1_result[25] is std_1c20:inst|cpu:the_cpu|lpm_add_sub:Add8|alt_stratix_add_sub:stratix_adder|result[25] at LC_X36_Y14_N5

--operation mode is arithmetic

YC1_result[25] = AMPP_FUNCTION(S1L1040, S1L878, YC1L71, S1_E_ctrl_alu_subtract);

--YC1L73 is std_1c20:inst|cpu:the_cpu|lpm_add_sub:Add8|alt_stratix_add_sub:stratix_adder|add_sub_cell[25]~COUT at LC_X36_Y14_N5

--operation mode is arithmetic

YC1L73 = AMPP_FUNCTION(S1L1040, S1L878, S1_E_ctrl_alu_subtract);

--YC1L74 is std_1c20:inst|cpu:the_cpu|lpm_add_sub:Add8|alt_stratix_add_sub:stratix_adder|add_sub_cell[25]~COUTCOUT1_1335 at LC_X36_Y14_N5

--operation mode is arithmetic

YC1L74 = AMPP_FUNCTION(S1L1040, S1L878, S1_E_ctrl_alu_subtract);

--S1_E_src2_imm[25] is std_1c20:inst|cpu:the_cpu|E_src2_imm[25] at LC_X38_Y14_N4

--operation mode is normal

S1_E_src2_imm[25] = AMPP_FUNCTION(QC2__clk0, S1_D_iw[21], S1_D_iw[15], S1L311, S1L301, F1_data_out, S1_W_stall);

--S1_E_src2_prelim[25] is std_1c20:inst|cpu:the_cpu|E_src2_prelim[25] at LC_X39_Y14_N8

--operation mode is normal

S1_E_src2_prelim[25] = AMPP_FUNCTION(QC2__clk0, S1_W_wr_data[25], S1L668, S1L2467, DD1_q_b[25], F1_data_out, S1L664, S1_W_stall);

--S1_M_shift_rot_result[25] is std_1c20:inst|cpu:the_cpu|M_shift_rot_result[25] at LC_X40_Y12_N7

--operation mode is normal

S1_M_shift_rot_result[25] = AMPP_FUNCTION(QC2__clk0, S1_M_shift_rot_result[24], S1_M_shift_rot_result[26], S1L878, S1_M_ctrl_shift_rot_right, F1_data_out, !S1_M_shift_rot_stall);

--S1L2465 is std_1c20:inst|cpu:the_cpu|M_wr_data_unfiltered[25]~3671 at LC_X39_Y13_N0

--operation mode is normal

S1L2465 = AMPP_FUNCTION(S1L2056Q, S1_M_shift_rot_result[25]);

--S1L205 is std_1c20:inst|cpu:the_cpu|av_ld_data_aligned_or_div[25]~74 at LC_X43_Y20_N6

--operation mode is normal

S1L205 = AMPP_FUNCTION(S1_M_ctrl_ld_signed, S1_M_iw[4], S1L239, S1L612);

--S1L206Q is std_1c20:inst|cpu:the_cpu|av_ld_data_aligned_or_div[25]~104 at LC_X43_Y20_N6

--operation mode is normal

S1L206Q = AMPP_FUNCTION(QC2__clk0, S1_M_ctrl_ld_signed, S1_M_iw[4], S1L239, S1L612, F1_data_out);

--S1L211Q is std_1c20:inst|cpu:the_cpu|av_ld_data_aligned_or_div[25]~131 at LC_X33_Y20_N6

--operation mode is normal

S1L211Q = AMPP_FUNCTION(QC2__clk0, S1_av_ld_aligning_data, S1L2063, S1L205, S1L1871, F1_data_out);

--S1L1143 is std_1c20:inst|cpu:the_cpu|E_src2_reg[25]~473 at LC_X39_Y13_N7

--operation mode is normal

S1L1143 = AMPP_FUNCTION(S1_E_src2_hazard_M, S1_E_src2_prelim[25], S1L211Q, S1L2465);

--S1L1040 is std_1c20:inst|cpu:the_cpu|E_src2[25]~1516 at LC_X39_Y13_N9

--operation mode is normal

S1L1040 = AMPP_FUNCTION(S1L1044, S1L1042, S1L211Q, S1L2465);

--S1_E_src1_prelim[25] is std_1c20:inst|cpu:the_cpu|E_src1_prelim[25] at LC_X39_Y13_N5

--operation mode is normal

S1_E_src1_prelim[25] = AMPP_FUNCTION(QC2__clk0, S1_D_src1_hazard_W, CD1_q_b[25], S1L2467, S1_W_wr_data[25], F1_data_out, S1_D_src1_hazard_M, S1_W_stall);

--S1L878 is std_1c20:inst|cpu:the_cpu|E_src1[25]~2028 at LC_X39_Y13_N1

--operation mode is normal

S1L878 = AMPP_FUNCTION(S1L886Q, S1_E_src1_prelim[25], S1L211Q, S1L2465);

--S1_E_extra_pc[18] is std_1c20:inst|cpu:the_cpu|E_extra_pc[18] at LC_X29_Y17_N4

--operation mode is normal

S1_E_extra_pc[18] = AMPP_FUNCTION(QC2__clk0, S1_D_pc_plus_one[18], S1L115, S1_D_iw[21], S1L287, F1_data_out, S1_W_stall);

--YC1_result[20] is std_1c20:inst|cpu:the_cpu|lpm_add_sub:Add8|alt_stratix_add_sub:stratix_adder|result[20] at LC_X36_Y14_N0

--operation mode is arithmetic

YC1_result[20] = AMPP_FUNCTION(S1L1015, S1L873, YC1L57, S1_E_ctrl_alu_subtract);

--YC1L59 is std_1c20:inst|cpu:the_cpu|lpm_add_sub:Add8|alt_stratix_add_sub:stratix_adder|add_sub_cell[20]~COUT at LC_X36_Y14_N0

--operation mode is arithmetic

YC1L59 = AMPP_FUNCTION(S1L1015, S1L873, S1_E_ctrl_alu_subtract);

--YC1L60 is std_1c20:inst|cpu:the_cpu|lpm_add_sub:Add8|alt_stratix_add_sub:stratix_adder|add_sub_cell[20]~COUTCOUT1_1327 at LC_X36_Y14_N0

--operation mode is arithmetic

YC1L60 = AMPP_FUNCTION(S1L1015, S1L873, S1_E_ctrl_alu_subtract);

--S1_E_src1_prelim[20] is std_1c20:inst|cpu:the_cpu|E_src1_prelim[20] at LC_X44_Y17_N0

--operation mode is normal

S1_E_src1_prelim[20] = AMPP_FUNCTION(QC2__clk0, S1_W_wr_data[20], CD1_q_b[20], S1L2452, S1_D_src1_hazard_W, F1_data_out, S1_D_src1_hazard_M, S1_W_stall);

--S1_M_shift_rot_result[20] is std_1c20:inst|cpu:the_cpu|M_shift_rot_result[20] at LC_X39_Y17_N0

--operation mode is normal

S1_M_shift_rot_result[20] = AMPP_FUNCTION(QC2__clk0, S1_M_shift_rot_result[21], S1_M_shift_rot_result[19], S1L873, S1_M_ctrl_shift_rot_right, F1_data_out, !S1_M_shift_rot_stall);

--S1L2450 is std_1c20:inst|cpu:the_cpu|M_wr_data_unfiltered[20]~3673 at LC_X39_Y17_N8

--operation mode is normal

S1L2450 = AMPP_FUNCTION(S1L2062Q, S1_M_shift_rot_result[20]);

--S1L186 is std_1c20:inst|cpu:the_cpu|av_ld_data_aligned_or_div[20]~64 at LC_X41_Y20_N2

--operation mode is normal

S1L186 = AMPP_FUNCTION(S1L239, S1L587, S1_M_iw[4], S1_M_ctrl_ld_signed);

--S1L187Q is std_1c20:inst|cpu:the_cpu|av_ld_data_aligned_or_div[20]~109 at LC_X41_Y20_N2

--operation mode is normal

S1L187Q = AMPP_FUNCTION(QC2__clk0, S1L239, S1L587, S1_M_iw[4], S1_M_ctrl_ld_signed, F1_data_out);

--S1L188Q is std_1c20:inst|cpu:the_cpu|av_ld_data_aligned_or_div[20]~128 at LC_X40_Y17_N4

--operation mode is normal

S1L188Q = AMPP_FUNCTION(QC2__clk0, S1_av_ld_aligning_data, S1L186, S1L1783, S1L2063, F1_data_out);

--S1L873 is std_1c20:inst|cpu:the_cpu|E_src1[20]~2029 at LC_X39_Y17_N9

--operation mode is normal

S1L873 = AMPP_FUNCTION(S1_E_src1_prelim[20], S1L188Q, S1L886Q, S1L2450);

--S1_E_src2_imm[20] is std_1c20:inst|cpu:the_cpu|E_src2_imm[20] at LC_X39_Y14_N3

--operation mode is normal

S1_E_src2_imm[20] = AMPP_FUNCTION(QC2__clk0, S1_D_iw[21], S1L301, S1_D_iw[10], S1L311, F1_data_out, S1_W_stall);

--S1L2348 is std_1c20:inst|cpu:the_cpu|M_st_data[20]~COMBOUT at LC_X39_Y14_N0

--operation mode is normal

S1L2348 = AMPP_FUNCTION(S1L2346, S1L2303, S1_E_iw[4]);

--S1L1015 is std_1c20:inst|cpu:the_cpu|E_src2[20]~1517 at LC_X39_Y14_N2

--operation mode is normal

S1L1015 = AMPP_FUNCTION(S1L2452, S1L1017, S1L1019);

--S1_E_extra_pc[21] is std_1c20:inst|cpu:the_cpu|E_extra_pc[21] at LC_X28_Y16_N3

--operation mode is normal

S1_E_extra_pc[21] = AMPP_FUNCTION(QC2__clk0, S1_D_pc_plus_one[21], S1_D_iw[21], S1L118, S1L287, F1_data_out, S1_W_stall);

--YC1_result[23] is std_1c20:inst|cpu:the_cpu|lpm_add_sub:Add8|alt_stratix_add_sub:stratix_adder|result[23] at LC_X36_Y14_N3

--operation mode is arithmetic

YC1_result[23] = AMPP_FUNCTION(S1L1030, S1L876, YC1L57, YC1L65, YC1L66, S1_E_ctrl_alu_subtract);

--YC1L68 is std_1c20:inst|cpu:the_cpu|lpm_add_sub:Add8|alt_stratix_add_sub:stratix_adder|add_sub_cell[23]~COUT at LC_X36_Y14_N3

--operation mode is arithmetic

YC1L68 = AMPP_FUNCTION(S1L1030, S1L876, YC1L65, S1_E_ctrl_alu_subtract);

--YC1L69 is std_1c20:inst|cpu:the_cpu|lpm_add_sub:Add8|alt_stratix_add_sub:stratix_adder|add_sub_cell[23]~COUTCOUT1_1333 at LC_X36_Y14_N3

--operation mode is arithmetic

YC1L69 = AMPP_FUNCTION(S1L1030, S1L876, YC1L66, S1_E_ctrl_alu_subtract);

--S1_E_src1_prelim[23] is std_1c20:inst|cpu:the_cpu|E_src1_prelim[23] at LC_X41_Y13_N3

--operation mode is normal

S1_E_src1_prelim[23] = AMPP_FUNCTION(QC2__clk0, S1_W_wr_data[23], CD1_q_b[23], S1L2461, S1_D_src1_hazard_W, F1_data_out, S1_D_src1_hazard_M, S1_W_stall);

--S1_M_shift_rot_result[23] is std_1c20:inst|cpu:the_cpu|M_shift_rot_result[23] at LC_X40_Y14_N1

--operation mode is normal

S1_M_shift_rot_result[23] = AMPP_FUNCTION(QC2__clk0, S1_M_shift_rot_result[24], S1_M_shift_rot_result[22], S1L876, S1_M_ctrl_shift_rot_right, F1_data_out, !S1_M_shift_rot_stall);

--S1L2459 is std_1c20:inst|cpu:the_cpu|M_wr_data_unfiltered[23]~3675 at LC_X41_Y13_N6

--operation mode is normal

S1L2459 = AMPP_FUNCTION(S1_M_shift_rot_result[23], S1L2062Q);

--S1L197 is std_1c20:inst|cpu:the_cpu|av_ld_data_aligned_or_div[23]~70 at LC_X41_Y20_N3

--operation mode is normal

S1L197 = AMPP_FUNCTION(S1_M_iw[4], S1L602, S1L239, S1_M_ctrl_ld_signed);

--S1L198Q is std_1c20:inst|cpu:the_cpu|av_ld_data_aligned_or_div[23]~107 at LC_X41_Y20_N3

--operation mode is normal

S1L198Q = AMPP_FUNCTION(QC2__clk0, S1_M_iw[4], S1L602, S1L239, S1_M_ctrl_ld_signed, F1_data_out);

--S1L199Q is std_1c20:inst|cpu:the_cpu|av_ld_data_aligned_or_div[23]~129 at LC_X33_Y20_N4

--operation mode is normal

S1L199Q = AMPP_FUNCTION(QC2__clk0, S1_av_ld_aligning_data, S1L2063, S1L197, T1L449, F1_data_out);

--S1L876 is std_1c20:inst|cpu:the_cpu|E_src1[23]~2030 at LC_X41_Y13_N7

--operation mode is normal

S1L876 = AMPP_FUNCTION(S1L199Q, S1_E_src1_prelim[23], S1L886Q, S1L2459);

--S1_E_src2_imm[23] is std_1c20:inst|cpu:the_cpu|E_src2_imm[23] at LC_X41_Y13_N9

--operation mode is normal

S1_E_src2_imm[23] = AMPP_FUNCTION(QC2__clk0, S1L311, S1_D_iw[21], S1_D_iw[13], S1L301, F1_data_out, S1_W_stall);

--S1L2363 is std_1c20:inst|cpu:the_cpu|M_st_data[23]~COMBOUT at LC_X42_Y15_N1

--operation mode is normal

S1L2363 = AMPP_FUNCTION(S1L2321, S1_E_iw[4], S1L2361);

--S1L1030 is std_1c20:inst|cpu:the_cpu|E_src2[23]~1518 at LC_X41_Y13_N5

--operation mode is normal

S1L1030 = AMPP_FUNCTION(S1L1032, S1L1034, S1L2558);

--S1_E_extra_pc[9] is std_1c20:inst|cpu:the_cpu|E_extra_pc[9] at LC_X26_Y17_N9

--operation mode is normal

S1_E_extra_pc[9] = AMPP_FUNCTION(QC2__clk0, S1_D_pc_plus_one[9], S1_D_br_taken_waddr_partial[9], S1_D_iw[21], S1L287, F1_data_out, S1_W_stall);

--YC1_result[11] is std_1c20:inst|cpu:the_cpu|lpm_add_sub:Add8|alt_stratix_add_sub:stratix_adder|result[11] at LC_X36_Y15_N1

--operation mode is arithmetic

YC1_result[11] = AMPP_FUNCTION(S1L965, S1L864, YC1L29, YC1L31, YC1L32, S1_E_ctrl_alu_subtract);

--YC1L34 is std_1c20:inst|cpu:the_cpu|lpm_add_sub:Add8|alt_stratix_add_sub:stratix_adder|add_sub_cell[11]~COUT at LC_X36_Y15_N1

--operation mode is arithmetic

YC1L34 = AMPP_FUNCTION(S1L965, S1L864, YC1L31, S1_E_ctrl_alu_subtract);

--YC1L35 is std_1c20:inst|cpu:the_cpu|lpm_add_sub:Add8|alt_stratix_add_sub:stratix_adder|add_sub_cell[11]~COUTCOUT1_1313 at LC_X36_Y15_N1

--operation mode is arithmetic

YC1L35 = AMPP_FUNCTION(S1L965, S1L864, YC1L32, S1_E_ctrl_alu_subtract);

--S1L21 is std_1c20:inst|cpu:the_cpu|A_WE_StdLogicVector~14100 at LC_X33_Y17_N3

--operation mode is normal

S1L21 = AMPP_FUNCTION(S1_E_ctrl_dst_data_sel_pc_plus_one, S1_E_extra_pc[9], YC1_result[11]);

--S1_E_src2_imm[11] is std_1c20:inst|cpu:the_cpu|E_src2_imm[11] at LC_X37_Y15_N1

--operation mode is normal

S1_E_src2_imm[11] = AMPP_FUNCTION(QC2__clk0, S1_D_iw[2], S1L300, S1_D_iw[17], S1_D_iw[5], F1_data_out, S1_W_stall);

--S1_E_src2_prelim[11] is std_1c20:inst|cpu:the_cpu|E_src2_prelim[11] at LC_X38_Y15_N3

--operation mode is normal

S1_E_src2_prelim[11] = AMPP_FUNCTION(QC2__clk0, S1_W_wr_data[11], S1L668, S1L2425, DD1_q_b[11], F1_data_out, S1L664, S1_W_stall);

--S1_M_shift_rot_result[11] is std_1c20:inst|cpu:the_cpu|M_shift_rot_result[11] at LC_X37_Y17_N7

--operation mode is normal

S1_M_shift_rot_result[11] = AMPP_FUNCTION(QC2__clk0, S1_M_shift_rot_result[10], S1_M_shift_rot_result[12], S1L864, S1_M_ctrl_shift_rot_right, F1_data_out, !S1_M_shift_rot_stall);

--S1L2423 is std_1c20:inst|cpu:the_cpu|M_wr_data_unfiltered[11]~3677 at LC_X38_Y15_N4

--operation mode is normal

S1L2423 = AMPP_FUNCTION(S1_M_shift_rot_result[11], S1L2056Q);

--S1_av_ld_data_aligned_or_div[11] is std_1c20:inst|cpu:the_cpu|av_ld_data_aligned_or_div[11] at LC_X38_Y19_N9

--operation mode is normal

S1_av_ld_data_aligned_or_div[11] = AMPP_FUNCTION(QC2__clk0, S1L537, S1L622, S1_av_fill_bit, S1_M_ld_align_sh16, F1_data_out, S1L1186);

--S1L2424 is std_1c20:inst|cpu:the_cpu|M_wr_data_unfiltered[11]~3678 at LC_X38_Y15_N2

--operation mode is normal

S1L2424 = AMPP_FUNCTION(S1L2056Q, S1_av_ld_data_aligned_or_div[11], S1_av_ld_or_div_done, S1_M_alu_result[11]);

--S1L1153 is std_1c20:inst|cpu:the_cpu|E_sth_data[11]~476 at LC_X38_Y15_N5

--operation mode is normal

S1L1153 = AMPP_FUNCTION(S1_E_src2_hazard_M, S1_E_src2_prelim[11], S1L2424, S1L2423);

--S1L965 is std_1c20:inst|cpu:the_cpu|E_src2[11]~1519 at LC_X37_Y15_N8

--operation mode is normal

S1L965 = AMPP_FUNCTION(S1_E_ctrl_src2_is_imm, S1L1153, S1_E_src2_imm[11]);

--S1_E_src1_prelim[11] is std_1c20:inst|cpu:the_cpu|E_src1_prelim[11] at LC_X44_Y15_N3

--operation mode is normal

S1_E_src1_prelim[11] = AMPP_FUNCTION(QC2__clk0, S1_W_wr_data[11], CD1_q_b[11], S1L2425, S1_D_src1_hazard_W, F1_data_out, S1_D_src1_hazard_M, S1_W_stall);

--S1L864 is std_1c20:inst|cpu:the_cpu|E_src1[11]~2031 at LC_X38_Y15_N1

--operation mode is normal

S1L864 = AMPP_FUNCTION(S1_E_src1_prelim[11], S1L2423, S1L2424, S1L886Q);

--S1L801 is std_1c20:inst|cpu:the_cpu|E_logic_result[11]~15609 at LC_X34_Y16_N6

--operation mode is normal

S1L801 = AMPP_FUNCTION(S1_E_logic_op[1], S1L965, S1_E_logic_op[0], S1L864);

--S1_E_extra_pc[8] is std_1c20:inst|cpu:the_cpu|E_extra_pc[8] at LC_X26_Y17_N8

--operation mode is normal

S1_E_extra_pc[8] = AMPP_FUNCTION(QC2__clk0, S1_D_br_taken_waddr_partial[8], S1_D_pc_plus_one[8], S1_D_iw[21], S1L287, F1_data_out, S1_W_stall);

--YC1_result[10] is std_1c20:inst|cpu:the_cpu|lpm_add_sub:Add8|alt_stratix_add_sub:stratix_adder|result[10] at LC_X36_Y15_N0

--operation mode is arithmetic

YC1_result[10] = AMPP_FUNCTION(S1L964, S1L863, YC1L29, S1_E_ctrl_alu_subtract);

--YC1L31 is std_1c20:inst|cpu:the_cpu|lpm_add_sub:Add8|alt_stratix_add_sub:stratix_adder|add_sub_cell[10]~COUT at LC_X36_Y15_N0

--operation mode is arithmetic

YC1L31 = AMPP_FUNCTION(S1L964, S1L863, S1_E_ctrl_alu_subtract);

--YC1L32 is std_1c20:inst|cpu:the_cpu|lpm_add_sub:Add8|alt_stratix_add_sub:stratix_adder|add_sub_cell[10]~COUTCOUT1_1311 at LC_X36_Y15_N0

--operation mode is arithmetic

YC1L32 = AMPP_FUNCTION(S1L964, S1L863, S1_E_ctrl_alu_subtract);

--S1L22 is std_1c20:inst|cpu:the_cpu|A_WE_StdLogicVector~14101 at LC_X36_Y20_N4

--operation mode is normal

S1L22 = AMPP_FUNCTION(S1_E_extra_pc[8], S1_E_ctrl_dst_data_sel_pc_plus_one, YC1_result[10]);

--S1_E_src2_imm[10] is std_1c20:inst|cpu:the_cpu|E_src2_imm[10] at LC_X37_Y15_N7

--operation mode is normal

S1_E_src2_imm[10] = AMPP_FUNCTION(QC2__clk0, S1_D_iw[2], S1_D_iw[5], S1_D_iw[16], S1L300, F1_data_out, S1_W_stall);

--S1_E_src2_prelim[10] is std_1c20:inst|cpu:the_cpu|E_src2_prelim[10] at LC_X39_Y18_N6

--operation mode is normal

S1_E_src2_prelim[10] = AMPP_FUNCTION(QC2__clk0, S1_W_wr_data[10], S1L668, S1L2422, DD1_q_b[10], F1_data_out, S1L664, S1_W_stall);

--S1_M_shift_rot_result[10] is std_1c20:inst|cpu:the_cpu|M_shift_rot_result[10] at LC_X37_Y17_N2

--operation mode is normal

S1_M_shift_rot_result[10] = AMPP_FUNCTION(QC2__clk0, S1_M_shift_rot_result[11], S1_M_ctrl_shift_rot_right, S1L863, S1_M_shift_rot_result[9], F1_data_out, !S1_M_shift_rot_stall);

--S1L2420 is std_1c20:inst|cpu:the_cpu|M_wr_data_unfiltered[10]~3679 at LC_X38_Y18_N2

--operation mode is normal

S1L2420 = AMPP_FUNCTION(S1_M_shift_rot_result[10], S1L2056Q);

--S1L162 is std_1c20:inst|cpu:the_cpu|av_ld_data_aligned_or_div[10]~COMBOUT at LC_X38_Y19_N3

--operation mode is normal

S1L162 = AMPP_FUNCTION(S1L617, S1_M_ld_align_sh16, S1L533);

--S1_av_ld_data_aligned_or_div[10] is std_1c20:inst|cpu:the_cpu|av_ld_data_aligned_or_div[10] at LC_X38_Y19_N3

--operation mode is normal

S1_av_ld_data_aligned_or_div[10] = AMPP_FUNCTION(QC2__clk0, S1L617, S1_M_ld_align_sh16, S1_av_fill_bit, S1L533, F1_data_out, S1L1186);

--S1L2421 is std_1c20:inst|cpu:the_cpu|M_wr_data_unfiltered[10]~3680 at LC_X38_Y18_N4

--operation mode is normal

S1L2421 = AMPP_FUNCTION(S1L2056Q, S1L235Q, S1_av_ld_data_aligned_or_div[10], S1L1756Q);

--S1L1152 is std_1c20:inst|cpu:the_cpu|E_sth_data[10]~477 at LC_X38_Y18_N3

--operation mode is normal

S1L1152 = AMPP_FUNCTION(S1_E_src2_prelim[10], S1_E_src2_hazard_M, S1L2421, S1L2420);

--S1L964 is std_1c20:inst|cpu:the_cpu|E_src2[10]~1520 at LC_X37_Y15_N6

--operation mode is normal

S1L964 = AMPP_FUNCTION(S1_E_ctrl_src2_is_imm, S1_E_src2_imm[10], S1L1152);

--S1_E_src1_prelim[10] is std_1c20:inst|cpu:the_cpu|E_src1_prelim[10] at LC_X38_Y18_N6

--operation mode is normal

S1_E_src1_prelim[10] = AMPP_FUNCTION(QC2__clk0, CD1_q_b[10], S1_D_src1_hazard_W, S1L2422, S1_W_wr_data[10], F1_data_out, S1_D_src1_hazard_M, S1_W_stall);

--S1L863 is std_1c20:inst|cpu:the_cpu|E_src1[10]~2032 at LC_X38_Y18_N8

--operation mode is normal

S1L863 = AMPP_FUNCTION(S1L2420, S1L886Q, S1L2421, S1_E_src1_prelim[10]);

--S1L800 is std_1c20:inst|cpu:the_cpu|E_logic_result[10]~15610 at LC_X37_Y15_N3

--operation mode is normal

S1L800 = AMPP_FUNCTION(S1L964, S1_E_logic_op[0], S1_E_logic_op[1], S1L863);

--S1_E_extra_pc[7] is std_1c20:inst|cpu:the_cpu|E_extra_pc[7] at LC_X26_Y17_N3

--operation mode is normal

S1_E_extra_pc[7] = AMPP_FUNCTION(QC2__clk0, S1L287, S1_D_br_taken_waddr_partial[7], S1_D_iw[21], S1_D_pc_plus_one[7], F1_data_out, S1_W_stall);

--YC1_result[9] is std_1c20:inst|cpu:the_cpu|lpm_add_sub:Add8|alt_stratix_add_sub:stratix_adder|result[9] at LC_X36_Y16_N9

--operation mode is arithmetic

YC1_result[9] = AMPP_FUNCTION(S1L963, S1L862, YC1L15, YC1L26, YC1L27, S1_E_ctrl_alu_subtract);

--YC1L29 is std_1c20:inst|cpu:the_cpu|lpm_add_sub:Add8|alt_stratix_add_sub:stratix_adder|add_sub_cell[9]~COUT at LC_X36_Y16_N9

--operation mode is arithmetic

YC1L29 = AMPP_FUNCTION(S1L963, S1L862, YC1L15, YC1L26, YC1L27, S1_E_ctrl_alu_subtract);

--S1L23 is std_1c20:inst|cpu:the_cpu|A_WE_StdLogicVector~14102 at LC_X32_Y17_N1

--operation mode is normal

S1L23 = AMPP_FUNCTION(S1_E_ctrl_dst_data_sel_pc_plus_one, S1_E_extra_pc[7], YC1_result[9]);

--S1_E_src2_imm[9] is std_1c20:inst|cpu:the_cpu|E_src2_imm[9] at LC_X37_Y16_N9

--operation mode is normal

S1_E_src2_imm[9] = AMPP_FUNCTION(QC2__clk0, S1_D_iw[5], S1_D_iw[15], S1L300, S1_D_iw[2], F1_data_out, S1_W_stall);

--S1_E_src2_prelim[9] is std_1c20:inst|cpu:the_cpu|E_src2_prelim[9] at LC_X36_Y18_N3

--operation mode is normal

S1_E_src2_prelim[9] = AMPP_FUNCTION(QC2__clk0, S1_W_wr_data[9], DD1_q_b[9], S1L2419, S1L668, F1_data_out, S1L664, S1_W_stall);

--S1_M_shift_rot_result[9] is std_1c20:inst|cpu:the_cpu|M_shift_rot_result[9] at LC_X37_Y17_N9

--operation mode is normal

S1_M_shift_rot_result[9] = AMPP_FUNCTION(QC2__clk0, S1_M_shift_rot_result[10], S1_M_ctrl_shift_rot_right, S1L862, S1_M_shift_rot_result[8], F1_data_out, !S1_M_shift_rot_stall);

--S1L2417 is std_1c20:inst|cpu:the_cpu|M_wr_data_unfiltered[9]~3681 at LC_X36_Y18_N4

--operation mode is normal

S1L2417 = AMPP_FUNCTION(S1_M_shift_rot_result[9], S1L2056Q);

--S1L159 is std_1c20:inst|cpu:the_cpu|av_ld_data_aligned_or_div[9]~COMBOUT at LC_X40_Y19_N2

--operation mode is normal

S1L159 = AMPP_FUNCTION(S1L612, S1L529, S1_M_ld_align_sh16);

--S1_av_ld_data_aligned_or_div[9] is std_1c20:inst|cpu:the_cpu|av_ld_data_aligned_or_div[9] at LC_X40_Y19_N2

--operation mode is normal

S1_av_ld_data_aligned_or_div[9] = AMPP_FUNCTION(QC2__clk0, S1L612, S1L529, S1_av_fill_bit, S1_M_ld_align_sh16, F1_data_out, S1L1186);

--S1L2418 is std_1c20:inst|cpu:the_cpu|M_wr_data_unfiltered[9]~3682 at LC_X36_Y18_N1

--operation mode is normal

S1L2418 = AMPP_FUNCTION(S1L2056Q, S1L235Q, S1_av_ld_data_aligned_or_div[9], S1_M_alu_result[9]);

--S1L1151 is std_1c20:inst|cpu:the_cpu|E_sth_data[9]~478 at LC_X36_Y18_N5

--operation mode is normal

S1L1151 = AMPP_FUNCTION(S1L2418, S1_E_src2_prelim[9], S1_E_src2_hazard_M, S1L2417);

--S1L963 is std_1c20:inst|cpu:the_cpu|E_src2[9]~1521 at LC_X36_Y18_N6

--operation mode is normal

S1L963 = AMPP_FUNCTION(S1_E_src2_imm[9], S1_E_ctrl_src2_is_imm, S1L1151);

--S1_E_src1_prelim[9] is std_1c20:inst|cpu:the_cpu|E_src1_prelim[9] at LC_X44_Y17_N8

--operation mode is normal

S1_E_src1_prelim[9] = AMPP_FUNCTION(QC2__clk0, S1_W_wr_data[9], CD1_q_b[9], S1L2419, S1_D_src1_hazard_W, F1_data_out, S1_D_src1_hazard_M, S1_W_stall);

--S1L862 is std_1c20:inst|cpu:the_cpu|E_src1[9]~2033 at LC_X36_Y18_N7

--operation mode is normal

S1L862 = AMPP_FUNCTION(S1_E_src1_prelim[9], S1L886Q, S1L2417, S1L2418);

--S1L799 is std_1c20:inst|cpu:the_cpu|E_logic_result[9]~15611 at LC_X36_Y18_N8

--operation mode is normal

S1L799 = AMPP_FUNCTION(S1_E_logic_op[1], S1_E_logic_op[0], S1L862, S1L963);

--S1_E_extra_pc[6] is std_1c20:inst|cpu:the_cpu|E_extra_pc[6] at LC_X26_Y17_N4

--operation mode is normal

S1_E_extra_pc[6] = AMPP_FUNCTION(QC2__clk0, S1_D_iw[21], S1_D_pc_plus_one[6], S1_D_br_taken_waddr_partial[6], S1L287, F1_data_out, S1_W_stall);

--YC1_result[8] is std_1c20:inst|cpu:the_cpu|lpm_add_sub:Add8|alt_stratix_add_sub:stratix_adder|result[8] at LC_X36_Y16_N8

--operation mode is arithmetic

YC1_result[8] = AMPP_FUNCTION(S1L962, S1L861, YC1L15, YC1L23, YC1L24, S1_E_ctrl_alu_subtract);

--YC1L26 is std_1c20:inst|cpu:the_cpu|lpm_add_sub:Add8|alt_stratix_add_sub:stratix_adder|add_sub_cell[8]~COUT at LC_X36_Y16_N8

--operation mode is arithmetic

YC1L26 = AMPP_FUNCTION(S1L962, S1L861, YC1L23, S1_E_ctrl_alu_subtract);

--YC1L27 is std_1c20:inst|cpu:the_cpu|lpm_add_sub:Add8|alt_stratix_add_sub:stratix_adder|add_sub_cell[8]~COUTCOUT1_1309 at LC_X36_Y16_N8

--operation mode is arithmetic

YC1L27 = AMPP_FUNCTION(S1L962, S1L861, YC1L24, S1_E_ctrl_alu_subtract);

--S1L24 is std_1c20:inst|cpu:the_cpu|A_WE_StdLogicVector~14103 at LC_X33_Y18_N5

--operation mode is normal

S1L24 = AMPP_FUNCTION(S1_E_extra_pc[6], YC1_result[8], S1_E_ctrl_dst_data_sel_pc_plus_one);

--S1_E_src2_imm[8] is std_1c20:inst|cpu:the_cpu|E_src2_imm[8] at LC_X37_Y18_N3

--operation mode is normal

S1_E_src2_imm[8] = AMPP_FUNCTION(QC2__clk0, S1_D_iw[5], S1L300, S1_D_iw[2], S1_D_iw[14], F1_data_out, S1_W_stall);

--S1_E_src2_prelim[8] is std_1c20:inst|cpu:the_cpu|E_src2_prelim[8] at LC_X37_Y18_N5

--operation mode is normal

S1_E_src2_prelim[8] = AMPP_FUNCTION(QC2__clk0, S1_W_wr_data[8], S1L668, S1L2416, DD1_q_b[8], F1_data_out, S1L664, S1_W_stall);

--S1_M_shift_rot_result[8] is std_1c20:inst|cpu:the_cpu|M_shift_rot_result[8] at LC_X37_Y17_N1

--operation mode is normal

S1_M_shift_rot_result[8] = AMPP_FUNCTION(QC2__clk0, S1_M_shift_rot_result[9], S1_M_shift_rot_result[7], S1L861, S1_M_ctrl_shift_rot_right, F1_data_out, !S1_M_shift_rot_stall);

--S1L2414 is std_1c20:inst|cpu:the_cpu|M_wr_data_unfiltered[8]~3683 at LC_X37_Y18_N6

--operation mode is normal

S1L2414 = AMPP_FUNCTION(S1L2056Q, S1_M_shift_rot_result[8]);

--S1L156 is std_1c20:inst|cpu:the_cpu|av_ld_data_aligned_or_div[8]~COMBOUT at LC_X38_Y19_N7

--operation mode is normal

S1L156 = AMPP_FUNCTION(S1L521, S1L607, S1_M_ld_align_sh16);

--S1_av_ld_data_aligned_or_div[8] is std_1c20:inst|cpu:the_cpu|av_ld_data_aligned_or_div[8] at LC_X38_Y19_N7

--operation mode is normal

S1_av_ld_data_aligned_or_div[8] = AMPP_FUNCTION(QC2__clk0, S1L521, S1L607, S1_av_fill_bit, S1_M_ld_align_sh16, F1_data_out, S1L1186);

--S1L2415 is std_1c20:inst|cpu:the_cpu|M_wr_data_unfiltered[8]~3684 at LC_X37_Y18_N7

--operation mode is normal

S1L2415 = AMPP_FUNCTION(S1L2056Q, S1L235Q, S1_M_alu_result[8], S1_av_ld_data_aligned_or_div[8]);

--S1L1150 is std_1c20:inst|cpu:the_cpu|E_sth_data[8]~479 at LC_X37_Y18_N0

--operation mode is normal

S1L1150 = AMPP_FUNCTION(S1_E_src2_hazard_M, S1_E_src2_prelim[8], S1L2415, S1L2414);

--S1L962 is std_1c20:inst|cpu:the_cpu|E_src2[8]~1522 at LC_X37_Y18_N1

--operation mode is normal

S1L962 = AMPP_FUNCTION(S1_E_src2_imm[8], S1_E_ctrl_src2_is_imm, S1L1150);

--S1_E_src1_prelim[8] is std_1c20:inst|cpu:the_cpu|E_src1_prelim[8] at LC_X38_Y18_N0

--operation mode is normal

S1_E_src1_prelim[8] = AMPP_FUNCTION(QC2__clk0, S1_W_wr_data[8], S1_D_src1_hazard_W, S1L2416, CD1_q_b[8], F1_data_out, S1_D_src1_hazard_M, S1_W_stall);

--S1L861 is std_1c20:inst|cpu:the_cpu|E_src1[8]~2034 at LC_X37_Y18_N4

--operation mode is normal

S1L861 = AMPP_FUNCTION(S1L2414, S1_E_src1_prelim[8], S1L2415, S1L886Q);

--S1L798 is std_1c20:inst|cpu:the_cpu|E_logic_result[8]~15612 at LC_X35_Y18_N1

--operation mode is normal

S1L798 = AMPP_FUNCTION(S1L861, S1_E_logic_op[0], S1L962, S1_E_logic_op[1]);

--S1_E_extra_pc[5] is std_1c20:inst|cpu:the_cpu|E_extra_pc[5] at LC_X29_Y17_N6

--operation mode is normal

S1_E_extra_pc[5] = AMPP_FUNCTION(QC2__clk0, S1_D_pc_plus_one[5], S1L287, S1_D_iw[21], S1_D_br_taken_waddr_partial[5], F1_data_out, S1_W_stall);

--YC1_result[7] is std_1c20:inst|cpu:the_cpu|lpm_add_sub:Add8|alt_stratix_add_sub:stratix_adder|result[7] at LC_X36_Y16_N7

--operation mode is arithmetic

YC1_result[7] = AMPP_FUNCTION(S1L957, S1L860, YC1L15, YC1L20, YC1L21, S1_E_ctrl_alu_subtract);

--YC1L23 is std_1c20:inst|cpu:the_cpu|lpm_add_sub:Add8|alt_stratix_add_sub:stratix_adder|add_sub_cell[7]~COUT at LC_X36_Y16_N7

--operation mode is arithmetic

YC1L23 = AMPP_FUNCTION(S1L957, S1L860, YC1L20, S1_E_ctrl_alu_subtract);

--YC1L24 is std_1c20:inst|cpu:the_cpu|lpm_add_sub:Add8|alt_stratix_add_sub:stratix_adder|add_sub_cell[7]~COUTCOUT1_1307 at LC_X36_Y16_N7

--operation mode is arithmetic

YC1L24 = AMPP_FUNCTION(S1L957, S1L860, YC1L21, S1_E_ctrl_alu_subtract);

--S1L25 is std_1c20:inst|cpu:the_cpu|A_WE_StdLogicVector~14104 at LC_X35_Y17_N0

--operation mode is normal

S1L25 = AMPP_FUNCTION(S1_E_ctrl_dst_data_sel_pc_plus_one, S1_E_extra_pc[5], YC1_result[7]);

--S1_E_src1_prelim[7] is std_1c20:inst|cpu:the_cpu|E_src1_prelim[7] at LC_X43_Y16_N9

--operation mode is normal

S1_E_src1_prelim[7] = AMPP_FUNCTION(QC2__clk0, S1_W_wr_data[7], CD1_q_b[7], S1L2537, S1_D_src1_hazard_W, F1_data_out, S1_D_src1_hazard_M, S1_W_stall);

--S1_M_shift_rot_result[7] is std_1c20:inst|cpu:the_cpu|M_shift_rot_result[7] at LC_X37_Y17_N4

--operation mode is normal

S1_M_shift_rot_result[7] = AMPP_FUNCTION(QC2__clk0, S1_M_shift_rot_result[8], S1_M_shift_rot_result[6], S1L860, S1_M_ctrl_shift_rot_right, F1_data_out, !S1_M_shift_rot_stall);

--S1L2411 is std_1c20:inst|cpu:the_cpu|M_wr_data_unfiltered[7]~3685 at LC_X37_Y16_N4

--operation mode is normal

S1L2411 = AMPP_FUNCTION(S1L2056Q, S1_M_shift_rot_result[7]);

--S1_av_ld_data_aligned_or_div[7] is std_1c20:inst|cpu:the_cpu|av_ld_data_aligned_or_div[7] at LC_X40_Y20_N3

--operation mode is normal

S1_av_ld_data_aligned_or_div[7] = AMPP_FUNCTION(QC2__clk0, S1L516, S1L602, S1L178, S1_M_ld_align_sh16, F1_data_out, S1_M_ld_align_sh8);

--S1L2412 is std_1c20:inst|cpu:the_cpu|M_wr_data_unfiltered[7]~3686 at LC_X41_Y17_N3

--operation mode is normal

S1L2412 = AMPP_FUNCTION(S1L2062Q, S1L236Q, S1_M_alu_result[7], S1_av_ld_data_aligned_or_div[7]);

--S1L860 is std_1c20:inst|cpu:the_cpu|E_src1[7]~2035 at LC_X37_Y16_N5

--operation mode is normal

S1L860 = AMPP_FUNCTION(S1L886Q, S1L2412, S1_E_src1_prelim[7], S1L2411);

--S1_E_src2_imm[7] is std_1c20:inst|cpu:the_cpu|E_src2_imm[7] at LC_X41_Y17_N0

--operation mode is normal

S1_E_src2_imm[7] = AMPP_FUNCTION(QC2__clk0, S1L300, S1_D_iw[13], S1_D_iw[5], S1_D_iw[2], F1_data_out, S1_W_stall);

--S1L2323 is std_1c20:inst|cpu:the_cpu|M_st_data[15]~COMBOUT at LC_X42_Y18_N6

--operation mode is normal

S1L2323 = AMPP_FUNCTION(S1L1185, S1L1157, S1L2321);

--S1L957 is std_1c20:inst|cpu:the_cpu|E_src2[7]~1523 at LC_X41_Y17_N7

--operation mode is normal

S1L957 = AMPP_FUNCTION(S1L2537, S1L959, S1L961);

--S1L797 is std_1c20:inst|cpu:the_cpu|E_logic_result[7]~15613 at LC_X34_Y17_N7

--operation mode is normal

S1L797 = AMPP_FUNCTION(S1_E_logic_op[1], S1L957, S1L860, S1_E_logic_op[0]);

--S1_E_control_rd_data_without_mmu_regs[6] is std_1c20:inst|cpu:the_cpu|E_control_rd_data_without_mmu_regs[6] at LC_X35_Y19_N5

--operation mode is normal

S1_E_control_rd_data_without_mmu_regs[6] = AMPP_FUNCTION(QC2__clk0, S1L273, S1_M_ipending_reg[6], S1_D_iw[8], S1L2117Q, F1_data_out, S1_W_stall);

--S1_E_src1_prelim[6] is std_1c20:inst|cpu:the_cpu|E_src1_prelim[6] at LC_X42_Y17_N2

--operation mode is normal

S1_E_src1_prelim[6] = AMPP_FUNCTION(QC2__clk0, S1_W_wr_data[6], CD1_q_b[6], S1L2410, S1_D_src1_hazard_W, F1_data_out, S1_D_src1_hazard_M, S1_W_stall);

--S1_M_shift_rot_result[6] is std_1c20:inst|cpu:the_cpu|M_shift_rot_result[6] at LC_X37_Y17_N8

--operation mode is normal

S1_M_shift_rot_result[6] = AMPP_FUNCTION(QC2__clk0, S1_M_shift_rot_result[5], S1_M_shift_rot_result[7], S1L859, S1_M_ctrl_shift_rot_right, F1_data_out, !S1_M_shift_rot_stall);

--S1L2408 is std_1c20:inst|cpu:the_cpu|M_wr_data_unfiltered[6]~3687 at LC_X36_Y17_N6

--operation mode is normal

S1L2408 = AMPP_FUNCTION(S1L2056Q, S1_M_shift_rot_result[6]);

--S1_av_ld_data_aligned_or_div[6] is std_1c20:inst|cpu:the_cpu|av_ld_data_aligned_or_div[6] at LC_X40_Y20_N0

--operation mode is normal

S1_av_ld_data_aligned_or_div[6] = AMPP_FUNCTION(QC2__clk0, T1_cpu_data_master_readdata[6], S1L597, S1L174, S1_M_ld_align_sh16, F1_data_out, S1_M_ld_align_sh8);

--S1L2409 is std_1c20:inst|cpu:the_cpu|M_wr_data_unfiltered[6]~3688 at LC_X36_Y17_N1

--operation mode is normal

S1L2409 = AMPP_FUNCTION(S1_av_ld_data_aligned_or_div[6], S1_M_alu_result[6], S1L235Q, S1L2056Q);

--S1L859 is std_1c20:inst|cpu:the_cpu|E_src1[6]~2036 at LC_X36_Y17_N4

--operation mode is normal

S1L859 = AMPP_FUNCTION(S1L2409, S1_E_src1_prelim[6], S1L886Q, S1L2408);

--S1_E_src2_imm[6] is std_1c20:inst|cpu:the_cpu|E_src2_imm[6] at LC_X36_Y17_N9

--operation mode is normal

S1_E_src2_imm[6] = AMPP_FUNCTION(QC2__clk0, S1_D_iw[12], S1_D_iw[2], S1_D_iw[5], S1L300, F1_data_out, S1_W_stall);

--S1L2317 is std_1c20:inst|cpu:the_cpu|M_st_data[14]~COMBOUT at LC_X42_Y18_N3

--operation mode is normal

S1L2317 = AMPP_FUNCTION(S1L1156, S1L1185, S1L2314);

--S1L952 is std_1c20:inst|cpu:the_cpu|E_src2[6]~1524 at LC_X36_Y17_N3

--operation mode is normal

S1L952 = AMPP_FUNCTION(S1L956, S1L2534, S1L954);

--S1L26 is std_1c20:inst|cpu:the_cpu|A_WE_StdLogicVector~14105 at LC_X34_Y17_N2

--operation mode is normal

S1L26 = AMPP_FUNCTION(S1L859, S1_E_logic_op[0], S1L952, S1_E_logic_op[1]);

--S1_E_extra_pc[4] is std_1c20:inst|cpu:the_cpu|E_extra_pc[4] at LC_X31_Y18_N6

--operation mode is normal

S1_E_extra_pc[4] = AMPP_FUNCTION(QC2__clk0, S1_D_pc_plus_one[4], S1_D_iw[21], S1_D_br_taken_waddr_partial[4], S1L287, F1_data_out, S1_W_stall);

--YC1_result[6] is std_1c20:inst|cpu:the_cpu|lpm_add_sub:Add8|alt_stratix_add_sub:stratix_adder|result[6] at LC_X36_Y16_N6

--operation mode is arithmetic

YC1_result[6] = AMPP_FUNCTION(S1L952, S1L859, YC1L15, YC1L17, YC1L18, S1_E_ctrl_alu_subtract);

--YC1L20 is std_1c20:inst|cpu:the_cpu|lpm_add_sub:Add8|alt_stratix_add_sub:stratix_adder|add_sub_cell[6]~COUT at LC_X36_Y16_N6

--operation mode is arithmetic

YC1L20 = AMPP_FUNCTION(S1L952, S1L859, YC1L17, S1_E_ctrl_alu_subtract);

--YC1L21 is std_1c20:inst|cpu:the_cpu|lpm_add_sub:Add8|alt_stratix_add_sub:stratix_adder|add_sub_cell[6]~COUTCOUT1_1305 at LC_X36_Y16_N6

--operation mode is arithmetic

YC1L21 = AMPP_FUNCTION(S1L952, S1L859, YC1L18, S1_E_ctrl_alu_subtract);

--S1L27 is std_1c20:inst|cpu:the_cpu|A_WE_StdLogicVector~14106 at LC_X35_Y17_N6

--operation mode is normal

S1L27 = AMPP_FUNCTION(S1_E_extra_pc[4], S1_E_ctrl_dst_data_sel_pc_plus_one, YC1_result[6]);

--S1_M_alu_result[6] is std_1c20:inst|cpu:the_cpu|M_alu_result[6] at LC_X35_Y17_N7

--operation mode is normal

S1_M_alu_result[6] = AMPP_FUNCTION(QC2__clk0, S1L1746, S1L26, S1L1748, S1L27, F1_data_out, S1_W_stall);

--S1_E_ctrl_st is std_1c20:inst|cpu:the_cpu|E_ctrl_st at LC_X31_Y15_N5

--operation mode is normal

S1_E_ctrl_st = AMPP_FUNCTION(QC2__clk0, S1_D_iw[0], S1_D_iw[1], F1_data_out, S1_W_stall);

--S1_E_control_rd_data_without_mmu_regs[4] is std_1c20:inst|cpu:the_cpu|E_control_rd_data_without_mmu_regs[4] at LC_X36_Y19_N4

--operation mode is normal

S1_E_control_rd_data_without_mmu_regs[4] = AMPP_FUNCTION(QC2__clk0, S1L273, S1_D_iw[8], S1_M_ipending_reg[4], S1L2107Q, F1_data_out, S1_W_stall);

--S1_E_src1_prelim[4] is std_1c20:inst|cpu:the_cpu|E_src1_prelim[4] at LC_X44_Y16_N4

--operation mode is normal

S1_E_src1_prelim[4] = AMPP_FUNCTION(QC2__clk0, S1_W_wr_data[4], S1_D_src1_hazard_W, S1L2404, CD1_q_b[4], F1_data_out, S1_D_src1_hazard_M, S1_W_stall);

--S1_M_shift_rot_result[4] is std_1c20:inst|cpu:the_cpu|M_shift_rot_result[4] at LC_X40_Y18_N9

--operation mode is normal

S1_M_shift_rot_result[4] = AMPP_FUNCTION(QC2__clk0, S1_M_shift_rot_result[3], S1_M_shift_rot_result[5], S1L855, S1_M_ctrl_shift_rot_right, F1_data_out, !S1_M_shift_rot_stall);

--S1_av_ld_data_aligned_or_div[4] is std_1c20:inst|cpu:the_cpu|av_ld_data_aligned_or_div[4] at LC_X41_Y20_N4

--operation mode is normal

S1_av_ld_data_aligned_or_div[4] = AMPP_FUNCTION(QC2__clk0, T1_cpu_data_master_readdata[4], S1L587, S1L169, S1_M_ld_align_sh16, F1_data_out, S1_M_ld_align_sh8);

--S1L2403 is std_1c20:inst|cpu:the_cpu|M_wr_data_unfiltered[4]~3690 at LC_X41_Y16_N6

--operation mode is normal

S1L2403 = AMPP_FUNCTION(S1L236Q, S1L1738Q, S1L2062Q, S1_av_ld_data_aligned_or_div[4]);

--S1L855 is std_1c20:inst|cpu:the_cpu|E_src1[4]~2037 at LC_X40_Y16_N0

--operation mode is normal

S1L855 = AMPP_FUNCTION(S1L857, S1L886Q, S1_E_src1_prelim[4], S1L2403);

--S1_E_src2_imm[4] is std_1c20:inst|cpu:the_cpu|E_src2_imm[4] at LC_X41_Y16_N2

--operation mode is normal

S1_E_src2_imm[4] = AMPP_FUNCTION(QC2__clk0, S1L300, S1_D_iw[2], S1_D_iw[10], S1_D_iw[5], F1_data_out, S1_W_stall);

--S1L2305 is std_1c20:inst|cpu:the_cpu|M_st_data[12]~COMBOUT at LC_X42_Y15_N2

--operation mode is normal

S1L2305 = AMPP_FUNCTION(S1L1185, S1L1154, S1L2303);

--S1L942 is std_1c20:inst|cpu:the_cpu|E_src2[4]~1525 at LC_X41_Y16_N8

--operation mode is normal

S1L942 = AMPP_FUNCTION(S1L944, S1L946, S1L2528);

--S1L29 is std_1c20:inst|cpu:the_cpu|A_WE_StdLogicVector~14108 at LC_X35_Y16_N3

--operation mode is normal

S1L29 = AMPP_FUNCTION(S1_E_logic_op[1], S1_E_logic_op[0], S1L942, S1L855);

--S1_E_extra_pc[2] is std_1c20:inst|cpu:the_cpu|E_extra_pc[2] at LC_X29_Y17_N8

--operation mode is normal

S1_E_extra_pc[2] = AMPP_FUNCTION(QC2__clk0, S1_D_br_taken_waddr_partial[2], S1L287, S1_D_iw[21], S1_D_pc_plus_one[2], F1_data_out, S1_W_stall);

--YC1_result[4] is std_1c20:inst|cpu:the_cpu|lpm_add_sub:Add8|alt_stratix_add_sub:stratix_adder|result[4] at LC_X36_Y16_N4

--operation mode is arithmetic

YC1_result[4] = AMPP_FUNCTION(S1L942, S1L855, YC1L12, YC1L13, S1_E_ctrl_alu_subtract);

--YC1L15 is std_1c20:inst|cpu:the_cpu|lpm_add_sub:Add8|alt_stratix_add_sub:stratix_adder|add_sub_cell[4]~COUT at LC_X36_Y16_N4

--operation mode is arithmetic

YC1L15 = AMPP_FUNCTION(S1L942, S1L855, YC1L12, YC1L13, S1_E_ctrl_alu_subtract);

--S1L30 is std_1c20:inst|cpu:the_cpu|A_WE_StdLogicVector~14109 at LC_X36_Y20_N9

--operation mode is normal

S1L30 = AMPP_FUNCTION(S1_E_extra_pc[2], S1_E_ctrl_dst_data_sel_pc_plus_one, YC1_result[4]);

--S1L31 is std_1c20:inst|cpu:the_cpu|A_WE_StdLogicVector~14110 at LC_X36_Y20_N5

--operation mode is normal

S1L31 = AMPP_FUNCTION(S1_E_ctrl_dst_data_sel_logic_result, S1L30, S1L29);

--S1_M_alu_result[4] is std_1c20:inst|cpu:the_cpu|M_alu_result[4] at LC_X36_Y20_N2

--operation mode is normal

S1_M_alu_result[4] = AMPP_FUNCTION(QC2__clk0, S1L1734, S1L1736, S1L30, S1L29, F1_data_out, S1_W_stall);

--EB1L1 is std_1c20:inst|lcd_display_control_slave_arbitrator:the_lcd_display_control_slave|Add0~99 at LC_X35_Y21_N2

--operation mode is arithmetic

EB1L1 = EB1_lcd_display_control_slave_wait_counter[1] $ (!EB1L5);

--EB1L2 is std_1c20:inst|lcd_display_control_slave_arbitrator:the_lcd_display_control_slave|Add0~100 at LC_X35_Y21_N2

--operation mode is arithmetic

EB1L2_cout_0 = !EB1_lcd_display_control_slave_wait_counter[1] & (!EB1L5);

EB1L2 = CARRY(EB1L2_cout_0);

--EB1L3 is std_1c20:inst|lcd_display_control_slave_arbitrator:the_lcd_display_control_slave|Add0~100COUT1_309 at LC_X35_Y21_N2

--operation mode is arithmetic

EB1L3_cout_1 = !EB1_lcd_display_control_slave_wait_counter[1] & (!EB1L6);

EB1L3 = CARRY(EB1L3_cout_1);

--EB1L31 is std_1c20:inst|lcd_display_control_slave_arbitrator:the_lcd_display_control_slave|lcd_display_control_slave_wait_counter[1]~72 at LC_X35_Y22_N7

--operation mode is normal

EB1L31 = !EB1_lcd_display_control_slave_wait_counter[1] & !EB1_lcd_display_control_slave_wait_counter[2];

--EB1L21 is std_1c20:inst|lcd_display_control_slave_arbitrator:the_lcd_display_control_slave|Equal2~97 at LC_X35_Y22_N5

--operation mode is normal

EB1L21 = !EB1_lcd_display_control_slave_wait_counter[3] & !EB1_lcd_display_control_slave_wait_counter[0] & EB1L31 & EB1L37;

--EB1L25 is std_1c20:inst|lcd_display_control_slave_arbitrator:the_lcd_display_control_slave|lcd_display_control_slave_in_a_write_cycle~49 at LC_X36_Y21_N5

--operation mode is normal

EB1L25 = !EB1_d1_reasons_to_wait & !S1_M_alu_result[5] & S1_internal_d_write & JB1L3;

--EB1L5 is std_1c20:inst|lcd_display_control_slave_arbitrator:the_lcd_display_control_slave|Add0~102 at LC_X35_Y21_N1

--operation mode is arithmetic

EB1L5_cout_0 = EB1_lcd_display_control_slave_wait_counter[0];

EB1L5 = CARRY(EB1L5_cout_0);

--EB1L6 is std_1c20:inst|lcd_display_control_slave_arbitrator:the_lcd_display_control_slave|Add0~102COUT1_307 at LC_X35_Y21_N1

--operation mode is arithmetic

EB1L6_cout_1 = EB1_lcd_display_control_slave_wait_counter[0];

EB1L6 = CARRY(EB1L6_cout_1);

--EB1L23 is std_1c20:inst|lcd_display_control_slave_arbitrator:the_lcd_display_control_slave|lcd_display_control_slave_counter_load_value~1 at LC_X36_Y21_N8

--operation mode is normal

EB1L23 = S1_M_alu_result[5] # EB1_d1_reasons_to_wait # !JB1L3 # !S1_internal_d_read;

--EB1L7 is std_1c20:inst|lcd_display_control_slave_arbitrator:the_lcd_display_control_slave|Add0~103 at LC_X35_Y21_N4

--operation mode is arithmetic

EB1L7 = EB1_lcd_display_control_slave_wait_counter[3] $ !EB1L12;

--EB1L8 is std_1c20:inst|lcd_display_control_slave_arbitrator:the_lcd_display_control_slave|Add0~104 at LC_X35_Y21_N4

--operation mode is arithmetic

EB1L8 = EB1L9;

--EB1L11 is std_1c20:inst|lcd_display_control_slave_arbitrator:the_lcd_display_control_slave|Add0~105 at LC_X35_Y21_N3

--operation mode is arithmetic

EB1L11 = EB1_lcd_display_control_slave_wait_counter[2] $ (EB1L2);

--EB1L12 is std_1c20:inst|lcd_display_control_slave_arbitrator:the_lcd_display_control_slave|Add0~106 at LC_X35_Y21_N3

--operation mode is arithmetic

EB1L12_cout_0 = EB1_lcd_display_control_slave_wait_counter[2] # !EB1L2;

EB1L12 = CARRY(EB1L12_cout_0);

--EB1L13 is std_1c20:inst|lcd_display_control_slave_arbitrator:the_lcd_display_control_slave|Add0~106COUT1_311 at LC_X35_Y21_N3

--operation mode is arithmetic

EB1L13_cout_1 = EB1_lcd_display_control_slave_wait_counter[2] # !EB1L3;

EB1L13 = CARRY(EB1L13_cout_1);

--EB1L14 is std_1c20:inst|lcd_display_control_slave_arbitrator:the_lcd_display_control_slave|Add0~107 at LC_X35_Y21_N6

--operation mode is normal

EB1L14_carry_eqn = (!EB1L8 & EB1L16) # (EB1L8 & EB1L17);

EB1L14 = EB1_lcd_display_control_slave_wait_counter[5] $ (!EB1L14_carry_eqn);

--EB1L15 is std_1c20:inst|lcd_display_control_slave_arbitrator:the_lcd_display_control_slave|Add0~109 at LC_X35_Y21_N5

--operation mode is arithmetic

EB1L15_carry_eqn = (!EB1L8 & GND) # (EB1L8 & VCC);

EB1L15 = EB1_lcd_display_control_slave_wait_counter[4] $ EB1L15_carry_eqn;

--EB1L16 is std_1c20:inst|lcd_display_control_slave_arbitrator:the_lcd_display_control_slave|Add0~110 at LC_X35_Y21_N5

--operation mode is arithmetic

EB1L16_cout_0 = EB1_lcd_display_control_slave_wait_counter[4] # !EB1L8;

EB1L16 = CARRY(EB1L16_cout_0);

--EB1L17 is std_1c20:inst|lcd_display_control_slave_arbitrator:the_lcd_display_control_slave|Add0~110COUT1_313 at LC_X35_Y21_N5

--operation mode is arithmetic

EB1L17_cout_1 = EB1_lcd_display_control_slave_wait_counter[4] # !EB1L8;

EB1L17 = CARRY(EB1L17_cout_1);

--S1_E_control_rd_data_without_mmu_regs[5] is std_1c20:inst|cpu:the_cpu|E_control_rd_data_without_mmu_regs[5] at LC_X35_Y19_N9

--operation mode is normal

S1_E_control_rd_data_without_mmu_regs[5] = AMPP_FUNCTION(QC2__clk0, S1_D_iw[8], S1_M_ipending_reg[5], S1L2110Q, S1L273, F1_data_out, S1_W_stall);

--S1_E_src1_prelim[5] is std_1c20:inst|cpu:the_cpu|E_src1_prelim[5] at LC_X44_Y17_N9

--operation mode is normal

S1_E_src1_prelim[5] = AMPP_FUNCTION(QC2__clk0, S1_W_wr_data[5], CD1_q_b[5], S1L2407, S1_D_src1_hazard_W, F1_data_out, S1_D_src1_hazard_M, S1_W_stall);

--S1_M_shift_rot_result[5] is std_1c20:inst|cpu:the_cpu|M_shift_rot_result[5] at LC_X40_Y18_N1

--operation mode is normal

S1_M_shift_rot_result[5] = AMPP_FUNCTION(QC2__clk0, S1_M_shift_rot_result[4], S1_M_shift_rot_result[6], S1L858, S1_M_ctrl_shift_rot_right, F1_data_out, !S1_M_shift_rot_stall);

--S1L2405 is std_1c20:inst|cpu:the_cpu|M_wr_data_unfiltered[5]~3691 at LC_X40_Y18_N3

--operation mode is normal

S1L2405 = AMPP_FUNCTION(S1L2062Q, S1_M_shift_rot_result[5]);

--S1_av_ld_data_aligned_or_div[5] is std_1c20:inst|cpu:the_cpu|av_ld_data_aligned_or_div[5] at LC_X39_Y19_N9

--operation mode is normal

S1_av_ld_data_aligned_or_div[5] = AMPP_FUNCTION(QC2__clk0, T1_cpu_data_master_readdata[5], S1L592, S1L172, S1_M_ld_align_sh16, F1_data_out, S1_M_ld_align_sh8);

--S1L2406 is std_1c20:inst|cpu:the_cpu|M_wr_data_unfiltered[5]~3692 at LC_X39_Y18_N8

--operation mode is normal

S1L2406 = AMPP_FUNCTION(S1_av_ld_data_aligned_or_div[5], S1L2061Q, S1L235Q, S1L1743Q);

--S1L858 is std_1c20:inst|cpu:the_cpu|E_src1[5]~2038 at LC_X40_Y18_N4

--operation mode is normal

S1L858 = AMPP_FUNCTION(S1L2406, S1L886Q, S1_E_src1_prelim[5], S1L2405);

--S1_E_src2_imm[5] is std_1c20:inst|cpu:the_cpu|E_src2_imm[5] at LC_X37_Y18_N9

--operation mode is normal

S1_E_src2_imm[5] = AMPP_FUNCTION(QC2__clk0, S1_D_iw[5], S1L300, S1_D_iw[11], S1_D_iw[2], F1_data_out, S1_W_stall);

--S1L2311 is std_1c20:inst|cpu:the_cpu|M_st_data[13]~COMBOUT at LC_X40_Y18_N8

--operation mode is normal

S1L2311 = AMPP_FUNCTION(S1L2309, S1L1185, S1L1155);

--S1L947 is std_1c20:inst|cpu:the_cpu|E_src2[5]~1526 at LC_X39_Y18_N2

--operation mode is normal

S1L947 = AMPP_FUNCTION(S1L949, S1L951, S1L2531);

--S1L32 is std_1c20:inst|cpu:the_cpu|A_WE_StdLogicVector~14111 at LC_X35_Y18_N8

--operation mode is normal

S1L32 = AMPP_FUNCTION(S1_E_logic_op[1], S1_E_logic_op[0], S1L947, S1L858);

--S1_E_extra_pc[3] is std_1c20:inst|cpu:the_cpu|E_extra_pc[3] at LC_X31_Y18_N1

--operation mode is normal

S1_E_extra_pc[3] = AMPP_FUNCTION(QC2__clk0, S1_D_br_taken_waddr_partial[3], S1_D_iw[21], S1_D_pc_plus_one[3], S1L287, F1_data_out, S1_W_stall);

--YC1_result[5] is std_1c20:inst|cpu:the_cpu|lpm_add_sub:Add8|alt_stratix_add_sub:stratix_adder|result[5] at LC_X36_Y16_N5

--operation mode is arithmetic

YC1_result[5] = AMPP_FUNCTION(S1L947, S1L858, YC1L15, S1_E_ctrl_alu_subtract);

--YC1L17 is std_1c20:inst|cpu:the_cpu|lpm_add_sub:Add8|alt_stratix_add_sub:stratix_adder|add_sub_cell[5]~COUT at LC_X36_Y16_N5

--operation mode is arithmetic

YC1L17 = AMPP_FUNCTION(S1L947, S1L858, S1_E_ctrl_alu_subtract);

--YC1L18 is std_1c20:inst|cpu:the_cpu|lpm_add_sub:Add8|alt_stratix_add_sub:stratix_adder|add_sub_cell[5]~COUTCOUT1_1303 at LC_X36_Y16_N5

--operation mode is arithmetic

YC1L18 = AMPP_FUNCTION(S1L947, S1L858, S1_E_ctrl_alu_subtract);

--S1L33 is std_1c20:inst|cpu:the_cpu|A_WE_StdLogicVector~14112 at LC_X34_Y19_N7

--operation mode is normal

S1L33 = AMPP_FUNCTION(S1_E_extra_pc[3], S1_E_ctrl_dst_data_sel_pc_plus_one, YC1_result[5]);

--S1_M_alu_result[5] is std_1c20:inst|cpu:the_cpu|M_alu_result[5] at LC_X34_Y19_N2

--operation mode is normal

S1_M_alu_result[5] = AMPP_FUNCTION(QC2__clk0, S1L32, S1L2114, S1L33, S1L2112, F1_data_out, S1_W_stall);

--YC1_result[0] is std_1c20:inst|cpu:the_cpu|lpm_add_sub:Add8|alt_stratix_add_sub:stratix_adder|result[0] at LC_X36_Y16_N0

--operation mode is arithmetic

YC1_result[0] = AMPP_FUNCTION(S1L922, S1L851);

--YC1L3 is std_1c20:inst|cpu:the_cpu|lpm_add_sub:Add8|alt_stratix_add_sub:stratix_adder|add_sub_cell[0]~COUT at LC_X36_Y16_N0

--operation mode is arithmetic

YC1L3 = AMPP_FUNCTION(S1L922, S1L851, S1_E_ctrl_alu_subtract);

--YC1L4 is std_1c20:inst|cpu:the_cpu|lpm_add_sub:Add8|alt_stratix_add_sub:stratix_adder|add_sub_cell[0]~COUTCOUT1_1295 at LC_X36_Y16_N0

--operation mode is arithmetic

YC1L4 = AMPP_FUNCTION(S1L922, S1L851, S1_E_ctrl_alu_subtract);

--YC1_result[1] is std_1c20:inst|cpu:the_cpu|lpm_add_sub:Add8|alt_stratix_add_sub:stratix_adder|result[1] at LC_X36_Y16_N1

--operation mode is arithmetic

YC1_result[1] = AMPP_FUNCTION(S1L927, S1L852, YC1L3, YC1L4, S1_E_ctrl_alu_subtract);

--YC1L6 is std_1c20:inst|cpu:the_cpu|lpm_add_sub:Add8|alt_stratix_add_sub:stratix_adder|add_sub_cell[1]~COUT at LC_X36_Y16_N1

--operation mode is arithmetic

YC1L6 = AMPP_FUNCTION(S1L927, S1L852, YC1L3, S1_E_ctrl_alu_subtract);

--YC1L7 is std_1c20:inst|cpu:the_cpu|lpm_add_sub:Add8|alt_stratix_add_sub:stratix_adder|add_sub_cell[1]~COUTCOUT1_1297 at LC_X36_Y16_N1

--operation mode is arithmetic

YC1L7 = AMPP_FUNCTION(S1L927, S1L852, YC1L4, S1_E_ctrl_alu_subtract);

--Y1L1001 is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|p1_ext_ram_bus_address[22]~3406 at LC_X29_Y23_N9

--operation mode is normal

Y1L1001 = !Y1L742 & (!Y1L28 & !Y1L31 # !Y1L112);

--Y1L95 is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|cpu_data_master_granted_ext_flash_s1~57 at LC_X29_Y27_N8

--operation mode is normal

Y1L95 = Y1L100 & (Y1L34 # Y1L37);

--Y1L775Q is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_avalon_slave_saved_chosen_master_vector[3]~657 at LC_X29_Y27_N8

--operation mode is normal

Y1L775Q = DFFEAS(Y1L95, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--S1_ic_fill_tag[10] is std_1c20:inst|cpu:the_cpu|ic_fill_tag[10] at LC_X25_Y23_N1

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

S1_ic_fill_tag[10] = AMPP_FUNCTION(QC2__clk0, S1_D_pc[20], F1_data_out, GND, S1_D_ic_fill_starting);

--S1_ic_fill_tag[9] is std_1c20:inst|cpu:the_cpu|ic_fill_tag[9] at LC_X26_Y23_N3

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

S1_ic_fill_tag[9] = AMPP_FUNCTION(QC2__clk0, S1_D_pc[19], F1_data_out, GND, S1_D_ic_fill_starting);

--Y1L1 is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|A_WE_StdLogicVector~4277 at LC_X29_Y27_N9

--operation mode is normal

Y1L1 = S1L1782Q & !Y1L742 & Y1L95;

--Y1L2 is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|A_WE_StdLogicVector~4278 at LC_X29_Y23_N2

--operation mode is normal

Y1L2 = !Y1L742 & (Y1L905 # !Y1L770 & Y1L916);

--Y1L1003 is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|p1_ext_ram_bus_address[22]~3412 at LC_X25_Y23_N5

--operation mode is normal

Y1L1003 = !Y1L905 & (Y1L14 # !Y1L916);

--S1_ic_fill_ap_offset[2] is std_1c20:inst|cpu:the_cpu|ic_fill_ap_offset[2] at LC_X26_Y21_N3

--operation mode is normal

S1_ic_fill_ap_offset[2] = AMPP_FUNCTION(QC2__clk0, S1_D_ic_fill_starting, S1_D_pc[2], S1L124, S1_ic_fill_ap_offset[2], F1_data_out, S1_ic_fill_req_accepted);

--S1_ic_fill_ap_offset[1] is std_1c20:inst|cpu:the_cpu|ic_fill_ap_offset[1] at LC_X26_Y22_N9

--operation mode is normal

S1_ic_fill_ap_offset[1] = AMPP_FUNCTION(QC2__clk0, S1_ic_fill_ap_offset[1], S1_D_ic_fill_starting, S1L125, S1_D_pc[1], F1_data_out, S1_ic_fill_req_accepted);

--S1_ic_fill_ap_offset[0] is std_1c20:inst|cpu:the_cpu|ic_fill_ap_offset[0] at LC_X26_Y21_N7

--operation mode is normal

S1_ic_fill_ap_offset[0] = AMPP_FUNCTION(QC2__clk0, S1_ic_fill_ap_offset[0], S1_D_pc[0], S1L1531, S1_D_ic_fill_starting, F1_data_out, S1_ic_fill_req_accepted);

--Y1L996 is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|p1_ext_ram_bus_address[0]~3431 at LC_X29_Y23_N0

--operation mode is normal

Y1L996 = Y1L736 # !Y1L742 & Y1L916 & Y1L998;

--U1_internal_cpu_instruction_master_dbs_address[1] is std_1c20:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|internal_cpu_instruction_master_dbs_address[1] at LC_X27_Y24_N7

--operation mode is normal

U1_internal_cpu_instruction_master_dbs_address[1]_lut_out = U1_internal_cpu_instruction_master_dbs_address[1] $ (U1_internal_cpu_instruction_master_dbs_address[0] & U1L224 & Y1L770);

U1_internal_cpu_instruction_master_dbs_address[1] = DFFEAS(U1_internal_cpu_instruction_master_dbs_address[1]_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--Y1L999 is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|p1_ext_ram_bus_address[1]~3432 at LC_X29_Y23_N6

--operation mode is normal

Y1L999 = Y1L905 & T1_internal_cpu_data_master_dbs_address[1] # !Y1L905 & (U1_internal_cpu_instruction_master_dbs_address[1] & Y1L770);

--U1_internal_cpu_instruction_master_dbs_address[0] is std_1c20:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|internal_cpu_instruction_master_dbs_address[0] at LC_X28_Y27_N8

--operation mode is normal

U1_internal_cpu_instruction_master_dbs_address[0]_lut_out = U1_internal_cpu_instruction_master_dbs_address[0] $ (Y1L653Q & Y1L118 & Y1L770);

U1_internal_cpu_instruction_master_dbs_address[0] = DFFEAS(U1_internal_cpu_instruction_master_dbs_address[0]_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--Y1L997 is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|p1_ext_ram_bus_address[0]~3434 at LC_X28_Y23_N7

--operation mode is normal

Y1L997 = Y1L905 & (T1_internal_cpu_data_master_dbs_address[0]) # !Y1L905 & U1_internal_cpu_instruction_master_dbs_address[0] & (Y1L770);

--ZE1L42 is std_1c20:inst|uart1:the_uart1|uart1_tx:the_uart1_tx|tx_wr_strobe_onset~34 at LC_X42_Y25_N5

--operation mode is normal

ZE1L42 = S1_M_alu_result[6] & !S1_M_alu_result[7] & UB1L5 & UB1L6;

--PB1L19 is std_1c20:inst|seven_seg_pio:the_seven_seg_pio|process0~29 at LC_X45_Y22_N0

--operation mode is normal

PB1L19 = !S1L1726Q & !S1_M_alu_result[3] & (!S1_internal_d_write # !T1_internal_cpu_data_master_waitrequest);

--PB1L20 is std_1c20:inst|seven_seg_pio:the_seven_seg_pio|process0~30 at LC_X47_Y24_N3

--operation mode is normal

PB1L20 = S1L1738Q & S1_internal_d_write & (PB1L19);

--FB1L10 is std_1c20:inst|led_pio:the_led_pio|process0~1 at LC_X47_Y24_N4

--operation mode is normal

FB1L10 = S1L2149Q & ZE1L42 & S1L1743Q & PB1L20;

--PB1L21 is std_1c20:inst|seven_seg_pio:the_seven_seg_pio|process0~31 at LC_X42_Y25_N2

--operation mode is normal

PB1L21 = S1L1743Q # !S1_internal_d_write # !PB1L19 # !S1L1738Q;

--PB1L18 is std_1c20:inst|seven_seg_pio:the_seven_seg_pio|process0~1 at LC_X36_Y25_N2

--operation mode is normal

PB1L18 = UB1L5 & UB1L6 & UB1L7 & !PB1L21;

--S1L2286 is std_1c20:inst|cpu:the_cpu|M_st_data[9]~COMBOUT at LC_X42_Y18_N7

--operation mode is normal

S1L2286 = AMPP_FUNCTION(S1L1185, S1L1151, S1L2283);

--S1L2279 is std_1c20:inst|cpu:the_cpu|M_st_data[8]~COMBOUT at LC_X42_Y15_N4

--operation mode is normal

S1L2279 = AMPP_FUNCTION(S1L1185, S1L2277, S1L1150);

--KB1L706 is std_1c20:inst|sdram:the_sdram|Mux104~1606 at LC_X13_Y20_N0

--operation mode is normal

KB1L706 = KB1_m_state[0] & !KB1_m_state[3] & !KB1_m_state[6] & !KB1_m_state[4];

--KB1_i_addr[0] is std_1c20:inst|sdram:the_sdram|i_addr[0] at LC_X11_Y22_N8

--operation mode is normal

KB1_i_addr[0]_lut_out = KB1_i_state[2] & KB1_i_state[1] & KB1_i_state[0];

KB1_i_addr[0] = DFFEAS(KB1_i_addr[0]_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--KB1L707 is std_1c20:inst|sdram:the_sdram|Mux104~1607 at LC_X11_Y19_N8

--operation mode is normal

KB1L707 = KB1_init_done & (KB1L217Q) # !KB1_init_done & (KB1L932 & !KB1_i_addr[0] # !KB1L932 & (KB1L217Q));

--KB1L708 is std_1c20:inst|sdram:the_sdram|Mux104~1608 at LC_X11_Y19_N0

--operation mode is normal

KB1L708 = KB1L217Q & (KB1_m_state[4] $ !KB1_m_state[3]);

--KB1L709 is std_1c20:inst|sdram:the_sdram|Mux104~1609 at LC_X11_Y19_N9

--operation mode is normal

KB1L709 = KB1_m_state[6] & (!KB1_m_state[0]) # !KB1_m_state[6] & (KB1_m_state[0] & KB1L708 # !KB1_m_state[0] & (KB1L707));

--KB1L710 is std_1c20:inst|sdram:the_sdram|Mux104~1610 at LC_X11_Y20_N8

--operation mode is normal

KB1L710 = KB1_m_state[6] & (KB1L217Q # KB1L857 & !KB1L709) # !KB1_m_state[6] & (KB1L709);

--KB1L711 is std_1c20:inst|sdram:the_sdram|Mux104~1611 at LC_X11_Y20_N3

--operation mode is normal

KB1L711 = KB1_m_state[1] & KB1_active_addr[20] & (KB1L706) # !KB1_m_state[1] & (KB1L710);

--KB1L712 is std_1c20:inst|sdram:the_sdram|Mux104~1612 at LC_X11_Y20_N2

--operation mode is normal

KB1L712 = KB1_m_state[1] & (!KB1L706);

--KB1L713 is std_1c20:inst|sdram:the_sdram|Mux104~1613 at LC_X14_Y22_N9

--operation mode is normal

KB1L713 = KB1_m_state[8] # KB1_m_state[2] # KB1_m_state[5] # KB1_m_state[7];

--KB1L714 is std_1c20:inst|sdram:the_sdram|Mux105~1397 at LC_X11_Y19_N1

--operation mode is normal

KB1L714 = KB1_init_done & (KB1L213Q) # !KB1_init_done & (KB1L932 & !KB1_i_addr[0] # !KB1L932 & (KB1L213Q));

--KB1L715 is std_1c20:inst|sdram:the_sdram|Mux105~1398 at LC_X11_Y19_N3

--operation mode is normal

KB1L715 = KB1L213Q & (KB1_m_state[3] $ !KB1_m_state[4]);

--KB1L716 is std_1c20:inst|sdram:the_sdram|Mux105~1399 at LC_X11_Y19_N2

--operation mode is normal

KB1L716 = KB1_m_state[6] & (!KB1_m_state[0]) # !KB1_m_state[6] & (KB1_m_state[0] & KB1L715 # !KB1_m_state[0] & (KB1L714));

--KB1L717 is std_1c20:inst|sdram:the_sdram|Mux105~1400 at LC_X11_Y20_N9

--operation mode is normal

KB1L717 = KB1_m_state[6] & (KB1L213Q # KB1L857 & !KB1L716) # !KB1_m_state[6] & (KB1L716);

--KB1L718 is std_1c20:inst|sdram:the_sdram|Mux105~1401 at LC_X11_Y20_N5

--operation mode is normal

KB1L718 = KB1_m_state[1] & KB1_active_addr[19] & (KB1L706) # !KB1_m_state[1] & (KB1L717);

--KB1L719 is std_1c20:inst|sdram:the_sdram|Mux106~1397 at LC_X13_Y20_N4

--operation mode is normal

KB1L719 = KB1L932 & (KB1_init_done & KB1L209Q # !KB1_init_done & (!KB1_i_addr[0])) # !KB1L932 & KB1L209Q;

--KB1L720 is std_1c20:inst|sdram:the_sdram|Mux106~1398 at LC_X13_Y20_N2

--operation mode is normal

KB1L720 = KB1L209Q & (KB1_m_state[3] $ !KB1_m_state[4]);

--KB1L721 is std_1c20:inst|sdram:the_sdram|Mux106~1399 at LC_X13_Y20_N5

--operation mode is normal

KB1L721 = KB1_m_state[0] & KB1L720 & !KB1_m_state[6] # !KB1_m_state[0] & (KB1_m_state[6] # KB1L719);

--KB1L722 is std_1c20:inst|sdram:the_sdram|Mux106~1400 at LC_X13_Y20_N6

--operation mode is normal

KB1L722 = KB1_m_state[6] & (KB1L209Q # KB1L932 & !KB1L721) # !KB1_m_state[6] & (KB1L721);

--KB1L723 is std_1c20:inst|sdram:the_sdram|Mux106~1401 at LC_X13_Y20_N7

--operation mode is normal

KB1L723 = KB1_m_state[1] & KB1L706 & KB1_active_addr[18] # !KB1_m_state[1] & (KB1L722);

--KB1L724 is std_1c20:inst|sdram:the_sdram|Mux107~1397 at LC_X11_Y19_N5

--operation mode is normal

KB1L724 = KB1_init_done & (KB1L205Q) # !KB1_init_done & (KB1L932 & !KB1_i_addr[0] # !KB1L932 & (KB1L205Q));

--KB1L725 is std_1c20:inst|sdram:the_sdram|Mux107~1398 at LC_X11_Y19_N4

--operation mode is normal

KB1L725 = KB1L205Q & (KB1_m_state[4] $ !KB1_m_state[3]);

--KB1L726 is std_1c20:inst|sdram:the_sdram|Mux107~1399 at LC_X11_Y19_N6

--operation mode is normal

KB1L726 = KB1_m_state[6] & (!KB1_m_state[0]) # !KB1_m_state[6] & (KB1_m_state[0] & KB1L725 # !KB1_m_state[0] & (KB1L724));

--KB1L727 is std_1c20:inst|sdram:the_sdram|Mux107~1400 at LC_X11_Y20_N4

--operation mode is normal

KB1L727 = KB1_m_state[6] & (KB1L205Q # !KB1L726 & KB1L857) # !KB1_m_state[6] & (KB1L726);

--KB1L728 is std_1c20:inst|sdram:the_sdram|Mux107~1401 at LC_X11_Y20_N0

--operation mode is normal

KB1L728 = KB1_m_state[1] & KB1_active_addr[17] & (KB1L706) # !KB1_m_state[1] & (KB1L727);

--KB1L729 is std_1c20:inst|sdram:the_sdram|Mux108~1491 at LC_X14_Y22_N2

--operation mode is normal

KB1L729 = !KB1_m_state[1] & !KB1_m_state[4] & KB1_m_state[0] & !KB1_m_state[3];

--KB1L730 is std_1c20:inst|sdram:the_sdram|Mux108~1492 at LC_X15_Y21_N5

--operation mode is normal

KB1L730 = KB1_m_state[3] & (KB1L200Q) # !KB1_m_state[3] & (KB1_m_state[4] & (KB1L200Q) # !KB1_m_state[4] & KB1_active_addr[16]);

--KB1L731 is std_1c20:inst|sdram:the_sdram|Mux108~1493 at LC_X14_Y21_N8

--operation mode is normal

KB1L731 = KB1_init_done & KB1L200Q # !KB1_init_done & (KB1L773 & (!KB1_i_addr[0]) # !KB1L773 & KB1L200Q);

--TE1L197 is std_1c20:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|rd_data[43]~495 at LC_X22_Y19_N1

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

TE1_entry_1[43]_qfbk = TE1_entry_1[43];

TE1L197 = TE1_rd_address & TE1_entry_1[43]_qfbk # !TE1_rd_address & (TE1_entry_0[43]);

--TE1_entry_1[43] is std_1c20:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_1[43] at LC_X22_Y19_N1

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

TE1_entry_1[43] = DFFEAS(TE1L197, GLOBAL(QC2__clk0), VCC, , TE1L148, NB1L46, , , VCC);

--KB1_active_addr[7] is std_1c20:inst|sdram:the_sdram|active_addr[7] at LC_X15_Y20_N5

--operation mode is normal

KB1_active_addr[7]_lut_out = KB1L14 & (KB1L12 & (TE1L197) # !KB1L12 & KB1_active_addr[7]) # !KB1L14 & KB1_active_addr[7];

KB1_active_addr[7] = DFFEAS(KB1_active_addr[7]_lut_out, GLOBAL(QC2__clk0), VCC, , , , , , );

--KB1L735 is std_1c20:inst|sdram:the_sdram|Mux108~1497 at LC_X14_Y21_N5

--operation mode is normal

KB1L735 = KB1L754 & (KB1L758 # KB1L752 & KB1L756) # !KB1L754 & (!KB1L752);

--KB1L759 is std_1c20:inst|sdram:the_sdram|Mux109~1364 at LC_X12_Y20_N8

--operation mode is normal

KB1L759 = KB1L713 & KB1L195Q # !KB1L713 & KB1_m_state[6] & (KB1L195Q # KB1L729);

--TE1L196 is std_1c20:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|rd_data[42]~496 at LC_X22_Y23_N5

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

TE1_entry_1[42]_qfbk = TE1_entry_1[42];

TE1L196 = TE1_rd_address & (TE1_entry_1[42]_qfbk) # !TE1_rd_address & TE1_entry_0[42];

--TE1_entry_1[42] is std_1c20:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_1[42] at LC_X22_Y23_N5

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

TE1_entry_1[42] = DFFEAS(TE1L196, GLOBAL(QC2__clk0), VCC, , TE1L148, NB1L45, , , VCC);

--KB1_active_addr[6] is std_1c20:inst|sdram:the_sdram|active_addr[6] at LC_X16_Y21_N7

--operation mode is normal

KB1_active_addr[6]_lut_out = KB1L14 & (KB1L12 & (TE1L196) # !KB1L12 & KB1_active_addr[6]) # !KB1L14 & KB1_active_addr[6];

KB1_active_addr[6] = DFFEAS(KB1_active_addr[6]_lut_out, GLOBAL(QC2__clk0), VCC, , , , , , );

--KB1L764 is std_1c20:inst|sdram:the_sdram|Mux109~1369 at LC_X16_Y21_N0

--operation mode is normal

KB1L764 = KB1L785 & KB1_active_addr[15] & KB1L783 # !KB1L785 & (KB1L783 # !KB1L775);

--KB1L786 is std_1c20:inst|sdram:the_sdram|Mux110~1388 at LC_X12_Y20_N4

--operation mode is normal

KB1L786 = KB1L713 & (KB1L190Q) # !KB1L713 & KB1_m_state[6] & (KB1L190Q # KB1L729);

--TE1L195 is std_1c20:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|rd_data[41]~497 at LC_X22_Y19_N4

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

TE1_entry_1[41]_qfbk = TE1_entry_1[41];

TE1L195 = TE1_rd_address & TE1_entry_1[41]_qfbk # !TE1_rd_address & (TE1_entry_0[41]);

--TE1_entry_1[41] is std_1c20:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_1[41] at LC_X22_Y19_N4

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

TE1_entry_1[41] = DFFEAS(TE1L195, GLOBAL(QC2__clk0), VCC, , TE1L148, NB1L44, , , VCC);

--KB1_active_addr[5] is std_1c20:inst|sdram:the_sdram|active_addr[5] at LC_X15_Y20_N3

--operation mode is normal

KB1_active_addr[5]_lut_out = KB1L14 & (KB1L12 & (TE1L195) # !KB1L12 & KB1_active_addr[5]) # !KB1L14 & KB1_active_addr[5];

KB1_active_addr[5] = DFFEAS(KB1_active_addr[5]_lut_out, GLOBAL(QC2__clk0), VCC, , , , , , );

--KB1L791 is std_1c20:inst|sdram:the_sdram|Mux110~1393 at LC_X15_Y20_N8

--operation mode is normal

KB1L791 = !KB1L813 & (KB1L803 # KB1L811 # !KB1L805);

--KB1L814 is std_1c20:inst|sdram:the_sdram|Mux111~1315 at LC_X12_Y20_N7

--operation mode is normal

KB1L814 = KB1L713 & KB1L185Q # !KB1L713 & KB1_m_state[6] & (KB1L185Q # KB1L729);

--TE1L194 is std_1c20:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|rd_data[40]~498 at LC_X22_Y19_N9

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

TE1_entry_1[40]_qfbk = TE1_entry_1[40];

TE1L194 = TE1_rd_address & TE1_entry_1[40]_qfbk # !TE1_rd_address & (TE1_entry_0[40]);

--TE1_entry_1[40] is std_1c20:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_1[40] at LC_X22_Y19_N9

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

TE1_entry_1[40] = DFFEAS(TE1L194, GLOBAL(QC2__clk0), VCC, , TE1L148, NB1L43, , , VCC);

--KB1_active_addr[4] is std_1c20:inst|sdram:the_sdram|active_addr[4] at LC_X15_Y20_N4

--operation mode is normal

KB1_active_addr[4]_lut_out = KB1L12 & (KB1L14 & TE1L194 # !KB1L14 & (KB1_active_addr[4])) # !KB1L12 & (KB1_active_addr[4]);

KB1_active_addr[4] = DFFEAS(KB1_active_addr[4]_lut_out, GLOBAL(QC2__clk0), VCC, , , , , , );

--KB1L819 is std_1c20:inst|sdram:the_sdram|Mux111~1320 at LC_X14_Y20_N6

--operation mode is normal

KB1L819 = !KB1L842 & (KB1L840 # KB1L832 # !KB1L834);

--KB1L843 is std_1c20:inst|sdram:the_sdram|Mux112~1347 at LC_X13_Y19_N3

--operation mode is normal

KB1L843 = KB1L713 & (KB1L180Q) # !KB1L713 & KB1_m_state[6] & (KB1L729 # KB1L180Q);

--TE1L193 is std_1c20:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|rd_data[39]~499 at LC_X22_Y19_N5

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

TE1_entry_1[39]_qfbk = TE1_entry_1[39];

TE1L193 = TE1_rd_address & TE1_entry_1[39]_qfbk # !TE1_rd_address & (TE1_entry_0[39]);

--TE1_entry_1[39] is std_1c20:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_1[39] at LC_X22_Y19_N5

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

TE1_entry_1[39] = DFFEAS(TE1L193, GLOBAL(QC2__clk0), VCC, , TE1L148, NB1L42, , , VCC);

--KB1_active_addr[3] is std_1c20:inst|sdram:the_sdram|active_addr[3] at LC_X16_Y19_N4

--operation mode is normal

KB1_active_addr[3]_lut_out = KB1L12 & (KB1L14 & TE1L193 # !KB1L14 & (KB1_active_addr[3])) # !KB1L12 & (KB1_active_addr[3]);

KB1_active_addr[3] = DFFEAS(KB1_active_addr[3]_lut_out, GLOBAL(QC2__clk0), VCC, , , , , , );

--KB1L848 is std_1c20:inst|sdram:the_sdram|Mux112~1352 at LC_X13_Y19_N5

--operation mode is normal

KB1L848 = KB1L865 & (KB1_active_addr[12] # !KB1L867) # !KB1L865 & (!KB1L867 & !KB1L859);

--KB1L868 is std_1c20:inst|sdram:the_sdram|Mux113~1347 at LC_X12_Y18_N7

--operation mode is normal

KB1L868 = KB1L713 & (KB1L175Q) # !KB1L713 & KB1_m_state[6] & (KB1L175Q # KB1L729);

--TE1L192 is std_1c20:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|rd_data[38]~500 at LC_X21_Y21_N2

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

TE1_entry_1[38]_qfbk = TE1_entry_1[38];

TE1L192 = TE1_rd_address & TE1_entry_1[38]_qfbk # !TE1_rd_address & (TE1_entry_0[38]);

--TE1_entry_1[38] is std_1c20:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_1[38] at LC_X21_Y21_N2

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

TE1_entry_1[38] = DFFEAS(TE1L192, GLOBAL(QC2__clk0), VCC, , TE1L148, NB1L41, , , VCC);

--KB1_active_addr[2] is std_1c20:inst|sdram:the_sdram|active_addr[2] at LC_X14_Y18_N2

--operation mode is normal

KB1_active_addr[2]_lut_out = KB1L14 & (KB1L12 & (TE1L192) # !KB1L12 & KB1_active_addr[2]) # !KB1L14 & KB1_active_addr[2];

KB1_active_addr[2] = DFFEAS(KB1_active_addr[2]_lut_out, GLOBAL(QC2__clk0), VCC, , , , , , );

--KB1L873 is std_1c20:inst|sdram:the_sdram|Mux113~1352 at LC_X12_Y18_N2

--operation mode is normal

KB1L873 = KB1L889 & (KB1_active_addr[11] # !KB1L891) # !KB1L889 & (!KB1L891 & !KB1L883);

--KB1L892 is std_1c20:inst|sdram:the_sdram|Mux114~1347 at LC_X14_Y19_N4

--operation mode is normal

KB1L892 = KB1L713 & (KB1L170Q) # !KB1L713 & KB1_m_state[6] & (KB1L170Q # KB1L729);

--TE1L191 is std_1c20:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|rd_data[37]~501 at LC_X22_Y19_N2

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

TE1_entry_1[37]_qfbk = TE1_entry_1[37];

TE1L191 = TE1_rd_address & TE1_entry_1[37]_qfbk # !TE1_rd_address & (TE1_entry_0[37]);

--TE1_entry_1[37] is std_1c20:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_1[37] at LC_X22_Y19_N2

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

TE1_entry_1[37] = DFFEAS(TE1L191, GLOBAL(QC2__clk0), VCC, , TE1L148, NB1L40, , , VCC);

--KB1_active_addr[1] is std_1c20:inst|sdram:the_sdram|active_addr[1] at LC_X16_Y19_N2

--operation mode is normal

KB1_active_addr[1]_lut_out = KB1L12 & (KB1L14 & (TE1L191) # !KB1L14 & KB1_active_addr[1]) # !KB1L12 & KB1_active_addr[1];

KB1_active_addr[1] = DFFEAS(KB1_active_addr[1]_lut_out, GLOBAL(QC2__clk0), VCC, , , , , , );

--KB1L897 is std_1c20:inst|sdram:the_sdram|Mux114~1352 at LC_X14_Y19_N2

--operation mode is normal

KB1L897 = KB1L917 & KB1_active_addr[10] & KB1L915 # !KB1L917 & (KB1L915 # !KB1L908);

--KB1L918 is std_1c20:inst|sdram:the_sdram|Mux115~1347 at LC_X13_Y18_N8

--operation mode is normal

KB1L918 = KB1L713 & (KB1L165Q) # !KB1L713 & KB1_m_state[6] & (KB1L729 # KB1L165Q);

--TE1L190 is std_1c20:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|rd_data[36]~502 at LC_X22_Y19_N8

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

TE1_entry_1[36]_qfbk = TE1_entry_1[36];

TE1L190 = TE1_rd_address & TE1_entry_1[36]_qfbk # !TE1_rd_address & (TE1_entry_0[36]);

--TE1_entry_1[36] is std_1c20:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_1[36] at LC_X22_Y19_N8

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

TE1_entry_1[36] = DFFEAS(TE1L190, GLOBAL(QC2__clk0), VCC, , TE1L148, NB1L39, , , VCC);

--KB1_active_addr[0] is std_1c20:inst|sdram:the_sdram|active_addr[0] at LC_X14_Y18_N4

--operation mode is normal

KB1_active_addr[0]_lut_out = KB1L14 & (KB1L12 & TE1L190 # !KB1L12 & (KB1_active_addr[0])) # !KB1L14 & (KB1_active_addr[0]);

KB1_active_addr[0] = DFFEAS(KB1_active_addr[0]_lut_out, GLOBAL(QC2__clk0), VCC, , , , , , );

--KB1L923 is std_1c20:inst|sdram:the_sdram|Mux115~1352 at LC_X13_Y18_N5

--operation mode is normal

KB1L923 = KB1L939 & (KB1_active_addr[9] # !KB1L941) # !KB1L939 & (!KB1L941 & !KB1L934);

--TE1L199 is std_1c20:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|rd_data[57]~503 at LC_X18_Y22_N9

--operation mode is normal

TE1L199 = TE1_rd_address & (TE1_entry_1[57]) # !TE1_rd_address & TE1_entry_0[57];

--KB1L942 is std_1c20:inst|sdram:the_sdram|Mux116~1304 at LC_X18_Y22_N0

--operation mode is normal

KB1L942 = KB1_m_state[1] & KB1_active_addr[21] # !KB1_m_state[1] & (KB1_f_select & (TE1L199) # !KB1_f_select & KB1_active_addr[21]);

--KB1L943 is std_1c20:inst|sdram:the_sdram|Mux116~1305 at LC_X13_Y21_N3

--operation mode is normal

KB1L943 = KB1_m_state[3] & !KB1_m_state[1] & !KB1_m_state[4] # !KB1_m_state[3] & (KB1_m_state[1] $ KB1_m_state[4]);

--KB1L518 is std_1c20:inst|sdram:the_sdram|Mux24~1464 at LC_X14_Y22_N4

--operation mode is normal

KB1L518 = !KB1_m_state[2] & KB1_m_state[0] & !KB1_m_state[7];

--KB1L550 is std_1c20:inst|sdram:the_sdram|Mux29~1324 at LC_X11_Y23_N7

--operation mode is normal

KB1L550 = !KB1_m_state[6] & !KB1_m_state[5];

--TE1L198 is std_1c20:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|rd_data[44]~504 at LC_X17_Y23_N3

--operation mode is normal

TE1L198 = TE1_rd_address & (TE1_entry_1[44]) # !TE1_rd_address & (TE1_entry_0[44]);

--KB1L944 is std_1c20:inst|sdram:the_sdram|Mux117~1184 at LC_X18_Y22_N7

--operation mode is normal

KB1L944 = KB1_f_select & (KB1_m_state[1] & (KB1_active_addr[8]) # !KB1_m_state[1] & TE1L198) # !KB1_f_select & (KB1_active_addr[8]);

--KB1_active_dqm[3] is std_1c20:inst|sdram:the_sdram|active_dqm[3] at LC_X18_Y21_N4

--operation mode is normal

KB1_active_dqm[3]_lut_out = KB1L12 & (KB1L14 & (TE1L189) # !KB1L14 & KB1_active_dqm[3]) # !KB1L12 & KB1_active_dqm[3];

KB1_active_dqm[3] = DFFEAS(KB1_active_dqm[3]_lut_out, GLOBAL(QC2__clk0), VCC, , , , , , );

--TE1L189 is std_1c20:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|rd_data[35]~505 at LC_X24_Y21_N1

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

TE1_entry_1[35]_qfbk = TE1_entry_1[35];

TE1L189 = TE1_rd_address & TE1_entry_1[35]_qfbk # !TE1_rd_address & (TE1_entry_0[35]);

--TE1_entry_1[35] is std_1c20:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_1[35] at LC_X24_Y21_N1

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

TE1_entry_1[35] = DFFEAS(TE1L189, GLOBAL(QC2__clk0), VCC, , TE1L148, KB1L476, , , VCC);

--KB1L980 is std_1c20:inst|sdram:the_sdram|Mux150~1184 at LC_X18_Y21_N1

--operation mode is normal

KB1L980 = KB1_m_state[1] & KB1_active_dqm[3] # !KB1_m_state[1] & (KB1_f_select & (TE1L189) # !KB1_f_select & KB1_active_dqm[3]);

--KB1_active_dqm[2] is std_1c20:inst|sdram:the_sdram|active_dqm[2] at LC_X18_Y21_N0

--operation mode is normal

KB1_active_dqm[2]_lut_out = KB1L12 & (KB1L14 & (TE1L188) # !KB1L14 & KB1_active_dqm[2]) # !KB1L12 & KB1_active_dqm[2];

KB1_active_dqm[2] = DFFEAS(KB1_active_dqm[2]_lut_out, GLOBAL(QC2__clk0), VCC, , , , , , );

--TE1L188 is std_1c20:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|rd_data[34]~506 at LC_X24_Y21_N7

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

TE1_entry_1[34]_qfbk = TE1_entry_1[34];

TE1L188 = TE1_rd_address & TE1_entry_1[34]_qfbk # !TE1_rd_address & (TE1_entry_0[34]);

--TE1_entry_1[34] is std_1c20:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_1[34] at LC_X24_Y21_N7

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

TE1_entry_1[34] = DFFEAS(TE1L188, GLOBAL(QC2__clk0), VCC, , TE1L148, KB1L475, , , VCC);

--KB1L981 is std_1c20:inst|sdram:the_sdram|Mux151~1184 at LC_X18_Y21_N5

--operation mode is normal

KB1L981 = KB1_m_state[1] & KB1_active_dqm[2] # !KB1_m_state[1] & (KB1_f_select & (TE1L188) # !KB1_f_select & KB1_active_dqm[2]);

--KB1_active_dqm[1] is std_1c20:inst|sdram:the_sdram|active_dqm[1] at LC_X18_Y21_N7

--operation mode is normal

KB1_active_dqm[1]_lut_out = KB1L12 & (KB1L14 & (TE1L187) # !KB1L14 & KB1_active_dqm[1]) # !KB1L12 & KB1_active_dqm[1];

KB1_active_dqm[1] = DFFEAS(KB1_active_dqm[1]_lut_out, GLOBAL(QC2__clk0), VCC, , , , , , );

--TE1L187 is std_1c20:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|rd_data[33]~507 at LC_X24_Y21_N3

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

TE1_entry_1[33]_qfbk = TE1_entry_1[33];

TE1L187 = TE1_rd_address & TE1_entry_1[33]_qfbk # !TE1_rd_address & (TE1_entry_0[33]);

--TE1_entry_1[33] is std_1c20:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_1[33] at LC_X24_Y21_N3

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

TE1_entry_1[33] = DFFEAS(TE1L187, GLOBAL(QC2__clk0), VCC, , TE1L148, KB1L474, , , VCC);

--KB1L982 is std_1c20:inst|sdram:the_sdram|Mux152~1184 at LC_X18_Y21_N8

--operation mode is normal

KB1L982 = KB1_f_select & (KB1_m_state[1] & KB1_active_dqm[1] # !KB1_m_state[1] & (TE1L187)) # !KB1_f_select & KB1_active_dqm[1];

--KB1_active_dqm[0] is std_1c20:inst|sdram:the_sdram|active_dqm[0] at LC_X13_Y21_N2

--operation mode is normal

KB1_active_dqm[0]_lut_out = KB1L14 & (KB1L12 & TE1L186 # !KB1L12 & (KB1_active_dqm[0])) # !KB1L14 & (KB1_active_dqm[0]);

KB1_active_dqm[0] = DFFEAS(KB1_active_dqm[0]_lut_out, GLOBAL(QC2__clk0), VCC, , , , , , );

--TE1L186 is std_1c20:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|rd_data[32]~508 at LC_X24_Y21_N9

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

TE1_entry_1[32]_qfbk = TE1_entry_1[32];

TE1L186 = TE1_rd_address & TE1_entry_1[32]_qfbk # !TE1_rd_address & (TE1_entry_0[32]);

--TE1_entry_1[32] is std_1c20:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_1[32] at LC_X24_Y21_N9

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

TE1_entry_1[32] = DFFEAS(TE1L186, GLOBAL(QC2__clk0), VCC, , TE1L148, KB1L473, , , VCC);

--KB1L983 is std_1c20:inst|sdram:the_sdram|Mux153~1184 at LC_X13_Y21_N5

--operation mode is normal

KB1L983 = KB1_m_state[1] & KB1_active_dqm[0] # !KB1_m_state[1] & (KB1_f_select & (TE1L186) # !KB1_f_select & KB1_active_dqm[0]);

--C1L15Q is sld_hub:sld_hub_inst|hub_tdo~549 at LC_X56_Y17_N3

--operation mode is normal

C1L15Q = AMPP_FUNCTION(!A1L5, BF8_Q[1], C1L21, GE1_td_shift[0], C1L20, !FF1_state[8]);

--C1L13Q is sld_hub:sld_hub_inst|hub_tdo~547 at LC_X56_Y17_N8

--operation mode is normal

C1L13Q = AMPP_FUNCTION(!A1L5, C1_jtag_debug_mode_usr1, BF3_Q[0], !FF1_state[8]);

--C1L18 is sld_hub:sld_hub_inst|hub_tdo~563 at LC_X56_Y17_N1

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

C1L18 = AMPP_FUNCTION(C1L13Q, C1L15Q);

--C1L14Q is sld_hub:sld_hub_inst|hub_tdo~548 at LC_X56_Y17_N1

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

C1L14Q = AMPP_FUNCTION(!A1L5, C1_jtag_debug_mode_usr1, !FF1_state[8], GND);

--C1L16Q is sld_hub:sld_hub_inst|hub_tdo~550 at LC_X56_Y17_N9

--operation mode is normal

C1L16Q = AMPP_FUNCTION(!A1L5, C1L19, !FF1_state[8]);

--C1L12Q is sld_hub:sld_hub_inst|hub_tdo~546 at LC_X56_Y17_N0

--operation mode is normal

C1L12Q = AMPP_FUNCTION(!A1L5, FF1L18, !FF1_state[8]);

--C1L19 is sld_hub:sld_hub_inst|hub_tdo~564 at LC_X56_Y17_N2

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

C1L19 = AMPP_FUNCTION(C1L16Q, C1L12Q, C1L18);

--C1L17Q is sld_hub:sld_hub_inst|hub_tdo~551 at LC_X56_Y17_N2

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

C1L17Q = AMPP_FUNCTION(!A1L5, FF1L18, !FF1_state[8], GND);

--S1L1525 is std_1c20:inst|cpu:the_cpu|ic_fill_ap_cnt[3]~31 at LC_X26_Y24_N1

--operation mode is normal

S1L1525 = AMPP_FUNCTION(S1L1527Q, U1L14Q, U1L10Q, U1L12Q);

--U1L257 is std_1c20:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|r_1~13 at LC_X27_Y23_N8

--operation mode is normal

U1L257 = Y1L40 # Y1L43 # !U1L223;

--U1L258 is std_1c20:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|r_1~15 at LC_X27_Y22_N9

--operation mode is normal

U1L258 = Y1L46 # Y1L49 # !Y1L1007;

--V1L39 is std_1c20:inst|cpu_jtag_debug_module_arbitrator:the_cpu_jtag_debug_module|cpu_jtag_debug_module_arb_addend[1]~751 at LC_X35_Y24_N6

--operation mode is normal

V1L39 = V1L43Q # V1L42Q # !V1_d1_reasons_to_wait & V1L41Q;

--V1L58 is std_1c20:inst|cpu_jtag_debug_module_arbitrator:the_cpu_jtag_debug_module|internal_cpu_instruction_master_qualified_request_cpu_jtag_debug_module~44 at LC_X29_Y22_N6

--operation mode is normal

V1L58 = S1L1574Q & (U1L238Q # WE1L8Q # U1_internal_cpu_instruction_master_latency_counter[0]);

--S1L1505Q is std_1c20:inst|cpu:the_cpu|ic_fill_ap_cnt[0]~50 at LC_X28_Y21_N2

--operation mode is normal

S1L1505Q = AMPP_FUNCTION(QC2__clk0, S1L1588, S1L1581, S1L1584, S1L1503, F1_data_out);

--S1L1570Q is std_1c20:inst|cpu:the_cpu|ic_fill_tag[0]~90 at LC_X28_Y22_N1

--operation mode is normal

S1L1570Q = AMPP_FUNCTION(QC2__clk0, S1L1679, S1L1578, S1L1569, F1_data_out);

--X1L16 is std_1c20:inst|epcs_controller_epcs_control_port_arbitrator:the_epcs_controller_epcs_control_port|cpu_instruction_master_requests_epcs_controller_epcs_control_port~67 at LC_X28_Y22_N9

--operation mode is normal

X1L16 = !S1L1559Q & S1L1573Q & S1L1574Q & S1L1572Q;

--V1L34Q is std_1c20:inst|cpu_jtag_debug_module_arbitrator:the_cpu_jtag_debug_module|cpu_jtag_debug_module_arb_addend[0]~760 at LC_X35_Y24_N4

--operation mode is normal

V1L34Q_lut_out = !V1L30 & V1L29 & (!V1L52 # !V1L10);

V1L34Q = DFFEAS(V1L34Q_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--V1L1 is std_1c20:inst|cpu_jtag_debug_module_arbitrator:the_cpu_jtag_debug_module|Add2~344 at LC_X33_Y24_N0

--operation mode is normal

V1L1 = !V1L34Q & (V1L58 # !S1L1593Q # !X1L16);

--K1L3 is std_1c20:inst|clock_0_in_arbitrator:the_clock_0_in|cpu_data_master_requests_clock_0_in~534 at LC_X33_Y21_N2

--operation mode is normal

K1L3 = !S1L1816Q & K1L17 & K1L15 & K1L13;

--V1L2 is std_1c20:inst|cpu_jtag_debug_module_arbitrator:the_cpu_jtag_debug_module|Add2~345 at LC_X33_Y24_N1

--operation mode is normal

V1L2 = V1L39 & (V1L1 # !K1L3 # !V1L8) # !V1L39 & V1L1 & (!K1L3 # !V1L8);

--U1L249 is std_1c20:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|r_0~1 at LC_X33_Y24_N3

--operation mode is normal

U1L249 = U1L253 & (!K1L3 # !V1L8) # !U1L253 & (!U1L251);

--U1L164 is std_1c20:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_run~165 at LC_X27_Y24_N0

--operation mode is normal

U1L164 = U1L249 & (Y1L25 # !Y1L874 # !Y1L5);

--U1L165 is std_1c20:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_run~166 at LC_X27_Y22_N6

--operation mode is normal

U1L165 = U1L249 & (U1L178 & (Y1L25) # !U1L178 & !U1L176);

--Y1L824 is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|internal_cpu_instruction_master_qualified_request_ext_ram_s1~96 at LC_X30_Y22_N6

--operation mode is normal

Y1L824 = S1L1506Q # Y1L820Q & (Y1L88 # Y1L826);

--Y1L380 is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_flash_s1_wait_counter[0]~95 at LC_X30_Y27_N3

--operation mode is normal

Y1L380 = Y1L382Q & !Y1L381Q & !Y1L398Q;

--Y1L389Q is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_flash_s1_wait_counter[2]~93 at LC_X31_Y27_N0

--operation mode is normal

Y1L389Q_lut_out = Y1_ext_flash_s1_wait_counter[1] # Y1L387Q # Y1L380 # Y1L396Q;

Y1L389Q = DFFEAS(Y1L389Q_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--U1L260 is std_1c20:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|r_1~293 at LC_X27_Y24_N9

--operation mode is normal

U1L260 = U1_internal_cpu_instruction_master_dbs_address[0] & Y1L653Q & U1_internal_cpu_instruction_master_dbs_address[1] & Y1L118;

--U1L166 is std_1c20:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_run~167 at LC_X27_Y23_N9

--operation mode is normal

U1L166 = Y1L824 & !S1L1640Q & !S1L1507Q # !Y1L824 & (U1L260 # !S1L1507Q);

--X1_epcs_controller_epcs_control_port_arb_addend[1] is std_1c20:inst|epcs_controller_epcs_control_port_arbitrator:the_epcs_controller_epcs_control_port|epcs_controller_epcs_control_port_arb_addend[1] at LC_X34_Y23_N4

--operation mode is normal

X1_epcs_controller_epcs_control_port_arb_addend[1]_lut_out = X1L4 & (X1L8 # X1L44) # !X1L4 & (X1L8 & (!X1L44) # !X1L8 & X1_epcs_controller_epcs_control_port_arb_addend[1]);

X1_epcs_controller_epcs_control_port_arb_addend[1] = DFFEAS(X1_epcs_controller_epcs_control_port_arb_addend[1]_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--X1L6 is std_1c20:inst|epcs_controller_epcs_control_port_arbitrator:the_epcs_controller_epcs_control_port|cpu_data_master_requests_epcs_controller_epcs_control_port~349 at LC_X34_Y21_N2

--operation mode is normal

X1L6 = !T1L448Q & S1L1782Q;

--X1_cpu_data_master_requests_epcs_controller_epcs_control_port is std_1c20:inst|epcs_controller_epcs_control_port_arbitrator:the_epcs_controller_epcs_control_port|cpu_data_master_requests_epcs_controller_epcs_control_port at LC_X33_Y21_N3

--operation mode is normal

X1_cpu_data_master_requests_epcs_controller_epcs_control_port = X1L6 & !S1L1773Q & S1L207Q & K1L3;

--S1L539Q is std_1c20:inst|cpu:the_cpu|d_readdata_d1[11]~211 at LC_X33_Y21_N3

--operation mode is normal

S1L539Q = AMPP_FUNCTION(QC2__clk0, X1L6, S1L1773Q, S1L207Q, K1L3, F1_data_out);

--X1_epcs_controller_epcs_control_port_arb_addend[0] is std_1c20:inst|epcs_controller_epcs_control_port_arbitrator:the_epcs_controller_epcs_control_port|epcs_controller_epcs_control_port_arb_addend[0] at LC_X33_Y23_N9

--operation mode is normal

X1_epcs_controller_epcs_control_port_arb_addend[0]_lut_out = X1L8 & (!X1L44) # !X1L8 & (X1L4 & (X1L44) # !X1L4 & X1_epcs_controller_epcs_control_port_arb_addend[0]);

X1_epcs_controller_epcs_control_port_arb_addend[0] = DFFEAS(X1_epcs_controller_epcs_control_port_arb_addend[0]_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--X1_cpu_instruction_master_granted_epcs_controller_epcs_control_port is std_1c20:inst|epcs_controller_epcs_control_port_arbitrator:the_epcs_controller_epcs_control_port|cpu_instruction_master_granted_epcs_controller_epcs_control_port at LC_X33_Y23_N2

--operation mode is normal

X1_cpu_instruction_master_granted_epcs_controller_epcs_control_port = X1_epcs_controller_epcs_control_port_arb_addend[0] & (X1_epcs_controller_epcs_control_port_arb_addend[1] & !X1_cpu_data_master_requests_epcs_controller_epcs_control_port # !X1L10) # !X1_epcs_controller_epcs_control_port_arb_addend[0] & (X1L10 # !X1_epcs_controller_epcs_control_port_arb_addend[1] & X1_cpu_data_master_requests_epcs_controller_epcs_control_port);

--NB1_sdram_s1_arb_addend[1] is std_1c20:inst|sdram_s1_arbitrator:the_sdram_s1|sdram_s1_arb_addend[1] at LC_X23_Y22_N4

--operation mode is normal

NB1_sdram_s1_arb_addend[1]_lut_out = NB1_WideOr1 & (NB1L65) # !NB1_WideOr1 & NB1_sdram_s1_arb_addend[1];

NB1_sdram_s1_arb_addend[1] = DFFEAS(NB1_sdram_s1_arb_addend[1]_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--S1L1697Q is std_1c20:inst|cpu:the_cpu|internal_d_write~78 at LC_X32_Y22_N4

--operation mode is normal

S1L1697Q = AMPP_FUNCTION(QC2__clk0, S1L1682, S1L1685, VE1L11, T1L458, F1_data_out);

--NB1_sdram_s1_slavearbiterlockenable is std_1c20:inst|sdram_s1_arbitrator:the_sdram_s1|sdram_s1_slavearbiterlockenable at LC_X23_Y22_N2

--operation mode is normal

NB1_sdram_s1_slavearbiterlockenable_lut_out = NB1L84 & NB1_sdram_s1_slavearbiterlockenable # !NB1L84 & (NB1L38 & (NB1L91) # !NB1L38 & NB1_sdram_s1_slavearbiterlockenable);

NB1_sdram_s1_slavearbiterlockenable = DFFEAS(NB1_sdram_s1_slavearbiterlockenable_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--NB1_last_cycle_cpu_instruction_master_granted_slave_sdram_s1 is std_1c20:inst|sdram_s1_arbitrator:the_sdram_s1|last_cycle_cpu_instruction_master_granted_slave_sdram_s1 at LC_X24_Y22_N6

--operation mode is normal

NB1_last_cycle_cpu_instruction_master_granted_slave_sdram_s1_lut_out = NB1L27 & (NB1L81 # NB1_last_cycle_cpu_instruction_master_granted_slave_sdram_s1 & !NB1L83);

NB1_last_cycle_cpu_instruction_master_granted_slave_sdram_s1 = DFFEAS(NB1_last_cycle_cpu_instruction_master_granted_slave_sdram_s1_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--NB1L79 is std_1c20:inst|sdram_s1_arbitrator:the_sdram_s1|sdram_s1_arb_share_counter_next_value[5]~576 at LC_X24_Y22_N2

--operation mode is normal

NB1L79 = NB1_last_cycle_cpu_instruction_master_granted_slave_sdram_s1 & !S1L1642Q & S1L1636Q & S1L1574Q;

--NB1L22 is std_1c20:inst|sdram_s1_arbitrator:the_sdram_s1|cpu_data_master_qualified_request_sdram_s1~115 at LC_X24_Y22_N3

--operation mode is normal

NB1L22 = !S1L1697Q & S1L1693Q & (!NB1L79 # !NB1_sdram_s1_slavearbiterlockenable);

--NB1L27 is std_1c20:inst|sdram_s1_arbitrator:the_sdram_s1|cpu_instruction_master_requests_sdram_s1~41 at LC_X27_Y22_N8

--operation mode is normal

NB1L27 = !S1L1642Q & S1L1574Q & S1L1636Q;

--NB1_last_cycle_cpu_data_master_granted_slave_sdram_s1 is std_1c20:inst|sdram_s1_arbitrator:the_sdram_s1|last_cycle_cpu_data_master_granted_slave_sdram_s1 at LC_X32_Y20_N7

--operation mode is normal

NB1_last_cycle_cpu_data_master_granted_slave_sdram_s1_lut_out = S1L1693Q & (NB1L1 # NB1_last_cycle_cpu_data_master_granted_slave_sdram_s1 & !NB1L83);

NB1_last_cycle_cpu_data_master_granted_slave_sdram_s1 = DFFEAS(NB1_last_cycle_cpu_data_master_granted_slave_sdram_s1_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--NB1L19 is std_1c20:inst|sdram_s1_arbitrator:the_sdram_s1|cpu_data_master_arbiterlock~23 at LC_X32_Y20_N9

--operation mode is normal

NB1L19 = !S1L207Q & S1L1866Q & NB1_last_cycle_cpu_data_master_granted_slave_sdram_s1 & S1L1686Q;

--NB1L29 is std_1c20:inst|sdram_s1_arbitrator:the_sdram_s1|internal_cpu_instruction_master_qualified_request_sdram_s1~59 at LC_X26_Y22_N8

--operation mode is normal

NB1L29 = S1L1574Q & (U1L238Q # U1_internal_cpu_instruction_master_latency_counter[0]);

--NB1L25 is std_1c20:inst|sdram_s1_arbitrator:the_sdram_s1|cpu_instruction_master_qualified_request_sdram_s1~58 at LC_X24_Y22_N9

--operation mode is normal

NB1L25 = NB1L27 & !NB1L29 & (!NB1L19 # !NB1_sdram_s1_slavearbiterlockenable);

--NB1_sdram_s1_arb_addend[0] is std_1c20:inst|sdram_s1_arbitrator:the_sdram_s1|sdram_s1_arb_addend[0] at LC_X23_Y23_N4

--operation mode is normal

NB1_sdram_s1_arb_addend[0]_lut_out = NB1_WideOr1 & !NB1L63 # !NB1_WideOr1 & (NB1_sdram_s1_arb_addend[0]);

NB1_sdram_s1_arb_addend[0] = DFFEAS(NB1_sdram_s1_arb_addend[0]_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--NB1L30 is std_1c20:inst|sdram_s1_arbitrator:the_sdram_s1|internal_cpu_instruction_master_qualified_request_sdram_s1~60 at LC_X24_Y22_N8

--operation mode is normal

NB1L30 = NB1L29 # NB1_last_cycle_cpu_data_master_granted_slave_sdram_s1 & !S1L207Q & NB1L32;

--TE1L151 is std_1c20:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|Equal0~93 at LC_X23_Y23_N5

--operation mode is normal

TE1L151 = TE1_entries[1] & !TE1_entries[0];

--U1L169 is std_1c20:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_run~170 at LC_X27_Y23_N6

--operation mode is normal

U1L169 = U1L186 & (U1L182 & !X1_cpu_data_master_requests_epcs_controller_epcs_control_port # !U1L182 & (!U1L180));

--U1L170 is std_1c20:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_run~171 at LC_X27_Y23_N7

--operation mode is normal

U1L170 = U1L166 & U1L169 & (!Y1L824 # !S1L1602Q);

--U1L10Q is std_1c20:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_read_but_no_slave_selected~59 at LC_X27_Y23_N7

--operation mode is normal

U1L10Q = DFFEAS(U1L170, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--S1L1498Q is std_1c20:inst|cpu:the_cpu|ic_fill_ap_cnt[0]~24 at LC_X27_Y24_N3

--operation mode is normal

S1L1498Q = AMPP_FUNCTION(QC2__clk0, U1L170, U1L257, U1L258, U1L165, F1_data_out);

--S1L331 is std_1c20:inst|cpu:the_cpu|D_inst_ram_hit~15 at LC_X25_Y18_N4

--operation mode is normal

S1L331 = AMPP_FUNCTION(S1L344Q, S1L332Q, S1L328, S1L333Q);

--S1_ic_fill_prevent_refill is std_1c20:inst|cpu:the_cpu|ic_fill_prevent_refill at LC_X24_Y20_N8

--operation mode is normal

S1_ic_fill_prevent_refill = AMPP_FUNCTION(QC2__clk0, S1L1562, S1_ic_fill_prevent_refill, S1L322, S1L323, F1_data_out);

--S1_D_ic_fill_same_tag_line is std_1c20:inst|cpu:the_cpu|D_ic_fill_same_tag_line at LC_X25_Y20_N5

--operation mode is normal

S1_D_ic_fill_same_tag_line = AMPP_FUNCTION(QC2__clk0, S1L1215, S1L1209, S1L1214, S1L1217, F1_data_out, S1_W_stall);

--S1L322 is std_1c20:inst|cpu:the_cpu|D_ic_fill_starting~75 at LC_X24_Y20_N2

--operation mode is normal

S1L322 = AMPP_FUNCTION(S1_D_kill, S1_D_ic_fill_same_tag_line, S1_ic_fill_prevent_refill, S1L331);

--S1_ic_fill_active is std_1c20:inst|cpu:the_cpu|ic_fill_active at LC_X23_Y20_N8

--operation mode is normal

S1_ic_fill_active = AMPP_FUNCTION(QC2__clk0, S1_i_readdatavalid_d1, S1_ic_fill_active, S1L1493, S1_D_ic_fill_starting, F1_data_out);

--S1L323 is std_1c20:inst|cpu:the_cpu|D_ic_fill_starting~76 at LC_X24_Y20_N0

--operation mode is normal

S1L323 = AMPP_FUNCTION(S1_ic_fill_active, S1_M_pipe_flush);

--S1_D_pc[18] is std_1c20:inst|cpu:the_cpu|D_pc[18] at LC_X25_Y16_N2

--operation mode is normal

S1_D_pc[18] = AMPP_FUNCTION(QC2__clk0, S1_F_pc[18], F1_data_out, S1_W_stall);

--S1_D_pc[23] is std_1c20:inst|cpu:the_cpu|D_pc[23] at LC_X29_Y19_N5

--operation mode is normal

S1_D_pc[23] = AMPP_FUNCTION(QC2__clk0, S1_F_pc[23], F1_data_out, S1_W_stall);

--S1_D_pc[19] is std_1c20:inst|cpu:the_cpu|D_pc[19] at LC_X29_Y18_N5

--operation mode is normal

S1_D_pc[19] = AMPP_FUNCTION(QC2__clk0, S1_F_pc[19], F1_data_out, S1_W_stall);

--S1_D_pc[20] is std_1c20:inst|cpu:the_cpu|D_pc[20] at LC_X25_Y18_N9

--operation mode is normal

S1_D_pc[20] = AMPP_FUNCTION(QC2__clk0, S1_F_pc[20], F1_data_out, S1_W_stall);

--S1_D_pc[21] is std_1c20:inst|cpu:the_cpu|D_pc[21] at LC_X26_Y16_N5

--operation mode is normal

S1_D_pc[21] = AMPP_FUNCTION(QC2__clk0, S1_F_pc[21], F1_data_out, S1_W_stall);

--S1_D_pc[22] is std_1c20:inst|cpu:the_cpu|D_pc[22] at LC_X27_Y20_N8

--operation mode is normal

S1_D_pc[22] = AMPP_FUNCTION(QC2__clk0, S1_F_pc[22], F1_data_out, S1_W_stall);

--S1_D_pc[16] is std_1c20:inst|cpu:the_cpu|D_pc[16] at LC_X25_Y20_N9

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

S1_D_pc[16] = AMPP_FUNCTION(QC2__clk0, S1_F_pc[16], F1_data_out, GND, S1_W_stall);

--S1_D_pc[17] is std_1c20:inst|cpu:the_cpu|D_pc[17] at LC_X25_Y16_N8

--operation mode is normal

S1_D_pc[17] = AMPP_FUNCTION(QC2__clk0, S1_F_pc[17], F1_data_out, S1_W_stall);

--S1_D_pc[14] is std_1c20:inst|cpu:the_cpu|D_pc[14] at LC_X26_Y16_N2

--operation mode is normal

S1_D_pc[14] = AMPP_FUNCTION(QC2__clk0, S1_F_pc[14], F1_data_out, S1_W_stall);

--S1_D_pc[15] is std_1c20:inst|cpu:the_cpu|D_pc[15] at LC_X30_Y19_N2

--operation mode is normal

S1_D_pc[15] = AMPP_FUNCTION(QC2__clk0, S1_F_pc[15], F1_data_out, S1_W_stall);

--Y1L706Q is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_avalon_slave_arb_share_counter[1]~601 at LC_X27_Y25_N5

--operation mode is normal

Y1L706Q_lut_out = Y1L710 # !Y1L726 & (Y1L587 # Y1L14);

Y1L706Q = DFFEAS(Y1L706Q_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--Y1L726 is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_avalon_slave_firsttransfer~139 at LC_X31_Y21_N6

--operation mode is normal

Y1L726 = Y1L819Q & (Y1L89 # S1L1629Q);

--Y1L812 is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_avalon_slave_slavearbiterlockenable~192 at LC_X30_Y21_N5

--operation mode is normal

Y1L812 = Y1L726 & (Y1L705) # !Y1L726 & (!Y1L998);

--Y1L816Q is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_avalon_slave_slavearbiterlockenable~196 at LC_X30_Y21_N5

--operation mode is normal

Y1L816Q = DFFEAS(Y1L812, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--Y1L1011 is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|process4~73 at LC_X34_Y21_N5

--operation mode is normal

Y1L1011 = S1L207Q & (S1L1782Q # !S1L209Q) # !S1L1688Q;

--Y1L1012 is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|process4~74 at LC_X28_Y21_N0

--operation mode is normal

Y1L1012 = S1L1642Q & (S1L1609Q # !S1L1618Q) # !Y1L193;

--Y1L1013 is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|process4~75 at LC_X33_Y22_N4

--operation mode is normal

Y1L1013 = Y1L1011 & !Y1L146 & Y1L1012 & !S1L1602Q;

--Y1L693Q is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_avalon_slave_arb_share_counter[0]~603 at LC_X33_Y22_N4

--operation mode is normal

Y1L693Q = DFFEAS(Y1L1013, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--Y1L1014 is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|process4~76 at LC_X31_Y21_N7

--operation mode is normal

Y1L1014 = Y1L1013 # !Y1L718;

--Y1L817Q is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_avalon_slave_slavearbiterlockenable~197 at LC_X31_Y21_N7

--operation mode is normal

Y1L817Q = DFFEAS(Y1L1014, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--Y1L188 is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|cpu_instruction_master_read_data_valid_lan91c111_s1_shift_register_in~15 at LC_X30_Y26_N3

--operation mode is normal

Y1L188 = Y1L192 & !Y1L874 & T1L1 # !Y1L192 & (Y1L190);

--Y1L721 is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_avalon_slave_end_xfer~79 at LC_X31_Y24_N9

--operation mode is normal

Y1L721 = !Y1L188 & (Y1L177 # S1L1686Q & Y1L736);

--Y1L199Q is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_ext_ram_bus_avalon_slave_end_xfer~4 at LC_X31_Y24_N9

--operation mode is normal

Y1L199Q = DFFEAS(Y1L721, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--Y1L181 is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|cpu_instruction_master_read_data_valid_ext_flash_s1_shift_register_in~16 at LC_X32_Y24_N5

--operation mode is normal

Y1L181 = Y1L118 & (Y1L653Q # Y1L718);

--Y1L201Q is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_ext_ram_bus_avalon_slave_end_xfer~5 at LC_X32_Y24_N5

--operation mode is normal

Y1L201Q = DFFEAS(Y1L181, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--Y1L206Q is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_ext_ram_bus_avalon_slave_end_xfer~8 at LC_X31_Y21_N3

--operation mode is normal

Y1L206Q_lut_out = Y1L721 # !Y1L181 & (Y1L372 # Y1L204);

Y1L206Q = DFFEAS(Y1L206Q_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--Y1_cpu_data_master_requests_ext_ram_s1 is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|cpu_data_master_requests_ext_ram_s1 at LC_X34_Y21_N7

--operation mode is normal

Y1_cpu_data_master_requests_ext_ram_s1 = S1L209Q & (S1L1688Q & !S1L1782Q);

--Y1L3 is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|A_WE_StdLogicVector~4279 at LC_X32_Y20_N4

--operation mode is normal

Y1L3 = Y1L919Q & (Y1L206Q # Y1L726 # Y1L718);

--Y1L915Q is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|last_cycle_cpu_data_master_granted_slave_ext_ram_s1~8 at LC_X32_Y20_N4

--operation mode is normal

Y1L915Q = DFFEAS(Y1L3, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--Y1L694Q is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_avalon_slave_arb_share_counter[0]~604 at LC_X27_Y25_N2

--operation mode is normal

Y1L694Q_lut_out = !Y1L737 & !Y1L916 & !Y1L587;

Y1L694Q = DFFEAS(Y1L694Q_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--Y1L695Q is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_avalon_slave_arb_share_counter[0]~605 at LC_X27_Y25_N1

--operation mode is normal

Y1L695Q_lut_out = !Y1L742 & (!Y1L14 & !Y1L176);

Y1L695Q = DFFEAS(Y1L695Q_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--Y1L711 is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_avalon_slave_arb_winner~0 at LC_X28_Y23_N2

--operation mode is normal

Y1L711 = !Y1L726 & (Y1L916 # Y1L736 # !Y1L713);

--Y1L805Q is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_avalon_slave_saved_chosen_master_vector[5]~654 at LC_X28_Y23_N2

--operation mode is normal

Y1L805Q = DFFEAS(Y1L711, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--Y1L917Q is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|last_cycle_cpu_data_master_granted_slave_ext_ram_s1~10 at LC_X32_Y20_N0

--operation mode is normal

Y1L917Q_lut_out = Y1L3 # Y1L711 & (Y1L96) # !Y1L711 & Y1L803;

Y1L917Q = DFFEAS(Y1L917Q_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--Y1L781Q is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_avalon_slave_saved_chosen_master_vector[3]~683 at LC_X29_Y25_N1

--operation mode is normal

Y1L781Q_lut_out = Y1L208 & (Y1L799) # !Y1L208 & Y1L903;

Y1L781Q = DFFEAS(Y1L781Q_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--Y1_ext_ram_bus_avalon_slave_arbitration_holdoff_internal is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_avalon_slave_arbitration_holdoff_internal at LC_X28_Y24_N7

--operation mode is normal

Y1_ext_ram_bus_avalon_slave_arbitration_holdoff_internal = !Y1L653Q & !Y1L726 & (!Y1L716 # !T1L1);

--Y1L970Q is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|last_cycle_cpu_instruction_master_granted_slave_lan91c111_s1~6 at LC_X28_Y24_N7

--operation mode is normal

Y1L970Q = DFFEAS(Y1_ext_ram_bus_avalon_slave_arbitration_holdoff_internal, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--Y1L753Q is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_avalon_slave_saved_chosen_master_vector[1]~746 at LC_X31_Y24_N5

--operation mode is normal

Y1L753Q_lut_out = Y1L654 & Y1L770 # !Y1L654 & (Y1L942);

Y1L753Q = DFFEAS(Y1L753Q_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--NB1L24 is std_1c20:inst|sdram_s1_arbitrator:the_sdram_s1|cpu_instruction_master_granted_sdram_s1~85 at LC_X24_Y23_N5

--operation mode is normal

NB1L24 = NB1L25 & (NB1_sdram_s1_arb_addend[1] & !NB1L22 # !NB1_sdram_s1_arb_addend[0]);

--WE1L38 is std_1c20:inst|sdram_s1_arbitrator:the_sdram_s1|rdv_fifo_for_cpu_instruction_master_to_sdram_s1_module:rdv_fifo_for_cpu_instruction_master_to_sdram_s1|stage_0~5 at LC_X24_Y25_N1

--operation mode is normal

WE1L38 = WE1_full_1 & WE1L41Q # !WE1_full_1 & (NB1L24);

--WE1L64 is std_1c20:inst|sdram_s1_arbitrator:the_sdram_s1|rdv_fifo_for_cpu_instruction_master_to_sdram_s1_module:rdv_fifo_for_cpu_instruction_master_to_sdram_s1|updated_one_count~70 at LC_X24_Y24_N7

--operation mode is normal

WE1L64 = KB1_za_valid & WE1L37Q;

--WE1L1 is std_1c20:inst|sdram_s1_arbitrator:the_sdram_s1|rdv_fifo_for_cpu_instruction_master_to_sdram_s1_module:rdv_fifo_for_cpu_instruction_master_to_sdram_s1|A_WE_StdLogicVector~1213 at LC_X25_Y24_N6

--operation mode is normal

WE1L1 = WE1_how_many_ones[2] & WE1_how_many_ones[1] & WE1_how_many_ones[0] & !WE1L64 # !WE1_how_many_ones[2] & !WE1_how_many_ones[1] & !WE1_how_many_ones[0] & WE1L64;

--WE1L2 is std_1c20:inst|sdram_s1_arbitrator:the_sdram_s1|rdv_fifo_for_cpu_instruction_master_to_sdram_s1_module:rdv_fifo_for_cpu_instruction_master_to_sdram_s1|A_WE_StdLogicVector~1214 at LC_X25_Y24_N2

--operation mode is normal

WE1_how_many_ones[3]_qfbk = WE1_how_many_ones[3];

WE1L2 = WE1_how_many_ones[3]_qfbk $ (WE1L1 & (WE1_how_many_ones[2] $ !WE1L65));

--WE1_how_many_ones[3] is std_1c20:inst|sdram_s1_arbitrator:the_sdram_s1|rdv_fifo_for_cpu_instruction_master_to_sdram_s1_module:rdv_fifo_for_cpu_instruction_master_to_sdram_s1|how_many_ones[3] at LC_X25_Y24_N2

--operation mode is normal

WE1_how_many_ones[3] = DFFEAS(WE1L2, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , WE1L33, , , , );

--WE1L3 is std_1c20:inst|sdram_s1_arbitrator:the_sdram_s1|rdv_fifo_for_cpu_instruction_master_to_sdram_s1_module:rdv_fifo_for_cpu_instruction_master_to_sdram_s1|A_WE_StdLogicVector~1215 at LC_X25_Y24_N7

--operation mode is normal

WE1_how_many_ones[2]_qfbk = WE1_how_many_ones[2];

WE1L3 = WE1_how_many_ones[2]_qfbk $ (WE1L5 & (WE1_how_many_ones[1] $ !WE1L65));

--WE1_how_many_ones[2] is std_1c20:inst|sdram_s1_arbitrator:the_sdram_s1|rdv_fifo_for_cpu_instruction_master_to_sdram_s1_module:rdv_fifo_for_cpu_instruction_master_to_sdram_s1|how_many_ones[2] at LC_X25_Y24_N7

--operation mode is normal

WE1_how_many_ones[2] = DFFEAS(WE1L3, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , WE1L33, , , , );

--WE1L4 is std_1c20:inst|sdram_s1_arbitrator:the_sdram_s1|rdv_fifo_for_cpu_instruction_master_to_sdram_s1_module:rdv_fifo_for_cpu_instruction_master_to_sdram_s1|A_WE_StdLogicVector~1216 at LC_X25_Y24_N5

--operation mode is normal

WE1_how_many_ones[1]_qfbk = WE1_how_many_ones[1];

WE1L4 = WE1_how_many_ones[1]_qfbk $ (WE1L64 & !WE1_how_many_ones[0] & !WE1L65 # !WE1L64 & WE1_how_many_ones[0] & WE1L65);

--WE1_how_many_ones[1] is std_1c20:inst|sdram_s1_arbitrator:the_sdram_s1|rdv_fifo_for_cpu_instruction_master_to_sdram_s1_module:rdv_fifo_for_cpu_instruction_master_to_sdram_s1|how_many_ones[1] at LC_X25_Y24_N5

--operation mode is normal

WE1_how_many_ones[1] = DFFEAS(WE1L4, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , WE1L33, , , , );

--NB1L20 is std_1c20:inst|sdram_s1_arbitrator:the_sdram_s1|cpu_data_master_granted_sdram_s1~36 at LC_X24_Y22_N5

--operation mode is normal

NB1L20 = NB1L22 & (NB1_sdram_s1_arb_addend[1] # !NB1L25 & !NB1_sdram_s1_arb_addend[0]);

--NB1L37 is std_1c20:inst|sdram_s1_arbitrator:the_sdram_s1|module_input5~34 at LC_X24_Y24_N6

--operation mode is normal

NB1L37 = !TE1L151 & (NB1L24 # S1_internal_d_read & NB1L20);

--WE1L33 is std_1c20:inst|sdram_s1_arbitrator:the_sdram_s1|rdv_fifo_for_cpu_instruction_master_to_sdram_s1_module:rdv_fifo_for_cpu_instruction_master_to_sdram_s1|process15~0 at LC_X24_Y24_N0

--operation mode is normal

WE1L33 = KB1_za_valid # !TE1L151 & (NB1L24 # WE1L35);

--U1L259 is std_1c20:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|r_1~20 at LC_X27_Y24_N6

--operation mode is normal

U1L259 = Y1L653Q & !Y1L976 # !Y1L874;

--U1L12Q is std_1c20:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_read_but_no_slave_selected~60 at LC_X27_Y24_N1

--operation mode is normal

U1L12Q_lut_out = U1L259 & U1L164 & U1L258 & U1L257;

U1L12Q = DFFEAS(U1L12Q_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--U1L242 is std_1c20:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|p1_cpu_instruction_master_latency_counter[1]~151 at LC_X24_Y18_N9

--operation mode is normal

U1L242 = !S1_ic_fill_tag[9] & !S1_ic_fill_tag[10] & !S1L1609Q;

--U1L243 is std_1c20:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|p1_cpu_instruction_master_latency_counter[1]~152 at LC_X25_Y22_N1

--operation mode is normal

U1L243 = !S1L1636Q & !S1L1633Q & (U1L242 # !S1L1642Q);

--U1L244 is std_1c20:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|p1_cpu_instruction_master_latency_counter[1]~153 at LC_X28_Y22_N7

--operation mode is normal

U1L244 = U1L243 # S1L1589Q & !S1L1597Q & S1L1616Q;

--U1L236Q is std_1c20:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|internal_cpu_instruction_master_latency_counter[1]~23 at LC_X28_Y22_N7

--operation mode is normal

U1L236Q = DFFEAS(U1L244, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--U1L245 is std_1c20:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|p1_cpu_instruction_master_latency_counter[1]~154 at LC_X29_Y22_N2

--operation mode is normal

U1L245 = U1L238Q & (U1_internal_cpu_instruction_master_latency_counter[0]);

--U1L237Q is std_1c20:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|internal_cpu_instruction_master_latency_counter[1]~24 at LC_X29_Y22_N2

--operation mode is normal

U1L237Q = DFFEAS(U1L245, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--Y1L507 is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_avalon_slave_arb_addend[0]~685 at LC_X31_Y25_N3

--operation mode is normal

Y1L507 = !Y1L200 & (Y1L181 # !Y1L7) # !Y1L177;

--Y1L588Q is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_avalon_slave_arb_addend[0]~869 at LC_X31_Y25_N3

--operation mode is normal

Y1L588Q = DFFEAS(Y1L507, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--Y1L5 is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|A_WE_StdLogicVector~4283 at LC_X30_Y25_N8

--operation mode is normal

Y1L5 = Y1L589Q & (Y1L524Q # Y1L591Q # !Y1L596Q);

--Y1L798Q is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_avalon_slave_saved_chosen_master_vector[4]~692 at LC_X31_Y22_N9

--operation mode is normal

Y1L798Q_lut_out = Y1L512 & (Y1L96) # !Y1L512 & Y1L681;

Y1L798Q = DFFEAS(Y1L798Q_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--Y1L768Q is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_avalon_slave_saved_chosen_master_vector[2]~691 at LC_X29_Y25_N4

--operation mode is normal

Y1L768Q_lut_out = Y1L208 & (Y1L787) # !Y1L208 & Y1L629;

Y1L768Q = DFFEAS(Y1L768Q_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--Y1L741Q is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_avalon_slave_saved_chosen_master_vector[0]~745 at LC_X30_Y21_N4

--operation mode is normal

Y1L741Q_lut_out = Y1L512 & Y1L755 # !Y1L512 & (Y1L973);

Y1L741Q = DFFEAS(Y1L741Q_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--T1L522 is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|pre_dbs_count_enable~74 at LC_X28_Y20_N0

--operation mode is normal

T1L522 = S1L1689Q & !T1L445Q & !T1_internal_cpu_data_master_no_byte_enables_and_last_term & !S1L2162Q;

--U1L224 is std_1c20:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|internal_cpu_instruction_master_dbs_address[1]~50 at LC_X31_Y27_N8

--operation mode is normal

U1L224 = !Y1L380 & !Y1L396Q & Y1L1010 & Y1L653Q;

--T1L523 is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|pre_dbs_count_enable~75 at LC_X29_Y26_N6

--operation mode is normal

T1L523 = U1L224 & Y1L100 & (Y1L34 # Y1L37);

--T1L524 is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|pre_dbs_count_enable~76 at LC_X29_Y26_N9

--operation mode is normal

T1L524 = Y1_cpu_data_master_read_data_valid_ext_flash_s1_shift_register[1] # S1_internal_d_write & (T1L522 # T1L523);

--T1L2 is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|A_WE_StdLogicVector~1428 at LC_X24_Y23_N0

--operation mode is normal

T1L2 = TE1L151 # !NB1_sdram_s1_arb_addend[1] & (NB1L25 # NB1_sdram_s1_arb_addend[0]);

--T1L3 is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|A_WE_StdLogicVector~1429 at LC_X24_Y23_N1

--operation mode is normal

T1L3 = S1_internal_d_read & (NB1L22 # !T1L1) # !S1_internal_d_read & NB1L22 & (T1L2);

--X1L1 is std_1c20:inst|epcs_controller_epcs_control_port_arbitrator:the_epcs_controller_epcs_control_port|Add2~344 at LC_X33_Y22_N1

--operation mode is normal

X1L1 = X1L6 & S1L207Q & K1L3 & X1L3;

--S1L522Q is std_1c20:inst|cpu:the_cpu|d_readdata_d1[8]~107 at LC_X39_Y19_N2

--operation mode is normal

S1L522Q = AMPP_FUNCTION(QC2__clk0, K1L3, V1L8, F1_data_out);

--V1L3 is std_1c20:inst|cpu_jtag_debug_module_arbitrator:the_cpu_jtag_debug_module|Add2~346 at LC_X35_Y24_N7

--operation mode is normal

V1L3 = !V1L5 & V1L8 & K1L3 & !V1L39;

--T1L528 is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|r_1~238 at LC_X32_Y24_N6

--operation mode is normal

T1L528 = T1_internal_cpu_data_master_dbs_address[1] & (T1_internal_cpu_data_master_dbs_address[0]);

--T1L529 is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|r_1~239 at LC_X32_Y24_N2

--operation mode is normal

T1L529 = T1L528 & (Y1_cpu_data_master_read_data_valid_ext_flash_s1_shift_register[0] # !S1L2177Q & S1_internal_d_write);

--Y1L382Q is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_flash_s1_wait_counter[0]~97 at LC_X30_Y27_N5

--operation mode is normal

Y1L382Q_lut_out = Y1_ext_flash_s1_wait_counter[1] # Y1L396Q # Y1L387Q;

Y1L382Q = DFFEAS(Y1L382Q_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--T1L530 is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|r_1~240 at LC_X31_Y26_N1

--operation mode is normal

T1L530 = Y1L380 & T1L531 & T1L528 # !S1_internal_d_write;

--T1L6 is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|A_WE_StdLogicVector~1432 at LC_X30_Y26_N5

--operation mode is normal

T1L6 = Y1L100 & (!Y1L34 & !Y1L37 # !T1L530);

--EB1L20 is std_1c20:inst|lcd_display_control_slave_arbitrator:the_lcd_display_control_slave|Equal1~75 at LC_X35_Y22_N9

--operation mode is normal

EB1L20 = EB1L31 & EB1_lcd_display_control_slave_wait_counter[0] & !EB1_lcd_display_control_slave_wait_counter[3] & EB1L37;

--T1L532 is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|r_2~102 at LC_X36_Y25_N4

--operation mode is normal

T1L532 = UB1L5 & !EB1L20 & UB1L6 & T1L534;

--Y1L977 is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|LessThan1~91 at LC_X32_Y27_N9

--operation mode is normal

Y1L977 = !Y1_lan91c111_s1_wait_counter[3] & !Y1L882 & !Y1L889;

--Y1L885Q is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|lan91c111_s1_wait_counter[1]~103 at LC_X32_Y27_N9

--operation mode is normal

Y1L885Q = DFFEAS(Y1L977, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--T1L7 is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|A_WE_StdLogicVector~1433 at LC_X32_Y26_N6

--operation mode is normal

T1L7 = S1_internal_d_write & (!Y1L977 # !Y1L978);

--T1L8 is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|A_WE_StdLogicVector~1434 at LC_X32_Y26_N7

--operation mode is normal

T1L8 = Y1L112 & (T1L7 # !Y1L28 & !Y1L31);

--Y1L115 is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|cpu_data_master_qualified_request_lan91c111_s1~129 at LC_X33_Y22_N6

--operation mode is normal

Y1L115 = Y1L146 & !Y1_cpu_data_master_read_data_valid_lan91c111_s1_shift_register[0];

--T1L9 is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|A_WE_StdLogicVector~1435 at LC_X35_Y22_N2

--operation mode is normal

T1L9 = Y1L112 & (!EB1L20 & EB1L24) # !Y1L112 & (Y1L115 # !EB1L20 & EB1L24);

--UB1L8 is std_1c20:inst|sysid_control_slave_arbitrator:the_sysid_control_slave|cpu_data_master_granted_sysid_control_slave~156 at LC_X34_Y23_N6

--operation mode is normal

UB1L8 = !S1_M_alu_result[9] & !S1_M_alu_result[8];

--K1L4 is std_1c20:inst|clock_0_in_arbitrator:the_clock_0_in|cpu_data_master_requests_clock_0_in~535 at LC_X34_Y22_N0

--operation mode is normal

K1L4 = T1L448Q & !S1L1782Q & !S1L207Q & !S1_M_alu_result[7];

--K1L5 is std_1c20:inst|clock_0_in_arbitrator:the_clock_0_in|cpu_data_master_requests_clock_0_in~536 at LC_X34_Y23_N0

--operation mode is normal

K1L5 = !S1L1756Q & K1L4 & !S1_M_alu_result[6] & UB1L8;

--K1L6 is std_1c20:inst|clock_0_in_arbitrator:the_clock_0_in|cpu_data_master_requests_clock_0_in~537 at LC_X34_Y23_N9

--operation mode is normal

K1L6 = UB1L2 & UB1L3 & K1L11 & K1L9;

--NC1_slave_state[0] is std_1c20:inst|clock_1:the_clock_1|clock_1_slave_FSM:slave_FSM|slave_state[0] at LC_X47_Y28_N5

--operation mode is normal

NC1_slave_state[0]_lut_out = !NC1L8 & (NC1_slave_state[2] # NC1L10 & !NC1L9);

NC1_slave_state[0] = DFFEAS(NC1_slave_state[0]_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--NC1_slave_state[1] is std_1c20:inst|clock_1:the_clock_1|clock_1_slave_FSM:slave_FSM|slave_state[1] at LC_X47_Y28_N2

--operation mode is normal

NC1_slave_state[1]_lut_out = !NC1L6 & (NC1_slave_state[1] & NC1_slave_state[0] # !NC1_slave_state[1] & !NC1_slave_state[0] & N1L1);

NC1_slave_state[1] = DFFEAS(NC1_slave_state[1]_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--T1L10 is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|A_WE_StdLogicVector~1436 at LC_X47_Y28_N6

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

MC2_data_in_d1_qfbk = MC2_data_in_d1;

T1L10 = !NC1_slave_state[1] & NC1_slave_state[0] & (GC1_data_out $ !MC2_data_in_d1_qfbk);

--MC2_data_in_d1 is std_1c20:inst|clock_1:the_clock_1|clock_1_edge_to_pulse:write_done_edge_to_pulse|data_in_d1 at LC_X47_Y28_N6

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

MC2_data_in_d1 = DFFEAS(T1L10, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , GC1_data_out, , , VCC);

--NC1_slave_state[2] is std_1c20:inst|clock_1:the_clock_1|clock_1_slave_FSM:slave_FSM|slave_state[2] at LC_X47_Y27_N4

--operation mode is normal

NC1_slave_state[2]_lut_out = !NC1L5 & !NC1_slave_state[1] & (NC1_slave_state[2] # NC1L4);

NC1_slave_state[2] = DFFEAS(NC1_slave_state[2]_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--NC1L10 is std_1c20:inst|clock_1:the_clock_1|clock_1_slave_FSM:slave_FSM|Mux3~68 at LC_X47_Y28_N0

--operation mode is normal

NC1L10 = NC1_slave_state[1] $ !NC1_slave_state[0];

--NC1L7 is std_1c20:inst|clock_1:the_clock_1|clock_1_slave_FSM:slave_FSM|Mux2~232 at LC_X47_Y28_N8

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

MC1_data_in_d1_qfbk = MC1_data_in_d1;

NC1L7 = NC1_slave_state[1] & (MC1_data_in_d1_qfbk $ FC1_data_out);

--MC1_data_in_d1 is std_1c20:inst|clock_1:the_clock_1|clock_1_edge_to_pulse:read_done_edge_to_pulse|data_in_d1 at LC_X47_Y28_N8

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

MC1_data_in_d1 = DFFEAS(NC1L7, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , FC1_data_out, , , VCC);

--EC1_slave_state[0] is std_1c20:inst|clock_0:the_clock_0|clock_0_slave_FSM:slave_FSM|slave_state[0] at LC_X43_Y27_N9

--operation mode is normal

EC1_slave_state[0]_lut_out = !EC1L8 & (EC1_slave_state[2] # EC1L10 & !EC1L9);

EC1_slave_state[0] = DFFEAS(EC1_slave_state[0]_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--EC1_slave_state[1] is std_1c20:inst|clock_0:the_clock_0|clock_0_slave_FSM:slave_FSM|slave_state[1] at LC_X43_Y27_N1

--operation mode is normal

EC1_slave_state[1]_lut_out = !EC1L6 & (EC1_slave_state[1] & (EC1_slave_state[0]) # !EC1_slave_state[1] & K1L1 & !EC1_slave_state[0]);

EC1_slave_state[1] = DFFEAS(EC1_slave_state[1]_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--T1L12 is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|A_WE_StdLogicVector~1438 at LC_X43_Y27_N5

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

DC2_data_in_d1_qfbk = DC2_data_in_d1;

T1L12 = EC1_slave_state[0] & !EC1_slave_state[1] & (YB1_data_out $ !DC2_data_in_d1_qfbk);

--DC2_data_in_d1 is std_1c20:inst|clock_0:the_clock_0|clock_0_edge_to_pulse:write_done_edge_to_pulse|data_in_d1 at LC_X43_Y27_N5

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

DC2_data_in_d1 = DFFEAS(T1L12, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , YB1_data_out, , , VCC);

--EC1_slave_state[2] is std_1c20:inst|clock_0:the_clock_0|clock_0_slave_FSM:slave_FSM|slave_state[2] at LC_X42_Y27_N7

--operation mode is normal

EC1_slave_state[2]_lut_out = !EC1_slave_state[1] & !EC1L5 & (EC1_slave_state[2] # EC1L4);

EC1_slave_state[2] = DFFEAS(EC1_slave_state[2]_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--EC1L10 is std_1c20:inst|clock_0:the_clock_0|clock_0_slave_FSM:slave_FSM|Mux3~68 at LC_X43_Y27_N2

--operation mode is normal

EC1L10 = EC1_slave_state[0] $ !EC1_slave_state[1];

--EC1L7 is std_1c20:inst|clock_0:the_clock_0|clock_0_slave_FSM:slave_FSM|Mux2~232 at LC_X43_Y27_N6

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

DC1_data_in_d1_qfbk = DC1_data_in_d1;

EC1L7 = EC1_slave_state[1] & (XB1_data_out $ DC1_data_in_d1_qfbk);

--DC1_data_in_d1 is std_1c20:inst|clock_0:the_clock_0|clock_0_edge_to_pulse:read_done_edge_to_pulse|data_in_d1 at LC_X43_Y27_N6

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

DC1_data_in_d1 = DFFEAS(EC1L7, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , XB1_data_out, , , VCC);

--T1L15 is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|A_WE_StdLogicVector~1441 at LC_X34_Y25_N4

--operation mode is normal

T1L15 = T1L22 # K1L6 & T1L28;

--UB1L9 is std_1c20:inst|sysid_control_slave_arbitrator:the_sysid_control_slave|cpu_data_master_granted_sysid_control_slave~157 at LC_X41_Y25_N1

--operation mode is normal

UB1L9 = S1L1743Q & UB1L5 & UB1L6 & UB1L7;

--CB1L2 is std_1c20:inst|jtag_uart_avalon_jtag_slave_arbitrator:the_jtag_uart_avalon_jtag_slave|cpu_data_master_requests_jtag_uart_avalon_jtag_slave~554 at LC_X36_Y21_N4

--operation mode is normal

CB1L2 = !S1_M_alu_result[3] & S1_M_alu_result[4] & (S1_internal_d_write # S1_internal_d_read);

--BB1L69 is std_1c20:inst|jtag_uart:the_jtag_uart|process2~46 at LC_X36_Y25_N0

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

BB1_internal_av_waitrequest_qfbk = BB1_internal_av_waitrequest;

BB1L69 = !BB1_internal_av_waitrequest_qfbk & (!S1_internal_d_write & !S1_internal_d_read # !T1_internal_cpu_data_master_waitrequest);

--BB1_internal_av_waitrequest is std_1c20:inst|jtag_uart:the_jtag_uart|internal_av_waitrequest at LC_X36_Y25_N0

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

BB1_internal_av_waitrequest = DFFEAS(BB1L69, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , BB1L70, , , VCC);

--BB1L70 is std_1c20:inst|jtag_uart:the_jtag_uart|process2~47 at LC_X36_Y25_N9

--operation mode is normal

BB1L70 = UB1L5 & CB1L2 & UB1L7 & BB1L73;

--T1L16 is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|A_WE_StdLogicVector~1442 at LC_X33_Y21_N9

--operation mode is normal

T1L16 = T1_internal_cpu_data_master_waitrequest # !S1_internal_d_write & !S1_internal_d_read;

--VE1L25 is std_1c20:inst|sdram_s1_arbitrator:the_sdram_s1|rdv_fifo_for_cpu_data_master_to_sdram_s1_module:rdv_fifo_for_cpu_data_master_to_sdram_s1|stage_0~579 at LC_X24_Y25_N9

--operation mode is normal

VE1L25 = WE1_full_1 & VE1L28Q # !WE1_full_1 & (NB1L20);

--T1L17 is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|A_WE_StdLogicVector~1443 at LC_X24_Y24_N2

--operation mode is normal

T1L17 = !VE1L8Q # !VE1L24Q # !KB1_za_valid;

--T1L18 is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|A_WE_StdLogicVector~1444 at LC_X24_Y24_N8

--operation mode is normal

T1L18 = T1L16 # S1L1693Q & T1L17 & !NB1L22;

--F1_data_in_d1 is std_1c20:inst|std_1c20_reset_sysclk2_domain_synch_module:std_1c20_reset_sysclk2_domain_synch|data_in_d1 at LC_X8_Y16_N2

--operation mode is normal

F1_data_in_d1_lut_out = VCC;

F1_data_in_d1 = DFFEAS(F1_data_in_d1_lut_out, GLOBAL(QC2__clk0), !B1L1, , , , , , );

--LB1_count_done is std_1c20:inst|sdram_pll:the_sdram_pll|count_done at LC_X18_Y25_N1

--operation mode is normal

LB1_count_done_lut_out = LB1_count_done # LB1_countup[5] & LB1L35 & LB1_countup[4];

LB1_count_done = DFFEAS(LB1_count_done_lut_out, GLOBAL(PLD_CLKFB), LB1_not_areset, , , , , , );

--Q1_count_done is std_1c20:inst|connector_pll:the_connector_pll|count_done at LC_X18_Y24_N3

--operation mode is normal

Q1_count_done_lut_out = Q1_count_done # Q1_countup[5] & Q1L35 & Q1_countup[4];

Q1_count_done = DFFEAS(Q1_count_done_lut_out, GLOBAL(PLD_CLOCKINPUT[1]), Q1_not_areset, , , , , , );

--B1L1 is std_1c20:inst|reset_n_sources~23 at LC_X18_Y24_N2

--operation mode is normal

B1L1 = JD1_resetrequest # !PLD_CLEAR_N # !Q1_count_done # !LB1_count_done;

--Y1L399Q is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_flash_s1_wait_counter[3]~89 at LC_X30_Y27_N0

--operation mode is normal

Y1L399Q_lut_out = Y1_ext_ram_bus_avalon_slave_begins_xfer & (Y1L372 # Y1L122 # Y1L770);

Y1L399Q = DFFEAS(Y1L399Q_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--Y1L388Q is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_flash_s1_wait_counter[2]~92 at LC_X31_Y28_N0

--operation mode is normal

Y1L388Q_lut_out = Y1L380 # Y1_ext_flash_s1_wait_counter[1];

Y1L388Q = DFFEAS(Y1L388Q_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--Y1L373 is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_flash_s1_counter_load_value[1]~170 at LC_X31_Y27_N7

--operation mode is normal

Y1L373 = Y1_ext_flash_s1_wait_counter[1] & (Y1L380) # !Y1_ext_flash_s1_wait_counter[1] & !Y1L380 & (Y1L387Q # Y1L396Q);

--Y1L878Q is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|lan91c111_s1_wait_counter[0]~113 at LC_X32_Y26_N2

--operation mode is normal

Y1L878Q_lut_out = Y1_ext_ram_bus_avalon_slave_begins_xfer & (Y1L177 # S1_internal_d_read & Y1L739);

Y1L878Q = DFFEAS(Y1L878Q_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--Y1L54 is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|Add3~133 at LC_X32_Y27_N5

--operation mode is normal

Y1L54 = Y1_lan91c111_s1_wait_counter[3] & (Y1L978 # Y1L882 # Y1L889);

--Y1L725 is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_avalon_slave_end_xfer~81 at LC_X32_Y26_N8

--operation mode is normal

Y1L725 = S1L1686Q & Y1L112 & (Y1L28 # Y1L31);

--Y1L886Q is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|lan91c111_s1_wait_counter[1]~104 at LC_X32_Y27_N4

--operation mode is normal

Y1L886Q_lut_out = !Y1L177 & (!Y1L739 # !S1L1686Q) # !Y1_ext_ram_bus_avalon_slave_begins_xfer;

Y1L886Q = DFFEAS(Y1L886Q_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--Y1L892Q is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|lan91c111_s1_wait_counter[2]~110 at LC_X32_Y27_N7

--operation mode is normal

Y1L892Q_lut_out = !Y1L978 & (!Y1L882);

Y1L892Q = DFFEAS(Y1L892Q_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--KB1L519 is std_1c20:inst|sdram:the_sdram|Mux24~1465 at LC_X12_Y22_N7

--operation mode is normal

KB1L519 = KB1_m_state[6] & (KB1_m_state[4] # !KB1L486 # !KB1L518);

--KB1L253 is std_1c20:inst|sdram:the_sdram|m_count~775 at LC_X11_Y24_N8

--operation mode is normal

KB1L253 = KB1_init_done & KB1_refresh_request;

--KB1L520 is std_1c20:inst|sdram:the_sdram|Mux24~1466 at LC_X11_Y23_N9

--operation mode is normal

KB1L520 = KB1L857 & KB1L253 & !KB1_m_state[0] & KB1L705;

--KB1L521 is std_1c20:inst|sdram:the_sdram|Mux24~1467 at LC_X13_Y23_N5

--operation mode is normal

KB1L521 = !KB1_m_state[4] & KB1_m_state[0] & !KB1_m_state[8] & !KB1_m_state[3];

--KB1L522 is std_1c20:inst|sdram:the_sdram|Mux24~1468 at LC_X14_Y23_N2

--operation mode is normal

KB1L522 = KB1_m_state[2] & !KB1_m_state[5] & KB1_m_next[1] # !KB1_m_state[2] & KB1_m_state[5];

--KB1_m_count[2] is std_1c20:inst|sdram:the_sdram|m_count[2] at LC_X12_Y24_N7

--operation mode is normal

KB1_m_count[2]_lut_out = KB1_m_state[8] & KB1_m_count[2] & (KB1L617 # KB1L629) # !KB1_m_state[8] & (KB1L629);

KB1_m_count[2] = DFFEAS(KB1_m_count[2]_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , !KB1_m_state[6], , , , );

--KB1_m_count[1] is std_1c20:inst|sdram:the_sdram|m_count[1] at LC_X11_Y24_N0

--operation mode is normal

KB1_m_count[1]_lut_out = KB1_m_state[4] & KB1_m_count[1] & (KB1L657 # KB1L647) # !KB1_m_state[4] & (KB1L657);

KB1_m_count[1] = DFFEAS(KB1_m_count[1]_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , !KB1_m_state[6], , , , );

--KB1L162 is std_1c20:inst|sdram:the_sdram|LessThan1~56 at LC_X12_Y23_N7

--operation mode is normal

KB1L162 = KB1_m_count[2] # KB1_m_count[1];

--KB1L945 is std_1c20:inst|sdram:the_sdram|Mux118~1217 at LC_X11_Y23_N4

--operation mode is normal

KB1L945 = !KB1_m_state[7] & !KB1_m_state[2] & KB1_m_state[0] & !KB1_m_state[8];

--KB1L551 is std_1c20:inst|sdram:the_sdram|Mux29~1325 at LC_X11_Y23_N8

--operation mode is normal

KB1L551 = KB1_m_state[1] & (!KB1L857 # !KB1L945 # !KB1L550);

--KB1L552 is std_1c20:inst|sdram:the_sdram|Mux29~1326 at LC_X12_Y22_N1

--operation mode is normal

KB1L552 = !KB1_m_state[7] & !KB1_m_state[6] & (!KB1_m_state[5]);

--KB1L512 is std_1c20:inst|sdram:the_sdram|Mux22~1322 at LC_X14_Y23_N0

--operation mode is normal

KB1L512 = KB1_m_state[2] & !KB1_m_count[1] & !KB1_m_count[2];

--KB1L525 is std_1c20:inst|sdram:the_sdram|Mux25~1260 at LC_X14_Y23_N7

--operation mode is normal

KB1L525 = KB1_m_next[1] & KB1L512 & KB1L521;

--KB1L672 is std_1c20:inst|sdram:the_sdram|Mux44~1259 at LC_X16_Y22_N0

--operation mode is normal

KB1L672 = !KB1_m_state[4] & !KB1_m_state[3] & (TE1_entries[0] # TE1_entries[1]);

--KB1L553 is std_1c20:inst|sdram:the_sdram|Mux29~1327 at LC_X13_Y22_N1

--operation mode is normal

KB1L553 = !KB1_m_state[0] & !KB1_m_state[2] & !KB1_m_state[8];

--KB1L554 is std_1c20:inst|sdram:the_sdram|Mux29~1328 at LC_X13_Y22_N9

--operation mode is normal

KB1L554 = !KB1_refresh_request & KB1_init_done & KB1L672 & KB1L553;

--KB1L984 is std_1c20:inst|sdram:the_sdram|Mux154~548 at LC_X14_Y22_N6

--operation mode is normal

KB1L984 = !KB1_m_state[1] & !KB1_m_state[6] & !KB1_m_state[5] & !KB1_m_state[7];

--KB1L1011 is std_1c20:inst|sdram:the_sdram|refresh_request~105 at LC_X16_Y22_N5

--operation mode is normal

KB1L1011 = !TE1_entries[0] & !TE1_entries[1] & !KB1_refresh_request;

--KB1L513 is std_1c20:inst|sdram:the_sdram|Mux22~1323 at LC_X15_Y22_N1

--operation mode is normal

KB1L513 = !KB1_m_state[2] & KB1L744 & (KB1L991 # !TE1L152);

--KB1L514 is std_1c20:inst|sdram:the_sdram|Mux22~1324 at LC_X15_Y22_N2

--operation mode is normal

KB1L514 = KB1_m_state[8] & (KB1L773) # !KB1_m_state[8] & (KB1L513 # KB1L516 & KB1L773);

--KB1L526 is std_1c20:inst|sdram:the_sdram|Mux25~1261 at LC_X14_Y23_N9

--operation mode is normal

KB1L526 = KB1_m_state[8] # KB1_m_count[1] # KB1_m_state[6] # KB1_m_count[2];

--KB1L660 is std_1c20:inst|sdram:the_sdram|Mux42~1480 at LC_X13_Y23_N7

--operation mode is normal

KB1L660 = !KB1_m_state[4] & !KB1_m_state[3] & KB1_m_state[0];

--KB1L615 is std_1c20:inst|sdram:the_sdram|Mux40~1466 at LC_X14_Y22_N0

--operation mode is normal

KB1L615 = !KB1_m_state[7] & !KB1_m_state[2] & (!KB1_m_state[1]);

--KB1L527 is std_1c20:inst|sdram:the_sdram|Mux25~1262 at LC_X14_Y23_N6

--operation mode is normal

KB1L527 = KB1_m_state[5] & (KB1L526 # !KB1L660 # !KB1L615);

--KB1L704 is std_1c20:inst|sdram:the_sdram|Mux59~1280 at LC_X13_Y22_N2

--operation mode is normal

KB1L704 = KB1L672 & !KB1_refresh_request;

--KB1L528 is std_1c20:inst|sdram:the_sdram|Mux25~1263 at LC_X13_Y22_N0

--operation mode is normal

KB1L528 = KB1_m_state[8] & KB1L991 & KB1L704 & KB1L496;

--KB1L540 is std_1c20:inst|sdram:the_sdram|Mux28~1626 at LC_X14_Y24_N8

--operation mode is normal

KB1L540 = KB1_m_state[2] & (KB1_m_state[8] # KB1L549 # !KB1L984);

--KB1L541 is std_1c20:inst|sdram:the_sdram|Mux28~1627 at LC_X13_Y24_N4

--operation mode is normal

KB1L541 = !KB1_m_state[2] & KB1_m_state[0] & !KB1_m_state[5];

--KB1L542 is std_1c20:inst|sdram:the_sdram|Mux28~1628 at LC_X13_Y24_N7

--operation mode is normal

KB1L542 = !KB1_m_state[1] & !KB1_m_state[6] & (KB1_refresh_request);

--KB1L543 is std_1c20:inst|sdram:the_sdram|Mux28~1629 at LC_X13_Y24_N2

--operation mode is normal

KB1L543 = !KB1_m_state[3] & !KB1_m_state[7] & KB1_m_state[8] & !KB1_m_state[4];

--KB1L544 is std_1c20:inst|sdram:the_sdram|Mux28~1630 at LC_X16_Y22_N4

--operation mode is normal

KB1L544 = !KB1_m_state[8] & !KB1L991 & TE1L152 & KB1L771;

--KB1L545 is std_1c20:inst|sdram:the_sdram|Mux28~1631 at LC_X13_Y24_N8

--operation mode is normal

KB1L545 = KB1L542 & (KB1L543 # !KB1L501 & KB1L544);

--KB1L546 is std_1c20:inst|sdram:the_sdram|Mux28~1632 at LC_X15_Y24_N0

--operation mode is normal

KB1L546 = !KB1_m_state[3] & !KB1_m_state[4] & !KB1_m_state[7] & !KB1_m_state[1];

--KB1L547 is std_1c20:inst|sdram:the_sdram|Mux28~1633 at LC_X13_Y24_N9

--operation mode is normal

KB1L547 = !KB1_m_state[4] & !KB1_m_state[3] & (KB1_m_state[7] $ KB1_m_state[1]);

--KB1L548 is std_1c20:inst|sdram:the_sdram|Mux28~1634 at LC_X14_Y24_N9

--operation mode is normal

KB1L548 = !KB1_m_state[8] & (KB1_m_state[6] & KB1L546 # !KB1_m_state[6] & (KB1L547));

--KB1L517 is std_1c20:inst|sdram:the_sdram|Mux23~1127 at LC_X14_Y24_N7

--operation mode is normal

KB1L517 = KB1L984 & KB1_m_next[7] & KB1L512 & KB1L521;

--KB1L529 is std_1c20:inst|sdram:the_sdram|Mux26~1231 at LC_X14_Y25_N9

--operation mode is normal

KB1L529 = KB1_m_state[4] & (KB1_m_state[3] # KB1L534 # !KB1L538);

--KB1L530 is std_1c20:inst|sdram:the_sdram|Mux26~1232 at LC_X14_Y23_N5

--operation mode is normal

KB1L530 = !KB1_m_state[8] & KB1_m_state[2] & !KB1_m_count[1] & !KB1_m_count[2];

--KB1L531 is std_1c20:inst|sdram:the_sdram|Mux26~1233 at LC_X14_Y24_N6

--operation mode is normal

KB1L531 = !KB1_m_state[2] & KB1_m_state[8];

--KB1L532 is std_1c20:inst|sdram:the_sdram|Mux26~1234 at LC_X14_Y24_N4

--operation mode is normal

KB1L532 = TE1L152 & !KB1L991 & !KB1_refresh_request & KB1L531;

--TE1L200 is std_1c20:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|rd_data[58]~509 at LC_X16_Y21_N2

--operation mode is normal

TE1L200 = TE1_rd_address & TE1_entry_1[58] # !TE1_rd_address & (TE1_entry_0[58]);

--KB1L533 is std_1c20:inst|sdram:the_sdram|Mux26~1235 at LC_X14_Y25_N3

--operation mode is normal

KB1L533 = KB1_m_next[4] & (KB1L530 # !TE1L200 & KB1L532) # !KB1_m_next[4] & !TE1L200 & KB1L532;

--KB1L646 is std_1c20:inst|sdram:the_sdram|Mux41~1466 at LC_X14_Y25_N6

--operation mode is normal

KB1L646 = KB1_m_state[0] & (!KB1_m_state[3]);

--KB1L535 is std_1c20:inst|sdram:the_sdram|Mux27~1230 at LC_X14_Y25_N7

--operation mode is normal

KB1L535 = KB1_m_state[3] & (KB1_m_state[4] # KB1L534 # !KB1L538);

--KB1L536 is std_1c20:inst|sdram:the_sdram|Mux27~1231 at LC_X14_Y25_N1

--operation mode is normal

KB1L536 = KB1_m_next[3] & (KB1L530 # TE1L200 & KB1L532) # !KB1_m_next[3] & TE1L200 & KB1L532;

--KB1L537 is std_1c20:inst|sdram:the_sdram|Mux27~1232 at LC_X14_Y25_N8

--operation mode is normal

KB1L537 = KB1_m_state[0] & (!KB1_m_state[4]);

--KB1L555 is std_1c20:inst|sdram:the_sdram|Mux30~1231 at LC_X15_Y22_N4

--operation mode is normal

KB1L555 = KB1L984 & !KB1_m_next[0] & KB1L773 & KB1L530;

--KB1L29 is std_1c20:inst|sdram:the_sdram|active_cs_n~289 at LC_X14_Y22_N1

--operation mode is normal

KB1L29 = !KB1_m_state[8] & !KB1_m_state[4] & KB1_init_done & !KB1_m_state[3];

--KB1L30 is std_1c20:inst|sdram:the_sdram|active_cs_n~290 at LC_X15_Y22_N7

--operation mode is normal

KB1L30 = KB1L984 & !KB1_m_state[2] & (KB1L29);

--KB1L673 is std_1c20:inst|sdram:the_sdram|Mux44~1260 at LC_X15_Y22_N6

--operation mode is normal

KB1L673 = !KB1_refresh_request & !KB1_m_state[2] & (KB1L984);

--KB1L674 is std_1c20:inst|sdram:the_sdram|Mux44~1261 at LC_X16_Y22_N1

--operation mode is normal

KB1L674 = KB1_m_state[0] & (KB1_m_state[8]) # !KB1_m_state[0] & KB1_init_done & !KB1_m_state[8];

--KB1L675 is std_1c20:inst|sdram:the_sdram|Mux44~1262 at LC_X16_Y22_N6

--operation mode is normal

KB1L675 = KB1L674 & KB1L672 & (!KB1_m_state[0] # !KB1L991);

--TE1_entry_1[45] is std_1c20:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_1[45] at LC_X18_Y23_N4

--operation mode is normal

TE1_entry_1[45]_lut_out = NB1L20 & S1_M_alu_result[11] # !NB1L20 & (S1L1559Q);

TE1_entry_1[45] = DFFEAS(TE1_entry_1[45]_lut_out, GLOBAL(QC2__clk0), VCC, , TE1L148, , , , );

--KB1L477 is std_1c20:inst|sdram:the_sdram|module_input~21 at LC_X24_Y23_N9

--operation mode is normal

KB1L477 = NB1L24 # NB1L20 & (S1_internal_d_read # S1_internal_d_write);

--TE1_wr_address is std_1c20:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|wr_address at LC_X23_Y23_N3

--operation mode is normal

TE1_wr_address_lut_out = TE1_wr_address $ (KB1L477 & (TE1_entries[0] # !TE1_entries[1]));

TE1_wr_address = DFFEAS(TE1_wr_address_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--KB1L700 is std_1c20:inst|sdram:the_sdram|Mux58~1328 at LC_X18_Y23_N0

--operation mode is normal

KB1L700 = TE1_rd_address & TE1_entry_1[45] # !TE1_rd_address & (TE1_entry_0[45]);

--KB1L677 is std_1c20:inst|sdram:the_sdram|Mux47~1291 at LC_X16_Y22_N2

--operation mode is normal

KB1L677 = !KB1_refresh_request & KB1L771 & TE1L152 & !KB1L991;

--KB1L701 is std_1c20:inst|sdram:the_sdram|Mux58~1329 at LC_X16_Y22_N7

--operation mode is normal

KB1L701 = KB1L704 & (KB1_m_state[0] & (!KB1L991) # !KB1_m_state[0] & KB1_init_done);

--KB1L702 is std_1c20:inst|sdram:the_sdram|Mux58~1330 at LC_X16_Y22_N8

--operation mode is normal

KB1L702 = KB1_m_state[8] & KB1_m_state[0] & (KB1L701) # !KB1_m_state[8] & (KB1_m_state[0] & KB1L677 # !KB1_m_state[0] & (KB1L701));

--KB1L703 is std_1c20:inst|sdram:the_sdram|Mux58~1331 at LC_X17_Y21_N2

--operation mode is normal

KB1L703 = KB1L702 & (KB1L700) # !KB1L702 & KB1_active_addr[9];

--KB1L676 is std_1c20:inst|sdram:the_sdram|Mux44~1264 at LC_X15_Y22_N9

--operation mode is normal

KB1L676 = !KB1_m_state[2] & (KB1L984);

--TE1_entry_1[44] is std_1c20:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_1[44] at LC_X17_Y23_N2

--operation mode is normal

TE1_entry_1[44]_lut_out = NB1L20 & (S1L1756Q) # !NB1L20 & S1_ic_fill_line[5];

TE1_entry_1[44] = DFFEAS(TE1_entry_1[44]_lut_out, GLOBAL(QC2__clk0), VCC, , TE1L148, , , , );

--KB1L12 is std_1c20:inst|sdram:the_sdram|active_addr[8]~4929 at LC_X13_Y20_N1

--operation mode is normal

KB1L12 = F1_data_out & KB1L676 & (KB1_m_state[0] # KB1_init_done);

--KB1L13 is std_1c20:inst|sdram:the_sdram|active_addr[8]~4930 at LC_X13_Y22_N3

--operation mode is normal

KB1L13 = KB1_m_state[0] & (!KB1_m_state[8] # !KB1L991);

--KB1L14 is std_1c20:inst|sdram:the_sdram|active_addr[8]~4931 at LC_X13_Y22_N4

--operation mode is normal

KB1L14 = KB1_m_state[8] & (KB1L704 & KB1L13) # !KB1_m_state[8] & (KB1L13 & KB1L677 # !KB1L13 & (KB1L704));

--TE1_entry_1[50] is std_1c20:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_1[50] at LC_X18_Y23_N9

--operation mode is normal

TE1_entry_1[50]_lut_out = NB1L20 & S1_M_alu_result[16] # !NB1L20 & (S1L1587Q);

TE1_entry_1[50] = DFFEAS(TE1_entry_1[50]_lut_out, GLOBAL(QC2__clk0), VCC, , TE1L148, , , , );

--KB1L690 is std_1c20:inst|sdram:the_sdram|Mux53~1277 at LC_X18_Y22_N2

--operation mode is normal

KB1L690 = TE1_rd_address & (TE1_entry_1[50]) # !TE1_rd_address & TE1_entry_0[50];

--KB1L691 is std_1c20:inst|sdram:the_sdram|Mux53~1278 at LC_X18_Y21_N3

--operation mode is normal

KB1L691 = KB1L702 & KB1L690 # !KB1L702 & (KB1_active_addr[14]);

--TE1_entry_1[49] is std_1c20:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_1[49] at LC_X18_Y23_N1

--operation mode is normal

TE1_entry_1[49]_lut_out = NB1L20 & S1_M_alu_result[15] # !NB1L20 & (S1L1583Q);

TE1_entry_1[49] = DFFEAS(TE1_entry_1[49]_lut_out, GLOBAL(QC2__clk0), VCC, , TE1L148, , , , );

--KB1L692 is std_1c20:inst|sdram:the_sdram|Mux54~1277 at LC_X17_Y23_N1

--operation mode is normal

KB1L692 = TE1_rd_address & (TE1_entry_1[49]) # !TE1_rd_address & TE1_entry_0[49];

--KB1L693 is std_1c20:inst|sdram:the_sdram|Mux54~1278 at LC_X17_Y21_N4

--operation mode is normal

KB1L693 = KB1L702 & KB1L692 # !KB1L702 & (KB1_active_addr[13]);

--TE1_entry_1[47] is std_1c20:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_1[47] at LC_X21_Y21_N9

--operation mode is normal

TE1_entry_1[47]_lut_out = NB1L20 & S1_M_alu_result[13] # !NB1L20 & (S1L1577Q);

TE1_entry_1[47] = DFFEAS(TE1_entry_1[47]_lut_out, GLOBAL(QC2__clk0), VCC, , TE1L148, , , , );

--KB1L696 is std_1c20:inst|sdram:the_sdram|Mux56~1277 at LC_X21_Y21_N5

--operation mode is normal

KB1L696 = TE1_rd_address & TE1_entry_1[47] # !TE1_rd_address & (TE1_entry_0[47]);

--KB1L697 is std_1c20:inst|sdram:the_sdram|Mux56~1278 at LC_X21_Y21_N8

--operation mode is normal

KB1L697 = KB1L702 & (KB1L696) # !KB1L702 & KB1_active_addr[11];

--NB1L60 is std_1c20:inst|sdram_s1_arbitrator:the_sdram_s1|sdram_s1_address[21]~159 at LC_X18_Y22_N4

--operation mode is normal

NB1L60 = NB1L20 & (T1L448Q) # !NB1L20 & S1L1633Q;

--TE1_entry_1[57] is std_1c20:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_1[57] at LC_X18_Y22_N4

--operation mode is normal

TE1_entry_1[57] = DFFEAS(NB1L60, GLOBAL(QC2__clk0), VCC, , TE1L148, , , , );

--TE1_entry_1[52] is std_1c20:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_1[52] at LC_X21_Y21_N4

--operation mode is normal

TE1_entry_1[52]_lut_out = NB1L20 & (S1_M_alu_result[18]) # !NB1L20 & S1_ic_fill_tag[6];

TE1_entry_1[52] = DFFEAS(TE1_entry_1[52]_lut_out, GLOBAL(QC2__clk0), VCC, , TE1L148, , , , );

--KB1L686 is std_1c20:inst|sdram:the_sdram|Mux51~1277 at LC_X21_Y21_N7

--operation mode is normal

KB1L686 = TE1_rd_address & (TE1_entry_1[52]) # !TE1_rd_address & TE1_entry_0[52];

--KB1L687 is std_1c20:inst|sdram:the_sdram|Mux51~1278 at LC_X17_Y21_N3

--operation mode is normal

KB1L687 = KB1L702 & (KB1L686) # !KB1L702 & KB1_active_addr[16];

--TE1_entry_1[51] is std_1c20:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_1[51] at LC_X18_Y20_N6

--operation mode is normal

TE1_entry_1[51]_lut_out = NB1L20 & (S1_M_alu_result[17]) # !NB1L20 & S1L1593Q;

TE1_entry_1[51] = DFFEAS(TE1_entry_1[51]_lut_out, GLOBAL(QC2__clk0), VCC, , TE1L148, , , , );

--KB1L688 is std_1c20:inst|sdram:the_sdram|Mux52~1277 at LC_X18_Y20_N9

--operation mode is normal

KB1L688 = TE1_rd_address & (TE1_entry_1[51]) # !TE1_rd_address & TE1_entry_0[51];

--KB1L689 is std_1c20:inst|sdram:the_sdram|Mux52~1278 at LC_X18_Y20_N1

--operation mode is normal

KB1L689 = KB1L702 & (KB1L688) # !KB1L702 & KB1_active_addr[15];

--TE1_entry_1[53] is std_1c20:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_1[53] at LC_X17_Y20_N5

--operation mode is normal

TE1_entry_1[53]_lut_out = NB1L20 & (S1_M_alu_result[19]) # !NB1L20 & S1_ic_fill_tag[7];

TE1_entry_1[53] = DFFEAS(TE1_entry_1[53]_lut_out, GLOBAL(QC2__clk0), VCC, , TE1L148, , , , );

--KB1L684 is std_1c20:inst|sdram:the_sdram|Mux50~1277 at LC_X17_Y19_N4

--operation mode is normal

KB1L684 = TE1_rd_address & (TE1_entry_1[53]) # !TE1_rd_address & TE1_entry_0[53];

--KB1L685 is std_1c20:inst|sdram:the_sdram|Mux50~1278 at LC_X16_Y20_N8

--operation mode is normal

KB1L685 = KB1L702 & (KB1L684) # !KB1L702 & KB1_active_addr[17];

--TE1_entry_1[46] is std_1c20:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_1[46] at LC_X17_Y20_N1

--operation mode is normal

TE1_entry_1[46]_lut_out = NB1L20 & (S1_M_alu_result[12]) # !NB1L20 & S1L1568Q;

TE1_entry_1[46] = DFFEAS(TE1_entry_1[46]_lut_out, GLOBAL(QC2__clk0), VCC, , TE1L148, , , , );

--KB1L698 is std_1c20:inst|sdram:the_sdram|Mux57~1277 at LC_X17_Y19_N2

--operation mode is normal

KB1L698 = TE1_rd_address & (TE1_entry_1[46]) # !TE1_rd_address & TE1_entry_0[46];

--KB1L699 is std_1c20:inst|sdram:the_sdram|Mux57~1278 at LC_X16_Y20_N3

--operation mode is normal

KB1L699 = KB1L702 & (KB1L698) # !KB1L702 & KB1_active_addr[10];

--NB1_sdram_s1_in_a_write_cycle is std_1c20:inst|sdram_s1_arbitrator:the_sdram_s1|sdram_s1_in_a_write_cycle at LC_X24_Y21_N8

--operation mode is normal

NB1_sdram_s1_in_a_write_cycle = S1_internal_d_write & NB1L20;

--TE1_entry_1[56] is std_1c20:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_1[56] at LC_X17_Y20_N6

--operation mode is normal

TE1_entry_1[56]_lut_out = NB1L20 & S1L1816Q # !NB1L20 & (S1_ic_fill_tag[10]);

TE1_entry_1[56] = DFFEAS(TE1_entry_1[56]_lut_out, GLOBAL(QC2__clk0), VCC, , TE1L148, , , , );

--KB1L678 is std_1c20:inst|sdram:the_sdram|Mux47~1292 at LC_X16_Y21_N3

--operation mode is normal

KB1L678 = TE1_rd_address & TE1_entry_1[56] # !TE1_rd_address & (TE1_entry_0[56]);

--KB1L679 is std_1c20:inst|sdram:the_sdram|Mux47~1293 at LC_X16_Y20_N4

--operation mode is normal

KB1L679 = KB1L702 & (KB1L678) # !KB1L702 & KB1_active_addr[20];

--TE1_entry_1[54] is std_1c20:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_1[54] at LC_X18_Y20_N3

--operation mode is normal

TE1_entry_1[54]_lut_out = NB1L20 & (S1L1782Q) # !NB1L20 & S1L1609Q;

TE1_entry_1[54] = DFFEAS(TE1_entry_1[54]_lut_out, GLOBAL(QC2__clk0), VCC, , TE1L148, , , , );

--KB1L682 is std_1c20:inst|sdram:the_sdram|Mux49~1277 at LC_X18_Y20_N5

--operation mode is normal

KB1L682 = TE1_rd_address & (TE1_entry_1[54]) # !TE1_rd_address & TE1_entry_0[54];

--KB1L683 is std_1c20:inst|sdram:the_sdram|Mux49~1278 at LC_X18_Y20_N8

--operation mode is normal

KB1L683 = KB1L702 & (KB1L682) # !KB1L702 & KB1_active_addr[18];

--NB1L51 is std_1c20:inst|sdram_s1_arbitrator:the_sdram_s1|sdram_s1_address[12]~166 at LC_X18_Y22_N5

--operation mode is normal

NB1L51 = NB1L20 & (S1L1762Q) # !NB1L20 & S1L1580Q;

--TE1_entry_1[48] is std_1c20:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_1[48] at LC_X18_Y22_N5

--operation mode is normal

TE1_entry_1[48] = DFFEAS(NB1L51, GLOBAL(QC2__clk0), VCC, , TE1L148, , , , );

--KB1L694 is std_1c20:inst|sdram:the_sdram|Mux55~1277 at LC_X17_Y21_N1

--operation mode is normal

KB1L694 = TE1_rd_address & (TE1_entry_1[48]) # !TE1_rd_address & TE1_entry_0[48];

--KB1L695 is std_1c20:inst|sdram:the_sdram|Mux55~1278 at LC_X17_Y21_N6

--operation mode is normal

KB1L695 = KB1L702 & KB1L694 # !KB1L702 & (KB1_active_addr[12]);

--KB1L31 is std_1c20:inst|sdram:the_sdram|active_cs_n~291 at LC_X8_Y16_N4

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

F1_data_out_qfbk = F1_data_out;

KB1L31 = F1_data_out_qfbk & !KB1_m_state[0];

--F1_data_out is std_1c20:inst|std_1c20_reset_sysclk2_domain_synch_module:std_1c20_reset_sysclk2_domain_synch|data_out at LC_X8_Y16_N4

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

F1_data_out = DFFEAS(KB1L31, GLOBAL(QC2__clk0), !B1L1, , , F1_data_in_d1, , , VCC);

--KB1L32 is std_1c20:inst|sdram:the_sdram|active_cs_n~292 at LC_X14_Y22_N7

--operation mode is normal

KB1L32 = KB1L984 & !KB1_m_state[2] & KB1L31 & KB1L29;

--TE1_entry_1[55] is std_1c20:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_1[55] at LC_X22_Y22_N9

--operation mode is normal

TE1_entry_1[55]_lut_out = NB1L20 & S1L1800Q # !NB1L20 & (S1_ic_fill_tag[9]);

TE1_entry_1[55] = DFFEAS(TE1_entry_1[55]_lut_out, GLOBAL(QC2__clk0), VCC, , TE1L148, , , , );

--KB1L680 is std_1c20:inst|sdram:the_sdram|Mux48~1277 at LC_X21_Y22_N2

--operation mode is normal

KB1L680 = TE1_rd_address & (TE1_entry_1[55]) # !TE1_rd_address & TE1_entry_0[55];

--KB1L681 is std_1c20:inst|sdram:the_sdram|Mux48~1278 at LC_X21_Y22_N5

--operation mode is normal

KB1L681 = KB1L702 & (KB1L680) # !KB1L702 & KB1_active_addr[19];

--KB1_i_state[0] is std_1c20:inst|sdram:the_sdram|i_state[0] at LC_X10_Y23_N6

--operation mode is normal

KB1_i_state[0]_lut_out = KB1L481 # KB1L151 & (KB1_i_state[1] # KB1L112);

KB1_i_state[0] = DFFEAS(KB1_i_state[0]_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--KB1_i_state[2] is std_1c20:inst|sdram:the_sdram|i_state[2] at LC_X10_Y23_N9

--operation mode is normal

KB1_i_state[2]_lut_out = KB1_i_state[0] & (KB1_i_state[1] & !KB1_i_state[2] & KB1L478 # !KB1_i_state[1] & KB1_i_state[2]);

KB1_i_state[2] = DFFEAS(KB1_i_state[2]_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--KB1_i_state[1] is std_1c20:inst|sdram:the_sdram|i_state[1] at LC_X10_Y23_N4

--operation mode is normal

KB1_i_state[1]_lut_out = KB1_i_state[0] & (KB1_i_state[1] & (KB1_i_state[2] # KB1L479) # !KB1_i_state[1] & !KB1_i_state[2]) # !KB1_i_state[0] & KB1_i_state[1] & !KB1_i_state[2];

KB1_i_state[1] = DFFEAS(KB1_i_state[1]_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--KB1L138 is std_1c20:inst|sdram:the_sdram|i_cmd[0]~642 at LC_X11_Y22_N2

--operation mode is normal

KB1L138 = KB1_i_state[1] & KB1_i_state[0] # !KB1_i_state[2];

--KB1_refresh_counter[3] is std_1c20:inst|sdram:the_sdram|refresh_counter[3] at LC_X63_Y31_N3

--operation mode is normal

KB1_refresh_counter[3]_lut_out = !KB1L74;

KB1_refresh_counter[3] = DFFEAS(KB1_refresh_counter[3]_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--KB1_refresh_counter[0] is std_1c20:inst|sdram:the_sdram|refresh_counter[0] at LC_X63_Y31_N1

--operation mode is normal

KB1_refresh_counter[0]_lut_out = KB1L77;

KB1_refresh_counter[0] = DFFEAS(KB1_refresh_counter[0]_lut_out, GLOBAL(QC2__clk0), VCC, , , A1L277, !GLOBAL(F1_data_out), , );

--KB1_refresh_counter[1] is std_1c20:inst|sdram:the_sdram|refresh_counter[1] at LC_X63_Y29_N7

--operation mode is normal

KB1_refresh_counter[1]_lut_out = !KB1L112 & KB1L79;

KB1_refresh_counter[1] = DFFEAS(KB1_refresh_counter[1]_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--KB1_refresh_counter[2] is std_1c20:inst|sdram:the_sdram|refresh_counter[2] at LC_X63_Y31_N0

--operation mode is normal

KB1_refresh_counter[2]_lut_out = KB1L82;

KB1_refresh_counter[2] = DFFEAS(KB1_refresh_counter[2]_lut_out, GLOBAL(QC2__clk0), VCC, , , A1L277, !GLOBAL(F1_data_out), , );

--KB1L109 is std_1c20:inst|sdram:the_sdram|Equal1~172 at LC_X63_Y31_N2

--operation mode is normal

KB1L109 = !KB1_refresh_counter[0] & !KB1_refresh_counter[2] & !KB1_refresh_counter[1] & KB1_refresh_counter[3];

--KB1_refresh_counter[7] is std_1c20:inst|sdram:the_sdram|refresh_counter[7] at LC_X63_Y29_N9

--operation mode is normal

KB1_refresh_counter[7]_lut_out = KB1L112 # !KB1L85;

KB1_refresh_counter[7] = DFFEAS(KB1_refresh_counter[7]_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--KB1_refresh_counter[4] is std_1c20:inst|sdram:the_sdram|refresh_counter[4] at LC_X63_Y29_N0

--operation mode is normal

KB1_refresh_counter[4]_lut_out = !KB1L112 & KB1L88;

KB1_refresh_counter[4] = DFFEAS(KB1_refresh_counter[4]_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--KB1_refresh_counter[5] is std_1c20:inst|sdram:the_sdram|refresh_counter[5] at LC_X63_Y29_N5

--operation mode is normal

KB1_refresh_counter[5]_lut_out = !KB1L112 & KB1L91;

KB1_refresh_counter[5] = DFFEAS(KB1_refresh_counter[5]_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--KB1_refresh_counter[6] is std_1c20:inst|sdram:the_sdram|refresh_counter[6] at LC_X63_Y29_N2

--operation mode is normal

KB1_refresh_counter[6]_lut_out = !KB1L112 & KB1L93;

KB1_refresh_counter[6] = DFFEAS(KB1_refresh_counter[6]_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--KB1L110 is std_1c20:inst|sdram:the_sdram|Equal1~173 at LC_X63_Y29_N8

--operation mode is normal

KB1L110 = !KB1_refresh_counter[6] & !KB1_refresh_counter[5] & KB1_refresh_counter[7] & !KB1_refresh_counter[4];

--KB1_refresh_counter[12] is std_1c20:inst|sdram:the_sdram|refresh_counter[12] at LC_X63_Y29_N3

--operation mode is normal

KB1_refresh_counter[12]_lut_out = KB1L112 # !KB1L96;

KB1_refresh_counter[12] = DFFEAS(KB1_refresh_counter[12]_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--KB1_refresh_counter[8] is std_1c20:inst|sdram:the_sdram|refresh_counter[8] at LC_X64_Y30_N2

--operation mode is normal

KB1_refresh_counter[8]_lut_out = !KB1L97;

KB1_refresh_counter[8] = DFFEAS(KB1_refresh_counter[8]_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--KB1_refresh_counter[9] is std_1c20:inst|sdram:the_sdram|refresh_counter[9] at LC_X64_Y30_N4

--operation mode is normal

KB1_refresh_counter[9]_lut_out = !KB1L100;

KB1_refresh_counter[9] = DFFEAS(KB1_refresh_counter[9]_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--KB1_refresh_counter[10] is std_1c20:inst|sdram:the_sdram|refresh_counter[10] at LC_X63_Y30_N8

--operation mode is normal

KB1_refresh_counter[10]_lut_out = KB1L103 & !KB1L112;

KB1_refresh_counter[10] = DFFEAS(KB1_refresh_counter[10]_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--KB1_refresh_counter[11] is std_1c20:inst|sdram:the_sdram|refresh_counter[11] at LC_X63_Y30_N7

--operation mode is normal

KB1_refresh_counter[11]_lut_out = !KB1L112 & (KB1L105);

KB1_refresh_counter[11] = DFFEAS(KB1_refresh_counter[11]_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--KB1L111 is std_1c20:inst|sdram:the_sdram|Equal1~174 at LC_X63_Y30_N9

--operation mode is normal

KB1L111 = KB1_refresh_counter[8] & !KB1_refresh_counter[10] & !KB1_refresh_counter[11] & KB1_refresh_counter[9];

--KB1L112 is std_1c20:inst|sdram:the_sdram|Equal1~175 at LC_X63_Y29_N6

--operation mode is normal

KB1L112 = KB1L109 & KB1_refresh_counter[12] & KB1L110 & KB1L111;

--KB1_ack_refresh_request is std_1c20:inst|sdram:the_sdram|ack_refresh_request at LC_X12_Y25_N3

--operation mode is normal

KB1_ack_refresh_request_lut_out = KB1L511 & (KB1_m_state[7] # !KB1_init_done & KB1_ack_refresh_request) # !KB1L511 & (KB1_ack_refresh_request);

KB1_ack_refresh_request = DFFEAS(KB1_ack_refresh_request_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--KB1L607 is std_1c20:inst|sdram:the_sdram|Mux39~1239 at LC_X14_Y24_N1

--operation mode is normal

KB1L607 = KB1L546 & (KB1_refresh_request # TE1L152 & KB1L991);

--KB1L558 is std_1c20:inst|sdram:the_sdram|Mux32~1283 at LC_X15_Y23_N9

--operation mode is normal

KB1L558 = KB1_m_state[4] & (KB1_m_state[7] # !KB1_m_state[1] & KB1L461) # !KB1_m_state[4] & KB1_m_state[1];

--KB1L561 is std_1c20:inst|sdram:the_sdram|Mux32~1286 at LC_X15_Y24_N5

--operation mode is normal

KB1L561 = KB1L574 & (KB1L565 & !KB1L576 # !KB1L565 & (!KB1L563)) # !KB1L574 & (KB1L576);

--KB1L608 is std_1c20:inst|sdram:the_sdram|Mux39~1240 at LC_X14_Y24_N2

--operation mode is normal

KB1L608 = !KB1_m_state[6] & !KB1_m_state[2] & !KB1_m_state[5];

--KB1L609 is std_1c20:inst|sdram:the_sdram|Mux39~1241 at LC_X15_Y23_N8

--operation mode is normal

KB1L609 = KB1L546 & (!KB1_m_next[0] & !KB1_refresh_request # !KB1_init_done) # !KB1L546 & !KB1_m_next[0];

--KB1L610 is std_1c20:inst|sdram:the_sdram|Mux39~1242 at LC_X15_Y21_N6

--operation mode is normal

KB1L610 = KB1_m_state[7] # KB1_m_state[1] & (KB1_m_state[4] # KB1_m_state[3]);

--KB1L611 is std_1c20:inst|sdram:the_sdram|Mux39~1243 at LC_X15_Y23_N2

--operation mode is normal

KB1L611 = KB1L610 & KB1L773 # !KB1L610 & (KB1L744 & KB1L461);

--KB1L612 is std_1c20:inst|sdram:the_sdram|Mux39~1244 at LC_X15_Y23_N3

--operation mode is normal

KB1L612 = KB1_m_state[1] & KB1L610 & (!KB1_m_next[0]) # !KB1_m_state[1] & (KB1L611 # !KB1_m_next[0]);

--KB1L613 is std_1c20:inst|sdram:the_sdram|Mux39~1245 at LC_X15_Y23_N4

--operation mode is normal

KB1L613 = KB1_m_state[0] & (!KB1_m_state[8] & KB1L612) # !KB1_m_state[0] & (KB1L609 # KB1_m_state[8]);

--KB1L596 is std_1c20:inst|sdram:the_sdram|Mux38~1215 at LC_X15_Y23_N1

--operation mode is normal

KB1L596 = KB1L600 & (KB1L606 # !KB1L598) # !KB1L600 & (KB1L598 & !KB1L604);

--KB1L586 is std_1c20:inst|sdram:the_sdram|Mux36~1270 at LC_X16_Y24_N0

--operation mode is normal

KB1L586 = KB1_m_state[3] & (KB1_m_next[3]) # !KB1_m_state[3] & (KB1_m_state[4] & KB1_m_next[3] # !KB1_m_state[4] & (KB1_active_rnw));

--KB1L587 is std_1c20:inst|sdram:the_sdram|Mux36~1271 at LC_X16_Y24_N5

--operation mode is normal

KB1L587 = KB1_m_next[3] & (!KB1_refresh_request & KB1_init_done # !KB1L773);

--KB1L579 is std_1c20:inst|sdram:the_sdram|Mux35~1200 at LC_X16_Y24_N4

--operation mode is normal

KB1L579 = KB1_m_state[3] & (KB1_m_next[4]) # !KB1_m_state[3] & (KB1_m_state[4] & KB1_m_next[4] # !KB1_m_state[4] & (!KB1_active_rnw));

--KB1L580 is std_1c20:inst|sdram:the_sdram|Mux35~1201 at LC_X16_Y24_N3

--operation mode is normal

KB1L580 = KB1_m_next[4] & (KB1_init_done & !KB1_refresh_request # !KB1L773);

--XE1L15 is std_1c20:inst|uart1:the_uart1|uart1_regs:the_uart1_regs|Equal1~116 at LC_X45_Y22_N4

--operation mode is normal

XE1L15 = S1L1726Q & !S1L1738Q & S1_M_alu_result[3];

--SB1L2 is std_1c20:inst|sys_clk_timer_s1_arbitrator:the_sys_clk_timer_s1|cpu_data_master_requests_sys_clk_timer_s1~180 at LC_X37_Y25_N9

--operation mode is normal

SB1L2 = UB1L6 & UB1L3 & UB1L2 & SB1L7;

--XE1L13 is std_1c20:inst|uart1:the_uart1|uart1_regs:the_uart1_regs|control_wr_strobe~26 at LC_X47_Y25_N6

--operation mode is normal

XE1L13 = S1_internal_d_write & S1_M_alu_result[6] & !S1L1743Q & SB1L2;

--ZE1_unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out[0] is std_1c20:inst|uart1:the_uart1|uart1_tx:the_uart1_tx|unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out[0] at LC_X48_Y25_N1

--operation mode is normal

ZE1_unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out[0]_lut_out = ZE1_unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out[1] & (!ZE1_do_load_shifter);

ZE1_unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out[0] = DFFEAS(ZE1_unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out[0]_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , ZE1L51, , , , );

--ZE1_unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out[3] is std_1c20:inst|uart1:the_uart1|uart1_tx:the_uart1_tx|unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out[3] at LC_X48_Y24_N0

--operation mode is normal

ZE1_unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out[3]_lut_out = ZE1_do_load_shifter & XE1_internal_tx_data[2] # !ZE1_do_load_shifter & (ZE1_unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out[4]);

ZE1_unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out[3] = DFFEAS(ZE1_unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out[3]_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , ZE1L51, , , , );

--ZE1_unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out[2] is std_1c20:inst|uart1:the_uart1|uart1_tx:the_uart1_tx|unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out[2] at LC_X48_Y24_N5

--operation mode is normal

ZE1_unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out[2]_lut_out = ZE1_do_load_shifter & (XE1_internal_tx_data[1]) # !ZE1_do_load_shifter & ZE1_unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out[3];

ZE1_unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out[2] = DFFEAS(ZE1_unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out[2]_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , ZE1L51, , , , );

--ZE1_unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out[1] is std_1c20:inst|uart1:the_uart1|uart1_tx:the_uart1_tx|unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out[1] at LC_X48_Y25_N5

--operation mode is normal

ZE1_unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out[1]_lut_out = ZE1_do_load_shifter & XE1_internal_tx_data[0] # !ZE1_do_load_shifter & (ZE1_unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out[2]);

ZE1_unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out[1] = DFFEAS(ZE1_unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out[1]_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , ZE1L51, , , , );

--ZE1_unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out[4] is std_1c20:inst|uart1:the_uart1|uart1_tx:the_uart1_tx|unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out[4] at LC_X48_Y24_N4

--operation mode is normal

ZE1_unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out[4]_lut_out = ZE1_do_load_shifter & (XE1_internal_tx_data[3]) # !ZE1_do_load_shifter & ZE1_unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out[5];

ZE1_unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out[4] = DFFEAS(ZE1_unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out[4]_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , ZE1L51, , , , );

--ZE1L35 is std_1c20:inst|uart1:the_uart1|uart1_tx:the_uart1_tx|pre_txd~65 at LC_X48_Y24_N3

--operation mode is normal

ZE1L35 = !ZE1_unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out[1] & !ZE1_unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out[2] & !ZE1_unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out[4] & !ZE1_unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out[3];

--ZE1_unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out[5] is std_1c20:inst|uart1:the_uart1|uart1_tx:the_uart1_tx|unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out[5] at LC_X48_Y24_N9

--operation mode is normal

ZE1_unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out[5]_lut_out = ZE1_do_load_shifter & (XE1_internal_tx_data[4]) # !ZE1_do_load_shifter & ZE1_unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out[6];

ZE1_unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out[5] = DFFEAS(ZE1_unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out[5]_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , ZE1L51, , , , );

--ZE1_unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out[6] is std_1c20:inst|uart1:the_uart1|uart1_tx:the_uart1_tx|unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out[6] at LC_X48_Y24_N7

--operation mode is normal

ZE1_unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out[6]_lut_out = ZE1_do_load_shifter & (XE1_internal_tx_data[5]) # !ZE1_do_load_shifter & ZE1_unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out[7];

ZE1_unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out[6] = DFFEAS(ZE1_unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out[6]_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , ZE1L51, , , , );

--ZE1_unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out[7] is std_1c20:inst|uart1:the_uart1|uart1_tx:the_uart1_tx|unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out[7] at LC_X48_Y24_N6

--operation mode is normal

ZE1_unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out[7]_lut_out = ZE1_do_load_shifter & (XE1_internal_tx_data[6]) # !ZE1_do_load_shifter & ZE1_unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out[8];

ZE1_unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out[7] = DFFEAS(ZE1_unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out[7]_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , ZE1L51, , , , );

--ZE1_unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out[8] is std_1c20:inst|uart1:the_uart1|uart1_tx:the_uart1_tx|unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out[8] at LC_X48_Y24_N8

--operation mode is normal

ZE1_unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out[8]_lut_out = ZE1_do_load_shifter & (XE1_internal_tx_data[7]) # !ZE1_do_load_shifter & ZE1_unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out[9];

ZE1_unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out[8] = DFFEAS(ZE1_unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out[8]_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , ZE1L51, , , , );

--ZE1L36 is std_1c20:inst|uart1:the_uart1|uart1_tx:the_uart1_tx|pre_txd~66 at LC_X48_Y24_N2

--operation mode is normal

ZE1L36 = !ZE1_unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out[6] & !ZE1_unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out[8] & !ZE1_unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out[5] & !ZE1_unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out[7];

--ZE1L37 is std_1c20:inst|uart1:the_uart1|uart1_tx:the_uart1_tx|pre_txd~67 at LC_X48_Y24_N1

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

ZE1_unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out[9]_qfbk = ZE1_unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out[9];

ZE1L37 = ZE1L36 & ZE1L35 & !ZE1_unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out[9]_qfbk;

--ZE1_unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out[9] is std_1c20:inst|uart1:the_uart1|uart1_tx:the_uart1_tx|unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out[9] at LC_X48_Y24_N1

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

ZE1_unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out[9] = DFFEAS(ZE1L37, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , ZE1L51, ZE1_do_load_shifter, , , VCC);

--S1_M_ipending_reg[2] is std_1c20:inst|cpu:the_cpu|M_ipending_reg[2] at LC_X44_Y20_N1

--operation mode is normal

S1_M_ipending_reg[2] = AMPP_FUNCTION(QC2__clk0, S1L2131, FD1L22Q, S1L2101Q, S1L2130, F1_data_out);

--S1_D_iw[8] is std_1c20:inst|cpu:the_cpu|D_iw[8] at LC_X32_Y19_N0

--operation mode is normal

S1_D_iw[8] = AMPP_FUNCTION(QC2__clk0, S1L2381, AD1_q_b[8], S1L1709, S1L1257, F1_data_out, S1_W_stall);

--S1_D_iw[7] is std_1c20:inst|cpu:the_cpu|D_iw[7] at LC_X32_Y19_N9

--operation mode is normal

S1_D_iw[7] = AMPP_FUNCTION(QC2__clk0, S1L2381, AD1_q_b[7], S1L1709, S1L1257, F1_data_out, S1_W_stall);

--S1_D_iw[6] is std_1c20:inst|cpu:the_cpu|D_iw[6] at LC_X32_Y19_N6

--operation mode is normal

S1_D_iw[6] = AMPP_FUNCTION(QC2__clk0, S1L2381, AD1_q_b[6], S1L1709, S1L1257, F1_data_out, S1_W_stall);

--S1L273 is std_1c20:inst|cpu:the_cpu|D_control_rd_data_without_mmu_regs[2]~497 at LC_X32_Y19_N1

--operation mode is normal

S1L273 = AMPP_FUNCTION(S1_D_iw[6], S1_D_iw[7], S1_D_iw[8]);

--S1_D_iw[4] is std_1c20:inst|cpu:the_cpu|D_iw[4] at LC_X28_Y15_N6

--operation mode is normal

S1_D_iw[4] = AMPP_FUNCTION(QC2__clk0, S1L2381, S1L1709, S1L1257, AD1_q_b[4], F1_data_out, S1_W_stall);

--S1_D_iw[15] is std_1c20:inst|cpu:the_cpu|D_iw[15] at LC_X28_Y16_N1

--operation mode is normal

S1_D_iw[15] = AMPP_FUNCTION(QC2__clk0, S1L1709, S1L2381, S1L1257, AD1_q_b[15], F1_data_out, S1_W_stall);

--S1_D_iw[0] is std_1c20:inst|cpu:the_cpu|D_iw[0] at LC_X28_Y15_N8

--operation mode is normal

S1_D_iw[0] = AMPP_FUNCTION(QC2__clk0, S1L2381, S1L1709, S1L1257, AD1_q_b[0], F1_data_out, S1_W_stall);

--S1_D_iw[1] is std_1c20:inst|cpu:the_cpu|D_iw[1] at LC_X28_Y15_N5

--operation mode is normal

S1_D_iw[1] = AMPP_FUNCTION(QC2__clk0, S1L2381, S1L1709, S1L1257, AD1_q_b[1], F1_data_out, S1_W_stall);

--S1_D_iw[2] is std_1c20:inst|cpu:the_cpu|D_iw[2] at LC_X28_Y15_N1

--operation mode is normal

S1_D_iw[2] = AMPP_FUNCTION(QC2__clk0, S1L2381, S1L1709, S1L1257, AD1_q_b[2], F1_data_out, S1_W_stall);

--S1_D_iw[3] is std_1c20:inst|cpu:the_cpu|D_iw[3] at LC_X28_Y15_N0

--operation mode is normal

S1_D_iw[3] = AMPP_FUNCTION(QC2__clk0, S1L2381, S1L1709, S1L1257, AD1_q_b[3], F1_data_out, S1_W_stall);

--S1L1168 is std_1c20:inst|cpu:the_cpu|Equal53~851 at LC_X30_Y14_N8

--operation mode is normal

S1L1168 = AMPP_FUNCTION(S1_D_iw[0], S1_D_iw[3], S1_D_iw[1], S1_D_iw[2]);

--S1_D_iw[5] is std_1c20:inst|cpu:the_cpu|D_iw[5] at LC_X28_Y15_N9

--operation mode is normal

S1_D_iw[5] = AMPP_FUNCTION(QC2__clk0, S1L2381, S1L1709, S1L1257, AD1_q_b[5], F1_data_out, S1_W_stall);

--CD1_q_b[2] is std_1c20:inst|cpu:the_cpu|cpu_register_bank_a_module:cpu_register_bank_a|altsyncram:the_altsyncram|altsyncram_3vd1:auto_generated|q_b[2] at M4K_X49_Y16

--RAM Block Operation Mode: Simple Dual-Port

--Port A Depth: 32, Port A Width: 32, Port B Depth: 32, Port B Width: 32

--Port A Logical Depth: 32, Port A Logical Width: 32, Port B Logical Depth: 32, Port B Logical Width: 32

--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered

CD1_q_b[2] = AMPP_FUNCTION(GND, GND, QC2__clk0, QC2__clk0, !S1_M_wr_dst_reg, S1_W_stall, S1L2398, S1_M_dst_regnum[0], S1_M_dst_regnum[1], S1_M_dst_regnum[2], S1_M_dst_regnum[3], S1_M_dst_regnum[4], AD1_q_b[27], AD1_q_b[28], AD1_q_b[29], AD1_q_b[30], AD1_q_b[31], GND, GND, GND, GND, S1L2401, S1L2458, S1L2455, S1L2449, S1L2446, S1L2464, S1L2440, S1L2437, S1L2434, S1L2431, S1L2428, S1L2443, S1L2467, S1L2452, S1L2461, S1L2425, S1L2422, S1L2419, S1L2416, S1L2537, S1L2410, S1L2404, S1L2407, S1L2517, S1L2395, S1L2470, S1L2495, S1L2473, S1L2482, S1L2476, S1L2479);

--CD1_q_b[29] is std_1c20:inst|cpu:the_cpu|cpu_register_bank_a_module:cpu_register_bank_a|altsyncram:the_altsyncram|altsyncram_3vd1:auto_generated|q_b[29] at M4K_X49_Y16

CD1_q_b[29] = AMPP_FUNCTION(GND, GND, QC2__clk0, QC2__clk0, !S1_M_wr_dst_reg, S1_W_stall, S1L2398, S1_M_dst_regnum[0], S1_M_dst_regnum[1], S1_M_dst_regnum[2], S1_M_dst_regnum[3], S1_M_dst_regnum[4], AD1_q_b[27], AD1_q_b[28], AD1_q_b[29], AD1_q_b[30], AD1_q_b[31], GND, GND, GND, GND, S1L2401, S1L2458, S1L2455, S1L2449, S1L2446, S1L2464, S1L2440, S1L2437, S1L2434, S1L2431, S1L2428, S1L2443, S1L2467, S1L2452, S1L2461, S1L2425, S1L2422, S1L2419, S1L2416, S1L2537, S1L2410, S1L2404, S1L2407, S1L2517, S1L2395, S1L2470, S1L2495, S1L2473, S1L2482, S1L2476, S1L2479);

--CD1_q_b[28] is std_1c20:inst|cpu:the_cpu|cpu_register_bank_a_module:cpu_register_bank_a|altsyncram:the_altsyncram|altsyncram_3vd1:auto_generated|q_b[28] at M4K_X49_Y16

CD1_q_b[28] = AMPP_FUNCTION(GND, GND, QC2__clk0, QC2__clk0, !S1_M_wr_dst_reg, S1_W_stall, S1L2398, S1_M_dst_regnum[0], S1_M_dst_regnum[1], S1_M_dst_regnum[2], S1_M_dst_regnum[3], S1_M_dst_regnum[4], AD1_q_b[27], AD1_q_b[28], AD1_q_b[29], AD1_q_b[30], AD1_q_b[31], GND, GND, GND, GND, S1L2401, S1L2458, S1L2455, S1L2449, S1L2446, S1L2464, S1L2440, S1L2437, S1L2434, S1L2431, S1L2428, S1L2443, S1L2467, S1L2452, S1L2461, S1L2425, S1L2422, S1L2419, S1L2416, S1L2537, S1L2410, S1L2404, S1L2407, S1L2517, S1L2395, S1L2470, S1L2495, S1L2473, S1L2482, S1L2476, S1L2479);

--CD1_q_b[30] is std_1c20:inst|cpu:the_cpu|cpu_register_bank_a_module:cpu_register_bank_a|altsyncram:the_altsyncram|altsyncram_3vd1:auto_generated|q_b[30] at M4K_X49_Y16

CD1_q_b[30] = AMPP_FUNCTION(GND, GND, QC2__clk0, QC2__clk0, !S1_M_wr_dst_reg, S1_W_stall, S1L2398, S1_M_dst_regnum[0], S1_M_dst_regnum[1], S1_M_dst_regnum[2], S1_M_dst_regnum[3], S1_M_dst_regnum[4], AD1_q_b[27], AD1_q_b[28], AD1_q_b[29], AD1_q_b[30], AD1_q_b[31], GND, GND, GND, GND, S1L2401, S1L2458, S1L2455, S1L2449, S1L2446, S1L2464, S1L2440, S1L2437, S1L2434, S1L2431, S1L2428, S1L2443, S1L2467, S1L2452, S1L2461, S1L2425, S1L2422, S1L2419, S1L2416, S1L2537, S1L2410, S1L2404, S1L2407, S1L2517, S1L2395, S1L2470, S1L2495, S1L2473, S1L2482, S1L2476, S1L2479);

--CD1_q_b[27] is std_1c20:inst|cpu:the_cpu|cpu_register_bank_a_module:cpu_register_bank_a|altsyncram:the_altsyncram|altsyncram_3vd1:auto_generated|q_b[27] at M4K_X49_Y16

CD1_q_b[27] = AMPP_FUNCTION(GND, GND, QC2__clk0, QC2__clk0, !S1_M_wr_dst_reg, S1_W_stall, S1L2398, S1_M_dst_regnum[0], S1_M_dst_regnum[1], S1_M_dst_regnum[2], S1_M_dst_regnum[3], S1_M_dst_regnum[4], AD1_q_b[27], AD1_q_b[28], AD1_q_b[29], AD1_q_b[30], AD1_q_b[31], GND, GND, GND, GND, S1L2401, S1L2458, S1L2455, S1L2449, S1L2446, S1L2464, S1L2440, S1L2437, S1L2434, S1L2431, S1L2428, S1L2443, S1L2467, S1L2452, S1L2461, S1L2425, S1L2422, S1L2419, S1L2416, S1L2537, S1L2410, S1L2404, S1L2407, S1L2517, S1L2395, S1L2470, S1L2495, S1L2473, S1L2482, S1L2476, S1L2479);

--CD1_q_b[31] is std_1c20:inst|cpu:the_cpu|cpu_register_bank_a_module:cpu_register_bank_a|altsyncram:the_altsyncram|altsyncram_3vd1:auto_generated|q_b[31] at M4K_X49_Y16

CD1_q_b[31] = AMPP_FUNCTION(GND, GND, QC2__clk0, QC2__clk0, !S1_M_wr_dst_reg, S1_W_stall, S1L2398, S1_M_dst_regnum[0], S1_M_dst_regnum[1], S1_M_dst_regnum[2], S1_M_dst_regnum[3], S1_M_dst_regnum[4], AD1_q_b[27], AD1_q_b[28], AD1_q_b[29], AD1_q_b[30], AD1_q_b[31], GND, GND, GND, GND, S1L2401, S1L2458, S1L2455, S1L2449, S1L2446, S1L2464, S1L2440, S1L2437, S1L2434, S1L2431, S1L2428, S1L2443, S1L2467, S1L2452, S1L2461, S1L2425, S1L2422, S1L2419, S1L2416, S1L2537, S1L2410, S1L2404, S1L2407, S1L2517, S1L2395, S1L2470, S1L2495, S1L2473, S1L2482, S1L2476, S1L2479);

--CD1_q_b[26] is std_1c20:inst|cpu:the_cpu|cpu_register_bank_a_module:cpu_register_bank_a|altsyncram:the_altsyncram|altsyncram_3vd1:auto_generated|q_b[26] at M4K_X49_Y16

CD1_q_b[26] = AMPP_FUNCTION(GND, GND, QC2__clk0, QC2__clk0, !S1_M_wr_dst_reg, S1_W_stall, S1L2398, S1_M_dst_regnum[0], S1_M_dst_regnum[1], S1_M_dst_regnum[2], S1_M_dst_regnum[3], S1_M_dst_regnum[4], AD1_q_b[27], AD1_q_b[28], AD1_q_b[29], AD1_q_b[30], AD1_q_b[31], GND, GND, GND, GND, S1L2401, S1L2458, S1L2455, S1L2449, S1L2446, S1L2464, S1L2440, S1L2437, S1L2434, S1L2431, S1L2428, S1L2443, S1L2467, S1L2452, S1L2461, S1L2425, S1L2422, S1L2419, S1L2416, S1L2537, S1L2410, S1L2404, S1L2407, S1L2517, S1L2395, S1L2470, S1L2495, S1L2473, S1L2482, S1L2476, S1L2479);

--CD1_q_b[1] is std_1c20:inst|cpu:the_cpu|cpu_register_bank_a_module:cpu_register_bank_a|altsyncram:the_altsyncram|altsyncram_3vd1:auto_generated|q_b[1] at M4K_X49_Y16

CD1_q_b[1] = AMPP_FUNCTION(GND, GND, QC2__clk0, QC2__clk0, !S1_M_wr_dst_reg, S1_W_stall, S1L2398, S1_M_dst_regnum[0], S1_M_dst_regnum[1], S1_M_dst_regnum[2], S1_M_dst_regnum[3], S1_M_dst_regnum[4], AD1_q_b[27], AD1_q_b[28], AD1_q_b[29], AD1_q_b[30], AD1_q_b[31], GND, GND, GND, GND, S1L2401, S1L2458, S1L2455, S1L2449, S1L2446, S1L2464, S1L2440, S1L2437, S1L2434, S1L2431, S1L2428, S1L2443, S1L2467, S1L2452, S1L2461, S1L2425, S1L2422, S1L2419, S1L2416, S1L2537, S1L2410, S1L2404, S1L2407, S1L2517, S1L2395, S1L2470, S1L2495, S1L2473, S1L2482, S1L2476, S1L2479);

--CD1_q_b[0] is std_1c20:inst|cpu:the_cpu|cpu_register_bank_a_module:cpu_register_bank_a|altsyncram:the_altsyncram|altsyncram_3vd1:auto_generated|q_b[0] at M4K_X49_Y16

CD1_q_b[0] = AMPP_FUNCTION(GND, GND, QC2__clk0, QC2__clk0, !S1_M_wr_dst_reg, S1_W_stall, S1L2398, S1_M_dst_regnum[0], S1_M_dst_regnum[1], S1_M_dst_regnum[2], S1_M_dst_regnum[3], S1_M_dst_regnum[4], AD1_q_b[27], AD1_q_b[28], AD1_q_b[29], AD1_q_b[30], AD1_q_b[31], GND, GND, GND, GND, S1L2401, S1L2458, S1L2455, S1L2449, S1L2446, S1L2464, S1L2440, S1L2437, S1L2434, S1L2431, S1L2428, S1L2443, S1L2467, S1L2452, S1L2461, S1L2425, S1L2422, S1L2419, S1L2416, S1L2537, S1L2410, S1L2404, S1L2407, S1L2517, S1L2395, S1L2470, S1L2495, S1L2473, S1L2482, S1L2476, S1L2479);

--CD1_q_b[5] is std_1c20:inst|cpu:the_cpu|cpu_register_bank_a_module:cpu_register_bank_a|altsyncram:the_altsyncram|altsyncram_3vd1:auto_generated|q_b[5] at M4K_X49_Y16

CD1_q_b[5] = AMPP_FUNCTION(GND, GND, QC2__clk0, QC2__clk0, !S1_M_wr_dst_reg, S1_W_stall, S1L2398, S1_M_dst_regnum[0], S1_M_dst_regnum[1], S1_M_dst_regnum[2], S1_M_dst_regnum[3], S1_M_dst_regnum[4], AD1_q_b[27], AD1_q_b[28], AD1_q_b[29], AD1_q_b[30], AD1_q_b[31], GND, GND, GND, GND, S1L2401, S1L2458, S1L2455, S1L2449, S1L2446, S1L2464, S1L2440, S1L2437, S1L2434, S1L2431, S1L2428, S1L2443, S1L2467, S1L2452, S1L2461, S1L2425, S1L2422, S1L2419, S1L2416, S1L2537, S1L2410, S1L2404, S1L2407, S1L2517, S1L2395, S1L2470, S1L2495, S1L2473, S1L2482, S1L2476, S1L2479);

--CD1_q_b[4] is std_1c20:inst|cpu:the_cpu|cpu_register_bank_a_module:cpu_register_bank_a|altsyncram:the_altsyncram|altsyncram_3vd1:auto_generated|q_b[4] at M4K_X49_Y16

CD1_q_b[4] = AMPP_FUNCTION(GND, GND, QC2__clk0, QC2__clk0, !S1_M_wr_dst_reg, S1_W_stall, S1L2398, S1_M_dst_regnum[0], S1_M_dst_regnum[1], S1_M_dst_regnum[2], S1_M_dst_regnum[3], S1_M_dst_regnum[4], AD1_q_b[27], AD1_q_b[28], AD1_q_b[29], AD1_q_b[30], AD1_q_b[31], GND, GND, GND, GND, S1L2401, S1L2458, S1L2455, S1L2449, S1L2446, S1L2464, S1L2440, S1L2437, S1L2434, S1L2431, S1L2428, S1L2443, S1L2467, S1L2452, S1L2461, S1L2425, S1L2422, S1L2419, S1L2416, S1L2537, S1L2410, S1L2404, S1L2407, S1L2517, S1L2395, S1L2470, S1L2495, S1L2473, S1L2482, S1L2476, S1L2479);

--CD1_q_b[6] is std_1c20:inst|cpu:the_cpu|cpu_register_bank_a_module:cpu_register_bank_a|altsyncram:the_altsyncram|altsyncram_3vd1:auto_generated|q_b[6] at M4K_X49_Y16

CD1_q_b[6] = AMPP_FUNCTION(GND, GND, QC2__clk0, QC2__clk0, !S1_M_wr_dst_reg, S1_W_stall, S1L2398, S1_M_dst_regnum[0], S1_M_dst_regnum[1], S1_M_dst_regnum[2], S1_M_dst_regnum[3], S1_M_dst_regnum[4], AD1_q_b[27], AD1_q_b[28], AD1_q_b[29], AD1_q_b[30], AD1_q_b[31], GND, GND, GND, GND, S1L2401, S1L2458, S1L2455, S1L2449, S1L2446, S1L2464, S1L2440, S1L2437, S1L2434, S1L2431, S1L2428, S1L2443, S1L2467, S1L2452, S1L2461, S1L2425, S1L2422, S1L2419, S1L2416, S1L2537, S1L2410, S1L2404, S1L2407, S1L2517, S1L2395, S1L2470, S1L2495, S1L2473, S1L2482, S1L2476, S1L2479);

--CD1_q_b[7] is std_1c20:inst|cpu:the_cpu|cpu_register_bank_a_module:cpu_register_bank_a|altsyncram:the_altsyncram|altsyncram_3vd1:auto_generated|q_b[7] at M4K_X49_Y16

CD1_q_b[7] = AMPP_FUNCTION(GND, GND, QC2__clk0, QC2__clk0, !S1_M_wr_dst_reg, S1_W_stall, S1L2398, S1_M_dst_regnum[0], S1_M_dst_regnum[1], S1_M_dst_regnum[2], S1_M_dst_regnum[3], S1_M_dst_regnum[4], AD1_q_b[27], AD1_q_b[28], AD1_q_b[29], AD1_q_b[30], AD1_q_b[31], GND, GND, GND, GND, S1L2401, S1L2458, S1L2455, S1L2449, S1L2446, S1L2464, S1L2440, S1L2437, S1L2434, S1L2431, S1L2428, S1L2443, S1L2467, S1L2452, S1L2461, S1L2425, S1L2422, S1L2419, S1L2416, S1L2537, S1L2410, S1L2404, S1L2407, S1L2517, S1L2395, S1L2470, S1L2495, S1L2473, S1L2482, S1L2476, S1L2479);

--CD1_q_b[8] is std_1c20:inst|cpu:the_cpu|cpu_register_bank_a_module:cpu_register_bank_a|altsyncram:the_altsyncram|altsyncram_3vd1:auto_generated|q_b[8] at M4K_X49_Y16

CD1_q_b[8] = AMPP_FUNCTION(GND, GND, QC2__clk0, QC2__clk0, !S1_M_wr_dst_reg, S1_W_stall, S1L2398, S1_M_dst_regnum[0], S1_M_dst_regnum[1], S1_M_dst_regnum[2], S1_M_dst_regnum[3], S1_M_dst_regnum[4], AD1_q_b[27], AD1_q_b[28], AD1_q_b[29], AD1_q_b[30], AD1_q_b[31], GND, GND, GND, GND, S1L2401, S1L2458, S1L2455, S1L2449, S1L2446, S1L2464, S1L2440, S1L2437, S1L2434, S1L2431, S1L2428, S1L2443, S1L2467, S1L2452, S1L2461, S1L2425, S1L2422, S1L2419, S1L2416, S1L2537, S1L2410, S1L2404, S1L2407, S1L2517, S1L2395, S1L2470, S1L2495, S1L2473, S1L2482, S1L2476, S1L2479);

--CD1_q_b[9] is std_1c20:inst|cpu:the_cpu|cpu_register_bank_a_module:cpu_register_bank_a|altsyncram:the_altsyncram|altsyncram_3vd1:auto_generated|q_b[9] at M4K_X49_Y16

CD1_q_b[9] = AMPP_FUNCTION(GND, GND, QC2__clk0, QC2__clk0, !S1_M_wr_dst_reg, S1_W_stall, S1L2398, S1_M_dst_regnum[0], S1_M_dst_regnum[1], S1_M_dst_regnum[2], S1_M_dst_regnum[3], S1_M_dst_regnum[4], AD1_q_b[27], AD1_q_b[28], AD1_q_b[29], AD1_q_b[30], AD1_q_b[31], GND, GND, GND, GND, S1L2401, S1L2458, S1L2455, S1L2449, S1L2446, S1L2464, S1L2440, S1L2437, S1L2434, S1L2431, S1L2428, S1L2443, S1L2467, S1L2452, S1L2461, S1L2425, S1L2422, S1L2419, S1L2416, S1L2537, S1L2410, S1L2404, S1L2407, S1L2517, S1L2395, S1L2470, S1L2495, S1L2473, S1L2482, S1L2476, S1L2479);

--CD1_q_b[10] is std_1c20:inst|cpu:the_cpu|cpu_register_bank_a_module:cpu_register_bank_a|altsyncram:the_altsyncram|altsyncram_3vd1:auto_generated|q_b[10] at M4K_X49_Y16

CD1_q_b[10] = AMPP_FUNCTION(GND, GND, QC2__clk0, QC2__clk0, !S1_M_wr_dst_reg, S1_W_stall, S1L2398, S1_M_dst_regnum[0], S1_M_dst_regnum[1], S1_M_dst_regnum[2], S1_M_dst_regnum[3], S1_M_dst_regnum[4], AD1_q_b[27], AD1_q_b[28], AD1_q_b[29], AD1_q_b[30], AD1_q_b[31], GND, GND, GND, GND, S1L2401, S1L2458, S1L2455, S1L2449, S1L2446, S1L2464, S1L2440, S1L2437, S1L2434, S1L2431, S1L2428, S1L2443, S1L2467, S1L2452, S1L2461, S1L2425, S1L2422, S1L2419, S1L2416, S1L2537, S1L2410, S1L2404, S1L2407, S1L2517, S1L2395, S1L2470, S1L2495, S1L2473, S1L2482, S1L2476, S1L2479);

--CD1_q_b[11] is std_1c20:inst|cpu:the_cpu|cpu_register_bank_a_module:cpu_register_bank_a|altsyncram:the_altsyncram|altsyncram_3vd1:auto_generated|q_b[11] at M4K_X49_Y16

CD1_q_b[11] = AMPP_FUNCTION(GND, GND, QC2__clk0, QC2__clk0, !S1_M_wr_dst_reg, S1_W_stall, S1L2398, S1_M_dst_regnum[0], S1_M_dst_regnum[1], S1_M_dst_regnum[2], S1_M_dst_regnum[3], S1_M_dst_regnum[4], AD1_q_b[27], AD1_q_b[28], AD1_q_b[29], AD1_q_b[30], AD1_q_b[31], GND, GND, GND, GND, S1L2401, S1L2458, S1L2455, S1L2449, S1L2446, S1L2464, S1L2440, S1L2437, S1L2434, S1L2431, S1L2428, S1L2443, S1L2467, S1L2452, S1L2461, S1L2425, S1L2422, S1L2419, S1L2416, S1L2537, S1L2410, S1L2404, S1L2407, S1L2517, S1L2395, S1L2470, S1L2495, S1L2473, S1L2482, S1L2476, S1L2479);

--CD1_q_b[23] is std_1c20:inst|cpu:the_cpu|cpu_register_bank_a_module:cpu_register_bank_a|altsyncram:the_altsyncram|altsyncram_3vd1:auto_generated|q_b[23] at M4K_X49_Y16

CD1_q_b[23] = AMPP_FUNCTION(GND, GND, QC2__clk0, QC2__clk0, !S1_M_wr_dst_reg, S1_W_stall, S1L2398, S1_M_dst_regnum[0], S1_M_dst_regnum[1], S1_M_dst_regnum[2], S1_M_dst_regnum[3], S1_M_dst_regnum[4], AD1_q_b[27], AD1_q_b[28], AD1_q_b[29], AD1_q_b[30], AD1_q_b[31], GND, GND, GND, GND, S1L2401, S1L2458, S1L2455, S1L2449, S1L2446, S1L2464, S1L2440, S1L2437, S1L2434, S1L2431, S1L2428, S1L2443, S1L2467, S1L2452, S1L2461, S1L2425, S1L2422, S1L2419, S1L2416, S1L2537, S1L2410, S1L2404, S1L2407, S1L2517, S1L2395, S1L2470, S1L2495, S1L2473, S1L2482, S1L2476, S1L2479);

--CD1_q_b[20] is std_1c20:inst|cpu:the_cpu|cpu_register_bank_a_module:cpu_register_bank_a|altsyncram:the_altsyncram|altsyncram_3vd1:auto_generated|q_b[20] at M4K_X49_Y16

CD1_q_b[20] = AMPP_FUNCTION(GND, GND, QC2__clk0, QC2__clk0, !S1_M_wr_dst_reg, S1_W_stall, S1L2398, S1_M_dst_regnum[0], S1_M_dst_regnum[1], S1_M_dst_regnum[2], S1_M_dst_regnum[3], S1_M_dst_regnum[4], AD1_q_b[27], AD1_q_b[28], AD1_q_b[29], AD1_q_b[30], AD1_q_b[31], GND, GND, GND, GND, S1L2401, S1L2458, S1L2455, S1L2449, S1L2446, S1L2464, S1L2440, S1L2437, S1L2434, S1L2431, S1L2428, S1L2443, S1L2467, S1L2452, S1L2461, S1L2425, S1L2422, S1L2419, S1L2416, S1L2537, S1L2410, S1L2404, S1L2407, S1L2517, S1L2395, S1L2470, S1L2495, S1L2473, S1L2482, S1L2476, S1L2479);

--CD1_q_b[25] is std_1c20:inst|cpu:the_cpu|cpu_register_bank_a_module:cpu_register_bank_a|altsyncram:the_altsyncram|altsyncram_3vd1:auto_generated|q_b[25] at M4K_X49_Y16

CD1_q_b[25] = AMPP_FUNCTION(GND, GND, QC2__clk0, QC2__clk0, !S1_M_wr_dst_reg, S1_W_stall, S1L2398, S1_M_dst_regnum[0], S1_M_dst_regnum[1], S1_M_dst_regnum[2], S1_M_dst_regnum[3], S1_M_dst_regnum[4], AD1_q_b[27], AD1_q_b[28], AD1_q_b[29], AD1_q_b[30], AD1_q_b[31], GND, GND, GND, GND, S1L2401, S1L2458, S1L2455, S1L2449, S1L2446, S1L2464, S1L2440, S1L2437, S1L2434, S1L2431, S1L2428, S1L2443, S1L2467, S1L2452, S1L2461, S1L2425, S1L2422, S1L2419, S1L2416, S1L2537, S1L2410, S1L2404, S1L2407, S1L2517, S1L2395, S1L2470, S1L2495, S1L2473, S1L2482, S1L2476, S1L2479);

--CD1_q_b[17] is std_1c20:inst|cpu:the_cpu|cpu_register_bank_a_module:cpu_register_bank_a|altsyncram:the_altsyncram|altsyncram_3vd1:auto_generated|q_b[17] at M4K_X49_Y16

CD1_q_b[17] = AMPP_FUNCTION(GND, GND, QC2__clk0, QC2__clk0, !S1_M_wr_dst_reg, S1_W_stall, S1L2398, S1_M_dst_regnum[0], S1_M_dst_regnum[1], S1_M_dst_regnum[2], S1_M_dst_regnum[3], S1_M_dst_regnum[4], AD1_q_b[27], AD1_q_b[28], AD1_q_b[29], AD1_q_b[30], AD1_q_b[31], GND, GND, GND, GND, S1L2401, S1L2458, S1L2455, S1L2449, S1L2446, S1L2464, S1L2440, S1L2437, S1L2434, S1L2431, S1L2428, S1L2443, S1L2467, S1L2452, S1L2461, S1L2425, S1L2422, S1L2419, S1L2416, S1L2537, S1L2410, S1L2404, S1L2407, S1L2517, S1L2395, S1L2470, S1L2495, S1L2473, S1L2482, S1L2476, S1L2479);

--CD1_q_b[12] is std_1c20:inst|cpu:the_cpu|cpu_register_bank_a_module:cpu_register_bank_a|altsyncram:the_altsyncram|altsyncram_3vd1:auto_generated|q_b[12] at M4K_X49_Y16

CD1_q_b[12] = AMPP_FUNCTION(GND, GND, QC2__clk0, QC2__clk0, !S1_M_wr_dst_reg, S1_W_stall, S1L2398, S1_M_dst_regnum[0], S1_M_dst_regnum[1], S1_M_dst_regnum[2], S1_M_dst_regnum[3], S1_M_dst_regnum[4], AD1_q_b[27], AD1_q_b[28], AD1_q_b[29], AD1_q_b[30], AD1_q_b[31], GND, GND, GND, GND, S1L2401, S1L2458, S1L2455, S1L2449, S1L2446, S1L2464, S1L2440, S1L2437, S1L2434, S1L2431, S1L2428, S1L2443, S1L2467, S1L2452, S1L2461, S1L2425, S1L2422, S1L2419, S1L2416, S1L2537, S1L2410, S1L2404, S1L2407, S1L2517, S1L2395, S1L2470, S1L2495, S1L2473, S1L2482, S1L2476, S1L2479);

--CD1_q_b[13] is std_1c20:inst|cpu:the_cpu|cpu_register_bank_a_module:cpu_register_bank_a|altsyncram:the_altsyncram|altsyncram_3vd1:auto_generated|q_b[13] at M4K_X49_Y16

CD1_q_b[13] = AMPP_FUNCTION(GND, GND, QC2__clk0, QC2__clk0, !S1_M_wr_dst_reg, S1_W_stall, S1L2398, S1_M_dst_regnum[0], S1_M_dst_regnum[1], S1_M_dst_regnum[2], S1_M_dst_regnum[3], S1_M_dst_regnum[4], AD1_q_b[27], AD1_q_b[28], AD1_q_b[29], AD1_q_b[30], AD1_q_b[31], GND, GND, GND, GND, S1L2401, S1L2458, S1L2455, S1L2449, S1L2446, S1L2464, S1L2440, S1L2437, S1L2434, S1L2431, S1L2428, S1L2443, S1L2467, S1L2452, S1L2461, S1L2425, S1L2422, S1L2419, S1L2416, S1L2537, S1L2410, S1L2404, S1L2407, S1L2517, S1L2395, S1L2470, S1L2495, S1L2473, S1L2482, S1L2476, S1L2479);

--CD1_q_b[14] is std_1c20:inst|cpu:the_cpu|cpu_register_bank_a_module:cpu_register_bank_a|altsyncram:the_altsyncram|altsyncram_3vd1:auto_generated|q_b[14] at M4K_X49_Y16

CD1_q_b[14] = AMPP_FUNCTION(GND, GND, QC2__clk0, QC2__clk0, !S1_M_wr_dst_reg, S1_W_stall, S1L2398, S1_M_dst_regnum[0], S1_M_dst_regnum[1], S1_M_dst_regnum[2], S1_M_dst_regnum[3], S1_M_dst_regnum[4], AD1_q_b[27], AD1_q_b[28], AD1_q_b[29], AD1_q_b[30], AD1_q_b[31], GND, GND, GND, GND, S1L2401, S1L2458, S1L2455, S1L2449, S1L2446, S1L2464, S1L2440, S1L2437, S1L2434, S1L2431, S1L2428, S1L2443, S1L2467, S1L2452, S1L2461, S1L2425, S1L2422, S1L2419, S1L2416, S1L2537, S1L2410, S1L2404, S1L2407, S1L2517, S1L2395, S1L2470, S1L2495, S1L2473, S1L2482, S1L2476, S1L2479);

--CD1_q_b[15] is std_1c20:inst|cpu:the_cpu|cpu_register_bank_a_module:cpu_register_bank_a|altsyncram:the_altsyncram|altsyncram_3vd1:auto_generated|q_b[15] at M4K_X49_Y16

CD1_q_b[15] = AMPP_FUNCTION(GND, GND, QC2__clk0, QC2__clk0, !S1_M_wr_dst_reg, S1_W_stall, S1L2398, S1_M_dst_regnum[0], S1_M_dst_regnum[1], S1_M_dst_regnum[2], S1_M_dst_regnum[3], S1_M_dst_regnum[4], AD1_q_b[27], AD1_q_b[28], AD1_q_b[29], AD1_q_b[30], AD1_q_b[31], GND, GND, GND, GND, S1L2401, S1L2458, S1L2455, S1L2449, S1L2446, S1L2464, S1L2440, S1L2437, S1L2434, S1L2431, S1L2428, S1L2443, S1L2467, S1L2452, S1L2461, S1L2425, S1L2422, S1L2419, S1L2416, S1L2537, S1L2410, S1L2404, S1L2407, S1L2517, S1L2395, S1L2470, S1L2495, S1L2473, S1L2482, S1L2476, S1L2479);

--CD1_q_b[16] is std_1c20:inst|cpu:the_cpu|cpu_register_bank_a_module:cpu_register_bank_a|altsyncram:the_altsyncram|altsyncram_3vd1:auto_generated|q_b[16] at M4K_X49_Y16

CD1_q_b[16] = AMPP_FUNCTION(GND, GND, QC2__clk0, QC2__clk0, !S1_M_wr_dst_reg, S1_W_stall, S1L2398, S1_M_dst_regnum[0], S1_M_dst_regnum[1], S1_M_dst_regnum[2], S1_M_dst_regnum[3], S1_M_dst_regnum[4], AD1_q_b[27], AD1_q_b[28], AD1_q_b[29], AD1_q_b[30], AD1_q_b[31], GND, GND, GND, GND, S1L2401, S1L2458, S1L2455, S1L2449, S1L2446, S1L2464, S1L2440, S1L2437, S1L2434, S1L2431, S1L2428, S1L2443, S1L2467, S1L2452, S1L2461, S1L2425, S1L2422, S1L2419, S1L2416, S1L2537, S1L2410, S1L2404, S1L2407, S1L2517, S1L2395, S1L2470, S1L2495, S1L2473, S1L2482, S1L2476, S1L2479);

--CD1_q_b[24] is std_1c20:inst|cpu:the_cpu|cpu_register_bank_a_module:cpu_register_bank_a|altsyncram:the_altsyncram|altsyncram_3vd1:auto_generated|q_b[24] at M4K_X49_Y16

CD1_q_b[24] = AMPP_FUNCTION(GND, GND, QC2__clk0, QC2__clk0, !S1_M_wr_dst_reg, S1_W_stall, S1L2398, S1_M_dst_regnum[0], S1_M_dst_regnum[1], S1_M_dst_regnum[2], S1_M_dst_regnum[3], S1_M_dst_regnum[4], AD1_q_b[27], AD1_q_b[28], AD1_q_b[29], AD1_q_b[30], AD1_q_b[31], GND, GND, GND, GND, S1L2401, S1L2458, S1L2455, S1L2449, S1L2446, S1L2464, S1L2440, S1L2437, S1L2434, S1L2431, S1L2428, S1L2443, S1L2467, S1L2452, S1L2461, S1L2425, S1L2422, S1L2419, S1L2416, S1L2537, S1L2410, S1L2404, S1L2407, S1L2517, S1L2395, S1L2470, S1L2495, S1L2473, S1L2482, S1L2476, S1L2479);

--CD1_q_b[18] is std_1c20:inst|cpu:the_cpu|cpu_register_bank_a_module:cpu_register_bank_a|altsyncram:the_altsyncram|altsyncram_3vd1:auto_generated|q_b[18] at M4K_X49_Y16

CD1_q_b[18] = AMPP_FUNCTION(GND, GND, QC2__clk0, QC2__clk0, !S1_M_wr_dst_reg, S1_W_stall, S1L2398, S1_M_dst_regnum[0], S1_M_dst_regnum[1], S1_M_dst_regnum[2], S1_M_dst_regnum[3], S1_M_dst_regnum[4], AD1_q_b[27], AD1_q_b[28], AD1_q_b[29], AD1_q_b[30], AD1_q_b[31], GND, GND, GND, GND, S1L2401, S1L2458, S1L2455, S1L2449, S1L2446, S1L2464, S1L2440, S1L2437, S1L2434, S1L2431, S1L2428, S1L2443, S1L2467, S1L2452, S1L2461, S1L2425, S1L2422, S1L2419, S1L2416, S1L2537, S1L2410, S1L2404, S1L2407, S1L2517, S1L2395, S1L2470, S1L2495, S1L2473, S1L2482, S1L2476, S1L2479);

--CD1_q_b[19] is std_1c20:inst|cpu:the_cpu|cpu_register_bank_a_module:cpu_register_bank_a|altsyncram:the_altsyncram|altsyncram_3vd1:auto_generated|q_b[19] at M4K_X49_Y16

CD1_q_b[19] = AMPP_FUNCTION(GND, GND, QC2__clk0, QC2__clk0, !S1_M_wr_dst_reg, S1_W_stall, S1L2398, S1_M_dst_regnum[0], S1_M_dst_regnum[1], S1_M_dst_regnum[2], S1_M_dst_regnum[3], S1_M_dst_regnum[4], AD1_q_b[27], AD1_q_b[28], AD1_q_b[29], AD1_q_b[30], AD1_q_b[31], GND, GND, GND, GND, S1L2401, S1L2458, S1L2455, S1L2449, S1L2446, S1L2464, S1L2440, S1L2437, S1L2434, S1L2431, S1L2428, S1L2443, S1L2467, S1L2452, S1L2461, S1L2425, S1L2422, S1L2419, S1L2416, S1L2537, S1L2410, S1L2404, S1L2407, S1L2517, S1L2395, S1L2470, S1L2495, S1L2473, S1L2482, S1L2476, S1L2479);

--CD1_q_b[21] is std_1c20:inst|cpu:the_cpu|cpu_register_bank_a_module:cpu_register_bank_a|altsyncram:the_altsyncram|altsyncram_3vd1:auto_generated|q_b[21] at M4K_X49_Y16

CD1_q_b[21] = AMPP_FUNCTION(GND, GND, QC2__clk0, QC2__clk0, !S1_M_wr_dst_reg, S1_W_stall, S1L2398, S1_M_dst_regnum[0], S1_M_dst_regnum[1], S1_M_dst_regnum[2], S1_M_dst_regnum[3], S1_M_dst_regnum[4], AD1_q_b[27], AD1_q_b[28], AD1_q_b[29], AD1_q_b[30], AD1_q_b[31], GND, GND, GND, GND, S1L2401, S1L2458, S1L2455, S1L2449, S1L2446, S1L2464, S1L2440, S1L2437, S1L2434, S1L2431, S1L2428, S1L2443, S1L2467, S1L2452, S1L2461, S1L2425, S1L2422, S1L2419, S1L2416, S1L2537, S1L2410, S1L2404, S1L2407, S1L2517, S1L2395, S1L2470, S1L2495, S1L2473, S1L2482, S1L2476, S1L2479);

--CD1_q_b[22] is std_1c20:inst|cpu:the_cpu|cpu_register_bank_a_module:cpu_register_bank_a|altsyncram:the_altsyncram|altsyncram_3vd1:auto_generated|q_b[22] at M4K_X49_Y16

CD1_q_b[22] = AMPP_FUNCTION(GND, GND, QC2__clk0, QC2__clk0, !S1_M_wr_dst_reg, S1_W_stall, S1L2398, S1_M_dst_regnum[0], S1_M_dst_regnum[1], S1_M_dst_regnum[2], S1_M_dst_regnum[3], S1_M_dst_regnum[4], AD1_q_b[27], AD1_q_b[28], AD1_q_b[29], AD1_q_b[30], AD1_q_b[31], GND, GND, GND, GND, S1L2401, S1L2458, S1L2455, S1L2449, S1L2446, S1L2464, S1L2440, S1L2437, S1L2434, S1L2431, S1L2428, S1L2443, S1L2467, S1L2452, S1L2461, S1L2425, S1L2422, S1L2419, S1L2416, S1L2537, S1L2410, S1L2404, S1L2407, S1L2517, S1L2395, S1L2470, S1L2495, S1L2473, S1L2482, S1L2476, S1L2479);

--CD1_q_b[3] is std_1c20:inst|cpu:the_cpu|cpu_register_bank_a_module:cpu_register_bank_a|altsyncram:the_altsyncram|altsyncram_3vd1:auto_generated|q_b[3] at M4K_X49_Y16

CD1_q_b[3] = AMPP_FUNCTION(GND, GND, QC2__clk0, QC2__clk0, !S1_M_wr_dst_reg, S1_W_stall, S1L2398, S1_M_dst_regnum[0], S1_M_dst_regnum[1], S1_M_dst_regnum[2], S1_M_dst_regnum[3], S1_M_dst_regnum[4], AD1_q_b[27], AD1_q_b[28], AD1_q_b[29], AD1_q_b[30], AD1_q_b[31], GND, GND, GND, GND, S1L2401, S1L2458, S1L2455, S1L2449, S1L2446, S1L2464, S1L2440, S1L2437, S1L2434, S1L2431, S1L2428, S1L2443, S1L2467, S1L2452, S1L2461, S1L2425, S1L2422, S1L2419, S1L2416, S1L2537, S1L2410, S1L2404, S1L2407, S1L2517, S1L2395, S1L2470, S1L2495, S1L2473, S1L2482, S1L2476, S1L2479);

--S1_D_iw[29] is std_1c20:inst|cpu:the_cpu|D_iw[29] at LC_X31_Y17_N8

--operation mode is normal

S1_D_iw[29] = AMPP_FUNCTION(QC2__clk0, S1L2381, AD1_q_b[29], S1L1709, S1L1257, F1_data_out, S1_W_stall);

--S1_D_iw[28] is std_1c20:inst|cpu:the_cpu|D_iw[28] at LC_X30_Y16_N2

--operation mode is normal

S1_D_iw[28] = AMPP_FUNCTION(QC2__clk0, S1L1709, AD1_q_b[28], S1L1257, S1L2381, F1_data_out, S1_W_stall);

--S1L655 is std_1c20:inst|cpu:the_cpu|D_src1_hazard_W~39 at LC_X33_Y16_N9

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

S1L655 = AMPP_FUNCTION(S1_D_iw[29], S1_D_iw[28], S1_W_dst_regnum[2]);

--S1_W_dst_regnum[1] is std_1c20:inst|cpu:the_cpu|W_dst_regnum[1] at LC_X33_Y16_N9

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

S1_W_dst_regnum[1] = AMPP_FUNCTION(QC2__clk0, S1_M_dst_regnum[1], F1_data_out, GND, S1_W_stall);

--S1_D_iw[30] is std_1c20:inst|cpu:the_cpu|D_iw[30] at LC_X32_Y16_N9

--operation mode is normal

S1_D_iw[30] = AMPP_FUNCTION(QC2__clk0, S1L2381, S1L1709, S1L1257, AD1_q_b[30], F1_data_out, S1_W_stall);

--S1_D_iw[27] is std_1c20:inst|cpu:the_cpu|D_iw[27] at LC_X30_Y16_N7

--operation mode is normal

S1_D_iw[27] = AMPP_FUNCTION(QC2__clk0, S1L1709, AD1_q_b[27], S1L1257, S1L2381, F1_data_out, S1_W_stall);

--S1L656 is std_1c20:inst|cpu:the_cpu|D_src1_hazard_W~40 at LC_X33_Y16_N1

--operation mode is normal

S1L656 = AMPP_FUNCTION(S1_D_iw[27], S1_D_iw[30], S1_W_dst_regnum[0], S1_W_dst_regnum[3]);

--S1_W_wr_dst_reg is std_1c20:inst|cpu:the_cpu|W_wr_dst_reg at LC_X34_Y15_N3

--operation mode is normal

S1_W_wr_dst_reg = AMPP_FUNCTION(QC2__clk0, S1_M_wr_dst_reg, F1_data_out, S1_W_stall);

--S1_D_iw[31] is std_1c20:inst|cpu:the_cpu|D_iw[31] at LC_X32_Y16_N6

--operation mode is normal

S1_D_iw[31] = AMPP_FUNCTION(QC2__clk0, S1L2381, S1L1709, S1L1257, AD1_q_b[31], F1_data_out, S1_W_stall);

--S1L657 is std_1c20:inst|cpu:the_cpu|D_src1_hazard_W~41 at LC_X33_Y16_N5

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

S1L657 = AMPP_FUNCTION(S1_D_iw[31], S1_W_wr_dst_reg);

--S1_W_dst_regnum[4] is std_1c20:inst|cpu:the_cpu|W_dst_regnum[4] at LC_X33_Y16_N5

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

S1_W_dst_regnum[4] = AMPP_FUNCTION(QC2__clk0, S1_M_dst_regnum[4], F1_data_out, GND, S1_W_stall);

--S1L274 is std_1c20:inst|cpu:the_cpu|D_ctrl_a_not_src~78 at LC_X28_Y15_N2

--operation mode is normal

S1L274 = AMPP_FUNCTION(S1_D_iw[5], S1_D_iw[4]);

--S1L275 is std_1c20:inst|cpu:the_cpu|D_ctrl_a_not_src~79 at LC_X31_Y15_N4

--operation mode is normal

S1L275 = AMPP_FUNCTION(S1_D_iw[2], S1_D_iw[1], S1_D_iw[3], S1L274);

--S1_E_ctrl_jmp_direct is std_1c20:inst|cpu:the_cpu|E_ctrl_jmp_direct at LC_X31_Y15_N4

--operation mode is normal

S1_E_ctrl_jmp_direct = AMPP_FUNCTION(QC2__clk0, S1_D_iw[2], S1_D_iw[1], S1_D_iw[3], S1L274, F1_data_out, S1_W_stall);

--S1_D_src1_hazard_W is std_1c20:inst|cpu:the_cpu|D_src1_hazard_W at LC_X33_Y16_N4

--operation mode is normal

S1_D_src1_hazard_W = AMPP_FUNCTION(S1L656, S1L657, S1L655, S1L275);

--S1L651 is std_1c20:inst|cpu:the_cpu|D_src1_hazard_M~39 at LC_X33_Y16_N0

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

S1L651 = AMPP_FUNCTION(S1_D_iw[29], S1_D_iw[28], S1_M_dst_regnum[2]);

--S1_M_dst_regnum[1] is std_1c20:inst|cpu:the_cpu|M_dst_regnum[1] at LC_X33_Y16_N0

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

S1_M_dst_regnum[1] = AMPP_FUNCTION(QC2__clk0, S1_E_dst_regnum[1], F1_data_out, GND, S1_W_stall);

--S1L652 is std_1c20:inst|cpu:the_cpu|D_src1_hazard_M~40 at LC_X33_Y16_N2

--operation mode is normal

S1L652 = AMPP_FUNCTION(S1_D_iw[27], S1_M_dst_regnum[3], S1_M_dst_regnum[0], S1_D_iw[30]);

--S1_M_wr_dst_reg is std_1c20:inst|cpu:the_cpu|M_wr_dst_reg at LC_X34_Y15_N4

--operation mode is normal

S1_M_wr_dst_reg = AMPP_FUNCTION(QC2__clk0, S1L1163, F1_data_out, S1_W_stall);

--S1L653 is std_1c20:inst|cpu:the_cpu|D_src1_hazard_M~41 at LC_X33_Y16_N3

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

S1L653 = AMPP_FUNCTION(S1_M_wr_dst_reg, S1_D_iw[31]);

--S1_M_dst_regnum[4] is std_1c20:inst|cpu:the_cpu|M_dst_regnum[4] at LC_X33_Y16_N3

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

S1_M_dst_regnum[4] = AMPP_FUNCTION(QC2__clk0, S1_E_dst_regnum[4], F1_data_out, GND, S1_W_stall);

--S1_D_src1_hazard_M is std_1c20:inst|cpu:the_cpu|D_src1_hazard_M at LC_X33_Y16_N8

--operation mode is normal

S1_D_src1_hazard_M = AMPP_FUNCTION(S1L651, S1L653, S1L652, S1L275);

--S1_E_wr_dst_reg_from_D is std_1c20:inst|cpu:the_cpu|E_wr_dst_reg_from_D at LC_X33_Y14_N5

--operation mode is normal

S1_E_wr_dst_reg_from_D = AMPP_FUNCTION(QC2__clk0, S1L672, S1L1188, S1L1189, S1L316, F1_data_out, S1_W_stall);

--S1L1162 is std_1c20:inst|cpu:the_cpu|E_wr_dst_reg~37 at LC_X30_Y14_N7

--operation mode is normal

S1L1162 = AMPP_FUNCTION(S1_M_pipe_flush, S1_E_wr_dst_reg_from_D);

--S1L1163 is std_1c20:inst|cpu:the_cpu|E_wr_dst_reg~38 at LC_X30_Y15_N6

--operation mode is normal

S1L1163 = AMPP_FUNCTION(S1L1162, S1L762, S1L761, S1L1356);

--S1_E_dst_regnum[4] is std_1c20:inst|cpu:the_cpu|E_dst_regnum[4] at LC_X33_Y14_N9

--operation mode is normal

S1_E_dst_regnum[4] = AMPP_FUNCTION(QC2__clk0, S1L304, S1L275, S1L317, F1_data_out, S1_W_stall);

--S1_E_dst_regnum[1] is std_1c20:inst|cpu:the_cpu|E_dst_regnum[1] at LC_X33_Y14_N6

--operation mode is normal

S1_E_dst_regnum[1] = AMPP_FUNCTION(QC2__clk0, S1L275, S1L304, S1L313, F1_data_out, S1_W_stall);

--S1L647 is std_1c20:inst|cpu:the_cpu|D_src1_hazard_E~54 at LC_X33_Y16_N6

--operation mode is normal

S1L647 = AMPP_FUNCTION(S1_D_iw[28], S1_E_dst_regnum[1], S1_E_dst_regnum[4], S1_D_iw[31]);

--S1_E_dst_regnum[2] is std_1c20:inst|cpu:the_cpu|E_dst_regnum[2] at LC_X33_Y14_N2

--operation mode is normal

S1_E_dst_regnum[2] = AMPP_FUNCTION(QC2__clk0, S1L275, S1L314, S1L304, F1_data_out, S1_W_stall);

--S1L648 is std_1c20:inst|cpu:the_cpu|D_src1_hazard_E~55 at LC_X33_Y16_N7

--operation mode is normal

S1L648 = AMPP_FUNCTION(S1_D_iw[29], S1_E_dst_regnum[2], S1L647);

--S1_E_dst_regnum[0] is std_1c20:inst|cpu:the_cpu|E_dst_regnum[0] at LC_X33_Y14_N1

--operation mode is normal

S1_E_dst_regnum[0] = AMPP_FUNCTION(QC2__clk0, S1L304, S1L275, S1L312, F1_data_out, S1_W_stall);

--S1L649 is std_1c20:inst|cpu:the_cpu|D_src1_hazard_E~56 at LC_X33_Y15_N7

--operation mode is normal

S1L649 = AMPP_FUNCTION(S1_D_iw[30], S1_E_dst_regnum[3], S1_E_dst_regnum[0], S1_D_iw[27]);

--S1_M_shift_rot_result[1] is std_1c20:inst|cpu:the_cpu|M_shift_rot_result[1] at LC_X38_Y16_N0

--operation mode is normal

S1_M_shift_rot_result[1] = AMPP_FUNCTION(QC2__clk0, S1_M_shift_rot_result[2], S1_M_shift_rot_result[0], S1L852, S1_M_ctrl_shift_rot_right, F1_data_out, !S1_M_shift_rot_stall);

--S1_M_ctrl_shift_rot_right is std_1c20:inst|cpu:the_cpu|M_ctrl_shift_rot_right at LC_X38_Y15_N6

--operation mode is normal

S1_M_ctrl_shift_rot_right = AMPP_FUNCTION(QC2__clk0, S1_E_ctrl_shift_rot_right, F1_data_out, S1_W_stall);

--S1L462Q is std_1c20:inst|cpu:the_cpu|d_readdata_d1[2]~86 at LC_X43_Y25_N2

--operation mode is normal

S1L462Q = AMPP_FUNCTION(QC2__clk0, X1_cpu_data_master_requests_epcs_controller_epcs_control_port, U1L151, S1L468, S1L470, F1_data_out);

--S1L438Q is std_1c20:inst|cpu:the_cpu|d_readdata_d1[0]~96 at LC_X39_Y19_N7

--operation mode is normal

S1L438Q = AMPP_FUNCTION(QC2__clk0, K1L3, V1L8, F1_data_out);

--S1L1374 is std_1c20:inst|cpu:the_cpu|i_readdata_d1[2]~136 at LC_X44_Y19_N6

--operation mode is normal

S1L1374 = AMPP_FUNCTION(S1L524Q, S1L1367Q, WC1L3, S1L1375Q);

--T1_cpu_data_master_readdata[2] is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[2] at LC_X39_Y19_N8

--operation mode is normal

T1_cpu_data_master_readdata[2] = S1L462Q & (S1L438Q # S1L1374);

--S1L577 is std_1c20:inst|cpu:the_cpu|d_readdata_d1[18]~177 at LC_X42_Y19_N4

--operation mode is normal

S1L577 = AMPP_FUNCTION(S1L522Q, S1L579Q, S1L524Q, S1L578Q);

--S1_M_ld_align_sh16 is std_1c20:inst|cpu:the_cpu|M_ld_align_sh16 at LC_X39_Y20_N1

--operation mode is normal

S1_M_ld_align_sh16 = AMPP_FUNCTION(S1_M_iw[4], S1_M_alu_result[1]);

--S1_M_ld_align_sh8 is std_1c20:inst|cpu:the_cpu|M_ld_align_sh8 at LC_X39_Y20_N5

--operation mode is normal

S1_M_ld_align_sh8 = AMPP_FUNCTION(S1_M_iw[3], S1_M_iw[4], S1L1716Q);

--S1_av_ld_aligning_data is std_1c20:inst|cpu:the_cpu|av_ld_aligning_data at LC_X42_Y19_N2

--operation mode is normal

S1_av_ld_aligning_data = AMPP_FUNCTION(QC2__clk0, T1_internal_cpu_data_master_waitrequest, S1_internal_d_read, F1_data_out);

--S1L300 is std_1c20:inst|cpu:the_cpu|D_ctrl_hi_imm~100 at LC_X31_Y15_N2

--operation mode is normal

S1L300 = AMPP_FUNCTION(S1_D_iw[0], S1_D_iw[1], S1_D_iw[3], S1_D_iw[4]);

--S1_E_src2_prelim[2] is std_1c20:inst|cpu:the_cpu|E_src2_prelim[2] at LC_X39_Y15_N1

--operation mode is normal

S1_E_src2_prelim[2] = AMPP_FUNCTION(QC2__clk0, DD1_q_b[2], S1_W_wr_data[2], S1L2398, S1L668, F1_data_out, S1L664, S1_W_stall);

--S1L1185 is std_1c20:inst|cpu:the_cpu|Equal143~6 at LC_X31_Y15_N7

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

S1L1185 = AMPP_FUNCTION(S1_E_iw[4]);

--S1_E_iw[3] is std_1c20:inst|cpu:the_cpu|E_iw[3] at LC_X31_Y15_N7

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

S1_E_iw[3] = AMPP_FUNCTION(QC2__clk0, S1_D_iw[3], F1_data_out, GND, S1_W_stall);

--S1L284 is std_1c20:inst|cpu:the_cpu|D_ctrl_b_is_dst~79 at LC_X28_Y14_N2

--operation mode is normal

S1L284 = AMPP_FUNCTION(S1_D_iw[0], S1_D_iw[1], S1_D_iw[4], S1_D_iw[5]);

--S1L285 is std_1c20:inst|cpu:the_cpu|D_ctrl_b_not_src~56 at LC_X28_Y14_N3

--operation mode is normal

S1L285 = AMPP_FUNCTION(S1_D_iw[0], S1_D_iw[2], S1_D_iw[1], S1L284);

--S1L1169 is std_1c20:inst|cpu:the_cpu|Equal53~852 at LC_X28_Y14_N9

--operation mode is normal

S1L1169 = AMPP_FUNCTION(S1_D_iw[0], S1_D_iw[1], S1_D_iw[2], S1_D_iw[3]);

--S1L1170 is std_1c20:inst|cpu:the_cpu|Equal53~853 at LC_X28_Y14_N4

--operation mode is normal

S1L1170 = AMPP_FUNCTION(S1_D_iw[4], S1L1169, S1_D_iw[5]);

--S1L308 is std_1c20:inst|cpu:the_cpu|D_ctrl_src2_is_imm~49 at LC_X28_Y14_N5

--operation mode is normal

S1L308 = AMPP_FUNCTION(S1L671, S1L285, S1L1170, S1L670);

--S1_D_iw[12] is std_1c20:inst|cpu:the_cpu|D_iw[12] at LC_X28_Y16_N8

--operation mode is normal

S1_D_iw[12] = AMPP_FUNCTION(QC2__clk0, S1L1709, S1L2381, S1L1257, AD1_q_b[12], F1_data_out, S1_W_stall);

--S1L1171 is std_1c20:inst|cpu:the_cpu|Equal53~854 at LC_X31_Y13_N4

--operation mode is normal

S1L1171 = AMPP_FUNCTION(S1_D_iw[4], S1_D_iw[5]);

--S1_D_iw[13] is std_1c20:inst|cpu:the_cpu|D_iw[13] at LC_X28_Y16_N2

--operation mode is normal

S1_D_iw[13] = AMPP_FUNCTION(QC2__clk0, S1L1709, S1L1257, S1L2381, AD1_q_b[13], F1_data_out, S1_W_stall);

--S1L307 is std_1c20:inst|cpu:the_cpu|D_ctrl_shift_rot~57 at LC_X32_Y14_N0

--operation mode is normal

S1L307 = AMPP_FUNCTION(S1_D_iw[13], S1L1171, S1_D_iw[12], S1L1168);

--S1_E_ctrl_shift_rot is std_1c20:inst|cpu:the_cpu|E_ctrl_shift_rot at LC_X32_Y14_N0

--operation mode is normal

S1_E_ctrl_shift_rot = AMPP_FUNCTION(QC2__clk0, S1_D_iw[13], S1L1171, S1_D_iw[12], S1L1168, F1_data_out, S1_W_stall);

--S1_D_iw[11] is std_1c20:inst|cpu:the_cpu|D_iw[11] at LC_X31_Y17_N0

--operation mode is normal

S1_D_iw[11] = AMPP_FUNCTION(QC2__clk0, S1L1257, S1L1709, AD1_q_b[11], S1L2381, F1_data_out, S1_W_stall);

--S1_D_iw[14] is std_1c20:inst|cpu:the_cpu|D_iw[14] at LC_X28_Y16_N7

--operation mode is normal

S1_D_iw[14] = AMPP_FUNCTION(QC2__clk0, S1L1709, S1L2381, S1L1257, AD1_q_b[14], F1_data_out, S1_W_stall);

--S1_D_br_taken_waddr_partial[0] is std_1c20:inst|cpu:the_cpu|D_br_taken_waddr_partial[0] at LC_X26_Y19_N5

--operation mode is arithmetic

S1_D_br_taken_waddr_partial[0] = AMPP_FUNCTION(QC2__clk0, S1L1284, AD1_q_b[8], F1_data_out, S1_W_stall);

--S1L243 is std_1c20:inst|cpu:the_cpu|D_br_taken_waddr_partial[0]~55 at LC_X26_Y19_N5

--operation mode is arithmetic

S1L243 = AMPP_FUNCTION(S1L1284, AD1_q_b[8]);

--S1L244 is std_1c20:inst|cpu:the_cpu|D_br_taken_waddr_partial[0]~55COUT1_460 at LC_X26_Y19_N5

--operation mode is arithmetic

S1L244 = AMPP_FUNCTION(S1L1284, AD1_q_b[8]);

--S1L286 is std_1c20:inst|cpu:the_cpu|D_ctrl_br_cond~94 at LC_X28_Y14_N8

--operation mode is normal

S1L286 = AMPP_FUNCTION(S1_D_iw[5], S1_D_iw[2], S1_D_iw[4], S1_D_iw[3]);

--S1L287 is std_1c20:inst|cpu:the_cpu|D_ctrl_br_cond~95 at LC_X27_Y15_N1

--operation mode is normal

S1L287 = AMPP_FUNCTION(S1_D_iw[0], S1_D_iw[1], S1L286);

--S1_D_iw[21] is std_1c20:inst|cpu:the_cpu|D_iw[21] at LC_X28_Y16_N4

--operation mode is normal

S1_D_iw[21] = AMPP_FUNCTION(QC2__clk0, S1L1709, S1L2381, S1L1257, AD1_q_b[21], F1_data_out, S1_W_stall);

--S1_E_ctrl_alu_subtract is std_1c20:inst|cpu:the_cpu|E_ctrl_alu_subtract at LC_X31_Y13_N8

--operation mode is normal

S1_E_ctrl_alu_subtract = AMPP_FUNCTION(QC2__clk0, S1L283, S1L282, S1L281, S1L280, F1_data_out, S1_W_stall);

--S1L1172 is std_1c20:inst|cpu:the_cpu|Equal53~855 at LC_X31_Y15_N3

--operation mode is normal

S1L1172 = AMPP_FUNCTION(S1_D_iw[3], S1_D_iw[1], S1_D_iw[0], S1_D_iw[2]);

--S1L1173 is std_1c20:inst|cpu:the_cpu|Equal53~856 at LC_X31_Y13_N6

--operation mode is normal

S1L1173 = AMPP_FUNCTION(S1_D_iw[4], S1_D_iw[5], S1L1172);

--S1_D_iw[16] is std_1c20:inst|cpu:the_cpu|D_iw[16] at LC_X28_Y15_N7

--operation mode is normal

S1_D_iw[16] = AMPP_FUNCTION(QC2__clk0, S1L2381, S1L1709, S1L1257, AD1_q_b[16], F1_data_out, S1_W_stall);

--S1L1179 is std_1c20:inst|cpu:the_cpu|Equal77~1059 at LC_X29_Y14_N4

--operation mode is normal

S1L1179 = AMPP_FUNCTION(S1_D_iw[14], S1_D_iw[15]);

--S1L291 is std_1c20:inst|cpu:the_cpu|D_ctrl_dst_data_sel_pc_plus_one~66 at LC_X31_Y14_N3

--operation mode is normal

S1L291 = AMPP_FUNCTION(S1_D_iw[16], S1L1179, S1_D_iw[13], S1L306);

--S1L1180 is std_1c20:inst|cpu:the_cpu|Equal77~1060 at LC_X32_Y14_N8

--operation mode is normal

S1L1180 = AMPP_FUNCTION(S1_D_iw[13], S1L1171, S1_D_iw[12], S1L1168);

--S1L1181 is std_1c20:inst|cpu:the_cpu|Equal77~1061 at LC_X31_Y14_N5

--operation mode is normal

S1L1181 = AMPP_FUNCTION(S1_D_iw[11], S1L1180);

--S1L1174 is std_1c20:inst|cpu:the_cpu|Equal53~857 at LC_X31_Y15_N9

--operation mode is normal

S1L1174 = AMPP_FUNCTION(S1_D_iw[3], S1_D_iw[1], S1_D_iw[0], S1_D_iw[2]);

--S1L290 is std_1c20:inst|cpu:the_cpu|D_ctrl_dst_data_sel_logic_result~51 at LC_X31_Y15_N1

--operation mode is normal

S1L290 = AMPP_FUNCTION(S1_D_iw[4], S1L1174, S1L1172);

--S1L1182 is std_1c20:inst|cpu:the_cpu|Equal77~1062 at LC_X29_Y14_N8

--operation mode is normal

S1L1182 = AMPP_FUNCTION(S1_D_iw[16], S1_D_iw[14]);

--S1L1175 is std_1c20:inst|cpu:the_cpu|Equal53~858 at LC_X30_Y14_N6

--operation mode is normal

S1L1175 = AMPP_FUNCTION(S1_D_iw[0], S1_D_iw[3], S1_D_iw[1], S1_D_iw[2]);

--S1L1176 is std_1c20:inst|cpu:the_cpu|Equal53~859 at LC_X30_Y14_N3

--operation mode is normal

S1L1176 = AMPP_FUNCTION(S1_D_iw[0], S1_D_iw[3], S1_D_iw[1], S1_D_iw[2]);

--S1L289 is std_1c20:inst|cpu:the_cpu|D_ctrl_dst_data_sel_cmp~174 at LC_X30_Y13_N1

--operation mode is normal

S1L289 = AMPP_FUNCTION(S1L1176, S1_D_iw[5], S1_D_iw[4], S1L1175);

--S1L279 is std_1c20:inst|cpu:the_cpu|D_ctrl_alu_subtract~404 at LC_X30_Y13_N5

--operation mode is normal

S1L279 = AMPP_FUNCTION(S1_D_iw[12], S1L1168, S1_D_iw[13]);

--S1L2256 is std_1c20:inst|cpu:the_cpu|M_shift_rot_stall_nxt~21 at LC_X38_Y13_N8

--operation mode is normal

S1L2256 = AMPP_FUNCTION(S1_M_shift_rot_stall, S1_W_stall, S1_E_ctrl_shift_rot, S1L1160);

--S1L129 is std_1c20:inst|cpu:the_cpu|Add9~277 at LC_X38_Y12_N1

--operation mode is arithmetic

S1L129 = AMPP_FUNCTION(S1_M_shift_rot_cnt[1], S1L134, S1L135);

--S1L130 is std_1c20:inst|cpu:the_cpu|Add9~278 at LC_X38_Y12_N1

--operation mode is arithmetic

S1L130 = AMPP_FUNCTION(S1_M_shift_rot_cnt[1], S1L134);

--S1L131 is std_1c20:inst|cpu:the_cpu|Add9~278COUT1_490 at LC_X38_Y12_N1

--operation mode is arithmetic

S1L131 = AMPP_FUNCTION(S1_M_shift_rot_cnt[1], S1L135);

--S1_E_src2_imm[1] is std_1c20:inst|cpu:the_cpu|E_src2_imm[1] at LC_X41_Y18_N7

--operation mode is normal

S1_E_src2_imm[1] = AMPP_FUNCTION(QC2__clk0, S1_D_iw[2], S1L300, S1_D_iw[5], S1_D_iw[7], F1_data_out, S1_W_stall);

--S1L927 is std_1c20:inst|cpu:the_cpu|E_src2[1]~1527 at LC_X40_Y16_N3

--operation mode is normal

S1L927 = AMPP_FUNCTION(S1L931, S1L929, S1L2395);

--S1L132 is std_1c20:inst|cpu:the_cpu|Add9~279 at LC_X38_Y13_N5

--operation mode is normal

S1L132 = AMPP_FUNCTION(S1_M_shift_rot_stall, S1L927, S1L129);

--S1_M_shift_rot_cnt[1] is std_1c20:inst|cpu:the_cpu|M_shift_rot_cnt[1] at LC_X38_Y13_N5

--operation mode is normal

S1_M_shift_rot_cnt[1] = AMPP_FUNCTION(QC2__clk0, S1_M_shift_rot_stall, S1L927, S1L129, F1_data_out);

--S1L134 is std_1c20:inst|cpu:the_cpu|Add9~281 at LC_X38_Y12_N0

--operation mode is arithmetic

S1L134 = AMPP_FUNCTION(S1_M_shift_rot_cnt[0]);

--S1L135 is std_1c20:inst|cpu:the_cpu|Add9~281COUT1_488 at LC_X38_Y12_N0

--operation mode is arithmetic

S1L135 = AMPP_FUNCTION(S1_M_shift_rot_cnt[0]);

--S1L136 is std_1c20:inst|cpu:the_cpu|Add9~282 at LC_X38_Y12_N2

--operation mode is arithmetic

S1L136 = AMPP_FUNCTION(S1_M_shift_rot_cnt[2], S1L130, S1L131);

--S1L137 is std_1c20:inst|cpu:the_cpu|Add9~283 at LC_X38_Y12_N2

--operation mode is arithmetic

S1L137 = AMPP_FUNCTION(S1_M_shift_rot_cnt[2], S1L130);

--S1L138 is std_1c20:inst|cpu:the_cpu|Add9~283COUT1_492 at LC_X38_Y12_N2

--operation mode is arithmetic

S1L138 = AMPP_FUNCTION(S1_M_shift_rot_cnt[2], S1L131);

--S1_E_src2_imm[0] is std_1c20:inst|cpu:the_cpu|E_src2_imm[0] at LC_X37_Y16_N0

--operation mode is normal

S1_E_src2_imm[0] = AMPP_FUNCTION(QC2__clk0, S1_D_iw[5], S1_D_iw[2], S1L300, S1_D_iw[6], F1_data_out, S1_W_stall);

--S1L1190 is std_1c20:inst|cpu:the_cpu|Equal199~132 at LC_X37_Y15_N9

--operation mode is normal

S1L1190 = AMPP_FUNCTION(S1_E_src2_imm[0], S1_E_src2_imm[2]);

--S1L1191 is std_1c20:inst|cpu:the_cpu|Equal199~133 at LC_X37_Y15_N5

--operation mode is normal

S1L1191 = AMPP_FUNCTION(S1_E_ctrl_src2_is_imm, S1L2290, S1L1190, S1L2277);

--S1L1192 is std_1c20:inst|cpu:the_cpu|Equal199~134 at LC_X38_Y13_N1

--operation mode is normal

S1L1192 = AMPP_FUNCTION(S1_M_shift_rot_stall, S1_M_shift_rot_cnt[0], S1L1191, S1L136);

--S1L139 is std_1c20:inst|cpu:the_cpu|Add9~284 at LC_X38_Y12_N4

--operation mode is normal

S1L139 = AMPP_FUNCTION(S1_M_shift_rot_cnt[4], S1L141, S1L142);

--S1L140 is std_1c20:inst|cpu:the_cpu|Add9~286 at LC_X38_Y12_N3

--operation mode is arithmetic

S1L140 = AMPP_FUNCTION(S1_M_shift_rot_cnt[3], S1L137, S1L138);

--S1L141 is std_1c20:inst|cpu:the_cpu|Add9~287 at LC_X38_Y12_N3

--operation mode is arithmetic

S1L141 = AMPP_FUNCTION(S1_M_shift_rot_cnt[3], S1L137);

--S1L142 is std_1c20:inst|cpu:the_cpu|Add9~287COUT1_494 at LC_X38_Y12_N3

--operation mode is arithmetic

S1L142 = AMPP_FUNCTION(S1_M_shift_rot_cnt[3], S1L138);

--S1L1193 is std_1c20:inst|cpu:the_cpu|Equal199~135 at LC_X41_Y16_N4

--operation mode is normal

S1L1193 = AMPP_FUNCTION(S1_E_src2_imm[4], S1_E_src2_imm[3]);

--S1L1194 is std_1c20:inst|cpu:the_cpu|Equal199~136 at LC_X42_Y15_N0

--operation mode is normal

S1L1194 = AMPP_FUNCTION(S1_E_ctrl_src2_is_imm, S1L2296, S1L1193, S1L2303);

--S1L1195 is std_1c20:inst|cpu:the_cpu|Equal199~137 at LC_X38_Y12_N8

--operation mode is normal

S1L1195 = AMPP_FUNCTION(S1_M_shift_rot_stall, S1L139, S1L1194, S1L140);

--S1_M_ipending_reg[3] is std_1c20:inst|cpu:the_cpu|M_ipending_reg[3] at LC_X43_Y19_N4

--operation mode is normal

S1_M_ipending_reg[3] = AMPP_FUNCTION(QC2__clk0, Z1_control_register[0], Z1_timeout_occurred, FD1L25Q, S1L2104Q, F1_data_out);

--S1L481 is std_1c20:inst|cpu:the_cpu|d_readdata_d1[3]~220 at LC_X44_Y24_N6

--operation mode is normal

S1L481 = AMPP_FUNCTION(S1L483Q, S1L484Q, S1L539Q, S1L482Q);

--S1L1388 is std_1c20:inst|cpu:the_cpu|i_readdata_d1[3]~133 at LC_X44_Y19_N8

--operation mode is normal

S1L1388 = AMPP_FUNCTION(S1L1389Q, S1L1367Q, S1L524Q, S1L1390Q);

--T1_cpu_data_master_readdata[3] is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[3] at LC_X43_Y20_N4

--operation mode is normal

T1_cpu_data_master_readdata[3] = S1L481 & (S1L1388 # S1L438Q);

--S1L582 is std_1c20:inst|cpu:the_cpu|d_readdata_d1[19]~174 at LC_X42_Y20_N7

--operation mode is normal

S1L582 = AMPP_FUNCTION(S1L524Q, S1L522Q, S1L584Q, S1L583Q);

--S1_D_iw[9] is std_1c20:inst|cpu:the_cpu|D_iw[9] at LC_X31_Y17_N7

--operation mode is normal

S1_D_iw[9] = AMPP_FUNCTION(QC2__clk0, S1L2381, AD1_q_b[9], S1L1709, S1L1257, F1_data_out, S1_W_stall);

--S1_E_src2_prelim[3] is std_1c20:inst|cpu:the_cpu|E_src2_prelim[3] at LC_X39_Y16_N1

--operation mode is normal

S1_E_src2_prelim[3] = AMPP_FUNCTION(QC2__clk0, S1_W_wr_data[3], S1L668, S1L2401, DD1_q_b[3], F1_data_out, S1L664, S1_W_stall);

--S1_D_br_taken_waddr_partial[1] is std_1c20:inst|cpu:the_cpu|D_br_taken_waddr_partial[1] at LC_X26_Y19_N6

--operation mode is arithmetic

S1_D_br_taken_waddr_partial[1] = AMPP_FUNCTION(QC2__clk0, AD1_q_b[9], S1L1287, F1_data_out, S1_W_stall, S1L243, S1L244);

--S1L246 is std_1c20:inst|cpu:the_cpu|D_br_taken_waddr_partial[1]~56 at LC_X26_Y19_N6

--operation mode is arithmetic

S1L246 = AMPP_FUNCTION(AD1_q_b[9], S1L1287, S1L243);

--S1L247 is std_1c20:inst|cpu:the_cpu|D_br_taken_waddr_partial[1]~56COUT1_462 at LC_X26_Y19_N6

--operation mode is arithmetic

S1L247 = AMPP_FUNCTION(AD1_q_b[9], S1L1287, S1L244);

--S1L343 is std_1c20:inst|cpu:the_cpu|D_issue~5 at LC_X25_Y19_N2

--operation mode is normal

S1L343 = AMPP_FUNCTION(S1L345Q, S1L346Q, S1L344Q, S1L342);

--S1_E_ctrl_flush_pipe_always is std_1c20:inst|cpu:the_cpu|E_ctrl_flush_pipe_always at LC_X30_Y14_N4

--operation mode is normal

S1_E_ctrl_flush_pipe_always = AMPP_FUNCTION(QC2__clk0, S1L1184, S1L298, S1L1181, S1L299, F1_data_out, S1_W_stall);

--XC1L1 is std_1c20:inst|cpu:the_cpu|cpu_test_bench:the_cpu_test_bench|Add0~558 at LC_X35_Y13_N6

--operation mode is normal

XC1L1 = AMPP_FUNCTION(XC1L6, XC1L3, XC1L4);

--YC1_result[32] is std_1c20:inst|cpu:the_cpu|lpm_add_sub:Add8|alt_stratix_add_sub:stratix_adder|result[32] at LC_X36_Y13_N2

--operation mode is normal

YC1_result[32] = AMPP_FUNCTION(GND, YC1L85, YC1L90, YC1L91, S1_E_ctrl_alu_subtract);

--S1L697 is std_1c20:inst|cpu:the_cpu|E_br_actually_taken~243 at LC_X35_Y13_N8

--operation mode is normal

S1L697 = AMPP_FUNCTION(YC1_result[32], S1_E_logic_op[1], S1_E_logic_op[0], XC1L1);

--S1L2043Q is std_1c20:inst|cpu:the_cpu|M_bstatus_reg~14 at LC_X35_Y13_N8

--operation mode is normal

S1L2043Q = AMPP_FUNCTION(QC2__clk0, YC1_result[32], S1_E_logic_op[1], S1_E_logic_op[0], XC1L1, F1_data_out);

--S1_E_ctrl_br_cond is std_1c20:inst|cpu:the_cpu|E_ctrl_br_cond at LC_X30_Y18_N6

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

S1_E_ctrl_br_cond = AMPP_FUNCTION(QC2__clk0, S1L287, F1_data_out, GND, S1_W_stall);

--JD1_probepresent is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_debug:the_cpu_nios2_oci_debug|probepresent at LC_X45_Y17_N2

--operation mode is normal

JD1_probepresent = AMPP_FUNCTION(QC2__clk0, SD1_internal_jdo1[18], JD1_probepresent, SD1_internal_jdo1[19], !C1_CLR_SIGNAL, SD1L190);

--SD1_internal_jdo1[20] is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|internal_jdo1[20] at LC_X47_Y16_N0

--operation mode is normal

SD1_internal_jdo1[20] = AMPP_FUNCTION(A1L8, SD1_sr[20], VCC, SD1L144);

--JD1L1 is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_debug:the_cpu_nios2_oci_debug|A_WE_StdLogicVector~9 at LC_X47_Y16_N7

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

JD1L1 = AMPP_FUNCTION(JD1_jtag_break, SD1_internal_jdo1[20]);

--SD1_internal_jdo1[21] is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|internal_jdo1[21] at LC_X47_Y16_N7

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

SD1_internal_jdo1[21] = AMPP_FUNCTION(A1L8, SD1_sr[21], VCC, GND, SD1L144);

--C1_CLR_SIGNAL is sld_hub:sld_hub_inst|CLR_SIGNAL at LC_X61_Y16_N5

--operation mode is normal

C1_CLR_SIGNAL = AMPP_FUNCTION(A1L5, BF1_Q[0], FF1_state[1], VCC);

--SD1_jxdr is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|jxdr at LC_X46_Y17_N2

--operation mode is normal

SD1_jxdr = AMPP_FUNCTION(QC2__clk0, SD1_dr_update1, SD1_dr_update2, VCC);

--SD1L189 is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|take_action_ocimem_a~54 at LC_X46_Y17_N3

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

SD1L189 = AMPP_FUNCTION(SD1_jxdr, SD1_ir[1], SD1_ir[0]);

--SD1_internal_jdo1[35] is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|internal_jdo1[35] at LC_X46_Y17_N3

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

SD1_internal_jdo1[35] = AMPP_FUNCTION(A1L8, SD1_sr[35], VCC, GND, SD1L144);

--SD1L190 is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|take_action_ocimem_a~55 at LC_X46_Y18_N6

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

SD1L190 = AMPP_FUNCTION(SD1L189);

--SD1_internal_jdo1[34] is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|internal_jdo1[34] at LC_X46_Y18_N6

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

SD1_internal_jdo1[34] = AMPP_FUNCTION(A1L8, SD1_sr[34], VCC, GND, SD1L144);

--S1L1350 is std_1c20:inst|cpu:the_cpu|hbreak_enabled~274 at LC_X34_Y18_N0

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

S1L1350 = AMPP_FUNCTION(S1_M_ctrl_break, S1_M_iw[4], S1_M_iw[3]);

--S1_M_iw[5] is std_1c20:inst|cpu:the_cpu|M_iw[5] at LC_X34_Y18_N0

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

S1_M_iw[5] = AMPP_FUNCTION(QC2__clk0, S1_E_iw[5], F1_data_out, GND, S1_W_stall);

--S1L1351 is std_1c20:inst|cpu:the_cpu|hbreak_enabled~275 at LC_X34_Y18_N1

--operation mode is normal

S1L1351 = AMPP_FUNCTION(S1L2514, S1L1350, S1_M_valid_from_E, RB1L7);

--S1_M_iw[2] is std_1c20:inst|cpu:the_cpu|M_iw[2] at LC_X27_Y15_N3

--operation mode is normal

S1_M_iw[2] = AMPP_FUNCTION(QC2__clk0, S1_E_iw[2], F1_data_out, S1_W_stall);

--S1_M_iw[0] is std_1c20:inst|cpu:the_cpu|M_iw[0] at LC_X27_Y15_N7

--operation mode is normal

S1_M_iw[0] = AMPP_FUNCTION(QC2__clk0, S1_E_iw[0], F1_data_out, S1_W_stall);

--S1_M_iw[16] is std_1c20:inst|cpu:the_cpu|M_iw[16] at LC_X27_Y15_N4

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

S1_M_iw[16] = AMPP_FUNCTION(QC2__clk0, S1_E_iw[16], F1_data_out, GND, S1_W_stall);

--S1L1352 is std_1c20:inst|cpu:the_cpu|hbreak_enabled~276 at LC_X27_Y15_N8

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

S1L1352 = AMPP_FUNCTION(S1_M_iw[0], S1_M_iw[16], S1_M_iw[2]);

--S1_M_iw[1] is std_1c20:inst|cpu:the_cpu|M_iw[1] at LC_X27_Y15_N8

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

S1_M_iw[1] = AMPP_FUNCTION(QC2__clk0, S1_E_iw[1], F1_data_out, GND, S1_W_stall);

--S1_M_iw[15] is std_1c20:inst|cpu:the_cpu|M_iw[15] at LC_X29_Y15_N3

--operation mode is normal

S1_M_iw[15] = AMPP_FUNCTION(QC2__clk0, S1_E_iw[15], F1_data_out, S1_W_stall);

--S1_M_iw[13] is std_1c20:inst|cpu:the_cpu|M_iw[13] at LC_X29_Y15_N5

--operation mode is normal

S1_M_iw[13] = AMPP_FUNCTION(QC2__clk0, S1_E_iw[13], F1_data_out, S1_W_stall);

--S1_M_iw[12] is std_1c20:inst|cpu:the_cpu|M_iw[12] at LC_X29_Y15_N8

--operation mode is normal

S1_M_iw[12] = AMPP_FUNCTION(QC2__clk0, S1_E_iw[12], F1_data_out, S1_W_stall);

--S1L1353 is std_1c20:inst|cpu:the_cpu|hbreak_enabled~277 at LC_X29_Y15_N6

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

S1L1353 = AMPP_FUNCTION(S1_M_iw[13], S1_M_iw[12], S1_M_iw[15]);

--S1_M_iw[14] is std_1c20:inst|cpu:the_cpu|M_iw[14] at LC_X29_Y15_N6

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

S1_M_iw[14] = AMPP_FUNCTION(QC2__clk0, S1_E_iw[14], F1_data_out, GND, S1_W_stall);

--S1L1354 is std_1c20:inst|cpu:the_cpu|hbreak_enabled~278 at LC_X29_Y15_N7

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

S1L1354 = AMPP_FUNCTION(S1L1353, S1L1352);

--S1_M_iw[11] is std_1c20:inst|cpu:the_cpu|M_iw[11] at LC_X29_Y15_N7

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

S1_M_iw[11] = AMPP_FUNCTION(QC2__clk0, S1_E_iw[11], F1_data_out, GND, S1_W_stall);

--S1L1355 is std_1c20:inst|cpu:the_cpu|hbreak_enabled~279 at LC_X34_Y18_N7

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

S1L1355 = AMPP_FUNCTION(S1L2514, S1_M_valid_from_E, RB1L7);

--S1_M_ctrl_break is std_1c20:inst|cpu:the_cpu|M_ctrl_break at LC_X34_Y18_N7

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

S1_M_ctrl_break = AMPP_FUNCTION(QC2__clk0, S1_E_ctrl_break, F1_data_out, GND, S1_W_stall);

--FD1_internal_oci_single_step_mode1 is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_avalon_reg:the_cpu_nios2_avalon_reg|internal_oci_single_step_mode1 at LC_X44_Y19_N7

--operation mode is normal

FD1_internal_oci_single_step_mode1 = AMPP_FUNCTION(QC2__clk0, FD1_internal_oci_single_step_mode1, S1_M_st_data[3], FD1L38, F1_data_out);

--S1_E_ctrl_ld_signed is std_1c20:inst|cpu:the_cpu|E_ctrl_ld_signed at LC_X31_Y15_N6

--operation mode is normal

S1_E_ctrl_ld_signed = AMPP_FUNCTION(QC2__clk0, S1_D_iw[1], S1_D_iw[0], S1_D_iw[2], F1_data_out, S1_W_stall);

--S1L84 is std_1c20:inst|cpu:the_cpu|Add1~250 at LC_X28_Y17_N4

--operation mode is arithmetic

S1L84 = AMPP_FUNCTION(S1_D_pc_plus_one[20], S1_D_iw[21], S1L113, S1L87, S1L88);

--S1L85 is std_1c20:inst|cpu:the_cpu|Add1~251 at LC_X28_Y17_N4

--operation mode is arithmetic

S1L85 = AMPP_FUNCTION(S1_D_pc_plus_one[20], S1_D_iw[21], S1L113, S1L87, S1L88);

--S1L597 is std_1c20:inst|cpu:the_cpu|d_readdata_d1[22]~171 at LC_X41_Y20_N9

--operation mode is normal

S1L597 = AMPP_FUNCTION(S1L598Q, S1L599Q, S1L522Q, S1L524Q);

--S1L563 is std_1c20:inst|cpu:the_cpu|d_readdata_d1[15]~130 at LC_X40_Y21_N7

--operation mode is normal

S1L563 = AMPP_FUNCTION(S1L522Q, S1L1471Q, S1L564Q, S1L524Q);

--S1L237 is std_1c20:inst|cpu:the_cpu|av_sign_bit~0 at LC_X39_Y20_N6

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

S1L237 = AMPP_FUNCTION(S1_M_iw[4], S1L1716Q);

--S1_M_iw[3] is std_1c20:inst|cpu:the_cpu|M_iw[3] at LC_X39_Y20_N6

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

S1_M_iw[3] = AMPP_FUNCTION(QC2__clk0, S1_E_iw[3], F1_data_out, GND, S1_W_stall);

--S1L602 is std_1c20:inst|cpu:the_cpu|d_readdata_d1[23]~168 at LC_X41_Y20_N1

--operation mode is normal

S1L602 = AMPP_FUNCTION(S1L604Q, S1L603Q, S1L522Q, S1L524Q);

--S1L516 is std_1c20:inst|cpu:the_cpu|d_readdata_d1[7]~111 at LC_X42_Y22_N8

--operation mode is normal

S1L516 = AMPP_FUNCTION(S1L518Q, S1L517Q, S1L522Q, S1L524Q);

--S1L238 is std_1c20:inst|cpu:the_cpu|av_sign_bit~9 at LC_X39_Y20_N7

--operation mode is normal

S1L238 = AMPP_FUNCTION(S1L516, S1_M_alu_result[1], S1L602, S1L237);

--S1L642 is std_1c20:inst|cpu:the_cpu|d_readdata_d1[31]~165 at LC_X39_Y20_N8

--operation mode is normal

S1L642 = AMPP_FUNCTION(S1L522Q, S1L643Q, S1L644Q, S1L524Q);

--S1L239 is std_1c20:inst|cpu:the_cpu|av_sign_bit~10 at LC_X39_Y20_N9

--operation mode is normal

S1L239 = AMPP_FUNCTION(S1L237, S1L563, S1L238, S1L642);

--S1L301 is std_1c20:inst|cpu:the_cpu|D_ctrl_hi_imm~101 at LC_X37_Y15_N0

--operation mode is normal

S1L301 = AMPP_FUNCTION(S1_D_iw[2], S1_D_iw[5], S1L300);

--S1L309 is std_1c20:inst|cpu:the_cpu|D_ctrl_unsigned_lo_imm~163 at LC_X30_Y13_N0

--operation mode is normal

S1L309 = AMPP_FUNCTION(S1L1176, S1_D_iw[5], S1_D_iw[4], S1L1175);

--S1L310 is std_1c20:inst|cpu:the_cpu|D_ctrl_unsigned_lo_imm~164 at LC_X31_Y13_N2

--operation mode is normal

S1L310 = AMPP_FUNCTION(S1L1174, S1_D_iw[4], S1_D_iw[5], S1L1172);

--S1L311 is std_1c20:inst|cpu:the_cpu|D_ctrl_unsigned_lo_imm~165 at LC_X32_Y14_N7

--operation mode is normal

S1L311 = AMPP_FUNCTION(S1_D_iw[11], S1L310, S1L309, S1L307);

--S1_E_src2_prelim[22] is std_1c20:inst|cpu:the_cpu|E_src2_prelim[22] at LC_X43_Y14_N3

--operation mode is normal

S1_E_src2_prelim[22] = AMPP_FUNCTION(QC2__clk0, S1_W_wr_data[22], DD1_q_b[22], S1L2458, S1L668, F1_data_out, S1L664, S1_W_stall);

--S1L86 is std_1c20:inst|cpu:the_cpu|Add1~252 at LC_X28_Y17_N3

--operation mode is arithmetic

S1L86 = AMPP_FUNCTION(S1_D_iw[21], S1_D_pc_plus_one[19], S1L113, S1L116, S1L117);

--S1L87 is std_1c20:inst|cpu:the_cpu|Add1~253 at LC_X28_Y17_N3

--operation mode is arithmetic

S1L87 = AMPP_FUNCTION(S1_D_iw[21], S1_D_pc_plus_one[19], S1L116);

--S1L88 is std_1c20:inst|cpu:the_cpu|Add1~253COUT1_837 at LC_X28_Y17_N3

--operation mode is arithmetic

S1L88 = AMPP_FUNCTION(S1_D_iw[21], S1_D_pc_plus_one[19], S1L117);

--S1L592 is std_1c20:inst|cpu:the_cpu|d_readdata_d1[21]~162 at LC_X41_Y21_N8

--operation mode is normal

S1L592 = AMPP_FUNCTION(S1L593Q, S1L594Q, S1L522Q, S1L524Q);

--S1_E_src2_prelim[21] is std_1c20:inst|cpu:the_cpu|E_src2_prelim[21] at LC_X42_Y14_N9

--operation mode is normal

S1_E_src2_prelim[21] = AMPP_FUNCTION(QC2__clk0, S1_W_wr_data[21], S1L668, S1L2455, DD1_q_b[21], F1_data_out, S1L664, S1_W_stall);

--S1L89 is std_1c20:inst|cpu:the_cpu|Add1~254 at LC_X28_Y17_N1

--operation mode is arithmetic

S1L89 = AMPP_FUNCTION(S1_D_iw[21], S1_D_pc_plus_one[17], S1L113, S1L93, S1L94);

--S1L90 is std_1c20:inst|cpu:the_cpu|Add1~255 at LC_X28_Y17_N1

--operation mode is arithmetic

S1L90 = AMPP_FUNCTION(S1_D_iw[21], S1_D_pc_plus_one[17], S1L93);

--S1L91 is std_1c20:inst|cpu:the_cpu|Add1~255COUT1_833 at LC_X28_Y17_N1

--operation mode is arithmetic

S1L91 = AMPP_FUNCTION(S1_D_iw[21], S1_D_pc_plus_one[17], S1L94);

--S1_E_src2_prelim[19] is std_1c20:inst|cpu:the_cpu|E_src2_prelim[19] at LC_X41_Y15_N5

--operation mode is normal

S1_E_src2_prelim[19] = AMPP_FUNCTION(QC2__clk0, DD1_q_b[19], S1L668, S1L2449, S1_W_wr_data[19], F1_data_out, S1L664, S1_W_stall);

--S1L92 is std_1c20:inst|cpu:the_cpu|Add1~256 at LC_X28_Y17_N0

--operation mode is arithmetic

S1L92 = AMPP_FUNCTION(S1_D_iw[21], S1_D_pc_plus_one[16], S1L113);

--S1L93 is std_1c20:inst|cpu:the_cpu|Add1~257 at LC_X28_Y17_N0

--operation mode is arithmetic

S1L93 = AMPP_FUNCTION(S1_D_iw[21], S1_D_pc_plus_one[16]);

--S1L94 is std_1c20:inst|cpu:the_cpu|Add1~257COUT1_831 at LC_X28_Y17_N0

--operation mode is arithmetic

S1L94 = AMPP_FUNCTION(S1_D_iw[21], S1_D_pc_plus_one[16]);

--S1_E_src2_prelim[18] is std_1c20:inst|cpu:the_cpu|E_src2_prelim[18] at LC_X41_Y15_N0

--operation mode is normal

S1_E_src2_prelim[18] = AMPP_FUNCTION(QC2__clk0, DD1_q_b[18], S1L668, S1L2446, S1_W_wr_data[18], F1_data_out, S1L664, S1_W_stall);

--S1L95 is std_1c20:inst|cpu:the_cpu|Add1~258 at LC_X28_Y17_N6

--operation mode is arithmetic

S1L95 = AMPP_FUNCTION(S1_D_iw[21], S1_D_pc_plus_one[22], S1L85, S1L119, S1L120);

--S1L96 is std_1c20:inst|cpu:the_cpu|Add1~259 at LC_X28_Y17_N6

--operation mode is arithmetic

S1L96 = AMPP_FUNCTION(S1_D_iw[21], S1_D_pc_plus_one[22], S1L119);

--S1L97 is std_1c20:inst|cpu:the_cpu|Add1~259COUT1_841 at LC_X28_Y17_N6

--operation mode is arithmetic

S1L97 = AMPP_FUNCTION(S1_D_iw[21], S1_D_pc_plus_one[22], S1L120);

--DD1_q_b[24] is std_1c20:inst|cpu:the_cpu|cpu_register_bank_b_module:cpu_register_bank_b|altsyncram:the_altsyncram|altsyncram_4vd1:auto_generated|q_b[24] at M4K_X49_Y15

--RAM Block Operation Mode: Simple Dual-Port

--Port A Depth: 32, Port A Width: 32, Port B Depth: 32, Port B Width: 32

--Port A Logical Depth: 32, Port A Logical Width: 32, Port B Logical Depth: 32, Port B Logical Width: 32

--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered

DD1_q_b[24] = AMPP_FUNCTION(GND, GND, QC2__clk0, QC2__clk0, !S1_M_wr_dst_reg, S1_W_stall, S1L2464, S1_M_dst_regnum[0], S1_M_dst_regnum[1], S1_M_dst_regnum[2], S1_M_dst_regnum[3], S1_M_dst_regnum[4], AD1_q_b[22], AD1_q_b[23], AD1_q_b[24], AD1_q_b[25], AD1_q_b[26], GND, GND, GND, GND, S1L2437, S1L2434, S1L2431, S1L2428, S1L2467, S1L2425, S1L2422, S1L2419, S1L2416, S1L2398, S1L2401, S1L2458, S1L2455, S1L2449, S1L2446, S1L2440, S1L2443, S1L2452, S1L2461, S1L2537, S1L2410, S1L2404, S1L2407, S1L2395, S1L2517, S1L2495, S1L2470, S1L2482, S1L2479, S1L2476, S1L2473);

--DD1_q_b[27] is std_1c20:inst|cpu:the_cpu|cpu_register_bank_b_module:cpu_register_bank_b|altsyncram:the_altsyncram|altsyncram_4vd1:auto_generated|q_b[27] at M4K_X49_Y15

DD1_q_b[27] = AMPP_FUNCTION(GND, GND, QC2__clk0, QC2__clk0, !S1_M_wr_dst_reg, S1_W_stall, S1L2464, S1_M_dst_regnum[0], S1_M_dst_regnum[1], S1_M_dst_regnum[2], S1_M_dst_regnum[3], S1_M_dst_regnum[4], AD1_q_b[22], AD1_q_b[23], AD1_q_b[24], AD1_q_b[25], AD1_q_b[26], GND, GND, GND, GND, S1L2437, S1L2434, S1L2431, S1L2428, S1L2467, S1L2425, S1L2422, S1L2419, S1L2416, S1L2398, S1L2401, S1L2458, S1L2455, S1L2449, S1L2446, S1L2440, S1L2443, S1L2452, S1L2461, S1L2537, S1L2410, S1L2404, S1L2407, S1L2395, S1L2517, S1L2495, S1L2470, S1L2482, S1L2479, S1L2476, S1L2473);

--DD1_q_b[28] is std_1c20:inst|cpu:the_cpu|cpu_register_bank_b_module:cpu_register_bank_b|altsyncram:the_altsyncram|altsyncram_4vd1:auto_generated|q_b[28] at M4K_X49_Y15

DD1_q_b[28] = AMPP_FUNCTION(GND, GND, QC2__clk0, QC2__clk0, !S1_M_wr_dst_reg, S1_W_stall, S1L2464, S1_M_dst_regnum[0], S1_M_dst_regnum[1], S1_M_dst_regnum[2], S1_M_dst_regnum[3], S1_M_dst_regnum[4], AD1_q_b[22], AD1_q_b[23], AD1_q_b[24], AD1_q_b[25], AD1_q_b[26], GND, GND, GND, GND, S1L2437, S1L2434, S1L2431, S1L2428, S1L2467, S1L2425, S1L2422, S1L2419, S1L2416, S1L2398, S1L2401, S1L2458, S1L2455, S1L2449, S1L2446, S1L2440, S1L2443, S1L2452, S1L2461, S1L2537, S1L2410, S1L2404, S1L2407, S1L2395, S1L2517, S1L2495, S1L2470, S1L2482, S1L2479, S1L2476, S1L2473);

--DD1_q_b[29] is std_1c20:inst|cpu:the_cpu|cpu_register_bank_b_module:cpu_register_bank_b|altsyncram:the_altsyncram|altsyncram_4vd1:auto_generated|q_b[29] at M4K_X49_Y15

DD1_q_b[29] = AMPP_FUNCTION(GND, GND, QC2__clk0, QC2__clk0, !S1_M_wr_dst_reg, S1_W_stall, S1L2464, S1_M_dst_regnum[0], S1_M_dst_regnum[1], S1_M_dst_regnum[2], S1_M_dst_regnum[3], S1_M_dst_regnum[4], AD1_q_b[22], AD1_q_b[23], AD1_q_b[24], AD1_q_b[25], AD1_q_b[26], GND, GND, GND, GND, S1L2437, S1L2434, S1L2431, S1L2428, S1L2467, S1L2425, S1L2422, S1L2419, S1L2416, S1L2398, S1L2401, S1L2458, S1L2455, S1L2449, S1L2446, S1L2440, S1L2443, S1L2452, S1L2461, S1L2537, S1L2410, S1L2404, S1L2407, S1L2395, S1L2517, S1L2495, S1L2470, S1L2482, S1L2479, S1L2476, S1L2473);

--DD1_q_b[30] is std_1c20:inst|cpu:the_cpu|cpu_register_bank_b_module:cpu_register_bank_b|altsyncram:the_altsyncram|altsyncram_4vd1:auto_generated|q_b[30] at M4K_X49_Y15

DD1_q_b[30] = AMPP_FUNCTION(GND, GND, QC2__clk0, QC2__clk0, !S1_M_wr_dst_reg, S1_W_stall, S1L2464, S1_M_dst_regnum[0], S1_M_dst_regnum[1], S1_M_dst_regnum[2], S1_M_dst_regnum[3], S1_M_dst_regnum[4], AD1_q_b[22], AD1_q_b[23], AD1_q_b[24], AD1_q_b[25], AD1_q_b[26], GND, GND, GND, GND, S1L2437, S1L2434, S1L2431, S1L2428, S1L2467, S1L2425, S1L2422, S1L2419, S1L2416, S1L2398, S1L2401, S1L2458, S1L2455, S1L2449, S1L2446, S1L2440, S1L2443, S1L2452, S1L2461, S1L2537, S1L2410, S1L2404, S1L2407, S1L2395, S1L2517, S1L2495, S1L2470, S1L2482, S1L2479, S1L2476, S1L2473);

--DD1_q_b[26] is std_1c20:inst|cpu:the_cpu|cpu_register_bank_b_module:cpu_register_bank_b|altsyncram:the_altsyncram|altsyncram_4vd1:auto_generated|q_b[26] at M4K_X49_Y15

DD1_q_b[26] = AMPP_FUNCTION(GND, GND, QC2__clk0, QC2__clk0, !S1_M_wr_dst_reg, S1_W_stall, S1L2464, S1_M_dst_regnum[0], S1_M_dst_regnum[1], S1_M_dst_regnum[2], S1_M_dst_regnum[3], S1_M_dst_regnum[4], AD1_q_b[22], AD1_q_b[23], AD1_q_b[24], AD1_q_b[25], AD1_q_b[26], GND, GND, GND, GND, S1L2437, S1L2434, S1L2431, S1L2428, S1L2467, S1L2425, S1L2422, S1L2419, S1L2416, S1L2398, S1L2401, S1L2458, S1L2455, S1L2449, S1L2446, S1L2440, S1L2443, S1L2452, S1L2461, S1L2537, S1L2410, S1L2404, S1L2407, S1L2395, S1L2517, S1L2495, S1L2470, S1L2482, S1L2479, S1L2476, S1L2473);

--DD1_q_b[31] is std_1c20:inst|cpu:the_cpu|cpu_register_bank_b_module:cpu_register_bank_b|altsyncram:the_altsyncram|altsyncram_4vd1:auto_generated|q_b[31] at M4K_X49_Y15

DD1_q_b[31] = AMPP_FUNCTION(GND, GND, QC2__clk0, QC2__clk0, !S1_M_wr_dst_reg, S1_W_stall, S1L2464, S1_M_dst_regnum[0], S1_M_dst_regnum[1], S1_M_dst_regnum[2], S1_M_dst_regnum[3], S1_M_dst_regnum[4], AD1_q_b[22], AD1_q_b[23], AD1_q_b[24], AD1_q_b[25], AD1_q_b[26], GND, GND, GND, GND, S1L2437, S1L2434, S1L2431, S1L2428, S1L2467, S1L2425, S1L2422, S1L2419, S1L2416, S1L2398, S1L2401, S1L2458, S1L2455, S1L2449, S1L2446, S1L2440, S1L2443, S1L2452, S1L2461, S1L2537, S1L2410, S1L2404, S1L2407, S1L2395, S1L2517, S1L2495, S1L2470, S1L2482, S1L2479, S1L2476, S1L2473);

--DD1_q_b[0] is std_1c20:inst|cpu:the_cpu|cpu_register_bank_b_module:cpu_register_bank_b|altsyncram:the_altsyncram|altsyncram_4vd1:auto_generated|q_b[0] at M4K_X49_Y15

DD1_q_b[0] = AMPP_FUNCTION(GND, GND, QC2__clk0, QC2__clk0, !S1_M_wr_dst_reg, S1_W_stall, S1L2464, S1_M_dst_regnum[0], S1_M_dst_regnum[1], S1_M_dst_regnum[2], S1_M_dst_regnum[3], S1_M_dst_regnum[4], AD1_q_b[22], AD1_q_b[23], AD1_q_b[24], AD1_q_b[25], AD1_q_b[26], GND, GND, GND, GND, S1L2437, S1L2434, S1L2431, S1L2428, S1L2467, S1L2425, S1L2422, S1L2419, S1L2416, S1L2398, S1L2401, S1L2458, S1L2455, S1L2449, S1L2446, S1L2440, S1L2443, S1L2452, S1L2461, S1L2537, S1L2410, S1L2404, S1L2407, S1L2395, S1L2517, S1L2495, S1L2470, S1L2482, S1L2479, S1L2476, S1L2473);

--DD1_q_b[1] is std_1c20:inst|cpu:the_cpu|cpu_register_bank_b_module:cpu_register_bank_b|altsyncram:the_altsyncram|altsyncram_4vd1:auto_generated|q_b[1] at M4K_X49_Y15

DD1_q_b[1] = AMPP_FUNCTION(GND, GND, QC2__clk0, QC2__clk0, !S1_M_wr_dst_reg, S1_W_stall, S1L2464, S1_M_dst_regnum[0], S1_M_dst_regnum[1], S1_M_dst_regnum[2], S1_M_dst_regnum[3], S1_M_dst_regnum[4], AD1_q_b[22], AD1_q_b[23], AD1_q_b[24], AD1_q_b[25], AD1_q_b[26], GND, GND, GND, GND, S1L2437, S1L2434, S1L2431, S1L2428, S1L2467, S1L2425, S1L2422, S1L2419, S1L2416, S1L2398, S1L2401, S1L2458, S1L2455, S1L2449, S1L2446, S1L2440, S1L2443, S1L2452, S1L2461, S1L2537, S1L2410, S1L2404, S1L2407, S1L2395, S1L2517, S1L2495, S1L2470, S1L2482, S1L2479, S1L2476, S1L2473);

--DD1_q_b[5] is std_1c20:inst|cpu:the_cpu|cpu_register_bank_b_module:cpu_register_bank_b|altsyncram:the_altsyncram|altsyncram_4vd1:auto_generated|q_b[5] at M4K_X49_Y15

DD1_q_b[5] = AMPP_FUNCTION(GND, GND, QC2__clk0, QC2__clk0, !S1_M_wr_dst_reg, S1_W_stall, S1L2464, S1_M_dst_regnum[0], S1_M_dst_regnum[1], S1_M_dst_regnum[2], S1_M_dst_regnum[3], S1_M_dst_regnum[4], AD1_q_b[22], AD1_q_b[23], AD1_q_b[24], AD1_q_b[25], AD1_q_b[26], GND, GND, GND, GND, S1L2437, S1L2434, S1L2431, S1L2428, S1L2467, S1L2425, S1L2422, S1L2419, S1L2416, S1L2398, S1L2401, S1L2458, S1L2455, S1L2449, S1L2446, S1L2440, S1L2443, S1L2452, S1L2461, S1L2537, S1L2410, S1L2404, S1L2407, S1L2395, S1L2517, S1L2495, S1L2470, S1L2482, S1L2479, S1L2476, S1L2473);

--DD1_q_b[4] is std_1c20:inst|cpu:the_cpu|cpu_register_bank_b_module:cpu_register_bank_b|altsyncram:the_altsyncram|altsyncram_4vd1:auto_generated|q_b[4] at M4K_X49_Y15

DD1_q_b[4] = AMPP_FUNCTION(GND, GND, QC2__clk0, QC2__clk0, !S1_M_wr_dst_reg, S1_W_stall, S1L2464, S1_M_dst_regnum[0], S1_M_dst_regnum[1], S1_M_dst_regnum[2], S1_M_dst_regnum[3], S1_M_dst_regnum[4], AD1_q_b[22], AD1_q_b[23], AD1_q_b[24], AD1_q_b[25], AD1_q_b[26], GND, GND, GND, GND, S1L2437, S1L2434, S1L2431, S1L2428, S1L2467, S1L2425, S1L2422, S1L2419, S1L2416, S1L2398, S1L2401, S1L2458, S1L2455, S1L2449, S1L2446, S1L2440, S1L2443, S1L2452, S1L2461, S1L2537, S1L2410, S1L2404, S1L2407, S1L2395, S1L2517, S1L2495, S1L2470, S1L2482, S1L2479, S1L2476, S1L2473);

--DD1_q_b[6] is std_1c20:inst|cpu:the_cpu|cpu_register_bank_b_module:cpu_register_bank_b|altsyncram:the_altsyncram|altsyncram_4vd1:auto_generated|q_b[6] at M4K_X49_Y15

DD1_q_b[6] = AMPP_FUNCTION(GND, GND, QC2__clk0, QC2__clk0, !S1_M_wr_dst_reg, S1_W_stall, S1L2464, S1_M_dst_regnum[0], S1_M_dst_regnum[1], S1_M_dst_regnum[2], S1_M_dst_regnum[3], S1_M_dst_regnum[4], AD1_q_b[22], AD1_q_b[23], AD1_q_b[24], AD1_q_b[25], AD1_q_b[26], GND, GND, GND, GND, S1L2437, S1L2434, S1L2431, S1L2428, S1L2467, S1L2425, S1L2422, S1L2419, S1L2416, S1L2398, S1L2401, S1L2458, S1L2455, S1L2449, S1L2446, S1L2440, S1L2443, S1L2452, S1L2461, S1L2537, S1L2410, S1L2404, S1L2407, S1L2395, S1L2517, S1L2495, S1L2470, S1L2482, S1L2479, S1L2476, S1L2473);

--DD1_q_b[7] is std_1c20:inst|cpu:the_cpu|cpu_register_bank_b_module:cpu_register_bank_b|altsyncram:the_altsyncram|altsyncram_4vd1:auto_generated|q_b[7] at M4K_X49_Y15

DD1_q_b[7] = AMPP_FUNCTION(GND, GND, QC2__clk0, QC2__clk0, !S1_M_wr_dst_reg, S1_W_stall, S1L2464, S1_M_dst_regnum[0], S1_M_dst_regnum[1], S1_M_dst_regnum[2], S1_M_dst_regnum[3], S1_M_dst_regnum[4], AD1_q_b[22], AD1_q_b[23], AD1_q_b[24], AD1_q_b[25], AD1_q_b[26], GND, GND, GND, GND, S1L2437, S1L2434, S1L2431, S1L2428, S1L2467, S1L2425, S1L2422, S1L2419, S1L2416, S1L2398, S1L2401, S1L2458, S1L2455, S1L2449, S1L2446, S1L2440, S1L2443, S1L2452, S1L2461, S1L2537, S1L2410, S1L2404, S1L2407, S1L2395, S1L2517, S1L2495, S1L2470, S1L2482, S1L2479, S1L2476, S1L2473);

--DD1_q_b[23] is std_1c20:inst|cpu:the_cpu|cpu_register_bank_b_module:cpu_register_bank_b|altsyncram:the_altsyncram|altsyncram_4vd1:auto_generated|q_b[23] at M4K_X49_Y15

DD1_q_b[23] = AMPP_FUNCTION(GND, GND, QC2__clk0, QC2__clk0, !S1_M_wr_dst_reg, S1_W_stall, S1L2464, S1_M_dst_regnum[0], S1_M_dst_regnum[1], S1_M_dst_regnum[2], S1_M_dst_regnum[3], S1_M_dst_regnum[4], AD1_q_b[22], AD1_q_b[23], AD1_q_b[24], AD1_q_b[25], AD1_q_b[26], GND, GND, GND, GND, S1L2437, S1L2434, S1L2431, S1L2428, S1L2467, S1L2425, S1L2422, S1L2419, S1L2416, S1L2398, S1L2401, S1L2458, S1L2455, S1L2449, S1L2446, S1L2440, S1L2443, S1L2452, S1L2461, S1L2537, S1L2410, S1L2404, S1L2407, S1L2395, S1L2517, S1L2495, S1L2470, S1L2482, S1L2479, S1L2476, S1L2473);

--DD1_q_b[20] is std_1c20:inst|cpu:the_cpu|cpu_register_bank_b_module:cpu_register_bank_b|altsyncram:the_altsyncram|altsyncram_4vd1:auto_generated|q_b[20] at M4K_X49_Y15

DD1_q_b[20] = AMPP_FUNCTION(GND, GND, QC2__clk0, QC2__clk0, !S1_M_wr_dst_reg, S1_W_stall, S1L2464, S1_M_dst_regnum[0], S1_M_dst_regnum[1], S1_M_dst_regnum[2], S1_M_dst_regnum[3], S1_M_dst_regnum[4], AD1_q_b[22], AD1_q_b[23], AD1_q_b[24], AD1_q_b[25], AD1_q_b[26], GND, GND, GND, GND, S1L2437, S1L2434, S1L2431, S1L2428, S1L2467, S1L2425, S1L2422, S1L2419, S1L2416, S1L2398, S1L2401, S1L2458, S1L2455, S1L2449, S1L2446, S1L2440, S1L2443, S1L2452, S1L2461, S1L2537, S1L2410, S1L2404, S1L2407, S1L2395, S1L2517, S1L2495, S1L2470, S1L2482, S1L2479, S1L2476, S1L2473);

--DD1_q_b[17] is std_1c20:inst|cpu:the_cpu|cpu_register_bank_b_module:cpu_register_bank_b|altsyncram:the_altsyncram|altsyncram_4vd1:auto_generated|q_b[17] at M4K_X49_Y15

DD1_q_b[17] = AMPP_FUNCTION(GND, GND, QC2__clk0, QC2__clk0, !S1_M_wr_dst_reg, S1_W_stall, S1L2464, S1_M_dst_regnum[0], S1_M_dst_regnum[1], S1_M_dst_regnum[2], S1_M_dst_regnum[3], S1_M_dst_regnum[4], AD1_q_b[22], AD1_q_b[23], AD1_q_b[24], AD1_q_b[25], AD1_q_b[26], GND, GND, GND, GND, S1L2437, S1L2434, S1L2431, S1L2428, S1L2467, S1L2425, S1L2422, S1L2419, S1L2416, S1L2398, S1L2401, S1L2458, S1L2455, S1L2449, S1L2446, S1L2440, S1L2443, S1L2452, S1L2461, S1L2537, S1L2410, S1L2404, S1L2407, S1L2395, S1L2517, S1L2495, S1L2470, S1L2482, S1L2479, S1L2476, S1L2473);

--DD1_q_b[16] is std_1c20:inst|cpu:the_cpu|cpu_register_bank_b_module:cpu_register_bank_b|altsyncram:the_altsyncram|altsyncram_4vd1:auto_generated|q_b[16] at M4K_X49_Y15

DD1_q_b[16] = AMPP_FUNCTION(GND, GND, QC2__clk0, QC2__clk0, !S1_M_wr_dst_reg, S1_W_stall, S1L2464, S1_M_dst_regnum[0], S1_M_dst_regnum[1], S1_M_dst_regnum[2], S1_M_dst_regnum[3], S1_M_dst_regnum[4], AD1_q_b[22], AD1_q_b[23], AD1_q_b[24], AD1_q_b[25], AD1_q_b[26], GND, GND, GND, GND, S1L2437, S1L2434, S1L2431, S1L2428, S1L2467, S1L2425, S1L2422, S1L2419, S1L2416, S1L2398, S1L2401, S1L2458, S1L2455, S1L2449, S1L2446, S1L2440, S1L2443, S1L2452, S1L2461, S1L2537, S1L2410, S1L2404, S1L2407, S1L2395, S1L2517, S1L2495, S1L2470, S1L2482, S1L2479, S1L2476, S1L2473);

--DD1_q_b[18] is std_1c20:inst|cpu:the_cpu|cpu_register_bank_b_module:cpu_register_bank_b|altsyncram:the_altsyncram|altsyncram_4vd1:auto_generated|q_b[18] at M4K_X49_Y15

DD1_q_b[18] = AMPP_FUNCTION(GND, GND, QC2__clk0, QC2__clk0, !S1_M_wr_dst_reg, S1_W_stall, S1L2464, S1_M_dst_regnum[0], S1_M_dst_regnum[1], S1_M_dst_regnum[2], S1_M_dst_regnum[3], S1_M_dst_regnum[4], AD1_q_b[22], AD1_q_b[23], AD1_q_b[24], AD1_q_b[25], AD1_q_b[26], GND, GND, GND, GND, S1L2437, S1L2434, S1L2431, S1L2428, S1L2467, S1L2425, S1L2422, S1L2419, S1L2416, S1L2398, S1L2401, S1L2458, S1L2455, S1L2449, S1L2446, S1L2440, S1L2443, S1L2452, S1L2461, S1L2537, S1L2410, S1L2404, S1L2407, S1L2395, S1L2517, S1L2495, S1L2470, S1L2482, S1L2479, S1L2476, S1L2473);

--DD1_q_b[19] is std_1c20:inst|cpu:the_cpu|cpu_register_bank_b_module:cpu_register_bank_b|altsyncram:the_altsyncram|altsyncram_4vd1:auto_generated|q_b[19] at M4K_X49_Y15

DD1_q_b[19] = AMPP_FUNCTION(GND, GND, QC2__clk0, QC2__clk0, !S1_M_wr_dst_reg, S1_W_stall, S1L2464, S1_M_dst_regnum[0], S1_M_dst_regnum[1], S1_M_dst_regnum[2], S1_M_dst_regnum[3], S1_M_dst_regnum[4], AD1_q_b[22], AD1_q_b[23], AD1_q_b[24], AD1_q_b[25], AD1_q_b[26], GND, GND, GND, GND, S1L2437, S1L2434, S1L2431, S1L2428, S1L2467, S1L2425, S1L2422, S1L2419, S1L2416, S1L2398, S1L2401, S1L2458, S1L2455, S1L2449, S1L2446, S1L2440, S1L2443, S1L2452, S1L2461, S1L2537, S1L2410, S1L2404, S1L2407, S1L2395, S1L2517, S1L2495, S1L2470, S1L2482, S1L2479, S1L2476, S1L2473);

--DD1_q_b[21] is std_1c20:inst|cpu:the_cpu|cpu_register_bank_b_module:cpu_register_bank_b|altsyncram:the_altsyncram|altsyncram_4vd1:auto_generated|q_b[21] at M4K_X49_Y15

DD1_q_b[21] = AMPP_FUNCTION(GND, GND, QC2__clk0, QC2__clk0, !S1_M_wr_dst_reg, S1_W_stall, S1L2464, S1_M_dst_regnum[0], S1_M_dst_regnum[1], S1_M_dst_regnum[2], S1_M_dst_regnum[3], S1_M_dst_regnum[4], AD1_q_b[22], AD1_q_b[23], AD1_q_b[24], AD1_q_b[25], AD1_q_b[26], GND, GND, GND, GND, S1L2437, S1L2434, S1L2431, S1L2428, S1L2467, S1L2425, S1L2422, S1L2419, S1L2416, S1L2398, S1L2401, S1L2458, S1L2455, S1L2449, S1L2446, S1L2440, S1L2443, S1L2452, S1L2461, S1L2537, S1L2410, S1L2404, S1L2407, S1L2395, S1L2517, S1L2495, S1L2470, S1L2482, S1L2479, S1L2476, S1L2473);

--DD1_q_b[22] is std_1c20:inst|cpu:the_cpu|cpu_register_bank_b_module:cpu_register_bank_b|altsyncram:the_altsyncram|altsyncram_4vd1:auto_generated|q_b[22] at M4K_X49_Y15

DD1_q_b[22] = AMPP_FUNCTION(GND, GND, QC2__clk0, QC2__clk0, !S1_M_wr_dst_reg, S1_W_stall, S1L2464, S1_M_dst_regnum[0], S1_M_dst_regnum[1], S1_M_dst_regnum[2], S1_M_dst_regnum[3], S1_M_dst_regnum[4], AD1_q_b[22], AD1_q_b[23], AD1_q_b[24], AD1_q_b[25], AD1_q_b[26], GND, GND, GND, GND, S1L2437, S1L2434, S1L2431, S1L2428, S1L2467, S1L2425, S1L2422, S1L2419, S1L2416, S1L2398, S1L2401, S1L2458, S1L2455, S1L2449, S1L2446, S1L2440, S1L2443, S1L2452, S1L2461, S1L2537, S1L2410, S1L2404, S1L2407, S1L2395, S1L2517, S1L2495, S1L2470, S1L2482, S1L2479, S1L2476, S1L2473);

--DD1_q_b[3] is std_1c20:inst|cpu:the_cpu|cpu_register_bank_b_module:cpu_register_bank_b|altsyncram:the_altsyncram|altsyncram_4vd1:auto_generated|q_b[3] at M4K_X49_Y15

DD1_q_b[3] = AMPP_FUNCTION(GND, GND, QC2__clk0, QC2__clk0, !S1_M_wr_dst_reg, S1_W_stall, S1L2464, S1_M_dst_regnum[0], S1_M_dst_regnum[1], S1_M_dst_regnum[2], S1_M_dst_regnum[3], S1_M_dst_regnum[4], AD1_q_b[22], AD1_q_b[23], AD1_q_b[24], AD1_q_b[25], AD1_q_b[26], GND, GND, GND, GND, S1L2437, S1L2434, S1L2431, S1L2428, S1L2467, S1L2425, S1L2422, S1L2419, S1L2416, S1L2398, S1L2401, S1L2458, S1L2455, S1L2449, S1L2446, S1L2440, S1L2443, S1L2452, S1L2461, S1L2537, S1L2410, S1L2404, S1L2407, S1L2395, S1L2517, S1L2495, S1L2470, S1L2482, S1L2479, S1L2476, S1L2473);

--DD1_q_b[2] is std_1c20:inst|cpu:the_cpu|cpu_register_bank_b_module:cpu_register_bank_b|altsyncram:the_altsyncram|altsyncram_4vd1:auto_generated|q_b[2] at M4K_X49_Y15

DD1_q_b[2] = AMPP_FUNCTION(GND, GND, QC2__clk0, QC2__clk0, !S1_M_wr_dst_reg, S1_W_stall, S1L2464, S1_M_dst_regnum[0], S1_M_dst_regnum[1], S1_M_dst_regnum[2], S1_M_dst_regnum[3], S1_M_dst_regnum[4], AD1_q_b[22], AD1_q_b[23], AD1_q_b[24], AD1_q_b[25], AD1_q_b[26], GND, GND, GND, GND, S1L2437, S1L2434, S1L2431, S1L2428, S1L2467, S1L2425, S1L2422, S1L2419, S1L2416, S1L2398, S1L2401, S1L2458, S1L2455, S1L2449, S1L2446, S1L2440, S1L2443, S1L2452, S1L2461, S1L2537, S1L2410, S1L2404, S1L2407, S1L2395, S1L2517, S1L2495, S1L2470, S1L2482, S1L2479, S1L2476, S1L2473);

--DD1_q_b[8] is std_1c20:inst|cpu:the_cpu|cpu_register_bank_b_module:cpu_register_bank_b|altsyncram:the_altsyncram|altsyncram_4vd1:auto_generated|q_b[8] at M4K_X49_Y15

DD1_q_b[8] = AMPP_FUNCTION(GND, GND, QC2__clk0, QC2__clk0, !S1_M_wr_dst_reg, S1_W_stall, S1L2464, S1_M_dst_regnum[0], S1_M_dst_regnum[1], S1_M_dst_regnum[2], S1_M_dst_regnum[3], S1_M_dst_regnum[4], AD1_q_b[22], AD1_q_b[23], AD1_q_b[24], AD1_q_b[25], AD1_q_b[26], GND, GND, GND, GND, S1L2437, S1L2434, S1L2431, S1L2428, S1L2467, S1L2425, S1L2422, S1L2419, S1L2416, S1L2398, S1L2401, S1L2458, S1L2455, S1L2449, S1L2446, S1L2440, S1L2443, S1L2452, S1L2461, S1L2537, S1L2410, S1L2404, S1L2407, S1L2395, S1L2517, S1L2495, S1L2470, S1L2482, S1L2479, S1L2476, S1L2473);

--DD1_q_b[9] is std_1c20:inst|cpu:the_cpu|cpu_register_bank_b_module:cpu_register_bank_b|altsyncram:the_altsyncram|altsyncram_4vd1:auto_generated|q_b[9] at M4K_X49_Y15

DD1_q_b[9] = AMPP_FUNCTION(GND, GND, QC2__clk0, QC2__clk0, !S1_M_wr_dst_reg, S1_W_stall, S1L2464, S1_M_dst_regnum[0], S1_M_dst_regnum[1], S1_M_dst_regnum[2], S1_M_dst_regnum[3], S1_M_dst_regnum[4], AD1_q_b[22], AD1_q_b[23], AD1_q_b[24], AD1_q_b[25], AD1_q_b[26], GND, GND, GND, GND, S1L2437, S1L2434, S1L2431, S1L2428, S1L2467, S1L2425, S1L2422, S1L2419, S1L2416, S1L2398, S1L2401, S1L2458, S1L2455, S1L2449, S1L2446, S1L2440, S1L2443, S1L2452, S1L2461, S1L2537, S1L2410, S1L2404, S1L2407, S1L2395, S1L2517, S1L2495, S1L2470, S1L2482, S1L2479, S1L2476, S1L2473);

--DD1_q_b[10] is std_1c20:inst|cpu:the_cpu|cpu_register_bank_b_module:cpu_register_bank_b|altsyncram:the_altsyncram|altsyncram_4vd1:auto_generated|q_b[10] at M4K_X49_Y15

DD1_q_b[10] = AMPP_FUNCTION(GND, GND, QC2__clk0, QC2__clk0, !S1_M_wr_dst_reg, S1_W_stall, S1L2464, S1_M_dst_regnum[0], S1_M_dst_regnum[1], S1_M_dst_regnum[2], S1_M_dst_regnum[3], S1_M_dst_regnum[4], AD1_q_b[22], AD1_q_b[23], AD1_q_b[24], AD1_q_b[25], AD1_q_b[26], GND, GND, GND, GND, S1L2437, S1L2434, S1L2431, S1L2428, S1L2467, S1L2425, S1L2422, S1L2419, S1L2416, S1L2398, S1L2401, S1L2458, S1L2455, S1L2449, S1L2446, S1L2440, S1L2443, S1L2452, S1L2461, S1L2537, S1L2410, S1L2404, S1L2407, S1L2395, S1L2517, S1L2495, S1L2470, S1L2482, S1L2479, S1L2476, S1L2473);

--DD1_q_b[11] is std_1c20:inst|cpu:the_cpu|cpu_register_bank_b_module:cpu_register_bank_b|altsyncram:the_altsyncram|altsyncram_4vd1:auto_generated|q_b[11] at M4K_X49_Y15

DD1_q_b[11] = AMPP_FUNCTION(GND, GND, QC2__clk0, QC2__clk0, !S1_M_wr_dst_reg, S1_W_stall, S1L2464, S1_M_dst_regnum[0], S1_M_dst_regnum[1], S1_M_dst_regnum[2], S1_M_dst_regnum[3], S1_M_dst_regnum[4], AD1_q_b[22], AD1_q_b[23], AD1_q_b[24], AD1_q_b[25], AD1_q_b[26], GND, GND, GND, GND, S1L2437, S1L2434, S1L2431, S1L2428, S1L2467, S1L2425, S1L2422, S1L2419, S1L2416, S1L2398, S1L2401, S1L2458, S1L2455, S1L2449, S1L2446, S1L2440, S1L2443, S1L2452, S1L2461, S1L2537, S1L2410, S1L2404, S1L2407, S1L2395, S1L2517, S1L2495, S1L2470, S1L2482, S1L2479, S1L2476, S1L2473);

--DD1_q_b[25] is std_1c20:inst|cpu:the_cpu|cpu_register_bank_b_module:cpu_register_bank_b|altsyncram:the_altsyncram|altsyncram_4vd1:auto_generated|q_b[25] at M4K_X49_Y15

DD1_q_b[25] = AMPP_FUNCTION(GND, GND, QC2__clk0, QC2__clk0, !S1_M_wr_dst_reg, S1_W_stall, S1L2464, S1_M_dst_regnum[0], S1_M_dst_regnum[1], S1_M_dst_regnum[2], S1_M_dst_regnum[3], S1_M_dst_regnum[4], AD1_q_b[22], AD1_q_b[23], AD1_q_b[24], AD1_q_b[25], AD1_q_b[26], GND, GND, GND, GND, S1L2437, S1L2434, S1L2431, S1L2428, S1L2467, S1L2425, S1L2422, S1L2419, S1L2416, S1L2398, S1L2401, S1L2458, S1L2455, S1L2449, S1L2446, S1L2440, S1L2443, S1L2452, S1L2461, S1L2537, S1L2410, S1L2404, S1L2407, S1L2395, S1L2517, S1L2495, S1L2470, S1L2482, S1L2479, S1L2476, S1L2473);

--DD1_q_b[12] is std_1c20:inst|cpu:the_cpu|cpu_register_bank_b_module:cpu_register_bank_b|altsyncram:the_altsyncram|altsyncram_4vd1:auto_generated|q_b[12] at M4K_X49_Y15

DD1_q_b[12] = AMPP_FUNCTION(GND, GND, QC2__clk0, QC2__clk0, !S1_M_wr_dst_reg, S1_W_stall, S1L2464, S1_M_dst_regnum[0], S1_M_dst_regnum[1], S1_M_dst_regnum[2], S1_M_dst_regnum[3], S1_M_dst_regnum[4], AD1_q_b[22], AD1_q_b[23], AD1_q_b[24], AD1_q_b[25], AD1_q_b[26], GND, GND, GND, GND, S1L2437, S1L2434, S1L2431, S1L2428, S1L2467, S1L2425, S1L2422, S1L2419, S1L2416, S1L2398, S1L2401, S1L2458, S1L2455, S1L2449, S1L2446, S1L2440, S1L2443, S1L2452, S1L2461, S1L2537, S1L2410, S1L2404, S1L2407, S1L2395, S1L2517, S1L2495, S1L2470, S1L2482, S1L2479, S1L2476, S1L2473);

--DD1_q_b[13] is std_1c20:inst|cpu:the_cpu|cpu_register_bank_b_module:cpu_register_bank_b|altsyncram:the_altsyncram|altsyncram_4vd1:auto_generated|q_b[13] at M4K_X49_Y15

DD1_q_b[13] = AMPP_FUNCTION(GND, GND, QC2__clk0, QC2__clk0, !S1_M_wr_dst_reg, S1_W_stall, S1L2464, S1_M_dst_regnum[0], S1_M_dst_regnum[1], S1_M_dst_regnum[2], S1_M_dst_regnum[3], S1_M_dst_regnum[4], AD1_q_b[22], AD1_q_b[23], AD1_q_b[24], AD1_q_b[25], AD1_q_b[26], GND, GND, GND, GND, S1L2437, S1L2434, S1L2431, S1L2428, S1L2467, S1L2425, S1L2422, S1L2419, S1L2416, S1L2398, S1L2401, S1L2458, S1L2455, S1L2449, S1L2446, S1L2440, S1L2443, S1L2452, S1L2461, S1L2537, S1L2410, S1L2404, S1L2407, S1L2395, S1L2517, S1L2495, S1L2470, S1L2482, S1L2479, S1L2476, S1L2473);

--DD1_q_b[14] is std_1c20:inst|cpu:the_cpu|cpu_register_bank_b_module:cpu_register_bank_b|altsyncram:the_altsyncram|altsyncram_4vd1:auto_generated|q_b[14] at M4K_X49_Y15

DD1_q_b[14] = AMPP_FUNCTION(GND, GND, QC2__clk0, QC2__clk0, !S1_M_wr_dst_reg, S1_W_stall, S1L2464, S1_M_dst_regnum[0], S1_M_dst_regnum[1], S1_M_dst_regnum[2], S1_M_dst_regnum[3], S1_M_dst_regnum[4], AD1_q_b[22], AD1_q_b[23], AD1_q_b[24], AD1_q_b[25], AD1_q_b[26], GND, GND, GND, GND, S1L2437, S1L2434, S1L2431, S1L2428, S1L2467, S1L2425, S1L2422, S1L2419, S1L2416, S1L2398, S1L2401, S1L2458, S1L2455, S1L2449, S1L2446, S1L2440, S1L2443, S1L2452, S1L2461, S1L2537, S1L2410, S1L2404, S1L2407, S1L2395, S1L2517, S1L2495, S1L2470, S1L2482, S1L2479, S1L2476, S1L2473);

--DD1_q_b[15] is std_1c20:inst|cpu:the_cpu|cpu_register_bank_b_module:cpu_register_bank_b|altsyncram:the_altsyncram|altsyncram_4vd1:auto_generated|q_b[15] at M4K_X49_Y15

DD1_q_b[15] = AMPP_FUNCTION(GND, GND, QC2__clk0, QC2__clk0, !S1_M_wr_dst_reg, S1_W_stall, S1L2464, S1_M_dst_regnum[0], S1_M_dst_regnum[1], S1_M_dst_regnum[2], S1_M_dst_regnum[3], S1_M_dst_regnum[4], AD1_q_b[22], AD1_q_b[23], AD1_q_b[24], AD1_q_b[25], AD1_q_b[26], GND, GND, GND, GND, S1L2437, S1L2434, S1L2431, S1L2428, S1L2467, S1L2425, S1L2422, S1L2419, S1L2416, S1L2398, S1L2401, S1L2458, S1L2455, S1L2449, S1L2446, S1L2440, S1L2443, S1L2452, S1L2461, S1L2537, S1L2410, S1L2404, S1L2407, S1L2395, S1L2517, S1L2495, S1L2470, S1L2482, S1L2479, S1L2476, S1L2473);

--S1_D_iw[25] is std_1c20:inst|cpu:the_cpu|D_iw[25] at LC_X31_Y17_N3

--operation mode is normal

S1_D_iw[25] = AMPP_FUNCTION(QC2__clk0, S1L1257, S1L1709, S1L2381, AD1_q_b[25], F1_data_out, S1_W_stall);

--S1_D_iw[26] is std_1c20:inst|cpu:the_cpu|D_iw[26] at LC_X30_Y16_N8

--operation mode is normal

S1_D_iw[26] = AMPP_FUNCTION(QC2__clk0, S1L1709, AD1_q_b[26], S1L1257, S1L2381, F1_data_out, S1_W_stall);

--S1_D_iw[24] is std_1c20:inst|cpu:the_cpu|D_iw[24] at LC_X30_Y16_N5

--operation mode is normal

S1_D_iw[24] = AMPP_FUNCTION(QC2__clk0, S1L1257, S1L2381, AD1_q_b[24], S1L1709, F1_data_out, S1_W_stall);

--S1L665 is std_1c20:inst|cpu:the_cpu|D_src2_hazard_W~58 at LC_X34_Y15_N5

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

S1L665 = AMPP_FUNCTION(S1_D_iw[26], S1_D_iw[24], S1_W_dst_regnum[4]);

--S1_W_dst_regnum[2] is std_1c20:inst|cpu:the_cpu|W_dst_regnum[2] at LC_X34_Y15_N5

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

S1_W_dst_regnum[2] = AMPP_FUNCTION(QC2__clk0, S1_M_dst_regnum[2], F1_data_out, GND, S1_W_stall);

--S1_D_iw[22] is std_1c20:inst|cpu:the_cpu|D_iw[22] at LC_X31_Y17_N6

--operation mode is normal

S1_D_iw[22] = AMPP_FUNCTION(QC2__clk0, S1L2381, AD1_q_b[22], S1L1709, S1L1257, F1_data_out, S1_W_stall);

--S1_D_iw[23] is std_1c20:inst|cpu:the_cpu|D_iw[23] at LC_X30_Y16_N3

--operation mode is normal

S1_D_iw[23] = AMPP_FUNCTION(QC2__clk0, S1L1709, AD1_q_b[23], S1L1257, S1L2381, F1_data_out, S1_W_stall);

--S1L666 is std_1c20:inst|cpu:the_cpu|D_src2_hazard_W~59 at LC_X33_Y15_N0

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

S1L666 = AMPP_FUNCTION(S1_D_iw[23], S1_W_dst_regnum[1], S1_D_iw[22]);

--S1_W_dst_regnum[0] is std_1c20:inst|cpu:the_cpu|W_dst_regnum[0] at LC_X33_Y15_N0

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

S1_W_dst_regnum[0] = AMPP_FUNCTION(QC2__clk0, S1_M_dst_regnum[0], F1_data_out, GND, S1_W_stall);

--S1L667 is std_1c20:inst|cpu:the_cpu|D_src2_hazard_W~60 at LC_X34_Y15_N6

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

S1L667 = AMPP_FUNCTION(S1_D_iw[25], S1L666, S1L665);

--S1_W_dst_regnum[3] is std_1c20:inst|cpu:the_cpu|W_dst_regnum[3] at LC_X34_Y15_N6

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

S1_W_dst_regnum[3] = AMPP_FUNCTION(QC2__clk0, S1_M_dst_regnum[3], F1_data_out, GND, S1_W_stall);

--S1L668 is std_1c20:inst|cpu:the_cpu|D_src2_hazard_W~61 at LC_X34_Y15_N8

--operation mode is normal

S1L668 = AMPP_FUNCTION(S1L667, S1_W_wr_dst_reg, S1L1170, S1L285);

--S1L661 is std_1c20:inst|cpu:the_cpu|D_src2_hazard_M~42 at LC_X34_Y15_N0

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

S1L661 = AMPP_FUNCTION(S1_M_dst_regnum[4], S1_D_iw[24], S1_D_iw[26]);

--S1_M_dst_regnum[2] is std_1c20:inst|cpu:the_cpu|M_dst_regnum[2] at LC_X34_Y15_N0

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

S1_M_dst_regnum[2] = AMPP_FUNCTION(QC2__clk0, S1_E_dst_regnum[2], F1_data_out, GND, S1_W_stall);

--S1L662 is std_1c20:inst|cpu:the_cpu|D_src2_hazard_M~43 at LC_X33_Y15_N1

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

S1L662 = AMPP_FUNCTION(S1_D_iw[23], S1_M_dst_regnum[1], S1_D_iw[22]);

--S1_M_dst_regnum[0] is std_1c20:inst|cpu:the_cpu|M_dst_regnum[0] at LC_X33_Y15_N1

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

S1_M_dst_regnum[0] = AMPP_FUNCTION(QC2__clk0, S1_E_dst_regnum[0], F1_data_out, GND, S1_W_stall);

--S1L663 is std_1c20:inst|cpu:the_cpu|D_src2_hazard_M~44 at LC_X34_Y15_N1

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

S1L663 = AMPP_FUNCTION(S1_D_iw[25], S1L661, S1L662);

--S1_M_dst_regnum[3] is std_1c20:inst|cpu:the_cpu|M_dst_regnum[3] at LC_X34_Y15_N1

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

S1_M_dst_regnum[3] = AMPP_FUNCTION(QC2__clk0, S1_E_dst_regnum[3], F1_data_out, GND, S1_W_stall);

--S1L664 is std_1c20:inst|cpu:the_cpu|D_src2_hazard_M~45 at LC_X34_Y15_N9

--operation mode is normal

S1L664 = AMPP_FUNCTION(S1L285, S1_M_wr_dst_reg, S1L1170, S1L663);

--S1L658 is std_1c20:inst|cpu:the_cpu|D_src2_hazard_E~41 at LC_X33_Y15_N5

--operation mode is normal

S1L658 = AMPP_FUNCTION(S1_D_iw[26], S1_E_dst_regnum[1], S1_E_dst_regnum[4], S1_D_iw[23]);

--S1L659 is std_1c20:inst|cpu:the_cpu|D_src2_hazard_E~42 at LC_X33_Y15_N9

--operation mode is normal

S1L659 = AMPP_FUNCTION(S1_E_dst_regnum[0], S1_E_dst_regnum[3], S1_D_iw[25], S1_D_iw[22]);

--S1L660 is std_1c20:inst|cpu:the_cpu|D_src2_hazard_E~43 at LC_X33_Y15_N8

--operation mode is normal

S1L660 = AMPP_FUNCTION(S1L659, S1L1170, S1L285, S1L658);

--S1L607 is std_1c20:inst|cpu:the_cpu|d_readdata_d1[24]~159 at LC_X40_Y19_N0

--operation mode is normal

S1L607 = AMPP_FUNCTION(S1L522Q, S1L524Q, S1L609Q, S1L608Q);

--S1L98 is std_1c20:inst|cpu:the_cpu|Add1~260 at LC_X28_Y18_N8

--operation mode is arithmetic

S1L98 = AMPP_FUNCTION(S1_D_pc_plus_one[14], S1_D_iw[21], S1L111, S1L102, S1L103);

--S1L99 is std_1c20:inst|cpu:the_cpu|Add1~261 at LC_X28_Y18_N8

--operation mode is arithmetic

S1L99 = AMPP_FUNCTION(S1_D_pc_plus_one[14], S1_D_iw[21], S1L102);

--S1L100 is std_1c20:inst|cpu:the_cpu|Add1~261COUT1_829 at LC_X28_Y18_N8

--operation mode is arithmetic

S1L100 = AMPP_FUNCTION(S1_D_pc_plus_one[14], S1_D_iw[21], S1L103);

--S1L567 is std_1c20:inst|cpu:the_cpu|d_readdata_d1[16]~156 at LC_X41_Y20_N5

--operation mode is normal

S1L567 = AMPP_FUNCTION(S1L568Q, S1L522Q, S1L569Q, S1L524Q);

--S1_E_src2_prelim[16] is std_1c20:inst|cpu:the_cpu|E_src2_prelim[16] at LC_X43_Y15_N3

--operation mode is normal

S1_E_src2_prelim[16] = AMPP_FUNCTION(QC2__clk0, S1L668, S1_W_wr_data[16], S1L2440, DD1_q_b[16], F1_data_out, S1L664, S1_W_stall);

--S1L101 is std_1c20:inst|cpu:the_cpu|Add1~262 at LC_X28_Y18_N7

--operation mode is arithmetic

S1L101 = AMPP_FUNCTION(S1_D_pc_plus_one[13], S1_D_iw[21], S1L111, S1L105, S1L106);

--S1L102 is std_1c20:inst|cpu:the_cpu|Add1~263 at LC_X28_Y18_N7

--operation mode is arithmetic

S1L102 = AMPP_FUNCTION(S1_D_pc_plus_one[13], S1_D_iw[21], S1L105);

--S1L103 is std_1c20:inst|cpu:the_cpu|Add1~263COUT1_827 at LC_X28_Y18_N7

--operation mode is arithmetic

S1L103 = AMPP_FUNCTION(S1_D_pc_plus_one[13], S1_D_iw[21], S1L106);

--S1_av_fill_bit is std_1c20:inst|cpu:the_cpu|av_fill_bit at LC_X39_Y20_N3

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

S1_av_fill_bit = AMPP_FUNCTION(S1L239);

--S1_M_ctrl_ld_signed is std_1c20:inst|cpu:the_cpu|M_ctrl_ld_signed at LC_X39_Y20_N3

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

S1_M_ctrl_ld_signed = AMPP_FUNCTION(QC2__clk0, S1_E_ctrl_ld_signed, F1_data_out, GND, S1_W_stall);

--S1L1186 is std_1c20:inst|cpu:the_cpu|Equal145~6 at LC_X39_Y20_N4

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

S1L1186 = AMPP_FUNCTION(S1_M_iw[3]);

--S1_M_iw[4] is std_1c20:inst|cpu:the_cpu|M_iw[4] at LC_X39_Y20_N4

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

S1_M_iw[4] = AMPP_FUNCTION(QC2__clk0, S1_E_iw[4], F1_data_out, GND, S1_W_stall);

--S1L104 is std_1c20:inst|cpu:the_cpu|Add1~264 at LC_X28_Y18_N6

--operation mode is arithmetic

S1L104 = AMPP_FUNCTION(S1_D_iw[20], S1_D_pc_plus_one[12], S1L111, S1L108, S1L109);

--S1L105 is std_1c20:inst|cpu:the_cpu|Add1~265 at LC_X28_Y18_N6

--operation mode is arithmetic

S1L105 = AMPP_FUNCTION(S1_D_iw[20], S1_D_pc_plus_one[12], S1L108);

--S1L106 is std_1c20:inst|cpu:the_cpu|Add1~265COUT1_825 at LC_X28_Y18_N6

--operation mode is arithmetic

S1L106 = AMPP_FUNCTION(S1_D_iw[20], S1_D_pc_plus_one[12], S1L109);

--S1_D_iw[20] is std_1c20:inst|cpu:the_cpu|D_iw[20] at LC_X28_Y16_N5

--operation mode is normal

S1_D_iw[20] = AMPP_FUNCTION(QC2__clk0, S1L1709, S1L2381, S1L1257, AD1_q_b[20], F1_data_out, S1_W_stall);

--S1L557 is std_1c20:inst|cpu:the_cpu|d_readdata_d1[14]~123 at LC_X42_Y22_N7

--operation mode is normal

S1L557 = AMPP_FUNCTION(T1L191, S1L524Q, S1L522Q, S1L558Q);

--S1L637 is std_1c20:inst|cpu:the_cpu|d_readdata_d1[30]~132 at LC_X42_Y20_N3

--operation mode is normal

S1L637 = AMPP_FUNCTION(S1L638Q, S1L522Q, S1L524Q, S1L639Q);

--S1L107 is std_1c20:inst|cpu:the_cpu|Add1~266 at LC_X28_Y18_N5

--operation mode is arithmetic

S1L107 = AMPP_FUNCTION(S1_D_iw[19], S1_D_pc_plus_one[11], S1L111);

--S1L108 is std_1c20:inst|cpu:the_cpu|Add1~267 at LC_X28_Y18_N5

--operation mode is arithmetic

S1L108 = AMPP_FUNCTION(S1_D_iw[19], S1_D_pc_plus_one[11]);

--S1L109 is std_1c20:inst|cpu:the_cpu|Add1~267COUT1_823 at LC_X28_Y18_N5

--operation mode is arithmetic

S1L109 = AMPP_FUNCTION(S1_D_iw[19], S1_D_pc_plus_one[11]);

--S1_D_iw[19] is std_1c20:inst|cpu:the_cpu|D_iw[19] at LC_X28_Y16_N9

--operation mode is normal

S1_D_iw[19] = AMPP_FUNCTION(QC2__clk0, S1L1709, S1L2381, S1L1257, AD1_q_b[19], F1_data_out, S1_W_stall);

--S1L551 is std_1c20:inst|cpu:the_cpu|d_readdata_d1[13]~120 at LC_X38_Y22_N4

--operation mode is normal

S1L551 = AMPP_FUNCTION(S1L522Q, S1L524Q, S1L552Q, T1L185);

--S1L632 is std_1c20:inst|cpu:the_cpu|d_readdata_d1[29]~153 at LC_X40_Y20_N5

--operation mode is normal

S1L632 = AMPP_FUNCTION(S1L634Q, S1L522Q, S1L524Q, S1L633Q);

--S1L110 is std_1c20:inst|cpu:the_cpu|Add1~268 at LC_X28_Y18_N4

--operation mode is arithmetic

S1L110 = AMPP_FUNCTION(S1_D_pc_plus_one[10], S1_D_iw[18], S1L122, S1L123);

--S1L111 is std_1c20:inst|cpu:the_cpu|Add1~269 at LC_X28_Y18_N4

--operation mode is arithmetic

S1L111 = AMPP_FUNCTION(S1_D_pc_plus_one[10], S1_D_iw[18], S1L122, S1L123);

--S1_D_iw[18] is std_1c20:inst|cpu:the_cpu|D_iw[18] at LC_X28_Y16_N6

--operation mode is normal

S1_D_iw[18] = AMPP_FUNCTION(QC2__clk0, S1L1709, S1L2381, S1L1257, AD1_q_b[18], F1_data_out, S1_W_stall);

--S1L545 is std_1c20:inst|cpu:the_cpu|d_readdata_d1[12]~117 at LC_X40_Y21_N3

--operation mode is normal

S1L545 = AMPP_FUNCTION(S1L522Q, S1L524Q, S1L546Q, T1L178);

--S1L627 is std_1c20:inst|cpu:the_cpu|d_readdata_d1[28]~150 at LC_X40_Y19_N4

--operation mode is normal

S1L627 = AMPP_FUNCTION(S1L629Q, S1L522Q, S1L628Q, S1L524Q);

--S1L112 is std_1c20:inst|cpu:the_cpu|Add1~270 at LC_X28_Y18_N9

--operation mode is arithmetic

S1L112 = AMPP_FUNCTION(S1_D_pc_plus_one[15], S1_D_iw[21], S1L111, S1L99, S1L100);

--S1L113 is std_1c20:inst|cpu:the_cpu|Add1~271 at LC_X28_Y18_N9

--operation mode is arithmetic

S1L113 = AMPP_FUNCTION(S1_D_pc_plus_one[15], S1_D_iw[21], S1L111, S1L99, S1L100);

--S1L572 is std_1c20:inst|cpu:the_cpu|d_readdata_d1[17]~147 at LC_X41_Y21_N9

--operation mode is normal

S1L572 = AMPP_FUNCTION(S1L524Q, S1L574Q, S1L522Q, S1L573Q);

--S1_E_src2_prelim[17] is std_1c20:inst|cpu:the_cpu|E_src2_prelim[17] at LC_X42_Y14_N0

--operation mode is normal

S1_E_src2_prelim[17] = AMPP_FUNCTION(QC2__clk0, S1_W_wr_data[17], S1L668, S1L2443, DD1_q_b[17], F1_data_out, S1L664, S1_W_stall);

--S1L114 is std_1c20:inst|cpu:the_cpu|Add1~272 at LC_X28_Y17_N7

--operation mode is normal

S1L114 = AMPP_FUNCTION(S1_D_iw[21], S1_D_pc_plus_one[23], S1L85, S1L96, S1L97);

--S1_M_shift_rot_result[26] is std_1c20:inst|cpu:the_cpu|M_shift_rot_result[26] at LC_X40_Y12_N8

--operation mode is normal

S1_M_shift_rot_result[26] = AMPP_FUNCTION(QC2__clk0, S1_M_shift_rot_result[27], S1_M_shift_rot_result[25], S1L879, S1_M_ctrl_shift_rot_right, F1_data_out, !S1_M_shift_rot_stall);

--S1L612 is std_1c20:inst|cpu:the_cpu|d_readdata_d1[25]~144 at LC_X43_Y21_N8

--operation mode is normal

S1L612 = AMPP_FUNCTION(S1L613Q, S1L524Q, S1L522Q, S1L614Q);

--S1L115 is std_1c20:inst|cpu:the_cpu|Add1~274 at LC_X28_Y17_N2

--operation mode is arithmetic

S1L115 = AMPP_FUNCTION(S1_D_iw[21], S1_D_pc_plus_one[18], S1L113, S1L90, S1L91);

--S1L116 is std_1c20:inst|cpu:the_cpu|Add1~275 at LC_X28_Y17_N2

--operation mode is arithmetic

S1L116 = AMPP_FUNCTION(S1_D_iw[21], S1_D_pc_plus_one[18], S1L90);

--S1L117 is std_1c20:inst|cpu:the_cpu|Add1~275COUT1_835 at LC_X28_Y17_N2

--operation mode is arithmetic

S1L117 = AMPP_FUNCTION(S1_D_iw[21], S1_D_pc_plus_one[18], S1L91);

--S1L587 is std_1c20:inst|cpu:the_cpu|d_readdata_d1[20]~141 at LC_X41_Y20_N8

--operation mode is normal

S1L587 = AMPP_FUNCTION(S1L589Q, S1L588Q, S1L522Q, S1L524Q);

--S1_D_iw[10] is std_1c20:inst|cpu:the_cpu|D_iw[10] at LC_X31_Y17_N2

--operation mode is normal

S1_D_iw[10] = AMPP_FUNCTION(QC2__clk0, S1L1257, S1L1709, AD1_q_b[10], S1L2381, F1_data_out, S1_W_stall);

--S1_E_src2_prelim[20] is std_1c20:inst|cpu:the_cpu|E_src2_prelim[20] at LC_X39_Y14_N5

--operation mode is normal

S1_E_src2_prelim[20] = AMPP_FUNCTION(QC2__clk0, S1_W_wr_data[20], S1L668, S1L2452, DD1_q_b[20], F1_data_out, S1L664, S1_W_stall);

--S1L118 is std_1c20:inst|cpu:the_cpu|Add1~276 at LC_X28_Y17_N5

--operation mode is arithmetic

S1L118 = AMPP_FUNCTION(S1_D_iw[21], S1_D_pc_plus_one[21], S1L85);

--S1L119 is std_1c20:inst|cpu:the_cpu|Add1~277 at LC_X28_Y17_N5

--operation mode is arithmetic

S1L119 = AMPP_FUNCTION(S1_D_iw[21], S1_D_pc_plus_one[21]);

--S1L120 is std_1c20:inst|cpu:the_cpu|Add1~277COUT1_839 at LC_X28_Y17_N5

--operation mode is arithmetic

S1L120 = AMPP_FUNCTION(S1_D_iw[21], S1_D_pc_plus_one[21]);

--S1_E_src2_prelim[23] is std_1c20:inst|cpu:the_cpu|E_src2_prelim[23] at LC_X43_Y14_N7

--operation mode is normal

S1_E_src2_prelim[23] = AMPP_FUNCTION(QC2__clk0, S1_W_wr_data[23], DD1_q_b[23], S1L2461, S1L668, F1_data_out, S1L664, S1_W_stall);

--S1_D_br_taken_waddr_partial[9] is std_1c20:inst|cpu:the_cpu|D_br_taken_waddr_partial[9] at LC_X26_Y18_N4

--operation mode is arithmetic

S1_D_br_taken_waddr_partial[9] = AMPP_FUNCTION(QC2__clk0, S1L1309, AD1_q_b[17], F1_data_out, S1_W_stall, S1L255, S1L266, S1L267);

--S1L269 is std_1c20:inst|cpu:the_cpu|D_br_taken_waddr_partial[9]~57 at LC_X26_Y18_N4

--operation mode is arithmetic

S1L269 = AMPP_FUNCTION(S1L1309, AD1_q_b[17], S1L255, S1L266, S1L267);

--S1_D_iw[17] is std_1c20:inst|cpu:the_cpu|D_iw[17] at LC_X31_Y17_N1

--operation mode is normal

S1_D_iw[17] = AMPP_FUNCTION(QC2__clk0, S1L1257, S1L1709, AD1_q_b[17], S1L2381, F1_data_out, S1_W_stall);

--S1L537 is std_1c20:inst|cpu:the_cpu|d_readdata_d1[11]~114 at LC_X38_Y22_N8

--operation mode is normal

S1L537 = AMPP_FUNCTION(S1L522Q, S1L538Q, S1L524Q, T1L169);

--S1L622 is std_1c20:inst|cpu:the_cpu|d_readdata_d1[27]~138 at LC_X40_Y20_N1

--operation mode is normal

S1L622 = AMPP_FUNCTION(S1L624Q, S1L522Q, S1L524Q, S1L623Q);

--S1_D_br_taken_waddr_partial[8] is std_1c20:inst|cpu:the_cpu|D_br_taken_waddr_partial[8] at LC_X26_Y18_N3

--operation mode is arithmetic

S1_D_br_taken_waddr_partial[8] = AMPP_FUNCTION(QC2__clk0, S1L1306, AD1_q_b[16], F1_data_out, S1_W_stall, S1L255, S1L263, S1L264);

--S1L266 is std_1c20:inst|cpu:the_cpu|D_br_taken_waddr_partial[8]~58 at LC_X26_Y18_N3

--operation mode is arithmetic

S1L266 = AMPP_FUNCTION(S1L1306, AD1_q_b[16], S1L263);

--S1L267 is std_1c20:inst|cpu:the_cpu|D_br_taken_waddr_partial[8]~58COUT1_474 at LC_X26_Y18_N3

--operation mode is arithmetic

S1L267 = AMPP_FUNCTION(S1L1306, AD1_q_b[16], S1L264);

--S1L533 is std_1c20:inst|cpu:the_cpu|d_readdata_d1[10]~128 at LC_X42_Y22_N4

--operation mode is normal

S1L533 = AMPP_FUNCTION(S1L534Q, S1L524Q, S1L522Q, S1L1448Q);

--S1L617 is std_1c20:inst|cpu:the_cpu|d_readdata_d1[26]~135 at LC_X42_Y19_N6

--operation mode is normal

S1L617 = AMPP_FUNCTION(S1L522Q, S1L618Q, S1L524Q, S1L619Q);

--S1_D_br_taken_waddr_partial[7] is std_1c20:inst|cpu:the_cpu|D_br_taken_waddr_partial[7] at LC_X26_Y18_N2

--operation mode is arithmetic

S1_D_br_taken_waddr_partial[7] = AMPP_FUNCTION(QC2__clk0, AD1_q_b[15], S1L1303, F1_data_out, S1_W_stall, S1L255, S1L260, S1L261);

--S1L263 is std_1c20:inst|cpu:the_cpu|D_br_taken_waddr_partial[7]~59 at LC_X26_Y18_N2

--operation mode is arithmetic

S1L263 = AMPP_FUNCTION(AD1_q_b[15], S1L1303, S1L260);

--S1L264 is std_1c20:inst|cpu:the_cpu|D_br_taken_waddr_partial[7]~59COUT1_472 at LC_X26_Y18_N2

--operation mode is arithmetic

S1L264 = AMPP_FUNCTION(AD1_q_b[15], S1L1303, S1L261);

--S1L529 is std_1c20:inst|cpu:the_cpu|d_readdata_d1[9]~126 at LC_X40_Y19_N3

--operation mode is normal

S1L529 = AMPP_FUNCTION(S1L522Q, S1L524Q, S1L1443Q, S1L530Q);

--S1_D_br_taken_waddr_partial[6] is std_1c20:inst|cpu:the_cpu|D_br_taken_waddr_partial[6] at LC_X26_Y18_N1

--operation mode is arithmetic

S1_D_br_taken_waddr_partial[6] = AMPP_FUNCTION(QC2__clk0, AD1_q_b[14], S1L1301, F1_data_out, S1_W_stall, S1L255, S1L257, S1L258);

--S1L260 is std_1c20:inst|cpu:the_cpu|D_br_taken_waddr_partial[6]~60 at LC_X26_Y18_N1

--operation mode is arithmetic

S1L260 = AMPP_FUNCTION(AD1_q_b[14], S1L1301, S1L257);

--S1L261 is std_1c20:inst|cpu:the_cpu|D_br_taken_waddr_partial[6]~60COUT1_470 at LC_X26_Y18_N1

--operation mode is arithmetic

S1L261 = AMPP_FUNCTION(AD1_q_b[14], S1L1301, S1L258);

--S1L521 is std_1c20:inst|cpu:the_cpu|d_readdata_d1[8]~106 at LC_X42_Y22_N0

--operation mode is normal

S1L521 = AMPP_FUNCTION(S1L525Q, S1L524Q, S1L522Q, S1L526Q);

--S1_D_br_taken_waddr_partial[5] is std_1c20:inst|cpu:the_cpu|D_br_taken_waddr_partial[5] at LC_X26_Y18_N0

--operation mode is arithmetic

S1_D_br_taken_waddr_partial[5] = AMPP_FUNCTION(QC2__clk0, AD1_q_b[13], S1L1298, F1_data_out, S1_W_stall, S1L255);

--S1L257 is std_1c20:inst|cpu:the_cpu|D_br_taken_waddr_partial[5]~61 at LC_X26_Y18_N0

--operation mode is arithmetic

S1L257 = AMPP_FUNCTION(AD1_q_b[13], S1L1298);

--S1L258 is std_1c20:inst|cpu:the_cpu|D_br_taken_waddr_partial[5]~61COUT1_468 at LC_X26_Y18_N0

--operation mode is arithmetic

S1L258 = AMPP_FUNCTION(AD1_q_b[13], S1L1298);

--S1_E_src2_prelim[7] is std_1c20:inst|cpu:the_cpu|E_src2_prelim[7] at LC_X41_Y17_N8

--operation mode is normal

S1_E_src2_prelim[7] = AMPP_FUNCTION(QC2__clk0, S1_W_wr_data[7], S1L668, S1L2537, DD1_q_b[7], F1_data_out, S1L664, S1_W_stall);

--S1_M_ipending_reg[6] is std_1c20:inst|cpu:the_cpu|M_ipending_reg[6] at LC_X41_Y19_N1

--operation mode is normal

S1_M_ipending_reg[6] = AMPP_FUNCTION(QC2__clk0, FD1L34Q, Y1_d1_irq_from_the_lan91c111, S1L2117Q, F1_data_out);

--S1L505Q is std_1c20:inst|cpu:the_cpu|d_readdata_d1[6]~88 at LC_X46_Y26_N3

--operation mode is normal

S1L505Q = AMPP_FUNCTION(QC2__clk0, U1L159, X1_cpu_data_master_requests_epcs_controller_epcs_control_port, S1L510, S1L514, F1_data_out);

--S1L506Q is std_1c20:inst|cpu:the_cpu|d_readdata_d1[6]~89 at LC_X38_Y20_N4

--operation mode is normal

S1L506Q = AMPP_FUNCTION(QC2__clk0, S1L1424, FD1L34Q, S1L523, WC1L21, F1_data_out);

--T1_cpu_data_master_readdata[6] is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[6] at LC_X40_Y20_N6

--operation mode is normal

T1_cpu_data_master_readdata[6] = S1L505Q & S1L506Q;

--S1_E_src2_prelim[6] is std_1c20:inst|cpu:the_cpu|E_src2_prelim[6] at LC_X36_Y17_N5

--operation mode is normal

S1_E_src2_prelim[6] = AMPP_FUNCTION(QC2__clk0, S1L668, DD1_q_b[6], S1L2410, S1_W_wr_data[6], F1_data_out, S1L664, S1_W_stall);

--S1_D_br_taken_waddr_partial[4] is std_1c20:inst|cpu:the_cpu|D_br_taken_waddr_partial[4] at LC_X26_Y19_N9

--operation mode is arithmetic

S1_D_br_taken_waddr_partial[4] = AMPP_FUNCTION(QC2__clk0, S1L1295, AD1_q_b[12], F1_data_out, S1_W_stall, S1L252, S1L253);

--S1L255 is std_1c20:inst|cpu:the_cpu|D_br_taken_waddr_partial[4]~62 at LC_X26_Y19_N9

--operation mode is arithmetic

S1L255 = AMPP_FUNCTION(S1L1295, AD1_q_b[12], S1L252, S1L253);

--S1_M_ipending_reg[4] is std_1c20:inst|cpu:the_cpu|M_ipending_reg[4] at LC_X38_Y20_N2

--operation mode is normal

S1_M_ipending_reg[4] = AMPP_FUNCTION(QC2__clk0, FD1L28Q, S1L2107Q, XE1_irq, F1_data_out);

--S1L485Q is std_1c20:inst|cpu:the_cpu|d_readdata_d1[4]~92 at LC_X43_Y23_N6

--operation mode is normal

S1L485Q = AMPP_FUNCTION(QC2__clk0, X1_cpu_data_master_requests_epcs_controller_epcs_control_port, S1L494, U1L160, S1L490, F1_data_out);

--S1L486Q is std_1c20:inst|cpu:the_cpu|d_readdata_d1[4]~93 at LC_X38_Y20_N1

--operation mode is normal

S1L486Q = AMPP_FUNCTION(QC2__clk0, FD1L28Q, S1L523, WC1L7, WC1L21, F1_data_out);

--T1_cpu_data_master_readdata[4] is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[4] at LC_X41_Y20_N7

--operation mode is normal

T1_cpu_data_master_readdata[4] = S1L485Q & S1L486Q;

--S1_E_src2_prelim[4] is std_1c20:inst|cpu:the_cpu|E_src2_prelim[4] at LC_X41_Y16_N1

--operation mode is normal

S1_E_src2_prelim[4] = AMPP_FUNCTION(QC2__clk0, S1_W_wr_data[4], DD1_q_b[4], S1L2404, S1L668, F1_data_out, S1L664, S1_W_stall);

--S1_D_br_taken_waddr_partial[2] is std_1c20:inst|cpu:the_cpu|D_br_taken_waddr_partial[2] at LC_X26_Y19_N7

--operation mode is arithmetic

S1_D_br_taken_waddr_partial[2] = AMPP_FUNCTION(QC2__clk0, AD1_q_b[10], S1L1289, F1_data_out, S1_W_stall, S1L246, S1L247);

--S1L249 is std_1c20:inst|cpu:the_cpu|D_br_taken_waddr_partial[2]~63 at LC_X26_Y19_N7

--operation mode is arithmetic

S1L249 = AMPP_FUNCTION(AD1_q_b[10], S1L1289, S1L246);

--S1L250 is std_1c20:inst|cpu:the_cpu|D_br_taken_waddr_partial[2]~63COUT1_464 at LC_X26_Y19_N7

--operation mode is arithmetic

S1L250 = AMPP_FUNCTION(AD1_q_b[10], S1L1289, S1L247);

--S1_M_ipending_reg[5] is std_1c20:inst|cpu:the_cpu|M_ipending_reg[5] at LC_X37_Y20_N2

--operation mode is normal

S1_M_ipending_reg[5] = AMPP_FUNCTION(QC2__clk0, S1L2110Q, FD1L31Q, DE1_irq_reg, F1_data_out);

--S1L495Q is std_1c20:inst|cpu:the_cpu|d_readdata_d1[5]~90 at LC_X46_Y23_N9

--operation mode is normal

S1L495Q = AMPP_FUNCTION(QC2__clk0, X1_cpu_data_master_requests_epcs_controller_epcs_control_port, U1L161, S1L500, S1L504, F1_data_out);

--S1L496Q is std_1c20:inst|cpu:the_cpu|d_readdata_d1[5]~91 at LC_X37_Y21_N5

--operation mode is normal

S1L496Q = AMPP_FUNCTION(QC2__clk0, S1L523, WC1L8, FD1L31Q, WC1L21, F1_data_out);

--T1_cpu_data_master_readdata[5] is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[5] at LC_X39_Y21_N5

--operation mode is normal

T1_cpu_data_master_readdata[5] = S1L495Q & (S1L496Q);

--S1_E_src2_prelim[5] is std_1c20:inst|cpu:the_cpu|E_src2_prelim[5] at LC_X39_Y18_N4

--operation mode is normal

S1_E_src2_prelim[5] = AMPP_FUNCTION(QC2__clk0, S1_W_wr_data[5], S1L668, S1L2407, DD1_q_b[5], F1_data_out, S1L664, S1_W_stall);

--S1_D_br_taken_waddr_partial[3] is std_1c20:inst|cpu:the_cpu|D_br_taken_waddr_partial[3] at LC_X26_Y19_N8

--operation mode is arithmetic

S1_D_br_taken_waddr_partial[3] = AMPP_FUNCTION(QC2__clk0, S1L1292, AD1_q_b[11], F1_data_out, S1_W_stall, S1L249, S1L250);

--S1L252 is std_1c20:inst|cpu:the_cpu|D_br_taken_waddr_partial[3]~64 at LC_X26_Y19_N8

--operation mode is arithmetic

S1L252 = AMPP_FUNCTION(S1L1292, AD1_q_b[11], S1L249);

--S1L253 is std_1c20:inst|cpu:the_cpu|D_br_taken_waddr_partial[3]~64COUT1_466 at LC_X26_Y19_N8

--operation mode is arithmetic

S1L253 = AMPP_FUNCTION(S1L1292, AD1_q_b[11], S1L250);

--S1L922 is std_1c20:inst|cpu:the_cpu|E_src2[0]~1528 at LC_X37_Y16_N8

--operation mode is normal

S1L922 = AMPP_FUNCTION(S1L2392, S1L926, S1L924);

--S1_E_src1_prelim[0] is std_1c20:inst|cpu:the_cpu|E_src1_prelim[0] at LC_X44_Y16_N6

--operation mode is normal

S1_E_src1_prelim[0] = AMPP_FUNCTION(QC2__clk0, S1_W_wr_data[0], S1_D_src1_hazard_W, S1L2517, CD1_q_b[0], F1_data_out, S1_D_src1_hazard_M, S1_W_stall);

--S1_M_shift_rot_result[0] is std_1c20:inst|cpu:the_cpu|M_shift_rot_result[0] at LC_X37_Y14_N6

--operation mode is normal

S1_M_shift_rot_result[0] = AMPP_FUNCTION(QC2__clk0, S1L2221, S1_M_shift_rot_result[1], S1L851, S1_M_ctrl_shift_rot_right, F1_data_out, !S1_M_shift_rot_stall);

--S1L2390 is std_1c20:inst|cpu:the_cpu|M_wr_data_unfiltered[0]~3693 at LC_X37_Y14_N0

--operation mode is normal

S1L2390 = AMPP_FUNCTION(S1L2056Q, S1_M_shift_rot_result[0]);

--S1_av_ld_data_aligned_or_div[0] is std_1c20:inst|cpu:the_cpu|av_ld_data_aligned_or_div[0] at LC_X39_Y19_N1

--operation mode is normal

S1_av_ld_data_aligned_or_div[0] = AMPP_FUNCTION(QC2__clk0, S1_M_ld_align_sh16, T1_cpu_data_master_readdata[0], S1L156, S1L567, F1_data_out, S1_M_ld_align_sh8);

--S1_av_ld_or_div_done is std_1c20:inst|cpu:the_cpu|av_ld_or_div_done at LC_X38_Y16_N1

--operation mode is normal

S1_av_ld_or_div_done = AMPP_FUNCTION(QC2__clk0, S1_av_ld_aligning_data, F1_data_out);

--S1L851 is std_1c20:inst|cpu:the_cpu|E_src1[0]~2039 at LC_X37_Y14_N1

--operation mode is normal

S1L851 = AMPP_FUNCTION(S1L886Q, S1_E_src1_prelim[0], S1L231, S1L2390);

--S1_E_src1_prelim[1] is std_1c20:inst|cpu:the_cpu|E_src1_prelim[1] at LC_X44_Y16_N8

--operation mode is normal

S1_E_src1_prelim[1] = AMPP_FUNCTION(QC2__clk0, CD1_q_b[1], S1_D_src1_hazard_W, S1L2395, S1_W_wr_data[1], F1_data_out, S1_D_src1_hazard_M, S1_W_stall);

--S1L2393 is std_1c20:inst|cpu:the_cpu|M_wr_data_unfiltered[1]~3695 at LC_X38_Y16_N7

--operation mode is normal

S1L2393 = AMPP_FUNCTION(S1L2056Q, S1_M_shift_rot_result[1]);

--S1_av_ld_data_aligned_or_div[1] is std_1c20:inst|cpu:the_cpu|av_ld_data_aligned_or_div[1] at LC_X39_Y19_N5

--operation mode is normal

S1_av_ld_data_aligned_or_div[1] = AMPP_FUNCTION(QC2__clk0, S1L572, T1_cpu_data_master_readdata[1], S1L159, S1_M_ld_align_sh16, F1_data_out, S1_M_ld_align_sh8);

--S1_M_alu_result[1] is std_1c20:inst|cpu:the_cpu|M_alu_result[1] at LC_X38_Y16_N3

--operation mode is normal

S1_M_alu_result[1] = AMPP_FUNCTION(QC2__clk0, S1L2097, YC1_result[1], S1L2095, S1L2093, F1_data_out, S1_W_stall);

--S1L852 is std_1c20:inst|cpu:the_cpu|E_src1[1]~2040 at LC_X38_Y16_N9

--operation mode is normal

S1L852 = AMPP_FUNCTION(S1L1718, S1L886Q, S1L2393, S1_E_src1_prelim[1]);

--S1_D_pc[13] is std_1c20:inst|cpu:the_cpu|D_pc[13] at LC_X28_Y19_N8

--operation mode is normal

S1_D_pc[13] = AMPP_FUNCTION(QC2__clk0, S1_F_pc[13], F1_data_out, S1_W_stall);

--S1_D_pc[12] is std_1c20:inst|cpu:the_cpu|D_pc[12] at LC_X27_Y20_N3

--operation mode is normal

S1_D_pc[12] = AMPP_FUNCTION(QC2__clk0, S1_F_pc[12], F1_data_out, S1_W_stall);

--S1_D_pc[11] is std_1c20:inst|cpu:the_cpu|D_pc[11] at LC_X25_Y19_N3

--operation mode is normal

S1_D_pc[11] = AMPP_FUNCTION(QC2__clk0, S1_F_pc[11], F1_data_out, S1_W_stall);

--S1_D_pc[10] is std_1c20:inst|cpu:the_cpu|D_pc[10] at LC_X28_Y19_N2

--operation mode is normal

S1_D_pc[10] = AMPP_FUNCTION(QC2__clk0, S1_F_pc[10], F1_data_out, S1_W_stall);

--S1L1679 is std_1c20:inst|cpu:the_cpu|ic_tag_wraddress[6]~COMBOUT at LC_X26_Y20_N7

--operation mode is normal

S1L1679 = AMPP_FUNCTION(S1_D_ic_fill_starting, S1_ic_fill_line[6], S1_D_pc[9]);

--S1_ic_tag_wraddress[6] is std_1c20:inst|cpu:the_cpu|ic_tag_wraddress[6] at LC_X26_Y20_N7

--operation mode is normal

S1_ic_tag_wraddress[6] = AMPP_FUNCTION(QC2__clk0, S1_D_ic_fill_starting, S1_ic_fill_line[6], S1_M_alu_result[11], S1_D_pc[9], F1_data_out, !S1_reset_d1, S1L1562);

--S1L1677 is std_1c20:inst|cpu:the_cpu|ic_tag_wraddress[5]~COMBOUT at LC_X26_Y20_N2

--operation mode is normal

S1L1677 = AMPP_FUNCTION(S1_ic_fill_line[5], S1_D_ic_fill_starting, S1_D_pc[8]);

--S1_ic_tag_wraddress[5] is std_1c20:inst|cpu:the_cpu|ic_tag_wraddress[5] at LC_X26_Y20_N2

--operation mode is normal

S1_ic_tag_wraddress[5] = AMPP_FUNCTION(QC2__clk0, S1_ic_fill_line[5], S1_D_ic_fill_starting, S1L1756Q, S1_D_pc[8], F1_data_out, !S1_reset_d1, S1L1562);

--S1L1675 is std_1c20:inst|cpu:the_cpu|ic_tag_wraddress[4]~COMBOUT at LC_X26_Y20_N4

--operation mode is normal

S1L1675 = AMPP_FUNCTION(S1_D_pc[7], S1_D_ic_fill_starting, S1_ic_fill_line[4]);

--S1_ic_tag_wraddress[4] is std_1c20:inst|cpu:the_cpu|ic_tag_wraddress[4] at LC_X26_Y20_N4

--operation mode is normal

S1_ic_tag_wraddress[4] = AMPP_FUNCTION(QC2__clk0, S1_D_pc[7], S1_D_ic_fill_starting, S1_M_alu_result[9], S1_ic_fill_line[4], F1_data_out, !S1_reset_d1, S1L1562);

--S1L1673 is std_1c20:inst|cpu:the_cpu|ic_tag_wraddress[3]~COMBOUT at LC_X28_Y20_N6

--operation mode is normal

S1L1673 = AMPP_FUNCTION(S1_ic_fill_line[3], S1_D_ic_fill_starting, S1_D_pc[6]);

--S1_ic_tag_wraddress[3] is std_1c20:inst|cpu:the_cpu|ic_tag_wraddress[3] at LC_X28_Y20_N6

--operation mode is normal

S1_ic_tag_wraddress[3] = AMPP_FUNCTION(QC2__clk0, S1_ic_fill_line[3], S1_D_ic_fill_starting, S1_M_alu_result[8], S1_D_pc[6], F1_data_out, !S1_reset_d1, S1L1562);

--S1L1671 is std_1c20:inst|cpu:the_cpu|ic_tag_wraddress[2]~COMBOUT at LC_X26_Y20_N6

--operation mode is normal

S1L1671 = AMPP_FUNCTION(S1_ic_fill_line[2], S1_D_ic_fill_starting, S1_D_pc[5]);

--S1_ic_tag_wraddress[2] is std_1c20:inst|cpu:the_cpu|ic_tag_wraddress[2] at LC_X26_Y20_N6

--operation mode is normal

S1_ic_tag_wraddress[2] = AMPP_FUNCTION(QC2__clk0, S1_ic_fill_line[2], S1_D_ic_fill_starting, S1_M_alu_result[7], S1_D_pc[5], F1_data_out, !S1_reset_d1, S1L1562);

--S1L1669 is std_1c20:inst|cpu:the_cpu|ic_tag_wraddress[1]~COMBOUT at LC_X28_Y20_N4

--operation mode is normal

S1L1669 = AMPP_FUNCTION(S1_D_pc[4], S1_D_ic_fill_starting, S1_ic_fill_line[1]);

--S1_ic_tag_wraddress[1] is std_1c20:inst|cpu:the_cpu|ic_tag_wraddress[1] at LC_X28_Y20_N4

--operation mode is normal

S1_ic_tag_wraddress[1] = AMPP_FUNCTION(QC2__clk0, S1_D_pc[4], S1_D_ic_fill_starting, S1_M_alu_result[6], S1_ic_fill_line[1], F1_data_out, !S1_reset_d1, S1L1562);

--S1L1560 is std_1c20:inst|cpu:the_cpu|ic_fill_line~121 at LC_X24_Y20_N6

--operation mode is normal

S1L1560 = AMPP_FUNCTION(S1_D_pc[3], S1_ic_fill_line[0], S1L322, S1L323);

--S1L124 is std_1c20:inst|cpu:the_cpu|Add5~39 at LC_X26_Y21_N9

--operation mode is normal

S1L124 = AMPP_FUNCTION(S1_ic_fill_ap_offset[1], S1_ic_fill_ap_offset[2], S1_ic_fill_ap_offset[0]);

--S1_ic_fill_req_accepted is std_1c20:inst|cpu:the_cpu|ic_fill_req_accepted at LC_X26_Y22_N1

--operation mode is normal

S1_ic_fill_req_accepted = AMPP_FUNCTION(U1L257, U1L258, S1L1565, U1L170);

--S1L125 is std_1c20:inst|cpu:the_cpu|Add5~40 at LC_X26_Y21_N4

--operation mode is normal

S1L125 = AMPP_FUNCTION(S1_ic_fill_ap_offset[1], S1_ic_fill_ap_offset[0]);

--S1_E_control_rd_data_without_mmu_regs[1] is std_1c20:inst|cpu:the_cpu|E_control_rd_data_without_mmu_regs[1] at LC_X36_Y19_N8

--operation mode is normal

S1_E_control_rd_data_without_mmu_regs[1] = AMPP_FUNCTION(QC2__clk0, S1L273, S1_D_iw[8], S1_M_ienable_reg[1], S1_M_ipending_reg[1], F1_data_out, S1_W_stall);

--S1_M_ienable_reg[1] is std_1c20:inst|cpu:the_cpu|M_ienable_reg[1] at LC_X35_Y19_N8

--operation mode is normal

S1_M_ienable_reg[1] = AMPP_FUNCTION(QC2__clk0, S1L2095, S1L2097, S1L2093, YC1_result[1], F1_data_out, S1L2099);

--S1_E_control_rd_data_without_mmu_regs[0] is std_1c20:inst|cpu:the_cpu|E_control_rd_data_without_mmu_regs[0] at LC_X32_Y19_N3

--operation mode is normal

S1_E_control_rd_data_without_mmu_regs[0] = AMPP_FUNCTION(QC2__clk0, S1_D_iw[6], S1L2037, S1L271, S1L272, F1_data_out, S1_W_stall);

--S1L675 is std_1c20:inst|cpu:the_cpu|E_alu_result[0]~2402 at LC_X34_Y16_N2

--operation mode is normal

S1L675 = AMPP_FUNCTION(S1L680, S1L678, YC1_result[0], S1L682);

--S1L2044Q is std_1c20:inst|cpu:the_cpu|M_bstatus_reg~15 at LC_X34_Y16_N2

--operation mode is normal

S1L2044Q = AMPP_FUNCTION(QC2__clk0, S1L680, S1L678, YC1_result[0], S1L682, F1_data_out);

--S1L676 is std_1c20:inst|cpu:the_cpu|E_alu_result[0]~2403 at LC_X32_Y19_N5

--operation mode is normal

S1L676 = AMPP_FUNCTION(S1_E_ctrl_dst_data_sel_cmp, S1L697, S1L675);

--S1_M_alu_result[0] is std_1c20:inst|cpu:the_cpu|M_alu_result[0] at LC_X32_Y19_N5

--operation mode is normal

S1_M_alu_result[0] = AMPP_FUNCTION(QC2__clk0, S1_E_ctrl_dst_data_sel_cmp, S1L697, S1L675, F1_data_out, S1_W_stall);

--S1_E_src2_prelim[1] is std_1c20:inst|cpu:the_cpu|E_src2_prelim[1] at LC_X40_Y16_N7

--operation mode is normal

S1_E_src2_prelim[1] = AMPP_FUNCTION(QC2__clk0, S1_W_wr_data[1], S1L668, S1L2395, DD1_q_b[1], F1_data_out, S1L664, S1_W_stall);

--S1_E_src2_prelim[0] is std_1c20:inst|cpu:the_cpu|E_src2_prelim[0] at LC_X37_Y16_N6

--operation mode is normal

S1_E_src2_prelim[0] = AMPP_FUNCTION(QC2__clk0, S1_W_wr_data[0], S1L668, S1L2392, DD1_q_b[0], F1_data_out, S1L664, S1_W_stall);

--NB1L46 is std_1c20:inst|sdram_s1_arbitrator:the_sdram_s1|sdram_s1_address[7]~168 at LC_X22_Y19_N3

--operation mode is normal

NB1L46 = NB1L20 & (S1_M_alu_result[9]) # !NB1L20 & S1_ic_fill_line[4];

--TE1_entry_0[43] is std_1c20:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_0[43] at LC_X22_Y19_N3

--operation mode is normal

TE1_entry_0[43] = DFFEAS(NB1L46, GLOBAL(QC2__clk0), VCC, , TE1L84, , , , );

--NB1L45 is std_1c20:inst|sdram_s1_arbitrator:the_sdram_s1|sdram_s1_address[6]~169 at LC_X22_Y23_N0

--operation mode is normal

NB1L45 = NB1L20 & (S1_M_alu_result[8]) # !NB1L20 & S1_ic_fill_line[3];

--TE1_entry_0[42] is std_1c20:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_0[42] at LC_X22_Y23_N0

--operation mode is normal

TE1_entry_0[42] = DFFEAS(NB1L45, GLOBAL(QC2__clk0), VCC, , TE1L84, , , , );

--NB1L44 is std_1c20:inst|sdram_s1_arbitrator:the_sdram_s1|sdram_s1_address[5]~170 at LC_X22_Y19_N6

--operation mode is normal

NB1L44 = NB1L20 & (S1_M_alu_result[7]) # !NB1L20 & S1_ic_fill_line[2];

--TE1_entry_0[41] is std_1c20:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_0[41] at LC_X22_Y19_N6

--operation mode is normal

TE1_entry_0[41] = DFFEAS(NB1L44, GLOBAL(QC2__clk0), VCC, , TE1L84, , , , );

--NB1L43 is std_1c20:inst|sdram_s1_arbitrator:the_sdram_s1|sdram_s1_address[4]~171 at LC_X24_Y19_N2

--operation mode is normal

NB1L43 = NB1L20 & S1_M_alu_result[6] # !NB1L20 & (S1_ic_fill_line[1]);

--TE1_entry_0[40] is std_1c20:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_0[40] at LC_X24_Y19_N2

--operation mode is normal

TE1_entry_0[40] = DFFEAS(NB1L43, GLOBAL(QC2__clk0), VCC, , TE1L84, , , , );

--NB1L42 is std_1c20:inst|sdram_s1_arbitrator:the_sdram_s1|sdram_s1_address[3]~172 at LC_X22_Y19_N0

--operation mode is normal

NB1L42 = NB1L20 & S1_M_alu_result[5] # !NB1L20 & (S1_ic_fill_line[0]);

--TE1_entry_0[39] is std_1c20:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_0[39] at LC_X22_Y19_N0

--operation mode is normal

TE1_entry_0[39] = DFFEAS(NB1L42, GLOBAL(QC2__clk0), VCC, , TE1L84, , , , );

--NB1L41 is std_1c20:inst|sdram_s1_arbitrator:the_sdram_s1|sdram_s1_address[2]~173 at LC_X24_Y21_N4

--operation mode is normal

NB1L41 = NB1L20 & (S1_M_alu_result[4]) # !NB1L20 & S1_ic_fill_ap_offset[2];

--TE1_entry_0[38] is std_1c20:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_0[38] at LC_X24_Y21_N4

--operation mode is normal

TE1_entry_0[38] = DFFEAS(NB1L41, GLOBAL(QC2__clk0), VCC, , TE1L84, , , , );

--NB1L40 is std_1c20:inst|sdram_s1_arbitrator:the_sdram_s1|sdram_s1_address[1]~174 at LC_X24_Y19_N8

--operation mode is normal

NB1L40 = NB1L20 & (S1_M_alu_result[3]) # !NB1L20 & S1_ic_fill_ap_offset[1];

--TE1_entry_0[37] is std_1c20:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_0[37] at LC_X24_Y19_N8

--operation mode is normal

TE1_entry_0[37] = DFFEAS(NB1L40, GLOBAL(QC2__clk0), VCC, , TE1L84, , , , );

--NB1L39 is std_1c20:inst|sdram_s1_arbitrator:the_sdram_s1|sdram_s1_address[0]~175 at LC_X24_Y19_N6

--operation mode is normal

NB1L39 = NB1L20 & S1_M_alu_result[2] # !NB1L20 & (S1_ic_fill_ap_offset[0]);

--TE1_entry_0[36] is std_1c20:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_0[36] at LC_X24_Y19_N6

--operation mode is normal

TE1_entry_0[36] = DFFEAS(NB1L39, GLOBAL(QC2__clk0), VCC, , TE1L84, , , , );

--KB1L476 is std_1c20:inst|sdram:the_sdram|module_input1[35]~44 at LC_X24_Y21_N6

--operation mode is normal

KB1L476 = S1_internal_d_write & !S1L2177Q & NB1L20;

--TE1_entry_0[35] is std_1c20:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_0[35] at LC_X24_Y21_N6

--operation mode is normal

TE1_entry_0[35] = DFFEAS(KB1L476, GLOBAL(QC2__clk0), VCC, , TE1L84, , , , );

--KB1L475 is std_1c20:inst|sdram:the_sdram|module_input1[34]~45 at LC_X24_Y21_N5

--operation mode is normal

KB1L475 = !S1L2168Q & S1_internal_d_write & NB1L20;

--TE1_entry_0[34] is std_1c20:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_0[34] at LC_X24_Y21_N5

--operation mode is normal

TE1_entry_0[34] = DFFEAS(KB1L475, GLOBAL(QC2__clk0), VCC, , TE1L84, , , , );

--KB1L474 is std_1c20:inst|sdram:the_sdram|module_input1[33]~46 at LC_X24_Y21_N2

--operation mode is normal

KB1L474 = !S1L2158Q & (S1_internal_d_write & NB1L20);

--TE1_entry_0[33] is std_1c20:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_0[33] at LC_X24_Y21_N2

--operation mode is normal

TE1_entry_0[33] = DFFEAS(KB1L474, GLOBAL(QC2__clk0), VCC, , TE1L84, , , , );

--KB1L473 is std_1c20:inst|sdram:the_sdram|module_input1[32]~47 at LC_X24_Y21_N0

--operation mode is normal

KB1L473 = S1_internal_d_write & NB1L20 & !S1L2149Q;

--TE1_entry_0[32] is std_1c20:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_0[32] at LC_X24_Y21_N0

--operation mode is normal

TE1_entry_0[32] = DFFEAS(KB1L473, GLOBAL(QC2__clk0), VCC, , TE1L84, , , , );

--C1_jtag_debug_mode_usr1 is sld_hub:sld_hub_inst|jtag_debug_mode_usr1 at LC_X58_Y16_N4

--operation mode is normal

C1_jtag_debug_mode_usr1 = AMPP_FUNCTION(A1L5, EF1_dffs[0], C1L6, EF1_dffs[1], C1L7, FF1_state[0], FF1_state[12]);

--FF1_state[8] is sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state[8] at LC_X58_Y15_N5

--operation mode is normal

FF1_state[8] = AMPP_FUNCTION(A1L5, FF1_state[7], FF1_state[5], VCC, !A1L7);

--BF9_Q[0] is sld_hub:sld_hub_inst|sld_dffex:IRF_ENA_0|Q[0] at LC_X56_Y16_N4

--operation mode is normal

BF9_Q[0] = AMPP_FUNCTION(A1L5, altera_internal_jtag, BF3_Q[6], VCC, C1L24);

--CF1_WORD_SR[0] is sld_hub:sld_hub_inst|sld_rom_sr:HUB_INFO_REG|WORD_SR[0] at LC_X59_Y18_N4

--operation mode is normal

CF1_WORD_SR[0] = AMPP_FUNCTION(A1L5, FF1_state[4], CF1_WORD_SR[1], CF1_clear_signal, CF1L23, VCC, CF1L25);

--GF1_dffe1a[0] is sld_hub:sld_hub_inst|lpm_decode:instruction_decoder|decode_ogi:auto_generated|dffe1a[0] at LC_X57_Y17_N5

--operation mode is normal

GF1_dffe1a[0] = AMPP_FUNCTION(A1L5, BF3_Q[2], BF3_Q[3], BF3_Q[1], C1L32, !C1_CLR_SIGNAL, C1L5);

--C1L20 is sld_hub:sld_hub_inst|hub_tdo~565 at LC_X56_Y17_N5

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

C1L20 = AMPP_FUNCTION(CF1_WORD_SR[0], GF1_dffe1a[0], BF9_Q[0]);

--C1_HUB_BYPASS_REG is sld_hub:sld_hub_inst|HUB_BYPASS_REG at LC_X56_Y17_N5

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

C1_HUB_BYPASS_REG = AMPP_FUNCTION(A1L5, C1L11, VCC, GND);

--BF8_Q[0] is sld_hub:sld_hub_inst|sld_dffex:IRF_ENA|Q[0] at LC_X56_Y16_N7

--operation mode is normal

BF8_Q[0] = AMPP_FUNCTION(A1L5, altera_internal_jtag, BF3_Q[6], !C1_CLR_SIGNAL, C1L24);

--SD1_sr[0] is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|sr[0] at LC_X53_Y16_N0

--operation mode is normal

SD1_sr[0] = AMPP_FUNCTION(A1L5, SD1L140, SD1L141, SD1L143, SD1L5, !C1_CLR_SIGNAL, SD1L6);

--C1L21 is sld_hub:sld_hub_inst|hub_tdo~566 at LC_X56_Y16_N6

--operation mode is normal

C1L21 = AMPP_FUNCTION(BF8_Q[0], SD1_sr[0]);

--GE1_td_shift[0] is std_1c20:inst|jtag_uart:the_jtag_uart|alt_jtag_atlantic:jtag_uart_alt_jtag_atlantic|td_shift[0] at LC_X54_Y19_N3

--operation mode is normal

GE1_td_shift[0] = AMPP_FUNCTION(A1L5, BF4_Q[0], GE1L67, GE1L65, !C1_CLR_SIGNAL, !FF1_state[4], GE1L52);

--BF8_Q[1] is sld_hub:sld_hub_inst|sld_dffex:IRF_ENA|Q[1] at LC_X56_Y16_N9

--operation mode is normal

BF8_Q[1] = AMPP_FUNCTION(A1L5, altera_internal_jtag, BF3_Q[6], !C1_CLR_SIGNAL, C1L24);

--BF3_Q[0] is sld_hub:sld_hub_inst|sld_dffex:IRSR|Q[0] at LC_X57_Y18_N7

--operation mode is normal

BF3_Q[0] = AMPP_FUNCTION(A1L5, SD1L119Q, C1L23, BF3_Q[1], BF3L3, !C1_CLR_SIGNAL, FF1_state[4], BF3L4);

--FF1_state[4] is sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state[4] at LC_X58_Y17_N3

--operation mode is normal

FF1_state[4] = AMPP_FUNCTION(A1L5, FF1_state[3], FF1_state[7], FF1_state[4], VCC, A1L7);

--FF1_state[3] is sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state[3] at LC_X58_Y17_N4

--operation mode is normal

FF1_state[3] = AMPP_FUNCTION(A1L5, FF1_state[2], A1L7, VCC);

--FF1L18 is sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state~13 at LC_X56_Y17_N7

--operation mode is normal

FF1L18 = AMPP_FUNCTION(FF1_state[4], FF1_state[3]);

--HB1_data_out is std_1c20:inst|reconfig_request_pio:the_reconfig_request_pio|data_out at LC_X24_Y19_N3

--operation mode is normal

HB1_data_out_lut_out = XE1L16 & (HB1L3 & (S1_M_st_data[0]) # !HB1L3 & HB1_data_out) # !XE1L16 & HB1_data_out;

HB1_data_out = DFFEAS(HB1_data_out_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--HB1_data_dir is std_1c20:inst|reconfig_request_pio:the_reconfig_request_pio|data_dir at LC_X47_Y22_N3

--operation mode is normal

HB1_data_dir_lut_out = XE1L17 & (HB1L3 & (S1_M_st_data[0]) # !HB1L3 & HB1_data_dir) # !XE1L17 & HB1_data_dir;

HB1_data_dir = DFFEAS(HB1_data_dir_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--Y1L366 is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_outgoing_ext_ram_bus_data[31]~COMB_OUT at LC_X33_Y26_N8

--operation mode is normal

Y1L366 = S1_M_st_data[31] & (Y1L97 # !Y1L215);

--Y1L247 is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_in_a_write_cycle~COMB_OUT at LC_X29_Y26_N4

--operation mode is normal

Y1L247 = !Y1L718 & S1_internal_d_write & (Y1L739 # !Y1L213);

--Y1L363 is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_outgoing_ext_ram_bus_data[30]~COMB_OUT at LC_X33_Y26_N2

--operation mode is normal

Y1L363 = S1_M_st_data[30] & (Y1L97 # !Y1L215);

--Y1L360 is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_outgoing_ext_ram_bus_data[29]~COMB_OUT at LC_X33_Y25_N4

--operation mode is normal

Y1L360 = S1_M_st_data[29] & (Y1L97 # !Y1L587);

--Y1L357 is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_outgoing_ext_ram_bus_data[28]~COMB_OUT at LC_X33_Y25_N9

--operation mode is normal

Y1L357 = S1_M_st_data[28] & (Y1L737 # !Y1L587);

--Y1L354 is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_outgoing_ext_ram_bus_data[27]~COMB_OUT at LC_X33_Y27_N0

--operation mode is normal

Y1L354 = S1_M_st_data[27] & (Y1L97 # !Y1L95);

--Y1L351 is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_outgoing_ext_ram_bus_data[26]~COMB_OUT at LC_X33_Y27_N2

--operation mode is normal

Y1L351 = S1_M_st_data[26] & (Y1L97 # !Y1L95);

--Y1L348 is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_outgoing_ext_ram_bus_data[25]~COMB_OUT at LC_X33_Y27_N5

--operation mode is normal

Y1L348 = S1_M_st_data[25] & (Y1L97 # !Y1L95);

--Y1L345 is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_outgoing_ext_ram_bus_data[24]~COMB_OUT at LC_X32_Y26_N1

--operation mode is normal

Y1L345 = S1_M_st_data[24] & (Y1L739 # !Y1L215);

--Y1L342 is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_outgoing_ext_ram_bus_data[23]~COMB_OUT at LC_X33_Y26_N3

--operation mode is normal

Y1L342 = S1L2360Q & (Y1L97 # !Y1L215);

--Y1L339 is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_outgoing_ext_ram_bus_data[22]~COMB_OUT at LC_X28_Y30_N5

--operation mode is normal

Y1L339 = S1L2355Q & (Y1L739 # !Y1L215);

--Y1L336 is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_outgoing_ext_ram_bus_data[21]~COMB_OUT at LC_X30_Y28_N2

--operation mode is normal

Y1L336 = S1L2350Q & (Y1L739 # !Y1L215);

--Y1L333 is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_outgoing_ext_ram_bus_data[20]~COMB_OUT at LC_X24_Y29_N6

--operation mode is normal

Y1L333 = S1L2345Q & (Y1L737 # !Y1L587);

--Y1L330 is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_outgoing_ext_ram_bus_data[19]~COMB_OUT at LC_X28_Y30_N2

--operation mode is normal

Y1L330 = S1L2340Q & (Y1L739 # !Y1L215);

--Y1L327 is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_outgoing_ext_ram_bus_data[18]~COMB_OUT at LC_X28_Y27_N2

--operation mode is normal

Y1L327 = S1L2335Q & (Y1L739 # !Y1L95);

--Y1L324 is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_outgoing_ext_ram_bus_data[17]~COMB_OUT at LC_X25_Y27_N4

--operation mode is normal

Y1L324 = S1L2330Q & (Y1L739 # !Y1L95);

--Y1L321 is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_outgoing_ext_ram_bus_data[16]~COMB_OUT at LC_X25_Y27_N0

--operation mode is normal

Y1L321 = S1L2325Q & (Y1L739 # !Y1L95);

--Y1L318 is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_outgoing_ext_ram_bus_data[15]~COMB_OUT at LC_X25_Y29_N4

--operation mode is normal

Y1L318 = S1L2319Q & (Y1L739 # !Y1L95);

--Y1L315 is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_outgoing_ext_ram_bus_data[14]~COMB_OUT at LC_X25_Y29_N1

--operation mode is normal

Y1L315 = S1L2313Q & (Y1L739 # !Y1L95);

--Y1L312 is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_outgoing_ext_ram_bus_data[13]~COMB_OUT at LC_X25_Y29_N5

--operation mode is normal

Y1L312 = S1L2307Q & (Y1L739 # !Y1L95);

--Y1L309 is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_outgoing_ext_ram_bus_data[12]~COMB_OUT at LC_X25_Y29_N9

--operation mode is normal

Y1L309 = S1L2301Q & (Y1L739 # !Y1L95);

--Y1L306 is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_outgoing_ext_ram_bus_data[11]~COMB_OUT at LC_X25_Y29_N6

--operation mode is normal

Y1L306 = S1L2294Q & (Y1L739 # !Y1L95);

--Y1L303 is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_outgoing_ext_ram_bus_data[10]~COMB_OUT at LC_X25_Y27_N5

--operation mode is normal

Y1L303 = S1L2288Q & (Y1L739 # !Y1L95);

--Y1L300 is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_outgoing_ext_ram_bus_data[9]~COMB_OUT at LC_X24_Y29_N4

--operation mode is normal

Y1L300 = S1L2281Q & (Y1L737 # !Y1L587);

--Y1L297 is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_outgoing_ext_ram_bus_data[8]~COMB_OUT at LC_X28_Y30_N4

--operation mode is normal

Y1L297 = S1L2275Q & (Y1L739 # !Y1L215);

--Y1L294 is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_outgoing_ext_ram_bus_data[7]~COMB_OUT at LC_X26_Y26_N4

--operation mode is normal

Y1L294 = Y1L739 & S1_M_st_data[7] # !Y1L739 & (Y1L286 & (Y1L292) # !Y1L286 & S1_M_st_data[7]);

--Y1L283 is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_outgoing_ext_ram_bus_data[6]~COMB_OUT at LC_X26_Y29_N2

--operation mode is normal

Y1L283 = Y1L739 & (S1_M_st_data[6]) # !Y1L739 & (Y1L275 & Y1L281 # !Y1L275 & (S1_M_st_data[6]));

--Y1L272 is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_outgoing_ext_ram_bus_data[5]~COMB_OUT at LC_X25_Y22_N4

--operation mode is normal

Y1L272 = Y1L755 & S1_M_st_data[5] # !Y1L755 & (Y1L264 & (Y1L270) # !Y1L264 & S1_M_st_data[5]);

--Y1L261 is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_outgoing_ext_ram_bus_data[4]~COMB_OUT at LC_X23_Y29_N5

--operation mode is normal

Y1L261 = T1L433 & (Y1L995 & (Y1L988) # !Y1L995 & S1_M_st_data[4]) # !T1L433 & S1_M_st_data[4];

--S1_M_st_data[3] is std_1c20:inst|cpu:the_cpu|M_st_data[3] at LC_X44_Y19_N4

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

S1_M_st_data[3] = AMPP_FUNCTION(QC2__clk0, S1L2295, F1_data_out, GND, S1_W_stall);

--S1_M_st_data[2] is std_1c20:inst|cpu:the_cpu|M_st_data[2] at LC_X43_Y18_N2

--operation mode is normal

S1_M_st_data[2] = AMPP_FUNCTION(QC2__clk0, S1L2290, F1_data_out, S1_W_stall);

--S1_M_st_data[1] is std_1c20:inst|cpu:the_cpu|M_st_data[1] at LC_X43_Y18_N9

--operation mode is normal

S1_M_st_data[1] = AMPP_FUNCTION(QC2__clk0, S1L2282, F1_data_out, S1_W_stall);

--S1_M_st_data[0] is std_1c20:inst|cpu:the_cpu|M_st_data[0] at LC_X43_Y16_N5

--operation mode is normal

S1_M_st_data[0] = AMPP_FUNCTION(QC2__clk0, S1L2277, F1_data_out, S1_W_stall);

--KB1L411 is std_1c20:inst|sdram:the_sdram|m_data[31]~COMB_OUT at LC_X13_Y15_N5

--operation mode is normal

KB1L411 = KB1L948 & (KB1L947 & (KB1L946) # !KB1L947 & KB1L409Q) # !KB1L948 & KB1L409Q;

--KB1L409Q is std_1c20:inst|sdram:the_sdram|m_data[31]~_Duplicate_1 at LC_X13_Y15_N5

--operation mode is normal

KB1L409Q = DFFEAS(KB1L411, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--KB1_oe is std_1c20:inst|sdram:the_sdram|oe at LC_X12_Y22_N2

--operation mode is normal

KB1_oe_lut_out = KB1L985 & (!KB1L991 & TE1L152 # !KB1_f_pop);

KB1_oe = DFFEAS(KB1_oe_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--KB1L406 is std_1c20:inst|sdram:the_sdram|m_data[30]~COMB_OUT at LC_X16_Y17_N8

--operation mode is normal

KB1L406 = KB1L948 & (KB1L947 & (KB1L949) # !KB1L947 & KB1L404Q) # !KB1L948 & KB1L404Q;

--KB1L404Q is std_1c20:inst|sdram:the_sdram|m_data[30]~_Duplicate_1 at LC_X16_Y17_N8

--operation mode is normal

KB1L404Q = DFFEAS(KB1L406, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--KB1L401 is std_1c20:inst|sdram:the_sdram|m_data[29]~COMB_OUT at LC_X17_Y14_N2

--operation mode is normal

KB1L401 = KB1L947 & (KB1L948 & (KB1L950) # !KB1L948 & KB1L399Q) # !KB1L947 & KB1L399Q;

--KB1L399Q is std_1c20:inst|sdram:the_sdram|m_data[29]~_Duplicate_1 at LC_X17_Y14_N2

--operation mode is normal

KB1L399Q = DFFEAS(KB1L401, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--KB1L396 is std_1c20:inst|sdram:the_sdram|m_data[28]~COMB_OUT at LC_X16_Y16_N6

--operation mode is normal

KB1L396 = KB1L947 & (KB1L948 & (KB1L951) # !KB1L948 & KB1L394Q) # !KB1L947 & KB1L394Q;

--KB1L394Q is std_1c20:inst|sdram:the_sdram|m_data[28]~_Duplicate_1 at LC_X16_Y16_N6

--operation mode is normal

KB1L394Q = DFFEAS(KB1L396, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--KB1L391 is std_1c20:inst|sdram:the_sdram|m_data[27]~COMB_OUT at LC_X13_Y14_N2

--operation mode is normal

KB1L391 = KB1L948 & (KB1L947 & (KB1L952) # !KB1L947 & KB1L389Q) # !KB1L948 & KB1L389Q;

--KB1L389Q is std_1c20:inst|sdram:the_sdram|m_data[27]~_Duplicate_1 at LC_X13_Y14_N2

--operation mode is normal

KB1L389Q = DFFEAS(KB1L391, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--KB1L386 is std_1c20:inst|sdram:the_sdram|m_data[26]~COMB_OUT at LC_X16_Y15_N2

--operation mode is normal

KB1L386 = KB1L947 & (KB1L948 & (KB1L953) # !KB1L948 & KB1L384Q) # !KB1L947 & KB1L384Q;

--KB1L384Q is std_1c20:inst|sdram:the_sdram|m_data[26]~_Duplicate_1 at LC_X16_Y15_N2

--operation mode is normal

KB1L384Q = DFFEAS(KB1L386, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--KB1L381 is std_1c20:inst|sdram:the_sdram|m_data[25]~COMB_OUT at LC_X13_Y17_N4

--operation mode is normal

KB1L381 = KB1L947 & (KB1L948 & (KB1L954) # !KB1L948 & KB1L379Q) # !KB1L947 & KB1L379Q;

--KB1L379Q is std_1c20:inst|sdram:the_sdram|m_data[25]~_Duplicate_1 at LC_X13_Y17_N4

--operation mode is normal

KB1L379Q = DFFEAS(KB1L381, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--KB1L376 is std_1c20:inst|sdram:the_sdram|m_data[24]~COMB_OUT at LC_X18_Y15_N7

--operation mode is normal

KB1L376 = KB1L947 & (KB1L948 & (KB1L955) # !KB1L948 & KB1L374Q) # !KB1L947 & KB1L374Q;

--KB1L374Q is std_1c20:inst|sdram:the_sdram|m_data[24]~_Duplicate_1 at LC_X18_Y15_N7

--operation mode is normal

KB1L374Q = DFFEAS(KB1L376, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--KB1L371 is std_1c20:inst|sdram:the_sdram|m_data[23]~COMB_OUT at LC_X13_Y16_N2

--operation mode is normal

KB1L371 = KB1L947 & (KB1L948 & (KB1L956) # !KB1L948 & KB1L369Q) # !KB1L947 & KB1L369Q;

--KB1L369Q is std_1c20:inst|sdram:the_sdram|m_data[23]~_Duplicate_1 at LC_X13_Y16_N2

--operation mode is normal

KB1L369Q = DFFEAS(KB1L371, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--KB1L366 is std_1c20:inst|sdram:the_sdram|m_data[22]~COMB_OUT at LC_X16_Y16_N4

--operation mode is normal

KB1L366 = KB1L948 & (KB1L947 & (KB1L957) # !KB1L947 & KB1L364Q) # !KB1L948 & KB1L364Q;

--KB1L364Q is std_1c20:inst|sdram:the_sdram|m_data[22]~_Duplicate_1 at LC_X16_Y16_N4

--operation mode is normal

KB1L364Q = DFFEAS(KB1L366, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--KB1L361 is std_1c20:inst|sdram:the_sdram|m_data[21]~COMB_OUT at LC_X13_Y14_N9

--operation mode is normal

KB1L361 = KB1L948 & (KB1L947 & (KB1L958) # !KB1L947 & KB1L359Q) # !KB1L948 & KB1L359Q;

--KB1L359Q is std_1c20:inst|sdram:the_sdram|m_data[21]~_Duplicate_1 at LC_X13_Y14_N9

--operation mode is normal

KB1L359Q = DFFEAS(KB1L361, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--KB1L356 is std_1c20:inst|sdram:the_sdram|m_data[20]~COMB_OUT at LC_X16_Y15_N9

--operation mode is normal

KB1L356 = KB1L947 & (KB1L948 & (KB1L959) # !KB1L948 & KB1L354Q) # !KB1L947 & KB1L354Q;

--KB1L354Q is std_1c20:inst|sdram:the_sdram|m_data[20]~_Duplicate_1 at LC_X16_Y15_N9

--operation mode is normal

KB1L354Q = DFFEAS(KB1L356, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--KB1L351 is std_1c20:inst|sdram:the_sdram|m_data[19]~COMB_OUT at LC_X13_Y17_N8

--operation mode is normal

KB1L351 = KB1L947 & (KB1L948 & (KB1L960) # !KB1L948 & KB1L349Q) # !KB1L947 & KB1L349Q;

--KB1L349Q is std_1c20:inst|sdram:the_sdram|m_data[19]~_Duplicate_1 at LC_X13_Y17_N8

--operation mode is normal

KB1L349Q = DFFEAS(KB1L351, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--KB1L343Q is std_1c20:inst|sdram:the_sdram|m_data[18]~_Duplicate_1 at LC_X18_Y16_N0

--operation mode is normal

KB1L343Q_lut_out = KB1L948 & (KB1L947 & (KB1L961) # !KB1L947 & KB1L343Q) # !KB1L948 & KB1L343Q;

KB1L343Q = DFFEAS(KB1L343Q_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--KB1L340 is std_1c20:inst|sdram:the_sdram|m_data[17]~COMB_OUT at LC_X17_Y14_N9

--operation mode is normal

KB1L340 = KB1L947 & (KB1L948 & (KB1L962) # !KB1L948 & KB1L338Q) # !KB1L947 & KB1L338Q;

--KB1L338Q is std_1c20:inst|sdram:the_sdram|m_data[17]~_Duplicate_1 at LC_X17_Y14_N9

--operation mode is normal

KB1L338Q = DFFEAS(KB1L340, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--KB1L335 is std_1c20:inst|sdram:the_sdram|m_data[16]~COMB_OUT at LC_X17_Y16_N4

--operation mode is normal

KB1L335 = KB1L948 & (KB1L947 & (KB1L963) # !KB1L947 & KB1L333Q) # !KB1L948 & KB1L333Q;

--KB1L333Q is std_1c20:inst|sdram:the_sdram|m_data[16]~_Duplicate_1 at LC_X17_Y16_N4

--operation mode is normal

KB1L333Q = DFFEAS(KB1L335, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--KB1L330 is std_1c20:inst|sdram:the_sdram|m_data[15]~COMB_OUT at LC_X16_Y18_N2

--operation mode is normal

KB1L330 = KB1L947 & (KB1L948 & (KB1L964) # !KB1L948 & KB1L328Q) # !KB1L947 & KB1L328Q;

--KB1L328Q is std_1c20:inst|sdram:the_sdram|m_data[15]~_Duplicate_1 at LC_X16_Y18_N2

--operation mode is normal

KB1L328Q = DFFEAS(KB1L330, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--KB1L325 is std_1c20:inst|sdram:the_sdram|m_data[14]~COMB_OUT at LC_X17_Y17_N7

--operation mode is normal

KB1L325 = KB1L947 & (KB1L948 & (KB1L965) # !KB1L948 & KB1L323Q) # !KB1L947 & KB1L323Q;

--KB1L323Q is std_1c20:inst|sdram:the_sdram|m_data[14]~_Duplicate_1 at LC_X17_Y17_N7

--operation mode is normal

KB1L323Q = DFFEAS(KB1L325, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--KB1L320 is std_1c20:inst|sdram:the_sdram|m_data[13]~COMB_OUT at LC_X13_Y15_N3

--operation mode is normal

KB1L320 = KB1L948 & (KB1L947 & (KB1L966) # !KB1L947 & KB1L318Q) # !KB1L948 & KB1L318Q;

--KB1L318Q is std_1c20:inst|sdram:the_sdram|m_data[13]~_Duplicate_1 at LC_X13_Y15_N3

--operation mode is normal

KB1L318Q = DFFEAS(KB1L320, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--KB1L315 is std_1c20:inst|sdram:the_sdram|m_data[12]~COMB_OUT at LC_X17_Y16_N8

--operation mode is normal

KB1L315 = KB1L948 & (KB1L947 & (KB1L967) # !KB1L947 & KB1L313Q) # !KB1L948 & KB1L313Q;

--KB1L313Q is std_1c20:inst|sdram:the_sdram|m_data[12]~_Duplicate_1 at LC_X17_Y16_N8

--operation mode is normal

KB1L313Q = DFFEAS(KB1L315, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--KB1L310 is std_1c20:inst|sdram:the_sdram|m_data[11]~COMB_OUT at LC_X16_Y14_N2

--operation mode is normal

KB1L310 = KB1L947 & (KB1L948 & (KB1L968) # !KB1L948 & KB1L308Q) # !KB1L947 & KB1L308Q;

--KB1L308Q is std_1c20:inst|sdram:the_sdram|m_data[11]~_Duplicate_1 at LC_X16_Y14_N2

--operation mode is normal

KB1L308Q = DFFEAS(KB1L310, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--KB1L305 is std_1c20:inst|sdram:the_sdram|m_data[10]~COMB_OUT at LC_X17_Y15_N7

--operation mode is normal

KB1L305 = KB1L947 & (KB1L948 & (KB1L969) # !KB1L948 & KB1L303Q) # !KB1L947 & KB1L303Q;

--KB1L303Q is std_1c20:inst|sdram:the_sdram|m_data[10]~_Duplicate_1 at LC_X17_Y15_N7

--operation mode is normal

KB1L303Q = DFFEAS(KB1L305, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--KB1L300 is std_1c20:inst|sdram:the_sdram|m_data[9]~COMB_OUT at LC_X16_Y18_N9

--operation mode is normal

KB1L300 = KB1L947 & (KB1L948 & (KB1L970) # !KB1L948 & KB1L298Q) # !KB1L947 & KB1L298Q;

--KB1L298Q is std_1c20:inst|sdram:the_sdram|m_data[9]~_Duplicate_1 at LC_X16_Y18_N9

--operation mode is normal

KB1L298Q = DFFEAS(KB1L300, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--KB1L295 is std_1c20:inst|sdram:the_sdram|m_data[8]~COMB_OUT at LC_X17_Y17_N9

--operation mode is normal

KB1L295 = KB1L947 & (KB1L948 & (KB1L971) # !KB1L948 & KB1L293Q) # !KB1L947 & KB1L293Q;

--KB1L293Q is std_1c20:inst|sdram:the_sdram|m_data[8]~_Duplicate_1 at LC_X17_Y17_N9

--operation mode is normal

KB1L293Q = DFFEAS(KB1L295, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--KB1L290 is std_1c20:inst|sdram:the_sdram|m_data[7]~COMB_OUT at LC_X14_Y15_N2

--operation mode is normal

KB1L290 = KB1L948 & (KB1L947 & (KB1L972) # !KB1L947 & KB1L288Q) # !KB1L948 & KB1L288Q;

--KB1L288Q is std_1c20:inst|sdram:the_sdram|m_data[7]~_Duplicate_1 at LC_X14_Y15_N2

--operation mode is normal

KB1L288Q = DFFEAS(KB1L290, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--KB1L285 is std_1c20:inst|sdram:the_sdram|m_data[6]~COMB_OUT at LC_X17_Y15_N2

--operation mode is normal

KB1L285 = KB1L947 & (KB1L948 & (KB1L973) # !KB1L948 & KB1L283Q) # !KB1L947 & KB1L283Q;

--KB1L283Q is std_1c20:inst|sdram:the_sdram|m_data[6]~_Duplicate_1 at LC_X17_Y15_N2

--operation mode is normal

KB1L283Q = DFFEAS(KB1L285, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--KB1L280 is std_1c20:inst|sdram:the_sdram|m_data[5]~COMB_OUT at LC_X13_Y16_N9

--operation mode is normal

KB1L280 = KB1L947 & (KB1L948 & (KB1L974) # !KB1L948 & KB1L278Q) # !KB1L947 & KB1L278Q;

--KB1L278Q is std_1c20:inst|sdram:the_sdram|m_data[5]~_Duplicate_1 at LC_X13_Y16_N9

--operation mode is normal

KB1L278Q = DFFEAS(KB1L280, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--KB1L275 is std_1c20:inst|sdram:the_sdram|m_data[4]~COMB_OUT at LC_X17_Y15_N9

--operation mode is normal

KB1L275 = KB1L947 & (KB1L948 & (KB1L975) # !KB1L948 & KB1L274Q) # !KB1L947 & KB1L274Q;

--KB1L274Q is std_1c20:inst|sdram:the_sdram|m_data[4]~_Duplicate_1 at LC_X17_Y15_N9

--operation mode is normal

KB1L274Q = DFFEAS(KB1L275, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--KB1L271 is std_1c20:inst|sdram:the_sdram|m_data[3]~COMB_OUT at LC_X18_Y15_N9

--operation mode is normal

KB1L271 = KB1L947 & (KB1L948 & (KB1L976) # !KB1L948 & KB1L270Q) # !KB1L947 & KB1L270Q;

--KB1L270Q is std_1c20:inst|sdram:the_sdram|m_data[3]~_Duplicate_1 at LC_X18_Y15_N9

--operation mode is normal

KB1L270Q = DFFEAS(KB1L271, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--KB1L267 is std_1c20:inst|sdram:the_sdram|m_data[2]~COMB_OUT at LC_X15_Y17_N2

--operation mode is normal

KB1L267 = KB1L948 & (KB1L947 & (KB1L977) # !KB1L947 & KB1L265Q) # !KB1L948 & (KB1L265Q);

--KB1L265Q is std_1c20:inst|sdram:the_sdram|m_data[2]~_Duplicate_1 at LC_X15_Y17_N2

--operation mode is normal

KB1L265Q = DFFEAS(KB1L267, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--KB1L262 is std_1c20:inst|sdram:the_sdram|m_data[1]~COMB_OUT at LC_X16_Y17_N3

--operation mode is normal

KB1L262 = KB1L948 & (KB1L947 & (KB1L978) # !KB1L947 & KB1L260Q) # !KB1L948 & KB1L260Q;

--KB1L260Q is std_1c20:inst|sdram:the_sdram|m_data[1]~_Duplicate_1 at LC_X16_Y17_N3

--operation mode is normal

KB1L260Q = DFFEAS(KB1L262, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--KB1L257 is std_1c20:inst|sdram:the_sdram|m_data[0]~COMB_OUT at LC_X15_Y16_N2

--operation mode is normal

KB1L257 = KB1L947 & (KB1L948 & (KB1L979) # !KB1L948 & KB1L256Q) # !KB1L947 & KB1L256Q;

--KB1L256Q is std_1c20:inst|sdram:the_sdram|m_data[0]~_Duplicate_1 at LC_X15_Y16_N2

--operation mode is normal

KB1L256Q = DFFEAS(KB1L257, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--S1L1517 is std_1c20:inst|cpu:the_cpu|ic_fill_ap_cnt[2]~29 at LC_X26_Y25_N6

--operation mode is normal

S1L1517 = AMPP_FUNCTION(U1L10Q, U1L14Q, U1L12Q, S1L1520Q);

--S1L1510 is std_1c20:inst|cpu:the_cpu|ic_fill_ap_cnt[1]~27 at LC_X26_Y25_N7

--operation mode is normal

S1L1510 = AMPP_FUNCTION(U1L10Q, U1L14Q, U1L12Q, S1L1513Q);

--S1L1496 is std_1c20:inst|cpu:the_cpu|ic_fill_ap_cnt[0]~22 at LC_X26_Y24_N3

--operation mode is normal

S1L1496 = AMPP_FUNCTION(S1L1498Q, U1L14Q, S1L1500Q, S1_D_ic_fill_starting_d1);

--S1L1500Q is std_1c20:inst|cpu:the_cpu|ic_fill_ap_cnt[0]~25 at LC_X26_Y24_N3

--operation mode is normal

S1L1500Q = AMPP_FUNCTION(QC2__clk0, S1L1498Q, U1L14Q, S1L1500Q, S1_D_ic_fill_starting_d1, F1_data_out);

--S1L1527Q is std_1c20:inst|cpu:the_cpu|ic_fill_ap_cnt[3]~43 at LC_X26_Y24_N7

--operation mode is normal

S1L1527Q = AMPP_FUNCTION(QC2__clk0, S1L1518, S1L1511, S1L1526, S1L1496, F1_data_out);

--S1L1545 is std_1c20:inst|cpu:the_cpu|ic_fill_initial_offset[0]~807 at LC_X26_Y24_N9

--operation mode is normal

S1L1545 = AMPP_FUNCTION(U1L12Q, U1L10Q, U1L14Q, S1_D_ic_fill_starting_d1);

--V1L6 is std_1c20:inst|cpu_jtag_debug_module_arbitrator:the_cpu_jtag_debug_module|cpu_data_master_granted_cpu_jtag_debug_module~64 at LC_X38_Y21_N4

--operation mode is normal

V1L6 = S1L523 & (V1L39 # !V1L34Q & !S1L1451);

--V1L10 is std_1c20:inst|cpu_jtag_debug_module_arbitrator:the_cpu_jtag_debug_module|cpu_instruction_master_granted_cpu_jtag_debug_module~88 at LC_X35_Y24_N5

--operation mode is normal

V1L10 = S1L1451 & (V1L2 # !V1L34Q);

--V1L41Q is std_1c20:inst|cpu_jtag_debug_module_arbitrator:the_cpu_jtag_debug_module|cpu_jtag_debug_module_arb_addend[1]~761 at LC_X35_Y24_N5

--operation mode is normal

V1L41Q = DFFEAS(V1L10, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--V1L45 is std_1c20:inst|cpu_jtag_debug_module_arbitrator:the_cpu_jtag_debug_module|cpu_jtag_debug_module_arb_winner[0]~20 at LC_X34_Y24_N8

--operation mode is normal

V1_cpu_jtag_debug_module_saved_chosen_master_vector[0]_qfbk = V1_cpu_jtag_debug_module_saved_chosen_master_vector[0];

V1L45 = V1L40 # !V1L6 & V1_cpu_jtag_debug_module_saved_chosen_master_vector[0]_qfbk;

--V1_cpu_jtag_debug_module_saved_chosen_master_vector[0] is std_1c20:inst|cpu_jtag_debug_module_arbitrator:the_cpu_jtag_debug_module|cpu_jtag_debug_module_saved_chosen_master_vector[0] at LC_X34_Y24_N8

--operation mode is normal

V1_cpu_jtag_debug_module_saved_chosen_master_vector[0] = DFFEAS(V1L45, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--X1L12 is std_1c20:inst|epcs_controller_epcs_control_port_arbitrator:the_epcs_controller_epcs_control_port|cpu_instruction_master_read_data_valid_epcs_controller_epcs_control_port~17 at LC_X33_Y24_N6

--operation mode is normal

X1L12 = !V1L58 & X1L16;

--U1L140 is std_1c20:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_readdatavalid~147 at LC_X34_Y24_N0

--operation mode is normal

U1L140 = S1L1593Q & (V1L13 & (V1L2 # !V1L34Q) # !V1L13 & (V1L34Q # !V1L2));

--V1L51 is std_1c20:inst|cpu_jtag_debug_module_arbitrator:the_cpu_jtag_debug_module|cpu_jtag_debug_module_end_xfer~41 at LC_X34_Y24_N1

--operation mode is normal

V1L51 = X1L12 & (U1L140 # S1L1686Q & V1L6) # !X1L12 & S1L1686Q & V1L6;

--V1L46 is std_1c20:inst|cpu_jtag_debug_module_arbitrator:the_cpu_jtag_debug_module|cpu_jtag_debug_module_begintransfer~58 at LC_X35_Y24_N9

--operation mode is normal

V1L46 = !V1_d1_reasons_to_wait & (S1L1451 # K1L3 & V1L8);

--V1L42Q is std_1c20:inst|cpu_jtag_debug_module_arbitrator:the_cpu_jtag_debug_module|cpu_jtag_debug_module_arb_addend[1]~762 at LC_X35_Y24_N0

--operation mode is normal

V1L42Q_lut_out = V1L6 & (V1L45 # V1L46 & V1L51);

V1L42Q = DFFEAS(V1L42Q_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--V1L52 is std_1c20:inst|cpu_jtag_debug_module_arbitrator:the_cpu_jtag_debug_module|cpu_jtag_debug_module_end_xfer~42 at LC_X35_Y24_N3

--operation mode is normal

V1L52 = V1L46 & V1L51;

--V1_d1_reasons_to_wait is std_1c20:inst|cpu_jtag_debug_module_arbitrator:the_cpu_jtag_debug_module|d1_reasons_to_wait at LC_X35_Y24_N3

--operation mode is normal

V1_d1_reasons_to_wait = DFFEAS(V1L52, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--V1L29 is std_1c20:inst|cpu_jtag_debug_module_arbitrator:the_cpu_jtag_debug_module|cpu_jtag_debug_module_arb_addend[0]~747 at LC_X34_Y24_N3

--operation mode is normal

V1L29 = V1L45 # V1L51 & V1L46 # !V1L6;

--V1L33Q is std_1c20:inst|cpu_jtag_debug_module_arbitrator:the_cpu_jtag_debug_module|cpu_jtag_debug_module_arb_addend[0]~757 at LC_X34_Y24_N3

--operation mode is normal

V1L33Q = DFFEAS(V1L29, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--X1L4 is std_1c20:inst|epcs_controller_epcs_control_port_arbitrator:the_epcs_controller_epcs_control_port|cpu_data_master_granted_epcs_controller_epcs_control_port~33 at LC_X33_Y23_N8

--operation mode is normal

X1L4 = X1_cpu_data_master_requests_epcs_controller_epcs_control_port & (X1_epcs_controller_epcs_control_port_arb_addend[1] # !X1_epcs_controller_epcs_control_port_arb_addend[0] & !X1L10);

--X1L8 is std_1c20:inst|epcs_controller_epcs_control_port_arbitrator:the_epcs_controller_epcs_control_port|cpu_instruction_master_granted_epcs_controller_epcs_control_port~91 at LC_X33_Y23_N5

--operation mode is normal

X1L8 = X1L10 & (X1_epcs_controller_epcs_control_port_arb_addend[1] & !X1_cpu_data_master_requests_epcs_controller_epcs_control_port # !X1_epcs_controller_epcs_control_port_arb_addend[0]);

--X1_epcs_controller_epcs_control_port_saved_chosen_master_vector[0] is std_1c20:inst|epcs_controller_epcs_control_port_arbitrator:the_epcs_controller_epcs_control_port|epcs_controller_epcs_control_port_saved_chosen_master_vector[0] at LC_X35_Y23_N6

--operation mode is normal

X1_epcs_controller_epcs_control_port_saved_chosen_master_vector[0]_lut_out = X1L8 # X1_epcs_controller_epcs_control_port_saved_chosen_master_vector[0] & (!X1L4);

X1_epcs_controller_epcs_control_port_saved_chosen_master_vector[0] = DFFEAS(X1_epcs_controller_epcs_control_port_saved_chosen_master_vector[0]_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--X1L45 is std_1c20:inst|epcs_controller_epcs_control_port_arbitrator:the_epcs_controller_epcs_control_port|epcs_controller_epcs_control_port_in_a_read_cycle~0 at LC_X35_Y27_N5

--operation mode is normal

X1L45 = X1L4 & S1_internal_d_read;

--X1L44 is std_1c20:inst|epcs_controller_epcs_control_port_arbitrator:the_epcs_controller_epcs_control_port|epcs_controller_epcs_control_port_end_xfer~21 at LC_X33_Y23_N7

--operation mode is normal

X1L44 = X1L27 & (X1L25 # !X1L23 & X1L4);

--X1_d1_reasons_to_wait is std_1c20:inst|epcs_controller_epcs_control_port_arbitrator:the_epcs_controller_epcs_control_port|d1_reasons_to_wait at LC_X33_Y23_N7

--operation mode is normal

X1_d1_reasons_to_wait = DFFEAS(X1L44, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--NB1L80 is std_1c20:inst|sdram_s1_arbitrator:the_sdram_s1|sdram_s1_arb_share_counter_next_value[5]~577 at LC_X23_Y22_N6

--operation mode is normal

NB1L80 = NB1_sdram_s1_slavearbiterlockenable & (NB1L19 # NB1L79);

--NB1L81 is std_1c20:inst|sdram_s1_arbitrator:the_sdram_s1|sdram_s1_arb_winner[0]~34 at LC_X23_Y23_N1

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

NB1_sdram_s1_saved_chosen_master_vector[0]_qfbk = NB1_sdram_s1_saved_chosen_master_vector[0];

NB1L81 = NB1L80 & (NB1_sdram_s1_saved_chosen_master_vector[0]_qfbk) # !NB1L80 & (NB1L24 # !NB1L20 & NB1_sdram_s1_saved_chosen_master_vector[0]_qfbk);

--NB1_sdram_s1_saved_chosen_master_vector[0] is std_1c20:inst|sdram_s1_arbitrator:the_sdram_s1|sdram_s1_saved_chosen_master_vector[0] at LC_X23_Y23_N1

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

NB1_sdram_s1_saved_chosen_master_vector[0] = DFFEAS(NB1L81, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , NB1L82, NB1L24, , , VCC);

--NB1L65 is std_1c20:inst|sdram_s1_arbitrator:the_sdram_s1|sdram_s1_arb_addend[1]~735 at LC_X23_Y23_N6

--operation mode is normal

NB1L65 = KB1L477 & (TE1L151 & NB1L20 # !TE1L151 & (NB1L81)) # !KB1L477 & (NB1L81);

--NB1_WideOr1 is std_1c20:inst|sdram_s1_arbitrator:the_sdram_s1|WideOr1 at LC_X23_Y22_N0

--operation mode is normal

NB1_WideOr1 = NB1_sdram_s1_arb_addend[0] & NB1_sdram_s1_arb_addend[1] & (NB1L22 # NB1L25) # !NB1_sdram_s1_arb_addend[0] & (NB1L22 # NB1L25);

--VE1L49 is std_1c20:inst|sdram_s1_arbitrator:the_sdram_s1|rdv_fifo_for_cpu_data_master_to_sdram_s1_module:rdv_fifo_for_cpu_data_master_to_sdram_s1|updated_one_count~70 at LC_X24_Y23_N4

--operation mode is normal

VE1L49 = !TE1L151 & (VE1L54 $ (!NB1L25 & VE1L52));

--VE1L50 is std_1c20:inst|sdram_s1_arbitrator:the_sdram_s1|rdv_fifo_for_cpu_data_master_to_sdram_s1_module:rdv_fifo_for_cpu_data_master_to_sdram_s1|updated_one_count~71 at LC_X24_Y24_N1

--operation mode is normal

VE1L50 = KB1_za_valid & VE1L24Q;

--VE1L1 is std_1c20:inst|sdram_s1_arbitrator:the_sdram_s1|rdv_fifo_for_cpu_data_master_to_sdram_s1_module:rdv_fifo_for_cpu_data_master_to_sdram_s1|A_WE_StdLogicVector~1206 at LC_X23_Y24_N6

--operation mode is normal

VE1L1 = VE1L50 & !VE1_how_many_ones[1] & !VE1_how_many_ones[0] & !VE1_how_many_ones[2] # !VE1L50 & VE1_how_many_ones[1] & VE1_how_many_ones[0] & VE1_how_many_ones[2];

--VE1L2 is std_1c20:inst|sdram_s1_arbitrator:the_sdram_s1|rdv_fifo_for_cpu_data_master_to_sdram_s1_module:rdv_fifo_for_cpu_data_master_to_sdram_s1|A_WE_StdLogicVector~1207 at LC_X23_Y24_N2

--operation mode is normal

VE1_how_many_ones[3]_qfbk = VE1_how_many_ones[3];

VE1L2 = VE1_how_many_ones[3]_qfbk $ (VE1L1 & (VE1_how_many_ones[2] $ !VE1L49));

--VE1_how_many_ones[3] is std_1c20:inst|sdram_s1_arbitrator:the_sdram_s1|rdv_fifo_for_cpu_data_master_to_sdram_s1_module:rdv_fifo_for_cpu_data_master_to_sdram_s1|how_many_ones[3] at LC_X23_Y24_N2

--operation mode is normal

VE1_how_many_ones[3] = DFFEAS(VE1L2, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , WE1L33, , , , );

--VE1L3 is std_1c20:inst|sdram_s1_arbitrator:the_sdram_s1|rdv_fifo_for_cpu_data_master_to_sdram_s1_module:rdv_fifo_for_cpu_data_master_to_sdram_s1|A_WE_StdLogicVector~1208 at LC_X23_Y24_N7

--operation mode is normal

VE1_how_many_ones[2]_qfbk = VE1_how_many_ones[2];

VE1L3 = VE1_how_many_ones[2]_qfbk $ (VE1L5 & (VE1_how_many_ones[1] $ !VE1L49));

--VE1_how_many_ones[2] is std_1c20:inst|sdram_s1_arbitrator:the_sdram_s1|rdv_fifo_for_cpu_data_master_to_sdram_s1_module:rdv_fifo_for_cpu_data_master_to_sdram_s1|how_many_ones[2] at LC_X23_Y24_N7

--operation mode is normal

VE1_how_many_ones[2] = DFFEAS(VE1L3, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , WE1L33, , , , );

--VE1L4 is std_1c20:inst|sdram_s1_arbitrator:the_sdram_s1|rdv_fifo_for_cpu_data_master_to_sdram_s1_module:rdv_fifo_for_cpu_data_master_to_sdram_s1|A_WE_StdLogicVector~1209 at LC_X23_Y24_N3

--operation mode is normal

VE1_how_many_ones[1]_qfbk = VE1_how_many_ones[1];

VE1L4 = VE1_how_many_ones[1]_qfbk $ (VE1_how_many_ones[0] & VE1L49 & !VE1L50 # !VE1_how_many_ones[0] & !VE1L49 & VE1L50);

--VE1_how_many_ones[1] is std_1c20:inst|sdram_s1_arbitrator:the_sdram_s1|rdv_fifo_for_cpu_data_master_to_sdram_s1_module:rdv_fifo_for_cpu_data_master_to_sdram_s1|how_many_ones[1] at LC_X23_Y24_N3

--operation mode is normal

VE1_how_many_ones[1] = DFFEAS(VE1L4, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , WE1L33, , , , );

--NB1L3 is std_1c20:inst|sdram_s1_arbitrator:the_sdram_s1|Add1~100 at LC_X22_Y21_N1

--operation mode is arithmetic

NB1L3_cout_0 = NB1_sdram_s1_arb_share_counter[0];

NB1L3 = CARRY(NB1L3_cout_0);

--NB1L4 is std_1c20:inst|sdram_s1_arbitrator:the_sdram_s1|Add1~100COUT1_307 at LC_X22_Y21_N1

--operation mode is arithmetic

NB1L4_cout_1 = NB1_sdram_s1_arb_share_counter[0];

NB1L4 = CARRY(NB1L4_cout_1);

--NB1_sdram_s1_arb_share_counter[3] is std_1c20:inst|sdram_s1_arbitrator:the_sdram_s1|sdram_s1_arb_share_counter[3] at LC_X22_Y21_N0

--operation mode is normal

NB1_sdram_s1_arb_share_counter[3]_lut_out = NB1L76 & NB1L14;

NB1_sdram_s1_arb_share_counter[3] = DFFEAS(NB1_sdram_s1_arb_share_counter[3]_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , NB1L67, , , , );

--NB1L94 is std_1c20:inst|sdram_s1_arbitrator:the_sdram_s1|WideOr0~28 at LC_X23_Y21_N3

--operation mode is normal

NB1L94 = NB1_sdram_s1_arb_share_counter[1] # NB1_sdram_s1_arb_share_counter[3] # NB1_sdram_s1_arb_share_counter[2] # NB1_sdram_s1_arb_share_counter[0];

--NB1_sdram_s1_arb_share_counter[4] is std_1c20:inst|sdram_s1_arbitrator:the_sdram_s1|sdram_s1_arb_share_counter[4] at LC_X22_Y21_N8

--operation mode is normal

NB1_sdram_s1_arb_share_counter[4]_lut_out = NB1L76 & (NB1L11);

NB1_sdram_s1_arb_share_counter[4] = DFFEAS(NB1_sdram_s1_arb_share_counter[4]_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , NB1L67, , , , );

--NB1_sdram_s1_arb_share_counter[5] is std_1c20:inst|sdram_s1_arbitrator:the_sdram_s1|sdram_s1_arb_share_counter[5] at LC_X22_Y21_N7

--operation mode is normal

NB1_sdram_s1_arb_share_counter[5]_lut_out = NB1L76 & (NB1L18);

NB1_sdram_s1_arb_share_counter[5] = DFFEAS(NB1_sdram_s1_arb_share_counter[5]_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , NB1L67, , , , );

--NB1_WideOr0 is std_1c20:inst|sdram_s1_arbitrator:the_sdram_s1|WideOr0 at LC_X23_Y21_N7

--operation mode is normal

NB1_WideOr0 = NB1L94 # NB1_sdram_s1_arb_share_counter[4] # NB1_sdram_s1_arb_share_counter[5];

--NB1L75 is std_1c20:inst|sdram_s1_arbitrator:the_sdram_s1|sdram_s1_arb_share_counter_next_value[0]~578 at LC_X23_Y21_N8

--operation mode is normal

NB1L75 = NB1L80 & !NB1_sdram_s1_arb_share_counter[0] & (NB1_WideOr0) # !NB1L80 & (WE1L62);

--NB1_sdram_s1_arb_share_counter[0] is std_1c20:inst|sdram_s1_arbitrator:the_sdram_s1|sdram_s1_arb_share_counter[0] at LC_X23_Y21_N8

--operation mode is normal

NB1_sdram_s1_arb_share_counter[0] = DFFEAS(NB1L75, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , NB1L67, , , , );

--NB1L5 is std_1c20:inst|sdram_s1_arbitrator:the_sdram_s1|Add1~101 at LC_X22_Y21_N2

--operation mode is arithmetic

NB1L5 = NB1_sdram_s1_arb_share_counter[1] $ !NB1L3;

--NB1L6 is std_1c20:inst|sdram_s1_arbitrator:the_sdram_s1|Add1~102 at LC_X22_Y21_N2

--operation mode is arithmetic

NB1L6_cout_0 = !NB1_sdram_s1_arb_share_counter[1] & !NB1L3;

NB1L6 = CARRY(NB1L6_cout_0);

--NB1L7 is std_1c20:inst|sdram_s1_arbitrator:the_sdram_s1|Add1~102COUT1_309 at LC_X22_Y21_N2

--operation mode is arithmetic

NB1L7_cout_1 = !NB1_sdram_s1_arb_share_counter[1] & !NB1L4;

NB1L7 = CARRY(NB1L7_cout_1);

--NB1L77 is std_1c20:inst|sdram_s1_arbitrator:the_sdram_s1|sdram_s1_arb_share_counter_next_value[1]~579 at LC_X23_Y21_N0

--operation mode is normal

NB1L77 = NB1L80 & NB1_WideOr0 & NB1L5 # !NB1L80 & (WE1L62);

--NB1_sdram_s1_arb_share_counter[1] is std_1c20:inst|sdram_s1_arbitrator:the_sdram_s1|sdram_s1_arb_share_counter[1] at LC_X23_Y21_N0

--operation mode is normal

NB1_sdram_s1_arb_share_counter[1] = DFFEAS(NB1L77, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , NB1L67, , , , );

--NB1L8 is std_1c20:inst|sdram_s1_arbitrator:the_sdram_s1|Add1~103 at LC_X22_Y21_N3

--operation mode is arithmetic

NB1L8 = NB1_sdram_s1_arb_share_counter[2] $ (NB1L6);

--NB1L9 is std_1c20:inst|sdram_s1_arbitrator:the_sdram_s1|Add1~104 at LC_X22_Y21_N3

--operation mode is arithmetic

NB1L9_cout_0 = NB1_sdram_s1_arb_share_counter[2] # !NB1L6;

NB1L9 = CARRY(NB1L9_cout_0);

--NB1L10 is std_1c20:inst|sdram_s1_arbitrator:the_sdram_s1|Add1~104COUT1_311 at LC_X22_Y21_N3

--operation mode is arithmetic

NB1L10_cout_1 = NB1_sdram_s1_arb_share_counter[2] # !NB1L7;

NB1L10 = CARRY(NB1L10_cout_1);

--NB1L78 is std_1c20:inst|sdram_s1_arbitrator:the_sdram_s1|sdram_s1_arb_share_counter_next_value[2]~580 at LC_X23_Y21_N2

--operation mode is normal

NB1L78 = NB1L80 & NB1_WideOr0 & (NB1L8) # !NB1L80 & (WE1L62);

--NB1_sdram_s1_arb_share_counter[2] is std_1c20:inst|sdram_s1_arbitrator:the_sdram_s1|sdram_s1_arb_share_counter[2] at LC_X23_Y21_N2

--operation mode is normal

NB1_sdram_s1_arb_share_counter[2] = DFFEAS(NB1L78, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , NB1L67, , , , );

--NB1L76 is std_1c20:inst|sdram_s1_arbitrator:the_sdram_s1|sdram_s1_arb_share_counter_next_value[0]~581 at LC_X23_Y22_N9

--operation mode is normal

NB1L76 = NB1_sdram_s1_slavearbiterlockenable & NB1_WideOr0 & (NB1L19 # NB1L79);

--NB1L11 is std_1c20:inst|sdram_s1_arbitrator:the_sdram_s1|Add1~105 at LC_X22_Y21_N5

--operation mode is arithmetic

NB1L11_carry_eqn = (!NB1L15 & GND) # (NB1L15 & VCC);

NB1L11 = NB1_sdram_s1_arb_share_counter[4] $ NB1L11_carry_eqn;

--NB1L12 is std_1c20:inst|sdram_s1_arbitrator:the_sdram_s1|Add1~106 at LC_X22_Y21_N5

--operation mode is arithmetic

NB1L12_cout_0 = NB1_sdram_s1_arb_share_counter[4] # !NB1L15;

NB1L12 = CARRY(NB1L12_cout_0);

--NB1L13 is std_1c20:inst|sdram_s1_arbitrator:the_sdram_s1|Add1~106COUT1_313 at LC_X22_Y21_N5

--operation mode is arithmetic

NB1L13_cout_1 = NB1_sdram_s1_arb_share_counter[4] # !NB1L15;

NB1L13 = CARRY(NB1L13_cout_1);

--NB1L14 is std_1c20:inst|sdram_s1_arbitrator:the_sdram_s1|Add1~107 at LC_X22_Y21_N4

--operation mode is arithmetic

NB1L14 = NB1_sdram_s1_arb_share_counter[3] $ !NB1L9;

--NB1L15 is std_1c20:inst|sdram_s1_arbitrator:the_sdram_s1|Add1~108 at LC_X22_Y21_N4

--operation mode is arithmetic

NB1L15 = NB1L16;

--NB1L18 is std_1c20:inst|sdram_s1_arbitrator:the_sdram_s1|Add1~109 at LC_X22_Y21_N6

--operation mode is normal

NB1L18_carry_eqn = (!NB1L15 & NB1L12) # (NB1L15 & NB1L13);

NB1L18 = NB1_sdram_s1_arb_share_counter[5] $ (!NB1L18_carry_eqn);

--NB1L90 is std_1c20:inst|sdram_s1_arbitrator:the_sdram_s1|sdram_s1_slavearbiterlockenable~156 at LC_X22_Y21_N9

--operation mode is normal

NB1L90 = NB1L76 & (NB1L18 # NB1L14 # NB1L11);

--NB1L91 is std_1c20:inst|sdram_s1_arbitrator:the_sdram_s1|sdram_s1_slavearbiterlockenable~157 at LC_X23_Y21_N5

--operation mode is normal

NB1L91 = NB1L78 # NB1L90 # NB1L75 # NB1L77;

--NB1L38 is std_1c20:inst|sdram_s1_arbitrator:the_sdram_s1|process2~55 at LC_X23_Y22_N1

--operation mode is normal

NB1L38 = NB1L22 # NB1L27 & !NB1L30 # !NB1L27 & (!S1L1693Q);

--NB1L83 is std_1c20:inst|sdram_s1_arbitrator:the_sdram_s1|sdram_s1_arbitration_holdoff_internal~152 at LC_X23_Y22_N7

--operation mode is normal

NB1L83 = !NB1_d1_reasons_to_wait & !NB1L80 & (NB1L22 # NB1L25);

--NB1L1 is std_1c20:inst|sdram_s1_arbitrator:the_sdram_s1|A_WE_StdLogicVector~132 at LC_X23_Y23_N9

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

NB1_sdram_s1_saved_chosen_master_vector[1]_qfbk = NB1_sdram_s1_saved_chosen_master_vector[1];

NB1L1 = NB1L80 & (NB1_sdram_s1_saved_chosen_master_vector[1]_qfbk) # !NB1L80 & (NB1L20 # !NB1L24 & NB1_sdram_s1_saved_chosen_master_vector[1]_qfbk);

--NB1_sdram_s1_saved_chosen_master_vector[1] is std_1c20:inst|sdram_s1_arbitrator:the_sdram_s1|sdram_s1_saved_chosen_master_vector[1] at LC_X23_Y23_N9

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

NB1_sdram_s1_saved_chosen_master_vector[1] = DFFEAS(NB1L1, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , NB1L82, NB1L20, , , VCC);

--NB1L63 is std_1c20:inst|sdram_s1_arbitrator:the_sdram_s1|sdram_s1_arb_addend[0]~737 at LC_X23_Y23_N8

--operation mode is normal

NB1L63 = TE1L151 & (KB1L477 & (NB1L24) # !KB1L477 & !NB1L81) # !TE1L151 & !NB1L81;

--S1L1177 is std_1c20:inst|cpu:the_cpu|Equal53~860 at LC_X28_Y15_N4

--operation mode is normal

S1L1177 = AMPP_FUNCTION(S1_D_iw[2], S1_D_iw[3], S1_D_iw[0], S1_D_iw[1]);

--S1L240 is std_1c20:inst|cpu:the_cpu|D_br_pred_taken~36 at LC_X28_Y15_N3

--operation mode is normal

S1L240 = AMPP_FUNCTION(S1_D_iw[21], S1L288, S1L1177, S1L274);

--S1_D_refetch is std_1c20:inst|cpu:the_cpu|D_refetch at LC_X25_Y18_N0

--operation mode is normal

S1_D_refetch = AMPP_FUNCTION(S1_D_kill, S1L331);

--S1_F_kill is std_1c20:inst|cpu:the_cpu|F_kill at LC_X25_Y18_N2

--operation mode is normal

S1_F_kill = AMPP_FUNCTION(S1_M_pipe_flush, S1_D_refetch, S1L343, S1L240);

--S1_D_kill is std_1c20:inst|cpu:the_cpu|D_kill at LC_X25_Y18_N2

--operation mode is normal

S1_D_kill = AMPP_FUNCTION(QC2__clk0, S1_M_pipe_flush, S1_D_refetch, S1L343, S1L240, F1_data_out, S1_W_stall);

--S1_F_pc[12] is std_1c20:inst|cpu:the_cpu|F_pc[12] at LC_X27_Y20_N4

--operation mode is normal

S1_F_pc[12] = AMPP_FUNCTION(QC2__clk0, S1L35, S1_D_pc[12], S1_M_pipe_flush_waddr[12], S1_D_refetch, F1_data_out, !S1_M_pipe_flush, S1_W_stall);

--S1_F_pc[16] is std_1c20:inst|cpu:the_cpu|F_pc[16] at LC_X27_Y20_N2

--operation mode is normal

S1_F_pc[16] = AMPP_FUNCTION(QC2__clk0, S1_D_pc[16], S1L36, S1_M_pipe_flush_waddr[16], S1_D_refetch, F1_data_out, !S1_M_pipe_flush, S1_W_stall);

--BD1_q_b[14] is std_1c20:inst|cpu:the_cpu|cpu_ic_tag_module:cpu_ic_tag|altsyncram:the_altsyncram|altsyncram_09e1:auto_generated|q_b[14] at M4K_X19_Y20

--RAM Block Operation Mode: Simple Dual-Port

--Port A Depth: 128, Port A Width: 22, Port B Depth: 128, Port B Width: 22

--Port A Logical Depth: 128, Port A Logical Width: 22, Port B Logical Depth: 128, Port B Logical Width: 22

--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered

BD1_q_b[14] = AMPP_FUNCTION(GND, GND, QC2__clk0, QC2__clk0, S1_ic_tag_wren, S1_W_stall, S1_ic_fill_tag[6], S1_ic_tag_wraddress[0], S1_ic_tag_wraddress[1], S1_ic_tag_wraddress[2], S1_ic_tag_wraddress[3], S1_ic_tag_wraddress[4], S1_ic_tag_wraddress[5], S1_ic_tag_wraddress[6], S1L1233, S1L1236, S1L1239, S1L1242, S1L1245, S1L1248, S1L1251, S1L1580Q, S1_ic_fill_tag[9], S1_ic_fill_tag[10], S1_ic_fill_tag[7], S1L1609Q, S1L1587Q, S1L1633Q, S1L1636Q, S1L1577Q, S1L1593Q, S1L1642Q, S1L1568Q, S1L1583Q, S1_ic_fill_valid_bits[5], S1_ic_fill_valid_bits[3], S1_ic_fill_valid_bits[1], S1_ic_fill_valid_bits[7], S1_ic_fill_valid_bits[2], S1_ic_fill_valid_bits[4], S1_ic_fill_valid_bits[0], S1_ic_fill_valid_bits[6]);

--BD1_q_b[6] is std_1c20:inst|cpu:the_cpu|cpu_ic_tag_module:cpu_ic_tag|altsyncram:the_altsyncram|altsyncram_09e1:auto_generated|q_b[6] at M4K_X19_Y20

BD1_q_b[6] = AMPP_FUNCTION(GND, GND, QC2__clk0, QC2__clk0, S1_ic_tag_wren, S1_W_stall, S1_ic_fill_tag[6], S1_ic_tag_wraddress[0], S1_ic_tag_wraddress[1], S1_ic_tag_wraddress[2], S1_ic_tag_wraddress[3], S1_ic_tag_wraddress[4], S1_ic_tag_wraddress[5], S1_ic_tag_wraddress[6], S1L1233, S1L1236, S1L1239, S1L1242, S1L1245, S1L1248, S1L1251, S1L1580Q, S1_ic_fill_tag[9], S1_ic_fill_tag[10], S1_ic_fill_tag[7], S1L1609Q, S1L1587Q, S1L1633Q, S1L1636Q, S1L1577Q, S1L1593Q, S1L1642Q, S1L1568Q, S1L1583Q, S1_ic_fill_valid_bits[5], S1_ic_fill_valid_bits[3], S1_ic_fill_valid_bits[1], S1_ic_fill_valid_bits[7], S1_ic_fill_valid_bits[2], S1_ic_fill_valid_bits[4], S1_ic_fill_valid_bits[0], S1_ic_fill_valid_bits[6]);

--BD1_q_b[0] is std_1c20:inst|cpu:the_cpu|cpu_ic_tag_module:cpu_ic_tag|altsyncram:the_altsyncram|altsyncram_09e1:auto_generated|q_b[0] at M4K_X19_Y20

BD1_q_b[0] = AMPP_FUNCTION(GND, GND, QC2__clk0, QC2__clk0, S1_ic_tag_wren, S1_W_stall, S1_ic_fill_tag[6], S1_ic_tag_wraddress[0], S1_ic_tag_wraddress[1], S1_ic_tag_wraddress[2], S1_ic_tag_wraddress[3], S1_ic_tag_wraddress[4], S1_ic_tag_wraddress[5], S1_ic_tag_wraddress[6], S1L1233, S1L1236, S1L1239, S1L1242, S1L1245, S1L1248, S1L1251, S1L1580Q, S1_ic_fill_tag[9], S1_ic_fill_tag[10], S1_ic_fill_tag[7], S1L1609Q, S1L1587Q, S1L1633Q, S1L1636Q, S1L1577Q, S1L1593Q, S1L1642Q, S1L1568Q, S1L1583Q, S1_ic_fill_valid_bits[5], S1_ic_fill_valid_bits[3], S1_ic_fill_valid_bits[1], S1_ic_fill_valid_bits[7], S1_ic_fill_valid_bits[2], S1_ic_fill_valid_bits[4], S1_ic_fill_valid_bits[0], S1_ic_fill_valid_bits[6]);

--BD1_q_b[4] is std_1c20:inst|cpu:the_cpu|cpu_ic_tag_module:cpu_ic_tag|altsyncram:the_altsyncram|altsyncram_09e1:auto_generated|q_b[4] at M4K_X19_Y20

BD1_q_b[4] = AMPP_FUNCTION(GND, GND, QC2__clk0, QC2__clk0, S1_ic_tag_wren, S1_W_stall, S1_ic_fill_tag[6], S1_ic_tag_wraddress[0], S1_ic_tag_wraddress[1], S1_ic_tag_wraddress[2], S1_ic_tag_wraddress[3], S1_ic_tag_wraddress[4], S1_ic_tag_wraddress[5], S1_ic_tag_wraddress[6], S1L1233, S1L1236, S1L1239, S1L1242, S1L1245, S1L1248, S1L1251, S1L1580Q, S1_ic_fill_tag[9], S1_ic_fill_tag[10], S1_ic_fill_tag[7], S1L1609Q, S1L1587Q, S1L1633Q, S1L1636Q, S1L1577Q, S1L1593Q, S1L1642Q, S1L1568Q, S1L1583Q, S1_ic_fill_valid_bits[5], S1_ic_fill_valid_bits[3], S1_ic_fill_valid_bits[1], S1_ic_fill_valid_bits[7], S1_ic_fill_valid_bits[2], S1_ic_fill_valid_bits[4], S1_ic_fill_valid_bits[0], S1_ic_fill_valid_bits[6]);

--BD1_q_b[2] is std_1c20:inst|cpu:the_cpu|cpu_ic_tag_module:cpu_ic_tag|altsyncram:the_altsyncram|altsyncram_09e1:auto_generated|q_b[2] at M4K_X19_Y20

BD1_q_b[2] = AMPP_FUNCTION(GND, GND, QC2__clk0, QC2__clk0, S1_ic_tag_wren, S1_W_stall, S1_ic_fill_tag[6], S1_ic_tag_wraddress[0], S1_ic_tag_wraddress[1], S1_ic_tag_wraddress[2], S1_ic_tag_wraddress[3], S1_ic_tag_wraddress[4], S1_ic_tag_wraddress[5], S1_ic_tag_wraddress[6], S1L1233, S1L1236, S1L1239, S1L1242, S1L1245, S1L1248, S1L1251, S1L1580Q, S1_ic_fill_tag[9], S1_ic_fill_tag[10], S1_ic_fill_tag[7], S1L1609Q, S1L1587Q, S1L1633Q, S1L1636Q, S1L1577Q, S1L1593Q, S1L1642Q, S1L1568Q, S1L1583Q, S1_ic_fill_valid_bits[5], S1_ic_fill_valid_bits[3], S1_ic_fill_valid_bits[1], S1_ic_fill_valid_bits[7], S1_ic_fill_valid_bits[2], S1_ic_fill_valid_bits[4], S1_ic_fill_valid_bits[0], S1_ic_fill_valid_bits[6]);

--BD1_q_b[7] is std_1c20:inst|cpu:the_cpu|cpu_ic_tag_module:cpu_ic_tag|altsyncram:the_altsyncram|altsyncram_09e1:auto_generated|q_b[7] at M4K_X19_Y20

BD1_q_b[7] = AMPP_FUNCTION(GND, GND, QC2__clk0, QC2__clk0, S1_ic_tag_wren, S1_W_stall, S1_ic_fill_tag[6], S1_ic_tag_wraddress[0], S1_ic_tag_wraddress[1], S1_ic_tag_wraddress[2], S1_ic_tag_wraddress[3], S1_ic_tag_wraddress[4], S1_ic_tag_wraddress[5], S1_ic_tag_wraddress[6], S1L1233, S1L1236, S1L1239, S1L1242, S1L1245, S1L1248, S1L1251, S1L1580Q, S1_ic_fill_tag[9], S1_ic_fill_tag[10], S1_ic_fill_tag[7], S1L1609Q, S1L1587Q, S1L1633Q, S1L1636Q, S1L1577Q, S1L1593Q, S1L1642Q, S1L1568Q, S1L1583Q, S1_ic_fill_valid_bits[5], S1_ic_fill_valid_bits[3], S1_ic_fill_valid_bits[1], S1_ic_fill_valid_bits[7], S1_ic_fill_valid_bits[2], S1_ic_fill_valid_bits[4], S1_ic_fill_valid_bits[0], S1_ic_fill_valid_bits[6]);

--BD1_q_b[1] is std_1c20:inst|cpu:the_cpu|cpu_ic_tag_module:cpu_ic_tag|altsyncram:the_altsyncram|altsyncram_09e1:auto_generated|q_b[1] at M4K_X19_Y20

BD1_q_b[1] = AMPP_FUNCTION(GND, GND, QC2__clk0, QC2__clk0, S1_ic_tag_wren, S1_W_stall, S1_ic_fill_tag[6], S1_ic_tag_wraddress[0], S1_ic_tag_wraddress[1], S1_ic_tag_wraddress[2], S1_ic_tag_wraddress[3], S1_ic_tag_wraddress[4], S1_ic_tag_wraddress[5], S1_ic_tag_wraddress[6], S1L1233, S1L1236, S1L1239, S1L1242, S1L1245, S1L1248, S1L1251, S1L1580Q, S1_ic_fill_tag[9], S1_ic_fill_tag[10], S1_ic_fill_tag[7], S1L1609Q, S1L1587Q, S1L1633Q, S1L1636Q, S1L1577Q, S1L1593Q, S1L1642Q, S1L1568Q, S1L1583Q, S1_ic_fill_valid_bits[5], S1_ic_fill_valid_bits[3], S1_ic_fill_valid_bits[1], S1_ic_fill_valid_bits[7], S1_ic_fill_valid_bits[2], S1_ic_fill_valid_bits[4], S1_ic_fill_valid_bits[0], S1_ic_fill_valid_bits[6]);

--BD1_q_b[3] is std_1c20:inst|cpu:the_cpu|cpu_ic_tag_module:cpu_ic_tag|altsyncram:the_altsyncram|altsyncram_09e1:auto_generated|q_b[3] at M4K_X19_Y20

BD1_q_b[3] = AMPP_FUNCTION(GND, GND, QC2__clk0, QC2__clk0, S1_ic_tag_wren, S1_W_stall, S1_ic_fill_tag[6], S1_ic_tag_wraddress[0], S1_ic_tag_wraddress[1], S1_ic_tag_wraddress[2], S1_ic_tag_wraddress[3], S1_ic_tag_wraddress[4], S1_ic_tag_wraddress[5], S1_ic_tag_wraddress[6], S1L1233, S1L1236, S1L1239, S1L1242, S1L1245, S1L1248, S1L1251, S1L1580Q, S1_ic_fill_tag[9], S1_ic_fill_tag[10], S1_ic_fill_tag[7], S1L1609Q, S1L1587Q, S1L1633Q, S1L1636Q, S1L1577Q, S1L1593Q, S1L1642Q, S1L1568Q, S1L1583Q, S1_ic_fill_valid_bits[5], S1_ic_fill_valid_bits[3], S1_ic_fill_valid_bits[1], S1_ic_fill_valid_bits[7], S1_ic_fill_valid_bits[2], S1_ic_fill_valid_bits[4], S1_ic_fill_valid_bits[0], S1_ic_fill_valid_bits[6]);

--BD1_q_b[5] is std_1c20:inst|cpu:the_cpu|cpu_ic_tag_module:cpu_ic_tag|altsyncram:the_altsyncram|altsyncram_09e1:auto_generated|q_b[5] at M4K_X19_Y20

BD1_q_b[5] = AMPP_FUNCTION(GND, GND, QC2__clk0, QC2__clk0, S1_ic_tag_wren, S1_W_stall, S1_ic_fill_tag[6], S1_ic_tag_wraddress[0], S1_ic_tag_wraddress[1], S1_ic_tag_wraddress[2], S1_ic_tag_wraddress[3], S1_ic_tag_wraddress[4], S1_ic_tag_wraddress[5], S1_ic_tag_wraddress[6], S1L1233, S1L1236, S1L1239, S1L1242, S1L1245, S1L1248, S1L1251, S1L1580Q, S1_ic_fill_tag[9], S1_ic_fill_tag[10], S1_ic_fill_tag[7], S1L1609Q, S1L1587Q, S1L1633Q, S1L1636Q, S1L1577Q, S1L1593Q, S1L1642Q, S1L1568Q, S1L1583Q, S1_ic_fill_valid_bits[5], S1_ic_fill_valid_bits[3], S1_ic_fill_valid_bits[1], S1_ic_fill_valid_bits[7], S1_ic_fill_valid_bits[2], S1_ic_fill_valid_bits[4], S1_ic_fill_valid_bits[0], S1_ic_fill_valid_bits[6]);

--BD1_q_b[11] is std_1c20:inst|cpu:the_cpu|cpu_ic_tag_module:cpu_ic_tag|altsyncram:the_altsyncram|altsyncram_09e1:auto_generated|q_b[11] at M4K_X19_Y20

BD1_q_b[11] = AMPP_FUNCTION(GND, GND, QC2__clk0, QC2__clk0, S1_ic_tag_wren, S1_W_stall, S1_ic_fill_tag[6], S1_ic_tag_wraddress[0], S1_ic_tag_wraddress[1], S1_ic_tag_wraddress[2], S1_ic_tag_wraddress[3], S1_ic_tag_wraddress[4], S1_ic_tag_wraddress[5], S1_ic_tag_wraddress[6], S1L1233, S1L1236, S1L1239, S1L1242, S1L1245, S1L1248, S1L1251, S1L1580Q, S1_ic_fill_tag[9], S1_ic_fill_tag[10], S1_ic_fill_tag[7], S1L1609Q, S1L1587Q, S1L1633Q, S1L1636Q, S1L1577Q, S1L1593Q, S1L1642Q, S1L1568Q, S1L1583Q, S1_ic_fill_valid_bits[5], S1_ic_fill_valid_bits[3], S1_ic_fill_valid_bits[1], S1_ic_fill_valid_bits[7], S1_ic_fill_valid_bits[2], S1_ic_fill_valid_bits[4], S1_ic_fill_valid_bits[0], S1_ic_fill_valid_bits[6]);

--BD1_q_b[8] is std_1c20:inst|cpu:the_cpu|cpu_ic_tag_module:cpu_ic_tag|altsyncram:the_altsyncram|altsyncram_09e1:auto_generated|q_b[8] at M4K_X19_Y20

BD1_q_b[8] = AMPP_FUNCTION(GND, GND, QC2__clk0, QC2__clk0, S1_ic_tag_wren, S1_W_stall, S1_ic_fill_tag[6], S1_ic_tag_wraddress[0], S1_ic_tag_wraddress[1], S1_ic_tag_wraddress[2], S1_ic_tag_wraddress[3], S1_ic_tag_wraddress[4], S1_ic_tag_wraddress[5], S1_ic_tag_wraddress[6], S1L1233, S1L1236, S1L1239, S1L1242, S1L1245, S1L1248, S1L1251, S1L1580Q, S1_ic_fill_tag[9], S1_ic_fill_tag[10], S1_ic_fill_tag[7], S1L1609Q, S1L1587Q, S1L1633Q, S1L1636Q, S1L1577Q, S1L1593Q, S1L1642Q, S1L1568Q, S1L1583Q, S1_ic_fill_valid_bits[5], S1_ic_fill_valid_bits[3], S1_ic_fill_valid_bits[1], S1_ic_fill_valid_bits[7], S1_ic_fill_valid_bits[2], S1_ic_fill_valid_bits[4], S1_ic_fill_valid_bits[0], S1_ic_fill_valid_bits[6]);

--BD1_q_b[21] is std_1c20:inst|cpu:the_cpu|cpu_ic_tag_module:cpu_ic_tag|altsyncram:the_altsyncram|altsyncram_09e1:auto_generated|q_b[21] at M4K_X19_Y20

BD1_q_b[21] = AMPP_FUNCTION(GND, GND, QC2__clk0, QC2__clk0, S1_ic_tag_wren, S1_W_stall, S1_ic_fill_tag[6], S1_ic_tag_wraddress[0], S1_ic_tag_wraddress[1], S1_ic_tag_wraddress[2], S1_ic_tag_wraddress[3], S1_ic_tag_wraddress[4], S1_ic_tag_wraddress[5], S1_ic_tag_wraddress[6], S1L1233, S1L1236, S1L1239, S1L1242, S1L1245, S1L1248, S1L1251, S1L1580Q, S1_ic_fill_tag[9], S1_ic_fill_tag[10], S1_ic_fill_tag[7], S1L1609Q, S1L1587Q, S1L1633Q, S1L1636Q, S1L1577Q, S1L1593Q, S1L1642Q, S1L1568Q, S1L1583Q, S1_ic_fill_valid_bits[5], S1_ic_fill_valid_bits[3], S1_ic_fill_valid_bits[1], S1_ic_fill_valid_bits[7], S1_ic_fill_valid_bits[2], S1_ic_fill_valid_bits[4], S1_ic_fill_valid_bits[0], S1_ic_fill_valid_bits[6]);

--BD1_q_b[13] is std_1c20:inst|cpu:the_cpu|cpu_ic_tag_module:cpu_ic_tag|altsyncram:the_altsyncram|altsyncram_09e1:auto_generated|q_b[13] at M4K_X19_Y20

BD1_q_b[13] = AMPP_FUNCTION(GND, GND, QC2__clk0, QC2__clk0, S1_ic_tag_wren, S1_W_stall, S1_ic_fill_tag[6], S1_ic_tag_wraddress[0], S1_ic_tag_wraddress[1], S1_ic_tag_wraddress[2], S1_ic_tag_wraddress[3], S1_ic_tag_wraddress[4], S1_ic_tag_wraddress[5], S1_ic_tag_wraddress[6], S1L1233, S1L1236, S1L1239, S1L1242, S1L1245, S1L1248, S1L1251, S1L1580Q, S1_ic_fill_tag[9], S1_ic_fill_tag[10], S1_ic_fill_tag[7], S1L1609Q, S1L1587Q, S1L1633Q, S1L1636Q, S1L1577Q, S1L1593Q, S1L1642Q, S1L1568Q, S1L1583Q, S1_ic_fill_valid_bits[5], S1_ic_fill_valid_bits[3], S1_ic_fill_valid_bits[1], S1_ic_fill_valid_bits[7], S1_ic_fill_valid_bits[2], S1_ic_fill_valid_bits[4], S1_ic_fill_valid_bits[0], S1_ic_fill_valid_bits[6]);

--BD1_q_b[9] is std_1c20:inst|cpu:the_cpu|cpu_ic_tag_module:cpu_ic_tag|altsyncram:the_altsyncram|altsyncram_09e1:auto_generated|q_b[9] at M4K_X19_Y20

BD1_q_b[9] = AMPP_FUNCTION(GND, GND, QC2__clk0, QC2__clk0, S1_ic_tag_wren, S1_W_stall, S1_ic_fill_tag[6], S1_ic_tag_wraddress[0], S1_ic_tag_wraddress[1], S1_ic_tag_wraddress[2], S1_ic_tag_wraddress[3], S1_ic_tag_wraddress[4], S1_ic_tag_wraddress[5], S1_ic_tag_wraddress[6], S1L1233, S1L1236, S1L1239, S1L1242, S1L1245, S1L1248, S1L1251, S1L1580Q, S1_ic_fill_tag[9], S1_ic_fill_tag[10], S1_ic_fill_tag[7], S1L1609Q, S1L1587Q, S1L1633Q, S1L1636Q, S1L1577Q, S1L1593Q, S1L1642Q, S1L1568Q, S1L1583Q, S1_ic_fill_valid_bits[5], S1_ic_fill_valid_bits[3], S1_ic_fill_valid_bits[1], S1_ic_fill_valid_bits[7], S1_ic_fill_valid_bits[2], S1_ic_fill_valid_bits[4], S1_ic_fill_valid_bits[0], S1_ic_fill_valid_bits[6]);

--BD1_q_b[20] is std_1c20:inst|cpu:the_cpu|cpu_ic_tag_module:cpu_ic_tag|altsyncram:the_altsyncram|altsyncram_09e1:auto_generated|q_b[20] at M4K_X19_Y20

BD1_q_b[20] = AMPP_FUNCTION(GND, GND, QC2__clk0, QC2__clk0, S1_ic_tag_wren, S1_W_stall, S1_ic_fill_tag[6], S1_ic_tag_wraddress[0], S1_ic_tag_wraddress[1], S1_ic_tag_wraddress[2], S1_ic_tag_wraddress[3], S1_ic_tag_wraddress[4], S1_ic_tag_wraddress[5], S1_ic_tag_wraddress[6], S1L1233, S1L1236, S1L1239, S1L1242, S1L1245, S1L1248, S1L1251, S1L1580Q, S1_ic_fill_tag[9], S1_ic_fill_tag[10], S1_ic_fill_tag[7], S1L1609Q, S1L1587Q, S1L1633Q, S1L1636Q, S1L1577Q, S1L1593Q, S1L1642Q, S1L1568Q, S1L1583Q, S1_ic_fill_valid_bits[5], S1_ic_fill_valid_bits[3], S1_ic_fill_valid_bits[1], S1_ic_fill_valid_bits[7], S1_ic_fill_valid_bits[2], S1_ic_fill_valid_bits[4], S1_ic_fill_valid_bits[0], S1_ic_fill_valid_bits[6]);

--BD1_q_b[19] is std_1c20:inst|cpu:the_cpu|cpu_ic_tag_module:cpu_ic_tag|altsyncram:the_altsyncram|altsyncram_09e1:auto_generated|q_b[19] at M4K_X19_Y20

BD1_q_b[19] = AMPP_FUNCTION(GND, GND, QC2__clk0, QC2__clk0, S1_ic_tag_wren, S1_W_stall, S1_ic_fill_tag[6], S1_ic_tag_wraddress[0], S1_ic_tag_wraddress[1], S1_ic_tag_wraddress[2], S1_ic_tag_wraddress[3], S1_ic_tag_wraddress[4], S1_ic_tag_wraddress[5], S1_ic_tag_wraddress[6], S1L1233, S1L1236, S1L1239, S1L1242, S1L1245, S1L1248, S1L1251, S1L1580Q, S1_ic_fill_tag[9], S1_ic_fill_tag[10], S1_ic_fill_tag[7], S1L1609Q, S1L1587Q, S1L1633Q, S1L1636Q, S1L1577Q, S1L1593Q, S1L1642Q, S1L1568Q, S1L1583Q, S1_ic_fill_valid_bits[5], S1_ic_fill_valid_bits[3], S1_ic_fill_valid_bits[1], S1_ic_fill_valid_bits[7], S1_ic_fill_valid_bits[2], S1_ic_fill_valid_bits[4], S1_ic_fill_valid_bits[0], S1_ic_fill_valid_bits[6]);

--BD1_q_b[12] is std_1c20:inst|cpu:the_cpu|cpu_ic_tag_module:cpu_ic_tag|altsyncram:the_altsyncram|altsyncram_09e1:auto_generated|q_b[12] at M4K_X19_Y20

BD1_q_b[12] = AMPP_FUNCTION(GND, GND, QC2__clk0, QC2__clk0, S1_ic_tag_wren, S1_W_stall, S1_ic_fill_tag[6], S1_ic_tag_wraddress[0], S1_ic_tag_wraddress[1], S1_ic_tag_wraddress[2], S1_ic_tag_wraddress[3], S1_ic_tag_wraddress[4], S1_ic_tag_wraddress[5], S1_ic_tag_wraddress[6], S1L1233, S1L1236, S1L1239, S1L1242, S1L1245, S1L1248, S1L1251, S1L1580Q, S1_ic_fill_tag[9], S1_ic_fill_tag[10], S1_ic_fill_tag[7], S1L1609Q, S1L1587Q, S1L1633Q, S1L1636Q, S1L1577Q, S1L1593Q, S1L1642Q, S1L1568Q, S1L1583Q, S1_ic_fill_valid_bits[5], S1_ic_fill_valid_bits[3], S1_ic_fill_valid_bits[1], S1_ic_fill_valid_bits[7], S1_ic_fill_valid_bits[2], S1_ic_fill_valid_bits[4], S1_ic_fill_valid_bits[0], S1_ic_fill_valid_bits[6]);

--BD1_q_b[16] is std_1c20:inst|cpu:the_cpu|cpu_ic_tag_module:cpu_ic_tag|altsyncram:the_altsyncram|altsyncram_09e1:auto_generated|q_b[16] at M4K_X19_Y20

BD1_q_b[16] = AMPP_FUNCTION(GND, GND, QC2__clk0, QC2__clk0, S1_ic_tag_wren, S1_W_stall, S1_ic_fill_tag[6], S1_ic_tag_wraddress[0], S1_ic_tag_wraddress[1], S1_ic_tag_wraddress[2], S1_ic_tag_wraddress[3], S1_ic_tag_wraddress[4], S1_ic_tag_wraddress[5], S1_ic_tag_wraddress[6], S1L1233, S1L1236, S1L1239, S1L1242, S1L1245, S1L1248, S1L1251, S1L1580Q, S1_ic_fill_tag[9], S1_ic_fill_tag[10], S1_ic_fill_tag[7], S1L1609Q, S1L1587Q, S1L1633Q, S1L1636Q, S1L1577Q, S1L1593Q, S1L1642Q, S1L1568Q, S1L1583Q, S1_ic_fill_valid_bits[5], S1_ic_fill_valid_bits[3], S1_ic_fill_valid_bits[1], S1_ic_fill_valid_bits[7], S1_ic_fill_valid_bits[2], S1_ic_fill_valid_bits[4], S1_ic_fill_valid_bits[0], S1_ic_fill_valid_bits[6]);

--BD1_q_b[15] is std_1c20:inst|cpu:the_cpu|cpu_ic_tag_module:cpu_ic_tag|altsyncram:the_altsyncram|altsyncram_09e1:auto_generated|q_b[15] at M4K_X19_Y20

BD1_q_b[15] = AMPP_FUNCTION(GND, GND, QC2__clk0, QC2__clk0, S1_ic_tag_wren, S1_W_stall, S1_ic_fill_tag[6], S1_ic_tag_wraddress[0], S1_ic_tag_wraddress[1], S1_ic_tag_wraddress[2], S1_ic_tag_wraddress[3], S1_ic_tag_wraddress[4], S1_ic_tag_wraddress[5], S1_ic_tag_wraddress[6], S1L1233, S1L1236, S1L1239, S1L1242, S1L1245, S1L1248, S1L1251, S1L1580Q, S1_ic_fill_tag[9], S1_ic_fill_tag[10], S1_ic_fill_tag[7], S1L1609Q, S1L1587Q, S1L1633Q, S1L1636Q, S1L1577Q, S1L1593Q, S1L1642Q, S1L1568Q, S1L1583Q, S1_ic_fill_valid_bits[5], S1_ic_fill_valid_bits[3], S1_ic_fill_valid_bits[1], S1_ic_fill_valid_bits[7], S1_ic_fill_valid_bits[2], S1_ic_fill_valid_bits[4], S1_ic_fill_valid_bits[0], S1_ic_fill_valid_bits[6]);

--BD1_q_b[18] is std_1c20:inst|cpu:the_cpu|cpu_ic_tag_module:cpu_ic_tag|altsyncram:the_altsyncram|altsyncram_09e1:auto_generated|q_b[18] at M4K_X19_Y20

BD1_q_b[18] = AMPP_FUNCTION(GND, GND, QC2__clk0, QC2__clk0, S1_ic_tag_wren, S1_W_stall, S1_ic_fill_tag[6], S1_ic_tag_wraddress[0], S1_ic_tag_wraddress[1], S1_ic_tag_wraddress[2], S1_ic_tag_wraddress[3], S1_ic_tag_wraddress[4], S1_ic_tag_wraddress[5], S1_ic_tag_wraddress[6], S1L1233, S1L1236, S1L1239, S1L1242, S1L1245, S1L1248, S1L1251, S1L1580Q, S1_ic_fill_tag[9], S1_ic_fill_tag[10], S1_ic_fill_tag[7], S1L1609Q, S1L1587Q, S1L1633Q, S1L1636Q, S1L1577Q, S1L1593Q, S1L1642Q, S1L1568Q, S1L1583Q, S1_ic_fill_valid_bits[5], S1_ic_fill_valid_bits[3], S1_ic_fill_valid_bits[1], S1_ic_fill_valid_bits[7], S1_ic_fill_valid_bits[2], S1_ic_fill_valid_bits[4], S1_ic_fill_valid_bits[0], S1_ic_fill_valid_bits[6]);

--BD1_q_b[17] is std_1c20:inst|cpu:the_cpu|cpu_ic_tag_module:cpu_ic_tag|altsyncram:the_altsyncram|altsyncram_09e1:auto_generated|q_b[17] at M4K_X19_Y20

BD1_q_b[17] = AMPP_FUNCTION(GND, GND, QC2__clk0, QC2__clk0, S1_ic_tag_wren, S1_W_stall, S1_ic_fill_tag[6], S1_ic_tag_wraddress[0], S1_ic_tag_wraddress[1], S1_ic_tag_wraddress[2], S1_ic_tag_wraddress[3], S1_ic_tag_wraddress[4], S1_ic_tag_wraddress[5], S1_ic_tag_wraddress[6], S1L1233, S1L1236, S1L1239, S1L1242, S1L1245, S1L1248, S1L1251, S1L1580Q, S1_ic_fill_tag[9], S1_ic_fill_tag[10], S1_ic_fill_tag[7], S1L1609Q, S1L1587Q, S1L1633Q, S1L1636Q, S1L1577Q, S1L1593Q, S1L1642Q, S1L1568Q, S1L1583Q, S1_ic_fill_valid_bits[5], S1_ic_fill_valid_bits[3], S1_ic_fill_valid_bits[1], S1_ic_fill_valid_bits[7], S1_ic_fill_valid_bits[2], S1_ic_fill_valid_bits[4], S1_ic_fill_valid_bits[0], S1_ic_fill_valid_bits[6]);

--BD1_q_b[10] is std_1c20:inst|cpu:the_cpu|cpu_ic_tag_module:cpu_ic_tag|altsyncram:the_altsyncram|altsyncram_09e1:auto_generated|q_b[10] at M4K_X19_Y20

BD1_q_b[10] = AMPP_FUNCTION(GND, GND, QC2__clk0, QC2__clk0, S1_ic_tag_wren, S1_W_stall, S1_ic_fill_tag[6], S1_ic_tag_wraddress[0], S1_ic_tag_wraddress[1], S1_ic_tag_wraddress[2], S1_ic_tag_wraddress[3], S1_ic_tag_wraddress[4], S1_ic_tag_wraddress[5], S1_ic_tag_wraddress[6], S1L1233, S1L1236, S1L1239, S1L1242, S1L1245, S1L1248, S1L1251, S1L1580Q, S1_ic_fill_tag[9], S1_ic_fill_tag[10], S1_ic_fill_tag[7], S1L1609Q, S1L1587Q, S1L1633Q, S1L1636Q, S1L1577Q, S1L1593Q, S1L1642Q, S1L1568Q, S1L1583Q, S1_ic_fill_valid_bits[5], S1_ic_fill_valid_bits[3], S1_ic_fill_valid_bits[1], S1_ic_fill_valid_bits[7], S1_ic_fill_valid_bits[2], S1_ic_fill_valid_bits[4], S1_ic_fill_valid_bits[0], S1_ic_fill_valid_bits[6]);

--S1L344Q is std_1c20:inst|cpu:the_cpu|D_issue~6 at LC_X25_Y20_N0

--operation mode is normal

S1L344Q = AMPP_FUNCTION(QC2__clk0, S1_F_pc[16], BD1_q_b[14], S1_F_pc[12], BD1_q_b[10], F1_data_out, S1_W_stall);

--S1_F_pc[20] is std_1c20:inst|cpu:the_cpu|F_pc[20] at LC_X25_Y18_N7

--operation mode is normal

S1_F_pc[20] = AMPP_FUNCTION(QC2__clk0, S1_D_pc[20], S1L37, S1_M_pipe_flush_waddr[20], S1_D_refetch, F1_data_out, !S1_M_pipe_flush, S1_W_stall);

--S1_F_pc[19] is std_1c20:inst|cpu:the_cpu|F_pc[19] at LC_X25_Y18_N1

--operation mode is normal

S1_F_pc[19] = AMPP_FUNCTION(QC2__clk0, S1L38, S1_D_pc[19], S1_M_pipe_flush_waddr[19], S1_D_refetch, F1_data_out, !S1_M_pipe_flush, S1_W_stall);

--S1L1219 is std_1c20:inst|cpu:the_cpu|F_ic_hit~119 at LC_X25_Y18_N3

--operation mode is normal

S1L1219 = AMPP_FUNCTION(S1_F_pc[19], BD1_q_b[17], S1_F_pc[20], BD1_q_b[18]);

--S1L347Q is std_1c20:inst|cpu:the_cpu|D_issue~10 at LC_X25_Y18_N3

--operation mode is normal

S1L347Q = AMPP_FUNCTION(QC2__clk0, S1_F_pc[19], BD1_q_b[17], S1_F_pc[20], BD1_q_b[18], F1_data_out, S1_W_stall);

--S1_F_pc[18] is std_1c20:inst|cpu:the_cpu|F_pc[18] at LC_X25_Y16_N6

--operation mode is normal

S1_F_pc[18] = AMPP_FUNCTION(QC2__clk0, S1_D_refetch, S1L39, S1_M_pipe_flush_waddr[18], S1_D_pc[18], F1_data_out, !S1_M_pipe_flush, S1_W_stall);

--S1_F_pc[17] is std_1c20:inst|cpu:the_cpu|F_pc[17] at LC_X25_Y16_N5

--operation mode is normal

S1_F_pc[17] = AMPP_FUNCTION(QC2__clk0, S1_D_refetch, S1_D_pc[17], S1_M_pipe_flush_waddr[17], S1L40, F1_data_out, !S1_M_pipe_flush, S1_W_stall);

--S1L1220 is std_1c20:inst|cpu:the_cpu|F_ic_hit~120 at LC_X24_Y18_N3

--operation mode is normal

S1L1220 = AMPP_FUNCTION(S1_F_pc[18], S1_F_pc[17], BD1_q_b[16], BD1_q_b[15]);

--S1_F_pc[21] is std_1c20:inst|cpu:the_cpu|F_pc[21] at LC_X26_Y16_N4

--operation mode is normal

S1_F_pc[21] = AMPP_FUNCTION(QC2__clk0, S1L41, S1_D_pc[21], S1_M_pipe_flush_waddr[21], S1_D_refetch, F1_data_out, !S1_M_pipe_flush, S1_W_stall);

--S1_F_pc[14] is std_1c20:inst|cpu:the_cpu|F_pc[14] at LC_X26_Y16_N9

--operation mode is normal

S1_F_pc[14] = AMPP_FUNCTION(QC2__clk0, S1_D_pc[14], S1L42, S1_M_pipe_flush_waddr[14], S1_D_refetch, F1_data_out, !S1_M_pipe_flush, S1_W_stall);

--S1L1221 is std_1c20:inst|cpu:the_cpu|F_ic_hit~121 at LC_X24_Y20_N1

--operation mode is normal

S1L1221 = AMPP_FUNCTION(BD1_q_b[19], S1_F_pc[21], BD1_q_b[12], S1_F_pc[14]);

--S1_F_pc[11] is std_1c20:inst|cpu:the_cpu|F_pc[11] at LC_X25_Y19_N1

--operation mode is normal

S1_F_pc[11] = AMPP_FUNCTION(QC2__clk0, S1L43, S1_D_refetch, S1_M_pipe_flush_waddr[11], S1_D_pc[11], F1_data_out, !S1_M_pipe_flush, S1_W_stall);

--S1_F_pc[22] is std_1c20:inst|cpu:the_cpu|F_pc[22] at LC_X27_Y20_N0

--operation mode is normal

S1_F_pc[22] = AMPP_FUNCTION(QC2__clk0, S1L44, S1_D_pc[22], S1_M_pipe_flush_waddr[22], S1_D_refetch, F1_data_out, !S1_M_pipe_flush, S1_W_stall);

--S1_F_pc[23] is std_1c20:inst|cpu:the_cpu|F_pc[23] at LC_X28_Y19_N7

--operation mode is normal

S1_F_pc[23] = AMPP_FUNCTION(QC2__clk0, S1_D_refetch, S1_D_pc[23], S1_M_pipe_flush_waddr[23], S1L45, F1_data_out, !S1_M_pipe_flush, S1_W_stall);

--S1_F_pc[15] is std_1c20:inst|cpu:the_cpu|F_pc[15] at LC_X28_Y19_N4

--operation mode is normal

S1_F_pc[15] = AMPP_FUNCTION(QC2__clk0, S1_D_refetch, S1_D_pc[15], S1_M_pipe_flush_waddr[15], S1L46, F1_data_out, !S1_M_pipe_flush, S1_W_stall);

--S1L334Q is std_1c20:inst|cpu:the_cpu|D_inst_ram_hit~19 at LC_X25_Y19_N0

--operation mode is normal

S1L334Q = AMPP_FUNCTION(QC2__clk0, S1_F_pc[15], BD1_q_b[21], BD1_q_b[13], S1_F_pc[23], F1_data_out, S1_W_stall);

--S1_F_pc[13] is std_1c20:inst|cpu:the_cpu|F_pc[13] at LC_X28_Y19_N9

--operation mode is normal

S1_F_pc[13] = AMPP_FUNCTION(QC2__clk0, S1_D_refetch, S1L47, S1_M_pipe_flush_waddr[13], S1_D_pc[13], F1_data_out, !S1_M_pipe_flush, S1_W_stall);

--S1_F_pc[10] is std_1c20:inst|cpu:the_cpu|F_pc[10] at LC_X28_Y19_N5

--operation mode is normal

S1_F_pc[10] = AMPP_FUNCTION(QC2__clk0, S1_D_pc[10], S1_D_refetch, S1_M_pipe_flush_waddr[10], S1L48, F1_data_out, !S1_M_pipe_flush, S1_W_stall);

--S1L1225 is std_1c20:inst|cpu:the_cpu|F_ic_hit~125 at LC_X24_Y18_N5

--operation mode is normal

S1L1225 = AMPP_FUNCTION(S1_F_pc[13], S1_F_pc[10], BD1_q_b[8], BD1_q_b[11]);

--S1L1253 is std_1c20:inst|cpu:the_cpu|F_ic_valid~23 at LC_X23_Y19_N5

--operation mode is normal

S1L1253 = AMPP_FUNCTION(BD1_q_b[3], S1_F_pc[2], S1_F_pc[1], BD1_q_b[1]);

--S1L335Q is std_1c20:inst|cpu:the_cpu|D_inst_ram_hit~20 at LC_X23_Y19_N6

--operation mode is normal

S1L335Q = AMPP_FUNCTION(QC2__clk0, BD1_q_b[5], S1_F_pc[2], BD1_q_b[7], S1L1253, F1_data_out, S1_W_stall);

--S1L1255 is std_1c20:inst|cpu:the_cpu|F_ic_valid~25 at LC_X23_Y19_N3

--operation mode is normal

S1L1255 = AMPP_FUNCTION(S1_F_pc[1], BD1_q_b[0], S1_F_pc[2], BD1_q_b[4]);

--S1L336Q is std_1c20:inst|cpu:the_cpu|D_inst_ram_hit~21 at LC_X23_Y19_N8

--operation mode is normal

S1L336Q = AMPP_FUNCTION(QC2__clk0, BD1_q_b[2], BD1_q_b[6], S1_F_pc[1], S1L1255, F1_data_out, S1_W_stall);

--S1_M_ctrl_invalidate_i is std_1c20:inst|cpu:the_cpu|M_ctrl_invalidate_i at LC_X30_Y15_N4

--operation mode is normal

S1_M_ctrl_invalidate_i = AMPP_FUNCTION(QC2__clk0, S1L823, S1_E_iw[14], S1L822, S1L715, F1_data_out, S1_W_stall);

--S1L1562 is std_1c20:inst|cpu:the_cpu|ic_fill_prevent_refill_nxt~0 at LC_X23_Y20_N0

--operation mode is normal

S1L1562 = AMPP_FUNCTION(S1_M_ctrl_invalidate_i, S1_M_valid_from_E);

--S1L1205 is std_1c20:inst|cpu:the_cpu|F_ic_fill_same_tag_line~197 at LC_X24_Y18_N4

--operation mode is normal

S1L1205 = AMPP_FUNCTION(S1_F_pc[19], S1_ic_fill_tag[9], S1_ic_fill_tag[7], S1_F_pc[17]);

--S1L1206 is std_1c20:inst|cpu:the_cpu|F_ic_fill_same_tag_line~198 at LC_X26_Y20_N9

--operation mode is normal

S1L1206 = AMPP_FUNCTION(S1_F_pc[9], S1_F_pc[13], S1_ic_fill_line[6], S1L1583Q);

--S1L1207 is std_1c20:inst|cpu:the_cpu|F_ic_fill_same_tag_line~199 at LC_X25_Y17_N5

--operation mode is normal

S1L1207 = AMPP_FUNCTION(S1_F_pc[7], S1L1633Q, S1_ic_fill_line[4], S1_F_pc[21]);

--S1L1208 is std_1c20:inst|cpu:the_cpu|F_ic_fill_same_tag_line~200 at LC_X25_Y19_N4

--operation mode is normal

S1L1208 = AMPP_FUNCTION(S1_F_pc[11], S1_ic_fill_line[2], S1_F_pc[5], S1L1577Q);

--S1L1209 is std_1c20:inst|cpu:the_cpu|F_ic_fill_same_tag_line~201 at LC_X25_Y17_N6

--operation mode is normal

S1L1209 = AMPP_FUNCTION(S1L1208, S1L1207, S1L1206, S1L1205);

--S1L1210 is std_1c20:inst|cpu:the_cpu|F_ic_fill_same_tag_line~202 at LC_X24_Y20_N4

--operation mode is normal

S1L1210 = AMPP_FUNCTION(S1_F_pc[3], S1L1587Q, S1_ic_fill_line[0], S1_F_pc[14]);

--S1L1211 is std_1c20:inst|cpu:the_cpu|F_ic_fill_same_tag_line~203 at LC_X24_Y18_N0

--operation mode is normal

S1L1211 = AMPP_FUNCTION(S1_ic_fill_line[5], S1_F_pc[8], S1_F_pc[18], S1L1609Q);

--S1L1212 is std_1c20:inst|cpu:the_cpu|F_ic_fill_same_tag_line~204 at LC_X24_Y18_N7

--operation mode is normal

S1L1212 = AMPP_FUNCTION(S1_F_pc[20], S1L1568Q, S1_ic_fill_tag[10], S1_F_pc[10]);

--S1L1213 is std_1c20:inst|cpu:the_cpu|F_ic_fill_same_tag_line~205 at LC_X24_Y19_N9

--operation mode is normal

S1L1213 = AMPP_FUNCTION(S1_F_pc[4], S1L1593Q, S1_F_pc[15], S1_ic_fill_line[1]);

--S1L1214 is std_1c20:inst|cpu:the_cpu|F_ic_fill_same_tag_line~206 at LC_X24_Y18_N2

--operation mode is normal

S1L1214 = AMPP_FUNCTION(S1L1212, S1L1211, S1L1210, S1L1213);

--S1L1215 is std_1c20:inst|cpu:the_cpu|F_ic_fill_same_tag_line~207 at LC_X25_Y20_N7

--operation mode is normal

S1L1215 = AMPP_FUNCTION(S1_F_pc[23], S1_ic_fill_tag[6], S1_F_pc[16], S1L1642Q);

--S1L1216 is std_1c20:inst|cpu:the_cpu|F_ic_fill_same_tag_line~208 at LC_X27_Y20_N9

--operation mode is normal

S1L1216 = AMPP_FUNCTION(S1_F_pc[6], S1_F_pc[12], S1L1580Q, S1_ic_fill_line[3]);

--S1L1217 is std_1c20:inst|cpu:the_cpu|F_ic_fill_same_tag_line~209 at LC_X27_Y20_N1

--operation mode is normal

S1L1217 = AMPP_FUNCTION(S1_F_pc[22], S1L1216, S1L1636Q);

--S1_i_readdatavalid_d1 is std_1c20:inst|cpu:the_cpu|i_readdatavalid_d1 at LC_X33_Y24_N8

--operation mode is normal

S1_i_readdatavalid_d1 = AMPP_FUNCTION(QC2__clk0, U1L143, U1L144, U1L142, X1L12, F1_data_out);

--S1_ic_fill_dp_offset[2] is std_1c20:inst|cpu:the_cpu|ic_fill_dp_offset[2] at LC_X22_Y20_N4

--operation mode is normal

S1_ic_fill_dp_offset[2] = AMPP_FUNCTION(QC2__clk0, S1_D_ic_fill_starting_d1, S1L1541, S1_ic_fill_initial_offset[2], F1_data_out, S1L1538);

--S1L1541 is std_1c20:inst|cpu:the_cpu|ic_fill_dp_offset_nxt[2]~152 at LC_X22_Y20_N2

--operation mode is normal

S1L1541 = AMPP_FUNCTION(S1_D_ic_fill_starting_d1, S1_ic_fill_dp_offset[0], S1_ic_fill_dp_offset[2], S1_ic_fill_dp_offset[1]);

--S1_ic_fill_initial_offset[0] is std_1c20:inst|cpu:the_cpu|ic_fill_initial_offset[0] at LC_X26_Y21_N6

--operation mode is normal

S1_ic_fill_initial_offset[0] = AMPP_FUNCTION(QC2__clk0, S1_D_pc[0], F1_data_out, S1_D_ic_fill_starting);

--S1L1492 is std_1c20:inst|cpu:the_cpu|ic_fill_active_nxt~270 at LC_X23_Y21_N4

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

S1L1492 = AMPP_FUNCTION(S1_ic_fill_initial_offset[0], S1_ic_fill_dp_offset[1], S1_ic_fill_dp_offset[0]);

--S1_ic_fill_initial_offset[1] is std_1c20:inst|cpu:the_cpu|ic_fill_initial_offset[1] at LC_X23_Y21_N4

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

S1_ic_fill_initial_offset[1] = AMPP_FUNCTION(QC2__clk0, S1_D_pc[1], F1_data_out, GND, S1_D_ic_fill_starting);

--S1L1493 is std_1c20:inst|cpu:the_cpu|ic_fill_active_nxt~271 at LC_X23_Y20_N7

--operation mode is normal

S1L1493 = AMPP_FUNCTION(S1_D_ic_fill_starting_d1, S1L1541, S1L1492, S1_ic_fill_initial_offset[2]);

--Y1L691Q is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_avalon_slave_arb_share_counter[0]~597 at LC_X27_Y25_N0

--operation mode is normal

Y1L691Q_lut_out = Y1L709 # !Y1L726 & (Y1L14 # Y1L587);

Y1L691Q = DFFEAS(Y1L691Q_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--Y1L710 is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_avalon_slave_arb_share_counter_next_value[1]~93 at LC_X27_Y25_N6

--operation mode is normal

Y1L710 = Y1L726 & Y1L705 & Y1L690;

--Y1L685 is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_avalon_slave_arb_counter_enable~20 at LC_X27_Y25_N3

--operation mode is normal

Y1L685 = Y1L699 & (Y1L693Q # !Y1L695Q # !Y1L694Q);

--Y1_WideOr6 is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|WideOr6 at LC_X30_Y24_N4

--operation mode is normal

Y1_WideOr6 = Y1L736 # Y1L916 # Y1L587 # !Y1L696;

--Y1L643Q is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_avalon_slave_arb_addend[4]~707 at LC_X30_Y24_N4

--operation mode is normal

Y1L643Q = DFFEAS(Y1_WideOr6, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--KB1_rd_valid[2] is std_1c20:inst|sdram:the_sdram|rd_valid[2] at LC_X16_Y25_N4

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

KB1_rd_valid[2]_lut_out = GND;

KB1_rd_valid[2] = DFFEAS(KB1_rd_valid[2]_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , KB1_rd_valid[1], , , VCC);

--WE1L42 is std_1c20:inst|sdram_s1_arbitrator:the_sdram_s1|rdv_fifo_for_cpu_instruction_master_to_sdram_s1_module:rdv_fifo_for_cpu_instruction_master_to_sdram_s1|stage_1~5 at LC_X24_Y25_N5

--operation mode is normal

WE1L42 = WE1_full_2 & WE1L45Q # !WE1_full_2 & (NB1L24);

--WE1_full_1 is std_1c20:inst|sdram_s1_arbitrator:the_sdram_s1|rdv_fifo_for_cpu_instruction_master_to_sdram_s1_module:rdv_fifo_for_cpu_instruction_master_to_sdram_s1|full_1 at LC_X23_Y26_N8

--operation mode is normal

WE1_full_1_lut_out = NB1L37 & WE1_full_0 # !NB1L37 & (KB1_za_valid & (WE1_full_2) # !KB1_za_valid & WE1_full_0);

WE1_full_1 = DFFEAS(WE1_full_1_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , VE1L22, , , , );

--WE1_full_0 is std_1c20:inst|sdram_s1_arbitrator:the_sdram_s1|rdv_fifo_for_cpu_instruction_master_to_sdram_s1_module:rdv_fifo_for_cpu_instruction_master_to_sdram_s1|full_0 at LC_X23_Y26_N5

--operation mode is normal

WE1_full_0_lut_out = WE1_full_1 # NB1L37 # !KB1_za_valid;

WE1_full_0 = DFFEAS(WE1_full_0_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , VE1L22, , , , );

--WE1L32 is std_1c20:inst|sdram_s1_arbitrator:the_sdram_s1|rdv_fifo_for_cpu_instruction_master_to_sdram_s1_module:rdv_fifo_for_cpu_instruction_master_to_sdram_s1|process12~3 at LC_X24_Y24_N3

--operation mode is normal

WE1L32 = KB1_za_valid # !WE1_full_0 & NB1L37;

--Y1L7 is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|A_WE_StdLogicVector~4288 at LC_X26_Y23_N0

--operation mode is normal

Y1L7 = Y1L175 # Y1L16 & (Y1L37 # Y1L34);

--Y1L573Q is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_avalon_slave_arb_addend[0]~810 at LC_X32_Y25_N3

--operation mode is normal

Y1L573Q_lut_out = Y1L633 # Y1L613 # Y1L662 # Y1L602;

Y1L573Q = DFFEAS(Y1L573Q_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--NC1L8 is std_1c20:inst|clock_1:the_clock_1|clock_1_slave_FSM:slave_FSM|Mux2~233 at LC_X47_Y28_N4

--operation mode is normal

NC1L8 = NC1L7 # !T1L10 & NC1_slave_state[2];

--N1_cpu_data_master_requests_clock_1_in is std_1c20:inst|clock_1_in_arbitrator:the_clock_1_in|cpu_data_master_requests_clock_1_in at LC_X41_Y23_N2

--operation mode is normal

N1_cpu_data_master_requests_clock_1_in = S1L1743Q & K1L3 & !S1L1773Q & K1L5;

--NC1L9 is std_1c20:inst|clock_1:the_clock_1|clock_1_slave_FSM:slave_FSM|Mux2~234 at LC_X42_Y27_N4

--operation mode is normal

NC1L9 = !NC1_slave_state[1] & (T1_internal_cpu_data_master_waitrequest # !N1_cpu_data_master_requests_clock_1_in # !S1L1686Q);

--GC1_data_in_d1 is std_1c20:inst|clock_1:the_clock_1|clock_1_master_write_done_sync_module:clock_1_master_write_done_sync|data_in_d1 at LC_X47_Y28_N9

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

GC1_data_in_d1_lut_out = GND;

GC1_data_in_d1 = DFFEAS(GC1_data_in_d1_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , LC1_internal_master_write_done, , , VCC);

--NC1L6 is std_1c20:inst|clock_1:the_clock_1|clock_1_slave_FSM:slave_FSM|Mux1~134 at LC_X47_Y28_N1

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

FC1_data_out_qfbk = FC1_data_out;

NC1L6 = NC1_slave_state[2] # NC1_slave_state[0] & (FC1_data_out_qfbk $ MC1_data_in_d1);

--FC1_data_out is std_1c20:inst|clock_1:the_clock_1|clock_1_master_read_done_sync_module:clock_1_master_read_done_sync|data_out at LC_X47_Y28_N1

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

FC1_data_out = DFFEAS(NC1L6, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , FC1_data_in_d1, , , VCC);

--NC1L5 is std_1c20:inst|clock_1:the_clock_1|clock_1_slave_FSM:slave_FSM|Mux0~141 at LC_X47_Y28_N3

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

GC1_data_out_qfbk = GC1_data_out;

NC1L5 = NC1_slave_state[2] & (GC1_data_out_qfbk $ MC2_data_in_d1 # !NC1_slave_state[0]) # !NC1_slave_state[2] & NC1_slave_state[0];

--GC1_data_out is std_1c20:inst|clock_1:the_clock_1|clock_1_master_write_done_sync_module:clock_1_master_write_done_sync|data_out at LC_X47_Y28_N3

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

GC1_data_out = DFFEAS(NC1L5, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , GC1_data_in_d1, , , VCC);

--NC1L4 is std_1c20:inst|clock_1:the_clock_1|clock_1_slave_FSM:slave_FSM|internal_slave_write_request~36 at LC_X47_Y27_N5

--operation mode is normal

NC1L4 = !S1_internal_d_read & !T1_internal_cpu_data_master_waitrequest & S1_internal_d_write & N1_cpu_data_master_requests_clock_1_in;

--FC1_data_in_d1 is std_1c20:inst|clock_1:the_clock_1|clock_1_master_read_done_sync_module:clock_1_master_read_done_sync|data_in_d1 at LC_X47_Y31_N2

--operation mode is normal

FC1_data_in_d1_lut_out = LC1_internal_master_read_done;

FC1_data_in_d1 = DFFEAS(FC1_data_in_d1_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--EC1L8 is std_1c20:inst|clock_0:the_clock_0|clock_0_slave_FSM:slave_FSM|Mux2~233 at LC_X43_Y27_N8

--operation mode is normal

EC1L8 = EC1L7 # EC1_slave_state[2] & !T1L12;

--K1_cpu_data_master_requests_clock_0_in is std_1c20:inst|clock_0_in_arbitrator:the_clock_0_in|cpu_data_master_requests_clock_0_in at LC_X41_Y23_N3

--operation mode is normal

K1_cpu_data_master_requests_clock_0_in = !S1L1773Q & K1L3 & !S1L1743Q & K1L5;

--EC1L9 is std_1c20:inst|clock_0:the_clock_0|clock_0_slave_FSM:slave_FSM|Mux2~234 at LC_X42_Y27_N0

--operation mode is normal

EC1L9 = !EC1_slave_state[1] & (T1_internal_cpu_data_master_waitrequest # !S1L1686Q # !K1_cpu_data_master_requests_clock_0_in);

--YB1_data_in_d1 is std_1c20:inst|clock_0:the_clock_0|clock_0_master_write_done_sync_module:clock_0_master_write_done_sync|data_in_d1 at LC_X43_Y28_N7

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

YB1_data_in_d1_lut_out = GND;

YB1_data_in_d1 = DFFEAS(YB1_data_in_d1_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , CC1_internal_master_write_done, , , VCC);

--EC1L6 is std_1c20:inst|clock_0:the_clock_0|clock_0_slave_FSM:slave_FSM|Mux1~129 at LC_X43_Y27_N0

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

XB1_data_out_qfbk = XB1_data_out;

EC1L6 = EC1_slave_state[2] # EC1_slave_state[0] & (DC1_data_in_d1 $ XB1_data_out_qfbk);

--XB1_data_out is std_1c20:inst|clock_0:the_clock_0|clock_0_master_read_done_sync_module:clock_0_master_read_done_sync|data_out at LC_X43_Y27_N0

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

XB1_data_out = DFFEAS(EC1L6, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , XB1_data_in_d1, , , VCC);

--EC1L5 is std_1c20:inst|clock_0:the_clock_0|clock_0_slave_FSM:slave_FSM|Mux0~141 at LC_X43_Y27_N7

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

YB1_data_out_qfbk = YB1_data_out;

EC1L5 = EC1_slave_state[0] & (DC2_data_in_d1 $ YB1_data_out_qfbk # !EC1_slave_state[2]) # !EC1_slave_state[0] & (EC1_slave_state[2]);

--YB1_data_out is std_1c20:inst|clock_0:the_clock_0|clock_0_master_write_done_sync_module:clock_0_master_write_done_sync|data_out at LC_X43_Y27_N7

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

YB1_data_out = DFFEAS(EC1L5, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , YB1_data_in_d1, , , VCC);

--EC1L4 is std_1c20:inst|clock_0:the_clock_0|clock_0_slave_FSM:slave_FSM|internal_slave_write_request~36 at LC_X42_Y27_N1

--operation mode is normal

EC1L4 = !T1_internal_cpu_data_master_waitrequest & S1_internal_d_write & !S1_internal_d_read & K1_cpu_data_master_requests_clock_0_in;

--XB1_data_in_d1 is std_1c20:inst|clock_0:the_clock_0|clock_0_master_read_done_sync_module:clock_0_master_read_done_sync|data_in_d1 at LC_X44_Y28_N9

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

XB1_data_in_d1_lut_out = GND;

XB1_data_in_d1 = DFFEAS(XB1_data_in_d1_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , CC1_internal_master_read_done, , , VCC);

--VE1L29 is std_1c20:inst|sdram_s1_arbitrator:the_sdram_s1|rdv_fifo_for_cpu_data_master_to_sdram_s1_module:rdv_fifo_for_cpu_data_master_to_sdram_s1|stage_1~573 at LC_X24_Y25_N2

--operation mode is normal

VE1L29 = WE1_full_2 & (VE1L32Q) # !WE1_full_2 & NB1L20;

--SD1_internal_jdo1[22] is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|internal_jdo1[22] at LC_X46_Y16_N7

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

SD1_internal_jdo1[22] = AMPP_FUNCTION(A1L8, SD1_sr[22], VCC, GND, SD1L144);

--LB1_countup[4] is std_1c20:inst|sdram_pll:the_sdram_pll|countup[4] at LC_X18_Y25_N8

--operation mode is arithmetic

LB1_countup[4]_lut_out = LB1_countup[4] $ LB1L29;

LB1_countup[4] = DFFEAS(LB1_countup[4]_lut_out, GLOBAL(PLD_CLKFB), LB1_not_areset, , !LB1_count_done, , , , );

--LB1L32 is std_1c20:inst|sdram_pll:the_sdram_pll|countup[4]~594 at LC_X18_Y25_N8

--operation mode is arithmetic

LB1L32_cout_0 = !LB1L29 # !LB1_countup[4];

LB1L32 = CARRY(LB1L32_cout_0);

--LB1L33 is std_1c20:inst|sdram_pll:the_sdram_pll|countup[4]~594COUT1_802 at LC_X18_Y25_N8

--operation mode is arithmetic

LB1L33_cout_1 = !LB1L30 # !LB1_countup[4];

LB1L33 = CARRY(LB1L33_cout_1);

--LB1_countup[5] is std_1c20:inst|sdram_pll:the_sdram_pll|countup[5] at LC_X18_Y25_N9

--operation mode is normal

LB1_countup[5]_lut_out = LB1_countup[5] $ (!LB1L32);

LB1_countup[5] = DFFEAS(LB1_countup[5]_lut_out, GLOBAL(PLD_CLKFB), LB1_not_areset, , !LB1_count_done, , , , );

--LB1_countup[1] is std_1c20:inst|sdram_pll:the_sdram_pll|countup[1] at LC_X18_Y25_N5

--operation mode is arithmetic

LB1_countup[1]_lut_out = LB1_countup[0] $ LB1_countup[1];

LB1_countup[1] = DFFEAS(LB1_countup[1]_lut_out, GLOBAL(PLD_CLKFB), LB1_not_areset, , !LB1_count_done, , , , );

--LB1L23 is std_1c20:inst|sdram_pll:the_sdram_pll|countup[1]~596 at LC_X18_Y25_N5

--operation mode is arithmetic

LB1L23_cout_0 = LB1_countup[0] & LB1_countup[1];

LB1L23 = CARRY(LB1L23_cout_0);

--LB1L24 is std_1c20:inst|sdram_pll:the_sdram_pll|countup[1]~596COUT1_796 at LC_X18_Y25_N5

--operation mode is arithmetic

LB1L24_cout_1 = LB1_countup[0] & LB1_countup[1];

LB1L24 = CARRY(LB1L24_cout_1);

--LB1_countup[2] is std_1c20:inst|sdram_pll:the_sdram_pll|countup[2] at LC_X18_Y25_N6

--operation mode is arithmetic

LB1_countup[2]_lut_out = LB1_countup[2] $ (LB1L23);

LB1_countup[2] = DFFEAS(LB1_countup[2]_lut_out, GLOBAL(PLD_CLKFB), LB1_not_areset, , !LB1_count_done, , , , );

--LB1L26 is std_1c20:inst|sdram_pll:the_sdram_pll|countup[2]~597 at LC_X18_Y25_N6

--operation mode is arithmetic

LB1L26_cout_0 = !LB1L23 # !LB1_countup[2];

LB1L26 = CARRY(LB1L26_cout_0);

--LB1L27 is std_1c20:inst|sdram_pll:the_sdram_pll|countup[2]~597COUT1_798 at LC_X18_Y25_N6

--operation mode is arithmetic

LB1L27_cout_1 = !LB1L24 # !LB1_countup[2];

LB1L27 = CARRY(LB1L27_cout_1);

--LB1_countup[3] is std_1c20:inst|sdram_pll:the_sdram_pll|countup[3] at LC_X18_Y25_N7

--operation mode is arithmetic

LB1_countup[3]_lut_out = LB1_countup[3] $ (!LB1L26);

LB1_countup[3] = DFFEAS(LB1_countup[3]_lut_out, GLOBAL(PLD_CLKFB), LB1_not_areset, , !LB1_count_done, , , , );

--LB1L29 is std_1c20:inst|sdram_pll:the_sdram_pll|countup[3]~598 at LC_X18_Y25_N7

--operation mode is arithmetic

LB1L29_cout_0 = LB1_countup[3] & (!LB1L26);

LB1L29 = CARRY(LB1L29_cout_0);

--LB1L30 is std_1c20:inst|sdram_pll:the_sdram_pll|countup[3]~598COUT1_800 at LC_X18_Y25_N7

--operation mode is arithmetic

LB1L30_cout_1 = LB1_countup[3] & (!LB1L27);

LB1L30 = CARRY(LB1L30_cout_1);

--LB1_countup[0] is std_1c20:inst|sdram_pll:the_sdram_pll|countup[0] at LC_X18_Y25_N2

--operation mode is normal

LB1_countup[0]_lut_out = LB1_countup[0] $ !LB1_count_done;

LB1_countup[0] = DFFEAS(LB1_countup[0]_lut_out, GLOBAL(PLD_CLKFB), LB1_not_areset, , , , , , );

--LB1L35 is std_1c20:inst|sdram_pll:the_sdram_pll|Equal0~41 at LC_X18_Y25_N4

--operation mode is normal

LB1L35 = LB1_countup[3] & LB1_countup[1] & LB1_countup[0] & LB1_countup[2];

--LB1_not_areset is std_1c20:inst|sdram_pll:the_sdram_pll|not_areset at LC_X18_Y25_N3

--operation mode is normal

LB1_not_areset_lut_out = VCC;

LB1_not_areset = DFFEAS(LB1_not_areset_lut_out, GLOBAL(PLD_CLKFB), VCC, , , , , , );

--Q1_countup[4] is std_1c20:inst|connector_pll:the_connector_pll|countup[4] at LC_X18_Y24_N8

--operation mode is arithmetic

Q1_countup[4]_lut_out = Q1_countup[4] $ Q1L29;

Q1_countup[4] = DFFEAS(Q1_countup[4]_lut_out, GLOBAL(PLD_CLOCKINPUT[1]), Q1_not_areset, , !Q1_count_done, , , , );

--Q1L32 is std_1c20:inst|connector_pll:the_connector_pll|countup[4]~594 at LC_X18_Y24_N8

--operation mode is arithmetic

Q1L32_cout_0 = !Q1L29 # !Q1_countup[4];

Q1L32 = CARRY(Q1L32_cout_0);

--Q1L33 is std_1c20:inst|connector_pll:the_connector_pll|countup[4]~594COUT1_802 at LC_X18_Y24_N8

--operation mode is arithmetic

Q1L33_cout_1 = !Q1L30 # !Q1_countup[4];

Q1L33 = CARRY(Q1L33_cout_1);

--Q1_countup[5] is std_1c20:inst|connector_pll:the_connector_pll|countup[5] at LC_X18_Y24_N9

--operation mode is normal

Q1_countup[5]_lut_out = Q1_countup[5] $ (!Q1L32);

Q1_countup[5] = DFFEAS(Q1_countup[5]_lut_out, GLOBAL(PLD_CLOCKINPUT[1]), Q1_not_areset, , !Q1_count_done, , , , );

--Q1_countup[1] is std_1c20:inst|connector_pll:the_connector_pll|countup[1] at LC_X18_Y24_N5

--operation mode is arithmetic

Q1_countup[1]_lut_out = Q1_countup[0] $ Q1_countup[1];

Q1_countup[1] = DFFEAS(Q1_countup[1]_lut_out, GLOBAL(PLD_CLOCKINPUT[1]), Q1_not_areset, , !Q1_count_done, , , , );

--Q1L23 is std_1c20:inst|connector_pll:the_connector_pll|countup[1]~596 at LC_X18_Y24_N5

--operation mode is arithmetic

Q1L23_cout_0 = Q1_countup[0] & Q1_countup[1];

Q1L23 = CARRY(Q1L23_cout_0);

--Q1L24 is std_1c20:inst|connector_pll:the_connector_pll|countup[1]~596COUT1_796 at LC_X18_Y24_N5

--operation mode is arithmetic

Q1L24_cout_1 = Q1_countup[0] & Q1_countup[1];

Q1L24 = CARRY(Q1L24_cout_1);

--Q1_countup[2] is std_1c20:inst|connector_pll:the_connector_pll|countup[2] at LC_X18_Y24_N6

--operation mode is arithmetic

Q1_countup[2]_lut_out = Q1_countup[2] $ Q1L23;

Q1_countup[2] = DFFEAS(Q1_countup[2]_lut_out, GLOBAL(PLD_CLOCKINPUT[1]), Q1_not_areset, , !Q1_count_done, , , , );

--Q1L26 is std_1c20:inst|connector_pll:the_connector_pll|countup[2]~597 at LC_X18_Y24_N6

--operation mode is arithmetic

Q1L26_cout_0 = !Q1L23 # !Q1_countup[2];

Q1L26 = CARRY(Q1L26_cout_0);

--Q1L27 is std_1c20:inst|connector_pll:the_connector_pll|countup[2]~597COUT1_798 at LC_X18_Y24_N6

--operation mode is arithmetic

Q1L27_cout_1 = !Q1L24 # !Q1_countup[2];

Q1L27 = CARRY(Q1L27_cout_1);

--Q1_countup[3] is std_1c20:inst|connector_pll:the_connector_pll|countup[3] at LC_X18_Y24_N7

--operation mode is arithmetic

Q1_countup[3]_lut_out = Q1_countup[3] $ (!Q1L26);

Q1_countup[3] = DFFEAS(Q1_countup[3]_lut_out, GLOBAL(PLD_CLOCKINPUT[1]), Q1_not_areset, , !Q1_count_done, , , , );

--Q1L29 is std_1c20:inst|connector_pll:the_connector_pll|countup[3]~598 at LC_X18_Y24_N7

--operation mode is arithmetic

Q1L29_cout_0 = Q1_countup[3] & (!Q1L26);

Q1L29 = CARRY(Q1L29_cout_0);

--Q1L30 is std_1c20:inst|connector_pll:the_connector_pll|countup[3]~598COUT1_800 at LC_X18_Y24_N7

--operation mode is arithmetic

Q1L30_cout_1 = Q1_countup[3] & (!Q1L27);

Q1L30 = CARRY(Q1L30_cout_1);

--Q1_countup[0] is std_1c20:inst|connector_pll:the_connector_pll|countup[0] at LC_X18_Y24_N1

--operation mode is normal

Q1_countup[0]_lut_out = Q1_countup[0] $ (!Q1_count_done);

Q1_countup[0] = DFFEAS(Q1_countup[0]_lut_out, GLOBAL(PLD_CLOCKINPUT[1]), Q1_not_areset, , , , , , );

--Q1L35 is std_1c20:inst|connector_pll:the_connector_pll|Equal0~41 at LC_X18_Y24_N0

--operation mode is normal

Q1L35 = Q1_countup[3] & Q1_countup[1] & Q1_countup[2] & Q1_countup[0];

--Q1_not_areset is std_1c20:inst|connector_pll:the_connector_pll|not_areset at LC_X18_Y24_N4

--operation mode is normal

Q1_not_areset_lut_out = VCC;

Q1_not_areset = DFFEAS(Q1_not_areset_lut_out, GLOBAL(PLD_CLOCKINPUT[1]), VCC, , , , , , );

--KB1L616 is std_1c20:inst|sdram:the_sdram|Mux40~1467 at LC_X11_Y24_N9

--operation mode is normal

KB1L616 = !KB1_m_state[5] & !KB1_m_state[1] & !KB1_m_state[7] & !KB1_m_state[2];

--KB1L617 is std_1c20:inst|sdram:the_sdram|Mux40~1468 at LC_X12_Y24_N4

--operation mode is normal

KB1L617 = !KB1_refresh_request & (!KB1L991 # !TE1L152) # !KB1L630;

--KB1L618 is std_1c20:inst|sdram:the_sdram|Mux40~1469 at LC_X12_Y24_N3

--operation mode is normal

KB1L618 = KB1_m_count[2] & (!KB1L857 # !KB1L253 # !KB1L616);

--KB1L619 is std_1c20:inst|sdram:the_sdram|Mux40~1470 at LC_X12_Y23_N2

--operation mode is normal

KB1L619 = !KB1_m_state[2] & !KB1_m_state[7] & !KB1_m_state[3] & !KB1_m_state[1];

--KB1L620 is std_1c20:inst|sdram:the_sdram|Mux40~1471 at LC_X12_Y24_N2

--operation mode is normal

KB1L620 = KB1L991 # !KB1_refresh_request # !TE1L152 # !KB1L619;

--KB1_m_count[0] is std_1c20:inst|sdram:the_sdram|m_count[0] at LC_X13_Y23_N3

--operation mode is normal

KB1_m_count[0]_lut_out = KB1_m_state[5] & (KB1L669 & (KB1_m_count[0]) # !KB1L669 & KB1L661) # !KB1_m_state[5] & (KB1L669);

KB1_m_count[0] = DFFEAS(KB1_m_count[0]_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , !KB1_m_state[6], , , , );

--KB1L623 is std_1c20:inst|sdram:the_sdram|Mux40~1474 at LC_X12_Y23_N4

--operation mode is normal

KB1L623 = KB1_m_count[2] & (KB1_m_count[0] # KB1_m_count[1] # !KB1L539);

--KB1L624 is std_1c20:inst|sdram:the_sdram|Mux40~1475 at LC_X12_Y23_N1

--operation mode is normal

KB1L624 = KB1_m_count[2] & (KB1_m_state[7] $ !KB1_m_state[1]);

--KB1L627 is std_1c20:inst|sdram:the_sdram|Mux40~1478 at LC_X12_Y23_N6

--operation mode is normal

KB1L627 = KB1L645 # KB1L643 & !KB1L634;

--KB1L628 is std_1c20:inst|sdram:the_sdram|Mux40~1479 at LC_X12_Y24_N5

--operation mode is normal

KB1L628 = KB1_m_state[4] & KB1_m_count[2] & (KB1L620 # KB1L627) # !KB1_m_state[4] & (KB1L627);

--KB1L629 is std_1c20:inst|sdram:the_sdram|Mux40~1480 at LC_X12_Y24_N6

--operation mode is normal

KB1L629 = KB1_m_state[0] & (!KB1_m_state[8] & KB1L628) # !KB1_m_state[0] & (KB1L618 # KB1_m_state[8]);

--KB1L647 is std_1c20:inst|sdram:the_sdram|Mux41~1467 at LC_X12_Y24_N8

--operation mode is normal

KB1L647 = KB1L991 # !KB1_refresh_request # !TE1L152 # !KB1L658;

--KB1L648 is std_1c20:inst|sdram:the_sdram|Mux41~1468 at LC_X11_Y24_N3

--operation mode is normal

KB1L648 = KB1_m_count[1] & (!KB1L646 # !KB1L462 # !KB1L616);

--KB1L649 is std_1c20:inst|sdram:the_sdram|Mux41~1469 at LC_X12_Y24_N0

--operation mode is normal

KB1L649 = !KB1L991 & KB1L616 & KB1_refresh_request & TE1L152;

--KB1L650 is std_1c20:inst|sdram:the_sdram|Mux41~1470 at LC_X11_Y24_N7

--operation mode is normal

KB1L650 = !KB1_m_state[2] & !KB1_m_state[5];

--KB1L651 is std_1c20:inst|sdram:the_sdram|Mux41~1471 at LC_X11_Y23_N2

--operation mode is normal

KB1L651 = KB1_m_state[1] & (KB1_m_state[2] # KB1_m_state[5]) # !KB1_m_state[1] & !KB1_m_count[0] & (KB1_m_state[2] $ KB1_m_state[5]);

--KB1L652 is std_1c20:inst|sdram:the_sdram|Mux41~1472 at LC_X11_Y23_N5

--operation mode is normal

KB1L652 = KB1L651 & (KB1_m_count[1] # KB1_m_count[2]);

--KB1L653 is std_1c20:inst|sdram:the_sdram|Mux41~1473 at LC_X11_Y23_N6

--operation mode is normal

KB1L653 = KB1_m_state[7] & KB1_m_state[1] # !KB1_m_state[7] & (KB1_m_state[1] & KB1_m_count[1] & KB1L652 # !KB1_m_state[1] & (KB1_m_count[1] $ KB1L652));

--KB1L654 is std_1c20:inst|sdram:the_sdram|Mux41~1474 at LC_X11_Y24_N5

--operation mode is normal

KB1L654 = KB1_m_state[7] & (KB1_m_count[1] # KB1L650 & !KB1L653) # !KB1_m_state[7] & (KB1L653);

--KB1L655 is std_1c20:inst|sdram:the_sdram|Mux41~1475 at LC_X11_Y24_N6

--operation mode is normal

KB1L655 = KB1_m_state[0] & KB1L654 & !KB1_m_state[3] # !KB1_m_state[0] & (KB1_m_state[3] # KB1L659);

--KB1L656 is std_1c20:inst|sdram:the_sdram|Mux41~1476 at LC_X11_Y24_N2

--operation mode is normal

KB1L656 = KB1_m_state[3] & (KB1_m_count[1] # !KB1L655 & KB1L649) # !KB1_m_state[3] & KB1L655;

--KB1L657 is std_1c20:inst|sdram:the_sdram|Mux41~1477 at LC_X11_Y24_N4

--operation mode is normal

KB1L657 = KB1_m_state[8] & (KB1_m_state[4] # KB1L648) # !KB1_m_state[8] & !KB1_m_state[4] & KB1L656;

--KB1_i_next[0] is std_1c20:inst|sdram:the_sdram|i_next[0] at LC_X9_Y22_N7

--operation mode is normal

KB1_i_next[0]_lut_out = KB1_i_state[2] # !KB1_i_refs[2] & RD1L35 & !KB1_i_refs[1];

KB1_i_next[0] = DFFEAS(KB1_i_next[0]_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , RD1L36, , , , );

--KB1_i_count[2] is std_1c20:inst|sdram:the_sdram|i_count[2] at LC_X10_Y22_N5

--operation mode is normal

KB1_i_count[2]_lut_out = KB1_i_state[0] & KB1_i_state[1] & (KB1_i_state[2] # KB1L482);

KB1_i_count[2] = DFFEAS(KB1_i_count[2]_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , KB1L483, , , , );

--KB1_i_count[1] is std_1c20:inst|sdram:the_sdram|i_count[1] at LC_X10_Y22_N7

--operation mode is normal

KB1_i_count[1]_lut_out = !KB1_i_state[2] & KB1_i_state[1] & (KB1L484 # !KB1_i_state[0]);

KB1_i_count[1] = DFFEAS(KB1_i_count[1]_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , KB1L483, , , , );

--KB1L161 is std_1c20:inst|sdram:the_sdram|LessThan0~45 at LC_X10_Y22_N8

--operation mode is normal

KB1L161 = KB1_i_count[1] # KB1_i_count[2];

--KB1L480 is std_1c20:inst|sdram:the_sdram|Mux9~225 at LC_X10_Y23_N5

--operation mode is normal

KB1L480 = !KB1_i_state[2] & (KB1_i_state[1]);

--KB1L481 is std_1c20:inst|sdram:the_sdram|Mux9~226 at LC_X10_Y22_N9

--operation mode is normal

KB1L481 = KB1_i_state[0] & (KB1L161 # KB1_i_next[0] # !KB1L480);

--KB1L151 is std_1c20:inst|sdram:the_sdram|i_refs[0]~286 at LC_X10_Y23_N2

--operation mode is normal

KB1L151 = !KB1_i_state[2] & !KB1_i_state[0];

--KB1L478 is std_1c20:inst|sdram:the_sdram|Mux7~97 at LC_X10_Y22_N6

--operation mode is normal

KB1L478 = !KB1_i_count[2] & !KB1_i_count[1] & KB1_i_next[0];

--KB1_i_next[1] is std_1c20:inst|sdram:the_sdram|i_next[1] at LC_X9_Y22_N4

--operation mode is normal

KB1_i_next[1]_lut_out = !KB1_i_state[2];

KB1_i_next[1] = DFFEAS(KB1_i_next[1]_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , RD1L36, , , , );

--KB1L479 is std_1c20:inst|sdram:the_sdram|Mux8~208 at LC_X10_Y22_N1

--operation mode is normal

KB1L479 = KB1_i_count[2] # KB1_i_count[1] # KB1_i_next[1];

--KB1L74 is std_1c20:inst|sdram:the_sdram|Add0~218 at LC_X63_Y31_N7

--operation mode is arithmetic

KB1L74_carry_eqn = (!KB1L78 & KB1L83) # (KB1L78 & KB1L84);

KB1L74 = KB1_refresh_counter[3] $ KB1L74_carry_eqn;

--KB1L75 is std_1c20:inst|sdram:the_sdram|Add0~219 at LC_X63_Y31_N7

--operation mode is arithmetic

KB1L75_cout_0 = KB1_refresh_counter[3] & !KB1L83;

KB1L75 = CARRY(KB1L75_cout_0);

--KB1L76 is std_1c20:inst|sdram:the_sdram|Add0~219COUT1_691 at LC_X63_Y31_N7

--operation mode is arithmetic

KB1L76_cout_1 = KB1_refresh_counter[3] & !KB1L84;

KB1L76 = CARRY(KB1L76_cout_1);

--KB1L77 is std_1c20:inst|sdram:the_sdram|Add0~220 at LC_X63_Y31_N4

--operation mode is arithmetic

KB1L77 = !KB1_refresh_counter[0];

--KB1L78 is std_1c20:inst|sdram:the_sdram|Add0~221 at LC_X63_Y31_N4

--operation mode is arithmetic

KB1L78 = CARRY(KB1_refresh_counter[0]);

--KB1L79 is std_1c20:inst|sdram:the_sdram|Add0~222 at LC_X63_Y31_N5

--operation mode is arithmetic

KB1L79_carry_eqn = KB1L78;

KB1L79 = KB1_refresh_counter[1] $ !KB1L79_carry_eqn;

--KB1L80 is std_1c20:inst|sdram:the_sdram|Add0~223 at LC_X63_Y31_N5

--operation mode is arithmetic

KB1L80_cout_0 = !KB1_refresh_counter[1] & !KB1L78;

KB1L80 = CARRY(KB1L80_cout_0);

--KB1L81 is std_1c20:inst|sdram:the_sdram|Add0~223COUT1_687 at LC_X63_Y31_N5

--operation mode is arithmetic

KB1L81_cout_1 = !KB1_refresh_counter[1] & !KB1L78;

KB1L81 = CARRY(KB1L81_cout_1);

--KB1L82 is std_1c20:inst|sdram:the_sdram|Add0~224 at LC_X63_Y31_N6

--operation mode is arithmetic

KB1L82_carry_eqn = (!KB1L78 & KB1L80) # (KB1L78 & KB1L81);

KB1L82 = KB1_refresh_counter[2] $ KB1L82_carry_eqn;

--KB1L83 is std_1c20:inst|sdram:the_sdram|Add0~225 at LC_X63_Y31_N6

--operation mode is arithmetic

KB1L83_cout_0 = KB1_refresh_counter[2] # !KB1L80;

KB1L83 = CARRY(KB1L83_cout_0);

--KB1L84 is std_1c20:inst|sdram:the_sdram|Add0~225COUT1_689 at LC_X63_Y31_N6

--operation mode is arithmetic

KB1L84_cout_1 = KB1_refresh_counter[2] # !KB1L81;

KB1L84 = CARRY(KB1L84_cout_1);

--KB1L85 is std_1c20:inst|sdram:the_sdram|Add0~226 at LC_X63_Y30_N1

--operation mode is arithmetic

KB1L85_carry_eqn = (!KB1L92 & KB1L94) # (KB1L92 & KB1L95);

KB1L85 = KB1_refresh_counter[7] $ KB1L85_carry_eqn;

--KB1L86 is std_1c20:inst|sdram:the_sdram|Add0~227 at LC_X63_Y30_N1

--operation mode is arithmetic

KB1L86_cout_0 = KB1_refresh_counter[7] & !KB1L94;

KB1L86 = CARRY(KB1L86_cout_0);

--KB1L87 is std_1c20:inst|sdram:the_sdram|Add0~227COUT1_697 at LC_X63_Y30_N1

--operation mode is arithmetic

KB1L87_cout_1 = KB1_refresh_counter[7] & !KB1L95;

KB1L87 = CARRY(KB1L87_cout_1);

--KB1L88 is std_1c20:inst|sdram:the_sdram|Add0~228 at LC_X63_Y31_N8

--operation mode is arithmetic

KB1L88_carry_eqn = (!KB1L78 & KB1L75) # (KB1L78 & KB1L76);

KB1L88 = KB1_refresh_counter[4] $ (KB1L88_carry_eqn);

--KB1L89 is std_1c20:inst|sdram:the_sdram|Add0~229 at LC_X63_Y31_N8

--operation mode is arithmetic

KB1L89_cout_0 = KB1_refresh_counter[4] # !KB1L75;

KB1L89 = CARRY(KB1L89_cout_0);

--KB1L90 is std_1c20:inst|sdram:the_sdram|Add0~229COUT1_693 at LC_X63_Y31_N8

--operation mode is arithmetic

KB1L90_cout_1 = KB1_refresh_counter[4] # !KB1L76;

KB1L90 = CARRY(KB1L90_cout_1);

--KB1L91 is std_1c20:inst|sdram:the_sdram|Add0~230 at LC_X63_Y31_N9

--operation mode is arithmetic

KB1L91_carry_eqn = (!KB1L78 & KB1L89) # (KB1L78 & KB1L90);

KB1L91 = KB1_refresh_counter[5] $ !KB1L91_carry_eqn;

--KB1L92 is std_1c20:inst|sdram:the_sdram|Add0~231 at LC_X63_Y31_N9

--operation mode is arithmetic

KB1L92 = CARRY(!KB1_refresh_counter[5] & !KB1L90);

--KB1L93 is std_1c20:inst|sdram:the_sdram|Add0~232 at LC_X63_Y30_N0

--operation mode is arithmetic

KB1L93_carry_eqn = KB1L92;

KB1L93 = KB1_refresh_counter[6] $ KB1L93_carry_eqn;

--KB1L94 is std_1c20:inst|sdram:the_sdram|Add0~233 at LC_X63_Y30_N0

--operation mode is arithmetic

KB1L94_cout_0 = KB1_refresh_counter[6] # !KB1L92;

KB1L94 = CARRY(KB1L94_cout_0);

--KB1L95 is std_1c20:inst|sdram:the_sdram|Add0~233COUT1_695 at LC_X63_Y30_N0

--operation mode is arithmetic

KB1L95_cout_1 = KB1_refresh_counter[6] # !KB1L92;

KB1L95 = CARRY(KB1L95_cout_1);

--KB1L96 is std_1c20:inst|sdram:the_sdram|Add0~234 at LC_X63_Y30_N6

--operation mode is normal

KB1L96_carry_eqn = (!KB1L104 & KB1L106) # (KB1L104 & KB1L107);

KB1L96 = KB1L96_carry_eqn $ !KB1_refresh_counter[12];

--KB1L97 is std_1c20:inst|sdram:the_sdram|Add0~236 at LC_X63_Y30_N2

--operation mode is arithmetic

KB1L97_carry_eqn = (!KB1L92 & KB1L86) # (KB1L92 & KB1L87);

KB1L97 = KB1_refresh_counter[8] $ (!KB1L97_carry_eqn);

--KB1L98 is std_1c20:inst|sdram:the_sdram|Add0~237 at LC_X63_Y30_N2

--operation mode is arithmetic

KB1L98_cout_0 = !KB1L86 # !KB1_refresh_counter[8];

KB1L98 = CARRY(KB1L98_cout_0);

--KB1L99 is std_1c20:inst|sdram:the_sdram|Add0~237COUT1_699 at LC_X63_Y30_N2

--operation mode is arithmetic

KB1L99_cout_1 = !KB1L87 # !KB1_refresh_counter[8];

KB1L99 = CARRY(KB1L99_cout_1);

--KB1L100 is std_1c20:inst|sdram:the_sdram|Add0~238 at LC_X63_Y30_N3

--operation mode is arithmetic

KB1L100_carry_eqn = (!KB1L92 & KB1L98) # (KB1L92 & KB1L99);

KB1L100 = KB1_refresh_counter[9] $ KB1L100_carry_eqn;

--KB1L101 is std_1c20:inst|sdram:the_sdram|Add0~239 at LC_X63_Y30_N3

--operation mode is arithmetic

KB1L101_cout_0 = KB1_refresh_counter[9] & !KB1L98;

KB1L101 = CARRY(KB1L101_cout_0);

--KB1L102 is std_1c20:inst|sdram:the_sdram|Add0~239COUT1_701 at LC_X63_Y30_N3

--operation mode is arithmetic

KB1L102_cout_1 = KB1_refresh_counter[9] & !KB1L99;

KB1L102 = CARRY(KB1L102_cout_1);

--KB1L103 is std_1c20:inst|sdram:the_sdram|Add0~240 at LC_X63_Y30_N4

--operation mode is arithmetic

KB1L103_carry_eqn = (!KB1L92 & KB1L101) # (KB1L92 & KB1L102);

KB1L103 = KB1_refresh_counter[10] $ KB1L103_carry_eqn;

--KB1L104 is std_1c20:inst|sdram:the_sdram|Add0~241 at LC_X63_Y30_N4

--operation mode is arithmetic

KB1L104 = CARRY(KB1_refresh_counter[10] # !KB1L102);

--KB1L105 is std_1c20:inst|sdram:the_sdram|Add0~242 at LC_X63_Y30_N5

--operation mode is arithmetic

KB1L105_carry_eqn = KB1L104;

KB1L105 = KB1_refresh_counter[11] $ (!KB1L105_carry_eqn);

--KB1L106 is std_1c20:inst|sdram:the_sdram|Add0~243 at LC_X63_Y30_N5

--operation mode is arithmetic

KB1L106_cout_0 = !KB1_refresh_counter[11] & (!KB1L104);

KB1L106 = CARRY(KB1L106_cout_0);

--KB1L107 is std_1c20:inst|sdram:the_sdram|Add0~243COUT1_703 at LC_X63_Y30_N5

--operation mode is arithmetic

KB1L107_cout_1 = !KB1_refresh_counter[11] & (!KB1L104);

KB1L107 = CARRY(KB1L107_cout_1);

--KB1L510 is std_1c20:inst|sdram:the_sdram|Mux21~1084 at LC_X12_Y25_N0

--operation mode is normal

KB1L510 = !KB1_m_state[2] & (KB1_m_state[7] $ !KB1_m_state[0]);

--KB1L511 is std_1c20:inst|sdram:the_sdram|Mux21~1085 at LC_X12_Y25_N2

--operation mode is normal

KB1L511 = !KB1_m_state[6] & KB1L510 & !KB1_m_state[4] & KB1L486;

--ZE1_do_load_shifter is std_1c20:inst|uart1:the_uart1|uart1_tx:the_uart1_tx|do_load_shifter at LC_X48_Y25_N0

--operation mode is normal

ZE1_do_load_shifter_lut_out = ZE1_internal_tx_ready & ZE1L37 & !ZE1_unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out[0];

ZE1_do_load_shifter = DFFEAS(ZE1_do_load_shifter_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--ZE1_baud_clk_en is std_1c20:inst|uart1:the_uart1|uart1_tx:the_uart1_tx|baud_clk_en at LC_X48_Y25_N4

--operation mode is normal

ZE1_baud_clk_en_lut_out = !ZE1_baud_rate_counter[8] & ZE1L30 & ZE1L31;

ZE1_baud_clk_en = DFFEAS(ZE1_baud_clk_en_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--ZE1L51 is std_1c20:inst|uart1:the_uart1|uart1_tx:the_uart1_tx|unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out[3]~2822 at LC_X48_Y25_N6

--operation mode is normal

ZE1L51 = ZE1_do_load_shifter # ZE1_baud_clk_en & (ZE1_unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out[0] # !ZE1L37);

--XE1_internal_tx_data[0] is std_1c20:inst|uart1:the_uart1|uart1_regs:the_uart1_regs|internal_tx_data[0] at LC_X47_Y22_N8

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

XE1_internal_tx_data[0]_lut_out = GND;

XE1_internal_tx_data[0] = DFFEAS(XE1_internal_tx_data[0]_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , XE1L64, S1_M_st_data[0], , , VCC);

--G1_edge_capture[3] is std_1c20:inst|button_pio:the_button_pio|edge_capture[3] at LC_X44_Y20_N4

--operation mode is normal

G1_edge_capture[3]_lut_out = G1L17 & (!H1_cpu_data_master_requests_button_pio_s1 # !G1L16 # !S1L1726Q);

G1_edge_capture[3] = DFFEAS(G1_edge_capture[3]_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--G1_edge_capture[1] is std_1c20:inst|button_pio:the_button_pio|edge_capture[1] at LC_X44_Y20_N3

--operation mode is normal

G1_edge_capture[1]_lut_out = G1L18 & (!H1_cpu_data_master_requests_button_pio_s1 # !G1L16 # !S1L1726Q);

G1_edge_capture[1] = DFFEAS(G1_edge_capture[1]_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--S1L2130 is std_1c20:inst|cpu:the_cpu|M_ipending_reg_nxt[2]~201 at LC_X44_Y20_N0

--operation mode is normal

S1L2130 = AMPP_FUNCTION(G1_irq_mask[1], G1_edge_capture[3], G1_irq_mask[3], G1_edge_capture[1]);

--G1_edge_capture[2] is std_1c20:inst|button_pio:the_button_pio|edge_capture[2] at LC_X45_Y20_N1

--operation mode is normal

G1_edge_capture[2]_lut_out = G1L19 & (!H1_cpu_data_master_requests_button_pio_s1 # !S1L1726Q # !G1L16);

G1_edge_capture[2] = DFFEAS(G1_edge_capture[2]_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--G1_edge_capture[0] is std_1c20:inst|button_pio:the_button_pio|edge_capture[0] at LC_X45_Y22_N3

--operation mode is normal

G1_edge_capture[0]_lut_out = G1L20 & (!H1_cpu_data_master_requests_button_pio_s1 # !S1L1726Q # !G1L16);

G1_edge_capture[0] = DFFEAS(G1_edge_capture[0]_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--S1L2131 is std_1c20:inst|cpu:the_cpu|M_ipending_reg_nxt[2]~202 at LC_X45_Y20_N2

--operation mode is normal

S1L2131 = AMPP_FUNCTION(G1_edge_capture[0], G1_irq_mask[2], G1_irq_mask[0], G1_edge_capture[2]);

--S1L1165 is std_1c20:inst|cpu:the_cpu|E_wrctl_bstatus~13 at LC_X31_Y16_N3

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

S1L1165 = AMPP_FUNCTION(S1_E_iw[8], S1_E_ctrl_wrctl_inst);

--S1_E_iw[7] is std_1c20:inst|cpu:the_cpu|E_iw[7] at LC_X31_Y16_N3

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

S1_E_iw[7] = AMPP_FUNCTION(QC2__clk0, S1_D_iw[7], F1_data_out, GND, S1_W_stall);

--S1L2099 is std_1c20:inst|cpu:the_cpu|M_ienable_reg[2]~4 at LC_X32_Y19_N4

--operation mode is normal

S1L2099 = AMPP_FUNCTION(S1L1165, S1_E_iw[6], S1L1160, S1_W_stall);

--AD1_q_b[8] is std_1c20:inst|cpu:the_cpu|cpu_ic_data_module:cpu_ic_data|altsyncram:the_altsyncram|altsyncram_qmb1:auto_generated|q_b[8] at M4K_X19_Y22

--RAM Block Operation Mode: Simple Dual-Port

--Port A Depth: 1024, Port A Width: 4, Port B Depth: 1024, Port B Width: 4

--Port A Logical Depth: 1024, Port A Logical Width: 32, Port B Logical Depth: 1024, Port B Logical Width: 32

--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered

AD1_q_b[8] = AMPP_FUNCTION(GND, GND, QC2__clk0, QC2__clk0, S1_i_readdatavalid_d1, S1_W_stall, S1L1438, S1_ic_fill_dp_offset[0], S1_ic_fill_dp_offset[1], S1_ic_fill_dp_offset[2], S1_ic_fill_line[0], S1_ic_fill_line[1], S1_ic_fill_line[2], S1_ic_fill_line[3], S1_ic_fill_line[4], S1_ic_fill_line[5], S1L1559Q, S1L1197, S1L1200, S1L1203, S1L1233, S1L1236, S1L1239, S1L1242, S1L1245, S1L1248, S1L1251, S1L1454, S1_i_readdata_d1[19], S1L1447);

--AD1_q_b[10] is std_1c20:inst|cpu:the_cpu|cpu_ic_data_module:cpu_ic_data|altsyncram:the_altsyncram|altsyncram_qmb1:auto_generated|q_b[10] at M4K_X19_Y22

AD1_q_b[10] = AMPP_FUNCTION(GND, GND, QC2__clk0, QC2__clk0, S1_i_readdatavalid_d1, S1_W_stall, S1L1438, S1_ic_fill_dp_offset[0], S1_ic_fill_dp_offset[1], S1_ic_fill_dp_offset[2], S1_ic_fill_line[0], S1_ic_fill_line[1], S1_ic_fill_line[2], S1_ic_fill_line[3], S1_ic_fill_line[4], S1_ic_fill_line[5], S1L1559Q, S1L1197, S1L1200, S1L1203, S1L1233, S1L1236, S1L1239, S1L1242, S1L1245, S1L1248, S1L1251, S1L1454, S1_i_readdata_d1[19], S1L1447);

--AD1_q_b[19] is std_1c20:inst|cpu:the_cpu|cpu_ic_data_module:cpu_ic_data|altsyncram:the_altsyncram|altsyncram_qmb1:auto_generated|q_b[19] at M4K_X19_Y22

AD1_q_b[19] = AMPP_FUNCTION(GND, GND, QC2__clk0, QC2__clk0, S1_i_readdatavalid_d1, S1_W_stall, S1L1438, S1_ic_fill_dp_offset[0], S1_ic_fill_dp_offset[1], S1_ic_fill_dp_offset[2], S1_ic_fill_line[0], S1_ic_fill_line[1], S1_ic_fill_line[2], S1_ic_fill_line[3], S1_ic_fill_line[4], S1_ic_fill_line[5], S1L1559Q, S1L1197, S1L1200, S1L1203, S1L1233, S1L1236, S1L1239, S1L1242, S1L1245, S1L1248, S1L1251, S1L1454, S1_i_readdata_d1[19], S1L1447);

--AD1_q_b[11] is std_1c20:inst|cpu:the_cpu|cpu_ic_data_module:cpu_ic_data|altsyncram:the_altsyncram|altsyncram_qmb1:auto_generated|q_b[11] at M4K_X19_Y22

AD1_q_b[11] = AMPP_FUNCTION(GND, GND, QC2__clk0, QC2__clk0, S1_i_readdatavalid_d1, S1_W_stall, S1L1438, S1_ic_fill_dp_offset[0], S1_ic_fill_dp_offset[1], S1_ic_fill_dp_offset[2], S1_ic_fill_line[0], S1_ic_fill_line[1], S1_ic_fill_line[2], S1_ic_fill_line[3], S1_ic_fill_line[4], S1_ic_fill_line[5], S1L1559Q, S1L1197, S1L1200, S1L1203, S1L1233, S1L1236, S1L1239, S1L1242, S1L1245, S1L1248, S1L1251, S1L1454, S1_i_readdata_d1[19], S1L1447);

--S1L2381 is std_1c20:inst|cpu:the_cpu|M_status_reg_pie~164 at LC_X32_Y16_N0

--operation mode is normal

S1L2381 = AMPP_FUNCTION(S1L2383Q, S1L2384Q, S1L2385Q, S1L2382Q);

--S1L2040Q is std_1c20:inst|cpu:the_cpu|M_bstatus_reg~9 at LC_X32_Y16_N0

--operation mode is normal

S1L2040Q = AMPP_FUNCTION(QC2__clk0, S1L2383Q, S1L2384Q, S1L2385Q, S1L2382Q, F1_data_out);

--S1L1708 is std_1c20:inst|cpu:the_cpu|intr_req~83 at LC_X36_Y19_N5

--operation mode is normal

S1L1708 = AMPP_FUNCTION(S1_M_ipending_reg[3], S1_M_ipending_reg[2], S1_M_ipending_reg[4], S1_M_ipending_reg[5]);

--S1_M_ipending_reg[1] is std_1c20:inst|cpu:the_cpu|M_ipending_reg[1] at LC_X41_Y19_N5

--operation mode is normal

S1_M_ipending_reg[1] = AMPP_FUNCTION(QC2__clk0, S1_M_ienable_reg[1], BB1L64, T1L514, FD1L19Q, F1_data_out);

--S1_M_ipending_reg[0] is std_1c20:inst|cpu:the_cpu|M_ipending_reg[0] at LC_X45_Y19_N1

--operation mode is normal

S1_M_ipending_reg[0] = AMPP_FUNCTION(QC2__clk0, RB1_control_register[0], RB1_timeout_occurred, FD1L14Q, S1_M_ienable_reg[0], F1_data_out);

--S1L1709 is std_1c20:inst|cpu:the_cpu|intr_req~84 at LC_X32_Y19_N7

--operation mode is normal

S1L1709 = AMPP_FUNCTION(S1_M_ipending_reg[6], S1_M_ipending_reg[0], S1_M_ipending_reg[1], S1L1708);

--S1L1257 is std_1c20:inst|cpu:the_cpu|F_iw~0 at LC_X44_Y18_N9

--operation mode is normal

S1L1257 = AMPP_FUNCTION(S1_latched_oci_tb_hbreak_req, S1_hbreak_enabled);

--AD1_q_b[7] is std_1c20:inst|cpu:the_cpu|cpu_ic_data_module:cpu_ic_data|altsyncram:the_altsyncram|altsyncram_qmb1:auto_generated|q_b[7] at M4K_X19_Y23

--RAM Block Operation Mode: Simple Dual-Port

--Port A Depth: 1024, Port A Width: 4, Port B Depth: 1024, Port B Width: 4

--Port A Logical Depth: 1024, Port A Logical Width: 32, Port B Logical Depth: 1024, Port B Logical Width: 32

--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered

AD1_q_b[7] = AMPP_FUNCTION(GND, GND, QC2__clk0, QC2__clk0, S1_i_readdatavalid_d1, S1_W_stall, S1L1434, S1_ic_fill_dp_offset[0], S1_ic_fill_dp_offset[1], S1_ic_fill_dp_offset[2], S1_ic_fill_line[0], S1_ic_fill_line[1], S1_ic_fill_line[2], S1_ic_fill_line[3], S1_ic_fill_line[4], S1_ic_fill_line[5], S1L1559Q, S1L1197, S1L1200, S1L1203, S1L1233, S1L1236, S1L1239, S1L1242, S1L1245, S1L1248, S1L1251, U1L35, S1L1466, S1_i_readdata_d1[17]);

--AD1_q_b[17] is std_1c20:inst|cpu:the_cpu|cpu_ic_data_module:cpu_ic_data|altsyncram:the_altsyncram|altsyncram_qmb1:auto_generated|q_b[17] at M4K_X19_Y23

AD1_q_b[17] = AMPP_FUNCTION(GND, GND, QC2__clk0, QC2__clk0, S1_i_readdatavalid_d1, S1_W_stall, S1L1434, S1_ic_fill_dp_offset[0], S1_ic_fill_dp_offset[1], S1_ic_fill_dp_offset[2], S1_ic_fill_line[0], S1_ic_fill_line[1], S1_ic_fill_line[2], S1_ic_fill_line[3], S1_ic_fill_line[4], S1_ic_fill_line[5], S1L1559Q, S1L1197, S1L1200, S1L1203, S1L1233, S1L1236, S1L1239, S1L1242, S1L1245, S1L1248, S1L1251, U1L35, S1L1466, S1_i_readdata_d1[17]);

--AD1_q_b[14] is std_1c20:inst|cpu:the_cpu|cpu_ic_data_module:cpu_ic_data|altsyncram:the_altsyncram|altsyncram_qmb1:auto_generated|q_b[14] at M4K_X19_Y23

AD1_q_b[14] = AMPP_FUNCTION(GND, GND, QC2__clk0, QC2__clk0, S1_i_readdatavalid_d1, S1_W_stall, S1L1434, S1_ic_fill_dp_offset[0], S1_ic_fill_dp_offset[1], S1_ic_fill_dp_offset[2], S1_ic_fill_line[0], S1_ic_fill_line[1], S1_ic_fill_line[2], S1_ic_fill_line[3], S1_ic_fill_line[4], S1_ic_fill_line[5], S1L1559Q, S1L1197, S1L1200, S1L1203, S1L1233, S1L1236, S1L1239, S1L1242, S1L1245, S1L1248, S1L1251, U1L35, S1L1466, S1_i_readdata_d1[17]);

--AD1_q_b[6] is std_1c20:inst|cpu:the_cpu|cpu_ic_data_module:cpu_ic_data|altsyncram:the_altsyncram|altsyncram_qmb1:auto_generated|q_b[6] at M4K_X19_Y23

AD1_q_b[6] = AMPP_FUNCTION(GND, GND, QC2__clk0, QC2__clk0, S1_i_readdatavalid_d1, S1_W_stall, S1L1434, S1_ic_fill_dp_offset[0], S1_ic_fill_dp_offset[1], S1_ic_fill_dp_offset[2], S1_ic_fill_line[0], S1_ic_fill_line[1], S1_ic_fill_line[2], S1_ic_fill_line[3], S1_ic_fill_line[4], S1_ic_fill_line[5], S1L1559Q, S1L1197, S1L1200, S1L1203, S1L1233, S1L1236, S1L1239, S1L1242, S1L1245, S1L1248, S1L1251, U1L35, S1L1466, S1_i_readdata_d1[17]);

--AD1_q_b[4] is std_1c20:inst|cpu:the_cpu|cpu_ic_data_module:cpu_ic_data|altsyncram:the_altsyncram|altsyncram_qmb1:auto_generated|q_b[4] at M4K_X19_Y16

--RAM Block Operation Mode: Simple Dual-Port

--Port A Depth: 1024, Port A Width: 4, Port B Depth: 1024, Port B Width: 4

--Port A Logical Depth: 1024, Port A Logical Width: 32, Port B Logical Depth: 1024, Port B Logical Width: 32

--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered

AD1_q_b[4] = AMPP_FUNCTION(GND, GND, QC2__clk0, QC2__clk0, S1_i_readdatavalid_d1, S1_W_stall, U1L29, S1_ic_fill_dp_offset[0], S1_ic_fill_dp_offset[1], S1_ic_fill_dp_offset[2], S1_ic_fill_line[0], S1_ic_fill_line[1], S1_ic_fill_line[2], S1_ic_fill_line[3], S1_ic_fill_line[4], S1_ic_fill_line[5], S1_ic_fill_line[6], S1L1197, S1L1200, S1L1203, S1L1233, S1L1236, S1L1239, S1L1242, S1L1245, S1L1248, S1L1251, S1_i_readdata_d1[27], S1_i_readdata_d1[24], S1_i_readdata_d1[20]);

--AD1_q_b[20] is std_1c20:inst|cpu:the_cpu|cpu_ic_data_module:cpu_ic_data|altsyncram:the_altsyncram|altsyncram_qmb1:auto_generated|q_b[20] at M4K_X19_Y16

AD1_q_b[20] = AMPP_FUNCTION(GND, GND, QC2__clk0, QC2__clk0, S1_i_readdatavalid_d1, S1_W_stall, U1L29, S1_ic_fill_dp_offset[0], S1_ic_fill_dp_offset[1], S1_ic_fill_dp_offset[2], S1_ic_fill_line[0], S1_ic_fill_line[1], S1_ic_fill_line[2], S1_ic_fill_line[3], S1_ic_fill_line[4], S1_ic_fill_line[5], S1_ic_fill_line[6], S1L1197, S1L1200, S1L1203, S1L1233, S1L1236, S1L1239, S1L1242, S1L1245, S1L1248, S1L1251, S1_i_readdata_d1[27], S1_i_readdata_d1[24], S1_i_readdata_d1[20]);

--AD1_q_b[24] is std_1c20:inst|cpu:the_cpu|cpu_ic_data_module:cpu_ic_data|altsyncram:the_altsyncram|altsyncram_qmb1:auto_generated|q_b[24] at M4K_X19_Y16

AD1_q_b[24] = AMPP_FUNCTION(GND, GND, QC2__clk0, QC2__clk0, S1_i_readdatavalid_d1, S1_W_stall, U1L29, S1_ic_fill_dp_offset[0], S1_ic_fill_dp_offset[1], S1_ic_fill_dp_offset[2], S1_ic_fill_line[0], S1_ic_fill_line[1], S1_ic_fill_line[2], S1_ic_fill_line[3], S1_ic_fill_line[4], S1_ic_fill_line[5], S1_ic_fill_line[6], S1L1197, S1L1200, S1L1203, S1L1233, S1L1236, S1L1239, S1L1242, S1L1245, S1L1248, S1L1251, S1_i_readdata_d1[27], S1_i_readdata_d1[24], S1_i_readdata_d1[20]);

--AD1_q_b[27] is std_1c20:inst|cpu:the_cpu|cpu_ic_data_module:cpu_ic_data|altsyncram:the_altsyncram|altsyncram_qmb1:auto_generated|q_b[27] at M4K_X19_Y16

AD1_q_b[27] = AMPP_FUNCTION(GND, GND, QC2__clk0, QC2__clk0, S1_i_readdatavalid_d1, S1_W_stall, U1L29, S1_ic_fill_dp_offset[0], S1_ic_fill_dp_offset[1], S1_ic_fill_dp_offset[2], S1_ic_fill_line[0], S1_ic_fill_line[1], S1_ic_fill_line[2], S1_ic_fill_line[3], S1_ic_fill_line[4], S1_ic_fill_line[5], S1_ic_fill_line[6], S1L1197, S1L1200, S1L1203, S1L1233, S1L1236, S1L1239, S1L1242, S1L1245, S1L1248, S1L1251, S1_i_readdata_d1[27], S1_i_readdata_d1[24], S1_i_readdata_d1[20]);

--AD1_q_b[15] is std_1c20:inst|cpu:the_cpu|cpu_ic_data_module:cpu_ic_data|altsyncram:the_altsyncram|altsyncram_qmb1:auto_generated|q_b[15] at M4K_X19_Y18

--RAM Block Operation Mode: Simple Dual-Port

--Port A Depth: 1024, Port A Width: 4, Port B Depth: 1024, Port B Width: 4

--Port A Logical Depth: 1024, Port A Logical Width: 32, Port B Logical Depth: 1024, Port B Logical Width: 32

--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered

AD1_q_b[15] = AMPP_FUNCTION(GND, GND, QC2__clk0, QC2__clk0, S1_i_readdatavalid_d1, S1_W_stall, S1L1470, S1_ic_fill_dp_offset[0], S1_ic_fill_dp_offset[1], S1_ic_fill_dp_offset[2], S1_ic_fill_line[0], S1_ic_fill_line[1], S1_ic_fill_line[2], S1_ic_fill_line[3], S1_ic_fill_line[4], S1_ic_fill_line[5], S1_ic_fill_line[6], S1L1197, S1L1200, S1L1203, S1L1233, S1L1236, S1L1239, S1L1242, S1L1245, S1L1248, S1L1251, S1_i_readdata_d1[31], S1_i_readdata_d1[16], S1_i_readdata_d1[22]);

--AD1_q_b[22] is std_1c20:inst|cpu:the_cpu|cpu_ic_data_module:cpu_ic_data|altsyncram:the_altsyncram|altsyncram_qmb1:auto_generated|q_b[22] at M4K_X19_Y18

AD1_q_b[22] = AMPP_FUNCTION(GND, GND, QC2__clk0, QC2__clk0, S1_i_readdatavalid_d1, S1_W_stall, S1L1470, S1_ic_fill_dp_offset[0], S1_ic_fill_dp_offset[1], S1_ic_fill_dp_offset[2], S1_ic_fill_line[0], S1_ic_fill_line[1], S1_ic_fill_line[2], S1_ic_fill_line[3], S1_ic_fill_line[4], S1_ic_fill_line[5], S1_ic_fill_line[6], S1L1197, S1L1200, S1L1203, S1L1233, S1L1236, S1L1239, S1L1242, S1L1245, S1L1248, S1L1251, S1_i_readdata_d1[31], S1_i_readdata_d1[16], S1_i_readdata_d1[22]);

--AD1_q_b[16] is std_1c20:inst|cpu:the_cpu|cpu_ic_data_module:cpu_ic_data|altsyncram:the_altsyncram|altsyncram_qmb1:auto_generated|q_b[16] at M4K_X19_Y18

AD1_q_b[16] = AMPP_FUNCTION(GND, GND, QC2__clk0, QC2__clk0, S1_i_readdatavalid_d1, S1_W_stall, S1L1470, S1_ic_fill_dp_offset[0], S1_ic_fill_dp_offset[1], S1_ic_fill_dp_offset[2], S1_ic_fill_line[0], S1_ic_fill_line[1], S1_ic_fill_line[2], S1_ic_fill_line[3], S1_ic_fill_line[4], S1_ic_fill_line[5], S1_ic_fill_line[6], S1L1197, S1L1200, S1L1203, S1L1233, S1L1236, S1L1239, S1L1242, S1L1245, S1L1248, S1L1251, S1_i_readdata_d1[31], S1_i_readdata_d1[16], S1_i_readdata_d1[22]);

--AD1_q_b[31] is std_1c20:inst|cpu:the_cpu|cpu_ic_data_module:cpu_ic_data|altsyncram:the_altsyncram|altsyncram_qmb1:auto_generated|q_b[31] at M4K_X19_Y18

AD1_q_b[31] = AMPP_FUNCTION(GND, GND, QC2__clk0, QC2__clk0, S1_i_readdatavalid_d1, S1_W_stall, S1L1470, S1_ic_fill_dp_offset[0], S1_ic_fill_dp_offset[1], S1_ic_fill_dp_offset[2], S1_ic_fill_line[0], S1_ic_fill_line[1], S1_ic_fill_line[2], S1_ic_fill_line[3], S1_ic_fill_line[4], S1_ic_fill_line[5], S1_ic_fill_line[6], S1L1197, S1L1200, S1L1203, S1L1233, S1L1236, S1L1239, S1L1242, S1L1245, S1L1248, S1L1251, S1_i_readdata_d1[31], S1_i_readdata_d1[16], S1_i_readdata_d1[22]);

--AD1_q_b[0] is std_1c20:inst|cpu:the_cpu|cpu_ic_data_module:cpu_ic_data|altsyncram:the_altsyncram|altsyncram_qmb1:auto_generated|q_b[0] at M4K_X19_Y24

--RAM Block Operation Mode: Simple Dual-Port

--Port A Depth: 1024, Port A Width: 4, Port B Depth: 1024, Port B Width: 4

--Port A Logical Depth: 1024, Port A Logical Width: 32, Port B Logical Depth: 1024, Port B Logical Width: 32

--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered

AD1_q_b[0] = AMPP_FUNCTION(GND, GND, QC2__clk0, QC2__clk0, S1_i_readdatavalid_d1, S1_W_stall, U1L17, S1_ic_fill_dp_offset[0], S1_ic_fill_dp_offset[1], S1_ic_fill_dp_offset[2], S1_ic_fill_line[0], S1_ic_fill_line[1], S1_ic_fill_line[2], S1_ic_fill_line[3], S1_ic_fill_line[4], S1_ic_fill_line[5], S1L1559Q, S1L1197, S1L1200, S1L1203, S1L1233, S1L1236, S1L1239, S1L1242, S1L1245, S1L1248, S1L1251, U1L20, U1L23, U1L26);

--AD1_q_b[3] is std_1c20:inst|cpu:the_cpu|cpu_ic_data_module:cpu_ic_data|altsyncram:the_altsyncram|altsyncram_qmb1:auto_generated|q_b[3] at M4K_X19_Y24

AD1_q_b[3] = AMPP_FUNCTION(GND, GND, QC2__clk0, QC2__clk0, S1_i_readdatavalid_d1, S1_W_stall, U1L17, S1_ic_fill_dp_offset[0], S1_ic_fill_dp_offset[1], S1_ic_fill_dp_offset[2], S1_ic_fill_line[0], S1_ic_fill_line[1], S1_ic_fill_line[2], S1_ic_fill_line[3], S1_ic_fill_line[4], S1_ic_fill_line[5], S1L1559Q, S1L1197, S1L1200, S1L1203, S1L1233, S1L1236, S1L1239, S1L1242, S1L1245, S1L1248, S1L1251, U1L20, U1L23, U1L26);

--AD1_q_b[2] is std_1c20:inst|cpu:the_cpu|cpu_ic_data_module:cpu_ic_data|altsyncram:the_altsyncram|altsyncram_qmb1:auto_generated|q_b[2] at M4K_X19_Y24

AD1_q_b[2] = AMPP_FUNCTION(GND, GND, QC2__clk0, QC2__clk0, S1_i_readdatavalid_d1, S1_W_stall, U1L17, S1_ic_fill_dp_offset[0], S1_ic_fill_dp_offset[1], S1_ic_fill_dp_offset[2], S1_ic_fill_line[0], S1_ic_fill_line[1], S1_ic_fill_line[2], S1_ic_fill_line[3], S1_ic_fill_line[4], S1_ic_fill_line[5], S1L1559Q, S1L1197, S1L1200, S1L1203, S1L1233, S1L1236, S1L1239, S1L1242, S1L1245, S1L1248, S1L1251, U1L20, U1L23, U1L26);

--AD1_q_b[1] is std_1c20:inst|cpu:the_cpu|cpu_ic_data_module:cpu_ic_data|altsyncram:the_altsyncram|altsyncram_qmb1:auto_generated|q_b[1] at M4K_X19_Y24

AD1_q_b[1] = AMPP_FUNCTION(GND, GND, QC2__clk0, QC2__clk0, S1_i_readdatavalid_d1, S1_W_stall, U1L17, S1_ic_fill_dp_offset[0], S1_ic_fill_dp_offset[1], S1_ic_fill_dp_offset[2], S1_ic_fill_line[0], S1_ic_fill_line[1], S1_ic_fill_line[2], S1_ic_fill_line[3], S1_ic_fill_line[4], S1_ic_fill_line[5], S1L1559Q, S1L1197, S1L1200, S1L1203, S1L1233, S1L1236, S1L1239, S1L1242, S1L1245, S1L1248, S1L1251, U1L20, U1L23, U1L26);

--AD1_q_b[5] is std_1c20:inst|cpu:the_cpu|cpu_ic_data_module:cpu_ic_data|altsyncram:the_altsyncram|altsyncram_qmb1:auto_generated|q_b[5] at M4K_X19_Y19

--RAM Block Operation Mode: Simple Dual-Port

--Port A Depth: 1024, Port A Width: 4, Port B Depth: 1024, Port B Width: 4

--Port A Logical Depth: 1024, Port A Logical Width: 32, Port B Logical Depth: 1024, Port B Logical Width: 32

--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered

AD1_q_b[5] = AMPP_FUNCTION(GND, GND, QC2__clk0, QC2__clk0, S1_i_readdatavalid_d1, S1_W_stall, U1L32, S1_ic_fill_dp_offset[0], S1_ic_fill_dp_offset[1], S1_ic_fill_dp_offset[2], S1_ic_fill_line[0], S1_ic_fill_line[1], S1_ic_fill_line[2], S1_ic_fill_line[3], S1_ic_fill_line[4], S1_ic_fill_line[5], S1_ic_fill_line[6], S1L1197, S1L1200, S1L1203, S1L1233, S1L1236, S1L1239, S1L1242, S1L1245, S1L1248, S1L1251, S1_i_readdata_d1[28], S1L1462, S1_i_readdata_d1[23]);

--AD1_q_b[23] is std_1c20:inst|cpu:the_cpu|cpu_ic_data_module:cpu_ic_data|altsyncram:the_altsyncram|altsyncram_qmb1:auto_generated|q_b[23] at M4K_X19_Y19

AD1_q_b[23] = AMPP_FUNCTION(GND, GND, QC2__clk0, QC2__clk0, S1_i_readdatavalid_d1, S1_W_stall, U1L32, S1_ic_fill_dp_offset[0], S1_ic_fill_dp_offset[1], S1_ic_fill_dp_offset[2], S1_ic_fill_line[0], S1_ic_fill_line[1], S1_ic_fill_line[2], S1_ic_fill_line[3], S1_ic_fill_line[4], S1_ic_fill_line[5], S1_ic_fill_line[6], S1L1197, S1L1200, S1L1203, S1L1233, S1L1236, S1L1239, S1L1242, S1L1245, S1L1248, S1L1251, S1_i_readdata_d1[28], S1L1462, S1_i_readdata_d1[23]);

--AD1_q_b[13] is std_1c20:inst|cpu:the_cpu|cpu_ic_data_module:cpu_ic_data|altsyncram:the_altsyncram|altsyncram_qmb1:auto_generated|q_b[13] at M4K_X19_Y19

AD1_q_b[13] = AMPP_FUNCTION(GND, GND, QC2__clk0, QC2__clk0, S1_i_readdatavalid_d1, S1_W_stall, U1L32, S1_ic_fill_dp_offset[0], S1_ic_fill_dp_offset[1], S1_ic_fill_dp_offset[2], S1_ic_fill_line[0], S1_ic_fill_line[1], S1_ic_fill_line[2], S1_ic_fill_line[3], S1_ic_fill_line[4], S1_ic_fill_line[5], S1_ic_fill_line[6], S1L1197, S1L1200, S1L1203, S1L1233, S1L1236, S1L1239, S1L1242, S1L1245, S1L1248, S1L1251, S1_i_readdata_d1[28], S1L1462, S1_i_readdata_d1[23]);

--AD1_q_b[28] is std_1c20:inst|cpu:the_cpu|cpu_ic_data_module:cpu_ic_data|altsyncram:the_altsyncram|altsyncram_qmb1:auto_generated|q_b[28] at M4K_X19_Y19

AD1_q_b[28] = AMPP_FUNCTION(GND, GND, QC2__clk0, QC2__clk0, S1_i_readdatavalid_d1, S1_W_stall, U1L32, S1_ic_fill_dp_offset[0], S1_ic_fill_dp_offset[1], S1_ic_fill_dp_offset[2], S1_ic_fill_line[0], S1_ic_fill_line[1], S1_ic_fill_line[2], S1_ic_fill_line[3], S1_ic_fill_line[4], S1_ic_fill_line[5], S1_ic_fill_line[6], S1L1197, S1L1200, S1L1203, S1L1233, S1L1236, S1L1239, S1L1242, S1L1245, S1L1248, S1L1251, S1_i_readdata_d1[28], S1L1462, S1_i_readdata_d1[23]);

--AD1_q_b[29] is std_1c20:inst|cpu:the_cpu|cpu_ic_data_module:cpu_ic_data|altsyncram:the_altsyncram|altsyncram_qmb1:auto_generated|q_b[29] at M4K_X19_Y17

--RAM Block Operation Mode: Simple Dual-Port

--Port A Depth: 1024, Port A Width: 4, Port B Depth: 1024, Port B Width: 4

--Port A Logical Depth: 1024, Port A Logical Width: 32, Port B Logical Depth: 1024, Port B Logical Width: 32

--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered

AD1_q_b[29] = AMPP_FUNCTION(GND, GND, QC2__clk0, QC2__clk0, S1_i_readdatavalid_d1, S1_W_stall, S1_i_readdata_d1[29], S1_ic_fill_dp_offset[0], S1_ic_fill_dp_offset[1], S1_ic_fill_dp_offset[2], S1_ic_fill_line[0], S1_ic_fill_line[1], S1_ic_fill_line[2], S1_ic_fill_line[3], S1_ic_fill_line[4], S1_ic_fill_line[5], S1_ic_fill_line[6], S1L1197, S1L1200, S1L1203, S1L1233, S1L1236, S1L1239, S1L1242, S1L1245, S1L1248, S1L1251, S1_i_readdata_d1[21], S1_i_readdata_d1[25], S1_i_readdata_d1[18]);

--AD1_q_b[18] is std_1c20:inst|cpu:the_cpu|cpu_ic_data_module:cpu_ic_data|altsyncram:the_altsyncram|altsyncram_qmb1:auto_generated|q_b[18] at M4K_X19_Y17

AD1_q_b[18] = AMPP_FUNCTION(GND, GND, QC2__clk0, QC2__clk0, S1_i_readdatavalid_d1, S1_W_stall, S1_i_readdata_d1[29], S1_ic_fill_dp_offset[0], S1_ic_fill_dp_offset[1], S1_ic_fill_dp_offset[2], S1_ic_fill_line[0], S1_ic_fill_line[1], S1_ic_fill_line[2], S1_ic_fill_line[3], S1_ic_fill_line[4], S1_ic_fill_line[5], S1_ic_fill_line[6], S1L1197, S1L1200, S1L1203, S1L1233, S1L1236, S1L1239, S1L1242, S1L1245, S1L1248, S1L1251, S1_i_readdata_d1[21], S1_i_readdata_d1[25], S1_i_readdata_d1[18]);

--AD1_q_b[25] is std_1c20:inst|cpu:the_cpu|cpu_ic_data_module:cpu_ic_data|altsyncram:the_altsyncram|altsyncram_qmb1:auto_generated|q_b[25] at M4K_X19_Y17

AD1_q_b[25] = AMPP_FUNCTION(GND, GND, QC2__clk0, QC2__clk0, S1_i_readdatavalid_d1, S1_W_stall, S1_i_readdata_d1[29], S1_ic_fill_dp_offset[0], S1_ic_fill_dp_offset[1], S1_ic_fill_dp_offset[2], S1_ic_fill_line[0], S1_ic_fill_line[1], S1_ic_fill_line[2], S1_ic_fill_line[3], S1_ic_fill_line[4], S1_ic_fill_line[5], S1_ic_fill_line[6], S1L1197, S1L1200, S1L1203, S1L1233, S1L1236, S1L1239, S1L1242, S1L1245, S1L1248, S1L1251, S1_i_readdata_d1[21], S1_i_readdata_d1[25], S1_i_readdata_d1[18]);

--AD1_q_b[21] is std_1c20:inst|cpu:the_cpu|cpu_ic_data_module:cpu_ic_data|altsyncram:the_altsyncram|altsyncram_qmb1:auto_generated|q_b[21] at M4K_X19_Y17

AD1_q_b[21] = AMPP_FUNCTION(GND, GND, QC2__clk0, QC2__clk0, S1_i_readdatavalid_d1, S1_W_stall, S1_i_readdata_d1[29], S1_ic_fill_dp_offset[0], S1_ic_fill_dp_offset[1], S1_ic_fill_dp_offset[2], S1_ic_fill_line[0], S1_ic_fill_line[1], S1_ic_fill_line[2], S1_ic_fill_line[3], S1_ic_fill_line[4], S1_ic_fill_line[5], S1_ic_fill_line[6], S1L1197, S1L1200, S1L1203, S1L1233, S1L1236, S1L1239, S1L1242, S1L1245, S1L1248, S1L1251, S1_i_readdata_d1[21], S1_i_readdata_d1[25], S1_i_readdata_d1[18]);

--AD1_q_b[30] is std_1c20:inst|cpu:the_cpu|cpu_ic_data_module:cpu_ic_data|altsyncram:the_altsyncram|altsyncram_qmb1:auto_generated|q_b[30] at M4K_X19_Y21

--RAM Block Operation Mode: Simple Dual-Port

--Port A Depth: 1024, Port A Width: 4, Port B Depth: 1024, Port B Width: 4

--Port A Logical Depth: 1024, Port A Logical Width: 32, Port B Logical Depth: 1024, Port B Logical Width: 32

--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered

AD1_q_b[30] = AMPP_FUNCTION(GND, GND, QC2__clk0, QC2__clk0, S1_i_readdatavalid_d1, S1_W_stall, S1_i_readdata_d1[30], S1_ic_fill_dp_offset[0], S1_ic_fill_dp_offset[1], S1_ic_fill_dp_offset[2], S1_ic_fill_line[0], S1_ic_fill_line[1], S1_ic_fill_line[2], S1_ic_fill_line[3], S1_ic_fill_line[4], S1_ic_fill_line[5], S1_ic_fill_line[6], S1L1197, S1L1200, S1L1203, S1L1233, S1L1236, S1L1239, S1L1242, S1L1245, S1L1248, S1L1251, S1L1458, S1L1442, S1_i_readdata_d1[26]);

--AD1_q_b[26] is std_1c20:inst|cpu:the_cpu|cpu_ic_data_module:cpu_ic_data|altsyncram:the_altsyncram|altsyncram_qmb1:auto_generated|q_b[26] at M4K_X19_Y21

AD1_q_b[26] = AMPP_FUNCTION(GND, GND, QC2__clk0, QC2__clk0, S1_i_readdatavalid_d1, S1_W_stall, S1_i_readdata_d1[30], S1_ic_fill_dp_offset[0], S1_ic_fill_dp_offset[1], S1_ic_fill_dp_offset[2], S1_ic_fill_line[0], S1_ic_fill_line[1], S1_ic_fill_line[2], S1_ic_fill_line[3], S1_ic_fill_line[4], S1_ic_fill_line[5], S1_ic_fill_line[6], S1L1197, S1L1200, S1L1203, S1L1233, S1L1236, S1L1239, S1L1242, S1L1245, S1L1248, S1L1251, S1L1458, S1L1442, S1_i_readdata_d1[26]);

--AD1_q_b[9] is std_1c20:inst|cpu:the_cpu|cpu_ic_data_module:cpu_ic_data|altsyncram:the_altsyncram|altsyncram_qmb1:auto_generated|q_b[9] at M4K_X19_Y21

AD1_q_b[9] = AMPP_FUNCTION(GND, GND, QC2__clk0, QC2__clk0, S1_i_readdatavalid_d1, S1_W_stall, S1_i_readdata_d1[30], S1_ic_fill_dp_offset[0], S1_ic_fill_dp_offset[1], S1_ic_fill_dp_offset[2], S1_ic_fill_line[0], S1_ic_fill_line[1], S1_ic_fill_line[2], S1_ic_fill_line[3], S1_ic_fill_line[4], S1_ic_fill_line[5], S1_ic_fill_line[6], S1L1197, S1L1200, S1L1203, S1L1233, S1L1236, S1L1239, S1L1242, S1L1245, S1L1248, S1L1251, S1L1458, S1L1442, S1_i_readdata_d1[26]);

--AD1_q_b[12] is std_1c20:inst|cpu:the_cpu|cpu_ic_data_module:cpu_ic_data|altsyncram:the_altsyncram|altsyncram_qmb1:auto_generated|q_b[12] at M4K_X19_Y21

AD1_q_b[12] = AMPP_FUNCTION(GND, GND, QC2__clk0, QC2__clk0, S1_i_readdatavalid_d1, S1_W_stall, S1_i_readdata_d1[30], S1_ic_fill_dp_offset[0], S1_ic_fill_dp_offset[1], S1_ic_fill_dp_offset[2], S1_ic_fill_line[0], S1_ic_fill_line[1], S1_ic_fill_line[2], S1_ic_fill_line[3], S1_ic_fill_line[4], S1_ic_fill_line[5], S1_ic_fill_line[6], S1L1197, S1L1200, S1L1203, S1L1233, S1L1236, S1L1239, S1L1242, S1L1245, S1L1248, S1L1251, S1L1458, S1L1442, S1_i_readdata_d1[26]);

--S1L302 is std_1c20:inst|cpu:the_cpu|D_ctrl_implicit_dst_eretaddr~147 at LC_X32_Y14_N1

--operation mode is normal

S1L302 = AMPP_FUNCTION(S1L1182, S1_D_iw[15], S1_D_iw[12], S1_D_iw[11]);

--S1L303 is std_1c20:inst|cpu:the_cpu|D_ctrl_implicit_dst_eretaddr~148 at LC_X32_Y14_N2

--operation mode is normal

S1L303 = AMPP_FUNCTION(S1L1168, S1_D_iw[13], S1L302);

--S1L304 is std_1c20:inst|cpu:the_cpu|D_ctrl_implicit_dst_eretaddr~149 at LC_X31_Y13_N5

--operation mode is normal

S1L304 = AMPP_FUNCTION(S1_D_iw[5], S1L1172, S1_D_iw[4], S1L303);

--S1L315 is std_1c20:inst|cpu:the_cpu|D_dst_regnum[3]~620 at LC_X33_Y15_N4

--operation mode is normal

S1L315 = AMPP_FUNCTION(S1_D_iw[20], S1L285, S1_D_iw[25], S1L1170);

--S1L316 is std_1c20:inst|cpu:the_cpu|D_dst_regnum[3]~621 at LC_X33_Y14_N0

--operation mode is normal

S1L316 = AMPP_FUNCTION(S1L275, S1L315, S1L304);

--S1_E_dst_regnum[3] is std_1c20:inst|cpu:the_cpu|E_dst_regnum[3] at LC_X33_Y14_N0

--operation mode is normal

S1_E_dst_regnum[3] = AMPP_FUNCTION(QC2__clk0, S1L275, S1L315, S1L304, F1_data_out, S1_W_stall);

--S1L313 is std_1c20:inst|cpu:the_cpu|D_dst_regnum[1]~622 at LC_X33_Y15_N6

--operation mode is normal

S1L313 = AMPP_FUNCTION(S1_D_iw[23], S1_D_iw[18], S1L285, S1L1170);

--S1L317 is std_1c20:inst|cpu:the_cpu|D_dst_regnum[4]~623 at LC_X33_Y15_N2

--operation mode is normal

S1L317 = AMPP_FUNCTION(S1_D_iw[21], S1L1170, S1L285, S1_D_iw[26]);

--S1L1188 is std_1c20:inst|cpu:the_cpu|Equal171~108 at LC_X33_Y14_N4

--operation mode is normal

S1L1188 = AMPP_FUNCTION(S1L275, S1L304, S1L313, S1L317);

--S1L314 is std_1c20:inst|cpu:the_cpu|D_dst_regnum[2]~624 at LC_X34_Y15_N2

--operation mode is normal

S1L314 = AMPP_FUNCTION(S1L285, S1_D_iw[19], S1L1170, S1_D_iw[24]);

--S1L312 is std_1c20:inst|cpu:the_cpu|D_dst_regnum[0]~625 at LC_X33_Y15_N3

--operation mode is normal

S1L312 = AMPP_FUNCTION(S1_D_iw[22], S1L1170, S1L285, S1_D_iw[17]);

--S1L1189 is std_1c20:inst|cpu:the_cpu|Equal171~109 at LC_X33_Y14_N8

--operation mode is normal

S1L1189 = AMPP_FUNCTION(S1L275, S1L304, S1L314, S1L312);

--S1_E_ctrl_shift_rot_right is std_1c20:inst|cpu:the_cpu|E_ctrl_shift_rot_right at LC_X38_Y14_N5

--operation mode is normal

S1_E_ctrl_shift_rot_right = AMPP_FUNCTION(QC2__clk0, S1_D_iw[14], S1L307, F1_data_out, S1_W_stall);

--G1_readdata[2] is std_1c20:inst|button_pio:the_button_pio|readdata[2] at LC_X45_Y20_N0

--operation mode is normal

G1_readdata[2]_lut_out = S1_M_alu_result[3] & (G1L31) # !S1_M_alu_result[3] & in_port_to_the_button_pio[2] & !S1L1726Q;

G1_readdata[2] = DFFEAS(G1_readdata[2]_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--XE1_readdata[2] is std_1c20:inst|uart1:the_uart1|uart1_regs:the_uart1_regs|readdata[2] at LC_X51_Y23_N2

--operation mode is normal

XE1_readdata[2]_lut_out = !S1L1738Q & (S1L1726Q & XE1L52 # !S1L1726Q & (XE1L53));

XE1_readdata[2] = DFFEAS(XE1_readdata[2]_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--WB1_cpu_data_master_granted_uart1_s1 is std_1c20:inst|uart1_s1_arbitrator:the_uart1_s1|cpu_data_master_granted_uart1_s1 at LC_X47_Y25_N9

--operation mode is normal

WB1_cpu_data_master_granted_uart1_s1 = S1_M_alu_result[6] & !S1L1743Q & SB1L2;

--H1L2 is std_1c20:inst|button_pio_s1_arbitrator:the_button_pio_s1|cpu_data_master_requests_button_pio_s1~74 at LC_X44_Y23_N2

--operation mode is normal

H1L2 = !S1L1738Q & S1_M_alu_result[6];

--RB1_readdata[2] is std_1c20:inst|sys_clk_timer:the_sys_clk_timer|readdata[2] at LC_X53_Y25_N6

--operation mode is normal

RB1_readdata[2]_lut_out = RB1L190 # RB1L191 # !RB1_period_l_register[2] & XE1L20;

RB1_readdata[2] = DFFEAS(RB1_readdata[2]_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--SB1_cpu_data_master_requests_sys_clk_timer_s1 is std_1c20:inst|sys_clk_timer_s1_arbitrator:the_sys_clk_timer_s1|cpu_data_master_requests_sys_clk_timer_s1 at LC_X47_Y25_N5

--operation mode is normal

SB1_cpu_data_master_requests_sys_clk_timer_s1 = !S1_M_alu_result[6] & !S1L1743Q & SB1L2;

--UB1L10 is std_1c20:inst|sysid_control_slave_arbitrator:the_sysid_control_slave|cpu_data_master_granted_sysid_control_slave~158 at LC_X44_Y25_N5

--operation mode is normal

UB1L10 = S1_M_alu_result[3] & S1L1738Q & (S1_internal_d_read);

--JB1_cpu_data_master_requests_reconfig_request_pio_s1 is std_1c20:inst|reconfig_request_pio_s1_arbitrator:the_reconfig_request_pio_s1|cpu_data_master_requests_reconfig_request_pio_s1 at LC_X42_Y25_N6

--operation mode is normal

JB1_cpu_data_master_requests_reconfig_request_pio_s1 = JB1L3 & (S1L1743Q);

--T1_registered_cpu_data_master_readdata[2] is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|registered_cpu_data_master_readdata[2] at LC_X45_Y26_N4

--operation mode is normal

T1_registered_cpu_data_master_readdata[2]_lut_out = T1L472 & T1L502 & (KB1_za_data[2] # !S1L1693Q);

T1_registered_cpu_data_master_readdata[2] = DFFEAS(T1_registered_cpu_data_master_readdata[2]_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--Z1_readdata[2] is std_1c20:inst|high_res_timer:the_high_res_timer|readdata[2] at LC_X54_Y25_N8

--operation mode is normal

Z1_readdata[2]_lut_out = Z1L188 # Z1L187 # !Z1_period_l_register[2] & XE1L20;

Z1_readdata[2] = DFFEAS(Z1_readdata[2]_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--AB1_cpu_data_master_requests_high_res_timer_s1 is std_1c20:inst|high_res_timer_s1_arbitrator:the_high_res_timer_s1|cpu_data_master_requests_high_res_timer_s1 at LC_X47_Y25_N0

--operation mode is normal

AB1_cpu_data_master_requests_high_res_timer_s1 = !S1_M_alu_result[6] & S1L1743Q & SB1L2;

--T1L54 is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[2]~5165 at LC_X46_Y25_N9

--operation mode is normal

T1L54 = !T1L66 & (T1L64 & !UB1L9 # !T1L64 & (!T1L62));

--EB1L18 is std_1c20:inst|lcd_display_control_slave_arbitrator:the_lcd_display_control_slave|cpu_data_master_granted_lcd_display_control_slave~123 at LC_X42_Y25_N8

--operation mode is normal

EB1L18 = !S1L1743Q & JB1L3;

--T1L55 is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[2]~5166 at LC_X47_Y24_N2

--operation mode is normal

T1L55 = T1L60 # !A1L139 & !S1L1743Q & JB1L3;

--T1L56 is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[2]~5167 at LC_X46_Y25_N1

--operation mode is normal

T1L56 = T1L55 # !T1_registered_cpu_data_master_readdata[2] & (S1L1693Q # K1_cpu_data_master_requests_clock_0_in);

--DE1_data_to_cpu[2] is std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|data_to_cpu[2] at LC_X38_Y29_N1

--operation mode is normal

DE1_data_to_cpu[2]_lut_out = !DE1L278 & (DE1L253 & DE1L109Q # !DE1L253 & (DE1L277));

DE1_data_to_cpu[2] = DFFEAS(DE1_data_to_cpu[2]_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--FE1_q_a[2] is std_1c20:inst|epcs_controller:the_epcs_controller|altsyncram:the_boot_copier_rom|altsyncram_3h31:auto_generated|q_a[2] at M4K_X49_Y23

--RAM Block Operation Mode: ROM

--Port A Depth: 128, Port A Width: 32

--Port A Logical Depth: 128, Port A Logical Width: 32

--Port A Input: Registered, Port A Output: Un-registered

FE1_q_a[2]_PORT_A_address = BUS(X1L28, DE1L21, X1L33, X1L34, X1L35, X1L36, X1L37);

FE1_q_a[2]_PORT_A_address_reg = DFFE(FE1_q_a[2]_PORT_A_address, FE1_q_a[2]_clock_0, , , );

FE1_q_a[2]_clock_0 = GLOBAL(QC2__clk0);

FE1_q_a[2]_PORT_A_data_out = MEMORY(, , FE1_q_a[2]_PORT_A_address_reg, , , , , , FE1_q_a[2]_clock_0, , , , , );

FE1_q_a[2] = FE1_q_a[2]_PORT_A_data_out[0];

--FE1_q_a[1] is std_1c20:inst|epcs_controller:the_epcs_controller|altsyncram:the_boot_copier_rom|altsyncram_3h31:auto_generated|q_a[1] at M4K_X49_Y23

FE1_q_a[2]_PORT_A_address = BUS(X1L28, DE1L21, X1L33, X1L34, X1L35, X1L36, X1L37);

FE1_q_a[2]_PORT_A_address_reg = DFFE(FE1_q_a[2]_PORT_A_address, FE1_q_a[2]_clock_0, , , );

FE1_q_a[2]_clock_0 = GLOBAL(QC2__clk0);

FE1_q_a[2]_PORT_A_data_out = MEMORY(, , FE1_q_a[2]_PORT_A_address_reg, , , , , , FE1_q_a[2]_clock_0, , , , , );

FE1_q_a[1] = FE1_q_a[2]_PORT_A_data_out[31];

--FE1_q_a[0] is std_1c20:inst|epcs_controller:the_epcs_controller|altsyncram:the_boot_copier_rom|altsyncram_3h31:auto_generated|q_a[0] at M4K_X49_Y23

FE1_q_a[2]_PORT_A_address = BUS(X1L28, DE1L21, X1L33, X1L34, X1L35, X1L36, X1L37);

FE1_q_a[2]_PORT_A_address_reg = DFFE(FE1_q_a[2]_PORT_A_address, FE1_q_a[2]_clock_0, , , );

FE1_q_a[2]_clock_0 = GLOBAL(QC2__clk0);

FE1_q_a[2]_PORT_A_data_out = MEMORY(, , FE1_q_a[2]_PORT_A_address_reg, , , , , , FE1_q_a[2]_clock_0, , , , , );

FE1_q_a[0] = FE1_q_a[2]_PORT_A_data_out[30];

--FE1_q_a[5] is std_1c20:inst|epcs_controller:the_epcs_controller|altsyncram:the_boot_copier_rom|altsyncram_3h31:auto_generated|q_a[5] at M4K_X49_Y23

FE1_q_a[2]_PORT_A_address = BUS(X1L28, DE1L21, X1L33, X1L34, X1L35, X1L36, X1L37);

FE1_q_a[2]_PORT_A_address_reg = DFFE(FE1_q_a[2]_PORT_A_address, FE1_q_a[2]_clock_0, , , );

FE1_q_a[2]_clock_0 = GLOBAL(QC2__clk0);

FE1_q_a[2]_PORT_A_data_out = MEMORY(, , FE1_q_a[2]_PORT_A_address_reg, , , , , , FE1_q_a[2]_clock_0, , , , , );

FE1_q_a[5] = FE1_q_a[2]_PORT_A_data_out[29];

--FE1_q_a[4] is std_1c20:inst|epcs_controller:the_epcs_controller|altsyncram:the_boot_copier_rom|altsyncram_3h31:auto_generated|q_a[4] at M4K_X49_Y23

FE1_q_a[2]_PORT_A_address = BUS(X1L28, DE1L21, X1L33, X1L34, X1L35, X1L36, X1L37);

FE1_q_a[2]_PORT_A_address_reg = DFFE(FE1_q_a[2]_PORT_A_address, FE1_q_a[2]_clock_0, , , );

FE1_q_a[2]_clock_0 = GLOBAL(QC2__clk0);

FE1_q_a[2]_PORT_A_data_out = MEMORY(, , FE1_q_a[2]_PORT_A_address_reg, , , , , , FE1_q_a[2]_clock_0, , , , , );

FE1_q_a[4] = FE1_q_a[2]_PORT_A_data_out[28];

--FE1_q_a[6] is std_1c20:inst|epcs_controller:the_epcs_controller|altsyncram:the_boot_copier_rom|altsyncram_3h31:auto_generated|q_a[6] at M4K_X49_Y23

FE1_q_a[2]_PORT_A_address = BUS(X1L28, DE1L21, X1L33, X1L34, X1L35, X1L36, X1L37);

FE1_q_a[2]_PORT_A_address_reg = DFFE(FE1_q_a[2]_PORT_A_address, FE1_q_a[2]_clock_0, , , );

FE1_q_a[2]_clock_0 = GLOBAL(QC2__clk0);

FE1_q_a[2]_PORT_A_data_out = MEMORY(, , FE1_q_a[2]_PORT_A_address_reg, , , , , , FE1_q_a[2]_clock_0, , , , , );

FE1_q_a[6] = FE1_q_a[2]_PORT_A_data_out[27];

--FE1_q_a[8] is std_1c20:inst|epcs_controller:the_epcs_controller|altsyncram:the_boot_copier_rom|altsyncram_3h31:auto_generated|q_a[8] at M4K_X49_Y23

FE1_q_a[2]_PORT_A_address = BUS(X1L28, DE1L21, X1L33, X1L34, X1L35, X1L36, X1L37);

FE1_q_a[2]_PORT_A_address_reg = DFFE(FE1_q_a[2]_PORT_A_address, FE1_q_a[2]_clock_0, , , );

FE1_q_a[2]_clock_0 = GLOBAL(QC2__clk0);

FE1_q_a[2]_PORT_A_data_out = MEMORY(, , FE1_q_a[2]_PORT_A_address_reg, , , , , , FE1_q_a[2]_clock_0, , , , , );

FE1_q_a[8] = FE1_q_a[2]_PORT_A_data_out[26];

--FE1_q_a[9] is std_1c20:inst|epcs_controller:the_epcs_controller|altsyncram:the_boot_copier_rom|altsyncram_3h31:auto_generated|q_a[9] at M4K_X49_Y23

FE1_q_a[2]_PORT_A_address = BUS(X1L28, DE1L21, X1L33, X1L34, X1L35, X1L36, X1L37);

FE1_q_a[2]_PORT_A_address_reg = DFFE(FE1_q_a[2]_PORT_A_address, FE1_q_a[2]_clock_0, , , );

FE1_q_a[2]_clock_0 = GLOBAL(QC2__clk0);

FE1_q_a[2]_PORT_A_data_out = MEMORY(, , FE1_q_a[2]_PORT_A_address_reg, , , , , , FE1_q_a[2]_clock_0, , , , , );

FE1_q_a[9] = FE1_q_a[2]_PORT_A_data_out[25];

--FE1_q_a[26] is std_1c20:inst|epcs_controller:the_epcs_controller|altsyncram:the_boot_copier_rom|altsyncram_3h31:auto_generated|q_a[26] at M4K_X49_Y23

FE1_q_a[2]_PORT_A_address = BUS(X1L28, DE1L21, X1L33, X1L34, X1L35, X1L36, X1L37);

FE1_q_a[2]_PORT_A_address_reg = DFFE(FE1_q_a[2]_PORT_A_address, FE1_q_a[2]_clock_0, , , );

FE1_q_a[2]_clock_0 = GLOBAL(QC2__clk0);

FE1_q_a[2]_PORT_A_data_out = MEMORY(, , FE1_q_a[2]_PORT_A_address_reg, , , , , , FE1_q_a[2]_clock_0, , , , , );

FE1_q_a[26] = FE1_q_a[2]_PORT_A_data_out[24];

--FE1_q_a[10] is std_1c20:inst|epcs_controller:the_epcs_controller|altsyncram:the_boot_copier_rom|altsyncram_3h31:auto_generated|q_a[10] at M4K_X49_Y23

FE1_q_a[2]_PORT_A_address = BUS(X1L28, DE1L21, X1L33, X1L34, X1L35, X1L36, X1L37);

FE1_q_a[2]_PORT_A_address_reg = DFFE(FE1_q_a[2]_PORT_A_address, FE1_q_a[2]_clock_0, , , );

FE1_q_a[2]_clock_0 = GLOBAL(QC2__clk0);

FE1_q_a[2]_PORT_A_data_out = MEMORY(, , FE1_q_a[2]_PORT_A_address_reg, , , , , , FE1_q_a[2]_clock_0, , , , , );

FE1_q_a[10] = FE1_q_a[2]_PORT_A_data_out[23];

--FE1_q_a[27] is std_1c20:inst|epcs_controller:the_epcs_controller|altsyncram:the_boot_copier_rom|altsyncram_3h31:auto_generated|q_a[27] at M4K_X49_Y23

FE1_q_a[2]_PORT_A_address = BUS(X1L28, DE1L21, X1L33, X1L34, X1L35, X1L36, X1L37);

FE1_q_a[2]_PORT_A_address_reg = DFFE(FE1_q_a[2]_PORT_A_address, FE1_q_a[2]_clock_0, , , );

FE1_q_a[2]_clock_0 = GLOBAL(QC2__clk0);

FE1_q_a[2]_PORT_A_data_out = MEMORY(, , FE1_q_a[2]_PORT_A_address_reg, , , , , , FE1_q_a[2]_clock_0, , , , , );

FE1_q_a[27] = FE1_q_a[2]_PORT_A_data_out[22];

--FE1_q_a[11] is std_1c20:inst|epcs_controller:the_epcs_controller|altsyncram:the_boot_copier_rom|altsyncram_3h31:auto_generated|q_a[11] at M4K_X49_Y23

FE1_q_a[2]_PORT_A_address = BUS(X1L28, DE1L21, X1L33, X1L34, X1L35, X1L36, X1L37);

FE1_q_a[2]_PORT_A_address_reg = DFFE(FE1_q_a[2]_PORT_A_address, FE1_q_a[2]_clock_0, , , );

FE1_q_a[2]_clock_0 = GLOBAL(QC2__clk0);

FE1_q_a[2]_PORT_A_data_out = MEMORY(, , FE1_q_a[2]_PORT_A_address_reg, , , , , , FE1_q_a[2]_clock_0, , , , , );

FE1_q_a[11] = FE1_q_a[2]_PORT_A_data_out[21];

--FE1_q_a[20] is std_1c20:inst|epcs_controller:the_epcs_controller|altsyncram:the_boot_copier_rom|altsyncram_3h31:auto_generated|q_a[20] at M4K_X49_Y23

FE1_q_a[2]_PORT_A_address = BUS(X1L28, DE1L21, X1L33, X1L34, X1L35, X1L36, X1L37);

FE1_q_a[2]_PORT_A_address_reg = DFFE(FE1_q_a[2]_PORT_A_address, FE1_q_a[2]_clock_0, , , );

FE1_q_a[2]_clock_0 = GLOBAL(QC2__clk0);

FE1_q_a[2]_PORT_A_data_out = MEMORY(, , FE1_q_a[2]_PORT_A_address_reg, , , , , , FE1_q_a[2]_clock_0, , , , , );

FE1_q_a[20] = FE1_q_a[2]_PORT_A_data_out[20];

--FE1_q_a[25] is std_1c20:inst|epcs_controller:the_epcs_controller|altsyncram:the_boot_copier_rom|altsyncram_3h31:auto_generated|q_a[25] at M4K_X49_Y23

FE1_q_a[2]_PORT_A_address = BUS(X1L28, DE1L21, X1L33, X1L34, X1L35, X1L36, X1L37);

FE1_q_a[2]_PORT_A_address_reg = DFFE(FE1_q_a[2]_PORT_A_address, FE1_q_a[2]_clock_0, , , );

FE1_q_a[2]_clock_0 = GLOBAL(QC2__clk0);

FE1_q_a[2]_PORT_A_data_out = MEMORY(, , FE1_q_a[2]_PORT_A_address_reg, , , , , , FE1_q_a[2]_clock_0, , , , , );

FE1_q_a[25] = FE1_q_a[2]_PORT_A_data_out[19];

--FE1_q_a[17] is std_1c20:inst|epcs_controller:the_epcs_controller|altsyncram:the_boot_copier_rom|altsyncram_3h31:auto_generated|q_a[17] at M4K_X49_Y23

FE1_q_a[2]_PORT_A_address = BUS(X1L28, DE1L21, X1L33, X1L34, X1L35, X1L36, X1L37);

FE1_q_a[2]_PORT_A_address_reg = DFFE(FE1_q_a[2]_PORT_A_address, FE1_q_a[2]_clock_0, , , );

FE1_q_a[2]_clock_0 = GLOBAL(QC2__clk0);

FE1_q_a[2]_PORT_A_data_out = MEMORY(, , FE1_q_a[2]_PORT_A_address_reg, , , , , , FE1_q_a[2]_clock_0, , , , , );

FE1_q_a[17] = FE1_q_a[2]_PORT_A_data_out[18];

--FE1_q_a[28] is std_1c20:inst|epcs_controller:the_epcs_controller|altsyncram:the_boot_copier_rom|altsyncram_3h31:auto_generated|q_a[28] at M4K_X49_Y23

FE1_q_a[2]_PORT_A_address = BUS(X1L28, DE1L21, X1L33, X1L34, X1L35, X1L36, X1L37);

FE1_q_a[2]_PORT_A_address_reg = DFFE(FE1_q_a[2]_PORT_A_address, FE1_q_a[2]_clock_0, , , );

FE1_q_a[2]_clock_0 = GLOBAL(QC2__clk0);

FE1_q_a[2]_PORT_A_data_out = MEMORY(, , FE1_q_a[2]_PORT_A_address_reg, , , , , , FE1_q_a[2]_clock_0, , , , , );

FE1_q_a[28] = FE1_q_a[2]_PORT_A_data_out[17];

--FE1_q_a[12] is std_1c20:inst|epcs_controller:the_epcs_controller|altsyncram:the_boot_copier_rom|altsyncram_3h31:auto_generated|q_a[12] at M4K_X49_Y23

FE1_q_a[2]_PORT_A_address = BUS(X1L28, DE1L21, X1L33, X1L34, X1L35, X1L36, X1L37);

FE1_q_a[2]_PORT_A_address_reg = DFFE(FE1_q_a[2]_PORT_A_address, FE1_q_a[2]_clock_0, , , );

FE1_q_a[2]_clock_0 = GLOBAL(QC2__clk0);

FE1_q_a[2]_PORT_A_data_out = MEMORY(, , FE1_q_a[2]_PORT_A_address_reg, , , , , , FE1_q_a[2]_clock_0, , , , , );

FE1_q_a[12] = FE1_q_a[2]_PORT_A_data_out[16];

--FE1_q_a[29] is std_1c20:inst|epcs_controller:the_epcs_controller|altsyncram:the_boot_copier_rom|altsyncram_3h31:auto_generated|q_a[29] at M4K_X49_Y23

FE1_q_a[2]_PORT_A_address = BUS(X1L28, DE1L21, X1L33, X1L34, X1L35, X1L36, X1L37);

FE1_q_a[2]_PORT_A_address_reg = DFFE(FE1_q_a[2]_PORT_A_address, FE1_q_a[2]_clock_0, , , );

FE1_q_a[2]_clock_0 = GLOBAL(QC2__clk0);

FE1_q_a[2]_PORT_A_data_out = MEMORY(, , FE1_q_a[2]_PORT_A_address_reg, , , , , , FE1_q_a[2]_clock_0, , , , , );

FE1_q_a[29] = FE1_q_a[2]_PORT_A_data_out[15];

--FE1_q_a[13] is std_1c20:inst|epcs_controller:the_epcs_controller|altsyncram:the_boot_copier_rom|altsyncram_3h31:auto_generated|q_a[13] at M4K_X49_Y23

FE1_q_a[2]_PORT_A_address = BUS(X1L28, DE1L21, X1L33, X1L34, X1L35, X1L36, X1L37);

FE1_q_a[2]_PORT_A_address_reg = DFFE(FE1_q_a[2]_PORT_A_address, FE1_q_a[2]_clock_0, , , );

FE1_q_a[2]_clock_0 = GLOBAL(QC2__clk0);

FE1_q_a[2]_PORT_A_data_out = MEMORY(, , FE1_q_a[2]_PORT_A_address_reg, , , , , , FE1_q_a[2]_clock_0, , , , , );

FE1_q_a[13] = FE1_q_a[2]_PORT_A_data_out[14];

--FE1_q_a[30] is std_1c20:inst|epcs_controller:the_epcs_controller|altsyncram:the_boot_copier_rom|altsyncram_3h31:auto_generated|q_a[30] at M4K_X49_Y23

FE1_q_a[2]_PORT_A_address = BUS(X1L28, DE1L21, X1L33, X1L34, X1L35, X1L36, X1L37);

FE1_q_a[2]_PORT_A_address_reg = DFFE(FE1_q_a[2]_PORT_A_address, FE1_q_a[2]_clock_0, , , );

FE1_q_a[2]_clock_0 = GLOBAL(QC2__clk0);

FE1_q_a[2]_PORT_A_data_out = MEMORY(, , FE1_q_a[2]_PORT_A_address_reg, , , , , , FE1_q_a[2]_clock_0, , , , , );

FE1_q_a[30] = FE1_q_a[2]_PORT_A_data_out[13];

--FE1_q_a[14] is std_1c20:inst|epcs_controller:the_epcs_controller|altsyncram:the_boot_copier_rom|altsyncram_3h31:auto_generated|q_a[14] at M4K_X49_Y23

FE1_q_a[2]_PORT_A_address = BUS(X1L28, DE1L21, X1L33, X1L34, X1L35, X1L36, X1L37);

FE1_q_a[2]_PORT_A_address_reg = DFFE(FE1_q_a[2]_PORT_A_address, FE1_q_a[2]_clock_0, , , );

FE1_q_a[2]_clock_0 = GLOBAL(QC2__clk0);

FE1_q_a[2]_PORT_A_data_out = MEMORY(, , FE1_q_a[2]_PORT_A_address_reg, , , , , , FE1_q_a[2]_clock_0, , , , , );

FE1_q_a[14] = FE1_q_a[2]_PORT_A_data_out[12];

--FE1_q_a[16] is std_1c20:inst|epcs_controller:the_epcs_controller|altsyncram:the_boot_copier_rom|altsyncram_3h31:auto_generated|q_a[16] at M4K_X49_Y23

FE1_q_a[2]_PORT_A_address = BUS(X1L28, DE1L21, X1L33, X1L34, X1L35, X1L36, X1L37);

FE1_q_a[2]_PORT_A_address_reg = DFFE(FE1_q_a[2]_PORT_A_address, FE1_q_a[2]_clock_0, , , );

FE1_q_a[2]_clock_0 = GLOBAL(QC2__clk0);

FE1_q_a[2]_PORT_A_data_out = MEMORY(, , FE1_q_a[2]_PORT_A_address_reg, , , , , , FE1_q_a[2]_clock_0, , , , , );

FE1_q_a[16] = FE1_q_a[2]_PORT_A_data_out[11];

--FE1_q_a[24] is std_1c20:inst|epcs_controller:the_epcs_controller|altsyncram:the_boot_copier_rom|altsyncram_3h31:auto_generated|q_a[24] at M4K_X49_Y23

FE1_q_a[2]_PORT_A_address = BUS(X1L28, DE1L21, X1L33, X1L34, X1L35, X1L36, X1L37);

FE1_q_a[2]_PORT_A_address_reg = DFFE(FE1_q_a[2]_PORT_A_address, FE1_q_a[2]_clock_0, , , );

FE1_q_a[2]_clock_0 = GLOBAL(QC2__clk0);

FE1_q_a[2]_PORT_A_data_out = MEMORY(, , FE1_q_a[2]_PORT_A_address_reg, , , , , , FE1_q_a[2]_clock_0, , , , , );

FE1_q_a[24] = FE1_q_a[2]_PORT_A_data_out[10];

--FE1_q_a[21] is std_1c20:inst|epcs_controller:the_epcs_controller|altsyncram:the_boot_copier_rom|altsyncram_3h31:auto_generated|q_a[21] at M4K_X49_Y23

FE1_q_a[2]_PORT_A_address = BUS(X1L28, DE1L21, X1L33, X1L34, X1L35, X1L36, X1L37);

FE1_q_a[2]_PORT_A_address_reg = DFFE(FE1_q_a[2]_PORT_A_address, FE1_q_a[2]_clock_0, , , );

FE1_q_a[2]_clock_0 = GLOBAL(QC2__clk0);

FE1_q_a[2]_PORT_A_data_out = MEMORY(, , FE1_q_a[2]_PORT_A_address_reg, , , , , , FE1_q_a[2]_clock_0, , , , , );

FE1_q_a[21] = FE1_q_a[2]_PORT_A_data_out[9];

--FE1_q_a[31] is std_1c20:inst|epcs_controller:the_epcs_controller|altsyncram:the_boot_copier_rom|altsyncram_3h31:auto_generated|q_a[31] at M4K_X49_Y23

FE1_q_a[2]_PORT_A_address = BUS(X1L28, DE1L21, X1L33, X1L34, X1L35, X1L36, X1L37);

FE1_q_a[2]_PORT_A_address_reg = DFFE(FE1_q_a[2]_PORT_A_address, FE1_q_a[2]_clock_0, , , );

FE1_q_a[2]_clock_0 = GLOBAL(QC2__clk0);

FE1_q_a[2]_PORT_A_data_out = MEMORY(, , FE1_q_a[2]_PORT_A_address_reg, , , , , , FE1_q_a[2]_clock_0, , , , , );

FE1_q_a[31] = FE1_q_a[2]_PORT_A_data_out[8];

--FE1_q_a[7] is std_1c20:inst|epcs_controller:the_epcs_controller|altsyncram:the_boot_copier_rom|altsyncram_3h31:auto_generated|q_a[7] at M4K_X49_Y23

FE1_q_a[2]_PORT_A_address = BUS(X1L28, DE1L21, X1L33, X1L34, X1L35, X1L36, X1L37);

FE1_q_a[2]_PORT_A_address_reg = DFFE(FE1_q_a[2]_PORT_A_address, FE1_q_a[2]_clock_0, , , );

FE1_q_a[2]_clock_0 = GLOBAL(QC2__clk0);

FE1_q_a[2]_PORT_A_data_out = MEMORY(, , FE1_q_a[2]_PORT_A_address_reg, , , , , , FE1_q_a[2]_clock_0, , , , , );

FE1_q_a[7] = FE1_q_a[2]_PORT_A_data_out[7];

--FE1_q_a[23] is std_1c20:inst|epcs_controller:the_epcs_controller|altsyncram:the_boot_copier_rom|altsyncram_3h31:auto_generated|q_a[23] at M4K_X49_Y23

FE1_q_a[2]_PORT_A_address = BUS(X1L28, DE1L21, X1L33, X1L34, X1L35, X1L36, X1L37);

FE1_q_a[2]_PORT_A_address_reg = DFFE(FE1_q_a[2]_PORT_A_address, FE1_q_a[2]_clock_0, , , );

FE1_q_a[2]_clock_0 = GLOBAL(QC2__clk0);

FE1_q_a[2]_PORT_A_data_out = MEMORY(, , FE1_q_a[2]_PORT_A_address_reg, , , , , , FE1_q_a[2]_clock_0, , , , , );

FE1_q_a[23] = FE1_q_a[2]_PORT_A_data_out[6];

--FE1_q_a[15] is std_1c20:inst|epcs_controller:the_epcs_controller|altsyncram:the_boot_copier_rom|altsyncram_3h31:auto_generated|q_a[15] at M4K_X49_Y23

FE1_q_a[2]_PORT_A_address = BUS(X1L28, DE1L21, X1L33, X1L34, X1L35, X1L36, X1L37);

FE1_q_a[2]_PORT_A_address_reg = DFFE(FE1_q_a[2]_PORT_A_address, FE1_q_a[2]_clock_0, , , );

FE1_q_a[2]_clock_0 = GLOBAL(QC2__clk0);

FE1_q_a[2]_PORT_A_data_out = MEMORY(, , FE1_q_a[2]_PORT_A_address_reg, , , , , , FE1_q_a[2]_clock_0, , , , , );

FE1_q_a[15] = FE1_q_a[2]_PORT_A_data_out[5];

--FE1_q_a[22] is std_1c20:inst|epcs_controller:the_epcs_controller|altsyncram:the_boot_copier_rom|altsyncram_3h31:auto_generated|q_a[22] at M4K_X49_Y23

FE1_q_a[2]_PORT_A_address = BUS(X1L28, DE1L21, X1L33, X1L34, X1L35, X1L36, X1L37);

FE1_q_a[2]_PORT_A_address_reg = DFFE(FE1_q_a[2]_PORT_A_address, FE1_q_a[2]_clock_0, , , );

FE1_q_a[2]_clock_0 = GLOBAL(QC2__clk0);

FE1_q_a[2]_PORT_A_data_out = MEMORY(, , FE1_q_a[2]_PORT_A_address_reg, , , , , , FE1_q_a[2]_clock_0, , , , , );

FE1_q_a[22] = FE1_q_a[2]_PORT_A_data_out[4];

--FE1_q_a[19] is std_1c20:inst|epcs_controller:the_epcs_controller|altsyncram:the_boot_copier_rom|altsyncram_3h31:auto_generated|q_a[19] at M4K_X49_Y23

FE1_q_a[2]_PORT_A_address = BUS(X1L28, DE1L21, X1L33, X1L34, X1L35, X1L36, X1L37);

FE1_q_a[2]_PORT_A_address_reg = DFFE(FE1_q_a[2]_PORT_A_address, FE1_q_a[2]_clock_0, , , );

FE1_q_a[2]_clock_0 = GLOBAL(QC2__clk0);

FE1_q_a[2]_PORT_A_data_out = MEMORY(, , FE1_q_a[2]_PORT_A_address_reg, , , , , , FE1_q_a[2]_clock_0, , , , , );

FE1_q_a[19] = FE1_q_a[2]_PORT_A_data_out[3];

--FE1_q_a[3] is std_1c20:inst|epcs_controller:the_epcs_controller|altsyncram:the_boot_copier_rom|altsyncram_3h31:auto_generated|q_a[3] at M4K_X49_Y23

FE1_q_a[2]_PORT_A_address = BUS(X1L28, DE1L21, X1L33, X1L34, X1L35, X1L36, X1L37);

FE1_q_a[2]_PORT_A_address_reg = DFFE(FE1_q_a[2]_PORT_A_address, FE1_q_a[2]_clock_0, , , );

FE1_q_a[2]_clock_0 = GLOBAL(QC2__clk0);

FE1_q_a[2]_PORT_A_data_out = MEMORY(, , FE1_q_a[2]_PORT_A_address_reg, , , , , , FE1_q_a[2]_clock_0, , , , , );

FE1_q_a[3] = FE1_q_a[2]_PORT_A_data_out[2];

--FE1_q_a[18] is std_1c20:inst|epcs_controller:the_epcs_controller|altsyncram:the_boot_copier_rom|altsyncram_3h31:auto_generated|q_a[18] at M4K_X49_Y23

FE1_q_a[2]_PORT_A_address = BUS(X1L28, DE1L21, X1L33, X1L34, X1L35, X1L36, X1L37);

FE1_q_a[2]_PORT_A_address_reg = DFFE(FE1_q_a[2]_PORT_A_address, FE1_q_a[2]_clock_0, , , );

FE1_q_a[2]_clock_0 = GLOBAL(QC2__clk0);

FE1_q_a[2]_PORT_A_data_out = MEMORY(, , FE1_q_a[2]_PORT_A_address_reg, , , , , , FE1_q_a[2]_clock_0, , , , , );

FE1_q_a[18] = FE1_q_a[2]_PORT_A_data_out[1];

--W1L1 is std_1c20:inst|epcs_controller:the_epcs_controller|epcs_select~62 at LC_X35_Y23_N4

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

S1_ic_fill_line[4]_qfbk = S1_ic_fill_line[4];

W1L1 = X1L4 & S1_M_alu_result[9] # !X1L4 & (S1_ic_fill_line[4]_qfbk & X1L8);

--S1_ic_fill_line[4] is std_1c20:inst|cpu:the_cpu|ic_fill_line[4] at LC_X35_Y23_N4

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

S1_ic_fill_line[4] = AMPP_FUNCTION(QC2__clk0, S1L1675, F1_data_out, GND);

--U1L151 is std_1c20:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_readdata~2397 at LC_X38_Y24_N4

--operation mode is normal

U1L151 = W1L1 & DE1_data_to_cpu[2] # !W1L1 & (FE1_q_a[2]);

--V1L26 is std_1c20:inst|cpu_jtag_debug_module_arbitrator:the_cpu_jtag_debug_module|cpu_jtag_debug_module_address[8]~90 at LC_X38_Y20_N0

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

S1_ic_fill_line[5]_qfbk = S1_ic_fill_line[5];

V1L26 = V1L6 & S1L1756Q # !V1L6 & (S1_ic_fill_line[5]_qfbk);

--S1_ic_fill_line[5] is std_1c20:inst|cpu:the_cpu|ic_fill_line[5] at LC_X38_Y20_N0

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

S1_ic_fill_line[5] = AMPP_FUNCTION(QC2__clk0, S1L1677, F1_data_out, GND);

--V1L17 is std_1c20:inst|cpu_jtag_debug_module_arbitrator:the_cpu_jtag_debug_module|cpu_jtag_debug_module_address[1]~91 at LC_X38_Y21_N6

--operation mode is normal

V1L17 = S1L523 & (V1L19 & (S1_ic_fill_ap_offset[1]) # !V1L19 & S1_M_alu_result[3]) # !S1L523 & (S1_ic_fill_ap_offset[1]);

--V1L25 is std_1c20:inst|cpu_jtag_debug_module_arbitrator:the_cpu_jtag_debug_module|cpu_jtag_debug_module_address[7]~92 at LC_X37_Y20_N6

--operation mode is normal

V1L25 = V1L6 & S1_M_alu_result[9] # !V1L6 & (S1_ic_fill_line[4]);

--V1L23 is std_1c20:inst|cpu_jtag_debug_module_arbitrator:the_cpu_jtag_debug_module|cpu_jtag_debug_module_address[5]~93 at LC_X34_Y20_N5

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

S1_ic_fill_line[2]_qfbk = S1_ic_fill_line[2];

V1L23 = V1L6 & S1_M_alu_result[7] # !V1L6 & (S1_ic_fill_line[2]_qfbk);

--S1_ic_fill_line[2] is std_1c20:inst|cpu:the_cpu|ic_fill_line[2] at LC_X34_Y20_N5

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

S1_ic_fill_line[2] = AMPP_FUNCTION(QC2__clk0, S1L1671, F1_data_out, GND);

--FD1L1 is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_avalon_reg:the_cpu_nios2_avalon_reg|Equal0~71 at LC_X38_Y21_N7

--operation mode is normal

FD1L1 = AMPP_FUNCTION(FD1L7, V1L6, FD1L5, V1L17);

--V1L21 is std_1c20:inst|cpu_jtag_debug_module_arbitrator:the_cpu_jtag_debug_module|cpu_jtag_debug_module_address[3]~94 at LC_X35_Y23_N8

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

S1_ic_fill_line[0]_qfbk = S1_ic_fill_line[0];

V1L21 = V1L6 & S1_M_alu_result[5] # !V1L6 & (S1_ic_fill_line[0]_qfbk);

--S1_ic_fill_line[0] is std_1c20:inst|cpu:the_cpu|ic_fill_line[0] at LC_X35_Y23_N8

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

S1_ic_fill_line[0] = AMPP_FUNCTION(QC2__clk0, S1L1560, F1_data_out, GND);

--V1L22 is std_1c20:inst|cpu_jtag_debug_module_arbitrator:the_cpu_jtag_debug_module|cpu_jtag_debug_module_address[4]~95 at LC_X33_Y20_N2

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

S1_ic_fill_line[1]_qfbk = S1_ic_fill_line[1];

V1L22 = V1L6 & S1_M_alu_result[6] # !V1L6 & (S1_ic_fill_line[1]_qfbk);

--S1_ic_fill_line[1] is std_1c20:inst|cpu:the_cpu|ic_fill_line[1] at LC_X33_Y20_N2

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

S1_ic_fill_line[1] = AMPP_FUNCTION(QC2__clk0, S1L1669, F1_data_out, GND);

--V1L24 is std_1c20:inst|cpu_jtag_debug_module_arbitrator:the_cpu_jtag_debug_module|cpu_jtag_debug_module_address[6]~96 at LC_X35_Y20_N3

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

S1_ic_fill_line[3]_qfbk = S1_ic_fill_line[3];

V1L24 = V1L6 & S1_M_alu_result[8] # !V1L6 & (S1_ic_fill_line[3]_qfbk);

--S1_ic_fill_line[3] is std_1c20:inst|cpu:the_cpu|ic_fill_line[3] at LC_X35_Y20_N3

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

S1_ic_fill_line[3] = AMPP_FUNCTION(QC2__clk0, S1L1673, F1_data_out, GND);

--V1L20 is std_1c20:inst|cpu_jtag_debug_module_arbitrator:the_cpu_jtag_debug_module|cpu_jtag_debug_module_address[2]~97 at LC_X38_Y20_N8

--operation mode is normal

V1L20 = V1L6 & (S1_M_alu_result[4]) # !V1L6 & S1_ic_fill_ap_offset[2];

--FD1L2 is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_avalon_reg:the_cpu_nios2_avalon_reg|Equal0~72 at LC_X38_Y21_N0

--operation mode is normal

FD1L2 = AMPP_FUNCTION(FD1L11, S1_ic_fill_ap_offset[2], V1L6, FD1L9);

--V1L16 is std_1c20:inst|cpu_jtag_debug_module_arbitrator:the_cpu_jtag_debug_module|cpu_jtag_debug_module_address[0]~98 at LC_X38_Y21_N5

--operation mode is normal

V1L16 = V1L6 & S1L1726Q # !V1L6 & (S1_ic_fill_ap_offset[0]);

--S1L1367Q is std_1c20:inst|cpu:the_cpu|i_readdata_d1[1]~127 at LC_X45_Y19_N5

--operation mode is normal

S1L1367Q = AMPP_FUNCTION(QC2__clk0, FD1L1, FD1L2, V1L16, F1_data_out);

--JD1_internal_monitor_go is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_debug:the_cpu_nios2_oci_debug|internal_monitor_go at LC_X46_Y18_N4

--operation mode is normal

JD1_internal_monitor_go = AMPP_FUNCTION(QC2__clk0, JD1L5, SD1_internal_jdo1[23], JD1_internal_monitor_go, FD1L38, VCC);

--CE1_q_a[0] is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|cpu_ociram_lpm_dram_bdp_component_module:cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_bp62:auto_generated|q_a[0] at M4K_X49_Y19

--RAM Block Operation Mode: True Dual-Port

--Port A Depth: 256, Port A Width: 16, Port B Depth: 256, Port B Width: 16

--Port A Logical Depth: 256, Port A Logical Width: 32, Port B Logical Depth: 256, Port B Logical Width: 32

--Port A Input: Registered, Port A Output: Un-registered, Port B Input: Registered, Port B Output: Un-registered

CE1_q_a[0] = AMPP_FUNCTION(RD1L71, RD1_MonWr, QC2__clk0, QC2__clk0, S1_M_st_data[0], S1_M_st_data[1], S1_M_st_data[2], S1_M_st_data[3], S1_M_st_data[4], S1_M_st_data[5], S1_M_st_data[6], S1_M_st_data[7], V1L16, V1L17, V1L20, V1L21, V1L22, V1L23, V1L24, V1L25, V1L47, RD1_internal_MonDReg[0], RD1_internal_MonDReg[1], RD1_internal_MonDReg[2], RD1_internal_MonDReg[3], RD1_internal_MonDReg[4], RD1_internal_MonDReg[5], RD1_internal_MonDReg[6], RD1_internal_MonDReg[7], RD1_MonAReg[2], RD1_MonAReg[3], RD1_MonAReg[4], RD1_MonAReg[5], RD1_MonAReg[6], RD1_MonAReg[7], RD1_MonAReg[8], RD1_MonAReg[9], S1L2275Q, S1L2281Q, S1L2288Q, S1L2294Q, S1L2301Q, S1L2307Q, S1L2313Q, S1L2319Q, RD1_internal_MonDReg[8], RD1_internal_MonDReg[9], RD1_internal_MonDReg[10], RD1_internal_MonDReg[11], RD1_internal_MonDReg[12], RD1_internal_MonDReg[13], RD1_internal_MonDReg[14], RD1_internal_MonDReg[15], V1L48);

--CE1_q_a[1] is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|cpu_ociram_lpm_dram_bdp_component_module:cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_bp62:auto_generated|q_a[1] at M4K_X49_Y19

CE1_q_a[1] = AMPP_FUNCTION(RD1L71, RD1_MonWr, QC2__clk0, QC2__clk0, S1_M_st_data[0], S1_M_st_data[1], S1_M_st_data[2], S1_M_st_data[3], S1_M_st_data[4], S1_M_st_data[5], S1_M_st_data[6], S1_M_st_data[7], V1L16, V1L17, V1L20, V1L21, V1L22, V1L23, V1L24, V1L25, V1L47, RD1_internal_MonDReg[0], RD1_internal_MonDReg[1], RD1_internal_MonDReg[2], RD1_internal_MonDReg[3], RD1_internal_MonDReg[4], RD1_internal_MonDReg[5], RD1_internal_MonDReg[6], RD1_internal_MonDReg[7], RD1_MonAReg[2], RD1_MonAReg[3], RD1_MonAReg[4], RD1_MonAReg[5], RD1_MonAReg[6], RD1_MonAReg[7], RD1_MonAReg[8], RD1_MonAReg[9], S1L2275Q, S1L2281Q, S1L2288Q, S1L2294Q, S1L2301Q, S1L2307Q, S1L2313Q, S1L2319Q, RD1_internal_MonDReg[8], RD1_internal_MonDReg[9], RD1_internal_MonDReg[10], RD1_internal_MonDReg[11], RD1_internal_MonDReg[12], RD1_internal_MonDReg[13], RD1_internal_MonDReg[14], RD1_internal_MonDReg[15], V1L48);

--CE1_q_a[2] is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|cpu_ociram_lpm_dram_bdp_component_module:cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_bp62:auto_generated|q_a[2] at M4K_X49_Y19

CE1_q_a[2] = AMPP_FUNCTION(RD1L71, RD1_MonWr, QC2__clk0, QC2__clk0, S1_M_st_data[0], S1_M_st_data[1], S1_M_st_data[2], S1_M_st_data[3], S1_M_st_data[4], S1_M_st_data[5], S1_M_st_data[6], S1_M_st_data[7], V1L16, V1L17, V1L20, V1L21, V1L22, V1L23, V1L24, V1L25, V1L47, RD1_internal_MonDReg[0], RD1_internal_MonDReg[1], RD1_internal_MonDReg[2], RD1_internal_MonDReg[3], RD1_internal_MonDReg[4], RD1_internal_MonDReg[5], RD1_internal_MonDReg[6], RD1_internal_MonDReg[7], RD1_MonAReg[2], RD1_MonAReg[3], RD1_MonAReg[4], RD1_MonAReg[5], RD1_MonAReg[6], RD1_MonAReg[7], RD1_MonAReg[8], RD1_MonAReg[9], S1L2275Q, S1L2281Q, S1L2288Q, S1L2294Q, S1L2301Q, S1L2307Q, S1L2313Q, S1L2319Q, RD1_internal_MonDReg[8], RD1_internal_MonDReg[9], RD1_internal_MonDReg[10], RD1_internal_MonDReg[11], RD1_internal_MonDReg[12], RD1_internal_MonDReg[13], RD1_internal_MonDReg[14], RD1_internal_MonDReg[15], V1L48);

--CE1_q_a[3] is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|cpu_ociram_lpm_dram_bdp_component_module:cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_bp62:auto_generated|q_a[3] at M4K_X49_Y19

CE1_q_a[3] = AMPP_FUNCTION(RD1L71, RD1_MonWr, QC2__clk0, QC2__clk0, S1_M_st_data[0], S1_M_st_data[1], S1_M_st_data[2], S1_M_st_data[3], S1_M_st_data[4], S1_M_st_data[5], S1_M_st_data[6], S1_M_st_data[7], V1L16, V1L17, V1L20, V1L21, V1L22, V1L23, V1L24, V1L25, V1L47, RD1_internal_MonDReg[0], RD1_internal_MonDReg[1], RD1_internal_MonDReg[2], RD1_internal_MonDReg[3], RD1_internal_MonDReg[4], RD1_internal_MonDReg[5], RD1_internal_MonDReg[6], RD1_internal_MonDReg[7], RD1_MonAReg[2], RD1_MonAReg[3], RD1_MonAReg[4], RD1_MonAReg[5], RD1_MonAReg[6], RD1_MonAReg[7], RD1_MonAReg[8], RD1_MonAReg[9], S1L2275Q, S1L2281Q, S1L2288Q, S1L2294Q, S1L2301Q, S1L2307Q, S1L2313Q, S1L2319Q, RD1_internal_MonDReg[8], RD1_internal_MonDReg[9], RD1_internal_MonDReg[10], RD1_internal_MonDReg[11], RD1_internal_MonDReg[12], RD1_internal_MonDReg[13], RD1_internal_MonDReg[14], RD1_internal_MonDReg[15], V1L48);

--CE1_q_a[4] is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|cpu_ociram_lpm_dram_bdp_component_module:cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_bp62:auto_generated|q_a[4] at M4K_X49_Y19

CE1_q_a[4] = AMPP_FUNCTION(RD1L71, RD1_MonWr, QC2__clk0, QC2__clk0, S1_M_st_data[0], S1_M_st_data[1], S1_M_st_data[2], S1_M_st_data[3], S1_M_st_data[4], S1_M_st_data[5], S1_M_st_data[6], S1_M_st_data[7], V1L16, V1L17, V1L20, V1L21, V1L22, V1L23, V1L24, V1L25, V1L47, RD1_internal_MonDReg[0], RD1_internal_MonDReg[1], RD1_internal_MonDReg[2], RD1_internal_MonDReg[3], RD1_internal_MonDReg[4], RD1_internal_MonDReg[5], RD1_internal_MonDReg[6], RD1_internal_MonDReg[7], RD1_MonAReg[2], RD1_MonAReg[3], RD1_MonAReg[4], RD1_MonAReg[5], RD1_MonAReg[6], RD1_MonAReg[7], RD1_MonAReg[8], RD1_MonAReg[9], S1L2275Q, S1L2281Q, S1L2288Q, S1L2294Q, S1L2301Q, S1L2307Q, S1L2313Q, S1L2319Q, RD1_internal_MonDReg[8], RD1_internal_MonDReg[9], RD1_internal_MonDReg[10], RD1_internal_MonDReg[11], RD1_internal_MonDReg[12], RD1_internal_MonDReg[13], RD1_internal_MonDReg[14], RD1_internal_MonDReg[15], V1L48);

--CE1_q_a[5] is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|cpu_ociram_lpm_dram_bdp_component_module:cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_bp62:auto_generated|q_a[5] at M4K_X49_Y19

CE1_q_a[5] = AMPP_FUNCTION(RD1L71, RD1_MonWr, QC2__clk0, QC2__clk0, S1_M_st_data[0], S1_M_st_data[1], S1_M_st_data[2], S1_M_st_data[3], S1_M_st_data[4], S1_M_st_data[5], S1_M_st_data[6], S1_M_st_data[7], V1L16, V1L17, V1L20, V1L21, V1L22, V1L23, V1L24, V1L25, V1L47, RD1_internal_MonDReg[0], RD1_internal_MonDReg[1], RD1_internal_MonDReg[2], RD1_internal_MonDReg[3], RD1_internal_MonDReg[4], RD1_internal_MonDReg[5], RD1_internal_MonDReg[6], RD1_internal_MonDReg[7], RD1_MonAReg[2], RD1_MonAReg[3], RD1_MonAReg[4], RD1_MonAReg[5], RD1_MonAReg[6], RD1_MonAReg[7], RD1_MonAReg[8], RD1_MonAReg[9], S1L2275Q, S1L2281Q, S1L2288Q, S1L2294Q, S1L2301Q, S1L2307Q, S1L2313Q, S1L2319Q, RD1_internal_MonDReg[8], RD1_internal_MonDReg[9], RD1_internal_MonDReg[10], RD1_internal_MonDReg[11], RD1_internal_MonDReg[12], RD1_internal_MonDReg[13], RD1_internal_MonDReg[14], RD1_internal_MonDReg[15], V1L48);

--CE1_q_a[6] is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|cpu_ociram_lpm_dram_bdp_component_module:cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_bp62:auto_generated|q_a[6] at M4K_X49_Y19

CE1_q_a[6] = AMPP_FUNCTION(RD1L71, RD1_MonWr, QC2__clk0, QC2__clk0, S1_M_st_data[0], S1_M_st_data[1], S1_M_st_data[2], S1_M_st_data[3], S1_M_st_data[4], S1_M_st_data[5], S1_M_st_data[6], S1_M_st_data[7], V1L16, V1L17, V1L20, V1L21, V1L22, V1L23, V1L24, V1L25, V1L47, RD1_internal_MonDReg[0], RD1_internal_MonDReg[1], RD1_internal_MonDReg[2], RD1_internal_MonDReg[3], RD1_internal_MonDReg[4], RD1_internal_MonDReg[5], RD1_internal_MonDReg[6], RD1_internal_MonDReg[7], RD1_MonAReg[2], RD1_MonAReg[3], RD1_MonAReg[4], RD1_MonAReg[5], RD1_MonAReg[6], RD1_MonAReg[7], RD1_MonAReg[8], RD1_MonAReg[9], S1L2275Q, S1L2281Q, S1L2288Q, S1L2294Q, S1L2301Q, S1L2307Q, S1L2313Q, S1L2319Q, RD1_internal_MonDReg[8], RD1_internal_MonDReg[9], RD1_internal_MonDReg[10], RD1_internal_MonDReg[11], RD1_internal_MonDReg[12], RD1_internal_MonDReg[13], RD1_internal_MonDReg[14], RD1_internal_MonDReg[15], V1L48);

--CE1_q_a[7] is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|cpu_ociram_lpm_dram_bdp_component_module:cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_bp62:auto_generated|q_a[7] at M4K_X49_Y19

CE1_q_a[7] = AMPP_FUNCTION(RD1L71, RD1_MonWr, QC2__clk0, QC2__clk0, S1_M_st_data[0], S1_M_st_data[1], S1_M_st_data[2], S1_M_st_data[3], S1_M_st_data[4], S1_M_st_data[5], S1_M_st_data[6], S1_M_st_data[7], V1L16, V1L17, V1L20, V1L21, V1L22, V1L23, V1L24, V1L25, V1L47, RD1_internal_MonDReg[0], RD1_internal_MonDReg[1], RD1_internal_MonDReg[2], RD1_internal_MonDReg[3], RD1_internal_MonDReg[4], RD1_internal_MonDReg[5], RD1_internal_MonDReg[6], RD1_internal_MonDReg[7], RD1_MonAReg[2], RD1_MonAReg[3], RD1_MonAReg[4], RD1_MonAReg[5], RD1_MonAReg[6], RD1_MonAReg[7], RD1_MonAReg[8], RD1_MonAReg[9], S1L2275Q, S1L2281Q, S1L2288Q, S1L2294Q, S1L2301Q, S1L2307Q, S1L2313Q, S1L2319Q, RD1_internal_MonDReg[8], RD1_internal_MonDReg[9], RD1_internal_MonDReg[10], RD1_internal_MonDReg[11], RD1_internal_MonDReg[12], RD1_internal_MonDReg[13], RD1_internal_MonDReg[14], RD1_internal_MonDReg[15], V1L48);

--CE1_q_b[0] is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|cpu_ociram_lpm_dram_bdp_component_module:cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_bp62:auto_generated|q_b[0] at M4K_X49_Y19

CE1_q_b[0] = AMPP_FUNCTION(RD1L71, RD1_MonWr, QC2__clk0, QC2__clk0, S1_M_st_data[0], S1_M_st_data[1], S1_M_st_data[2], S1_M_st_data[3], S1_M_st_data[4], S1_M_st_data[5], S1_M_st_data[6], S1_M_st_data[7], V1L16, V1L17, V1L20, V1L21, V1L22, V1L23, V1L24, V1L25, V1L47, RD1_internal_MonDReg[0], RD1_internal_MonDReg[1], RD1_internal_MonDReg[2], RD1_internal_MonDReg[3], RD1_internal_MonDReg[4], RD1_internal_MonDReg[5], RD1_internal_MonDReg[6], RD1_internal_MonDReg[7], RD1_MonAReg[2], RD1_MonAReg[3], RD1_MonAReg[4], RD1_MonAReg[5], RD1_MonAReg[6], RD1_MonAReg[7], RD1_MonAReg[8], RD1_MonAReg[9], S1L2275Q, S1L2281Q, S1L2288Q, S1L2294Q, S1L2301Q, S1L2307Q, S1L2313Q, S1L2319Q, RD1_internal_MonDReg[8], RD1_internal_MonDReg[9], RD1_internal_MonDReg[10], RD1_internal_MonDReg[11], RD1_internal_MonDReg[12], RD1_internal_MonDReg[13], RD1_internal_MonDReg[14], RD1_internal_MonDReg[15], V1L48);

--CE1_q_b[1] is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|cpu_ociram_lpm_dram_bdp_component_module:cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_bp62:auto_generated|q_b[1] at M4K_X49_Y19

CE1_q_b[1] = AMPP_FUNCTION(RD1L71, RD1_MonWr, QC2__clk0, QC2__clk0, S1_M_st_data[0], S1_M_st_data[1], S1_M_st_data[2], S1_M_st_data[3], S1_M_st_data[4], S1_M_st_data[5], S1_M_st_data[6], S1_M_st_data[7], V1L16, V1L17, V1L20, V1L21, V1L22, V1L23, V1L24, V1L25, V1L47, RD1_internal_MonDReg[0], RD1_internal_MonDReg[1], RD1_internal_MonDReg[2], RD1_internal_MonDReg[3], RD1_internal_MonDReg[4], RD1_internal_MonDReg[5], RD1_internal_MonDReg[6], RD1_internal_MonDReg[7], RD1_MonAReg[2], RD1_MonAReg[3], RD1_MonAReg[4], RD1_MonAReg[5], RD1_MonAReg[6], RD1_MonAReg[7], RD1_MonAReg[8], RD1_MonAReg[9], S1L2275Q, S1L2281Q, S1L2288Q, S1L2294Q, S1L2301Q, S1L2307Q, S1L2313Q, S1L2319Q, RD1_internal_MonDReg[8], RD1_internal_MonDReg[9], RD1_internal_MonDReg[10], RD1_internal_MonDReg[11], RD1_internal_MonDReg[12], RD1_internal_MonDReg[13], RD1_internal_MonDReg[14], RD1_internal_MonDReg[15], V1L48);

--CE1_q_b[2] is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|cpu_ociram_lpm_dram_bdp_component_module:cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_bp62:auto_generated|q_b[2] at M4K_X49_Y19

CE1_q_b[2] = AMPP_FUNCTION(RD1L71, RD1_MonWr, QC2__clk0, QC2__clk0, S1_M_st_data[0], S1_M_st_data[1], S1_M_st_data[2], S1_M_st_data[3], S1_M_st_data[4], S1_M_st_data[5], S1_M_st_data[6], S1_M_st_data[7], V1L16, V1L17, V1L20, V1L21, V1L22, V1L23, V1L24, V1L25, V1L47, RD1_internal_MonDReg[0], RD1_internal_MonDReg[1], RD1_internal_MonDReg[2], RD1_internal_MonDReg[3], RD1_internal_MonDReg[4], RD1_internal_MonDReg[5], RD1_internal_MonDReg[6], RD1_internal_MonDReg[7], RD1_MonAReg[2], RD1_MonAReg[3], RD1_MonAReg[4], RD1_MonAReg[5], RD1_MonAReg[6], RD1_MonAReg[7], RD1_MonAReg[8], RD1_MonAReg[9], S1L2275Q, S1L2281Q, S1L2288Q, S1L2294Q, S1L2301Q, S1L2307Q, S1L2313Q, S1L2319Q, RD1_internal_MonDReg[8], RD1_internal_MonDReg[9], RD1_internal_MonDReg[10], RD1_internal_MonDReg[11], RD1_internal_MonDReg[12], RD1_internal_MonDReg[13], RD1_internal_MonDReg[14], RD1_internal_MonDReg[15], V1L48);

--CE1_q_b[3] is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|cpu_ociram_lpm_dram_bdp_component_module:cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_bp62:auto_generated|q_b[3] at M4K_X49_Y19

CE1_q_b[3] = AMPP_FUNCTION(RD1L71, RD1_MonWr, QC2__clk0, QC2__clk0, S1_M_st_data[0], S1_M_st_data[1], S1_M_st_data[2], S1_M_st_data[3], S1_M_st_data[4], S1_M_st_data[5], S1_M_st_data[6], S1_M_st_data[7], V1L16, V1L17, V1L20, V1L21, V1L22, V1L23, V1L24, V1L25, V1L47, RD1_internal_MonDReg[0], RD1_internal_MonDReg[1], RD1_internal_MonDReg[2], RD1_internal_MonDReg[3], RD1_internal_MonDReg[4], RD1_internal_MonDReg[5], RD1_internal_MonDReg[6], RD1_internal_MonDReg[7], RD1_MonAReg[2], RD1_MonAReg[3], RD1_MonAReg[4], RD1_MonAReg[5], RD1_MonAReg[6], RD1_MonAReg[7], RD1_MonAReg[8], RD1_MonAReg[9], S1L2275Q, S1L2281Q, S1L2288Q, S1L2294Q, S1L2301Q, S1L2307Q, S1L2313Q, S1L2319Q, RD1_internal_MonDReg[8], RD1_internal_MonDReg[9], RD1_internal_MonDReg[10], RD1_internal_MonDReg[11], RD1_internal_MonDReg[12], RD1_internal_MonDReg[13], RD1_internal_MonDReg[14], RD1_internal_MonDReg[15], V1L48);

--CE1_q_b[4] is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|cpu_ociram_lpm_dram_bdp_component_module:cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_bp62:auto_generated|q_b[4] at M4K_X49_Y19

CE1_q_b[4] = AMPP_FUNCTION(RD1L71, RD1_MonWr, QC2__clk0, QC2__clk0, S1_M_st_data[0], S1_M_st_data[1], S1_M_st_data[2], S1_M_st_data[3], S1_M_st_data[4], S1_M_st_data[5], S1_M_st_data[6], S1_M_st_data[7], V1L16, V1L17, V1L20, V1L21, V1L22, V1L23, V1L24, V1L25, V1L47, RD1_internal_MonDReg[0], RD1_internal_MonDReg[1], RD1_internal_MonDReg[2], RD1_internal_MonDReg[3], RD1_internal_MonDReg[4], RD1_internal_MonDReg[5], RD1_internal_MonDReg[6], RD1_internal_MonDReg[7], RD1_MonAReg[2], RD1_MonAReg[3], RD1_MonAReg[4], RD1_MonAReg[5], RD1_MonAReg[6], RD1_MonAReg[7], RD1_MonAReg[8], RD1_MonAReg[9], S1L2275Q, S1L2281Q, S1L2288Q, S1L2294Q, S1L2301Q, S1L2307Q, S1L2313Q, S1L2319Q, RD1_internal_MonDReg[8], RD1_internal_MonDReg[9], RD1_internal_MonDReg[10], RD1_internal_MonDReg[11], RD1_internal_MonDReg[12], RD1_internal_MonDReg[13], RD1_internal_MonDReg[14], RD1_internal_MonDReg[15], V1L48);

--CE1_q_b[5] is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|cpu_ociram_lpm_dram_bdp_component_module:cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_bp62:auto_generated|q_b[5] at M4K_X49_Y19

CE1_q_b[5] = AMPP_FUNCTION(RD1L71, RD1_MonWr, QC2__clk0, QC2__clk0, S1_M_st_data[0], S1_M_st_data[1], S1_M_st_data[2], S1_M_st_data[3], S1_M_st_data[4], S1_M_st_data[5], S1_M_st_data[6], S1_M_st_data[7], V1L16, V1L17, V1L20, V1L21, V1L22, V1L23, V1L24, V1L25, V1L47, RD1_internal_MonDReg[0], RD1_internal_MonDReg[1], RD1_internal_MonDReg[2], RD1_internal_MonDReg[3], RD1_internal_MonDReg[4], RD1_internal_MonDReg[5], RD1_internal_MonDReg[6], RD1_internal_MonDReg[7], RD1_MonAReg[2], RD1_MonAReg[3], RD1_MonAReg[4], RD1_MonAReg[5], RD1_MonAReg[6], RD1_MonAReg[7], RD1_MonAReg[8], RD1_MonAReg[9], S1L2275Q, S1L2281Q, S1L2288Q, S1L2294Q, S1L2301Q, S1L2307Q, S1L2313Q, S1L2319Q, RD1_internal_MonDReg[8], RD1_internal_MonDReg[9], RD1_internal_MonDReg[10], RD1_internal_MonDReg[11], RD1_internal_MonDReg[12], RD1_internal_MonDReg[13], RD1_internal_MonDReg[14], RD1_internal_MonDReg[15], V1L48);

--CE1_q_b[6] is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|cpu_ociram_lpm_dram_bdp_component_module:cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_bp62:auto_generated|q_b[6] at M4K_X49_Y19

CE1_q_b[6] = AMPP_FUNCTION(RD1L71, RD1_MonWr, QC2__clk0, QC2__clk0, S1_M_st_data[0], S1_M_st_data[1], S1_M_st_data[2], S1_M_st_data[3], S1_M_st_data[4], S1_M_st_data[5], S1_M_st_data[6], S1_M_st_data[7], V1L16, V1L17, V1L20, V1L21, V1L22, V1L23, V1L24, V1L25, V1L47, RD1_internal_MonDReg[0], RD1_internal_MonDReg[1], RD1_internal_MonDReg[2], RD1_internal_MonDReg[3], RD1_internal_MonDReg[4], RD1_internal_MonDReg[5], RD1_internal_MonDReg[6], RD1_internal_MonDReg[7], RD1_MonAReg[2], RD1_MonAReg[3], RD1_MonAReg[4], RD1_MonAReg[5], RD1_MonAReg[6], RD1_MonAReg[7], RD1_MonAReg[8], RD1_MonAReg[9], S1L2275Q, S1L2281Q, S1L2288Q, S1L2294Q, S1L2301Q, S1L2307Q, S1L2313Q, S1L2319Q, RD1_internal_MonDReg[8], RD1_internal_MonDReg[9], RD1_internal_MonDReg[10], RD1_internal_MonDReg[11], RD1_internal_MonDReg[12], RD1_internal_MonDReg[13], RD1_internal_MonDReg[14], RD1_internal_MonDReg[15], V1L48);

--CE1_q_b[7] is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|cpu_ociram_lpm_dram_bdp_component_module:cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_bp62:auto_generated|q_b[7] at M4K_X49_Y19

CE1_q_b[7] = AMPP_FUNCTION(RD1L71, RD1_MonWr, QC2__clk0, QC2__clk0, S1_M_st_data[0], S1_M_st_data[1], S1_M_st_data[2], S1_M_st_data[3], S1_M_st_data[4], S1_M_st_data[5], S1_M_st_data[6], S1_M_st_data[7], V1L16, V1L17, V1L20, V1L21, V1L22, V1L23, V1L24, V1L25, V1L47, RD1_internal_MonDReg[0], RD1_internal_MonDReg[1], RD1_internal_MonDReg[2], RD1_internal_MonDReg[3], RD1_internal_MonDReg[4], RD1_internal_MonDReg[5], RD1_internal_MonDReg[6], RD1_internal_MonDReg[7], RD1_MonAReg[2], RD1_MonAReg[3], RD1_MonAReg[4], RD1_MonAReg[5], RD1_MonAReg[6], RD1_MonAReg[7], RD1_MonAReg[8], RD1_MonAReg[9], S1L2275Q, S1L2281Q, S1L2288Q, S1L2294Q, S1L2301Q, S1L2307Q, S1L2313Q, S1L2319Q, RD1_internal_MonDReg[8], RD1_internal_MonDReg[9], RD1_internal_MonDReg[10], RD1_internal_MonDReg[11], RD1_internal_MonDReg[12], RD1_internal_MonDReg[13], RD1_internal_MonDReg[14], RD1_internal_MonDReg[15], V1L48);

--CE1_q_a[15] is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|cpu_ociram_lpm_dram_bdp_component_module:cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_bp62:auto_generated|q_a[15] at M4K_X49_Y19

CE1_q_a[15] = AMPP_FUNCTION(RD1L71, RD1_MonWr, QC2__clk0, QC2__clk0, S1_M_st_data[0], S1_M_st_data[1], S1_M_st_data[2], S1_M_st_data[3], S1_M_st_data[4], S1_M_st_data[5], S1_M_st_data[6], S1_M_st_data[7], V1L16, V1L17, V1L20, V1L21, V1L22, V1L23, V1L24, V1L25, V1L47, RD1_internal_MonDReg[0], RD1_internal_MonDReg[1], RD1_internal_MonDReg[2], RD1_internal_MonDReg[3], RD1_internal_MonDReg[4], RD1_internal_MonDReg[5], RD1_internal_MonDReg[6], RD1_internal_MonDReg[7], RD1_MonAReg[2], RD1_MonAReg[3], RD1_MonAReg[4], RD1_MonAReg[5], RD1_MonAReg[6], RD1_MonAReg[7], RD1_MonAReg[8], RD1_MonAReg[9], S1L2275Q, S1L2281Q, S1L2288Q, S1L2294Q, S1L2301Q, S1L2307Q, S1L2313Q, S1L2319Q, RD1_internal_MonDReg[8], RD1_internal_MonDReg[9], RD1_internal_MonDReg[10], RD1_internal_MonDReg[11], RD1_internal_MonDReg[12], RD1_internal_MonDReg[13], RD1_internal_MonDReg[14], RD1_internal_MonDReg[15], V1L48);

--CE1_q_a[14] is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|cpu_ociram_lpm_dram_bdp_component_module:cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_bp62:auto_generated|q_a[14] at M4K_X49_Y19

CE1_q_a[14] = AMPP_FUNCTION(RD1L71, RD1_MonWr, QC2__clk0, QC2__clk0, S1_M_st_data[0], S1_M_st_data[1], S1_M_st_data[2], S1_M_st_data[3], S1_M_st_data[4], S1_M_st_data[5], S1_M_st_data[6], S1_M_st_data[7], V1L16, V1L17, V1L20, V1L21, V1L22, V1L23, V1L24, V1L25, V1L47, RD1_internal_MonDReg[0], RD1_internal_MonDReg[1], RD1_internal_MonDReg[2], RD1_internal_MonDReg[3], RD1_internal_MonDReg[4], RD1_internal_MonDReg[5], RD1_internal_MonDReg[6], RD1_internal_MonDReg[7], RD1_MonAReg[2], RD1_MonAReg[3], RD1_MonAReg[4], RD1_MonAReg[5], RD1_MonAReg[6], RD1_MonAReg[7], RD1_MonAReg[8], RD1_MonAReg[9], S1L2275Q, S1L2281Q, S1L2288Q, S1L2294Q, S1L2301Q, S1L2307Q, S1L2313Q, S1L2319Q, RD1_internal_MonDReg[8], RD1_internal_MonDReg[9], RD1_internal_MonDReg[10], RD1_internal_MonDReg[11], RD1_internal_MonDReg[12], RD1_internal_MonDReg[13], RD1_internal_MonDReg[14], RD1_internal_MonDReg[15], V1L48);

--CE1_q_a[13] is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|cpu_ociram_lpm_dram_bdp_component_module:cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_bp62:auto_generated|q_a[13] at M4K_X49_Y19

CE1_q_a[13] = AMPP_FUNCTION(RD1L71, RD1_MonWr, QC2__clk0, QC2__clk0, S1_M_st_data[0], S1_M_st_data[1], S1_M_st_data[2], S1_M_st_data[3], S1_M_st_data[4], S1_M_st_data[5], S1_M_st_data[6], S1_M_st_data[7], V1L16, V1L17, V1L20, V1L21, V1L22, V1L23, V1L24, V1L25, V1L47, RD1_internal_MonDReg[0], RD1_internal_MonDReg[1], RD1_internal_MonDReg[2], RD1_internal_MonDReg[3], RD1_internal_MonDReg[4], RD1_internal_MonDReg[5], RD1_internal_MonDReg[6], RD1_internal_MonDReg[7], RD1_MonAReg[2], RD1_MonAReg[3], RD1_MonAReg[4], RD1_MonAReg[5], RD1_MonAReg[6], RD1_MonAReg[7], RD1_MonAReg[8], RD1_MonAReg[9], S1L2275Q, S1L2281Q, S1L2288Q, S1L2294Q, S1L2301Q, S1L2307Q, S1L2313Q, S1L2319Q, RD1_internal_MonDReg[8], RD1_internal_MonDReg[9], RD1_internal_MonDReg[10], RD1_internal_MonDReg[11], RD1_internal_MonDReg[12], RD1_internal_MonDReg[13], RD1_internal_MonDReg[14], RD1_internal_MonDReg[15], V1L48);

--CE1_q_a[12] is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|cpu_ociram_lpm_dram_bdp_component_module:cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_bp62:auto_generated|q_a[12] at M4K_X49_Y19

CE1_q_a[12] = AMPP_FUNCTION(RD1L71, RD1_MonWr, QC2__clk0, QC2__clk0, S1_M_st_data[0], S1_M_st_data[1], S1_M_st_data[2], S1_M_st_data[3], S1_M_st_data[4], S1_M_st_data[5], S1_M_st_data[6], S1_M_st_data[7], V1L16, V1L17, V1L20, V1L21, V1L22, V1L23, V1L24, V1L25, V1L47, RD1_internal_MonDReg[0], RD1_internal_MonDReg[1], RD1_internal_MonDReg[2], RD1_internal_MonDReg[3], RD1_internal_MonDReg[4], RD1_internal_MonDReg[5], RD1_internal_MonDReg[6], RD1_internal_MonDReg[7], RD1_MonAReg[2], RD1_MonAReg[3], RD1_MonAReg[4], RD1_MonAReg[5], RD1_MonAReg[6], RD1_MonAReg[7], RD1_MonAReg[8], RD1_MonAReg[9], S1L2275Q, S1L2281Q, S1L2288Q, S1L2294Q, S1L2301Q, S1L2307Q, S1L2313Q, S1L2319Q, RD1_internal_MonDReg[8], RD1_internal_MonDReg[9], RD1_internal_MonDReg[10], RD1_internal_MonDReg[11], RD1_internal_MonDReg[12], RD1_internal_MonDReg[13], RD1_internal_MonDReg[14], RD1_internal_MonDReg[15], V1L48);

--CE1_q_a[11] is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|cpu_ociram_lpm_dram_bdp_component_module:cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_bp62:auto_generated|q_a[11] at M4K_X49_Y19

CE1_q_a[11] = AMPP_FUNCTION(RD1L71, RD1_MonWr, QC2__clk0, QC2__clk0, S1_M_st_data[0], S1_M_st_data[1], S1_M_st_data[2], S1_M_st_data[3], S1_M_st_data[4], S1_M_st_data[5], S1_M_st_data[6], S1_M_st_data[7], V1L16, V1L17, V1L20, V1L21, V1L22, V1L23, V1L24, V1L25, V1L47, RD1_internal_MonDReg[0], RD1_internal_MonDReg[1], RD1_internal_MonDReg[2], RD1_internal_MonDReg[3], RD1_internal_MonDReg[4], RD1_internal_MonDReg[5], RD1_internal_MonDReg[6], RD1_internal_MonDReg[7], RD1_MonAReg[2], RD1_MonAReg[3], RD1_MonAReg[4], RD1_MonAReg[5], RD1_MonAReg[6], RD1_MonAReg[7], RD1_MonAReg[8], RD1_MonAReg[9], S1L2275Q, S1L2281Q, S1L2288Q, S1L2294Q, S1L2301Q, S1L2307Q, S1L2313Q, S1L2319Q, RD1_internal_MonDReg[8], RD1_internal_MonDReg[9], RD1_internal_MonDReg[10], RD1_internal_MonDReg[11], RD1_internal_MonDReg[12], RD1_internal_MonDReg[13], RD1_internal_MonDReg[14], RD1_internal_MonDReg[15], V1L48);

--CE1_q_a[10] is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|cpu_ociram_lpm_dram_bdp_component_module:cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_bp62:auto_generated|q_a[10] at M4K_X49_Y19

CE1_q_a[10] = AMPP_FUNCTION(RD1L71, RD1_MonWr, QC2__clk0, QC2__clk0, S1_M_st_data[0], S1_M_st_data[1], S1_M_st_data[2], S1_M_st_data[3], S1_M_st_data[4], S1_M_st_data[5], S1_M_st_data[6], S1_M_st_data[7], V1L16, V1L17, V1L20, V1L21, V1L22, V1L23, V1L24, V1L25, V1L47, RD1_internal_MonDReg[0], RD1_internal_MonDReg[1], RD1_internal_MonDReg[2], RD1_internal_MonDReg[3], RD1_internal_MonDReg[4], RD1_internal_MonDReg[5], RD1_internal_MonDReg[6], RD1_internal_MonDReg[7], RD1_MonAReg[2], RD1_MonAReg[3], RD1_MonAReg[4], RD1_MonAReg[5], RD1_MonAReg[6], RD1_MonAReg[7], RD1_MonAReg[8], RD1_MonAReg[9], S1L2275Q, S1L2281Q, S1L2288Q, S1L2294Q, S1L2301Q, S1L2307Q, S1L2313Q, S1L2319Q, RD1_internal_MonDReg[8], RD1_internal_MonDReg[9], RD1_internal_MonDReg[10], RD1_internal_MonDReg[11], RD1_internal_MonDReg[12], RD1_internal_MonDReg[13], RD1_internal_MonDReg[14], RD1_internal_MonDReg[15], V1L48);

--CE1_q_a[9] is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|cpu_ociram_lpm_dram_bdp_component_module:cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_bp62:auto_generated|q_a[9] at M4K_X49_Y19

CE1_q_a[9] = AMPP_FUNCTION(RD1L71, RD1_MonWr, QC2__clk0, QC2__clk0, S1_M_st_data[0], S1_M_st_data[1], S1_M_st_data[2], S1_M_st_data[3], S1_M_st_data[4], S1_M_st_data[5], S1_M_st_data[6], S1_M_st_data[7], V1L16, V1L17, V1L20, V1L21, V1L22, V1L23, V1L24, V1L25, V1L47, RD1_internal_MonDReg[0], RD1_internal_MonDReg[1], RD1_internal_MonDReg[2], RD1_internal_MonDReg[3], RD1_internal_MonDReg[4], RD1_internal_MonDReg[5], RD1_internal_MonDReg[6], RD1_internal_MonDReg[7], RD1_MonAReg[2], RD1_MonAReg[3], RD1_MonAReg[4], RD1_MonAReg[5], RD1_MonAReg[6], RD1_MonAReg[7], RD1_MonAReg[8], RD1_MonAReg[9], S1L2275Q, S1L2281Q, S1L2288Q, S1L2294Q, S1L2301Q, S1L2307Q, S1L2313Q, S1L2319Q, RD1_internal_MonDReg[8], RD1_internal_MonDReg[9], RD1_internal_MonDReg[10], RD1_internal_MonDReg[11], RD1_internal_MonDReg[12], RD1_internal_MonDReg[13], RD1_internal_MonDReg[14], RD1_internal_MonDReg[15], V1L48);

--CE1_q_a[8] is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|cpu_ociram_lpm_dram_bdp_component_module:cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_bp62:auto_generated|q_a[8] at M4K_X49_Y19

CE1_q_a[8] = AMPP_FUNCTION(RD1L71, RD1_MonWr, QC2__clk0, QC2__clk0, S1_M_st_data[0], S1_M_st_data[1], S1_M_st_data[2], S1_M_st_data[3], S1_M_st_data[4], S1_M_st_data[5], S1_M_st_data[6], S1_M_st_data[7], V1L16, V1L17, V1L20, V1L21, V1L22, V1L23, V1L24, V1L25, V1L47, RD1_internal_MonDReg[0], RD1_internal_MonDReg[1], RD1_internal_MonDReg[2], RD1_internal_MonDReg[3], RD1_internal_MonDReg[4], RD1_internal_MonDReg[5], RD1_internal_MonDReg[6], RD1_internal_MonDReg[7], RD1_MonAReg[2], RD1_MonAReg[3], RD1_MonAReg[4], RD1_MonAReg[5], RD1_MonAReg[6], RD1_MonAReg[7], RD1_MonAReg[8], RD1_MonAReg[9], S1L2275Q, S1L2281Q, S1L2288Q, S1L2294Q, S1L2301Q, S1L2307Q, S1L2313Q, S1L2319Q, RD1_internal_MonDReg[8], RD1_internal_MonDReg[9], RD1_internal_MonDReg[10], RD1_internal_MonDReg[11], RD1_internal_MonDReg[12], RD1_internal_MonDReg[13], RD1_internal_MonDReg[14], RD1_internal_MonDReg[15], V1L48);

--CE1_q_b[15] is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|cpu_ociram_lpm_dram_bdp_component_module:cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_bp62:auto_generated|q_b[15] at M4K_X49_Y19

CE1_q_b[15] = AMPP_FUNCTION(RD1L71, RD1_MonWr, QC2__clk0, QC2__clk0, S1_M_st_data[0], S1_M_st_data[1], S1_M_st_data[2], S1_M_st_data[3], S1_M_st_data[4], S1_M_st_data[5], S1_M_st_data[6], S1_M_st_data[7], V1L16, V1L17, V1L20, V1L21, V1L22, V1L23, V1L24, V1L25, V1L47, RD1_internal_MonDReg[0], RD1_internal_MonDReg[1], RD1_internal_MonDReg[2], RD1_internal_MonDReg[3], RD1_internal_MonDReg[4], RD1_internal_MonDReg[5], RD1_internal_MonDReg[6], RD1_internal_MonDReg[7], RD1_MonAReg[2], RD1_MonAReg[3], RD1_MonAReg[4], RD1_MonAReg[5], RD1_MonAReg[6], RD1_MonAReg[7], RD1_MonAReg[8], RD1_MonAReg[9], S1L2275Q, S1L2281Q, S1L2288Q, S1L2294Q, S1L2301Q, S1L2307Q, S1L2313Q, S1L2319Q, RD1_internal_MonDReg[8], RD1_internal_MonDReg[9], RD1_internal_MonDReg[10], RD1_internal_MonDReg[11], RD1_internal_MonDReg[12], RD1_internal_MonDReg[13], RD1_internal_MonDReg[14], RD1_internal_MonDReg[15], V1L48);

--CE1_q_b[14] is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|cpu_ociram_lpm_dram_bdp_component_module:cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_bp62:auto_generated|q_b[14] at M4K_X49_Y19

CE1_q_b[14] = AMPP_FUNCTION(RD1L71, RD1_MonWr, QC2__clk0, QC2__clk0, S1_M_st_data[0], S1_M_st_data[1], S1_M_st_data[2], S1_M_st_data[3], S1_M_st_data[4], S1_M_st_data[5], S1_M_st_data[6], S1_M_st_data[7], V1L16, V1L17, V1L20, V1L21, V1L22, V1L23, V1L24, V1L25, V1L47, RD1_internal_MonDReg[0], RD1_internal_MonDReg[1], RD1_internal_MonDReg[2], RD1_internal_MonDReg[3], RD1_internal_MonDReg[4], RD1_internal_MonDReg[5], RD1_internal_MonDReg[6], RD1_internal_MonDReg[7], RD1_MonAReg[2], RD1_MonAReg[3], RD1_MonAReg[4], RD1_MonAReg[5], RD1_MonAReg[6], RD1_MonAReg[7], RD1_MonAReg[8], RD1_MonAReg[9], S1L2275Q, S1L2281Q, S1L2288Q, S1L2294Q, S1L2301Q, S1L2307Q, S1L2313Q, S1L2319Q, RD1_internal_MonDReg[8], RD1_internal_MonDReg[9], RD1_internal_MonDReg[10], RD1_internal_MonDReg[11], RD1_internal_MonDReg[12], RD1_internal_MonDReg[13], RD1_internal_MonDReg[14], RD1_internal_MonDReg[15], V1L48);

--CE1_q_b[13] is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|cpu_ociram_lpm_dram_bdp_component_module:cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_bp62:auto_generated|q_b[13] at M4K_X49_Y19

CE1_q_b[13] = AMPP_FUNCTION(RD1L71, RD1_MonWr, QC2__clk0, QC2__clk0, S1_M_st_data[0], S1_M_st_data[1], S1_M_st_data[2], S1_M_st_data[3], S1_M_st_data[4], S1_M_st_data[5], S1_M_st_data[6], S1_M_st_data[7], V1L16, V1L17, V1L20, V1L21, V1L22, V1L23, V1L24, V1L25, V1L47, RD1_internal_MonDReg[0], RD1_internal_MonDReg[1], RD1_internal_MonDReg[2], RD1_internal_MonDReg[3], RD1_internal_MonDReg[4], RD1_internal_MonDReg[5], RD1_internal_MonDReg[6], RD1_internal_MonDReg[7], RD1_MonAReg[2], RD1_MonAReg[3], RD1_MonAReg[4], RD1_MonAReg[5], RD1_MonAReg[6], RD1_MonAReg[7], RD1_MonAReg[8], RD1_MonAReg[9], S1L2275Q, S1L2281Q, S1L2288Q, S1L2294Q, S1L2301Q, S1L2307Q, S1L2313Q, S1L2319Q, RD1_internal_MonDReg[8], RD1_internal_MonDReg[9], RD1_internal_MonDReg[10], RD1_internal_MonDReg[11], RD1_internal_MonDReg[12], RD1_internal_MonDReg[13], RD1_internal_MonDReg[14], RD1_internal_MonDReg[15], V1L48);

--CE1_q_b[12] is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|cpu_ociram_lpm_dram_bdp_component_module:cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_bp62:auto_generated|q_b[12] at M4K_X49_Y19

CE1_q_b[12] = AMPP_FUNCTION(RD1L71, RD1_MonWr, QC2__clk0, QC2__clk0, S1_M_st_data[0], S1_M_st_data[1], S1_M_st_data[2], S1_M_st_data[3], S1_M_st_data[4], S1_M_st_data[5], S1_M_st_data[6], S1_M_st_data[7], V1L16, V1L17, V1L20, V1L21, V1L22, V1L23, V1L24, V1L25, V1L47, RD1_internal_MonDReg[0], RD1_internal_MonDReg[1], RD1_internal_MonDReg[2], RD1_internal_MonDReg[3], RD1_internal_MonDReg[4], RD1_internal_MonDReg[5], RD1_internal_MonDReg[6], RD1_internal_MonDReg[7], RD1_MonAReg[2], RD1_MonAReg[3], RD1_MonAReg[4], RD1_MonAReg[5], RD1_MonAReg[6], RD1_MonAReg[7], RD1_MonAReg[8], RD1_MonAReg[9], S1L2275Q, S1L2281Q, S1L2288Q, S1L2294Q, S1L2301Q, S1L2307Q, S1L2313Q, S1L2319Q, RD1_internal_MonDReg[8], RD1_internal_MonDReg[9], RD1_internal_MonDReg[10], RD1_internal_MonDReg[11], RD1_internal_MonDReg[12], RD1_internal_MonDReg[13], RD1_internal_MonDReg[14], RD1_internal_MonDReg[15], V1L48);

--CE1_q_b[11] is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|cpu_ociram_lpm_dram_bdp_component_module:cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_bp62:auto_generated|q_b[11] at M4K_X49_Y19

CE1_q_b[11] = AMPP_FUNCTION(RD1L71, RD1_MonWr, QC2__clk0, QC2__clk0, S1_M_st_data[0], S1_M_st_data[1], S1_M_st_data[2], S1_M_st_data[3], S1_M_st_data[4], S1_M_st_data[5], S1_M_st_data[6], S1_M_st_data[7], V1L16, V1L17, V1L20, V1L21, V1L22, V1L23, V1L24, V1L25, V1L47, RD1_internal_MonDReg[0], RD1_internal_MonDReg[1], RD1_internal_MonDReg[2], RD1_internal_MonDReg[3], RD1_internal_MonDReg[4], RD1_internal_MonDReg[5], RD1_internal_MonDReg[6], RD1_internal_MonDReg[7], RD1_MonAReg[2], RD1_MonAReg[3], RD1_MonAReg[4], RD1_MonAReg[5], RD1_MonAReg[6], RD1_MonAReg[7], RD1_MonAReg[8], RD1_MonAReg[9], S1L2275Q, S1L2281Q, S1L2288Q, S1L2294Q, S1L2301Q, S1L2307Q, S1L2313Q, S1L2319Q, RD1_internal_MonDReg[8], RD1_internal_MonDReg[9], RD1_internal_MonDReg[10], RD1_internal_MonDReg[11], RD1_internal_MonDReg[12], RD1_internal_MonDReg[13], RD1_internal_MonDReg[14], RD1_internal_MonDReg[15], V1L48);

--CE1_q_b[10] is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|cpu_ociram_lpm_dram_bdp_component_module:cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_bp62:auto_generated|q_b[10] at M4K_X49_Y19

CE1_q_b[10] = AMPP_FUNCTION(RD1L71, RD1_MonWr, QC2__clk0, QC2__clk0, S1_M_st_data[0], S1_M_st_data[1], S1_M_st_data[2], S1_M_st_data[3], S1_M_st_data[4], S1_M_st_data[5], S1_M_st_data[6], S1_M_st_data[7], V1L16, V1L17, V1L20, V1L21, V1L22, V1L23, V1L24, V1L25, V1L47, RD1_internal_MonDReg[0], RD1_internal_MonDReg[1], RD1_internal_MonDReg[2], RD1_internal_MonDReg[3], RD1_internal_MonDReg[4], RD1_internal_MonDReg[5], RD1_internal_MonDReg[6], RD1_internal_MonDReg[7], RD1_MonAReg[2], RD1_MonAReg[3], RD1_MonAReg[4], RD1_MonAReg[5], RD1_MonAReg[6], RD1_MonAReg[7], RD1_MonAReg[8], RD1_MonAReg[9], S1L2275Q, S1L2281Q, S1L2288Q, S1L2294Q, S1L2301Q, S1L2307Q, S1L2313Q, S1L2319Q, RD1_internal_MonDReg[8], RD1_internal_MonDReg[9], RD1_internal_MonDReg[10], RD1_internal_MonDReg[11], RD1_internal_MonDReg[12], RD1_internal_MonDReg[13], RD1_internal_MonDReg[14], RD1_internal_MonDReg[15], V1L48);

--CE1_q_b[9] is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|cpu_ociram_lpm_dram_bdp_component_module:cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_bp62:auto_generated|q_b[9] at M4K_X49_Y19

CE1_q_b[9] = AMPP_FUNCTION(RD1L71, RD1_MonWr, QC2__clk0, QC2__clk0, S1_M_st_data[0], S1_M_st_data[1], S1_M_st_data[2], S1_M_st_data[3], S1_M_st_data[4], S1_M_st_data[5], S1_M_st_data[6], S1_M_st_data[7], V1L16, V1L17, V1L20, V1L21, V1L22, V1L23, V1L24, V1L25, V1L47, RD1_internal_MonDReg[0], RD1_internal_MonDReg[1], RD1_internal_MonDReg[2], RD1_internal_MonDReg[3], RD1_internal_MonDReg[4], RD1_internal_MonDReg[5], RD1_internal_MonDReg[6], RD1_internal_MonDReg[7], RD1_MonAReg[2], RD1_MonAReg[3], RD1_MonAReg[4], RD1_MonAReg[5], RD1_MonAReg[6], RD1_MonAReg[7], RD1_MonAReg[8], RD1_MonAReg[9], S1L2275Q, S1L2281Q, S1L2288Q, S1L2294Q, S1L2301Q, S1L2307Q, S1L2313Q, S1L2319Q, RD1_internal_MonDReg[8], RD1_internal_MonDReg[9], RD1_internal_MonDReg[10], RD1_internal_MonDReg[11], RD1_internal_MonDReg[12], RD1_internal_MonDReg[13], RD1_internal_MonDReg[14], RD1_internal_MonDReg[15], V1L48);

--CE1_q_b[8] is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|cpu_ociram_lpm_dram_bdp_component_module:cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_bp62:auto_generated|q_b[8] at M4K_X49_Y19

CE1_q_b[8] = AMPP_FUNCTION(RD1L71, RD1_MonWr, QC2__clk0, QC2__clk0, S1_M_st_data[0], S1_M_st_data[1], S1_M_st_data[2], S1_M_st_data[3], S1_M_st_data[4], S1_M_st_data[5], S1_M_st_data[6], S1_M_st_data[7], V1L16, V1L17, V1L20, V1L21, V1L22, V1L23, V1L24, V1L25, V1L47, RD1_internal_MonDReg[0], RD1_internal_MonDReg[1], RD1_internal_MonDReg[2], RD1_internal_MonDReg[3], RD1_internal_MonDReg[4], RD1_internal_MonDReg[5], RD1_internal_MonDReg[6], RD1_internal_MonDReg[7], RD1_MonAReg[2], RD1_MonAReg[3], RD1_MonAReg[4], RD1_MonAReg[5], RD1_MonAReg[6], RD1_MonAReg[7], RD1_MonAReg[8], RD1_MonAReg[9], S1L2275Q, S1L2281Q, S1L2288Q, S1L2294Q, S1L2301Q, S1L2307Q, S1L2313Q, S1L2319Q, RD1_internal_MonDReg[8], RD1_internal_MonDReg[9], RD1_internal_MonDReg[10], RD1_internal_MonDReg[11], RD1_internal_MonDReg[12], RD1_internal_MonDReg[13], RD1_internal_MonDReg[14], RD1_internal_MonDReg[15], V1L48);

--WC1L3 is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|readdata[2]~1336 at LC_X46_Y19_N0

--operation mode is normal

WC1L3 = AMPP_FUNCTION(S1L1376Q, S1L1377Q, S1L1367Q, S1L1369Q);

--WC1L21 is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|readdata[18]~1337 at LC_X38_Y21_N1

--operation mode is normal

WC1L21 = AMPP_FUNCTION(V1L26, V1L16, FD1L1, FD1L2);

--S1L524Q is std_1c20:inst|cpu:the_cpu|d_readdata_d1[8]~108 at LC_X38_Y21_N1

--operation mode is normal

S1L524Q = AMPP_FUNCTION(QC2__clk0, V1L26, V1L16, FD1L1, FD1L2, F1_data_out);

--T1L150 is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[9]~5171 at LC_X44_Y23_N0

--operation mode is normal

T1L150 = !JB1L3 & (!SB1L2 # !S1L1743Q # !H1L2);

--T1L196 is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[16]~5172 at LC_X44_Y23_N3

--operation mode is normal

T1L196 = S1_M_alu_result[6] # !SB1L2;

--T1L211 is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[18]~5173 at LC_X42_Y23_N8

--operation mode is normal

T1L211 = !UB1_cpu_data_master_granted_sysid_control_slave & T1L196 & T1L150 & !WB1_cpu_data_master_granted_uart1_s1;

--T1_registered_cpu_data_master_readdata[18] is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|registered_cpu_data_master_readdata[18] at LC_X41_Y23_N1

--operation mode is normal

T1_registered_cpu_data_master_readdata[18]_lut_out = T1L486 & !K1L6 & (BB1L26 # !CB1_cpu_data_master_requests_jtag_uart_avalon_jtag_slave);

T1_registered_cpu_data_master_readdata[18] = DFFEAS(T1_registered_cpu_data_master_readdata[18]_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--CB1_cpu_data_master_requests_jtag_uart_avalon_jtag_slave is std_1c20:inst|jtag_uart_avalon_jtag_slave_arbitrator:the_jtag_uart_avalon_jtag_slave|cpu_data_master_requests_jtag_uart_avalon_jtag_slave at LC_X41_Y25_N2

--operation mode is normal

CB1_cpu_data_master_requests_jtag_uart_avalon_jtag_slave = CB1L2 & UB1L9;

--T1L214 is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[18]~5176 at LC_X41_Y23_N7

--operation mode is normal

T1L214 = !T1L219 & !T1L217 & (T1_registered_cpu_data_master_readdata[18] # !T1L241);

--W1L4 is std_1c20:inst|epcs_controller:the_epcs_controller|readdata[18]~688 at LC_X42_Y23_N1

--operation mode is normal

W1L4 = !W1L1 & (FE1_q_a[18]);

--S1L578Q is std_1c20:inst|cpu:the_cpu|d_readdata_d1[18]~178 at LC_X42_Y23_N9

--operation mode is normal

S1L578Q = AMPP_FUNCTION(QC2__clk0, X1_cpu_data_master_requests_epcs_controller_epcs_control_port, T1L214, T1L211, W1L4, F1_data_out);

--CE1_q_a[16] is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|cpu_ociram_lpm_dram_bdp_component_module:cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_bp62:auto_generated|q_a[16] at M4K_X49_Y18

--RAM Block Operation Mode: True Dual-Port

--Port A Depth: 256, Port A Width: 16, Port B Depth: 256, Port B Width: 16

--Port A Logical Depth: 256, Port A Logical Width: 32, Port B Logical Depth: 256, Port B Logical Width: 32

--Port A Input: Registered, Port A Output: Un-registered, Port B Input: Registered, Port B Output: Un-registered

CE1_q_a[16] = AMPP_FUNCTION(RD1L71, RD1_MonWr, QC2__clk0, QC2__clk0, S1L2325Q, S1L2330Q, S1L2335Q, S1L2340Q, S1L2345Q, S1L2350Q, S1L2355Q, S1L2360Q, V1L16, V1L17, V1L20, V1L21, V1L22, V1L23, V1L24, V1L25, V1L49, RD1_internal_MonDReg[16], RD1_internal_MonDReg[17], RD1_internal_MonDReg[18], RD1_internal_MonDReg[19], RD1_internal_MonDReg[20], RD1_internal_MonDReg[21], RD1_internal_MonDReg[22], RD1_internal_MonDReg[23], RD1_MonAReg[2], RD1_MonAReg[3], RD1_MonAReg[4], RD1_MonAReg[5], RD1_MonAReg[6], RD1_MonAReg[7], RD1_MonAReg[8], RD1_MonAReg[9], S1_M_st_data[24], S1_M_st_data[25], S1_M_st_data[26], S1_M_st_data[27], S1_M_st_data[28], S1_M_st_data[29], S1_M_st_data[30], S1_M_st_data[31], RD1_internal_MonDReg[24], RD1_internal_MonDReg[25], RD1_internal_MonDReg[26], RD1_internal_MonDReg[27], RD1_internal_MonDReg[28], RD1_internal_MonDReg[29], RD1_internal_MonDReg[30], RD1_internal_MonDReg[31], V1L50);

--CE1_q_a[17] is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|cpu_ociram_lpm_dram_bdp_component_module:cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_bp62:auto_generated|q_a[17] at M4K_X49_Y18

CE1_q_a[17] = AMPP_FUNCTION(RD1L71, RD1_MonWr, QC2__clk0, QC2__clk0, S1L2325Q, S1L2330Q, S1L2335Q, S1L2340Q, S1L2345Q, S1L2350Q, S1L2355Q, S1L2360Q, V1L16, V1L17, V1L20, V1L21, V1L22, V1L23, V1L24, V1L25, V1L49, RD1_internal_MonDReg[16], RD1_internal_MonDReg[17], RD1_internal_MonDReg[18], RD1_internal_MonDReg[19], RD1_internal_MonDReg[20], RD1_internal_MonDReg[21], RD1_internal_MonDReg[22], RD1_internal_MonDReg[23], RD1_MonAReg[2], RD1_MonAReg[3], RD1_MonAReg[4], RD1_MonAReg[5], RD1_MonAReg[6], RD1_MonAReg[7], RD1_MonAReg[8], RD1_MonAReg[9], S1_M_st_data[24], S1_M_st_data[25], S1_M_st_data[26], S1_M_st_data[27], S1_M_st_data[28], S1_M_st_data[29], S1_M_st_data[30], S1_M_st_data[31], RD1_internal_MonDReg[24], RD1_internal_MonDReg[25], RD1_internal_MonDReg[26], RD1_internal_MonDReg[27], RD1_internal_MonDReg[28], RD1_internal_MonDReg[29], RD1_internal_MonDReg[30], RD1_internal_MonDReg[31], V1L50);

--CE1_q_a[18] is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|cpu_ociram_lpm_dram_bdp_component_module:cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_bp62:auto_generated|q_a[18] at M4K_X49_Y18

CE1_q_a[18] = AMPP_FUNCTION(RD1L71, RD1_MonWr, QC2__clk0, QC2__clk0, S1L2325Q, S1L2330Q, S1L2335Q, S1L2340Q, S1L2345Q, S1L2350Q, S1L2355Q, S1L2360Q, V1L16, V1L17, V1L20, V1L21, V1L22, V1L23, V1L24, V1L25, V1L49, RD1_internal_MonDReg[16], RD1_internal_MonDReg[17], RD1_internal_MonDReg[18], RD1_internal_MonDReg[19], RD1_internal_MonDReg[20], RD1_internal_MonDReg[21], RD1_internal_MonDReg[22], RD1_internal_MonDReg[23], RD1_MonAReg[2], RD1_MonAReg[3], RD1_MonAReg[4], RD1_MonAReg[5], RD1_MonAReg[6], RD1_MonAReg[7], RD1_MonAReg[8], RD1_MonAReg[9], S1_M_st_data[24], S1_M_st_data[25], S1_M_st_data[26], S1_M_st_data[27], S1_M_st_data[28], S1_M_st_data[29], S1_M_st_data[30], S1_M_st_data[31], RD1_internal_MonDReg[24], RD1_internal_MonDReg[25], RD1_internal_MonDReg[26], RD1_internal_MonDReg[27], RD1_internal_MonDReg[28], RD1_internal_MonDReg[29], RD1_internal_MonDReg[30], RD1_internal_MonDReg[31], V1L50);

--CE1_q_a[19] is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|cpu_ociram_lpm_dram_bdp_component_module:cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_bp62:auto_generated|q_a[19] at M4K_X49_Y18

CE1_q_a[19] = AMPP_FUNCTION(RD1L71, RD1_MonWr, QC2__clk0, QC2__clk0, S1L2325Q, S1L2330Q, S1L2335Q, S1L2340Q, S1L2345Q, S1L2350Q, S1L2355Q, S1L2360Q, V1L16, V1L17, V1L20, V1L21, V1L22, V1L23, V1L24, V1L25, V1L49, RD1_internal_MonDReg[16], RD1_internal_MonDReg[17], RD1_internal_MonDReg[18], RD1_internal_MonDReg[19], RD1_internal_MonDReg[20], RD1_internal_MonDReg[21], RD1_internal_MonDReg[22], RD1_internal_MonDReg[23], RD1_MonAReg[2], RD1_MonAReg[3], RD1_MonAReg[4], RD1_MonAReg[5], RD1_MonAReg[6], RD1_MonAReg[7], RD1_MonAReg[8], RD1_MonAReg[9], S1_M_st_data[24], S1_M_st_data[25], S1_M_st_data[26], S1_M_st_data[27], S1_M_st_data[28], S1_M_st_data[29], S1_M_st_data[30], S1_M_st_data[31], RD1_internal_MonDReg[24], RD1_internal_MonDReg[25], RD1_internal_MonDReg[26], RD1_internal_MonDReg[27], RD1_internal_MonDReg[28], RD1_internal_MonDReg[29], RD1_internal_MonDReg[30], RD1_internal_MonDReg[31], V1L50);

--CE1_q_a[20] is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|cpu_ociram_lpm_dram_bdp_component_module:cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_bp62:auto_generated|q_a[20] at M4K_X49_Y18

CE1_q_a[20] = AMPP_FUNCTION(RD1L71, RD1_MonWr, QC2__clk0, QC2__clk0, S1L2325Q, S1L2330Q, S1L2335Q, S1L2340Q, S1L2345Q, S1L2350Q, S1L2355Q, S1L2360Q, V1L16, V1L17, V1L20, V1L21, V1L22, V1L23, V1L24, V1L25, V1L49, RD1_internal_MonDReg[16], RD1_internal_MonDReg[17], RD1_internal_MonDReg[18], RD1_internal_MonDReg[19], RD1_internal_MonDReg[20], RD1_internal_MonDReg[21], RD1_internal_MonDReg[22], RD1_internal_MonDReg[23], RD1_MonAReg[2], RD1_MonAReg[3], RD1_MonAReg[4], RD1_MonAReg[5], RD1_MonAReg[6], RD1_MonAReg[7], RD1_MonAReg[8], RD1_MonAReg[9], S1_M_st_data[24], S1_M_st_data[25], S1_M_st_data[26], S1_M_st_data[27], S1_M_st_data[28], S1_M_st_data[29], S1_M_st_data[30], S1_M_st_data[31], RD1_internal_MonDReg[24], RD1_internal_MonDReg[25], RD1_internal_MonDReg[26], RD1_internal_MonDReg[27], RD1_internal_MonDReg[28], RD1_internal_MonDReg[29], RD1_internal_MonDReg[30], RD1_internal_MonDReg[31], V1L50);

--CE1_q_a[21] is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|cpu_ociram_lpm_dram_bdp_component_module:cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_bp62:auto_generated|q_a[21] at M4K_X49_Y18

CE1_q_a[21] = AMPP_FUNCTION(RD1L71, RD1_MonWr, QC2__clk0, QC2__clk0, S1L2325Q, S1L2330Q, S1L2335Q, S1L2340Q, S1L2345Q, S1L2350Q, S1L2355Q, S1L2360Q, V1L16, V1L17, V1L20, V1L21, V1L22, V1L23, V1L24, V1L25, V1L49, RD1_internal_MonDReg[16], RD1_internal_MonDReg[17], RD1_internal_MonDReg[18], RD1_internal_MonDReg[19], RD1_internal_MonDReg[20], RD1_internal_MonDReg[21], RD1_internal_MonDReg[22], RD1_internal_MonDReg[23], RD1_MonAReg[2], RD1_MonAReg[3], RD1_MonAReg[4], RD1_MonAReg[5], RD1_MonAReg[6], RD1_MonAReg[7], RD1_MonAReg[8], RD1_MonAReg[9], S1_M_st_data[24], S1_M_st_data[25], S1_M_st_data[26], S1_M_st_data[27], S1_M_st_data[28], S1_M_st_data[29], S1_M_st_data[30], S1_M_st_data[31], RD1_internal_MonDReg[24], RD1_internal_MonDReg[25], RD1_internal_MonDReg[26], RD1_internal_MonDReg[27], RD1_internal_MonDReg[28], RD1_internal_MonDReg[29], RD1_internal_MonDReg[30], RD1_internal_MonDReg[31], V1L50);

--CE1_q_a[22] is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|cpu_ociram_lpm_dram_bdp_component_module:cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_bp62:auto_generated|q_a[22] at M4K_X49_Y18

CE1_q_a[22] = AMPP_FUNCTION(RD1L71, RD1_MonWr, QC2__clk0, QC2__clk0, S1L2325Q, S1L2330Q, S1L2335Q, S1L2340Q, S1L2345Q, S1L2350Q, S1L2355Q, S1L2360Q, V1L16, V1L17, V1L20, V1L21, V1L22, V1L23, V1L24, V1L25, V1L49, RD1_internal_MonDReg[16], RD1_internal_MonDReg[17], RD1_internal_MonDReg[18], RD1_internal_MonDReg[19], RD1_internal_MonDReg[20], RD1_internal_MonDReg[21], RD1_internal_MonDReg[22], RD1_internal_MonDReg[23], RD1_MonAReg[2], RD1_MonAReg[3], RD1_MonAReg[4], RD1_MonAReg[5], RD1_MonAReg[6], RD1_MonAReg[7], RD1_MonAReg[8], RD1_MonAReg[9], S1_M_st_data[24], S1_M_st_data[25], S1_M_st_data[26], S1_M_st_data[27], S1_M_st_data[28], S1_M_st_data[29], S1_M_st_data[30], S1_M_st_data[31], RD1_internal_MonDReg[24], RD1_internal_MonDReg[25], RD1_internal_MonDReg[26], RD1_internal_MonDReg[27], RD1_internal_MonDReg[28], RD1_internal_MonDReg[29], RD1_internal_MonDReg[30], RD1_internal_MonDReg[31], V1L50);

--CE1_q_a[23] is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|cpu_ociram_lpm_dram_bdp_component_module:cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_bp62:auto_generated|q_a[23] at M4K_X49_Y18

CE1_q_a[23] = AMPP_FUNCTION(RD1L71, RD1_MonWr, QC2__clk0, QC2__clk0, S1L2325Q, S1L2330Q, S1L2335Q, S1L2340Q, S1L2345Q, S1L2350Q, S1L2355Q, S1L2360Q, V1L16, V1L17, V1L20, V1L21, V1L22, V1L23, V1L24, V1L25, V1L49, RD1_internal_MonDReg[16], RD1_internal_MonDReg[17], RD1_internal_MonDReg[18], RD1_internal_MonDReg[19], RD1_internal_MonDReg[20], RD1_internal_MonDReg[21], RD1_internal_MonDReg[22], RD1_internal_MonDReg[23], RD1_MonAReg[2], RD1_MonAReg[3], RD1_MonAReg[4], RD1_MonAReg[5], RD1_MonAReg[6], RD1_MonAReg[7], RD1_MonAReg[8], RD1_MonAReg[9], S1_M_st_data[24], S1_M_st_data[25], S1_M_st_data[26], S1_M_st_data[27], S1_M_st_data[28], S1_M_st_data[29], S1_M_st_data[30], S1_M_st_data[31], RD1_internal_MonDReg[24], RD1_internal_MonDReg[25], RD1_internal_MonDReg[26], RD1_internal_MonDReg[27], RD1_internal_MonDReg[28], RD1_internal_MonDReg[29], RD1_internal_MonDReg[30], RD1_internal_MonDReg[31], V1L50);

--CE1_q_b[16] is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|cpu_ociram_lpm_dram_bdp_component_module:cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_bp62:auto_generated|q_b[16] at M4K_X49_Y18

CE1_q_b[16] = AMPP_FUNCTION(RD1L71, RD1_MonWr, QC2__clk0, QC2__clk0, S1L2325Q, S1L2330Q, S1L2335Q, S1L2340Q, S1L2345Q, S1L2350Q, S1L2355Q, S1L2360Q, V1L16, V1L17, V1L20, V1L21, V1L22, V1L23, V1L24, V1L25, V1L49, RD1_internal_MonDReg[16], RD1_internal_MonDReg[17], RD1_internal_MonDReg[18], RD1_internal_MonDReg[19], RD1_internal_MonDReg[20], RD1_internal_MonDReg[21], RD1_internal_MonDReg[22], RD1_internal_MonDReg[23], RD1_MonAReg[2], RD1_MonAReg[3], RD1_MonAReg[4], RD1_MonAReg[5], RD1_MonAReg[6], RD1_MonAReg[7], RD1_MonAReg[8], RD1_MonAReg[9], S1_M_st_data[24], S1_M_st_data[25], S1_M_st_data[26], S1_M_st_data[27], S1_M_st_data[28], S1_M_st_data[29], S1_M_st_data[30], S1_M_st_data[31], RD1_internal_MonDReg[24], RD1_internal_MonDReg[25], RD1_internal_MonDReg[26], RD1_internal_MonDReg[27], RD1_internal_MonDReg[28], RD1_internal_MonDReg[29], RD1_internal_MonDReg[30], RD1_internal_MonDReg[31], V1L50);

--CE1_q_b[17] is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|cpu_ociram_lpm_dram_bdp_component_module:cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_bp62:auto_generated|q_b[17] at M4K_X49_Y18

CE1_q_b[17] = AMPP_FUNCTION(RD1L71, RD1_MonWr, QC2__clk0, QC2__clk0, S1L2325Q, S1L2330Q, S1L2335Q, S1L2340Q, S1L2345Q, S1L2350Q, S1L2355Q, S1L2360Q, V1L16, V1L17, V1L20, V1L21, V1L22, V1L23, V1L24, V1L25, V1L49, RD1_internal_MonDReg[16], RD1_internal_MonDReg[17], RD1_internal_MonDReg[18], RD1_internal_MonDReg[19], RD1_internal_MonDReg[20], RD1_internal_MonDReg[21], RD1_internal_MonDReg[22], RD1_internal_MonDReg[23], RD1_MonAReg[2], RD1_MonAReg[3], RD1_MonAReg[4], RD1_MonAReg[5], RD1_MonAReg[6], RD1_MonAReg[7], RD1_MonAReg[8], RD1_MonAReg[9], S1_M_st_data[24], S1_M_st_data[25], S1_M_st_data[26], S1_M_st_data[27], S1_M_st_data[28], S1_M_st_data[29], S1_M_st_data[30], S1_M_st_data[31], RD1_internal_MonDReg[24], RD1_internal_MonDReg[25], RD1_internal_MonDReg[26], RD1_internal_MonDReg[27], RD1_internal_MonDReg[28], RD1_internal_MonDReg[29], RD1_internal_MonDReg[30], RD1_internal_MonDReg[31], V1L50);

--CE1_q_b[18] is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|cpu_ociram_lpm_dram_bdp_component_module:cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_bp62:auto_generated|q_b[18] at M4K_X49_Y18

CE1_q_b[18] = AMPP_FUNCTION(RD1L71, RD1_MonWr, QC2__clk0, QC2__clk0, S1L2325Q, S1L2330Q, S1L2335Q, S1L2340Q, S1L2345Q, S1L2350Q, S1L2355Q, S1L2360Q, V1L16, V1L17, V1L20, V1L21, V1L22, V1L23, V1L24, V1L25, V1L49, RD1_internal_MonDReg[16], RD1_internal_MonDReg[17], RD1_internal_MonDReg[18], RD1_internal_MonDReg[19], RD1_internal_MonDReg[20], RD1_internal_MonDReg[21], RD1_internal_MonDReg[22], RD1_internal_MonDReg[23], RD1_MonAReg[2], RD1_MonAReg[3], RD1_MonAReg[4], RD1_MonAReg[5], RD1_MonAReg[6], RD1_MonAReg[7], RD1_MonAReg[8], RD1_MonAReg[9], S1_M_st_data[24], S1_M_st_data[25], S1_M_st_data[26], S1_M_st_data[27], S1_M_st_data[28], S1_M_st_data[29], S1_M_st_data[30], S1_M_st_data[31], RD1_internal_MonDReg[24], RD1_internal_MonDReg[25], RD1_internal_MonDReg[26], RD1_internal_MonDReg[27], RD1_internal_MonDReg[28], RD1_internal_MonDReg[29], RD1_internal_MonDReg[30], RD1_internal_MonDReg[31], V1L50);

--CE1_q_b[19] is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|cpu_ociram_lpm_dram_bdp_component_module:cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_bp62:auto_generated|q_b[19] at M4K_X49_Y18

CE1_q_b[19] = AMPP_FUNCTION(RD1L71, RD1_MonWr, QC2__clk0, QC2__clk0, S1L2325Q, S1L2330Q, S1L2335Q, S1L2340Q, S1L2345Q, S1L2350Q, S1L2355Q, S1L2360Q, V1L16, V1L17, V1L20, V1L21, V1L22, V1L23, V1L24, V1L25, V1L49, RD1_internal_MonDReg[16], RD1_internal_MonDReg[17], RD1_internal_MonDReg[18], RD1_internal_MonDReg[19], RD1_internal_MonDReg[20], RD1_internal_MonDReg[21], RD1_internal_MonDReg[22], RD1_internal_MonDReg[23], RD1_MonAReg[2], RD1_MonAReg[3], RD1_MonAReg[4], RD1_MonAReg[5], RD1_MonAReg[6], RD1_MonAReg[7], RD1_MonAReg[8], RD1_MonAReg[9], S1_M_st_data[24], S1_M_st_data[25], S1_M_st_data[26], S1_M_st_data[27], S1_M_st_data[28], S1_M_st_data[29], S1_M_st_data[30], S1_M_st_data[31], RD1_internal_MonDReg[24], RD1_internal_MonDReg[25], RD1_internal_MonDReg[26], RD1_internal_MonDReg[27], RD1_internal_MonDReg[28], RD1_internal_MonDReg[29], RD1_internal_MonDReg[30], RD1_internal_MonDReg[31], V1L50);

--CE1_q_b[20] is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|cpu_ociram_lpm_dram_bdp_component_module:cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_bp62:auto_generated|q_b[20] at M4K_X49_Y18

CE1_q_b[20] = AMPP_FUNCTION(RD1L71, RD1_MonWr, QC2__clk0, QC2__clk0, S1L2325Q, S1L2330Q, S1L2335Q, S1L2340Q, S1L2345Q, S1L2350Q, S1L2355Q, S1L2360Q, V1L16, V1L17, V1L20, V1L21, V1L22, V1L23, V1L24, V1L25, V1L49, RD1_internal_MonDReg[16], RD1_internal_MonDReg[17], RD1_internal_MonDReg[18], RD1_internal_MonDReg[19], RD1_internal_MonDReg[20], RD1_internal_MonDReg[21], RD1_internal_MonDReg[22], RD1_internal_MonDReg[23], RD1_MonAReg[2], RD1_MonAReg[3], RD1_MonAReg[4], RD1_MonAReg[5], RD1_MonAReg[6], RD1_MonAReg[7], RD1_MonAReg[8], RD1_MonAReg[9], S1_M_st_data[24], S1_M_st_data[25], S1_M_st_data[26], S1_M_st_data[27], S1_M_st_data[28], S1_M_st_data[29], S1_M_st_data[30], S1_M_st_data[31], RD1_internal_MonDReg[24], RD1_internal_MonDReg[25], RD1_internal_MonDReg[26], RD1_internal_MonDReg[27], RD1_internal_MonDReg[28], RD1_internal_MonDReg[29], RD1_internal_MonDReg[30], RD1_internal_MonDReg[31], V1L50);

--CE1_q_b[21] is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|cpu_ociram_lpm_dram_bdp_component_module:cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_bp62:auto_generated|q_b[21] at M4K_X49_Y18

CE1_q_b[21] = AMPP_FUNCTION(RD1L71, RD1_MonWr, QC2__clk0, QC2__clk0, S1L2325Q, S1L2330Q, S1L2335Q, S1L2340Q, S1L2345Q, S1L2350Q, S1L2355Q, S1L2360Q, V1L16, V1L17, V1L20, V1L21, V1L22, V1L23, V1L24, V1L25, V1L49, RD1_internal_MonDReg[16], RD1_internal_MonDReg[17], RD1_internal_MonDReg[18], RD1_internal_MonDReg[19], RD1_internal_MonDReg[20], RD1_internal_MonDReg[21], RD1_internal_MonDReg[22], RD1_internal_MonDReg[23], RD1_MonAReg[2], RD1_MonAReg[3], RD1_MonAReg[4], RD1_MonAReg[5], RD1_MonAReg[6], RD1_MonAReg[7], RD1_MonAReg[8], RD1_MonAReg[9], S1_M_st_data[24], S1_M_st_data[25], S1_M_st_data[26], S1_M_st_data[27], S1_M_st_data[28], S1_M_st_data[29], S1_M_st_data[30], S1_M_st_data[31], RD1_internal_MonDReg[24], RD1_internal_MonDReg[25], RD1_internal_MonDReg[26], RD1_internal_MonDReg[27], RD1_internal_MonDReg[28], RD1_internal_MonDReg[29], RD1_internal_MonDReg[30], RD1_internal_MonDReg[31], V1L50);

--CE1_q_b[22] is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|cpu_ociram_lpm_dram_bdp_component_module:cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_bp62:auto_generated|q_b[22] at M4K_X49_Y18

CE1_q_b[22] = AMPP_FUNCTION(RD1L71, RD1_MonWr, QC2__clk0, QC2__clk0, S1L2325Q, S1L2330Q, S1L2335Q, S1L2340Q, S1L2345Q, S1L2350Q, S1L2355Q, S1L2360Q, V1L16, V1L17, V1L20, V1L21, V1L22, V1L23, V1L24, V1L25, V1L49, RD1_internal_MonDReg[16], RD1_internal_MonDReg[17], RD1_internal_MonDReg[18], RD1_internal_MonDReg[19], RD1_internal_MonDReg[20], RD1_internal_MonDReg[21], RD1_internal_MonDReg[22], RD1_internal_MonDReg[23], RD1_MonAReg[2], RD1_MonAReg[3], RD1_MonAReg[4], RD1_MonAReg[5], RD1_MonAReg[6], RD1_MonAReg[7], RD1_MonAReg[8], RD1_MonAReg[9], S1_M_st_data[24], S1_M_st_data[25], S1_M_st_data[26], S1_M_st_data[27], S1_M_st_data[28], S1_M_st_data[29], S1_M_st_data[30], S1_M_st_data[31], RD1_internal_MonDReg[24], RD1_internal_MonDReg[25], RD1_internal_MonDReg[26], RD1_internal_MonDReg[27], RD1_internal_MonDReg[28], RD1_internal_MonDReg[29], RD1_internal_MonDReg[30], RD1_internal_MonDReg[31], V1L50);

--CE1_q_b[23] is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|cpu_ociram_lpm_dram_bdp_component_module:cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_bp62:auto_generated|q_b[23] at M4K_X49_Y18

CE1_q_b[23] = AMPP_FUNCTION(RD1L71, RD1_MonWr, QC2__clk0, QC2__clk0, S1L2325Q, S1L2330Q, S1L2335Q, S1L2340Q, S1L2345Q, S1L2350Q, S1L2355Q, S1L2360Q, V1L16, V1L17, V1L20, V1L21, V1L22, V1L23, V1L24, V1L25, V1L49, RD1_internal_MonDReg[16], RD1_internal_MonDReg[17], RD1_internal_MonDReg[18], RD1_internal_MonDReg[19], RD1_internal_MonDReg[20], RD1_internal_MonDReg[21], RD1_internal_MonDReg[22], RD1_internal_MonDReg[23], RD1_MonAReg[2], RD1_MonAReg[3], RD1_MonAReg[4], RD1_MonAReg[5], RD1_MonAReg[6], RD1_MonAReg[7], RD1_MonAReg[8], RD1_MonAReg[9], S1_M_st_data[24], S1_M_st_data[25], S1_M_st_data[26], S1_M_st_data[27], S1_M_st_data[28], S1_M_st_data[29], S1_M_st_data[30], S1_M_st_data[31], RD1_internal_MonDReg[24], RD1_internal_MonDReg[25], RD1_internal_MonDReg[26], RD1_internal_MonDReg[27], RD1_internal_MonDReg[28], RD1_internal_MonDReg[29], RD1_internal_MonDReg[30], RD1_internal_MonDReg[31], V1L50);

--CE1_q_a[31] is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|cpu_ociram_lpm_dram_bdp_component_module:cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_bp62:auto_generated|q_a[31] at M4K_X49_Y18

CE1_q_a[31] = AMPP_FUNCTION(RD1L71, RD1_MonWr, QC2__clk0, QC2__clk0, S1L2325Q, S1L2330Q, S1L2335Q, S1L2340Q, S1L2345Q, S1L2350Q, S1L2355Q, S1L2360Q, V1L16, V1L17, V1L20, V1L21, V1L22, V1L23, V1L24, V1L25, V1L49, RD1_internal_MonDReg[16], RD1_internal_MonDReg[17], RD1_internal_MonDReg[18], RD1_internal_MonDReg[19], RD1_internal_MonDReg[20], RD1_internal_MonDReg[21], RD1_internal_MonDReg[22], RD1_internal_MonDReg[23], RD1_MonAReg[2], RD1_MonAReg[3], RD1_MonAReg[4], RD1_MonAReg[5], RD1_MonAReg[6], RD1_MonAReg[7], RD1_MonAReg[8], RD1_MonAReg[9], S1_M_st_data[24], S1_M_st_data[25], S1_M_st_data[26], S1_M_st_data[27], S1_M_st_data[28], S1_M_st_data[29], S1_M_st_data[30], S1_M_st_data[31], RD1_internal_MonDReg[24], RD1_internal_MonDReg[25], RD1_internal_MonDReg[26], RD1_internal_MonDReg[27], RD1_internal_MonDReg[28], RD1_internal_MonDReg[29], RD1_internal_MonDReg[30], RD1_internal_MonDReg[31], V1L50);

--CE1_q_a[30] is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|cpu_ociram_lpm_dram_bdp_component_module:cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_bp62:auto_generated|q_a[30] at M4K_X49_Y18

CE1_q_a[30] = AMPP_FUNCTION(RD1L71, RD1_MonWr, QC2__clk0, QC2__clk0, S1L2325Q, S1L2330Q, S1L2335Q, S1L2340Q, S1L2345Q, S1L2350Q, S1L2355Q, S1L2360Q, V1L16, V1L17, V1L20, V1L21, V1L22, V1L23, V1L24, V1L25, V1L49, RD1_internal_MonDReg[16], RD1_internal_MonDReg[17], RD1_internal_MonDReg[18], RD1_internal_MonDReg[19], RD1_internal_MonDReg[20], RD1_internal_MonDReg[21], RD1_internal_MonDReg[22], RD1_internal_MonDReg[23], RD1_MonAReg[2], RD1_MonAReg[3], RD1_MonAReg[4], RD1_MonAReg[5], RD1_MonAReg[6], RD1_MonAReg[7], RD1_MonAReg[8], RD1_MonAReg[9], S1_M_st_data[24], S1_M_st_data[25], S1_M_st_data[26], S1_M_st_data[27], S1_M_st_data[28], S1_M_st_data[29], S1_M_st_data[30], S1_M_st_data[31], RD1_internal_MonDReg[24], RD1_internal_MonDReg[25], RD1_internal_MonDReg[26], RD1_internal_MonDReg[27], RD1_internal_MonDReg[28], RD1_internal_MonDReg[29], RD1_internal_MonDReg[30], RD1_internal_MonDReg[31], V1L50);

--CE1_q_a[29] is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|cpu_ociram_lpm_dram_bdp_component_module:cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_bp62:auto_generated|q_a[29] at M4K_X49_Y18

CE1_q_a[29] = AMPP_FUNCTION(RD1L71, RD1_MonWr, QC2__clk0, QC2__clk0, S1L2325Q, S1L2330Q, S1L2335Q, S1L2340Q, S1L2345Q, S1L2350Q, S1L2355Q, S1L2360Q, V1L16, V1L17, V1L20, V1L21, V1L22, V1L23, V1L24, V1L25, V1L49, RD1_internal_MonDReg[16], RD1_internal_MonDReg[17], RD1_internal_MonDReg[18], RD1_internal_MonDReg[19], RD1_internal_MonDReg[20], RD1_internal_MonDReg[21], RD1_internal_MonDReg[22], RD1_internal_MonDReg[23], RD1_MonAReg[2], RD1_MonAReg[3], RD1_MonAReg[4], RD1_MonAReg[5], RD1_MonAReg[6], RD1_MonAReg[7], RD1_MonAReg[8], RD1_MonAReg[9], S1_M_st_data[24], S1_M_st_data[25], S1_M_st_data[26], S1_M_st_data[27], S1_M_st_data[28], S1_M_st_data[29], S1_M_st_data[30], S1_M_st_data[31], RD1_internal_MonDReg[24], RD1_internal_MonDReg[25], RD1_internal_MonDReg[26], RD1_internal_MonDReg[27], RD1_internal_MonDReg[28], RD1_internal_MonDReg[29], RD1_internal_MonDReg[30], RD1_internal_MonDReg[31], V1L50);

--CE1_q_a[28] is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|cpu_ociram_lpm_dram_bdp_component_module:cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_bp62:auto_generated|q_a[28] at M4K_X49_Y18

CE1_q_a[28] = AMPP_FUNCTION(RD1L71, RD1_MonWr, QC2__clk0, QC2__clk0, S1L2325Q, S1L2330Q, S1L2335Q, S1L2340Q, S1L2345Q, S1L2350Q, S1L2355Q, S1L2360Q, V1L16, V1L17, V1L20, V1L21, V1L22, V1L23, V1L24, V1L25, V1L49, RD1_internal_MonDReg[16], RD1_internal_MonDReg[17], RD1_internal_MonDReg[18], RD1_internal_MonDReg[19], RD1_internal_MonDReg[20], RD1_internal_MonDReg[21], RD1_internal_MonDReg[22], RD1_internal_MonDReg[23], RD1_MonAReg[2], RD1_MonAReg[3], RD1_MonAReg[4], RD1_MonAReg[5], RD1_MonAReg[6], RD1_MonAReg[7], RD1_MonAReg[8], RD1_MonAReg[9], S1_M_st_data[24], S1_M_st_data[25], S1_M_st_data[26], S1_M_st_data[27], S1_M_st_data[28], S1_M_st_data[29], S1_M_st_data[30], S1_M_st_data[31], RD1_internal_MonDReg[24], RD1_internal_MonDReg[25], RD1_internal_MonDReg[26], RD1_internal_MonDReg[27], RD1_internal_MonDReg[28], RD1_internal_MonDReg[29], RD1_internal_MonDReg[30], RD1_internal_MonDReg[31], V1L50);

--CE1_q_a[27] is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|cpu_ociram_lpm_dram_bdp_component_module:cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_bp62:auto_generated|q_a[27] at M4K_X49_Y18

CE1_q_a[27] = AMPP_FUNCTION(RD1L71, RD1_MonWr, QC2__clk0, QC2__clk0, S1L2325Q, S1L2330Q, S1L2335Q, S1L2340Q, S1L2345Q, S1L2350Q, S1L2355Q, S1L2360Q, V1L16, V1L17, V1L20, V1L21, V1L22, V1L23, V1L24, V1L25, V1L49, RD1_internal_MonDReg[16], RD1_internal_MonDReg[17], RD1_internal_MonDReg[18], RD1_internal_MonDReg[19], RD1_internal_MonDReg[20], RD1_internal_MonDReg[21], RD1_internal_MonDReg[22], RD1_internal_MonDReg[23], RD1_MonAReg[2], RD1_MonAReg[3], RD1_MonAReg[4], RD1_MonAReg[5], RD1_MonAReg[6], RD1_MonAReg[7], RD1_MonAReg[8], RD1_MonAReg[9], S1_M_st_data[24], S1_M_st_data[25], S1_M_st_data[26], S1_M_st_data[27], S1_M_st_data[28], S1_M_st_data[29], S1_M_st_data[30], S1_M_st_data[31], RD1_internal_MonDReg[24], RD1_internal_MonDReg[25], RD1_internal_MonDReg[26], RD1_internal_MonDReg[27], RD1_internal_MonDReg[28], RD1_internal_MonDReg[29], RD1_internal_MonDReg[30], RD1_internal_MonDReg[31], V1L50);

--CE1_q_a[26] is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|cpu_ociram_lpm_dram_bdp_component_module:cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_bp62:auto_generated|q_a[26] at M4K_X49_Y18

CE1_q_a[26] = AMPP_FUNCTION(RD1L71, RD1_MonWr, QC2__clk0, QC2__clk0, S1L2325Q, S1L2330Q, S1L2335Q, S1L2340Q, S1L2345Q, S1L2350Q, S1L2355Q, S1L2360Q, V1L16, V1L17, V1L20, V1L21, V1L22, V1L23, V1L24, V1L25, V1L49, RD1_internal_MonDReg[16], RD1_internal_MonDReg[17], RD1_internal_MonDReg[18], RD1_internal_MonDReg[19], RD1_internal_MonDReg[20], RD1_internal_MonDReg[21], RD1_internal_MonDReg[22], RD1_internal_MonDReg[23], RD1_MonAReg[2], RD1_MonAReg[3], RD1_MonAReg[4], RD1_MonAReg[5], RD1_MonAReg[6], RD1_MonAReg[7], RD1_MonAReg[8], RD1_MonAReg[9], S1_M_st_data[24], S1_M_st_data[25], S1_M_st_data[26], S1_M_st_data[27], S1_M_st_data[28], S1_M_st_data[29], S1_M_st_data[30], S1_M_st_data[31], RD1_internal_MonDReg[24], RD1_internal_MonDReg[25], RD1_internal_MonDReg[26], RD1_internal_MonDReg[27], RD1_internal_MonDReg[28], RD1_internal_MonDReg[29], RD1_internal_MonDReg[30], RD1_internal_MonDReg[31], V1L50);

--CE1_q_a[25] is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|cpu_ociram_lpm_dram_bdp_component_module:cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_bp62:auto_generated|q_a[25] at M4K_X49_Y18

CE1_q_a[25] = AMPP_FUNCTION(RD1L71, RD1_MonWr, QC2__clk0, QC2__clk0, S1L2325Q, S1L2330Q, S1L2335Q, S1L2340Q, S1L2345Q, S1L2350Q, S1L2355Q, S1L2360Q, V1L16, V1L17, V1L20, V1L21, V1L22, V1L23, V1L24, V1L25, V1L49, RD1_internal_MonDReg[16], RD1_internal_MonDReg[17], RD1_internal_MonDReg[18], RD1_internal_MonDReg[19], RD1_internal_MonDReg[20], RD1_internal_MonDReg[21], RD1_internal_MonDReg[22], RD1_internal_MonDReg[23], RD1_MonAReg[2], RD1_MonAReg[3], RD1_MonAReg[4], RD1_MonAReg[5], RD1_MonAReg[6], RD1_MonAReg[7], RD1_MonAReg[8], RD1_MonAReg[9], S1_M_st_data[24], S1_M_st_data[25], S1_M_st_data[26], S1_M_st_data[27], S1_M_st_data[28], S1_M_st_data[29], S1_M_st_data[30], S1_M_st_data[31], RD1_internal_MonDReg[24], RD1_internal_MonDReg[25], RD1_internal_MonDReg[26], RD1_internal_MonDReg[27], RD1_internal_MonDReg[28], RD1_internal_MonDReg[29], RD1_internal_MonDReg[30], RD1_internal_MonDReg[31], V1L50);

--CE1_q_a[24] is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|cpu_ociram_lpm_dram_bdp_component_module:cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_bp62:auto_generated|q_a[24] at M4K_X49_Y18

CE1_q_a[24] = AMPP_FUNCTION(RD1L71, RD1_MonWr, QC2__clk0, QC2__clk0, S1L2325Q, S1L2330Q, S1L2335Q, S1L2340Q, S1L2345Q, S1L2350Q, S1L2355Q, S1L2360Q, V1L16, V1L17, V1L20, V1L21, V1L22, V1L23, V1L24, V1L25, V1L49, RD1_internal_MonDReg[16], RD1_internal_MonDReg[17], RD1_internal_MonDReg[18], RD1_internal_MonDReg[19], RD1_internal_MonDReg[20], RD1_internal_MonDReg[21], RD1_internal_MonDReg[22], RD1_internal_MonDReg[23], RD1_MonAReg[2], RD1_MonAReg[3], RD1_MonAReg[4], RD1_MonAReg[5], RD1_MonAReg[6], RD1_MonAReg[7], RD1_MonAReg[8], RD1_MonAReg[9], S1_M_st_data[24], S1_M_st_data[25], S1_M_st_data[26], S1_M_st_data[27], S1_M_st_data[28], S1_M_st_data[29], S1_M_st_data[30], S1_M_st_data[31], RD1_internal_MonDReg[24], RD1_internal_MonDReg[25], RD1_internal_MonDReg[26], RD1_internal_MonDReg[27], RD1_internal_MonDReg[28], RD1_internal_MonDReg[29], RD1_internal_MonDReg[30], RD1_internal_MonDReg[31], V1L50);

--CE1_q_b[31] is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|cpu_ociram_lpm_dram_bdp_component_module:cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_bp62:auto_generated|q_b[31] at M4K_X49_Y18

CE1_q_b[31] = AMPP_FUNCTION(RD1L71, RD1_MonWr, QC2__clk0, QC2__clk0, S1L2325Q, S1L2330Q, S1L2335Q, S1L2340Q, S1L2345Q, S1L2350Q, S1L2355Q, S1L2360Q, V1L16, V1L17, V1L20, V1L21, V1L22, V1L23, V1L24, V1L25, V1L49, RD1_internal_MonDReg[16], RD1_internal_MonDReg[17], RD1_internal_MonDReg[18], RD1_internal_MonDReg[19], RD1_internal_MonDReg[20], RD1_internal_MonDReg[21], RD1_internal_MonDReg[22], RD1_internal_MonDReg[23], RD1_MonAReg[2], RD1_MonAReg[3], RD1_MonAReg[4], RD1_MonAReg[5], RD1_MonAReg[6], RD1_MonAReg[7], RD1_MonAReg[8], RD1_MonAReg[9], S1_M_st_data[24], S1_M_st_data[25], S1_M_st_data[26], S1_M_st_data[27], S1_M_st_data[28], S1_M_st_data[29], S1_M_st_data[30], S1_M_st_data[31], RD1_internal_MonDReg[24], RD1_internal_MonDReg[25], RD1_internal_MonDReg[26], RD1_internal_MonDReg[27], RD1_internal_MonDReg[28], RD1_internal_MonDReg[29], RD1_internal_MonDReg[30], RD1_internal_MonDReg[31], V1L50);

--CE1_q_b[30] is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|cpu_ociram_lpm_dram_bdp_component_module:cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_bp62:auto_generated|q_b[30] at M4K_X49_Y18

CE1_q_b[30] = AMPP_FUNCTION(RD1L71, RD1_MonWr, QC2__clk0, QC2__clk0, S1L2325Q, S1L2330Q, S1L2335Q, S1L2340Q, S1L2345Q, S1L2350Q, S1L2355Q, S1L2360Q, V1L16, V1L17, V1L20, V1L21, V1L22, V1L23, V1L24, V1L25, V1L49, RD1_internal_MonDReg[16], RD1_internal_MonDReg[17], RD1_internal_MonDReg[18], RD1_internal_MonDReg[19], RD1_internal_MonDReg[20], RD1_internal_MonDReg[21], RD1_internal_MonDReg[22], RD1_internal_MonDReg[23], RD1_MonAReg[2], RD1_MonAReg[3], RD1_MonAReg[4], RD1_MonAReg[5], RD1_MonAReg[6], RD1_MonAReg[7], RD1_MonAReg[8], RD1_MonAReg[9], S1_M_st_data[24], S1_M_st_data[25], S1_M_st_data[26], S1_M_st_data[27], S1_M_st_data[28], S1_M_st_data[29], S1_M_st_data[30], S1_M_st_data[31], RD1_internal_MonDReg[24], RD1_internal_MonDReg[25], RD1_internal_MonDReg[26], RD1_internal_MonDReg[27], RD1_internal_MonDReg[28], RD1_internal_MonDReg[29], RD1_internal_MonDReg[30], RD1_internal_MonDReg[31], V1L50);

--CE1_q_b[29] is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|cpu_ociram_lpm_dram_bdp_component_module:cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_bp62:auto_generated|q_b[29] at M4K_X49_Y18

CE1_q_b[29] = AMPP_FUNCTION(RD1L71, RD1_MonWr, QC2__clk0, QC2__clk0, S1L2325Q, S1L2330Q, S1L2335Q, S1L2340Q, S1L2345Q, S1L2350Q, S1L2355Q, S1L2360Q, V1L16, V1L17, V1L20, V1L21, V1L22, V1L23, V1L24, V1L25, V1L49, RD1_internal_MonDReg[16], RD1_internal_MonDReg[17], RD1_internal_MonDReg[18], RD1_internal_MonDReg[19], RD1_internal_MonDReg[20], RD1_internal_MonDReg[21], RD1_internal_MonDReg[22], RD1_internal_MonDReg[23], RD1_MonAReg[2], RD1_MonAReg[3], RD1_MonAReg[4], RD1_MonAReg[5], RD1_MonAReg[6], RD1_MonAReg[7], RD1_MonAReg[8], RD1_MonAReg[9], S1_M_st_data[24], S1_M_st_data[25], S1_M_st_data[26], S1_M_st_data[27], S1_M_st_data[28], S1_M_st_data[29], S1_M_st_data[30], S1_M_st_data[31], RD1_internal_MonDReg[24], RD1_internal_MonDReg[25], RD1_internal_MonDReg[26], RD1_internal_MonDReg[27], RD1_internal_MonDReg[28], RD1_internal_MonDReg[29], RD1_internal_MonDReg[30], RD1_internal_MonDReg[31], V1L50);

--CE1_q_b[28] is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|cpu_ociram_lpm_dram_bdp_component_module:cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_bp62:auto_generated|q_b[28] at M4K_X49_Y18

CE1_q_b[28] = AMPP_FUNCTION(RD1L71, RD1_MonWr, QC2__clk0, QC2__clk0, S1L2325Q, S1L2330Q, S1L2335Q, S1L2340Q, S1L2345Q, S1L2350Q, S1L2355Q, S1L2360Q, V1L16, V1L17, V1L20, V1L21, V1L22, V1L23, V1L24, V1L25, V1L49, RD1_internal_MonDReg[16], RD1_internal_MonDReg[17], RD1_internal_MonDReg[18], RD1_internal_MonDReg[19], RD1_internal_MonDReg[20], RD1_internal_MonDReg[21], RD1_internal_MonDReg[22], RD1_internal_MonDReg[23], RD1_MonAReg[2], RD1_MonAReg[3], RD1_MonAReg[4], RD1_MonAReg[5], RD1_MonAReg[6], RD1_MonAReg[7], RD1_MonAReg[8], RD1_MonAReg[9], S1_M_st_data[24], S1_M_st_data[25], S1_M_st_data[26], S1_M_st_data[27], S1_M_st_data[28], S1_M_st_data[29], S1_M_st_data[30], S1_M_st_data[31], RD1_internal_MonDReg[24], RD1_internal_MonDReg[25], RD1_internal_MonDReg[26], RD1_internal_MonDReg[27], RD1_internal_MonDReg[28], RD1_internal_MonDReg[29], RD1_internal_MonDReg[30], RD1_internal_MonDReg[31], V1L50);

--CE1_q_b[27] is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|cpu_ociram_lpm_dram_bdp_component_module:cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_bp62:auto_generated|q_b[27] at M4K_X49_Y18

CE1_q_b[27] = AMPP_FUNCTION(RD1L71, RD1_MonWr, QC2__clk0, QC2__clk0, S1L2325Q, S1L2330Q, S1L2335Q, S1L2340Q, S1L2345Q, S1L2350Q, S1L2355Q, S1L2360Q, V1L16, V1L17, V1L20, V1L21, V1L22, V1L23, V1L24, V1L25, V1L49, RD1_internal_MonDReg[16], RD1_internal_MonDReg[17], RD1_internal_MonDReg[18], RD1_internal_MonDReg[19], RD1_internal_MonDReg[20], RD1_internal_MonDReg[21], RD1_internal_MonDReg[22], RD1_internal_MonDReg[23], RD1_MonAReg[2], RD1_MonAReg[3], RD1_MonAReg[4], RD1_MonAReg[5], RD1_MonAReg[6], RD1_MonAReg[7], RD1_MonAReg[8], RD1_MonAReg[9], S1_M_st_data[24], S1_M_st_data[25], S1_M_st_data[26], S1_M_st_data[27], S1_M_st_data[28], S1_M_st_data[29], S1_M_st_data[30], S1_M_st_data[31], RD1_internal_MonDReg[24], RD1_internal_MonDReg[25], RD1_internal_MonDReg[26], RD1_internal_MonDReg[27], RD1_internal_MonDReg[28], RD1_internal_MonDReg[29], RD1_internal_MonDReg[30], RD1_internal_MonDReg[31], V1L50);

--CE1_q_b[26] is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|cpu_ociram_lpm_dram_bdp_component_module:cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_bp62:auto_generated|q_b[26] at M4K_X49_Y18

CE1_q_b[26] = AMPP_FUNCTION(RD1L71, RD1_MonWr, QC2__clk0, QC2__clk0, S1L2325Q, S1L2330Q, S1L2335Q, S1L2340Q, S1L2345Q, S1L2350Q, S1L2355Q, S1L2360Q, V1L16, V1L17, V1L20, V1L21, V1L22, V1L23, V1L24, V1L25, V1L49, RD1_internal_MonDReg[16], RD1_internal_MonDReg[17], RD1_internal_MonDReg[18], RD1_internal_MonDReg[19], RD1_internal_MonDReg[20], RD1_internal_MonDReg[21], RD1_internal_MonDReg[22], RD1_internal_MonDReg[23], RD1_MonAReg[2], RD1_MonAReg[3], RD1_MonAReg[4], RD1_MonAReg[5], RD1_MonAReg[6], RD1_MonAReg[7], RD1_MonAReg[8], RD1_MonAReg[9], S1_M_st_data[24], S1_M_st_data[25], S1_M_st_data[26], S1_M_st_data[27], S1_M_st_data[28], S1_M_st_data[29], S1_M_st_data[30], S1_M_st_data[31], RD1_internal_MonDReg[24], RD1_internal_MonDReg[25], RD1_internal_MonDReg[26], RD1_internal_MonDReg[27], RD1_internal_MonDReg[28], RD1_internal_MonDReg[29], RD1_internal_MonDReg[30], RD1_internal_MonDReg[31], V1L50);

--CE1_q_b[25] is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|cpu_ociram_lpm_dram_bdp_component_module:cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_bp62:auto_generated|q_b[25] at M4K_X49_Y18

CE1_q_b[25] = AMPP_FUNCTION(RD1L71, RD1_MonWr, QC2__clk0, QC2__clk0, S1L2325Q, S1L2330Q, S1L2335Q, S1L2340Q, S1L2345Q, S1L2350Q, S1L2355Q, S1L2360Q, V1L16, V1L17, V1L20, V1L21, V1L22, V1L23, V1L24, V1L25, V1L49, RD1_internal_MonDReg[16], RD1_internal_MonDReg[17], RD1_internal_MonDReg[18], RD1_internal_MonDReg[19], RD1_internal_MonDReg[20], RD1_internal_MonDReg[21], RD1_internal_MonDReg[22], RD1_internal_MonDReg[23], RD1_MonAReg[2], RD1_MonAReg[3], RD1_MonAReg[4], RD1_MonAReg[5], RD1_MonAReg[6], RD1_MonAReg[7], RD1_MonAReg[8], RD1_MonAReg[9], S1_M_st_data[24], S1_M_st_data[25], S1_M_st_data[26], S1_M_st_data[27], S1_M_st_data[28], S1_M_st_data[29], S1_M_st_data[30], S1_M_st_data[31], RD1_internal_MonDReg[24], RD1_internal_MonDReg[25], RD1_internal_MonDReg[26], RD1_internal_MonDReg[27], RD1_internal_MonDReg[28], RD1_internal_MonDReg[29], RD1_internal_MonDReg[30], RD1_internal_MonDReg[31], V1L50);

--CE1_q_b[24] is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|cpu_ociram_lpm_dram_bdp_component_module:cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_bp62:auto_generated|q_b[24] at M4K_X49_Y18

CE1_q_b[24] = AMPP_FUNCTION(RD1L71, RD1_MonWr, QC2__clk0, QC2__clk0, S1L2325Q, S1L2330Q, S1L2335Q, S1L2340Q, S1L2345Q, S1L2350Q, S1L2355Q, S1L2360Q, V1L16, V1L17, V1L20, V1L21, V1L22, V1L23, V1L24, V1L25, V1L49, RD1_internal_MonDReg[16], RD1_internal_MonDReg[17], RD1_internal_MonDReg[18], RD1_internal_MonDReg[19], RD1_internal_MonDReg[20], RD1_internal_MonDReg[21], RD1_internal_MonDReg[22], RD1_internal_MonDReg[23], RD1_MonAReg[2], RD1_MonAReg[3], RD1_MonAReg[4], RD1_MonAReg[5], RD1_MonAReg[6], RD1_MonAReg[7], RD1_MonAReg[8], RD1_MonAReg[9], S1_M_st_data[24], S1_M_st_data[25], S1_M_st_data[26], S1_M_st_data[27], S1_M_st_data[28], S1_M_st_data[29], S1_M_st_data[30], S1_M_st_data[31], RD1_internal_MonDReg[24], RD1_internal_MonDReg[25], RD1_internal_MonDReg[26], RD1_internal_MonDReg[27], RD1_internal_MonDReg[28], RD1_internal_MonDReg[29], RD1_internal_MonDReg[30], RD1_internal_MonDReg[31], V1L50);

--WC1L22 is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|readdata[18]~1339 at LC_X43_Y19_N5

--operation mode is normal

WC1L22 = AMPP_FUNCTION(S1_ic_fill_line[5], S1L1756Q, V1L6, CE1_q_a[18]);

--S1L579Q is std_1c20:inst|cpu:the_cpu|d_readdata_d1[18]~179 at LC_X43_Y19_N5

--operation mode is normal

S1L579Q = AMPP_FUNCTION(QC2__clk0, S1_ic_fill_line[5], S1L1756Q, V1L6, CE1_q_a[18], F1_data_out);

--S1L1284 is std_1c20:inst|cpu:the_cpu|F_pc_plus_one[0]~48 at LC_X27_Y19_N3

--operation mode is arithmetic

S1L1284 = AMPP_FUNCTION(S1_F_pc[0]);

--S1_D_pc_plus_one[0] is std_1c20:inst|cpu:the_cpu|D_pc_plus_one[0] at LC_X27_Y19_N3

--operation mode is arithmetic

S1_D_pc_plus_one[0] = AMPP_FUNCTION(QC2__clk0, S1_F_pc[0], F1_data_out, S1_W_stall);

--S1L1285 is std_1c20:inst|cpu:the_cpu|F_pc_plus_one[0]~49 at LC_X27_Y19_N3

--operation mode is arithmetic

S1L1285 = AMPP_FUNCTION(S1_F_pc[0]);

--S1L1286 is std_1c20:inst|cpu:the_cpu|F_pc_plus_one[0]~49COUT1_980 at LC_X27_Y19_N3

--operation mode is arithmetic

S1L1286 = AMPP_FUNCTION(S1_F_pc[0]);

--S1L1178 is std_1c20:inst|cpu:the_cpu|Equal53~861 at LC_X30_Y14_N9

--operation mode is normal

S1L1178 = AMPP_FUNCTION(S1_D_iw[0], S1_D_iw[3], S1_D_iw[1], S1_D_iw[2]);

--S1L280 is std_1c20:inst|cpu:the_cpu|D_ctrl_alu_subtract~405 at LC_X30_Y13_N7

--operation mode is normal

S1L280 = AMPP_FUNCTION(S1L1176, S1L1168, S1_D_iw[4], S1L1178);

--S1L281 is std_1c20:inst|cpu:the_cpu|D_ctrl_alu_subtract~406 at LC_X30_Y13_N8

--operation mode is normal

S1L281 = AMPP_FUNCTION(S1_D_iw[4], S1L1177, S1L1175);

--S1L282 is std_1c20:inst|cpu:the_cpu|D_ctrl_alu_subtract~407 at LC_X30_Y13_N9

--operation mode is normal

S1L282 = AMPP_FUNCTION(S1_D_iw[12], S1L1168, S1_D_iw[5], S1_D_iw[13]);

--S1L283 is std_1c20:inst|cpu:the_cpu|D_ctrl_alu_subtract~408 at LC_X31_Y14_N7

--operation mode is normal

S1L283 = AMPP_FUNCTION(S1_D_iw[15], S1_D_iw[14], S1_D_iw[11]);

--S1_M_shift_rot_cnt[0] is std_1c20:inst|cpu:the_cpu|M_shift_rot_cnt[0] at LC_X38_Y13_N4

--operation mode is normal

S1_M_shift_rot_cnt[0] = AMPP_FUNCTION(QC2__clk0, S1_M_shift_rot_stall, S1L922, S1_M_shift_rot_cnt[0], F1_data_out);

--S1_M_shift_rot_cnt[2] is std_1c20:inst|cpu:the_cpu|M_shift_rot_cnt[2] at LC_X38_Y12_N7

--operation mode is normal

S1_M_shift_rot_cnt[2] = AMPP_FUNCTION(QC2__clk0, S1_M_shift_rot_stall, S1L932, S1L136, F1_data_out);

--S1_M_shift_rot_cnt[4] is std_1c20:inst|cpu:the_cpu|M_shift_rot_cnt[4] at LC_X38_Y12_N5

--operation mode is normal

S1_M_shift_rot_cnt[4] = AMPP_FUNCTION(QC2__clk0, S1_M_shift_rot_stall, S1L139, S1L942, F1_data_out);

--S1_M_shift_rot_cnt[3] is std_1c20:inst|cpu:the_cpu|M_shift_rot_cnt[3] at LC_X38_Y12_N9

--operation mode is normal

S1_M_shift_rot_cnt[3] = AMPP_FUNCTION(QC2__clk0, S1_M_shift_rot_stall, S1L140, S1L937, F1_data_out);

--Z1_timeout_occurred is std_1c20:inst|high_res_timer:the_high_res_timer|timeout_occurred at LC_X53_Y23_N5

--operation mode is normal

Z1_timeout_occurred_lut_out = Z1L234 & (!AB1_cpu_data_master_requests_high_res_timer_s1 # !RB1L7 # !XE1L21);

Z1_timeout_occurred = DFFEAS(Z1_timeout_occurred_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--G1_readdata[3] is std_1c20:inst|button_pio:the_button_pio|readdata[3] at LC_X44_Y25_N9

--operation mode is normal

G1_readdata[3]_lut_out = S1_M_alu_result[3] & G1L32 # !S1_M_alu_result[3] & (!S1L1726Q & in_port_to_the_button_pio[3]);

G1_readdata[3] = DFFEAS(G1_readdata[3]_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--XE1_readdata[3] is std_1c20:inst|uart1:the_uart1|uart1_regs:the_uart1_regs|readdata[3] at LC_X47_Y22_N6

--operation mode is normal

XE1_readdata[3]_lut_out = !S1L1738Q & (S1L1726Q & XE1L54 # !S1L1726Q & (XE1L55));

XE1_readdata[3] = DFFEAS(XE1_readdata[3]_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--RB1_readdata[3] is std_1c20:inst|sys_clk_timer:the_sys_clk_timer|readdata[3] at LC_X53_Y25_N1

--operation mode is normal

RB1_readdata[3]_lut_out = RB1L193 # RB1L192 # !RB1_period_l_register[3] & XE1L20;

RB1_readdata[3] = DFFEAS(RB1_readdata[3]_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--SB1L3 is std_1c20:inst|sys_clk_timer_s1_arbitrator:the_sys_clk_timer_s1|cpu_data_master_requests_sys_clk_timer_s1~181 at LC_X42_Y25_N1

--operation mode is normal

SB1L3 = S1L1686Q & !S1_M_alu_result[7] & UB1L5 & SB1L5;

--T1_registered_cpu_data_master_readdata[3] is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|registered_cpu_data_master_readdata[3] at LC_X45_Y25_N1

--operation mode is normal

T1_registered_cpu_data_master_readdata[3]_lut_out = T1L473 & T1L503 & (KB1_za_data[3] # !S1L1693Q);

T1_registered_cpu_data_master_readdata[3] = DFFEAS(T1_registered_cpu_data_master_readdata[3]_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--T1L70 is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[3]~5180 at LC_X45_Y25_N8

--operation mode is normal

T1L70 = T1_registered_cpu_data_master_readdata[3] # !N1_cpu_data_master_requests_clock_1_in & (!CB1L2 # !UB1L9);

--Z1_readdata[3] is std_1c20:inst|high_res_timer:the_high_res_timer|readdata[3] at LC_X54_Y25_N7

--operation mode is normal

Z1_readdata[3]_lut_out = Z1L189 # Z1L190 # !Z1_period_l_register[3] & XE1L20;

Z1_readdata[3] = DFFEAS(Z1_readdata[3]_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--T1L71 is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[3]~5181 at LC_X46_Y24_N6

--operation mode is normal

T1L71 = T1L70 & (Z1_readdata[3] # !AB1_cpu_data_master_requests_high_res_timer_s1);

--T1L73 is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[3]~5183 at LC_X44_Y25_N2

--operation mode is normal

T1L73 = T1L79 # T1L77 # !A1L138 & EB1L18;

--DE1_data_to_cpu[3] is std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|data_to_cpu[3] at LC_X39_Y27_N7

--operation mode is normal

DE1_data_to_cpu[3]_lut_out = DE1L255 & DE1_iROE_reg # !DE1L255 & (DE1L3);

DE1_data_to_cpu[3] = DFFEAS(DE1_data_to_cpu[3]_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , DE1_ROE, , , DE1L256);

--S1L482Q is std_1c20:inst|cpu:the_cpu|d_readdata_d1[3]~221 at LC_X44_Y24_N0

--operation mode is normal

S1L482Q = AMPP_FUNCTION(QC2__clk0, DE1_data_to_cpu[3], FE1_q_a[3], W1L1, F1_data_out);

--S1L1390Q is std_1c20:inst|cpu:the_cpu|i_readdata_d1[3]~135 at LC_X45_Y19_N9

--operation mode is normal

S1L1390Q = AMPP_FUNCTION(QC2__clk0, FD1L1, CE1_q_a[3], V1L26, WC1L6, F1_data_out);

--T1L322 is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata~775 at LC_X43_Y23_N4

--operation mode is normal

T1L322 = S1L1726Q # !UB1L9 # !UB1L10;

--T1L271 is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[26]~5187 at LC_X42_Y23_N3

--operation mode is normal

T1L271 = !WB1_cpu_data_master_granted_uart1_s1 & T1L196 & T1L150 & T1L322;

--T1_registered_cpu_data_master_readdata[19] is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|registered_cpu_data_master_readdata[19] at LC_X40_Y22_N0

--operation mode is normal

T1_registered_cpu_data_master_readdata[19]_lut_out = !K1L6 & T1L487 & (BB1L30 # !CB1_cpu_data_master_requests_jtag_uart_avalon_jtag_slave);

T1_registered_cpu_data_master_readdata[19] = DFFEAS(T1_registered_cpu_data_master_readdata[19]_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--T1L221 is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[19]~5189 at LC_X40_Y23_N2

--operation mode is normal

T1L221 = !T1L226 & !T1L224 & (T1_registered_cpu_data_master_readdata[19] # !T1L241);

--W1L5 is std_1c20:inst|epcs_controller:the_epcs_controller|readdata[19]~689 at LC_X42_Y23_N5

--operation mode is normal

W1L5 = !W1L1 & FE1_q_a[19];

--S1L583Q is std_1c20:inst|cpu:the_cpu|d_readdata_d1[19]~175 at LC_X42_Y23_N6

--operation mode is normal

S1L583Q = AMPP_FUNCTION(QC2__clk0, X1_cpu_data_master_requests_epcs_controller_epcs_control_port, T1L271, T1L221, W1L5, F1_data_out);

--WC1L23 is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|readdata[19]~1342 at LC_X42_Y20_N9

--operation mode is normal

WC1L23 = AMPP_FUNCTION(S1L1756Q, V1L6, S1_ic_fill_line[5], CE1_q_a[19]);

--S1L584Q is std_1c20:inst|cpu:the_cpu|d_readdata_d1[19]~176 at LC_X42_Y20_N9

--operation mode is normal

S1L584Q = AMPP_FUNCTION(QC2__clk0, S1L1756Q, V1L6, S1_ic_fill_line[5], CE1_q_a[19], F1_data_out);

--S1L1287 is std_1c20:inst|cpu:the_cpu|F_pc_plus_one[1]~50 at LC_X27_Y19_N4

--operation mode is arithmetic

S1L1287 = AMPP_FUNCTION(S1_F_pc[1], S1L1285, S1L1286);

--S1_D_pc_plus_one[1] is std_1c20:inst|cpu:the_cpu|D_pc_plus_one[1] at LC_X27_Y19_N4

--operation mode is arithmetic

S1_D_pc_plus_one[1] = AMPP_FUNCTION(QC2__clk0, S1_F_pc[1], F1_data_out, S1_W_stall, S1L1285, S1L1286);

--S1L1288 is std_1c20:inst|cpu:the_cpu|F_pc_plus_one[1]~51 at LC_X27_Y19_N4

--operation mode is arithmetic

S1L1288 = AMPP_FUNCTION(S1_F_pc[1], S1L1285, S1L1286);

--S1L345Q is std_1c20:inst|cpu:the_cpu|D_issue~7 at LC_X25_Y19_N9

--operation mode is normal

S1L345Q = AMPP_FUNCTION(QC2__clk0, S1_F_pc[22], S1L1229, BD1_q_b[20], S1L1231, F1_data_out, S1_W_stall);

--S1L1183 is std_1c20:inst|cpu:the_cpu|Equal77~1064 at LC_X31_Y14_N9

--operation mode is normal

S1L1183 = AMPP_FUNCTION(S1_D_iw[14], S1_D_iw[16]);

--S1L1184 is std_1c20:inst|cpu:the_cpu|Equal77~1065 at LC_X31_Y14_N8

--operation mode is normal

S1L1184 = AMPP_FUNCTION(S1_D_iw[11], S1_D_iw[15], S1L1183, S1L1180);

--S1_E_ctrl_wrctl_inst is std_1c20:inst|cpu:the_cpu|E_ctrl_wrctl_inst at LC_X31_Y14_N8

--operation mode is normal

S1_E_ctrl_wrctl_inst = AMPP_FUNCTION(QC2__clk0, S1_D_iw[11], S1_D_iw[15], S1L1183, S1L1180, F1_data_out, S1_W_stall);

--S1L294 is std_1c20:inst|cpu:the_cpu|D_ctrl_flush_pipe_always~582 at LC_X29_Y14_N7

--operation mode is normal

S1L294 = AMPP_FUNCTION(S1_D_iw[16], S1_D_iw[13]);

--S1L295 is std_1c20:inst|cpu:the_cpu|D_ctrl_flush_pipe_always~583 at LC_X29_Y14_N6

--operation mode is normal

S1L295 = AMPP_FUNCTION(S1L294, S1_D_iw[11], S1L1179, S1_D_iw[12]);

--S1L305 is std_1c20:inst|cpu:the_cpu|D_ctrl_jmp_indirect~44 at LC_X29_Y14_N5

--operation mode is normal

S1L305 = AMPP_FUNCTION(S1_D_iw[11], S1_D_iw[16]);

--S1L296 is std_1c20:inst|cpu:the_cpu|D_ctrl_flush_pipe_always~584 at LC_X29_Y14_N2

--operation mode is normal

S1L296 = AMPP_FUNCTION(S1_D_iw[14], S1_D_iw[11], S1_D_iw[16], S1_D_iw[13]);

--S1L297 is std_1c20:inst|cpu:the_cpu|D_ctrl_flush_pipe_always~585 at LC_X29_Y14_N3

--operation mode is normal

S1L297 = AMPP_FUNCTION(S1_D_iw[12], S1_D_iw[15], S1L296, S1L305);

--S1L298 is std_1c20:inst|cpu:the_cpu|D_ctrl_flush_pipe_always~586 at LC_X29_Y14_N9

--operation mode is normal

S1L298 = AMPP_FUNCTION(S1L1168, S1L297, S1L1171, S1L295);

--XC1L3 is std_1c20:inst|cpu:the_cpu|cpu_test_bench:the_cpu_test_bench|Add0~561 at LC_X35_Y13_N5

--operation mode is arithmetic

XC1L3 = AMPP_FUNCTION(S1L1070, S1L884);

--XC1L4 is std_1c20:inst|cpu:the_cpu|cpu_test_bench:the_cpu_test_bench|Add0~561COUT1_1899 at LC_X35_Y13_N5

--operation mode is arithmetic

XC1L4 = AMPP_FUNCTION(S1L1070, S1L884);

--YC1_result[31] is std_1c20:inst|cpu:the_cpu|lpm_add_sub:Add8|alt_stratix_add_sub:stratix_adder|result[31] at LC_X36_Y13_N1

--operation mode is arithmetic

YC1_result[31] = AMPP_FUNCTION(S1L696, S1L691, YC1L85, YC1L87, YC1L88, S1_E_ctrl_alu_subtract);

--YC1L90 is std_1c20:inst|cpu:the_cpu|lpm_add_sub:Add8|alt_stratix_add_sub:stratix_adder|add_sub_cell[31]~COUT at LC_X36_Y13_N1

--operation mode is arithmetic

YC1L90 = AMPP_FUNCTION(S1L696, S1L691, YC1L87, S1_E_ctrl_alu_subtract);

--YC1L91 is std_1c20:inst|cpu:the_cpu|lpm_add_sub:Add8|alt_stratix_add_sub:stratix_adder|add_sub_cell[31]~COUTCOUT1_1345 at LC_X36_Y13_N1

--operation mode is arithmetic

YC1L91 = AMPP_FUNCTION(S1L696, S1L691, YC1L88, S1_E_ctrl_alu_subtract);

--SD1_internal_jdo1[19] is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|internal_jdo1[19] at LC_X47_Y15_N7

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

SD1_internal_jdo1[19] = AMPP_FUNCTION(A1L8, SD1_sr[19], VCC, GND, SD1L144);

--SD1_internal_jdo1[18] is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|internal_jdo1[18] at LC_X47_Y15_N8

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

SD1_internal_jdo1[18] = AMPP_FUNCTION(A1L8, SD1_sr[18], VCC, GND, SD1L144);

--SD1_sr[21] is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|sr[21] at LC_X47_Y16_N8

--operation mode is normal

SD1_sr[21] = AMPP_FUNCTION(A1L5, SD1L8, SD1L9, SD1L10, SD1_sr[22], !C1_CLR_SIGNAL, SD1L12);

--C1_jtag_debug_mode is sld_hub:sld_hub_inst|jtag_debug_mode at LC_X57_Y15_N6

--operation mode is normal

C1_jtag_debug_mode = AMPP_FUNCTION(A1L5, FF1_state[15], C1L32, C1_jtag_debug_mode, C1L33, FF1_state[0]);

--BF2_Q[0] is sld_hub:sld_hub_inst|sld_dffex:BROADCAST|Q[0] at LC_X57_Y17_N7

--operation mode is normal

BF2_Q[0] = AMPP_FUNCTION(A1L5, BF2_Q[0], GF1_dffe1a[1], C1L1, BF9_Q[0], !C1_CLR_SIGNAL);

--SD1L144 is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|process3~14 at LC_X56_Y16_N2

--operation mode is normal

SD1L144 = AMPP_FUNCTION(BF2_Q[0], C1_jtag_debug_mode_usr1, BF8_Q[0], C1_jtag_debug_mode);

--SD1_sr[20] is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|sr[20] at LC_X47_Y16_N6

--operation mode is normal

SD1_sr[20] = AMPP_FUNCTION(A1L5, SD1L14, SD1L9, SD1_sr[21], SD1L15, !C1_CLR_SIGNAL, SD1L12);

--FF1_state[1] is sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state[1] at LC_X57_Y15_N8

--operation mode is normal

FF1_state[1] = AMPP_FUNCTION(A1L5, FF1_state[0], FF1_state[1], FF1_state[8], FF1_state[15], VCC, A1L7);

--BF1_Q[0] is sld_hub:sld_hub_inst|sld_dffex:RESET|Q[0] at LC_X57_Y17_N3

--operation mode is normal

BF1_Q[0] = AMPP_FUNCTION(A1L5, BF2_Q[0], BF1_Q[0], GF1_dffe1a[7], C1L2, C1_jtag_debug_mode_usr1);

--SD1_sr[34] is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|sr[34] at LC_X46_Y15_N9

--operation mode is normal

SD1_sr[34] = AMPP_FUNCTION(A1L5, SD1L17, SD1L141, SD1_sr[35], SD1L16, !C1_CLR_SIGNAL, SD1L12);

--SD1_dr_update2 is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|dr_update2 at LC_X46_Y17_N0

--operation mode is normal

SD1_dr_update2 = AMPP_FUNCTION(QC2__clk0, SD1_dr_update1, VCC);

--SD1_dr_update1 is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|dr_update1 at LC_X46_Y17_N5

--operation mode is normal

SD1_dr_update1 = AMPP_FUNCTION(QC2__clk0, SD1_st_updatedr, VCC);

--SD1_sr[35] is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|sr[35] at LC_X46_Y15_N8

--operation mode is normal

SD1_sr[35] = AMPP_FUNCTION(A1L5, SD1_ir[1], SD1L133, SD1L19, SD1L18, !C1_CLR_SIGNAL, !SD1_ir[0], SD1L12);

--BF5_Q[0] is sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:1:IRF|Q[0] at LC_X57_Y16_N4

--operation mode is normal

BF5_Q[0] = AMPP_FUNCTION(A1L5, BF3_Q[0], BF2_Q[0], BF7_Q[0], !C1_CLR_SIGNAL, C1L26);

--SD1_st_updateir is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|st_updateir at LC_X54_Y16_N4

--operation mode is normal

SD1_st_updateir = AMPP_FUNCTION(A1L5, SD1L145, VCC, A1L8);

--SD1L117 is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|ir[0]~0 at LC_X54_Y16_N7

--operation mode is normal

SD1L117 = AMPP_FUNCTION(SD1_st_updateir, C1_CLR_SIGNAL);

--BF5_Q[1] is sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:1:IRF|Q[1] at LC_X57_Y16_N7

--operation mode is normal

BF5_Q[1] = AMPP_FUNCTION(A1L5, BF2_Q[0], BF3_Q[1], BF7_Q[1], !C1_CLR_SIGNAL, C1L26);

--S1_E_ctrl_break is std_1c20:inst|cpu:the_cpu|E_ctrl_break at LC_X32_Y14_N4

--operation mode is normal

S1_E_ctrl_break = AMPP_FUNCTION(QC2__clk0, S1L1182, S1_D_iw[15], S1_D_iw[13], S1L306, F1_data_out, S1_W_stall);

--RD1L70 is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|module_input6~26 at LC_X43_Y19_N9

--operation mode is normal

RD1L70 = AMPP_FUNCTION(S1_hbreak_enabled, S1_internal_d_write, V1L6);

--FD1L38 is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_avalon_reg:the_cpu_nios2_avalon_reg|take_action_ocireg~15 at LC_X45_Y19_N2

--operation mode is normal

FD1L38 = AMPP_FUNCTION(FD1L2, FD1L1, RD1L70, V1L16);

--S1L1340 is std_1c20:inst|cpu:the_cpu|F_pc_plus_one[20]~52 at LC_X27_Y17_N3

--operation mode is arithmetic

S1L1340 = AMPP_FUNCTION(S1_F_pc[20], S1L1330, S1L1338, S1L1339);

--S1_D_pc_plus_one[20] is std_1c20:inst|cpu:the_cpu|D_pc_plus_one[20] at LC_X27_Y17_N3

--operation mode is arithmetic

S1_D_pc_plus_one[20] = AMPP_FUNCTION(QC2__clk0, S1_F_pc[20], F1_data_out, S1_W_stall, S1L1330, S1L1338, S1L1339);

--S1L1341 is std_1c20:inst|cpu:the_cpu|F_pc_plus_one[20]~53 at LC_X27_Y17_N3

--operation mode is arithmetic

S1L1341 = AMPP_FUNCTION(S1_F_pc[20], S1L1338);

--S1L1342 is std_1c20:inst|cpu:the_cpu|F_pc_plus_one[20]~53COUT1_1012 at LC_X27_Y17_N3

--operation mode is arithmetic

S1L1342 = AMPP_FUNCTION(S1_F_pc[20], S1L1339);

--T1_registered_cpu_data_master_readdata[22] is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|registered_cpu_data_master_readdata[22] at LC_X40_Y22_N3

--operation mode is normal

T1_registered_cpu_data_master_readdata[22]_lut_out = T1L490 & !K1L6 & (BB1L34 # !CB1_cpu_data_master_requests_jtag_uart_avalon_jtag_slave);

T1_registered_cpu_data_master_readdata[22] = DFFEAS(T1_registered_cpu_data_master_readdata[22]_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--T1L241 is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[22]~5191 at LC_X41_Y23_N8

--operation mode is normal

T1L241 = N1_cpu_data_master_requests_clock_1_in # S1L1693Q # CB1_cpu_data_master_requests_jtag_uart_avalon_jtag_slave # K1_cpu_data_master_requests_clock_0_in;

--T1L243 is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[22]~5193 at LC_X40_Y22_N8

--operation mode is normal

T1L243 = !T1L246 & !T1L248 & (T1_registered_cpu_data_master_readdata[22] # !T1L241);

--W1L8 is std_1c20:inst|epcs_controller:the_epcs_controller|readdata[22]~690 at LC_X41_Y22_N2

--operation mode is normal

W1L8 = !W1L1 & FE1_q_a[22];

--S1L598Q is std_1c20:inst|cpu:the_cpu|d_readdata_d1[22]~172 at LC_X41_Y22_N3

--operation mode is normal

S1L598Q = AMPP_FUNCTION(QC2__clk0, X1_cpu_data_master_requests_epcs_controller_epcs_control_port, T1L271, T1L243, W1L8, F1_data_out);

--WC1L26 is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|readdata[22]~1343 at LC_X42_Y20_N0

--operation mode is normal

WC1L26 = AMPP_FUNCTION(S1L1756Q, V1L6, S1_ic_fill_line[5], CE1_q_a[22]);

--S1L599Q is std_1c20:inst|cpu:the_cpu|d_readdata_d1[22]~173 at LC_X42_Y20_N0

--operation mode is normal

S1L599Q = AMPP_FUNCTION(QC2__clk0, S1L1756Q, V1L6, S1_ic_fill_line[5], CE1_q_a[22], F1_data_out);

--DE1_data_to_cpu[15] is std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|data_to_cpu[15] at LC_X36_Y29_N7

--operation mode is normal

DE1_data_to_cpu[15]_lut_out = DE1L253 & (DE1L140Q) # !DE1L253 & DE1L250Q & (DE1L252);

DE1_data_to_cpu[15] = DFFEAS(DE1_data_to_cpu[15]_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--T1L314 is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata~211 at LC_X40_Y26_N9

--operation mode is normal

T1L314 = W1L1 & DE1_data_to_cpu[15] # !W1L1 & (FE1_q_a[15]) # !X1_cpu_data_master_requests_epcs_controller_epcs_control_port;

--Z1_readdata[15] is std_1c20:inst|high_res_timer:the_high_res_timer|readdata[15] at LC_X56_Y26_N8

--operation mode is normal

Z1_readdata[15]_lut_out = S1_M_alu_result[3] & !S1L1738Q & (Z1L214 $ !Z1L213) # !S1_M_alu_result[3] & S1L1738Q & (Z1L213);

Z1_readdata[15] = DFFEAS(Z1_readdata[15]_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--RB1_readdata[15] is std_1c20:inst|sys_clk_timer:the_sys_clk_timer|readdata[15] at LC_X51_Y25_N4

--operation mode is normal

RB1_readdata[15]_lut_out = S1_M_alu_result[3] & !S1L1738Q & (RB1L217 $ !RB1L216) # !S1_M_alu_result[3] & S1L1738Q & (RB1L216);

RB1_readdata[15] = DFFEAS(RB1_readdata[15]_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--T1L192 is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[15]~5195 at LC_X48_Y26_N6

--operation mode is normal

T1L192 = Z1_readdata[15] & (RB1_readdata[15] # !SB1_cpu_data_master_requests_sys_clk_timer_s1) # !Z1_readdata[15] & !AB1_cpu_data_master_requests_high_res_timer_s1 & (RB1_readdata[15] # !SB1_cpu_data_master_requests_sys_clk_timer_s1);

--T1_registered_cpu_data_master_readdata[15] is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|registered_cpu_data_master_readdata[15] at LC_X44_Y27_N2

--operation mode is normal

T1_registered_cpu_data_master_readdata[15]_lut_out = T1L513 & T1L485 & (KB1_za_data[15] # !S1L1693Q);

T1_registered_cpu_data_master_readdata[15] = DFFEAS(T1_registered_cpu_data_master_readdata[15]_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--T1L193 is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[15]~5196 at LC_X41_Y26_N5

--operation mode is normal

T1L193 = S1L1689Q & (!T1_registered_cpu_data_master_readdata[15] & T1L241 # !T1L396) # !S1L1689Q & (!T1_registered_cpu_data_master_readdata[15] & T1L241);

--T1L194 is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[15]~5197 at LC_X41_Y26_N6

--operation mode is normal

T1L194 = !T1L193 & (Y1_internal_incoming_ext_ram_bus_data[15] # !Y1L146 & !Y1_cpu_data_master_requests_ext_ram_s1);

--S1L564Q is std_1c20:inst|cpu:the_cpu|d_readdata_d1[15]~131 at LC_X41_Y26_N8

--operation mode is normal

S1L564Q = AMPP_FUNCTION(QC2__clk0, T1L162, T1L314, T1L192, T1L194, F1_data_out);

--S1L1471Q is std_1c20:inst|cpu:the_cpu|i_readdata_d1[15]~147 at LC_X42_Y21_N6

--operation mode is normal

S1L1471Q = AMPP_FUNCTION(QC2__clk0, S1L1756Q, S1_ic_fill_line[5], V1L6, CE1_q_a[15], F1_data_out);

--T1L321 is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata~772 at LC_X40_Y25_N3

--operation mode is normal

T1L321 = !UB1L9 # !UB1L10 # !S1L1726Q;

--T1L249 is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[23]~5199 at LC_X42_Y23_N4

--operation mode is normal

T1L249 = T1L321 & T1L196 & T1L150 & !WB1_cpu_data_master_granted_uart1_s1;

--T1_registered_cpu_data_master_readdata[23] is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|registered_cpu_data_master_readdata[23] at LC_X43_Y22_N6

--operation mode is normal

T1_registered_cpu_data_master_readdata[23]_lut_out = !K1L6 & T1L491 & (KB1_za_data[23] # !S1L1693Q);

T1_registered_cpu_data_master_readdata[23] = DFFEAS(T1_registered_cpu_data_master_readdata[23]_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--T1L251 is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[23]~5201 at LC_X41_Y22_N6

--operation mode is normal

T1L251 = !T1L256 & !T1L254 & (T1_registered_cpu_data_master_readdata[23] # !T1L241);

--W1L9 is std_1c20:inst|epcs_controller:the_epcs_controller|readdata[23]~691 at LC_X42_Y22_N5

--operation mode is normal

W1L9 = !W1L1 & (FE1_q_a[23]);

--S1L603Q is std_1c20:inst|cpu:the_cpu|d_readdata_d1[23]~169 at LC_X41_Y22_N9

--operation mode is normal

S1L603Q = AMPP_FUNCTION(QC2__clk0, T1L251, X1_cpu_data_master_requests_epcs_controller_epcs_control_port, W1L9, T1L249, F1_data_out);

--WC1L27 is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|readdata[23]~1345 at LC_X42_Y20_N8

--operation mode is normal

WC1L27 = AMPP_FUNCTION(S1L1756Q, S1_ic_fill_line[5], V1L6, CE1_q_a[23]);

--S1L604Q is std_1c20:inst|cpu:the_cpu|d_readdata_d1[23]~170 at LC_X42_Y20_N8

--operation mode is normal

S1L604Q = AMPP_FUNCTION(QC2__clk0, S1L1756Q, S1_ic_fill_line[5], V1L6, CE1_q_a[23], F1_data_out);

--T1L81 is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[4]~5203 at LC_X44_Y23_N9

--operation mode is normal

T1L81 = !JB1L3 & (!SB1L2 # !H1L2) # !S1L1743Q;

--RB1_readdata[7] is std_1c20:inst|sys_clk_timer:the_sys_clk_timer|readdata[7] at LC_X51_Y25_N1

--operation mode is normal

RB1_readdata[7]_lut_out = S1_M_alu_result[3] & !S1L1738Q & (RB1L200 $ !RB1L201) # !S1_M_alu_result[3] & RB1L200 & S1L1738Q;

RB1_readdata[7] = DFFEAS(RB1_readdata[7]_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--Z1_readdata[7] is std_1c20:inst|high_res_timer:the_high_res_timer|readdata[7] at LC_X54_Y25_N3

--operation mode is normal

Z1_readdata[7]_lut_out = S1L1738Q & (!S1_M_alu_result[3] & Z1L197) # !S1L1738Q & S1_M_alu_result[3] & (Z1L198 $ !Z1L197);

Z1_readdata[7] = DFFEAS(Z1_readdata[7]_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--XE1_readdata[7] is std_1c20:inst|uart1:the_uart1|uart1_regs:the_uart1_regs|readdata[7] at LC_X51_Y23_N3

--operation mode is normal

XE1_readdata[7]_lut_out = !S1L1738Q & (S1L1726Q & (XE1L62) # !S1L1726Q & XE1L63);

XE1_readdata[7] = DFFEAS(XE1_readdata[7]_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--T1_registered_cpu_data_master_readdata[7] is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|registered_cpu_data_master_readdata[7] at LC_X42_Y26_N2

--operation mode is normal

T1_registered_cpu_data_master_readdata[7]_lut_out = T1L507 & T1L477 & (KB1_za_data[7] # !S1L1693Q);

T1_registered_cpu_data_master_readdata[7] = DFFEAS(T1_registered_cpu_data_master_readdata[7]_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--T1L118 is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[7]~5206 at LC_X42_Y26_N1

--operation mode is normal

T1L118 = T1_registered_cpu_data_master_readdata[7] # !K1_cpu_data_master_requests_clock_0_in & (!CB1L2 # !UB1L9);

--T1L120 is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[7]~5208 at LC_X43_Y26_N0

--operation mode is normal

T1L120 = T1L135 # T1L133 # !A1L134 & EB1L18;

--DE1_data_to_cpu[7] is std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|data_to_cpu[7] at LC_X39_Y27_N4

--operation mode is normal

DE1_data_to_cpu[7]_lut_out = DE1L255 & DE1_iRRDY_reg # !DE1L255 & (DE1L6);

DE1_data_to_cpu[7] = DFFEAS(DE1_data_to_cpu[7]_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , DE1_RRDY, , , DE1L256);

--U1L153 is std_1c20:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_readdata~2399 at LC_X43_Y26_N8

--operation mode is normal

U1L153 = W1L1 & DE1_data_to_cpu[7] # !W1L1 & (FE1_q_a[7]);

--S1L517Q is std_1c20:inst|cpu:the_cpu|d_readdata_d1[7]~112 at LC_X43_Y26_N2

--operation mode is normal

S1L517Q = AMPP_FUNCTION(QC2__clk0, X1_cpu_data_master_requests_epcs_controller_epcs_control_port, T1L131, U1L153, T1L127, F1_data_out);

--S1L518Q is std_1c20:inst|cpu:the_cpu|d_readdata_d1[7]~113 at LC_X42_Y21_N7

--operation mode is normal

S1L518Q = AMPP_FUNCTION(QC2__clk0, S1_ic_fill_line[5], V1L6, CE1_q_a[7], S1L1756Q, F1_data_out);

--T1_registered_cpu_data_master_readdata[31] is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|registered_cpu_data_master_readdata[31] at LC_X36_Y22_N9

--operation mode is normal

T1_registered_cpu_data_master_readdata[31]_lut_out = !K1L6 & T1L499 & (!CB1L2 # !UB1L9);

T1_registered_cpu_data_master_readdata[31] = DFFEAS(T1_registered_cpu_data_master_readdata[31]_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--T1L306 is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[31]~5213 at LC_X39_Y23_N5

--operation mode is normal

T1L306 = !T1L309 & !T1L311 & (T1_registered_cpu_data_master_readdata[31] # !T1L241);

--W1L16 is std_1c20:inst|epcs_controller:the_epcs_controller|readdata[31]~692 at LC_X37_Y21_N7

--operation mode is normal

W1L16 = FE1_q_a[31] & !W1L1;

--S1L643Q is std_1c20:inst|cpu:the_cpu|d_readdata_d1[31]~166 at LC_X39_Y23_N8

--operation mode is normal

S1L643Q = AMPP_FUNCTION(QC2__clk0, T1L211, X1_cpu_data_master_requests_epcs_controller_epcs_control_port, W1L16, T1L306, F1_data_out);

--WC1L35 is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|readdata[31]~1347 at LC_X38_Y20_N5

--operation mode is normal

WC1L35 = AMPP_FUNCTION(S1L1756Q, S1_ic_fill_line[5], CE1_q_a[31], V1L6);

--S1L644Q is std_1c20:inst|cpu:the_cpu|d_readdata_d1[31]~167 at LC_X38_Y20_N5

--operation mode is normal

S1L644Q = AMPP_FUNCTION(QC2__clk0, S1L1756Q, S1_ic_fill_line[5], CE1_q_a[31], V1L6, F1_data_out);

--S1L1337 is std_1c20:inst|cpu:the_cpu|F_pc_plus_one[19]~54 at LC_X27_Y17_N2

--operation mode is arithmetic

S1L1337 = AMPP_FUNCTION(S1_F_pc[19], S1L1330, S1L1335, S1L1336);

--S1_D_pc_plus_one[19] is std_1c20:inst|cpu:the_cpu|D_pc_plus_one[19] at LC_X27_Y17_N2

--operation mode is arithmetic

S1_D_pc_plus_one[19] = AMPP_FUNCTION(QC2__clk0, S1_F_pc[19], F1_data_out, S1_W_stall, S1L1330, S1L1335, S1L1336);

--S1L1338 is std_1c20:inst|cpu:the_cpu|F_pc_plus_one[19]~55 at LC_X27_Y17_N2

--operation mode is arithmetic

S1L1338 = AMPP_FUNCTION(S1_F_pc[19], S1L1335);

--S1L1339 is std_1c20:inst|cpu:the_cpu|F_pc_plus_one[19]~55COUT1_1010 at LC_X27_Y17_N2

--operation mode is arithmetic

S1L1339 = AMPP_FUNCTION(S1_F_pc[19], S1L1336);

--T1_registered_cpu_data_master_readdata[21] is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|registered_cpu_data_master_readdata[21] at LC_X40_Y22_N9

--operation mode is normal

T1_registered_cpu_data_master_readdata[21]_lut_out = T1L489 & !K1L6 & (BB1L39 # !CB1_cpu_data_master_requests_jtag_uart_avalon_jtag_slave);

T1_registered_cpu_data_master_readdata[21] = DFFEAS(T1_registered_cpu_data_master_readdata[21]_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--T1L235 is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[21]~5216 at LC_X40_Y23_N6

--operation mode is normal

T1L235 = !T1L240 & !T1L238 & (T1_registered_cpu_data_master_readdata[21] # !T1L241);

--W1L7 is std_1c20:inst|epcs_controller:the_epcs_controller|readdata[21]~693 at LC_X41_Y21_N0

--operation mode is normal

W1L7 = FE1_q_a[21] & !W1L1;

--S1L593Q is std_1c20:inst|cpu:the_cpu|d_readdata_d1[21]~163 at LC_X41_Y21_N1

--operation mode is normal

S1L593Q = AMPP_FUNCTION(QC2__clk0, T1L249, X1_cpu_data_master_requests_epcs_controller_epcs_control_port, T1L235, W1L7, F1_data_out);

--WC1L25 is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|readdata[21]~1348 at LC_X41_Y21_N4

--operation mode is normal

WC1L25 = AMPP_FUNCTION(S1L1756Q, S1_ic_fill_line[5], V1L6, CE1_q_a[21]);

--S1L594Q is std_1c20:inst|cpu:the_cpu|d_readdata_d1[21]~164 at LC_X41_Y21_N4

--operation mode is normal

S1L594Q = AMPP_FUNCTION(QC2__clk0, S1L1756Q, S1_ic_fill_line[5], V1L6, CE1_q_a[21], F1_data_out);

--S1L1331 is std_1c20:inst|cpu:the_cpu|F_pc_plus_one[17]~56 at LC_X27_Y17_N0

--operation mode is arithmetic

S1L1331 = AMPP_FUNCTION(S1_F_pc[17], S1L1330);

--S1_D_pc_plus_one[17] is std_1c20:inst|cpu:the_cpu|D_pc_plus_one[17] at LC_X27_Y17_N0

--operation mode is arithmetic

S1_D_pc_plus_one[17] = AMPP_FUNCTION(QC2__clk0, S1_F_pc[17], F1_data_out, S1_W_stall, S1L1330);

--S1L1332 is std_1c20:inst|cpu:the_cpu|F_pc_plus_one[17]~57 at LC_X27_Y17_N0

--operation mode is arithmetic

S1L1332 = AMPP_FUNCTION(S1_F_pc[17]);

--S1L1333 is std_1c20:inst|cpu:the_cpu|F_pc_plus_one[17]~57COUT1_1006 at LC_X27_Y17_N0

--operation mode is arithmetic

S1L1333 = AMPP_FUNCTION(S1_F_pc[17]);

--S1L1329 is std_1c20:inst|cpu:the_cpu|F_pc_plus_one[16]~58 at LC_X27_Y18_N9

--operation mode is arithmetic

S1L1329 = AMPP_FUNCTION(S1_F_pc[16], S1L1316, S1L1327, S1L1328);

--S1_D_pc_plus_one[16] is std_1c20:inst|cpu:the_cpu|D_pc_plus_one[16] at LC_X27_Y18_N9

--operation mode is arithmetic

S1_D_pc_plus_one[16] = AMPP_FUNCTION(QC2__clk0, S1_F_pc[16], F1_data_out, S1_W_stall, S1L1316, S1L1327, S1L1328);

--S1L1330 is std_1c20:inst|cpu:the_cpu|F_pc_plus_one[16]~59 at LC_X27_Y18_N9

--operation mode is arithmetic

S1L1330 = AMPP_FUNCTION(S1_F_pc[16], S1L1316, S1L1327, S1L1328);

--S1L1345 is std_1c20:inst|cpu:the_cpu|F_pc_plus_one[22]~60 at LC_X27_Y17_N5

--operation mode is arithmetic

S1L1345 = AMPP_FUNCTION(S1_F_pc[22], S1L1344);

--S1_D_pc_plus_one[22] is std_1c20:inst|cpu:the_cpu|D_pc_plus_one[22] at LC_X27_Y17_N5

--operation mode is arithmetic

S1_D_pc_plus_one[22] = AMPP_FUNCTION(QC2__clk0, S1_F_pc[22], F1_data_out, S1_W_stall, S1L1344);

--S1L1346 is std_1c20:inst|cpu:the_cpu|F_pc_plus_one[22]~61 at LC_X27_Y17_N5

--operation mode is arithmetic

S1L1346 = AMPP_FUNCTION(S1_F_pc[22]);

--S1L1347 is std_1c20:inst|cpu:the_cpu|F_pc_plus_one[22]~61COUT1_1014 at LC_X27_Y17_N5

--operation mode is arithmetic

S1L1347 = AMPP_FUNCTION(S1_F_pc[22]);

--T1_registered_cpu_data_master_readdata[24] is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|registered_cpu_data_master_readdata[24] at LC_X40_Y22_N7

--operation mode is normal

T1_registered_cpu_data_master_readdata[24]_lut_out = !K1L6 & T1L492 & (!UB1L9 # !CB1L2);

T1_registered_cpu_data_master_readdata[24] = DFFEAS(T1_registered_cpu_data_master_readdata[24]_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--T1L258 is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[24]~5219 at LC_X39_Y23_N6

--operation mode is normal

T1L258 = !T1L261 & !T1L263 & (T1_registered_cpu_data_master_readdata[24] # !T1L241);

--W1L10 is std_1c20:inst|epcs_controller:the_epcs_controller|readdata[24]~694 at LC_X40_Y21_N2

--operation mode is normal

W1L10 = !W1L1 & FE1_q_a[24];

--S1L608Q is std_1c20:inst|cpu:the_cpu|d_readdata_d1[24]~160 at LC_X39_Y23_N7

--operation mode is normal

S1L608Q = AMPP_FUNCTION(QC2__clk0, T1L211, W1L10, X1_cpu_data_master_requests_epcs_controller_epcs_control_port, T1L258, F1_data_out);

--WC1L28 is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|readdata[24]~1349 at LC_X39_Y21_N8

--operation mode is normal

WC1L28 = AMPP_FUNCTION(S1L1756Q, V1L6, S1_ic_fill_line[5], CE1_q_a[24]);

--S1L609Q is std_1c20:inst|cpu:the_cpu|d_readdata_d1[24]~161 at LC_X39_Y21_N8

--operation mode is normal

S1L609Q = AMPP_FUNCTION(QC2__clk0, S1L1756Q, V1L6, S1_ic_fill_line[5], CE1_q_a[24], F1_data_out);

--S1L1323 is std_1c20:inst|cpu:the_cpu|F_pc_plus_one[14]~62 at LC_X27_Y18_N7

--operation mode is arithmetic

S1L1323 = AMPP_FUNCTION(S1_F_pc[14], S1L1316, S1L1321, S1L1322);

--S1_D_pc_plus_one[14] is std_1c20:inst|cpu:the_cpu|D_pc_plus_one[14] at LC_X27_Y18_N7

--operation mode is arithmetic

S1_D_pc_plus_one[14] = AMPP_FUNCTION(QC2__clk0, S1_F_pc[14], F1_data_out, S1_W_stall, S1L1316, S1L1321, S1L1322);

--S1L1324 is std_1c20:inst|cpu:the_cpu|F_pc_plus_one[14]~63 at LC_X27_Y18_N7

--operation mode is arithmetic

S1L1324 = AMPP_FUNCTION(S1_F_pc[14], S1L1321);

--S1L1325 is std_1c20:inst|cpu:the_cpu|F_pc_plus_one[14]~63COUT1_1002 at LC_X27_Y18_N7

--operation mode is arithmetic

S1L1325 = AMPP_FUNCTION(S1_F_pc[14], S1L1322);

--T1_registered_cpu_data_master_readdata[16] is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|registered_cpu_data_master_readdata[16] at LC_X43_Y22_N4

--operation mode is normal

T1_registered_cpu_data_master_readdata[16]_lut_out = !K1L6 & BB1L41 & (KB1_za_data[16] # !S1L1693Q);

T1_registered_cpu_data_master_readdata[16] = DFFEAS(T1_registered_cpu_data_master_readdata[16]_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--T1L198 is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[16]~5222 at LC_X41_Y22_N4

--operation mode is normal

T1L198 = !T1L201 & !T1L203 & (T1_registered_cpu_data_master_readdata[16] # !T1L241);

--W1L2 is std_1c20:inst|epcs_controller:the_epcs_controller|readdata[16]~695 at LC_X41_Y22_N1

--operation mode is normal

W1L2 = !W1L1 & FE1_q_a[16];

--S1L568Q is std_1c20:inst|cpu:the_cpu|d_readdata_d1[16]~157 at LC_X41_Y22_N7

--operation mode is normal

S1L568Q = AMPP_FUNCTION(QC2__clk0, T1L249, X1_cpu_data_master_requests_epcs_controller_epcs_control_port, T1L198, W1L2, F1_data_out);

--WC1L19 is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|readdata[16]~1350 at LC_X42_Y20_N5

--operation mode is normal

WC1L19 = AMPP_FUNCTION(S1L1756Q, V1L6, S1_ic_fill_line[5], CE1_q_a[16]);

--S1L569Q is std_1c20:inst|cpu:the_cpu|d_readdata_d1[16]~158 at LC_X42_Y20_N5

--operation mode is normal

S1L569Q = AMPP_FUNCTION(QC2__clk0, S1L1756Q, V1L6, S1_ic_fill_line[5], CE1_q_a[16], F1_data_out);

--S1L1320 is std_1c20:inst|cpu:the_cpu|F_pc_plus_one[13]~64 at LC_X27_Y18_N6

--operation mode is arithmetic

S1L1320 = AMPP_FUNCTION(S1_F_pc[13], S1L1316, S1L1318, S1L1319);

--S1_D_pc_plus_one[13] is std_1c20:inst|cpu:the_cpu|D_pc_plus_one[13] at LC_X27_Y18_N6

--operation mode is arithmetic

S1_D_pc_plus_one[13] = AMPP_FUNCTION(QC2__clk0, S1_F_pc[13], F1_data_out, S1_W_stall, S1L1316, S1L1318, S1L1319);

--S1L1321 is std_1c20:inst|cpu:the_cpu|F_pc_plus_one[13]~65 at LC_X27_Y18_N6

--operation mode is arithmetic

S1L1321 = AMPP_FUNCTION(S1_F_pc[13], S1L1318);

--S1L1322 is std_1c20:inst|cpu:the_cpu|F_pc_plus_one[13]~65COUT1_1000 at LC_X27_Y18_N6

--operation mode is arithmetic

S1L1322 = AMPP_FUNCTION(S1_F_pc[13], S1L1319);

--S1L1317 is std_1c20:inst|cpu:the_cpu|F_pc_plus_one[12]~66 at LC_X27_Y18_N5

--operation mode is arithmetic

S1L1317 = AMPP_FUNCTION(S1_F_pc[12], S1L1316);

--S1_D_pc_plus_one[12] is std_1c20:inst|cpu:the_cpu|D_pc_plus_one[12] at LC_X27_Y18_N5

--operation mode is arithmetic

S1_D_pc_plus_one[12] = AMPP_FUNCTION(QC2__clk0, S1_F_pc[12], F1_data_out, S1_W_stall, S1L1316);

--S1L1318 is std_1c20:inst|cpu:the_cpu|F_pc_plus_one[12]~67 at LC_X27_Y18_N5

--operation mode is arithmetic

S1L1318 = AMPP_FUNCTION(S1_F_pc[12]);

--S1L1319 is std_1c20:inst|cpu:the_cpu|F_pc_plus_one[12]~67COUT1_998 at LC_X27_Y18_N5

--operation mode is arithmetic

S1L1319 = AMPP_FUNCTION(S1_F_pc[12]);

--T1L172 is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[12]~5224 at LC_X44_Y23_N6

--operation mode is normal

T1L172 = !UB1_cpu_data_master_granted_sysid_control_slave & !JB1L3 & (!SB1L2 # !T1L171);

--T1_registered_cpu_data_master_readdata[14] is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|registered_cpu_data_master_readdata[14] at LC_X45_Y24_N4

--operation mode is normal

T1_registered_cpu_data_master_readdata[14]_lut_out = T1L484 & T1L512 & (KB1_za_data[14] # !S1L1693Q);

T1_registered_cpu_data_master_readdata[14] = DFFEAS(T1_registered_cpu_data_master_readdata[14]_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--T1L186 is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[14]~5225 at LC_X45_Y24_N6

--operation mode is normal

T1L186 = T1_registered_cpu_data_master_readdata[14] # !K1_cpu_data_master_requests_clock_0_in & (!UB1L9 # !CB1L2);

--T1L318 is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata~338 at LC_X41_Y26_N4

--operation mode is normal

T1L318 = T1L392Q & T1L391Q # !T1L392Q & (T1L393Q) # !S1L1689Q;

--T1L187 is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[14]~5226 at LC_X41_Y24_N4

--operation mode is normal

T1L187 = T1L318 & (Y1_internal_incoming_ext_ram_bus_data[14] # !Y1L146 & !Y1_cpu_data_master_requests_ext_ram_s1);

--T1L188 is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[14]~5227 at LC_X45_Y24_N2

--operation mode is normal

T1L188 = T1L187 & (T1_registered_cpu_data_master_readdata[14] # !S1L1693Q & !N1_cpu_data_master_requests_clock_1_in);

--RB1_readdata[14] is std_1c20:inst|sys_clk_timer:the_sys_clk_timer|readdata[14] at LC_X51_Y24_N5

--operation mode is normal

RB1_readdata[14]_lut_out = S1L1738Q & (!S1_M_alu_result[3] & RB1L214) # !S1L1738Q & S1_M_alu_result[3] & (RB1L215 $ !RB1L214);

RB1_readdata[14] = DFFEAS(RB1_readdata[14]_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--T1L189 is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[14]~5228 at LC_X45_Y24_N7

--operation mode is normal

T1L189 = T1L188 & T1L186 & (RB1_readdata[14] # !SB1_cpu_data_master_requests_sys_clk_timer_s1);

--Z1_readdata[14] is std_1c20:inst|high_res_timer:the_high_res_timer|readdata[14] at LC_X56_Y26_N7

--operation mode is normal

Z1_readdata[14]_lut_out = S1_M_alu_result[3] & !S1L1738Q & (Z1L211 $ !Z1L212) # !S1_M_alu_result[3] & S1L1738Q & Z1L211;

Z1_readdata[14] = DFFEAS(Z1_readdata[14]_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--S1L559Q is std_1c20:inst|cpu:the_cpu|d_readdata_d1[14]~218 at LC_X43_Y25_N5

--operation mode is normal

S1L559Q = AMPP_FUNCTION(QC2__clk0, Z1_readdata[14], AB1_cpu_data_master_requests_high_res_timer_s1, T1L172, T1L189, F1_data_out);

--DE1_data_to_cpu[14] is std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|data_to_cpu[14] at LC_X36_Y28_N8

--operation mode is normal

DE1_data_to_cpu[14]_lut_out = DE1L253 & DE1L138Q # !DE1L253 & (DE1L252 & DE1L247Q);

DE1_data_to_cpu[14] = DFFEAS(DE1_data_to_cpu[14]_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--U1L154 is std_1c20:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_readdata~2400 at LC_X42_Y24_N0

--operation mode is normal

U1L154 = W1L1 & DE1_data_to_cpu[14] # !W1L1 & (FE1_q_a[14]);

--S1L560Q is std_1c20:inst|cpu:the_cpu|d_readdata_d1[14]~219 at LC_X42_Y24_N0

--operation mode is normal

S1L560Q = AMPP_FUNCTION(QC2__clk0, DE1_data_to_cpu[14], W1L1, FE1_q_a[14], F1_data_out);

--T1L191 is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[14]~5230 at LC_X42_Y24_N8

--operation mode is normal

T1L191 = S1L559Q & (S1L560Q # !S1L539Q);

--S1L558Q is std_1c20:inst|cpu:the_cpu|d_readdata_d1[14]~125 at LC_X42_Y21_N9

--operation mode is normal

S1L558Q = AMPP_FUNCTION(QC2__clk0, S1L1756Q, S1_ic_fill_line[5], V1L6, CE1_q_a[14], F1_data_out);

--T1_registered_cpu_data_master_readdata[30] is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|registered_cpu_data_master_readdata[30] at LC_X36_Y22_N3

--operation mode is normal

T1_registered_cpu_data_master_readdata[30]_lut_out = !K1L6 & T1L498 & (!CB1L2 # !UB1L9);

T1_registered_cpu_data_master_readdata[30] = DFFEAS(T1_registered_cpu_data_master_readdata[30]_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--T1L300 is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[30]~5231 at LC_X43_Y22_N2

--operation mode is normal

T1L300 = T1_registered_cpu_data_master_readdata[30] # !K1_cpu_data_master_requests_clock_0_in & (!CB1L2 # !UB1L9);

--T1L319 is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata~354 at LC_X41_Y27_N2

--operation mode is normal

T1L319 = Y1_internal_incoming_ext_ram_bus_data[6] # !S1L1689Q;

--T1L301 is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[30]~5232 at LC_X41_Y26_N7

--operation mode is normal

T1L301 = T1L319 & (Y1_internal_incoming_ext_ram_bus_data[30] # !Y1L146 & !Y1_cpu_data_master_requests_ext_ram_s1);

--T1L302 is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[30]~5233 at LC_X43_Y22_N5

--operation mode is normal

T1L302 = T1L301 & (T1_registered_cpu_data_master_readdata[30] # !S1L1693Q & !N1_cpu_data_master_requests_clock_1_in);

--T1L303 is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[30]~5234 at LC_X43_Y22_N0

--operation mode is normal

T1L303 = T1L196 & T1L302 & T1L300 & T1L162;

--S1L638Q is std_1c20:inst|cpu:the_cpu|d_readdata_d1[30]~133 at LC_X43_Y22_N1

--operation mode is normal

S1L638Q = AMPP_FUNCTION(QC2__clk0, X1_cpu_data_master_requests_epcs_controller_epcs_control_port, W1L1, FE1_q_a[30], T1L303, F1_data_out);

--WC1L34 is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|readdata[30]~1352 at LC_X42_Y20_N6

--operation mode is normal

WC1L34 = AMPP_FUNCTION(S1L1756Q, S1_ic_fill_line[5], V1L6, CE1_q_a[30]);

--S1L639Q is std_1c20:inst|cpu:the_cpu|d_readdata_d1[30]~134 at LC_X42_Y20_N6

--operation mode is normal

S1L639Q = AMPP_FUNCTION(QC2__clk0, S1L1756Q, S1_ic_fill_line[5], V1L6, CE1_q_a[30], F1_data_out);

--S1L1315 is std_1c20:inst|cpu:the_cpu|F_pc_plus_one[11]~68 at LC_X27_Y18_N4

--operation mode is arithmetic

S1L1315 = AMPP_FUNCTION(S1_F_pc[11], S1L1302, S1L1313, S1L1314);

--S1_D_pc_plus_one[11] is std_1c20:inst|cpu:the_cpu|D_pc_plus_one[11] at LC_X27_Y18_N4

--operation mode is arithmetic

S1_D_pc_plus_one[11] = AMPP_FUNCTION(QC2__clk0, S1_F_pc[11], F1_data_out, S1_W_stall, S1L1302, S1L1313, S1L1314);

--S1L1316 is std_1c20:inst|cpu:the_cpu|F_pc_plus_one[11]~69 at LC_X27_Y18_N4

--operation mode is arithmetic

S1L1316 = AMPP_FUNCTION(S1_F_pc[11], S1L1302, S1L1313, S1L1314);

--T1L163 is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[11]~5236 at LC_X44_Y23_N5

--operation mode is normal

T1L163 = !JB1L3 & T1L322 & (!T1L171 # !SB1L2);

--T1_registered_cpu_data_master_readdata[13] is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|registered_cpu_data_master_readdata[13] at LC_X44_Y26_N6

--operation mode is normal

T1_registered_cpu_data_master_readdata[13]_lut_out = T1L511 & T1L483 & (KB1_za_data[13] # !S1L1693Q);

T1_registered_cpu_data_master_readdata[13] = DFFEAS(T1_registered_cpu_data_master_readdata[13]_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--T1L180 is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[13]~5237 at LC_X46_Y26_N0

--operation mode is normal

T1L180 = T1_registered_cpu_data_master_readdata[13] # !K1_cpu_data_master_requests_clock_0_in & (!UB1L9 # !CB1L2);

--T1L317 is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata~337 at LC_X41_Y26_N0

--operation mode is normal

T1L317 = T1L392Q & T1L386Q # !T1L392Q & (T1L387Q) # !S1L1689Q;

--T1L181 is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[13]~5238 at LC_X41_Y26_N1

--operation mode is normal

T1L181 = T1L317 & (Y1_internal_incoming_ext_ram_bus_data[13] # !Y1L146 & !Y1_cpu_data_master_requests_ext_ram_s1);

--T1L182 is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[13]~5239 at LC_X44_Y26_N8

--operation mode is normal

T1L182 = T1L181 & (T1_registered_cpu_data_master_readdata[13] # !S1L1693Q & !N1_cpu_data_master_requests_clock_1_in);

--Z1_readdata[13] is std_1c20:inst|high_res_timer:the_high_res_timer|readdata[13] at LC_X56_Y26_N6

--operation mode is normal

Z1_readdata[13]_lut_out = S1_M_alu_result[3] & !S1L1738Q & (Z1L210 $ !Z1L209) # !S1_M_alu_result[3] & S1L1738Q & (Z1L209);

Z1_readdata[13] = DFFEAS(Z1_readdata[13]_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--T1L183 is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[13]~5240 at LC_X46_Y26_N6

--operation mode is normal

T1L183 = T1L182 & T1L180 & (Z1_readdata[13] # !AB1_cpu_data_master_requests_high_res_timer_s1);

--RB1_readdata[13] is std_1c20:inst|sys_clk_timer:the_sys_clk_timer|readdata[13] at LC_X51_Y25_N9

--operation mode is normal

RB1_readdata[13]_lut_out = S1L1738Q & RB1L212 & !S1_M_alu_result[3] # !S1L1738Q & S1_M_alu_result[3] & (RB1L212 $ !RB1L213);

RB1_readdata[13] = DFFEAS(RB1_readdata[13]_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--S1L553Q is std_1c20:inst|cpu:the_cpu|d_readdata_d1[13]~216 at LC_X46_Y26_N7

--operation mode is normal

S1L553Q = AMPP_FUNCTION(QC2__clk0, SB1_cpu_data_master_requests_sys_clk_timer_s1, T1L163, RB1_readdata[13], T1L183, F1_data_out);

--DE1_data_to_cpu[13] is std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|data_to_cpu[13] at LC_X36_Y28_N0

--operation mode is normal

DE1_data_to_cpu[13]_lut_out = DE1L253 & DE1L135Q # !DE1L253 & (DE1L244Q & DE1L252);

DE1_data_to_cpu[13] = DFFEAS(DE1_data_to_cpu[13]_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--U1L155 is std_1c20:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_readdata~2401 at LC_X42_Y24_N5

--operation mode is normal

U1L155 = W1L1 & DE1_data_to_cpu[13] # !W1L1 & (FE1_q_a[13]);

--S1L554Q is std_1c20:inst|cpu:the_cpu|d_readdata_d1[13]~217 at LC_X42_Y24_N5

--operation mode is normal

S1L554Q = AMPP_FUNCTION(QC2__clk0, DE1_data_to_cpu[13], FE1_q_a[13], W1L1, F1_data_out);

--T1L185 is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[13]~5242 at LC_X42_Y24_N7

--operation mode is normal

T1L185 = S1L553Q & (S1L554Q # !S1L539Q);

--S1L552Q is std_1c20:inst|cpu:the_cpu|d_readdata_d1[13]~122 at LC_X42_Y21_N8

--operation mode is normal

S1L552Q = AMPP_FUNCTION(QC2__clk0, S1L1756Q, S1_ic_fill_line[5], V1L6, CE1_q_a[13], F1_data_out);

--T1_registered_cpu_data_master_readdata[29] is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|registered_cpu_data_master_readdata[29] at LC_X37_Y23_N1

--operation mode is normal

T1_registered_cpu_data_master_readdata[29]_lut_out = !K1L6 & T1L497 & (!UB1L9 # !CB1L2);

T1_registered_cpu_data_master_readdata[29] = DFFEAS(T1_registered_cpu_data_master_readdata[29]_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--T1L294 is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[29]~5244 at LC_X39_Y23_N1

--operation mode is normal

T1L294 = !T1L297 & !T1L299 & (T1_registered_cpu_data_master_readdata[29] # !T1L241);

--W1L15 is std_1c20:inst|epcs_controller:the_epcs_controller|readdata[29]~696 at LC_X39_Y23_N9

--operation mode is normal

W1L15 = !W1L1 & FE1_q_a[29];

--S1L633Q is std_1c20:inst|cpu:the_cpu|d_readdata_d1[29]~154 at LC_X39_Y23_N2

--operation mode is normal

S1L633Q = AMPP_FUNCTION(QC2__clk0, W1L15, X1_cpu_data_master_requests_epcs_controller_epcs_control_port, T1L211, T1L294, F1_data_out);

--WC1L33 is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|readdata[29]~1354 at LC_X42_Y20_N1

--operation mode is normal

WC1L33 = AMPP_FUNCTION(S1L1756Q, S1_ic_fill_line[5], V1L6, CE1_q_a[29]);

--S1L634Q is std_1c20:inst|cpu:the_cpu|d_readdata_d1[29]~155 at LC_X42_Y20_N1

--operation mode is normal

S1L634Q = AMPP_FUNCTION(QC2__clk0, S1L1756Q, S1_ic_fill_line[5], V1L6, CE1_q_a[29], F1_data_out);

--S1L1312 is std_1c20:inst|cpu:the_cpu|F_pc_plus_one[10]~70 at LC_X27_Y18_N3

--operation mode is arithmetic

S1L1312 = AMPP_FUNCTION(S1_F_pc[10], S1L1302, S1L1310, S1L1311);

--S1_D_pc_plus_one[10] is std_1c20:inst|cpu:the_cpu|D_pc_plus_one[10] at LC_X27_Y18_N3

--operation mode is arithmetic

S1_D_pc_plus_one[10] = AMPP_FUNCTION(QC2__clk0, S1_F_pc[10], F1_data_out, S1_W_stall, S1L1302, S1L1310, S1L1311);

--S1L1313 is std_1c20:inst|cpu:the_cpu|F_pc_plus_one[10]~71 at LC_X27_Y18_N3

--operation mode is arithmetic

S1L1313 = AMPP_FUNCTION(S1_F_pc[10], S1L1310);

--S1L1314 is std_1c20:inst|cpu:the_cpu|F_pc_plus_one[10]~71COUT1_996 at LC_X27_Y18_N3

--operation mode is arithmetic

S1L1314 = AMPP_FUNCTION(S1_F_pc[10], S1L1311);

--S1L122 is std_1c20:inst|cpu:the_cpu|Add1~279 at LC_X28_Y18_N3

--operation mode is arithmetic

S1L122 = AMPP_FUNCTION(S1_D_br_taken_waddr_partial[10]);

--S1L123 is std_1c20:inst|cpu:the_cpu|Add1~279COUT1_821 at LC_X28_Y18_N3

--operation mode is arithmetic

S1L123 = AMPP_FUNCTION(S1_D_br_taken_waddr_partial[10]);

--T1_registered_cpu_data_master_readdata[12] is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|registered_cpu_data_master_readdata[12] at LC_X41_Y25_N5

--operation mode is normal

T1_registered_cpu_data_master_readdata[12]_lut_out = T1L510 & T1L482 & (KB1_za_data[12] # !S1L1693Q);

T1_registered_cpu_data_master_readdata[12] = DFFEAS(T1_registered_cpu_data_master_readdata[12]_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--T1L173 is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[12]~5246 at LC_X42_Y26_N3

--operation mode is normal

T1L173 = T1_registered_cpu_data_master_readdata[12] # !K1_cpu_data_master_requests_clock_0_in & (!CB1L2 # !UB1L9);

--T1L316 is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata~336 at LC_X39_Y26_N6

--operation mode is normal

T1L316 = T1L392Q & (T1L381Q) # !T1L392Q & T1L382Q # !S1L1689Q;

--T1L174 is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[12]~5247 at LC_X39_Y26_N9

--operation mode is normal

T1L174 = T1L316 & (Y1_internal_incoming_ext_ram_bus_data[12] # !Y1_cpu_data_master_requests_ext_ram_s1 & !Y1L146);

--T1L175 is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[12]~5248 at LC_X42_Y26_N6

--operation mode is normal

T1L175 = T1L174 & (T1_registered_cpu_data_master_readdata[12] # !S1L1693Q & !N1_cpu_data_master_requests_clock_1_in);

--Z1_readdata[12] is std_1c20:inst|high_res_timer:the_high_res_timer|readdata[12] at LC_X56_Y26_N9

--operation mode is normal

Z1_readdata[12]_lut_out = S1_M_alu_result[3] & !S1L1738Q & (Z1L208 $ !Z1L207) # !S1_M_alu_result[3] & S1L1738Q & (Z1L207);

Z1_readdata[12] = DFFEAS(Z1_readdata[12]_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--T1L176 is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[12]~5249 at LC_X47_Y26_N7

--operation mode is normal

T1L176 = T1L175 & T1L173 & (Z1_readdata[12] # !AB1_cpu_data_master_requests_high_res_timer_s1);

--RB1_readdata[12] is std_1c20:inst|sys_clk_timer:the_sys_clk_timer|readdata[12] at LC_X47_Y26_N5

--operation mode is normal

RB1_readdata[12]_lut_out = S1L1738Q & (!S1_M_alu_result[3] & RB1L210) # !S1L1738Q & S1_M_alu_result[3] & (RB1L211 $ !RB1L210);

RB1_readdata[12] = DFFEAS(RB1_readdata[12]_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--S1L547Q is std_1c20:inst|cpu:the_cpu|d_readdata_d1[12]~214 at LC_X47_Y26_N0

--operation mode is normal

S1L547Q = AMPP_FUNCTION(QC2__clk0, SB1_cpu_data_master_requests_sys_clk_timer_s1, RB1_readdata[12], T1L176, T1L172, F1_data_out);

--DE1_data_to_cpu[12] is std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|data_to_cpu[12] at LC_X38_Y27_N6

--operation mode is normal

DE1_data_to_cpu[12]_lut_out = DE1L47 & DE1L133Q # !DE1L47 & (DE1L241Q & DE1L74);

DE1_data_to_cpu[12] = DFFEAS(DE1_data_to_cpu[12]_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--U1L156 is std_1c20:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_readdata~2402 at LC_X40_Y26_N0

--operation mode is normal

U1L156 = W1L1 & (DE1_data_to_cpu[12]) # !W1L1 & FE1_q_a[12];

--S1L548Q is std_1c20:inst|cpu:the_cpu|d_readdata_d1[12]~215 at LC_X40_Y26_N0

--operation mode is normal

S1L548Q = AMPP_FUNCTION(QC2__clk0, FE1_q_a[12], DE1_data_to_cpu[12], W1L1, F1_data_out);

--T1L178 is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[12]~5251 at LC_X42_Y24_N6

--operation mode is normal

T1L178 = S1L547Q & (S1L548Q # !S1L539Q);

--S1L546Q is std_1c20:inst|cpu:the_cpu|d_readdata_d1[12]~119 at LC_X43_Y21_N4

--operation mode is normal

S1L546Q = AMPP_FUNCTION(QC2__clk0, S1L1756Q, S1_ic_fill_line[5], V1L6, CE1_q_a[12], F1_data_out);

--T1_registered_cpu_data_master_readdata[28] is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|registered_cpu_data_master_readdata[28] at LC_X40_Y22_N1

--operation mode is normal

T1_registered_cpu_data_master_readdata[28]_lut_out = !K1L6 & T1L496 & (!UB1L9 # !CB1L2);

T1_registered_cpu_data_master_readdata[28] = DFFEAS(T1_registered_cpu_data_master_readdata[28]_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--T1L287 is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[28]~5253 at LC_X39_Y23_N3

--operation mode is normal

T1L287 = !T1L290 & !T1L292 & (T1_registered_cpu_data_master_readdata[28] # !T1L241);

--W1L14 is std_1c20:inst|epcs_controller:the_epcs_controller|readdata[28]~697 at LC_X39_Y23_N0

--operation mode is normal

W1L14 = !W1L1 & FE1_q_a[28];

--S1L628Q is std_1c20:inst|cpu:the_cpu|d_readdata_d1[28]~151 at LC_X39_Y23_N4

--operation mode is normal

S1L628Q = AMPP_FUNCTION(QC2__clk0, X1_cpu_data_master_requests_epcs_controller_epcs_control_port, W1L14, T1L211, T1L287, F1_data_out);

--WC1L32 is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|readdata[28]~1356 at LC_X38_Y19_N2

--operation mode is normal

WC1L32 = AMPP_FUNCTION(V1L6, S1L1756Q, S1_ic_fill_line[5], CE1_q_a[28]);

--S1L629Q is std_1c20:inst|cpu:the_cpu|d_readdata_d1[28]~152 at LC_X38_Y19_N2

--operation mode is normal

S1L629Q = AMPP_FUNCTION(QC2__clk0, V1L6, S1L1756Q, S1_ic_fill_line[5], CE1_q_a[28], F1_data_out);

--S1L1326 is std_1c20:inst|cpu:the_cpu|F_pc_plus_one[15]~72 at LC_X27_Y18_N8

--operation mode is arithmetic

S1L1326 = AMPP_FUNCTION(S1_F_pc[15], S1L1316, S1L1324, S1L1325);

--S1_D_pc_plus_one[15] is std_1c20:inst|cpu:the_cpu|D_pc_plus_one[15] at LC_X27_Y18_N8

--operation mode is arithmetic

S1_D_pc_plus_one[15] = AMPP_FUNCTION(QC2__clk0, S1_F_pc[15], F1_data_out, S1_W_stall, S1L1316, S1L1324, S1L1325);

--S1L1327 is std_1c20:inst|cpu:the_cpu|F_pc_plus_one[15]~73 at LC_X27_Y18_N8

--operation mode is arithmetic

S1L1327 = AMPP_FUNCTION(S1_F_pc[15], S1L1324);

--S1L1328 is std_1c20:inst|cpu:the_cpu|F_pc_plus_one[15]~73COUT1_1004 at LC_X27_Y18_N8

--operation mode is arithmetic

S1L1328 = AMPP_FUNCTION(S1_F_pc[15], S1L1325);

--T1_registered_cpu_data_master_readdata[17] is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|registered_cpu_data_master_readdata[17] at LC_X43_Y22_N8

--operation mode is normal

T1_registered_cpu_data_master_readdata[17]_lut_out = !K1L6 & BB1L46 & (KB1_za_data[17] # !S1L1693Q);

T1_registered_cpu_data_master_readdata[17] = DFFEAS(T1_registered_cpu_data_master_readdata[17]_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--T1L205 is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[17]~5256 at LC_X41_Y24_N9

--operation mode is normal

T1L205 = !T1L210 & !T1L208 & (T1_registered_cpu_data_master_readdata[17] # !T1L241);

--W1L3 is std_1c20:inst|epcs_controller:the_epcs_controller|readdata[17]~698 at LC_X41_Y21_N2

--operation mode is normal

W1L3 = !W1L1 & (FE1_q_a[17]);

--S1L573Q is std_1c20:inst|cpu:the_cpu|d_readdata_d1[17]~148 at LC_X41_Y21_N3

--operation mode is normal

S1L573Q = AMPP_FUNCTION(QC2__clk0, W1L3, X1_cpu_data_master_requests_epcs_controller_epcs_control_port, T1L205, T1L249, F1_data_out);

--WC1L20 is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|readdata[17]~1357 at LC_X41_Y21_N5

--operation mode is normal

WC1L20 = AMPP_FUNCTION(S1L1756Q, V1L6, CE1_q_a[17], S1_ic_fill_line[5]);

--S1L574Q is std_1c20:inst|cpu:the_cpu|d_readdata_d1[17]~149 at LC_X41_Y21_N5

--operation mode is normal

S1L574Q = AMPP_FUNCTION(QC2__clk0, S1L1756Q, V1L6, CE1_q_a[17], S1_ic_fill_line[5], F1_data_out);

--S1L1348 is std_1c20:inst|cpu:the_cpu|F_pc_plus_one[23]~74 at LC_X27_Y17_N6

--operation mode is normal

S1L1348 = AMPP_FUNCTION(S1_F_pc[23], S1L1344, S1L1346, S1L1347);

--S1_D_pc_plus_one[23] is std_1c20:inst|cpu:the_cpu|D_pc_plus_one[23] at LC_X27_Y17_N6

--operation mode is normal

S1_D_pc_plus_one[23] = AMPP_FUNCTION(QC2__clk0, S1_F_pc[23], F1_data_out, S1_W_stall, S1L1344, S1L1346, S1L1347);

--S1_M_shift_rot_result[27] is std_1c20:inst|cpu:the_cpu|M_shift_rot_result[27] at LC_X40_Y12_N9

--operation mode is normal

S1_M_shift_rot_result[27] = AMPP_FUNCTION(QC2__clk0, S1_M_shift_rot_result[28], S1_M_shift_rot_result[26], S1L880, S1_M_ctrl_shift_rot_right, F1_data_out, !S1_M_shift_rot_stall);

--S1_E_src1_prelim[26] is std_1c20:inst|cpu:the_cpu|E_src1_prelim[26] at LC_X44_Y13_N3

--operation mode is normal

S1_E_src1_prelim[26] = AMPP_FUNCTION(QC2__clk0, S1_W_wr_data[26], S1_D_src1_hazard_W, S1L2470, CD1_q_b[26], F1_data_out, S1_D_src1_hazard_M, S1_W_stall);

--S1L2468 is std_1c20:inst|cpu:the_cpu|M_wr_data_unfiltered[26]~3697 at LC_X44_Y13_N2

--operation mode is normal

S1L2468 = AMPP_FUNCTION(S1L2062Q, S1_M_shift_rot_result[26]);

--S1L213 is std_1c20:inst|cpu:the_cpu|av_ld_data_aligned_or_div[26]~76 at LC_X41_Y19_N8

--operation mode is normal

S1L213 = AMPP_FUNCTION(S1L617, S1_M_ctrl_ld_signed, S1_M_iw[4], S1L239);

--S1_av_ld_data_aligned_or_div[26] is std_1c20:inst|cpu:the_cpu|av_ld_data_aligned_or_div[26] at LC_X41_Y19_N8

--operation mode is normal

S1_av_ld_data_aligned_or_div[26] = AMPP_FUNCTION(QC2__clk0, S1L617, S1_M_ctrl_ld_signed, S1_M_iw[4], S1L239, F1_data_out);

--S1L214Q is std_1c20:inst|cpu:the_cpu|av_ld_data_aligned_or_div[26]~77 at LC_X41_Y12_N5

--operation mode is normal

S1L214Q = AMPP_FUNCTION(QC2__clk0, S1_av_ld_aligning_data, S1L2057, S1L1892, S1L213, F1_data_out);

--S1L879 is std_1c20:inst|cpu:the_cpu|E_src1[26]~2041 at LC_X44_Y13_N4

--operation mode is normal

S1L879 = AMPP_FUNCTION(S1L886Q, S1L214Q, S1L2468, S1_E_src1_prelim[26]);

--T1_registered_cpu_data_master_readdata[25] is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|registered_cpu_data_master_readdata[25] at LC_X39_Y24_N3

--operation mode is normal

T1_registered_cpu_data_master_readdata[25]_lut_out = !K1L6 & T1L493 & (!UB1L9 # !CB1L2);

T1_registered_cpu_data_master_readdata[25] = DFFEAS(T1_registered_cpu_data_master_readdata[25]_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--T1L265 is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[25]~5259 at LC_X39_Y24_N8

--operation mode is normal

T1L265 = !T1L270 & !T1L268 & (T1_registered_cpu_data_master_readdata[25] # !T1L241);

--W1L11 is std_1c20:inst|epcs_controller:the_epcs_controller|readdata[25]~699 at LC_X43_Y21_N0

--operation mode is normal

W1L11 = !W1L1 & FE1_q_a[25];

--S1L613Q is std_1c20:inst|cpu:the_cpu|d_readdata_d1[25]~145 at LC_X43_Y21_N1

--operation mode is normal

S1L613Q = AMPP_FUNCTION(QC2__clk0, X1_cpu_data_master_requests_epcs_controller_epcs_control_port, W1L11, T1L249, T1L265, F1_data_out);

--WC1L29 is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|readdata[25]~1358 at LC_X43_Y21_N9

--operation mode is normal

WC1L29 = AMPP_FUNCTION(S1L1756Q, S1_ic_fill_line[5], V1L6, CE1_q_a[25]);

--S1L614Q is std_1c20:inst|cpu:the_cpu|d_readdata_d1[25]~146 at LC_X43_Y21_N9

--operation mode is normal

S1L614Q = AMPP_FUNCTION(QC2__clk0, S1L1756Q, S1_ic_fill_line[5], V1L6, CE1_q_a[25], F1_data_out);

--S1L1334 is std_1c20:inst|cpu:the_cpu|F_pc_plus_one[18]~76 at LC_X27_Y17_N1

--operation mode is arithmetic

S1L1334 = AMPP_FUNCTION(S1_F_pc[18], S1L1330, S1L1332, S1L1333);

--S1_D_pc_plus_one[18] is std_1c20:inst|cpu:the_cpu|D_pc_plus_one[18] at LC_X27_Y17_N1

--operation mode is arithmetic

S1_D_pc_plus_one[18] = AMPP_FUNCTION(QC2__clk0, S1_F_pc[18], F1_data_out, S1_W_stall, S1L1330, S1L1332, S1L1333);

--S1L1335 is std_1c20:inst|cpu:the_cpu|F_pc_plus_one[18]~77 at LC_X27_Y17_N1

--operation mode is arithmetic

S1L1335 = AMPP_FUNCTION(S1_F_pc[18], S1L1332);

--S1L1336 is std_1c20:inst|cpu:the_cpu|F_pc_plus_one[18]~77COUT1_1008 at LC_X27_Y17_N1

--operation mode is arithmetic

S1L1336 = AMPP_FUNCTION(S1_F_pc[18], S1L1333);

--T1_registered_cpu_data_master_readdata[20] is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|registered_cpu_data_master_readdata[20] at LC_X40_Y22_N5

--operation mode is normal

T1_registered_cpu_data_master_readdata[20]_lut_out = T1L488 & !K1L6 & (BB1L51 # !CB1_cpu_data_master_requests_jtag_uart_avalon_jtag_slave);

T1_registered_cpu_data_master_readdata[20] = DFFEAS(T1_registered_cpu_data_master_readdata[20]_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--T1L228 is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[20]~5262 at LC_X40_Y22_N2

--operation mode is normal

T1L228 = !T1L231 & !T1L233 & (T1_registered_cpu_data_master_readdata[20] # !T1L241);

--W1L6 is std_1c20:inst|epcs_controller:the_epcs_controller|readdata[20]~700 at LC_X39_Y21_N4

--operation mode is normal

W1L6 = !W1L1 & FE1_q_a[20];

--S1L588Q is std_1c20:inst|cpu:the_cpu|d_readdata_d1[20]~142 at LC_X41_Y22_N0

--operation mode is normal

S1L588Q = AMPP_FUNCTION(QC2__clk0, W1L6, T1L228, X1_cpu_data_master_requests_epcs_controller_epcs_control_port, T1L249, F1_data_out);

--WC1L24 is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|readdata[20]~1359 at LC_X42_Y21_N4

--operation mode is normal

WC1L24 = AMPP_FUNCTION(S1L1756Q, S1_ic_fill_line[5], V1L6, CE1_q_a[20]);

--S1L589Q is std_1c20:inst|cpu:the_cpu|d_readdata_d1[20]~143 at LC_X42_Y21_N4

--operation mode is normal

S1L589Q = AMPP_FUNCTION(QC2__clk0, S1L1756Q, S1_ic_fill_line[5], V1L6, CE1_q_a[20], F1_data_out);

--S1L1343 is std_1c20:inst|cpu:the_cpu|F_pc_plus_one[21]~78 at LC_X27_Y17_N4

--operation mode is arithmetic

S1L1343 = AMPP_FUNCTION(S1_F_pc[21], S1L1330, S1L1341, S1L1342);

--S1_D_pc_plus_one[21] is std_1c20:inst|cpu:the_cpu|D_pc_plus_one[21] at LC_X27_Y17_N4

--operation mode is arithmetic

S1_D_pc_plus_one[21] = AMPP_FUNCTION(QC2__clk0, S1_F_pc[21], F1_data_out, S1_W_stall, S1L1330, S1L1341, S1L1342);

--S1L1344 is std_1c20:inst|cpu:the_cpu|F_pc_plus_one[21]~79 at LC_X27_Y17_N4

--operation mode is arithmetic

S1L1344 = AMPP_FUNCTION(S1_F_pc[21], S1L1330, S1L1341, S1L1342);

--S1L1309 is std_1c20:inst|cpu:the_cpu|F_pc_plus_one[9]~80 at LC_X27_Y18_N2

--operation mode is arithmetic

S1L1309 = AMPP_FUNCTION(S1_F_pc[9], S1L1302, S1L1307, S1L1308);

--S1_D_pc_plus_one[9] is std_1c20:inst|cpu:the_cpu|D_pc_plus_one[9] at LC_X27_Y18_N2

--operation mode is arithmetic

S1_D_pc_plus_one[9] = AMPP_FUNCTION(QC2__clk0, S1_F_pc[9], F1_data_out, S1_W_stall, S1L1302, S1L1307, S1L1308);

--S1L1310 is std_1c20:inst|cpu:the_cpu|F_pc_plus_one[9]~81 at LC_X27_Y18_N2

--operation mode is arithmetic

S1L1310 = AMPP_FUNCTION(S1_F_pc[9], S1L1307);

--S1L1311 is std_1c20:inst|cpu:the_cpu|F_pc_plus_one[9]~81COUT1_994 at LC_X27_Y18_N2

--operation mode is arithmetic

S1L1311 = AMPP_FUNCTION(S1_F_pc[9], S1L1308);

--T1_registered_cpu_data_master_readdata[11] is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|registered_cpu_data_master_readdata[11] at LC_X41_Y25_N4

--operation mode is normal

T1_registered_cpu_data_master_readdata[11]_lut_out = T1L481 & !CB1_cpu_data_master_requests_jtag_uart_avalon_jtag_slave & (M1_slave_readdata[11] # !N1_cpu_data_master_requests_clock_1_in);

T1_registered_cpu_data_master_readdata[11] = DFFEAS(T1_registered_cpu_data_master_readdata[11]_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--T1L164 is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[11]~5264 at LC_X45_Y26_N5

--operation mode is normal

T1L164 = T1_registered_cpu_data_master_readdata[11] # !K1_cpu_data_master_requests_clock_0_in & (!UB1L9 # !CB1L2);

--T1L315 is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata~335 at LC_X39_Y26_N7

--operation mode is normal

T1L315 = T1L392Q & T1L376Q # !T1L392Q & (T1L377Q) # !S1L1689Q;

--T1L165 is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[11]~5265 at LC_X39_Y26_N2

--operation mode is normal

T1L165 = T1L315 & (Y1_internal_incoming_ext_ram_bus_data[11] # !Y1_cpu_data_master_requests_ext_ram_s1 & !Y1L146);

--T1L166 is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[11]~5266 at LC_X44_Y26_N0

--operation mode is normal

T1L166 = T1L165 & (T1_registered_cpu_data_master_readdata[11] # !N1_cpu_data_master_requests_clock_1_in & !S1L1693Q);

--Z1_readdata[11] is std_1c20:inst|high_res_timer:the_high_res_timer|readdata[11] at LC_X56_Y26_N4

--operation mode is normal

Z1_readdata[11]_lut_out = S1_M_alu_result[3] & !S1L1738Q & (Z1L205 $ !Z1L206) # !S1_M_alu_result[3] & S1L1738Q & Z1L205;

Z1_readdata[11] = DFFEAS(Z1_readdata[11]_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--T1L167 is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[11]~5267 at LC_X47_Y26_N1

--operation mode is normal

T1L167 = T1L166 & T1L164 & (Z1_readdata[11] # !AB1_cpu_data_master_requests_high_res_timer_s1);

--RB1_readdata[11] is std_1c20:inst|sys_clk_timer:the_sys_clk_timer|readdata[11] at LC_X48_Y26_N9

--operation mode is normal

RB1_readdata[11]_lut_out = S1_M_alu_result[3] & !S1L1738Q & (RB1L208 $ !RB1L209) # !S1_M_alu_result[3] & S1L1738Q & RB1L208;

RB1_readdata[11] = DFFEAS(RB1_readdata[11]_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--S1L541Q is std_1c20:inst|cpu:the_cpu|d_readdata_d1[11]~212 at LC_X47_Y26_N3

--operation mode is normal

S1L541Q = AMPP_FUNCTION(QC2__clk0, SB1_cpu_data_master_requests_sys_clk_timer_s1, RB1_readdata[11], T1L163, T1L167, F1_data_out);

--DE1_data_to_cpu[11] is std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|data_to_cpu[11] at LC_X36_Y29_N4

--operation mode is normal

DE1_data_to_cpu[11]_lut_out = DE1L253 & DE1L130Q # !DE1L253 & (DE1L238Q & DE1L252);

DE1_data_to_cpu[11] = DFFEAS(DE1_data_to_cpu[11]_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--U1L157 is std_1c20:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_readdata~2403 at LC_X38_Y22_N3

--operation mode is normal

U1L157 = W1L1 & DE1_data_to_cpu[11] # !W1L1 & (FE1_q_a[11]);

--S1L542Q is std_1c20:inst|cpu:the_cpu|d_readdata_d1[11]~213 at LC_X38_Y22_N3

--operation mode is normal

S1L542Q = AMPP_FUNCTION(QC2__clk0, DE1_data_to_cpu[11], W1L1, FE1_q_a[11], F1_data_out);

--T1L169 is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[11]~5269 at LC_X38_Y22_N0

--operation mode is normal

T1L169 = S1L541Q & (S1L542Q # !S1L539Q);

--S1L538Q is std_1c20:inst|cpu:the_cpu|d_readdata_d1[11]~116 at LC_X43_Y19_N8

--operation mode is normal

S1L538Q = AMPP_FUNCTION(QC2__clk0, S1_ic_fill_line[5], S1L1756Q, V1L6, CE1_q_a[11], F1_data_out);

--T1_registered_cpu_data_master_readdata[27] is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|registered_cpu_data_master_readdata[27] at LC_X39_Y25_N3

--operation mode is normal

T1_registered_cpu_data_master_readdata[27]_lut_out = !K1L6 & T1L495 & (!UB1L9 # !CB1L2);

T1_registered_cpu_data_master_readdata[27] = DFFEAS(T1_registered_cpu_data_master_readdata[27]_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--T1L280 is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[27]~5271 at LC_X39_Y25_N1

--operation mode is normal

T1L280 = !T1L283 & !T1L285 & (T1_registered_cpu_data_master_readdata[27] # !T1L241);

--W1L13 is std_1c20:inst|epcs_controller:the_epcs_controller|readdata[27]~701 at LC_X40_Y21_N5

--operation mode is normal

W1L13 = !W1L1 & (FE1_q_a[27]);

--S1L623Q is std_1c20:inst|cpu:the_cpu|d_readdata_d1[27]~139 at LC_X40_Y21_N4

--operation mode is normal

S1L623Q = AMPP_FUNCTION(QC2__clk0, T1L280, W1L13, X1_cpu_data_master_requests_epcs_controller_epcs_control_port, T1L249, F1_data_out);

--WC1L31 is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|readdata[27]~1361 at LC_X39_Y21_N2

--operation mode is normal

WC1L31 = AMPP_FUNCTION(S1L1756Q, V1L6, S1_ic_fill_line[5], CE1_q_a[27]);

--S1L624Q is std_1c20:inst|cpu:the_cpu|d_readdata_d1[27]~140 at LC_X39_Y21_N2

--operation mode is normal

S1L624Q = AMPP_FUNCTION(QC2__clk0, S1L1756Q, V1L6, S1_ic_fill_line[5], CE1_q_a[27], F1_data_out);

--S1L1306 is std_1c20:inst|cpu:the_cpu|F_pc_plus_one[8]~82 at LC_X27_Y18_N1

--operation mode is arithmetic

S1L1306 = AMPP_FUNCTION(S1_F_pc[8], S1L1302, S1L1304, S1L1305);

--S1_D_pc_plus_one[8] is std_1c20:inst|cpu:the_cpu|D_pc_plus_one[8] at LC_X27_Y18_N1

--operation mode is arithmetic

S1_D_pc_plus_one[8] = AMPP_FUNCTION(QC2__clk0, S1_F_pc[8], F1_data_out, S1_W_stall, S1L1302, S1L1304, S1L1305);

--S1L1307 is std_1c20:inst|cpu:the_cpu|F_pc_plus_one[8]~83 at LC_X27_Y18_N1

--operation mode is arithmetic

S1L1307 = AMPP_FUNCTION(S1_F_pc[8], S1L1304);

--S1L1308 is std_1c20:inst|cpu:the_cpu|F_pc_plus_one[8]~83COUT1_992 at LC_X27_Y18_N1

--operation mode is arithmetic

S1L1308 = AMPP_FUNCTION(S1_F_pc[8], S1L1305);

--DE1_data_to_cpu[10] is std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|data_to_cpu[10] at LC_X36_Y27_N4

--operation mode is normal

DE1_data_to_cpu[10]_lut_out = DE1L47 & DE1L127Q # !DE1L47 & (DE1L7);

DE1_data_to_cpu[10] = DFFEAS(DE1_data_to_cpu[10]_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , DE1_SSO_reg, , , DE1L255);

--T1L313 is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata~206 at LC_X45_Y23_N0

--operation mode is normal

T1L313 = W1L1 & DE1_data_to_cpu[10] # !W1L1 & (FE1_q_a[10]) # !X1_cpu_data_master_requests_epcs_controller_epcs_control_port;

--Z1_readdata[10] is std_1c20:inst|high_res_timer:the_high_res_timer|readdata[10] at LC_X56_Y26_N2

--operation mode is normal

Z1_readdata[10]_lut_out = S1_M_alu_result[3] & !S1L1738Q & (Z1L203 $ !Z1L204) # !S1_M_alu_result[3] & S1L1738Q & Z1L203;

Z1_readdata[10] = DFFEAS(Z1_readdata[10]_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--RB1_readdata[10] is std_1c20:inst|sys_clk_timer:the_sys_clk_timer|readdata[10] at LC_X48_Y26_N7

--operation mode is normal

RB1_readdata[10]_lut_out = S1L1738Q & RB1L206 & !S1_M_alu_result[3] # !S1L1738Q & S1_M_alu_result[3] & (RB1L206 $ !RB1L207);

RB1_readdata[10] = DFFEAS(RB1_readdata[10]_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--T1L156 is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[10]~5273 at LC_X48_Y26_N3

--operation mode is normal

T1L156 = RB1_readdata[10] & (Z1_readdata[10] # !AB1_cpu_data_master_requests_high_res_timer_s1) # !RB1_readdata[10] & !SB1_cpu_data_master_requests_sys_clk_timer_s1 & (Z1_readdata[10] # !AB1_cpu_data_master_requests_high_res_timer_s1);

--T1_registered_cpu_data_master_readdata[10] is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|registered_cpu_data_master_readdata[10] at LC_X44_Y22_N0

--operation mode is normal

T1_registered_cpu_data_master_readdata[10]_lut_out = T1L509 & T1L480 & (KB1_za_data[10] # !S1L1693Q);

T1_registered_cpu_data_master_readdata[10] = DFFEAS(T1_registered_cpu_data_master_readdata[10]_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--T1L157 is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[10]~5274 at LC_X44_Y22_N7

--operation mode is normal

T1L157 = T1_registered_cpu_data_master_readdata[10] # !K1_cpu_data_master_requests_clock_0_in & (!UB1L9 # !CB1L2);

--T1L158 is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[10]~5275 at LC_X41_Y24_N1

--operation mode is normal

T1L158 = T1L321 & (Y1_internal_incoming_ext_ram_bus_data[10] # !Y1_cpu_data_master_requests_ext_ram_s1 & !Y1L146);

--T1L159 is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[10]~5276 at LC_X44_Y22_N3

--operation mode is normal

T1L159 = T1L158 & (T1_registered_cpu_data_master_readdata[10] # !S1L1693Q & !N1_cpu_data_master_requests_clock_1_in);

--T1L160 is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[10]~5277 at LC_X44_Y22_N4

--operation mode is normal

T1L160 = T1L157 & T1L159 & (T1L370 # !S1L1689Q);

--S1L534Q is std_1c20:inst|cpu:the_cpu|d_readdata_d1[10]~129 at LC_X44_Y22_N5

--operation mode is normal

S1L534Q = AMPP_FUNCTION(QC2__clk0, T1L162, T1L313, T1L156, T1L160, F1_data_out);

--S1L1448Q is std_1c20:inst|cpu:the_cpu|i_readdata_d1[10]~140 at LC_X43_Y19_N1

--operation mode is normal

S1L1448Q = AMPP_FUNCTION(QC2__clk0, S1_ic_fill_line[5], S1L1756Q, V1L6, CE1_q_a[10], F1_data_out);

--T1_registered_cpu_data_master_readdata[26] is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|registered_cpu_data_master_readdata[26] at LC_X37_Y23_N0

--operation mode is normal

T1_registered_cpu_data_master_readdata[26]_lut_out = !K1L6 & T1L494 & (!UB1L9 # !CB1L2);

T1_registered_cpu_data_master_readdata[26] = DFFEAS(T1_registered_cpu_data_master_readdata[26]_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--T1L273 is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[26]~5280 at LC_X41_Y24_N3

--operation mode is normal

T1L273 = !T1L278 & !T1L276 & (T1_registered_cpu_data_master_readdata[26] # !T1L241);

--W1L12 is std_1c20:inst|epcs_controller:the_epcs_controller|readdata[26]~702 at LC_X42_Y24_N4

--operation mode is normal

W1L12 = FE1_q_a[26] & !W1L1;

--S1L618Q is std_1c20:inst|cpu:the_cpu|d_readdata_d1[26]~136 at LC_X42_Y23_N7

--operation mode is normal

S1L618Q = AMPP_FUNCTION(QC2__clk0, X1_cpu_data_master_requests_epcs_controller_epcs_control_port, T1L271, T1L273, W1L12, F1_data_out);

--WC1L30 is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|readdata[26]~1363 at LC_X43_Y21_N7

--operation mode is normal

WC1L30 = AMPP_FUNCTION(S1L1756Q, S1_ic_fill_line[5], V1L6, CE1_q_a[26]);

--S1L619Q is std_1c20:inst|cpu:the_cpu|d_readdata_d1[26]~137 at LC_X43_Y21_N7

--operation mode is normal

S1L619Q = AMPP_FUNCTION(QC2__clk0, S1L1756Q, S1_ic_fill_line[5], V1L6, CE1_q_a[26], F1_data_out);

--S1L1303 is std_1c20:inst|cpu:the_cpu|F_pc_plus_one[7]~84 at LC_X27_Y18_N0

--operation mode is arithmetic

S1L1303 = AMPP_FUNCTION(S1_F_pc[7], S1L1302);

--S1_D_pc_plus_one[7] is std_1c20:inst|cpu:the_cpu|D_pc_plus_one[7] at LC_X27_Y18_N0

--operation mode is arithmetic

S1_D_pc_plus_one[7] = AMPP_FUNCTION(QC2__clk0, S1_F_pc[7], F1_data_out, S1_W_stall, S1L1302);

--S1L1304 is std_1c20:inst|cpu:the_cpu|F_pc_plus_one[7]~85 at LC_X27_Y18_N0

--operation mode is arithmetic

S1L1304 = AMPP_FUNCTION(S1_F_pc[7]);

--S1L1305 is std_1c20:inst|cpu:the_cpu|F_pc_plus_one[7]~85COUT1_990 at LC_X27_Y18_N0

--operation mode is arithmetic

S1L1305 = AMPP_FUNCTION(S1_F_pc[7]);

--DE1_data_to_cpu[9] is std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|data_to_cpu[9] at LC_X37_Y26_N4

--operation mode is normal

DE1_data_to_cpu[9]_lut_out = DE1L255 & DE1_iEOP_reg # !DE1L255 & (DE1L8);

DE1_data_to_cpu[9] = DFFEAS(DE1_data_to_cpu[9]_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , DE1L157, , , DE1L256);

--T1L312 is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata~205 at LC_X40_Y26_N8

--operation mode is normal

T1L312 = W1L1 & DE1_data_to_cpu[9] # !W1L1 & (FE1_q_a[9]) # !X1_cpu_data_master_requests_epcs_controller_epcs_control_port;

--XE1_readdata[9] is std_1c20:inst|uart1:the_uart1|uart1_regs:the_uart1_regs|readdata[9] at LC_X47_Y23_N9

--operation mode is normal

XE1_readdata[9]_lut_out = S1L1726Q & S1_M_alu_result[3] & !S1L1738Q & XE1_control_reg[9];

XE1_readdata[9] = DFFEAS(XE1_readdata[9]_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--T1L151 is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[9]~5282 at LC_X42_Y23_N2

--operation mode is normal

T1L151 = T1L150 & (XE1_readdata[9] # !WB1_cpu_data_master_granted_uart1_s1);

--Z1_readdata[9] is std_1c20:inst|high_res_timer:the_high_res_timer|readdata[9] at LC_X56_Y26_N3

--operation mode is normal

Z1_readdata[9]_lut_out = S1_M_alu_result[3] & !S1L1738Q & (Z1L201 $ !Z1L202) # !S1_M_alu_result[3] & S1L1738Q & Z1L201;

Z1_readdata[9] = DFFEAS(Z1_readdata[9]_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--RB1_readdata[9] is std_1c20:inst|sys_clk_timer:the_sys_clk_timer|readdata[9] at LC_X51_Y25_N6

--operation mode is normal

RB1_readdata[9]_lut_out = S1_M_alu_result[3] & !S1L1738Q & (RB1L204 $ !RB1L205) # !S1_M_alu_result[3] & S1L1738Q & RB1L204;

RB1_readdata[9] = DFFEAS(RB1_readdata[9]_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--T1L152 is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[9]~5283 at LC_X48_Y26_N8

--operation mode is normal

T1L152 = Z1_readdata[9] & (RB1_readdata[9] # !SB1_cpu_data_master_requests_sys_clk_timer_s1) # !Z1_readdata[9] & !AB1_cpu_data_master_requests_high_res_timer_s1 & (RB1_readdata[9] # !SB1_cpu_data_master_requests_sys_clk_timer_s1);

--T1_registered_cpu_data_master_readdata[9] is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|registered_cpu_data_master_readdata[9] at LC_X44_Y27_N7

--operation mode is normal

T1_registered_cpu_data_master_readdata[9]_lut_out = T1L508 & T1L479 & (KB1_za_data[9] # !S1L1693Q);

T1_registered_cpu_data_master_readdata[9] = DFFEAS(T1_registered_cpu_data_master_readdata[9]_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--T1L153 is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[9]~5284 at LC_X40_Y25_N0

--operation mode is normal

T1L153 = T1L365 & !T1_registered_cpu_data_master_readdata[9] & (T1L241) # !T1L365 & (S1L1689Q # !T1_registered_cpu_data_master_readdata[9] & T1L241);

--T1L154 is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[9]~5285 at LC_X40_Y25_N6

--operation mode is normal

T1L154 = !T1L153 & (Y1_internal_incoming_ext_ram_bus_data[9] # !Y1L146 & !Y1_cpu_data_master_requests_ext_ram_s1);

--S1L530Q is std_1c20:inst|cpu:the_cpu|d_readdata_d1[9]~127 at LC_X40_Y25_N7

--operation mode is normal

S1L530Q = AMPP_FUNCTION(QC2__clk0, T1L312, T1L152, T1L151, T1L154, F1_data_out);

--S1L1443Q is std_1c20:inst|cpu:the_cpu|i_readdata_d1[9]~144 at LC_X43_Y19_N3

--operation mode is normal

S1L1443Q = AMPP_FUNCTION(QC2__clk0, S1_ic_fill_line[5], CE1_q_a[9], V1L6, S1L1756Q, F1_data_out);

--S1L1301 is std_1c20:inst|cpu:the_cpu|F_pc_plus_one[6]~86 at LC_X27_Y19_N9

--operation mode is arithmetic

S1L1301 = AMPP_FUNCTION(S1_F_pc[6], S1L1288, S1L1299, S1L1300);

--S1_D_pc_plus_one[6] is std_1c20:inst|cpu:the_cpu|D_pc_plus_one[6] at LC_X27_Y19_N9

--operation mode is arithmetic

S1_D_pc_plus_one[6] = AMPP_FUNCTION(QC2__clk0, S1_F_pc[6], F1_data_out, S1_W_stall, S1L1288, S1L1299, S1L1300);

--S1L1302 is std_1c20:inst|cpu:the_cpu|F_pc_plus_one[6]~87 at LC_X27_Y19_N9

--operation mode is arithmetic

S1L1302 = AMPP_FUNCTION(S1_F_pc[6], S1L1288, S1L1299, S1L1300);

--Z1_readdata[8] is std_1c20:inst|high_res_timer:the_high_res_timer|readdata[8] at LC_X51_Y23_N4

--operation mode is normal

Z1_readdata[8]_lut_out = S1L1738Q & !S1_M_alu_result[3] & (Z1L199) # !S1L1738Q & S1_M_alu_result[3] & (Z1L200 $ !Z1L199);

Z1_readdata[8] = DFFEAS(Z1_readdata[8]_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--XE1_readdata[8] is std_1c20:inst|uart1:the_uart1|uart1_regs:the_uart1_regs|readdata[8] at LC_X48_Y22_N3

--operation mode is normal

XE1_readdata[8]_lut_out = XE1L22 & (S1L1726Q & XE1_control_reg[8] # !S1L1726Q & (XE1L1));

XE1_readdata[8] = DFFEAS(XE1_readdata[8]_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--T1_registered_cpu_data_master_readdata[8] is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|registered_cpu_data_master_readdata[8] at LC_X44_Y26_N5

--operation mode is normal

T1_registered_cpu_data_master_readdata[8]_lut_out = T1L478 & T1L515 & (KB1_za_data[8] # !S1L1693Q);

T1_registered_cpu_data_master_readdata[8] = DFFEAS(T1_registered_cpu_data_master_readdata[8]_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--T1L137 is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[8]~5288 at LC_X46_Y26_N1

--operation mode is normal

T1L137 = T1_registered_cpu_data_master_readdata[8] # !K1_cpu_data_master_requests_clock_0_in & (!UB1L9 # !CB1L2);

--RB1_readdata[8] is std_1c20:inst|sys_clk_timer:the_sys_clk_timer|readdata[8] at LC_X48_Y26_N4

--operation mode is normal

RB1_readdata[8]_lut_out = S1_M_alu_result[3] & !S1L1738Q & (RB1L202 $ !RB1L203) # !S1_M_alu_result[3] & S1L1738Q & RB1L202;

RB1_readdata[8] = DFFEAS(RB1_readdata[8]_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--T1L139 is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[8]~5290 at LC_X44_Y26_N2

--operation mode is normal

T1L139 = S1L1693Q & (!T1L360 & S1L1689Q # !T1_registered_cpu_data_master_readdata[8]) # !S1L1693Q & (!T1L360 & S1L1689Q);

--T1L140 is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[8]~5291 at LC_X44_Y26_N9

--operation mode is normal

T1L140 = !T1L139 & (Y1_internal_incoming_ext_ram_bus_data[8] # !Y1_cpu_data_master_requests_ext_ram_s1 & !Y1L146);

--T1L141 is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[8]~5292 at LC_X44_Y26_N7

--operation mode is normal

T1L141 = T1L140 & !EB1L18 & (T1_registered_cpu_data_master_readdata[8] # !N1_cpu_data_master_requests_clock_1_in);

--DE1_data_to_cpu[8] is std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|data_to_cpu[8] at LC_X39_Y27_N6

--operation mode is normal

DE1_data_to_cpu[8]_lut_out = DE1L255 & DE1_iE_reg # !DE1L255 & (DE1L9);

DE1_data_to_cpu[8] = DFFEAS(DE1_data_to_cpu[8]_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , DE1_E, , , DE1L256);

--U1L158 is std_1c20:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_readdata~2404 at LC_X45_Y23_N1

--operation mode is normal

U1L158 = W1L1 & DE1_data_to_cpu[8] # !W1L1 & (FE1_q_a[8]);

--S1L525Q is std_1c20:inst|cpu:the_cpu|d_readdata_d1[8]~109 at LC_X46_Y23_N6

--operation mode is normal

S1L525Q = AMPP_FUNCTION(QC2__clk0, T1L149, T1L145, T1L99, T1L147, F1_data_out);

--S1L526Q is std_1c20:inst|cpu:the_cpu|d_readdata_d1[8]~110 at LC_X42_Y21_N5

--operation mode is normal

S1L526Q = AMPP_FUNCTION(QC2__clk0, S1L1756Q, S1_ic_fill_line[5], V1L6, CE1_q_a[8], F1_data_out);

--S1L1298 is std_1c20:inst|cpu:the_cpu|F_pc_plus_one[5]~88 at LC_X27_Y19_N8

--operation mode is arithmetic

S1L1298 = AMPP_FUNCTION(S1_F_pc[5], S1L1288, S1L1296, S1L1297);

--S1_D_pc_plus_one[5] is std_1c20:inst|cpu:the_cpu|D_pc_plus_one[5] at LC_X27_Y19_N8

--operation mode is arithmetic

S1_D_pc_plus_one[5] = AMPP_FUNCTION(QC2__clk0, S1_F_pc[5], F1_data_out, S1_W_stall, S1L1288, S1L1296, S1L1297);

--S1L1299 is std_1c20:inst|cpu:the_cpu|F_pc_plus_one[5]~89 at LC_X27_Y19_N8

--operation mode is arithmetic

S1L1299 = AMPP_FUNCTION(S1_F_pc[5], S1L1296);

--S1L1300 is std_1c20:inst|cpu:the_cpu|F_pc_plus_one[5]~89COUT1_988 at LC_X27_Y19_N8

--operation mode is arithmetic

S1L1300 = AMPP_FUNCTION(S1_F_pc[5], S1L1297);

--Y1_d1_irq_from_the_lan91c111 is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_irq_from_the_lan91c111 at LC_X58_Y30_N2

--operation mode is normal

Y1_d1_irq_from_the_lan91c111_lut_out = irq_from_the_lan91c111;

Y1_d1_irq_from_the_lan91c111 = DFFEAS(Y1_d1_irq_from_the_lan91c111_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--RB1_readdata[6] is std_1c20:inst|sys_clk_timer:the_sys_clk_timer|readdata[6] at LC_X47_Y26_N2

--operation mode is normal

RB1_readdata[6]_lut_out = S1L1738Q & (!S1_M_alu_result[3] & RB1L198) # !S1L1738Q & S1_M_alu_result[3] & (RB1L199 $ !RB1L198);

RB1_readdata[6] = DFFEAS(RB1_readdata[6]_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--Z1_readdata[6] is std_1c20:inst|high_res_timer:the_high_res_timer|readdata[6] at LC_X55_Y26_N1

--operation mode is normal

Z1_readdata[6]_lut_out = S1_M_alu_result[3] & !S1L1738Q & (Z1L195 $ !Z1L196) # !S1_M_alu_result[3] & S1L1738Q & Z1L195;

Z1_readdata[6] = DFFEAS(Z1_readdata[6]_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--XE1_readdata[6] is std_1c20:inst|uart1:the_uart1|uart1_regs:the_uart1_regs|readdata[6] at LC_X51_Y23_N9

--operation mode is normal

XE1_readdata[6]_lut_out = !S1L1738Q & (S1L1726Q & (XE1L60) # !S1L1726Q & XE1L61);

XE1_readdata[6] = DFFEAS(XE1_readdata[6]_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--T1_registered_cpu_data_master_readdata[6] is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|registered_cpu_data_master_readdata[6] at LC_X45_Y26_N1

--operation mode is normal

T1_registered_cpu_data_master_readdata[6]_lut_out = T1L476 & T1L506 & (KB1_za_data[6] # !S1L1693Q);

T1_registered_cpu_data_master_readdata[6] = DFFEAS(T1_registered_cpu_data_master_readdata[6]_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--T1L107 is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[6]~5297 at LC_X45_Y26_N2

--operation mode is normal

T1L107 = T1_registered_cpu_data_master_readdata[6] # !K1_cpu_data_master_requests_clock_0_in & (!UB1L9 # !CB1L2);

--T1L109 is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[6]~5299 at LC_X46_Y25_N7

--operation mode is normal

T1L109 = T1L115 # T1L113 # EB1L18 & !A1L135;

--DE1L82 is std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|data_to_cpu[6]~42 at LC_X38_Y28_N7

--operation mode is normal

DE1L82 = DE1L61Q & (DE1L83Q) # !DE1L61Q & DE1L84Q;

--U1L159 is std_1c20:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_readdata~2405 at LC_X46_Y27_N4

--operation mode is normal

U1L159 = W1L1 & (DE1L82) # !W1L1 & FE1_q_a[6];

--S1L1295 is std_1c20:inst|cpu:the_cpu|F_pc_plus_one[4]~90 at LC_X27_Y19_N7

--operation mode is arithmetic

S1L1295 = AMPP_FUNCTION(S1_F_pc[4], S1L1288, S1L1293, S1L1294);

--S1_D_pc_plus_one[4] is std_1c20:inst|cpu:the_cpu|D_pc_plus_one[4] at LC_X27_Y19_N7

--operation mode is arithmetic

S1_D_pc_plus_one[4] = AMPP_FUNCTION(QC2__clk0, S1_F_pc[4], F1_data_out, S1_W_stall, S1L1288, S1L1293, S1L1294);

--S1L1296 is std_1c20:inst|cpu:the_cpu|F_pc_plus_one[4]~91 at LC_X27_Y19_N7

--operation mode is arithmetic

S1L1296 = AMPP_FUNCTION(S1_F_pc[4], S1L1293);

--S1L1297 is std_1c20:inst|cpu:the_cpu|F_pc_plus_one[4]~91COUT1_986 at LC_X27_Y19_N7

--operation mode is arithmetic

S1L1297 = AMPP_FUNCTION(S1_F_pc[4], S1L1294);

--XE1_irq is std_1c20:inst|uart1:the_uart1|uart1_regs:the_uart1_regs|irq at LC_X48_Y22_N9

--operation mode is normal

XE1_irq_lut_out = XE1L37 # XE1L36 # YE1_internal_rx_char_ready & XE1_control_reg[7];

XE1_irq = DFFEAS(XE1_irq_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--Z1_readdata[4] is std_1c20:inst|high_res_timer:the_high_res_timer|readdata[4] at LC_X55_Y26_N2

--operation mode is normal

Z1_readdata[4]_lut_out = S1_M_alu_result[3] & !S1L1738Q & (Z1L192 $ !Z1L191) # !S1_M_alu_result[3] & S1L1738Q & (Z1L191);

Z1_readdata[4] = DFFEAS(Z1_readdata[4]_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--XE1_readdata[4] is std_1c20:inst|uart1:the_uart1|uart1_regs:the_uart1_regs|readdata[4] at LC_X47_Y23_N2

--operation mode is normal

XE1_readdata[4]_lut_out = !S1L1738Q & (S1L1726Q & XE1L56 # !S1L1726Q & (XE1L57));

XE1_readdata[4] = DFFEAS(XE1_readdata[4]_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--RB1_readdata[4] is std_1c20:inst|sys_clk_timer:the_sys_clk_timer|readdata[4] at LC_X51_Y25_N2

--operation mode is normal

RB1_readdata[4]_lut_out = S1_M_alu_result[3] & !S1L1738Q & (RB1L195 $ !RB1L194) # !S1_M_alu_result[3] & S1L1738Q & (RB1L194);

RB1_readdata[4] = DFFEAS(RB1_readdata[4]_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--T1_registered_cpu_data_master_readdata[4] is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|registered_cpu_data_master_readdata[4] at LC_X43_Y23_N9

--operation mode is normal

T1_registered_cpu_data_master_readdata[4]_lut_out = T1L474 & T1L504 & (KB1_za_data[4] # !S1L1693Q);

T1_registered_cpu_data_master_readdata[4] = DFFEAS(T1_registered_cpu_data_master_readdata[4]_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--T1L84 is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[4]~5305 at LC_X43_Y23_N0

--operation mode is normal

T1L84 = T1_registered_cpu_data_master_readdata[4] # !N1_cpu_data_master_requests_clock_1_in & (!UB1L9 # !CB1L2);

--T1L85 is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[4]~5306 at LC_X43_Y23_N8

--operation mode is normal

T1L85 = !T1L90 & (!UB1L9 # !UB1L10 # !S1L1726Q);

--T1L320 is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata~568 at LC_X44_Y23_N8

--operation mode is normal

T1L320 = A1L137 # S1L1743Q # !JB1L3;

--T1L87 is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[4]~5308 at LC_X43_Y23_N2

--operation mode is normal

T1L87 = T1L320 & (T1_registered_cpu_data_master_readdata[4] # !S1L1693Q & !K1_cpu_data_master_requests_clock_0_in);

--DE1L60 is std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|data_to_cpu[4]~41 at LC_X38_Y28_N4

--operation mode is normal

DE1L60 = DE1L61Q & DE1L62Q # !DE1L61Q & (DE1L63Q);

--U1L160 is std_1c20:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_readdata~2406 at LC_X38_Y23_N4

--operation mode is normal

U1L160 = W1L1 & (DE1L60) # !W1L1 & FE1_q_a[4];

--WC1L7 is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|readdata[4]~1367 at LC_X38_Y20_N7

--operation mode is normal

WC1L7 = AMPP_FUNCTION(S1L1756Q, S1_ic_fill_line[5], CE1_q_a[4], V1L6);

--S1L1289 is std_1c20:inst|cpu:the_cpu|F_pc_plus_one[2]~92 at LC_X27_Y19_N5

--operation mode is arithmetic

S1L1289 = AMPP_FUNCTION(S1_F_pc[2], S1L1288);

--S1_D_pc_plus_one[2] is std_1c20:inst|cpu:the_cpu|D_pc_plus_one[2] at LC_X27_Y19_N5

--operation mode is arithmetic

S1_D_pc_plus_one[2] = AMPP_FUNCTION(QC2__clk0, S1_F_pc[2], F1_data_out, S1_W_stall, S1L1288);

--S1L1290 is std_1c20:inst|cpu:the_cpu|F_pc_plus_one[2]~93 at LC_X27_Y19_N5

--operation mode is arithmetic

S1L1290 = AMPP_FUNCTION(S1_F_pc[2]);

--S1L1291 is std_1c20:inst|cpu:the_cpu|F_pc_plus_one[2]~93COUT1_982 at LC_X27_Y19_N5

--operation mode is arithmetic

S1L1291 = AMPP_FUNCTION(S1_F_pc[2]);

--DE1_irq_reg is std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|irq_reg at LC_X38_Y27_N0

--operation mode is normal

DE1_irq_reg_lut_out = DE1L268 # DE1L269 # DE1_ROE & DE1_iROE_reg;

DE1_irq_reg = DFFEAS(DE1_irq_reg_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--Z1_readdata[5] is std_1c20:inst|high_res_timer:the_high_res_timer|readdata[5] at LC_X51_Y23_N7

--operation mode is normal

Z1_readdata[5]_lut_out = S1L1738Q & (Z1L193 & !S1_M_alu_result[3]) # !S1L1738Q & S1_M_alu_result[3] & (Z1L194 $ !Z1L193);

Z1_readdata[5] = DFFEAS(Z1_readdata[5]_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--XE1_readdata[5] is std_1c20:inst|uart1:the_uart1|uart1_regs:the_uart1_regs|readdata[5] at LC_X47_Y23_N4

--operation mode is normal

XE1_readdata[5]_lut_out = !S1L1738Q & (S1L1726Q & (XE1L58) # !S1L1726Q & XE1L59);

XE1_readdata[5] = DFFEAS(XE1_readdata[5]_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--T1_registered_cpu_data_master_readdata[5] is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|registered_cpu_data_master_readdata[5] at LC_X45_Y25_N9

--operation mode is normal

T1_registered_cpu_data_master_readdata[5]_lut_out = T1L505 & T1L475 & (KB1_za_data[5] # !S1L1693Q);

T1_registered_cpu_data_master_readdata[5] = DFFEAS(T1_registered_cpu_data_master_readdata[5]_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--T1L93 is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[5]~5312 at LC_X45_Y25_N5

--operation mode is normal

T1L93 = T1_registered_cpu_data_master_readdata[5] # !K1_cpu_data_master_requests_clock_0_in & (!UB1L9 # !CB1L2);

--RB1_readdata[5] is std_1c20:inst|sys_clk_timer:the_sys_clk_timer|readdata[5] at LC_X48_Y26_N1

--operation mode is normal

RB1_readdata[5]_lut_out = S1_M_alu_result[3] & !S1L1738Q & (RB1L196 $ !RB1L197) # !S1_M_alu_result[3] & S1L1738Q & RB1L196;

RB1_readdata[5] = DFFEAS(RB1_readdata[5]_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--T1L96 is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[5]~5315 at LC_X46_Y25_N3

--operation mode is normal

T1L96 = T1L103 # T1L101 # EB1L18 & !A1L136;

--DE1L68 is std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|data_to_cpu[5]~32 at LC_X37_Y26_N6

--operation mode is normal

DE1L68 = DE1L72Q & DE1L71Q & (!DE1L69Q) # !DE1L72Q & (DE1L70Q);

--U1L161 is std_1c20:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_readdata~2407 at LC_X46_Y23_N0

--operation mode is normal

U1L161 = W1L1 & (DE1L68) # !W1L1 & FE1_q_a[5];

--WC1L8 is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|readdata[5]~1368 at LC_X39_Y21_N1

--operation mode is normal

WC1L8 = AMPP_FUNCTION(S1L1756Q, S1_ic_fill_line[5], CE1_q_a[5], V1L6);

--S1L1292 is std_1c20:inst|cpu:the_cpu|F_pc_plus_one[3]~94 at LC_X27_Y19_N6

--operation mode is arithmetic

S1L1292 = AMPP_FUNCTION(S1_F_pc[3], S1L1288, S1L1290, S1L1291);

--S1_D_pc_plus_one[3] is std_1c20:inst|cpu:the_cpu|D_pc_plus_one[3] at LC_X27_Y19_N6

--operation mode is arithmetic

S1_D_pc_plus_one[3] = AMPP_FUNCTION(QC2__clk0, S1_F_pc[3], F1_data_out, S1_W_stall, S1L1288, S1L1290, S1L1291);

--S1L1293 is std_1c20:inst|cpu:the_cpu|F_pc_plus_one[3]~95 at LC_X27_Y19_N6

--operation mode is arithmetic

S1L1293 = AMPP_FUNCTION(S1_F_pc[3], S1L1290);

--S1L1294 is std_1c20:inst|cpu:the_cpu|F_pc_plus_one[3]~95COUT1_984 at LC_X27_Y19_N6

--operation mode is arithmetic

S1L1294 = AMPP_FUNCTION(S1_F_pc[3], S1L1291);

--S1_M_shift_rot_result[31] is std_1c20:inst|cpu:the_cpu|M_shift_rot_result[31] at LC_X40_Y12_N5

--operation mode is normal

S1_M_shift_rot_result[31] = AMPP_FUNCTION(QC2__clk0, S1_M_shift_rot_result[30], S1L2221, S1L884, S1_M_ctrl_shift_rot_right, F1_data_out, !S1_M_shift_rot_stall);

--S1_M_ctrl_shift_logical is std_1c20:inst|cpu:the_cpu|M_ctrl_shift_logical at LC_X38_Y14_N8

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

S1_M_ctrl_shift_logical = AMPP_FUNCTION(QC2__clk0, S1_E_ctrl_shift_logical, F1_data_out, GND, S1_W_stall);

--S1L2221 is std_1c20:inst|cpu:the_cpu|M_shift_rot_fill_bit~45 at LC_X38_Y13_N9

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

S1L2221 = AMPP_FUNCTION(S1_M_shift_rot_result[0], S1_M_shift_rot_result[31], S1_M_ctrl_shift_logical);

--S1_M_ctrl_rot_right is std_1c20:inst|cpu:the_cpu|M_ctrl_rot_right at LC_X38_Y13_N9

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

S1_M_ctrl_rot_right = AMPP_FUNCTION(QC2__clk0, S1_E_ctrl_rot_right, F1_data_out, GND, S1_W_stall);

--S1L437Q is std_1c20:inst|cpu:the_cpu|d_readdata_d1[0]~95 at LC_X41_Y23_N6

--operation mode is normal

S1L437Q = AMPP_FUNCTION(QC2__clk0, S1L444, S1L446, S1L442, S1L440, F1_data_out);

--S1L1360 is std_1c20:inst|cpu:the_cpu|i_readdata_d1[0]~130 at LC_X44_Y19_N1

--operation mode is normal

S1L1360 = AMPP_FUNCTION(S1L1361Q, S1L1367Q, S1L524Q, WC1L1);

--T1_cpu_data_master_readdata[0] is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[0] at LC_X39_Y19_N3

--operation mode is normal

T1_cpu_data_master_readdata[0] = S1L437Q & (S1L438Q # S1L1360);

--S1L453Q is std_1c20:inst|cpu:the_cpu|d_readdata_d1[1]~94 at LC_X43_Y24_N4

--operation mode is normal

S1L453Q = AMPP_FUNCTION(QC2__clk0, S1L457, S1L459, S1L461, S1L455, F1_data_out);

--S1L1366 is std_1c20:inst|cpu:the_cpu|i_readdata_d1[1]~126 at LC_X44_Y19_N5

--operation mode is normal

S1L1366 = AMPP_FUNCTION(S1L1368Q, S1L1367Q, S1L524Q, WC1L2);

--T1_cpu_data_master_readdata[1] is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[1] at LC_X39_Y19_N4

--operation mode is normal

T1_cpu_data_master_readdata[1] = S1L453Q & (S1L438Q # S1L1366);

--S1_reset_d1 is std_1c20:inst|cpu:the_cpu|reset_d1 at LC_X26_Y20_N5

--operation mode is normal

S1_reset_d1 = AMPP_FUNCTION(QC2__clk0, F1_data_out);

--S1L2035 is std_1c20:inst|cpu:the_cpu|M_bstatus_reg~3 at LC_X32_Y15_N2

--operation mode is normal

S1L2035 = AMPP_FUNCTION(S1L2040Q, S1L2041Q, S1L2045);

--S1L2071 is std_1c20:inst|cpu:the_cpu|M_estatus_reg~3 at LC_X32_Y15_N3

--operation mode is normal

S1L2071 = AMPP_FUNCTION(S1L2040Q, S1L2075Q, S1L2077);

--S1L271 is std_1c20:inst|cpu:the_cpu|D_control_rd_data_without_mmu_regs[0]~504 at LC_X32_Y19_N8

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

S1L271 = AMPP_FUNCTION(S1_D_iw[7], S1L2073, S1_D_iw[6]);

--S1_M_ienable_reg[0] is std_1c20:inst|cpu:the_cpu|M_ienable_reg[0] at LC_X32_Y19_N8

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

S1_M_ienable_reg[0] = AMPP_FUNCTION(QC2__clk0, S1L676, F1_data_out, GND, S1L2099);

--S1L272 is std_1c20:inst|cpu:the_cpu|D_control_rd_data_without_mmu_regs[0]~505 at LC_X32_Y19_N2

--operation mode is normal

S1L272 = AMPP_FUNCTION(S1L2381, S1_M_ipending_reg[0], S1L271, S1_D_iw[8]);

--EF1_dffs[1] is sld_hub:sld_hub_inst|lpm_shiftreg:jtag_ir_register|dffs[1] at LC_X58_Y16_N2

--operation mode is normal

EF1_dffs[1] = AMPP_FUNCTION(A1L5, EF1_dffs[2], FF1_state[0], FF1_state[11]);

--EF1_dffs[8] is sld_hub:sld_hub_inst|lpm_shiftreg:jtag_ir_register|dffs[8] at LC_X58_Y16_N7

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

EF1_dffs[8] = AMPP_FUNCTION(A1L5, EF1_dffs[9], FF1_state[0], GND, FF1_state[11]);

--EF1_dffs[7] is sld_hub:sld_hub_inst|lpm_shiftreg:jtag_ir_register|dffs[7] at LC_X58_Y16_N0

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

EF1_dffs[7] = AMPP_FUNCTION(A1L5, EF1_dffs[8], FF1_state[0], GND, FF1_state[11]);

--EF1_dffs[6] is sld_hub:sld_hub_inst|lpm_shiftreg:jtag_ir_register|dffs[6] at LC_X58_Y15_N1

--operation mode is normal

EF1_dffs[6] = AMPP_FUNCTION(A1L5, EF1_dffs[7], FF1_state[0], FF1_state[11]);

--C1L6 is sld_hub:sld_hub_inst|Equal0~87 at LC_X58_Y16_N5

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

C1L6 = AMPP_FUNCTION(EF1_dffs[8], EF1_dffs[6], EF1_dffs[7]);

--EF1_dffs[9] is sld_hub:sld_hub_inst|lpm_shiftreg:jtag_ir_register|dffs[9] at LC_X58_Y16_N5

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

EF1_dffs[9] = AMPP_FUNCTION(A1L5, altera_internal_jtag, FF1_state[0], GND, FF1_state[11]);

--EF1_dffs[2] is sld_hub:sld_hub_inst|lpm_shiftreg:jtag_ir_register|dffs[2] at LC_X58_Y16_N1

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

EF1_dffs[2] = AMPP_FUNCTION(A1L5, EF1_dffs[3], FF1_state[0], GND, FF1_state[11]);

--EF1_dffs[5] is sld_hub:sld_hub_inst|lpm_shiftreg:jtag_ir_register|dffs[5] at LC_X58_Y15_N2

--operation mode is normal

EF1_dffs[5] = AMPP_FUNCTION(A1L5, EF1_dffs[6], FF1_state[0], FF1_state[11]);

--EF1_dffs[4] is sld_hub:sld_hub_inst|lpm_shiftreg:jtag_ir_register|dffs[4] at LC_X58_Y16_N3

--operation mode is normal

EF1_dffs[4] = AMPP_FUNCTION(A1L5, EF1_dffs[5], FF1_state[0], FF1_state[11]);

--C1L7 is sld_hub:sld_hub_inst|Equal0~88 at LC_X58_Y16_N6

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

C1L7 = AMPP_FUNCTION(EF1_dffs[5], EF1_dffs[4], EF1_dffs[2]);

--EF1_dffs[3] is sld_hub:sld_hub_inst|lpm_shiftreg:jtag_ir_register|dffs[3] at LC_X58_Y16_N6

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

EF1_dffs[3] = AMPP_FUNCTION(A1L5, EF1_dffs[4], FF1_state[0], GND, FF1_state[11]);

--EF1_dffs[0] is sld_hub:sld_hub_inst|lpm_shiftreg:jtag_ir_register|dffs[0] at LC_X58_Y16_N9

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

EF1_dffs[0] = AMPP_FUNCTION(A1L5, EF1_dffs[1], FF1_state[0], GND, FF1_state[11]);

--FF1_state[0] is sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state[0] at LC_X57_Y15_N1

--operation mode is normal

FF1_state[0] = AMPP_FUNCTION(A1L5, FF1_state[0], FF1L19, A1L7, FF1_state[9], VCC);

--FF1_state[12] is sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state[12] at LC_X58_Y15_N9

--operation mode is normal

FF1_state[12] = AMPP_FUNCTION(A1L5, FF1_state[10], FF1_state[11], VCC, !A1L7);

--FF1_state[5] is sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state[5] at LC_X58_Y17_N0

--operation mode is normal

FF1_state[5] = AMPP_FUNCTION(A1L5, FF1_state[3], A1L7, FF1_state[4], VCC);

--FF1_state[7] is sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state[7] at LC_X58_Y17_N9

--operation mode is normal

FF1_state[7] = AMPP_FUNCTION(A1L5, A1L7, FF1_state[6], VCC);

--BF3_Q[6] is sld_hub:sld_hub_inst|sld_dffex:IRSR|Q[6] at LC_X56_Y18_N4

--operation mode is normal

BF3_Q[6] = AMPP_FUNCTION(A1L5, altera_internal_jtag, !C1_CLR_SIGNAL, FF1_state[4], C1_IRSR_ENA);

--C1_OK_TO_UPDATE_IR_Q is sld_hub:sld_hub_inst|OK_TO_UPDATE_IR_Q at LC_X56_Y17_N6

--operation mode is normal

C1_OK_TO_UPDATE_IR_Q = AMPP_FUNCTION(A1L5, C1_jtag_debug_mode_usr1, FF1_state[8], FF1_state[4], C1_OK_TO_UPDATE_IR_Q, VCC);

--C1L24 is sld_hub:sld_hub_inst|IRF_ENA_ENABLE~29 at LC_X58_Y17_N7

--operation mode is normal

C1L24 = AMPP_FUNCTION(A1L7, FF1_state[4], C1_OK_TO_UPDATE_IR_Q, C1_jtag_debug_mode_usr1);

--CF1_WORD_SR[1] is sld_hub:sld_hub_inst|sld_rom_sr:HUB_INFO_REG|WORD_SR[1] at LC_X59_Y18_N3

--operation mode is normal

CF1_WORD_SR[1] = AMPP_FUNCTION(A1L5, CF1_WORD_SR[2], CF1_clear_signal, FF1_state[4], CF1L19, VCC, CF1L25);

--CF1_word_counter[4] is sld_hub:sld_hub_inst|sld_rom_sr:HUB_INFO_REG|word_counter[4] at LC_X58_Y18_N5

--operation mode is normal

CF1_word_counter[4] = AMPP_FUNCTION(A1L5, CF1_clear_signal, CF1L15, CF1_word_counter[3], CF1L1, VCC, CF1L24);

--CF1_word_counter[0] is sld_hub:sld_hub_inst|sld_rom_sr:HUB_INFO_REG|word_counter[0] at LC_X58_Y18_N7

--operation mode is normal

CF1_word_counter[0] = AMPP_FUNCTION(A1L5, CF1_word_counter[0], CF1L15, CF1_word_counter[3], CF1_clear_signal, VCC, CF1L24);

--CF1_word_counter[1] is sld_hub:sld_hub_inst|sld_rom_sr:HUB_INFO_REG|word_counter[1] at LC_X58_Y18_N9

--operation mode is normal

CF1_word_counter[1] = AMPP_FUNCTION(A1L5, FF1_state[8], C1_jtag_debug_mode_usr1, CF1L5, VCC, CF1L24);

--CF1_word_counter[2] is sld_hub:sld_hub_inst|sld_rom_sr:HUB_INFO_REG|word_counter[2] at LC_X58_Y18_N6

--operation mode is normal

CF1_word_counter[2] = AMPP_FUNCTION(A1L5, CF1L8, FF1_state[8], C1_jtag_debug_mode_usr1, VCC, CF1L24);

--CF1_word_counter[3] is sld_hub:sld_hub_inst|sld_rom_sr:HUB_INFO_REG|word_counter[3] at LC_X58_Y18_N8

--operation mode is normal

CF1_word_counter[3] = AMPP_FUNCTION(A1L5, CF1_clear_signal, CF1L15, CF1_word_counter[3], CF1L11, VCC, CF1L24);

--CF1L20 is sld_hub:sld_hub_inst|sld_rom_sr:HUB_INFO_REG|Mux3~33 at LC_X59_Y18_N7

--operation mode is normal

CF1L20 = AMPP_FUNCTION(CF1_word_counter[2], CF1_word_counter[1], CF1_word_counter[3], CF1_word_counter[0]);

--CF1L23 is sld_hub:sld_hub_inst|sld_rom_sr:HUB_INFO_REG|word_counter[0]~1274 at LC_X60_Y18_N9

--operation mode is normal

CF1L23 = AMPP_FUNCTION(CF1_word_counter[4], CF1L20);

--CF1_clear_signal is sld_hub:sld_hub_inst|sld_rom_sr:HUB_INFO_REG|clear_signal at LC_X58_Y17_N5

--operation mode is normal

CF1_clear_signal = AMPP_FUNCTION(C1_jtag_debug_mode_usr1, FF1_state[8]);

--C1_jtag_debug_mode_usr0 is sld_hub:sld_hub_inst|jtag_debug_mode_usr0 at LC_X58_Y16_N8

--operation mode is normal

C1_jtag_debug_mode_usr0 = AMPP_FUNCTION(A1L5, EF1_dffs[0], C1L6, EF1_dffs[1], C1L7, FF1_state[0], FF1_state[12]);

--C1L11 is sld_hub:sld_hub_inst|HUB_BYPASS_REG~20 at LC_X53_Y19_N2

--operation mode is normal

C1L11 = AMPP_FUNCTION(altera_internal_jtag, FF1_state[4]);

--GE1_td_shift[10] is std_1c20:inst|jtag_uart:the_jtag_uart|alt_jtag_atlantic:jtag_uart_alt_jtag_atlantic|td_shift[10] at LC_X53_Y19_N2

--operation mode is normal

GE1_td_shift[10] = AMPP_FUNCTION(A1L5, altera_internal_jtag, FF1_state[4], !C1_CLR_SIGNAL, GE1L52);

--C1L32 is sld_hub:sld_hub_inst|jtag_debug_mode~2 at LC_X57_Y17_N1

--operation mode is normal

C1L32 = AMPP_FUNCTION(C1_jtag_debug_mode_usr1, C1_jtag_debug_mode_usr0);

--BF3_Q[1] is sld_hub:sld_hub_inst|sld_dffex:IRSR|Q[1] at LC_X57_Y18_N0

--operation mode is normal

BF3_Q[1] = AMPP_FUNCTION(A1L5, C1L23, BF3_Q[2], SD1L120Q, !C1_CLR_SIGNAL, FF1_state[4], BF3L4);

--BF3_Q[3] is sld_hub:sld_hub_inst|sld_dffex:IRSR|Q[3] at LC_X57_Y18_N1

--operation mode is normal

BF3_Q[3] = AMPP_FUNCTION(A1L5, BF3_Q[4], FF1_state[4], !C1_CLR_SIGNAL, BF3L4);

--BF3_Q[2] is sld_hub:sld_hub_inst|sld_dffex:IRSR|Q[2] at LC_X57_Y18_N2

--operation mode is normal

BF3_Q[2] = AMPP_FUNCTION(A1L5, BF3_Q[3], FF1_state[4], !C1_CLR_SIGNAL, BF3L4);

--C1L4 is sld_hub:sld_hub_inst|comb~98 at LC_X58_Y17_N2

--operation mode is normal

C1L4 = AMPP_FUNCTION(C1_jtag_debug_mode_usr0, FF1_state[3], FF1_state[4], C1_jtag_debug_mode_usr1);

--SD1_sr[1] is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|sr[1] at LC_X52_Y16_N5

--operation mode is normal

SD1_sr[1] = AMPP_FUNCTION(A1L5, SD1L143, SD1L141, SD1_sr[2], SD1L130, !C1_CLR_SIGNAL, SD1L6);

--SD1_DRsize[2] is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|DRsize[2] at LC_X52_Y15_N9

--operation mode is normal

SD1_DRsize[2] = AMPP_FUNCTION(A1L5, BF5_Q[0], BF5_Q[1], !C1_CLR_SIGNAL, SD1_st_updateir);

--SD1_DRsize[0] is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|DRsize[0] at LC_X52_Y15_N7

--operation mode is normal

SD1_DRsize[0] = AMPP_FUNCTION(A1L5, BF5_Q[0], BF5_Q[1], !C1_CLR_SIGNAL, SD1_st_updateir);

--SD1L73Q is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|DRsize[1]~19729 at LC_X52_Y15_N0

--operation mode is normal

SD1L73Q = AMPP_FUNCTION(A1L5, !C1_CLR_SIGNAL, SD1_st_updateir);

--SD1L139 is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|Mux45~158 at LC_X52_Y15_N8

--operation mode is normal

SD1L139 = AMPP_FUNCTION(SD1_DRsize[1], SD1_DRsize[0], SD1_DRsize[2], SD1L73Q);

--SD1L140 is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|Mux45~159 at LC_X53_Y16_N1

--operation mode is normal

SD1L140 = AMPP_FUNCTION(SD1L139, altera_internal_jtag, SD1_sr[1]);

--JD1_internal_monitor_ready is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_debug:the_cpu_nios2_oci_debug|internal_monitor_ready at LC_X45_Y19_N0

--operation mode is normal

JD1_internal_monitor_ready = AMPP_FUNCTION(QC2__clk0, FD1L1, JD1L10, FD1L2, JD1L8, VCC);

--SD1L5 is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|DRsize[0]~19969 at LC_X46_Y17_N1

--operation mode is normal

SD1L5 = AMPP_FUNCTION(SD1_ir[1], JD1_internal_monitor_ready, SD1_ir[0]);

--SD1_in_between_shiftdr_and_updatedr is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|in_between_shiftdr_and_updatedr at LC_X52_Y14_N5

--operation mode is normal

SD1_in_between_shiftdr_and_updatedr = AMPP_FUNCTION(A1L5, SD1_st_shiftdr, SD1_st_updatedr, SD1_in_between_shiftdr_and_updatedr, !C1_CLR_SIGNAL);

--SD1L142 is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|process2~311 at LC_X46_Y14_N8

--operation mode is normal

SD1L142 = AMPP_FUNCTION(A1L4, SD1_in_between_shiftdr_and_updatedr);

--SD1L143 is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|process2~312 at LC_X46_Y15_N0

--operation mode is normal

SD1L143 = AMPP_FUNCTION(A1L4, SD1L144);

--SD1L6 is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|DRsize[0]~19971 at LC_X52_Y14_N6

--operation mode is normal

SD1L6 = AMPP_FUNCTION(SD1_st_updateir, SD1L144, A1L4, SD1_in_between_shiftdr_and_updatedr);

--GE1_td_shift[1] is std_1c20:inst|jtag_uart:the_jtag_uart|alt_jtag_atlantic:jtag_uart_alt_jtag_atlantic|td_shift[1] at LC_X53_Y19_N1

--operation mode is normal

GE1_td_shift[1] = AMPP_FUNCTION(A1L5, GE1L53, GE1L54, GE1L63, !C1_CLR_SIGNAL, GE1L52);

--GE1_count[9] is std_1c20:inst|jtag_uart:the_jtag_uart|alt_jtag_atlantic:jtag_uart_alt_jtag_atlantic|count[9] at LC_X54_Y19_N9

--operation mode is normal

GE1_count[9] = AMPP_FUNCTION(A1L5, GND, GE1L55, VCC, C1_CLR_SIGNAL, GE1L52);

--GE1L65 is std_1c20:inst|jtag_uart:the_jtag_uart|alt_jtag_atlantic:jtag_uart_alt_jtag_atlantic|td_shift~3548 at LC_X52_Y19_N2

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

GE1L65 = AMPP_FUNCTION(GE1_count[9], GE1_td_shift[1]);

--GE1_rvalid is std_1c20:inst|jtag_uart:the_jtag_uart|alt_jtag_atlantic:jtag_uart_alt_jtag_atlantic|rvalid at LC_X52_Y19_N2

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

GE1_rvalid = AMPP_FUNCTION(QC2__clk0, GE1_rvalid0, F1_data_out, GND);

--GE1_state is std_1c20:inst|jtag_uart:the_jtag_uart|alt_jtag_atlantic:jtag_uart_alt_jtag_atlantic|state at LC_X55_Y19_N6

--operation mode is normal

GE1_state = AMPP_FUNCTION(A1L5, C1L11, GE1L36, GE1L1, GE1_state, !C1_CLR_SIGNAL);

--GE1L66 is std_1c20:inst|jtag_uart:the_jtag_uart|alt_jtag_atlantic:jtag_uart_alt_jtag_atlantic|td_shift~3549 at LC_X52_Y19_N8

--operation mode is normal

GE1L66 = AMPP_FUNCTION(GE1_state, altera_internal_jtag);

--GE1_count[1] is std_1c20:inst|jtag_uart:the_jtag_uart|alt_jtag_atlantic:jtag_uart_alt_jtag_atlantic|count[1] at LC_X54_Y19_N6

--operation mode is normal

GE1_count[1] = AMPP_FUNCTION(A1L5, GE1_count[0], FF1_state[4], !C1_CLR_SIGNAL, GE1L52);

--GE1_td_shift[9] is std_1c20:inst|jtag_uart:the_jtag_uart|alt_jtag_atlantic:jtag_uart_alt_jtag_atlantic|td_shift[9] at LC_X53_Y19_N8

--operation mode is normal

GE1_td_shift[9] = AMPP_FUNCTION(A1L5, GE1_td_shift[10], GE1_count[9], GE1_rdata[7], !C1_CLR_SIGNAL, !FF1_state[4], GE1L52);

--GE1_user_saw_rvalid is std_1c20:inst|jtag_uart:the_jtag_uart|alt_jtag_atlantic:jtag_uart_alt_jtag_atlantic|user_saw_rvalid at LC_X54_Y19_N1

--operation mode is normal

GE1_user_saw_rvalid = AMPP_FUNCTION(A1L5, GE1L69, GE1_user_saw_rvalid, GE1_count[0], GE1_td_shift[0], !C1_CLR_SIGNAL);

--GE1L67 is std_1c20:inst|jtag_uart:the_jtag_uart|alt_jtag_atlantic:jtag_uart_alt_jtag_atlantic|td_shift~3550 at LC_X52_Y19_N5

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

GE1L67 = AMPP_FUNCTION(GE1L65, GE1L66, GE1L62);

--BB1_t_dav is std_1c20:inst|jtag_uart:the_jtag_uart|t_dav at LC_X52_Y19_N5

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

BB1_t_dav = DFFEAS(GE1L67, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , NE2_b_full, , , VCC);

--BF4_Q[0] is sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:2:IRF|Q[0] at LC_X57_Y18_N3

--operation mode is normal

BF4_Q[0] = AMPP_FUNCTION(A1L5, C1L27, BF4L3, BF4_Q[0], !C1_CLR_SIGNAL);

--GE1L1 is std_1c20:inst|jtag_uart:the_jtag_uart|alt_jtag_atlantic:jtag_uart_alt_jtag_atlantic|always0~58 at LC_X56_Y16_N5

--operation mode is normal

GE1L1 = AMPP_FUNCTION(BF2_Q[0], C1_jtag_debug_mode, BF8_Q[1], C1_jtag_debug_mode_usr1);

--GE1L52 is std_1c20:inst|jtag_uart:the_jtag_uart|alt_jtag_atlantic:jtag_uart_alt_jtag_atlantic|td_shift[9]~3551 at LC_X55_Y19_N5

--operation mode is normal

GE1L52 = AMPP_FUNCTION(FF1_state[3], GE1L1, FF1_state[4]);

--SD1L119Q is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|ir_out[0]~reg0 at LC_X46_Y19_N2

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

SD1L119Q = AMPP_FUNCTION(A1L5, JD1_internal_monitor_ready, !C1_CLR_SIGNAL, GND);

--BF3_Q[4] is sld_hub:sld_hub_inst|sld_dffex:IRSR|Q[4] at LC_X57_Y18_N6

--operation mode is normal

BF3_Q[4] = AMPP_FUNCTION(A1L5, BF3_Q[5], FF1_state[4], !C1_CLR_SIGNAL, BF3L4);

--GF1_dffe1a[3] is sld_hub:sld_hub_inst|lpm_decode:instruction_decoder|decode_ogi:auto_generated|dffe1a[3] at LC_X57_Y17_N9

--operation mode is normal

GF1_dffe1a[3] = AMPP_FUNCTION(A1L5, BF3_Q[2], BF3_Q[3], BF3_Q[1], C1L32, !C1_CLR_SIGNAL, C1L5);

--C1L23 is sld_hub:sld_hub_inst|IR_MUX_SEL[1]~30 at LC_X57_Y18_N8

--operation mode is normal

C1L23 = AMPP_FUNCTION(BF3_Q[4], GF1_dffe1a[3], BF3_Q[6]);

--BF3_Q[5] is sld_hub:sld_hub_inst|sld_dffex:IRSR|Q[5] at LC_X56_Y18_N5

--operation mode is normal

BF3_Q[5] = AMPP_FUNCTION(A1L5, BF3_Q[5], FF1_state[4], BF3_Q[6], C1_jtag_debug_mode_usr1, !C1_CLR_SIGNAL);

--C1L22 is sld_hub:sld_hub_inst|IR_MUX_SEL[0]~31 at LC_X57_Y18_N4

--operation mode is normal

C1L22 = AMPP_FUNCTION(BF3_Q[3], BF3_Q[5], GF1_dffe1a[3]);

--BF3L3 is sld_hub:sld_hub_inst|sld_dffex:IRSR|Q[0]~7720 at LC_X57_Y18_N5

--operation mode is normal

BF3L3 = AMPP_FUNCTION(C1L23, C1L22, BF4_Q[0]);

--C1_IRSR_ENA is sld_hub:sld_hub_inst|IRSR_ENA at LC_X56_Y18_N2

--operation mode is normal

C1_IRSR_ENA = AMPP_FUNCTION(FF1_state[3], FF1_state[4], C1_jtag_debug_mode_usr1);

--BF3L4 is sld_hub:sld_hub_inst|sld_dffex:IRSR|Q[0]~7721 at LC_X57_Y18_N9

--operation mode is normal

BF3L4 = AMPP_FUNCTION(C1_IRSR_ENA, C1L22, C1L23, FF1_state[4]);

--FF1_state[2] is sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state[2] at LC_X58_Y15_N6

--operation mode is normal

FF1_state[2] = AMPP_FUNCTION(A1L5, FF1_state[1], FF1_state[15], FF1_state[8], VCC, !A1L7);

--XE1L16 is std_1c20:inst|uart1:the_uart1|uart1_regs:the_uart1_regs|Equal1~117 at LC_X24_Y19_N7

--operation mode is normal

XE1L16 = !S1_M_alu_result[3] & !S1_M_alu_result[2];

--XE1L17 is std_1c20:inst|uart1:the_uart1|uart1_regs:the_uart1_regs|Equal1~118 at LC_X51_Y24_N0

--operation mode is normal

XE1L17 = !S1_M_alu_result[3] & S1L1726Q;

--S1_M_st_data[31] is std_1c20:inst|cpu:the_cpu|M_st_data[31] at LC_X42_Y18_N2

--operation mode is normal

S1_M_st_data[31] = AMPP_FUNCTION(QC2__clk0, S1L1157, S1_E_iw[3], S1L1149, S1L2321, F1_data_out, S1_E_iw[4], S1_W_stall);

--S1_M_st_data[30] is std_1c20:inst|cpu:the_cpu|M_st_data[30] at LC_X42_Y18_N1

--operation mode is normal

S1_M_st_data[30] = AMPP_FUNCTION(QC2__clk0, S1L1156, S1_E_iw[3], S1L1148, S1L2314, F1_data_out, S1_E_iw[4], S1_W_stall);

--S1_M_st_data[29] is std_1c20:inst|cpu:the_cpu|M_st_data[29] at LC_X43_Y18_N3

--operation mode is normal

S1_M_st_data[29] = AMPP_FUNCTION(QC2__clk0, S1L1155, S1L2309, S1L1147, S1_E_iw[3], F1_data_out, S1_E_iw[4], S1_W_stall);

--S1_M_st_data[28] is std_1c20:inst|cpu:the_cpu|M_st_data[28] at LC_X42_Y15_N8

--operation mode is normal

S1_M_st_data[28] = AMPP_FUNCTION(QC2__clk0, S1L1154, S1_E_iw[3], S1L1146, S1L2303, F1_data_out, S1_E_iw[4], S1_W_stall);

--S1_M_st_data[27] is std_1c20:inst|cpu:the_cpu|M_st_data[27] at LC_X42_Y15_N3

--operation mode is normal

S1_M_st_data[27] = AMPP_FUNCTION(QC2__clk0, S1L1153, S1_E_iw[3], S1L1145, S1L2296, F1_data_out, S1_E_iw[4], S1_W_stall);

--S1_M_st_data[26] is std_1c20:inst|cpu:the_cpu|M_st_data[26] at LC_X37_Y15_N4

--operation mode is normal

S1_M_st_data[26] = AMPP_FUNCTION(QC2__clk0, S1_E_iw[3], S1L2290, S1L1144, S1L1152, F1_data_out, S1_E_iw[4], S1_W_stall);

--S1_M_st_data[25] is std_1c20:inst|cpu:the_cpu|M_st_data[25] at LC_X42_Y18_N4

--operation mode is normal

S1_M_st_data[25] = AMPP_FUNCTION(QC2__clk0, S1L2283, S1L1151, S1L1143, S1_E_iw[3], F1_data_out, S1_E_iw[4], S1_W_stall);

--S1_M_st_data[24] is std_1c20:inst|cpu:the_cpu|M_st_data[24] at LC_X42_Y15_N9

--operation mode is normal

S1_M_st_data[24] = AMPP_FUNCTION(QC2__clk0, S1L2277, S1_E_iw[3], S1L1142, S1L1150, F1_data_out, S1_E_iw[4], S1_W_stall);

--T1L433 is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|Equal1~40 at LC_X26_Y29_N4

--operation mode is normal

T1L433 = T1_internal_cpu_data_master_dbs_address[1] # T1_internal_cpu_data_master_dbs_address[0];

--Y1L995 is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|outgoing_ext_ram_bus_data[31]~2895 at LC_X23_Y29_N3

--operation mode is normal

Y1L995 = Y1L100 & !Y1L739 & (Y1L37 # Y1L34);

--Y1L987 is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|outgoing_ext_ram_bus_data[4]~2903 at LC_X24_Y29_N8

--operation mode is normal

Y1L987 = T1_internal_cpu_data_master_dbs_address[1] & (T1_internal_cpu_data_master_dbs_address[0] & S1_M_st_data[28] # !T1_internal_cpu_data_master_dbs_address[0] & (S1L2345Q)) # !T1_internal_cpu_data_master_dbs_address[1] & S1_M_st_data[28] & !T1_internal_cpu_data_master_dbs_address[0];

--Y1L988 is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|outgoing_ext_ram_bus_data[4]~2904 at LC_X25_Y29_N8

--operation mode is normal

Y1L988 = Y1L987 # !T1_internal_cpu_data_master_dbs_address[1] & T1_internal_cpu_data_master_dbs_address[0] & S1L2301Q;

--Y1L985 is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|outgoing_ext_ram_bus_data[3]~2906 at LC_X25_Y27_N9

--operation mode is normal

Y1L985 = T1_internal_cpu_data_master_dbs_address[0] & (T1_internal_cpu_data_master_dbs_address[1] & S1_M_st_data[27]) # !T1_internal_cpu_data_master_dbs_address[0] & (T1_internal_cpu_data_master_dbs_address[1] & S1L2340Q # !T1_internal_cpu_data_master_dbs_address[1] & (S1_M_st_data[27]));

--Y1L986 is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|outgoing_ext_ram_bus_data[3]~2907 at LC_X25_Y29_N0

--operation mode is normal

Y1L986 = Y1L985 # !T1_internal_cpu_data_master_dbs_address[1] & T1_internal_cpu_data_master_dbs_address[0] & S1L2294Q;

--Y1L983 is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|outgoing_ext_ram_bus_data[2]~2909 at LC_X25_Y27_N7

--operation mode is normal

Y1L983 = T1_internal_cpu_data_master_dbs_address[1] & (T1_internal_cpu_data_master_dbs_address[0] & S1_M_st_data[26] # !T1_internal_cpu_data_master_dbs_address[0] & (S1L2335Q)) # !T1_internal_cpu_data_master_dbs_address[1] & !T1_internal_cpu_data_master_dbs_address[0] & S1_M_st_data[26];

--Y1L984 is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|outgoing_ext_ram_bus_data[2]~2910 at LC_X25_Y27_N8

--operation mode is normal

Y1L984 = Y1L983 # !T1_internal_cpu_data_master_dbs_address[1] & S1L2288Q & T1_internal_cpu_data_master_dbs_address[0];

--Y1L981 is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|outgoing_ext_ram_bus_data[1]~2912 at LC_X25_Y27_N1

--operation mode is normal

Y1L981 = T1_internal_cpu_data_master_dbs_address[0] & S1_M_st_data[25] & T1_internal_cpu_data_master_dbs_address[1] # !T1_internal_cpu_data_master_dbs_address[0] & (T1_internal_cpu_data_master_dbs_address[1] & (S1L2330Q) # !T1_internal_cpu_data_master_dbs_address[1] & S1_M_st_data[25]);

--Y1L982 is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|outgoing_ext_ram_bus_data[1]~2913 at LC_X24_Y29_N9

--operation mode is normal

Y1L982 = Y1L981 # T1_internal_cpu_data_master_dbs_address[0] & !T1_internal_cpu_data_master_dbs_address[1] & S1L2281Q;

--Y1L979 is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|outgoing_ext_ram_bus_data[0]~2915 at LC_X25_Y27_N2

--operation mode is normal

Y1L979 = T1_internal_cpu_data_master_dbs_address[1] & (T1_internal_cpu_data_master_dbs_address[0] & (S1_M_st_data[24]) # !T1_internal_cpu_data_master_dbs_address[0] & S1L2325Q) # !T1_internal_cpu_data_master_dbs_address[1] & !T1_internal_cpu_data_master_dbs_address[0] & (S1_M_st_data[24]);

--Y1L980 is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|outgoing_ext_ram_bus_data[0]~2916 at LC_X25_Y27_N3

--operation mode is normal

Y1L980 = Y1L979 # !T1_internal_cpu_data_master_dbs_address[1] & T1_internal_cpu_data_master_dbs_address[0] & S1L2275Q;

--KB1_active_data[31] is std_1c20:inst|sdram:the_sdram|active_data[31] at LC_X13_Y15_N7

--operation mode is normal

KB1_active_data[31]_lut_out = KB1L12 & (KB1L14 & TE1L185 # !KB1L14 & (KB1_active_data[31])) # !KB1L12 & (KB1_active_data[31]);

KB1_active_data[31] = DFFEAS(KB1_active_data[31]_lut_out, GLOBAL(QC2__clk0), VCC, , , , , , );

--TE1_entry_0[31] is std_1c20:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_0[31] at LC_X24_Y17_N5

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

TE1_entry_0[31]_lut_out = GND;

TE1_entry_0[31] = DFFEAS(TE1_entry_0[31]_lut_out, GLOBAL(QC2__clk0), VCC, , TE1L84, S1_M_st_data[31], , , VCC);

--TE1L185 is std_1c20:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|rd_data[31]~510 at LC_X24_Y17_N7

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

TE1_entry_1[31]_qfbk = TE1_entry_1[31];

TE1L185 = TE1_rd_address & (TE1_entry_1[31]_qfbk) # !TE1_rd_address & TE1_entry_0[31];

--TE1_entry_1[31] is std_1c20:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_1[31] at LC_X24_Y17_N7

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

TE1_entry_1[31] = DFFEAS(TE1L185, GLOBAL(QC2__clk0), VCC, , TE1L148, S1_M_st_data[31], , , VCC);

--KB1L946 is std_1c20:inst|sdram:the_sdram|Mux118~1218 at LC_X13_Y15_N4

--operation mode is normal

KB1L946 = KB1_m_state[1] & KB1_active_data[31] # !KB1_m_state[1] & (KB1_f_select & (TE1L185) # !KB1_f_select & KB1_active_data[31]);

--KB1L947 is std_1c20:inst|sdram:the_sdram|Mux118~1219 at LC_X15_Y18_N2

--operation mode is normal

KB1L947 = !KB1_m_state[3] & (KB1_m_state[4] $ KB1_m_state[1]);

--KB1L985 is std_1c20:inst|sdram:the_sdram|Mux154~549 at LC_X12_Y22_N9

--operation mode is normal

KB1L985 = KB1_m_state[4] & !KB1_m_state[3] & KB1L538;

--KB1_active_data[30] is std_1c20:inst|sdram:the_sdram|active_data[30] at LC_X16_Y17_N5

--operation mode is normal

KB1_active_data[30]_lut_out = KB1L66 & (KB1L65 & TE1L184 # !KB1L65 & (KB1_active_data[30])) # !KB1L66 & (KB1_active_data[30]);

KB1_active_data[30] = DFFEAS(KB1_active_data[30]_lut_out, GLOBAL(QC2__clk0), VCC, , , , , , );

--TE1_entry_0[30] is std_1c20:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_0[30] at LC_X21_Y18_N5

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

TE1_entry_0[30]_lut_out = GND;

TE1_entry_0[30] = DFFEAS(TE1_entry_0[30]_lut_out, GLOBAL(QC2__clk0), VCC, , TE1L84, S1_M_st_data[30], , , VCC);

--TE1L184 is std_1c20:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|rd_data[30]~511 at LC_X21_Y18_N2

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

TE1_entry_1[30]_qfbk = TE1_entry_1[30];

TE1L184 = TE1_rd_address & TE1_entry_1[30]_qfbk # !TE1_rd_address & (TE1_entry_0[30]);

--TE1_entry_1[30] is std_1c20:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_1[30] at LC_X21_Y18_N2

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

TE1_entry_1[30] = DFFEAS(TE1L184, GLOBAL(QC2__clk0), VCC, , TE1L148, S1_M_st_data[30], , , VCC);

--KB1L949 is std_1c20:inst|sdram:the_sdram|Mux119~1170 at LC_X16_Y17_N7

--operation mode is normal

KB1L949 = KB1_m_state[1] & (KB1_active_data[30]) # !KB1_m_state[1] & (KB1_f_select & TE1L184 # !KB1_f_select & (KB1_active_data[30]));

--KB1_active_data[29] is std_1c20:inst|sdram:the_sdram|active_data[29] at LC_X17_Y14_N3

--operation mode is normal

KB1_active_data[29]_lut_out = KB1L12 & (KB1L14 & TE1L183 # !KB1L14 & (KB1_active_data[29])) # !KB1L12 & (KB1_active_data[29]);

KB1_active_data[29] = DFFEAS(KB1_active_data[29]_lut_out, GLOBAL(QC2__clk0), VCC, , , , , , );

--TE1_entry_0[29] is std_1c20:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_0[29] at LC_X25_Y22_N6

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

TE1_entry_0[29]_lut_out = GND;

TE1_entry_0[29] = DFFEAS(TE1_entry_0[29]_lut_out, GLOBAL(QC2__clk0), VCC, , TE1L84, S1_M_st_data[29], , , VCC);

--TE1L183 is std_1c20:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|rd_data[29]~512 at LC_X25_Y22_N9

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

TE1_entry_1[29]_qfbk = TE1_entry_1[29];

TE1L183 = TE1_rd_address & TE1_entry_1[29]_qfbk # !TE1_rd_address & (TE1_entry_0[29]);

--TE1_entry_1[29] is std_1c20:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_1[29] at LC_X25_Y22_N9

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

TE1_entry_1[29] = DFFEAS(TE1L183, GLOBAL(QC2__clk0), VCC, , TE1L148, S1_M_st_data[29], , , VCC);

--KB1L950 is std_1c20:inst|sdram:the_sdram|Mux120~1170 at LC_X17_Y14_N1

--operation mode is normal

KB1L950 = KB1_m_state[1] & KB1_active_data[29] # !KB1_m_state[1] & (KB1_f_select & (TE1L183) # !KB1_f_select & KB1_active_data[29]);

--KB1_active_data[28] is std_1c20:inst|sdram:the_sdram|active_data[28] at LC_X16_Y16_N9

--operation mode is normal

KB1_active_data[28]_lut_out = KB1L66 & (KB1L65 & (TE1L182) # !KB1L65 & KB1_active_data[28]) # !KB1L66 & KB1_active_data[28];

KB1_active_data[28] = DFFEAS(KB1_active_data[28]_lut_out, GLOBAL(QC2__clk0), VCC, , , , , , );

--TE1_entry_0[28] is std_1c20:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_0[28] at LC_X23_Y15_N0

--operation mode is normal

TE1_entry_0[28]_lut_out = S1_M_st_data[28];

TE1_entry_0[28] = DFFEAS(TE1_entry_0[28]_lut_out, GLOBAL(QC2__clk0), VCC, , TE1L84, , , , );

--TE1L182 is std_1c20:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|rd_data[28]~513 at LC_X23_Y15_N5

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

TE1_entry_1[28]_qfbk = TE1_entry_1[28];

TE1L182 = TE1_rd_address & (TE1_entry_1[28]_qfbk) # !TE1_rd_address & TE1_entry_0[28];

--TE1_entry_1[28] is std_1c20:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_1[28] at LC_X23_Y15_N5

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

TE1_entry_1[28] = DFFEAS(TE1L182, GLOBAL(QC2__clk0), VCC, , TE1L148, S1_M_st_data[28], , , VCC);

--KB1L951 is std_1c20:inst|sdram:the_sdram|Mux121~1170 at LC_X16_Y16_N5

--operation mode is normal

KB1L951 = KB1_m_state[1] & KB1_active_data[28] # !KB1_m_state[1] & (KB1_f_select & (TE1L182) # !KB1_f_select & KB1_active_data[28]);

--KB1_active_data[27] is std_1c20:inst|sdram:the_sdram|active_data[27] at LC_X13_Y14_N4

--operation mode is normal

KB1_active_data[27]_lut_out = KB1L12 & (KB1L14 & TE1L181 # !KB1L14 & (KB1_active_data[27])) # !KB1L12 & (KB1_active_data[27]);

KB1_active_data[27] = DFFEAS(KB1_active_data[27]_lut_out, GLOBAL(QC2__clk0), VCC, , , , , , );

--TE1_entry_0[27] is std_1c20:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_0[27] at LC_X24_Y16_N5

--operation mode is normal

TE1_entry_0[27]_lut_out = S1_M_st_data[27];

TE1_entry_0[27] = DFFEAS(TE1_entry_0[27]_lut_out, GLOBAL(QC2__clk0), VCC, , TE1L84, , , , );

--TE1L181 is std_1c20:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|rd_data[27]~514 at LC_X24_Y16_N8

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

TE1_entry_1[27]_qfbk = TE1_entry_1[27];

TE1L181 = TE1_rd_address & TE1_entry_1[27]_qfbk # !TE1_rd_address & (TE1_entry_0[27]);

--TE1_entry_1[27] is std_1c20:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_1[27] at LC_X24_Y16_N8

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

TE1_entry_1[27] = DFFEAS(TE1L181, GLOBAL(QC2__clk0), VCC, , TE1L148, S1_M_st_data[27], , , VCC);

--KB1L952 is std_1c20:inst|sdram:the_sdram|Mux122~1170 at LC_X13_Y14_N1

--operation mode is normal

KB1L952 = KB1_m_state[1] & (KB1_active_data[27]) # !KB1_m_state[1] & (KB1_f_select & TE1L181 # !KB1_f_select & (KB1_active_data[27]));

--KB1_active_data[26] is std_1c20:inst|sdram:the_sdram|active_data[26] at LC_X16_Y15_N5

--operation mode is normal

KB1_active_data[26]_lut_out = KB1L66 & (KB1L65 & (TE1L180) # !KB1L65 & KB1_active_data[26]) # !KB1L66 & KB1_active_data[26];

KB1_active_data[26] = DFFEAS(KB1_active_data[26]_lut_out, GLOBAL(QC2__clk0), VCC, , , , , , );

--TE1_entry_0[26] is std_1c20:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_0[26] at LC_X24_Y16_N6

--operation mode is normal

TE1_entry_0[26]_lut_out = S1_M_st_data[26];

TE1_entry_0[26] = DFFEAS(TE1_entry_0[26]_lut_out, GLOBAL(QC2__clk0), VCC, , TE1L84, , , , );

--TE1L180 is std_1c20:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|rd_data[26]~515 at LC_X24_Y16_N7

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

TE1_entry_1[26]_qfbk = TE1_entry_1[26];

TE1L180 = TE1_rd_address & TE1_entry_1[26]_qfbk # !TE1_rd_address & (TE1_entry_0[26]);

--TE1_entry_1[26] is std_1c20:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_1[26] at LC_X24_Y16_N7

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

TE1_entry_1[26] = DFFEAS(TE1L180, GLOBAL(QC2__clk0), VCC, , TE1L148, S1_M_st_data[26], , , VCC);

--KB1L953 is std_1c20:inst|sdram:the_sdram|Mux123~1170 at LC_X16_Y15_N1

--operation mode is normal

KB1L953 = KB1_m_state[1] & KB1_active_data[26] # !KB1_m_state[1] & (KB1_f_select & (TE1L180) # !KB1_f_select & KB1_active_data[26]);

--KB1_active_data[25] is std_1c20:inst|sdram:the_sdram|active_data[25] at LC_X13_Y17_N5

--operation mode is normal

KB1_active_data[25]_lut_out = KB1L14 & (KB1L12 & TE1L179 # !KB1L12 & (KB1_active_data[25])) # !KB1L14 & (KB1_active_data[25]);

KB1_active_data[25] = DFFEAS(KB1_active_data[25]_lut_out, GLOBAL(QC2__clk0), VCC, , , , , , );

--TE1_entry_0[25] is std_1c20:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_0[25] at LC_X24_Y17_N0

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

TE1_entry_0[25]_lut_out = GND;

TE1_entry_0[25] = DFFEAS(TE1_entry_0[25]_lut_out, GLOBAL(QC2__clk0), VCC, , TE1L84, S1_M_st_data[25], , , VCC);

--TE1L179 is std_1c20:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|rd_data[25]~516 at LC_X24_Y17_N6

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

TE1_entry_1[25]_qfbk = TE1_entry_1[25];

TE1L179 = TE1_rd_address & (TE1_entry_1[25]_qfbk) # !TE1_rd_address & TE1_entry_0[25];

--TE1_entry_1[25] is std_1c20:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_1[25] at LC_X24_Y17_N6

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

TE1_entry_1[25] = DFFEAS(TE1L179, GLOBAL(QC2__clk0), VCC, , TE1L148, S1_M_st_data[25], , , VCC);

--KB1L954 is std_1c20:inst|sdram:the_sdram|Mux124~1170 at LC_X13_Y17_N3

--operation mode is normal

KB1L954 = KB1_m_state[1] & (KB1_active_data[25]) # !KB1_m_state[1] & (KB1_f_select & TE1L179 # !KB1_f_select & (KB1_active_data[25]));

--KB1_active_data[24] is std_1c20:inst|sdram:the_sdram|active_data[24] at LC_X18_Y15_N2

--operation mode is normal

KB1_active_data[24]_lut_out = KB1L66 & (KB1L65 & TE1L178 # !KB1L65 & (KB1_active_data[24])) # !KB1L66 & (KB1_active_data[24]);

KB1_active_data[24] = DFFEAS(KB1_active_data[24]_lut_out, GLOBAL(QC2__clk0), VCC, , , , , , );

--TE1_entry_0[24] is std_1c20:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_0[24] at LC_X24_Y15_N5

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

TE1_entry_0[24]_lut_out = GND;

TE1_entry_0[24] = DFFEAS(TE1_entry_0[24]_lut_out, GLOBAL(QC2__clk0), VCC, , TE1L84, S1_M_st_data[24], , , VCC);

--TE1L178 is std_1c20:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|rd_data[24]~517 at LC_X24_Y15_N6

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

TE1_entry_1[24]_qfbk = TE1_entry_1[24];

TE1L178 = TE1_rd_address & (TE1_entry_1[24]_qfbk) # !TE1_rd_address & TE1_entry_0[24];

--TE1_entry_1[24] is std_1c20:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_1[24] at LC_X24_Y15_N6

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

TE1_entry_1[24] = DFFEAS(TE1L178, GLOBAL(QC2__clk0), VCC, , TE1L148, S1_M_st_data[24], , , VCC);

--KB1L955 is std_1c20:inst|sdram:the_sdram|Mux125~1170 at LC_X18_Y15_N6

--operation mode is normal

KB1L955 = KB1_m_state[1] & KB1_active_data[24] # !KB1_m_state[1] & (KB1_f_select & (TE1L178) # !KB1_f_select & KB1_active_data[24]);

--KB1_active_data[23] is std_1c20:inst|sdram:the_sdram|active_data[23] at LC_X13_Y16_N5

--operation mode is normal

KB1_active_data[23]_lut_out = KB1L12 & (KB1L14 & (TE1L177) # !KB1L14 & KB1_active_data[23]) # !KB1L12 & KB1_active_data[23];

KB1_active_data[23] = DFFEAS(KB1_active_data[23]_lut_out, GLOBAL(QC2__clk0), VCC, , , , , , );

--TE1_entry_0[23] is std_1c20:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_0[23] at LC_X24_Y16_N2

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

TE1_entry_0[23]_lut_out = GND;

TE1_entry_0[23] = DFFEAS(TE1_entry_0[23]_lut_out, GLOBAL(QC2__clk0), VCC, , TE1L84, S1L2360Q, , , VCC);

--TE1L177 is std_1c20:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|rd_data[23]~518 at LC_X24_Y16_N4

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

TE1_entry_1[23]_qfbk = TE1_entry_1[23];

TE1L177 = TE1_rd_address & (TE1_entry_1[23]_qfbk) # !TE1_rd_address & TE1_entry_0[23];

--TE1_entry_1[23] is std_1c20:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_1[23] at LC_X24_Y16_N4

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

TE1_entry_1[23] = DFFEAS(TE1L177, GLOBAL(QC2__clk0), VCC, , TE1L148, S1L2360Q, , , VCC);

--KB1L956 is std_1c20:inst|sdram:the_sdram|Mux126~1170 at LC_X13_Y16_N1

--operation mode is normal

KB1L956 = KB1_m_state[1] & KB1_active_data[23] # !KB1_m_state[1] & (KB1_f_select & (TE1L177) # !KB1_f_select & KB1_active_data[23]);

--KB1_active_data[22] is std_1c20:inst|sdram:the_sdram|active_data[22] at LC_X16_Y16_N2

--operation mode is normal

KB1_active_data[22]_lut_out = KB1L66 & (KB1L65 & (TE1L176) # !KB1L65 & KB1_active_data[22]) # !KB1L66 & KB1_active_data[22];

KB1_active_data[22] = DFFEAS(KB1_active_data[22]_lut_out, GLOBAL(QC2__clk0), VCC, , , , , , );

--TE1_entry_0[22] is std_1c20:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_0[22] at LC_X23_Y16_N5

--operation mode is normal

TE1_entry_0[22]_lut_out = S1L2355Q;

TE1_entry_0[22] = DFFEAS(TE1_entry_0[22]_lut_out, GLOBAL(QC2__clk0), VCC, , TE1L84, , , , );

--TE1L176 is std_1c20:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|rd_data[22]~519 at LC_X23_Y16_N2

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

TE1_entry_1[22]_qfbk = TE1_entry_1[22];

TE1L176 = TE1_rd_address & (TE1_entry_1[22]_qfbk) # !TE1_rd_address & TE1_entry_0[22];

--TE1_entry_1[22] is std_1c20:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_1[22] at LC_X23_Y16_N2

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

TE1_entry_1[22] = DFFEAS(TE1L176, GLOBAL(QC2__clk0), VCC, , TE1L148, S1L2355Q, , , VCC);

--KB1L957 is std_1c20:inst|sdram:the_sdram|Mux127~1170 at LC_X16_Y16_N3

--operation mode is normal

KB1L957 = KB1_m_state[1] & KB1_active_data[22] # !KB1_m_state[1] & (KB1_f_select & (TE1L176) # !KB1_f_select & KB1_active_data[22]);

--KB1_active_data[21] is std_1c20:inst|sdram:the_sdram|active_data[21] at LC_X13_Y14_N6

--operation mode is normal

KB1_active_data[21]_lut_out = KB1L12 & (KB1L14 & (TE1L175) # !KB1L14 & KB1_active_data[21]) # !KB1L12 & KB1_active_data[21];

KB1_active_data[21] = DFFEAS(KB1_active_data[21]_lut_out, GLOBAL(QC2__clk0), VCC, , , , , , );

--TE1_entry_0[21] is std_1c20:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_0[21] at LC_X24_Y16_N0

--operation mode is normal

TE1_entry_0[21]_lut_out = S1L2350Q;

TE1_entry_0[21] = DFFEAS(TE1_entry_0[21]_lut_out, GLOBAL(QC2__clk0), VCC, , TE1L84, , , , );

--TE1L175 is std_1c20:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|rd_data[21]~520 at LC_X24_Y16_N1

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

TE1_entry_1[21]_qfbk = TE1_entry_1[21];

TE1L175 = TE1_rd_address & TE1_entry_1[21]_qfbk # !TE1_rd_address & (TE1_entry_0[21]);

--TE1_entry_1[21] is std_1c20:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_1[21] at LC_X24_Y16_N1

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

TE1_entry_1[21] = DFFEAS(TE1L175, GLOBAL(QC2__clk0), VCC, , TE1L148, S1L2350Q, , , VCC);

--KB1L958 is std_1c20:inst|sdram:the_sdram|Mux128~1170 at LC_X13_Y14_N8

--operation mode is normal

KB1L958 = KB1_m_state[1] & KB1_active_data[21] # !KB1_m_state[1] & (KB1_f_select & (TE1L175) # !KB1_f_select & KB1_active_data[21]);

--KB1_active_data[20] is std_1c20:inst|sdram:the_sdram|active_data[20] at LC_X16_Y15_N4

--operation mode is normal

KB1_active_data[20]_lut_out = KB1L65 & (KB1L66 & TE1L174 # !KB1L66 & (KB1_active_data[20])) # !KB1L65 & (KB1_active_data[20]);

KB1_active_data[20] = DFFEAS(KB1_active_data[20]_lut_out, GLOBAL(QC2__clk0), VCC, , , , , , );

--TE1_entry_0[20] is std_1c20:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_0[20] at LC_X24_Y15_N0

--operation mode is normal

TE1_entry_0[20]_lut_out = S1L2345Q;

TE1_entry_0[20] = DFFEAS(TE1_entry_0[20]_lut_out, GLOBAL(QC2__clk0), VCC, , TE1L84, , , , );

--TE1L174 is std_1c20:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|rd_data[20]~521 at LC_X24_Y15_N4

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

TE1_entry_1[20]_qfbk = TE1_entry_1[20];

TE1L174 = TE1_rd_address & (TE1_entry_1[20]_qfbk) # !TE1_rd_address & TE1_entry_0[20];

--TE1_entry_1[20] is std_1c20:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_1[20] at LC_X24_Y15_N4

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

TE1_entry_1[20] = DFFEAS(TE1L174, GLOBAL(QC2__clk0), VCC, , TE1L148, S1L2345Q, , , VCC);

--KB1L959 is std_1c20:inst|sdram:the_sdram|Mux129~1170 at LC_X16_Y15_N8

--operation mode is normal

KB1L959 = KB1_m_state[1] & KB1_active_data[20] # !KB1_m_state[1] & (KB1_f_select & (TE1L174) # !KB1_f_select & KB1_active_data[20]);

--KB1_active_data[19] is std_1c20:inst|sdram:the_sdram|active_data[19] at LC_X13_Y17_N9

--operation mode is normal

KB1_active_data[19]_lut_out = KB1L12 & (KB1L14 & TE1L173 # !KB1L14 & (KB1_active_data[19])) # !KB1L12 & (KB1_active_data[19]);

KB1_active_data[19] = DFFEAS(KB1_active_data[19]_lut_out, GLOBAL(QC2__clk0), VCC, , , , , , );

--TE1_entry_0[19] is std_1c20:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_0[19] at LC_X21_Y19_N3

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

TE1_entry_0[19]_lut_out = GND;

TE1_entry_0[19] = DFFEAS(TE1_entry_0[19]_lut_out, GLOBAL(QC2__clk0), VCC, , TE1L84, S1L2340Q, , , VCC);

--TE1L173 is std_1c20:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|rd_data[19]~522 at LC_X21_Y19_N2

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

TE1_entry_1[19]_qfbk = TE1_entry_1[19];

TE1L173 = TE1_rd_address & TE1_entry_1[19]_qfbk # !TE1_rd_address & (TE1_entry_0[19]);

--TE1_entry_1[19] is std_1c20:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_1[19] at LC_X21_Y19_N2

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

TE1_entry_1[19] = DFFEAS(TE1L173, GLOBAL(QC2__clk0), VCC, , TE1L148, S1L2340Q, , , VCC);

--KB1L960 is std_1c20:inst|sdram:the_sdram|Mux130~1170 at LC_X13_Y17_N7

--operation mode is normal

KB1L960 = KB1_m_state[1] & (KB1_active_data[19]) # !KB1_m_state[1] & (KB1_f_select & TE1L173 # !KB1_f_select & (KB1_active_data[19]));

--KB1_active_data[18] is std_1c20:inst|sdram:the_sdram|active_data[18] at LC_X17_Y17_N4

--operation mode is normal

KB1_active_data[18]_lut_out = KB1L65 & (KB1L66 & TE1L172 # !KB1L66 & (KB1_active_data[18])) # !KB1L65 & (KB1_active_data[18]);

KB1_active_data[18] = DFFEAS(KB1_active_data[18]_lut_out, GLOBAL(QC2__clk0), VCC, , , , , , );

--TE1_entry_0[18] is std_1c20:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_0[18] at LC_X24_Y17_N4

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

TE1_entry_0[18]_lut_out = GND;

TE1_entry_0[18] = DFFEAS(TE1_entry_0[18]_lut_out, GLOBAL(QC2__clk0), VCC, , TE1L84, S1L2335Q, , , VCC);

--TE1L172 is std_1c20:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|rd_data[18]~523 at LC_X24_Y17_N9

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

TE1_entry_1[18]_qfbk = TE1_entry_1[18];

TE1L172 = TE1_rd_address & (TE1_entry_1[18]_qfbk) # !TE1_rd_address & TE1_entry_0[18];

--TE1_entry_1[18] is std_1c20:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_1[18] at LC_X24_Y17_N9

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

TE1_entry_1[18] = DFFEAS(TE1L172, GLOBAL(QC2__clk0), VCC, , TE1L148, S1L2335Q, , , VCC);

--KB1L961 is std_1c20:inst|sdram:the_sdram|Mux131~1170 at LC_X17_Y16_N5

--operation mode is normal

KB1L961 = KB1_m_state[1] & KB1_active_data[18] # !KB1_m_state[1] & (KB1_f_select & (TE1L172) # !KB1_f_select & KB1_active_data[18]);

--KB1_active_data[17] is std_1c20:inst|sdram:the_sdram|active_data[17] at LC_X17_Y14_N7

--operation mode is normal

KB1_active_data[17]_lut_out = KB1L12 & (KB1L14 & (TE1L171) # !KB1L14 & KB1_active_data[17]) # !KB1L12 & KB1_active_data[17];

KB1_active_data[17] = DFFEAS(KB1_active_data[17]_lut_out, GLOBAL(QC2__clk0), VCC, , , , , , );

--TE1_entry_0[17] is std_1c20:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_0[17] at LC_X24_Y17_N8

--operation mode is normal

TE1_entry_0[17]_lut_out = S1L2330Q;

TE1_entry_0[17] = DFFEAS(TE1_entry_0[17]_lut_out, GLOBAL(QC2__clk0), VCC, , TE1L84, , , , );

--TE1L171 is std_1c20:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|rd_data[17]~524 at LC_X24_Y17_N1

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

TE1_entry_1[17]_qfbk = TE1_entry_1[17];

TE1L171 = TE1_rd_address & (TE1_entry_1[17]_qfbk) # !TE1_rd_address & TE1_entry_0[17];

--TE1_entry_1[17] is std_1c20:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_1[17] at LC_X24_Y17_N1

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

TE1_entry_1[17] = DFFEAS(TE1L171, GLOBAL(QC2__clk0), VCC, , TE1L148, S1L2330Q, , , VCC);

--KB1L962 is std_1c20:inst|sdram:the_sdram|Mux132~1170 at LC_X17_Y14_N8

--operation mode is normal

KB1L962 = KB1_m_state[1] & (KB1_active_data[17]) # !KB1_m_state[1] & (KB1_f_select & TE1L171 # !KB1_f_select & (KB1_active_data[17]));

--KB1_active_data[16] is std_1c20:inst|sdram:the_sdram|active_data[16] at LC_X17_Y16_N2

--operation mode is normal

KB1_active_data[16]_lut_out = KB1L66 & (KB1L65 & (TE1L170) # !KB1L65 & KB1_active_data[16]) # !KB1L66 & KB1_active_data[16];

KB1_active_data[16] = DFFEAS(KB1_active_data[16]_lut_out, GLOBAL(QC2__clk0), VCC, , , , , , );

--TE1_entry_0[16] is std_1c20:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_0[16] at LC_X23_Y16_N0

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

TE1_entry_0[16]_lut_out = GND;

TE1_entry_0[16] = DFFEAS(TE1_entry_0[16]_lut_out, GLOBAL(QC2__clk0), VCC, , TE1L84, S1L2325Q, , , VCC);

--TE1L170 is std_1c20:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|rd_data[16]~525 at LC_X23_Y16_N7

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

TE1_entry_1[16]_qfbk = TE1_entry_1[16];

TE1L170 = TE1_rd_address & (TE1_entry_1[16]_qfbk) # !TE1_rd_address & TE1_entry_0[16];

--TE1_entry_1[16] is std_1c20:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_1[16] at LC_X23_Y16_N7

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

TE1_entry_1[16] = DFFEAS(TE1L170, GLOBAL(QC2__clk0), VCC, , TE1L148, S1L2325Q, , , VCC);

--KB1L963 is std_1c20:inst|sdram:the_sdram|Mux133~1170 at LC_X17_Y16_N3

--operation mode is normal

KB1L963 = KB1_m_state[1] & KB1_active_data[16] # !KB1_m_state[1] & (KB1_f_select & (TE1L170) # !KB1_f_select & KB1_active_data[16]);

--KB1_active_data[15] is std_1c20:inst|sdram:the_sdram|active_data[15] at LC_X16_Y18_N5

--operation mode is normal

KB1_active_data[15]_lut_out = KB1L14 & (KB1L12 & (TE1L169) # !KB1L12 & KB1_active_data[15]) # !KB1L14 & KB1_active_data[15];

KB1_active_data[15] = DFFEAS(KB1_active_data[15]_lut_out, GLOBAL(QC2__clk0), VCC, , , , , , );

--TE1_entry_0[15] is std_1c20:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_0[15] at LC_X21_Y18_N3

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

TE1_entry_0[15]_lut_out = GND;

TE1_entry_0[15] = DFFEAS(TE1_entry_0[15]_lut_out, GLOBAL(QC2__clk0), VCC, , TE1L84, S1L2319Q, , , VCC);

--TE1L169 is std_1c20:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|rd_data[15]~526 at LC_X21_Y18_N4

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

TE1_entry_1[15]_qfbk = TE1_entry_1[15];

TE1L169 = TE1_rd_address & TE1_entry_1[15]_qfbk # !TE1_rd_address & (TE1_entry_0[15]);

--TE1_entry_1[15] is std_1c20:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_1[15] at LC_X21_Y18_N4

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

TE1_entry_1[15] = DFFEAS(TE1L169, GLOBAL(QC2__clk0), VCC, , TE1L148, S1L2319Q, , , VCC);

--KB1L964 is std_1c20:inst|sdram:the_sdram|Mux134~1170 at LC_X16_Y18_N1

--operation mode is normal

KB1L964 = KB1_m_state[1] & KB1_active_data[15] # !KB1_m_state[1] & (KB1_f_select & (TE1L169) # !KB1_f_select & KB1_active_data[15]);

--KB1_active_data[14] is std_1c20:inst|sdram:the_sdram|active_data[14] at LC_X17_Y17_N5

--operation mode is normal

KB1_active_data[14]_lut_out = KB1L65 & (KB1L66 & TE1L168 # !KB1L66 & (KB1_active_data[14])) # !KB1L65 & (KB1_active_data[14]);

KB1_active_data[14] = DFFEAS(KB1_active_data[14]_lut_out, GLOBAL(QC2__clk0), VCC, , , , , , );

--TE1_entry_0[14] is std_1c20:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_0[14] at LC_X21_Y17_N5

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

TE1_entry_0[14]_lut_out = GND;

TE1_entry_0[14] = DFFEAS(TE1_entry_0[14]_lut_out, GLOBAL(QC2__clk0), VCC, , TE1L84, S1L2313Q, , , VCC);

--TE1L168 is std_1c20:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|rd_data[14]~527 at LC_X21_Y17_N2

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

TE1_entry_1[14]_qfbk = TE1_entry_1[14];

TE1L168 = TE1_rd_address & (TE1_entry_1[14]_qfbk) # !TE1_rd_address & TE1_entry_0[14];

--TE1_entry_1[14] is std_1c20:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_1[14] at LC_X21_Y17_N2

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

TE1_entry_1[14] = DFFEAS(TE1L168, GLOBAL(QC2__clk0), VCC, , TE1L148, S1L2313Q, , , VCC);

--KB1L965 is std_1c20:inst|sdram:the_sdram|Mux135~1170 at LC_X17_Y17_N6

--operation mode is normal

KB1L965 = KB1_m_state[1] & KB1_active_data[14] # !KB1_m_state[1] & (KB1_f_select & (TE1L168) # !KB1_f_select & KB1_active_data[14]);

--KB1_active_data[13] is std_1c20:inst|sdram:the_sdram|active_data[13] at LC_X13_Y15_N9

--operation mode is normal

KB1_active_data[13]_lut_out = KB1L12 & (KB1L14 & TE1L167 # !KB1L14 & (KB1_active_data[13])) # !KB1L12 & (KB1_active_data[13]);

KB1_active_data[13] = DFFEAS(KB1_active_data[13]_lut_out, GLOBAL(QC2__clk0), VCC, , , , , , );

--TE1_entry_0[13] is std_1c20:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_0[13] at LC_X25_Y22_N0

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

TE1_entry_0[13]_lut_out = GND;

TE1_entry_0[13] = DFFEAS(TE1_entry_0[13]_lut_out, GLOBAL(QC2__clk0), VCC, , TE1L84, S1L2307Q, , , VCC);

--TE1L167 is std_1c20:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|rd_data[13]~528 at LC_X25_Y22_N5

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

TE1_entry_1[13]_qfbk = TE1_entry_1[13];

TE1L167 = TE1_rd_address & TE1_entry_1[13]_qfbk # !TE1_rd_address & (TE1_entry_0[13]);

--TE1_entry_1[13] is std_1c20:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_1[13] at LC_X25_Y22_N5

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

TE1_entry_1[13] = DFFEAS(TE1L167, GLOBAL(QC2__clk0), VCC, , TE1L148, S1L2307Q, , , VCC);

--KB1L966 is std_1c20:inst|sdram:the_sdram|Mux136~1170 at LC_X13_Y15_N2

--operation mode is normal

KB1L966 = KB1_m_state[1] & KB1_active_data[13] # !KB1_m_state[1] & (KB1_f_select & (TE1L167) # !KB1_f_select & KB1_active_data[13]);

--KB1_active_data[12] is std_1c20:inst|sdram:the_sdram|active_data[12] at LC_X17_Y16_N9

--operation mode is normal

KB1_active_data[12]_lut_out = KB1L66 & (KB1L65 & (TE1L166) # !KB1L65 & KB1_active_data[12]) # !KB1L66 & KB1_active_data[12];

KB1_active_data[12] = DFFEAS(KB1_active_data[12]_lut_out, GLOBAL(QC2__clk0), VCC, , , , , , );

--TE1_entry_0[12] is std_1c20:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_0[12] at LC_X22_Y16_N3

--operation mode is normal

TE1_entry_0[12]_lut_out = S1L2301Q;

TE1_entry_0[12] = DFFEAS(TE1_entry_0[12]_lut_out, GLOBAL(QC2__clk0), VCC, , TE1L84, , , , );

--TE1L166 is std_1c20:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|rd_data[12]~529 at LC_X22_Y16_N2

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

TE1_entry_1[12]_qfbk = TE1_entry_1[12];

TE1L166 = TE1_rd_address & (TE1_entry_1[12]_qfbk) # !TE1_rd_address & TE1_entry_0[12];

--TE1_entry_1[12] is std_1c20:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_1[12] at LC_X22_Y16_N2

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

TE1_entry_1[12] = DFFEAS(TE1L166, GLOBAL(QC2__clk0), VCC, , TE1L148, S1L2301Q, , , VCC);

--KB1L967 is std_1c20:inst|sdram:the_sdram|Mux137~1170 at LC_X17_Y16_N7

--operation mode is normal

KB1L967 = KB1_m_state[1] & KB1_active_data[12] # !KB1_m_state[1] & (KB1_f_select & (TE1L166) # !KB1_f_select & KB1_active_data[12]);

--KB1_active_data[11] is std_1c20:inst|sdram:the_sdram|active_data[11] at LC_X17_Y14_N4

--operation mode is normal

KB1_active_data[11]_lut_out = KB1L14 & (KB1L12 & (TE1L165) # !KB1L12 & KB1_active_data[11]) # !KB1L14 & KB1_active_data[11];

KB1_active_data[11] = DFFEAS(KB1_active_data[11]_lut_out, GLOBAL(QC2__clk0), VCC, , , , , , );

--TE1_entry_0[11] is std_1c20:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_0[11] at LC_X21_Y15_N3

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

TE1_entry_0[11]_lut_out = GND;

TE1_entry_0[11] = DFFEAS(TE1_entry_0[11]_lut_out, GLOBAL(QC2__clk0), VCC, , TE1L84, S1L2294Q, , , VCC);

--TE1L165 is std_1c20:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|rd_data[11]~530 at LC_X21_Y15_N2

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

TE1_entry_1[11]_qfbk = TE1_entry_1[11];

TE1L165 = TE1_rd_address & (TE1_entry_1[11]_qfbk) # !TE1_rd_address & TE1_entry_0[11];

--TE1_entry_1[11] is std_1c20:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_1[11] at LC_X21_Y15_N2

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

TE1_entry_1[11] = DFFEAS(TE1L165, GLOBAL(QC2__clk0), VCC, , TE1L148, S1L2294Q, , , VCC);

--KB1L968 is std_1c20:inst|sdram:the_sdram|Mux138~1170 at LC_X17_Y14_N6

--operation mode is normal

KB1L968 = KB1_m_state[1] & KB1_active_data[11] # !KB1_m_state[1] & (KB1_f_select & (TE1L165) # !KB1_f_select & KB1_active_data[11]);

--KB1_active_data[10] is std_1c20:inst|sdram:the_sdram|active_data[10] at LC_X17_Y15_N5

--operation mode is normal

KB1_active_data[10]_lut_out = KB1L65 & (KB1L66 & TE1L164 # !KB1L66 & (KB1_active_data[10])) # !KB1L65 & (KB1_active_data[10]);

KB1_active_data[10] = DFFEAS(KB1_active_data[10]_lut_out, GLOBAL(QC2__clk0), VCC, , , , , , );

--TE1_entry_0[10] is std_1c20:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_0[10] at LC_X23_Y16_N8

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

TE1_entry_0[10]_lut_out = GND;

TE1_entry_0[10] = DFFEAS(TE1_entry_0[10]_lut_out, GLOBAL(QC2__clk0), VCC, , TE1L84, S1L2288Q, , , VCC);

--TE1L164 is std_1c20:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|rd_data[10]~531 at LC_X23_Y16_N1

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

TE1_entry_1[10]_qfbk = TE1_entry_1[10];

TE1L164 = TE1_rd_address & (TE1_entry_1[10]_qfbk) # !TE1_rd_address & TE1_entry_0[10];

--TE1_entry_1[10] is std_1c20:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_1[10] at LC_X23_Y16_N1

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

TE1_entry_1[10] = DFFEAS(TE1L164, GLOBAL(QC2__clk0), VCC, , TE1L148, S1L2288Q, , , VCC);

--KB1L969 is std_1c20:inst|sdram:the_sdram|Mux139~1170 at LC_X17_Y15_N6

--operation mode is normal

KB1L969 = KB1_m_state[1] & KB1_active_data[10] # !KB1_m_state[1] & (KB1_f_select & (TE1L164) # !KB1_f_select & KB1_active_data[10]);

--KB1_active_data[9] is std_1c20:inst|sdram:the_sdram|active_data[9] at LC_X16_Y18_N4

--operation mode is normal

KB1_active_data[9]_lut_out = KB1L14 & (KB1L12 & TE1L163 # !KB1L12 & (KB1_active_data[9])) # !KB1L14 & (KB1_active_data[9]);

KB1_active_data[9] = DFFEAS(KB1_active_data[9]_lut_out, GLOBAL(QC2__clk0), VCC, , , , , , );

--TE1_entry_0[9] is std_1c20:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_0[9] at LC_X23_Y18_N5

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

TE1_entry_0[9]_lut_out = GND;

TE1_entry_0[9] = DFFEAS(TE1_entry_0[9]_lut_out, GLOBAL(QC2__clk0), VCC, , TE1L84, S1L2281Q, , , VCC);

--TE1L163 is std_1c20:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|rd_data[9]~532 at LC_X23_Y18_N4

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

TE1_entry_1[9]_qfbk = TE1_entry_1[9];

TE1L163 = TE1_rd_address & (TE1_entry_1[9]_qfbk) # !TE1_rd_address & TE1_entry_0[9];

--TE1_entry_1[9] is std_1c20:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_1[9] at LC_X23_Y18_N4

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

TE1_entry_1[9] = DFFEAS(TE1L163, GLOBAL(QC2__clk0), VCC, , TE1L148, S1L2281Q, , , VCC);

--KB1L970 is std_1c20:inst|sdram:the_sdram|Mux140~1170 at LC_X16_Y18_N8

--operation mode is normal

KB1L970 = KB1_m_state[1] & KB1_active_data[9] # !KB1_m_state[1] & (KB1_f_select & (TE1L163) # !KB1_f_select & KB1_active_data[9]);

--KB1_active_data[8] is std_1c20:inst|sdram:the_sdram|active_data[8] at LC_X17_Y17_N2

--operation mode is normal

KB1_active_data[8]_lut_out = KB1L66 & (KB1L65 & TE1L162 # !KB1L65 & (KB1_active_data[8])) # !KB1L66 & (KB1_active_data[8]);

KB1_active_data[8] = DFFEAS(KB1_active_data[8]_lut_out, GLOBAL(QC2__clk0), VCC, , , , , , );

--TE1_entry_0[8] is std_1c20:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_0[8] at LC_X21_Y17_N4

--operation mode is normal

TE1_entry_0[8]_lut_out = S1L2275Q;

TE1_entry_0[8] = DFFEAS(TE1_entry_0[8]_lut_out, GLOBAL(QC2__clk0), VCC, , TE1L84, , , , );

--TE1L162 is std_1c20:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|rd_data[8]~533 at LC_X21_Y17_N6

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

TE1_entry_1[8]_qfbk = TE1_entry_1[8];

TE1L162 = TE1_rd_address & (TE1_entry_1[8]_qfbk) # !TE1_rd_address & TE1_entry_0[8];

--TE1_entry_1[8] is std_1c20:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_1[8] at LC_X21_Y17_N6

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

TE1_entry_1[8] = DFFEAS(TE1L162, GLOBAL(QC2__clk0), VCC, , TE1L148, S1L2275Q, , , VCC);

--KB1L971 is std_1c20:inst|sdram:the_sdram|Mux141~1170 at LC_X17_Y17_N8

--operation mode is normal

KB1L971 = KB1_m_state[1] & KB1_active_data[8] # !KB1_m_state[1] & (KB1_f_select & (TE1L162) # !KB1_f_select & KB1_active_data[8]);

--KB1_active_data[7] is std_1c20:inst|sdram:the_sdram|active_data[7] at LC_X14_Y15_N5

--operation mode is normal

KB1_active_data[7]_lut_out = KB1L12 & (KB1L14 & (TE1L161) # !KB1L14 & KB1_active_data[7]) # !KB1L12 & KB1_active_data[7];

KB1_active_data[7] = DFFEAS(KB1_active_data[7]_lut_out, GLOBAL(QC2__clk0), VCC, , , , , , );

--TE1_entry_0[7] is std_1c20:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_0[7] at LC_X23_Y16_N3

--operation mode is normal

TE1_entry_0[7]_lut_out = S1_M_st_data[7];

TE1_entry_0[7] = DFFEAS(TE1_entry_0[7]_lut_out, GLOBAL(QC2__clk0), VCC, , TE1L84, , , , );

--TE1L161 is std_1c20:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|rd_data[7]~534 at LC_X23_Y16_N9

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

TE1_entry_1[7]_qfbk = TE1_entry_1[7];

TE1L161 = TE1_rd_address & (TE1_entry_1[7]_qfbk) # !TE1_rd_address & TE1_entry_0[7];

--TE1_entry_1[7] is std_1c20:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_1[7] at LC_X23_Y16_N9

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

TE1_entry_1[7] = DFFEAS(TE1L161, GLOBAL(QC2__clk0), VCC, , TE1L148, S1_M_st_data[7], , , VCC);

--KB1L972 is std_1c20:inst|sdram:the_sdram|Mux142~1170 at LC_X14_Y15_N1

--operation mode is normal

KB1L972 = KB1_m_state[1] & KB1_active_data[7] # !KB1_m_state[1] & (KB1_f_select & (TE1L161) # !KB1_f_select & KB1_active_data[7]);

--KB1_active_data[6] is std_1c20:inst|sdram:the_sdram|active_data[6] at LC_X18_Y15_N4

--operation mode is normal

KB1_active_data[6]_lut_out = KB1L66 & (KB1L65 & TE1L160 # !KB1L65 & (KB1_active_data[6])) # !KB1L66 & (KB1_active_data[6]);

KB1_active_data[6] = DFFEAS(KB1_active_data[6]_lut_out, GLOBAL(QC2__clk0), VCC, , , , , , );

--TE1_entry_0[6] is std_1c20:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_0[6] at LC_X24_Y15_N3

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

TE1_entry_0[6]_lut_out = GND;

TE1_entry_0[6] = DFFEAS(TE1_entry_0[6]_lut_out, GLOBAL(QC2__clk0), VCC, , TE1L84, S1_M_st_data[6], , , VCC);

--TE1L160 is std_1c20:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|rd_data[6]~535 at LC_X24_Y15_N9

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

TE1_entry_1[6]_qfbk = TE1_entry_1[6];

TE1L160 = TE1_rd_address & (TE1_entry_1[6]_qfbk) # !TE1_rd_address & TE1_entry_0[6];

--TE1_entry_1[6] is std_1c20:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_1[6] at LC_X24_Y15_N9

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

TE1_entry_1[6] = DFFEAS(TE1L160, GLOBAL(QC2__clk0), VCC, , TE1L148, S1_M_st_data[6], , , VCC);

--KB1L973 is std_1c20:inst|sdram:the_sdram|Mux143~1170 at LC_X18_Y15_N3

--operation mode is normal

KB1L973 = KB1_m_state[1] & (KB1_active_data[6]) # !KB1_m_state[1] & (KB1_f_select & TE1L160 # !KB1_f_select & (KB1_active_data[6]));

--KB1_active_data[5] is std_1c20:inst|sdram:the_sdram|active_data[5] at LC_X13_Y16_N4

--operation mode is normal

KB1_active_data[5]_lut_out = KB1L12 & (KB1L14 & (TE1L159) # !KB1L14 & KB1_active_data[5]) # !KB1L12 & KB1_active_data[5];

KB1_active_data[5] = DFFEAS(KB1_active_data[5]_lut_out, GLOBAL(QC2__clk0), VCC, , , , , , );

--TE1_entry_0[5] is std_1c20:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_0[5] at LC_X23_Y15_N3

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

TE1_entry_0[5]_lut_out = GND;

TE1_entry_0[5] = DFFEAS(TE1_entry_0[5]_lut_out, GLOBAL(QC2__clk0), VCC, , TE1L84, S1_M_st_data[5], , , VCC);

--TE1L159 is std_1c20:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|rd_data[5]~536 at LC_X23_Y15_N4

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

TE1_entry_1[5]_qfbk = TE1_entry_1[5];

TE1L159 = TE1_rd_address & (TE1_entry_1[5]_qfbk) # !TE1_rd_address & TE1_entry_0[5];

--TE1_entry_1[5] is std_1c20:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_1[5] at LC_X23_Y15_N4

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

TE1_entry_1[5] = DFFEAS(TE1L159, GLOBAL(QC2__clk0), VCC, , TE1L148, S1_M_st_data[5], , , VCC);

--KB1L974 is std_1c20:inst|sdram:the_sdram|Mux144~1170 at LC_X13_Y16_N8

--operation mode is normal

KB1L974 = KB1_m_state[1] & KB1_active_data[5] # !KB1_m_state[1] & (KB1_f_select & (TE1L159) # !KB1_f_select & KB1_active_data[5]);

--KB1_active_data[4] is std_1c20:inst|sdram:the_sdram|active_data[4] at LC_X17_Y15_N4

--operation mode is normal

KB1_active_data[4]_lut_out = KB1L66 & (KB1L65 & (TE1L158) # !KB1L65 & KB1_active_data[4]) # !KB1L66 & (KB1_active_data[4]);

KB1_active_data[4] = DFFEAS(KB1_active_data[4]_lut_out, GLOBAL(QC2__clk0), VCC, , , , , , );

--TE1_entry_0[4] is std_1c20:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_0[4] at LC_X23_Y16_N4

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

TE1_entry_0[4]_lut_out = GND;

TE1_entry_0[4] = DFFEAS(TE1_entry_0[4]_lut_out, GLOBAL(QC2__clk0), VCC, , TE1L84, S1_M_st_data[4], , , VCC);

--TE1L158 is std_1c20:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|rd_data[4]~537 at LC_X23_Y16_N6

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

TE1_entry_1[4]_qfbk = TE1_entry_1[4];

TE1L158 = TE1_rd_address & (TE1_entry_1[4]_qfbk) # !TE1_rd_address & TE1_entry_0[4];

--TE1_entry_1[4] is std_1c20:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_1[4] at LC_X23_Y16_N6

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

TE1_entry_1[4] = DFFEAS(TE1L158, GLOBAL(QC2__clk0), VCC, , TE1L148, S1_M_st_data[4], , , VCC);

--KB1L975 is std_1c20:inst|sdram:the_sdram|Mux145~1170 at LC_X17_Y15_N8

--operation mode is normal

KB1L975 = KB1_m_state[1] & KB1_active_data[4] # !KB1_m_state[1] & (KB1_f_select & (TE1L158) # !KB1_f_select & KB1_active_data[4]);

--KB1_active_data[3] is std_1c20:inst|sdram:the_sdram|active_data[3] at LC_X18_Y15_N5

--operation mode is normal

KB1_active_data[3]_lut_out = KB1L12 & (KB1L14 & (TE1L157) # !KB1L14 & KB1_active_data[3]) # !KB1L12 & KB1_active_data[3];

KB1_active_data[3] = DFFEAS(KB1_active_data[3]_lut_out, GLOBAL(QC2__clk0), VCC, , , , , , );

--TE1_entry_0[3] is std_1c20:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_0[3] at LC_X23_Y18_N3

--operation mode is normal

TE1_entry_0[3]_lut_out = S1_M_st_data[3];

TE1_entry_0[3] = DFFEAS(TE1_entry_0[3]_lut_out, GLOBAL(QC2__clk0), VCC, , TE1L84, , , , );

--TE1L157 is std_1c20:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|rd_data[3]~538 at LC_X23_Y18_N7

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

TE1_entry_1[3]_qfbk = TE1_entry_1[3];

TE1L157 = TE1_rd_address & (TE1_entry_1[3]_qfbk) # !TE1_rd_address & TE1_entry_0[3];

--TE1_entry_1[3] is std_1c20:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_1[3] at LC_X23_Y18_N7

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

TE1_entry_1[3] = DFFEAS(TE1L157, GLOBAL(QC2__clk0), VCC, , TE1L148, S1_M_st_data[3], , , VCC);

--KB1L976 is std_1c20:inst|sdram:the_sdram|Mux146~1170 at LC_X18_Y15_N8

--operation mode is normal

KB1L976 = KB1_m_state[1] & KB1_active_data[3] # !KB1_m_state[1] & (KB1_f_select & (TE1L157) # !KB1_f_select & KB1_active_data[3]);

--KB1_active_data[2] is std_1c20:inst|sdram:the_sdram|active_data[2] at LC_X16_Y17_N4

--operation mode is normal

KB1_active_data[2]_lut_out = KB1L66 & (KB1L65 & TE1L156 # !KB1L65 & (KB1_active_data[2])) # !KB1L66 & (KB1_active_data[2]);

KB1_active_data[2] = DFFEAS(KB1_active_data[2]_lut_out, GLOBAL(QC2__clk0), VCC, , , , , , );

--TE1_entry_0[2] is std_1c20:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_0[2] at LC_X22_Y18_N3

--operation mode is normal

TE1_entry_0[2]_lut_out = S1_M_st_data[2];

TE1_entry_0[2] = DFFEAS(TE1_entry_0[2]_lut_out, GLOBAL(QC2__clk0), VCC, , TE1L84, , , , );

--TE1L156 is std_1c20:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|rd_data[2]~539 at LC_X22_Y18_N8

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

TE1_entry_1[2]_qfbk = TE1_entry_1[2];

TE1L156 = TE1_rd_address & (TE1_entry_1[2]_qfbk) # !TE1_rd_address & TE1_entry_0[2];

--TE1_entry_1[2] is std_1c20:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_1[2] at LC_X22_Y18_N8

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

TE1_entry_1[2] = DFFEAS(TE1L156, GLOBAL(QC2__clk0), VCC, , TE1L148, S1_M_st_data[2], , , VCC);

--KB1L977 is std_1c20:inst|sdram:the_sdram|Mux147~1170 at LC_X16_Y17_N9

--operation mode is normal

KB1L977 = KB1_m_state[1] & KB1_active_data[2] # !KB1_m_state[1] & (KB1_f_select & (TE1L156) # !KB1_f_select & KB1_active_data[2]);

--KB1_active_data[1] is std_1c20:inst|sdram:the_sdram|active_data[1] at LC_X16_Y17_N6

--operation mode is normal

KB1_active_data[1]_lut_out = KB1L12 & (KB1L14 & (TE1L155) # !KB1L14 & KB1_active_data[1]) # !KB1L12 & KB1_active_data[1];

KB1_active_data[1] = DFFEAS(KB1_active_data[1]_lut_out, GLOBAL(QC2__clk0), VCC, , , , , , );

--TE1_entry_0[1] is std_1c20:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_0[1] at LC_X24_Y17_N3

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

TE1_entry_0[1]_lut_out = GND;

TE1_entry_0[1] = DFFEAS(TE1_entry_0[1]_lut_out, GLOBAL(QC2__clk0), VCC, , TE1L84, S1_M_st_data[1], , , VCC);

--TE1L155 is std_1c20:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|rd_data[1]~540 at LC_X24_Y17_N2

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

TE1_entry_1[1]_qfbk = TE1_entry_1[1];

TE1L155 = TE1_rd_address & (TE1_entry_1[1]_qfbk) # !TE1_rd_address & TE1_entry_0[1];

--TE1_entry_1[1] is std_1c20:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_1[1] at LC_X24_Y17_N2

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

TE1_entry_1[1] = DFFEAS(TE1L155, GLOBAL(QC2__clk0), VCC, , TE1L148, S1_M_st_data[1], , , VCC);

--KB1L978 is std_1c20:inst|sdram:the_sdram|Mux148~1170 at LC_X16_Y17_N2

--operation mode is normal

KB1L978 = KB1_m_state[1] & KB1_active_data[1] # !KB1_m_state[1] & (KB1_f_select & (TE1L155) # !KB1_f_select & KB1_active_data[1]);

--KB1_active_data[0] is std_1c20:inst|sdram:the_sdram|active_data[0] at LC_X16_Y16_N7

--operation mode is normal

KB1_active_data[0]_lut_out = KB1L66 & (KB1L65 & TE1L154 # !KB1L65 & (KB1_active_data[0])) # !KB1L66 & (KB1_active_data[0]);

KB1_active_data[0] = DFFEAS(KB1_active_data[0]_lut_out, GLOBAL(QC2__clk0), VCC, , , , , , );

--TE1_entry_0[0] is std_1c20:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_0[0] at LC_X24_Y16_N3

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

TE1_entry_0[0]_lut_out = GND;

TE1_entry_0[0] = DFFEAS(TE1_entry_0[0]_lut_out, GLOBAL(QC2__clk0), VCC, , TE1L84, S1_M_st_data[0], , , VCC);

--TE1L154 is std_1c20:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|rd_data[0]~541 at LC_X24_Y16_N9

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

TE1_entry_1[0]_qfbk = TE1_entry_1[0];

TE1L154 = TE1_rd_address & TE1_entry_1[0]_qfbk # !TE1_rd_address & (TE1_entry_0[0]);

--TE1_entry_1[0] is std_1c20:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_1[0] at LC_X24_Y16_N9

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

TE1_entry_1[0] = DFFEAS(TE1L154, GLOBAL(QC2__clk0), VCC, , TE1L148, S1_M_st_data[0], , , VCC);

--KB1L979 is std_1c20:inst|sdram:the_sdram|Mux149~1170 at LC_X16_Y16_N8

--operation mode is normal

KB1L979 = KB1_m_state[1] & (KB1_active_data[0]) # !KB1_m_state[1] & (KB1_f_select & TE1L154 # !KB1_f_select & (KB1_active_data[0]));

--S1L1520Q is std_1c20:inst|cpu:the_cpu|ic_fill_ap_cnt[2]~42 at LC_X26_Y25_N3

--operation mode is normal

S1L1520Q = AMPP_FUNCTION(QC2__clk0, S1L1511, S1L1496, S1L1518, F1_data_out);

--S1L1513Q is std_1c20:inst|cpu:the_cpu|ic_fill_ap_cnt[1]~41 at LC_X26_Y25_N5

--operation mode is normal

S1L1513Q = AMPP_FUNCTION(QC2__clk0, S1L1496, S1L1511, F1_data_out);

--NB1L66 is std_1c20:inst|sdram_s1_arbitrator:the_sdram_s1|sdram_s1_arb_counter_enable~44 at LC_X23_Y22_N5

--operation mode is normal

NB1L66 = NB1_WideOr1 # !NB1L27 & !S1L1693Q;

--S1L35 is std_1c20:inst|cpu:the_cpu|A_WE_StdLogicVector~14115 at LC_X27_Y20_N6

--operation mode is normal

S1L35 = AMPP_FUNCTION(S1L240, S1L1317, S1L104, S1L343);

--S1_M_pipe_flush_waddr[12] is std_1c20:inst|cpu:the_cpu|M_pipe_flush_waddr[12] at LC_X29_Y18_N6

--operation mode is normal

S1_M_pipe_flush_waddr[12] = AMPP_FUNCTION(QC2__clk0, S1L50, S1_E_ctrl_jmp_indirect, S1_E_pc[12], S1L867, F1_data_out, S1_E_hbreak_req, S1_W_stall);

--S1L36 is std_1c20:inst|cpu:the_cpu|A_WE_StdLogicVector~14116 at LC_X27_Y20_N5

--operation mode is normal

S1L36 = AMPP_FUNCTION(S1L240, S1L343, S1L1329, S1L92);

--S1_M_pipe_flush_waddr[16] is std_1c20:inst|cpu:the_cpu|M_pipe_flush_waddr[16] at LC_X29_Y18_N2

--operation mode is normal

S1_M_pipe_flush_waddr[16] = AMPP_FUNCTION(QC2__clk0, S1L51, S1_E_ctrl_jmp_indirect, S1_E_pc[16], S1L871, F1_data_out, S1_E_hbreak_req, S1_W_stall);

--S1_ic_tag_clr_valid_bits is std_1c20:inst|cpu:the_cpu|ic_tag_clr_valid_bits at LC_X23_Y20_N9

--operation mode is normal

S1_ic_tag_clr_valid_bits = AMPP_FUNCTION(QC2__clk0, S1_ic_tag_clr_valid_bits_nxt, F1_data_out);

--S1_ic_tag_wren is std_1c20:inst|cpu:the_cpu|ic_tag_wren at LC_X23_Y20_N5

--operation mode is normal

S1_ic_tag_wren = AMPP_FUNCTION(S1_ic_tag_clr_valid_bits, S1_i_readdatavalid_d1);

--S1_ic_tag_wraddress[0] is std_1c20:inst|cpu:the_cpu|ic_tag_wraddress[0] at LC_X24_Y20_N9

--operation mode is normal

S1_ic_tag_wraddress[0] = AMPP_FUNCTION(QC2__clk0, S1_M_alu_result[5], S1L1560, S1L1562, S1_reset_d1, F1_data_out);

--S1L1232 is std_1c20:inst|cpu:the_cpu|F_ic_tag_rd_addr_nxt[0]~4242 at LC_X26_Y19_N2

--operation mode is normal

S1L1232 = AMPP_FUNCTION(S1L1292, S1L240, S1_D_br_taken_waddr_partial[3], S1L343);

--S1_M_pipe_flush_waddr[3] is std_1c20:inst|cpu:the_cpu|M_pipe_flush_waddr[3] at LC_X29_Y19_N0

--operation mode is normal

S1_M_pipe_flush_waddr[3] = AMPP_FUNCTION(QC2__clk0, S1_E_ctrl_jmp_indirect, S1L858, S1_E_pc[3], S1L52, F1_data_out, S1_E_hbreak_req, S1_W_stall);

--S1L1233 is std_1c20:inst|cpu:the_cpu|F_ic_tag_rd_addr_nxt[0]~4243 at LC_X27_Y19_N2

--operation mode is normal

S1L1233 = AMPP_FUNCTION(S1_M_pipe_flush, S1_M_pipe_flush_waddr[3], S1L1234);

--S1_F_pc[3] is std_1c20:inst|cpu:the_cpu|F_pc[3] at LC_X27_Y19_N2

--operation mode is normal

S1_F_pc[3] = AMPP_FUNCTION(QC2__clk0, S1_M_pipe_flush, S1_M_pipe_flush_waddr[3], S1L1234, F1_data_out, S1_W_stall);

--S1L1235 is std_1c20:inst|cpu:the_cpu|F_ic_tag_rd_addr_nxt[1]~4244 at LC_X26_Y19_N4

--operation mode is normal

S1L1235 = AMPP_FUNCTION(S1_D_br_taken_waddr_partial[4], S1L240, S1L1295, S1L343);

--S1_M_pipe_flush_waddr[4] is std_1c20:inst|cpu:the_cpu|M_pipe_flush_waddr[4] at LC_X30_Y19_N5

--operation mode is normal

S1_M_pipe_flush_waddr[4] = AMPP_FUNCTION(QC2__clk0, S1L859, S1_E_ctrl_jmp_indirect, S1_E_pc[4], S1L53, F1_data_out, S1_E_hbreak_req, S1_W_stall);

--S1L1236 is std_1c20:inst|cpu:the_cpu|F_ic_tag_rd_addr_nxt[1]~4245 at LC_X23_Y19_N0

--operation mode is normal

S1L1236 = AMPP_FUNCTION(S1_M_pipe_flush, S1_M_pipe_flush_waddr[4], S1L1237);

--S1_F_pc[4] is std_1c20:inst|cpu:the_cpu|F_pc[4] at LC_X23_Y19_N0

--operation mode is normal

S1_F_pc[4] = AMPP_FUNCTION(QC2__clk0, S1_M_pipe_flush, S1_M_pipe_flush_waddr[4], S1L1237, F1_data_out, S1_W_stall);

--S1L1238 is std_1c20:inst|cpu:the_cpu|F_ic_tag_rd_addr_nxt[2]~4246 at LC_X26_Y18_N7

--operation mode is normal

S1L1238 = AMPP_FUNCTION(S1L240, S1_D_br_taken_waddr_partial[5], S1L1298, S1L343);

--S1_M_pipe_flush_waddr[5] is std_1c20:inst|cpu:the_cpu|M_pipe_flush_waddr[5] at LC_X29_Y18_N3

--operation mode is normal

S1_M_pipe_flush_waddr[5] = AMPP_FUNCTION(QC2__clk0, S1L54, S1_E_ctrl_jmp_indirect, S1_E_pc[5], S1L860, F1_data_out, S1_E_hbreak_req, S1_W_stall);

--S1L1239 is std_1c20:inst|cpu:the_cpu|F_ic_tag_rd_addr_nxt[2]~4247 at LC_X25_Y18_N8

--operation mode is normal

S1L1239 = AMPP_FUNCTION(S1_M_pipe_flush_waddr[5], S1_M_pipe_flush, S1L1240);

--S1_F_pc[5] is std_1c20:inst|cpu:the_cpu|F_pc[5] at LC_X25_Y18_N8

--operation mode is normal

S1_F_pc[5] = AMPP_FUNCTION(QC2__clk0, S1_M_pipe_flush_waddr[5], S1_M_pipe_flush, S1L1240, F1_data_out, S1_W_stall);

--S1L1241 is std_1c20:inst|cpu:the_cpu|F_ic_tag_rd_addr_nxt[3]~4248 at LC_X25_Y17_N4

--operation mode is normal

S1L1241 = AMPP_FUNCTION(S1L343, S1_D_br_taken_waddr_partial[6], S1L1301, S1L240);

--S1_M_pipe_flush_waddr[6] is std_1c20:inst|cpu:the_cpu|M_pipe_flush_waddr[6] at LC_X29_Y18_N1

--operation mode is normal

S1_M_pipe_flush_waddr[6] = AMPP_FUNCTION(QC2__clk0, S1L861, S1_E_ctrl_jmp_indirect, S1_E_pc[6], S1L55, F1_data_out, S1_E_hbreak_req, S1_W_stall);

--S1L1242 is std_1c20:inst|cpu:the_cpu|F_ic_tag_rd_addr_nxt[3]~4249 at LC_X26_Y17_N6

--operation mode is normal

S1L1242 = AMPP_FUNCTION(S1_M_pipe_flush, S1_M_pipe_flush_waddr[6], S1L1243);

--S1_F_pc[6] is std_1c20:inst|cpu:the_cpu|F_pc[6] at LC_X26_Y17_N6

--operation mode is normal

S1_F_pc[6] = AMPP_FUNCTION(QC2__clk0, S1_M_pipe_flush, S1_M_pipe_flush_waddr[6], S1L1243, F1_data_out, S1_W_stall);

--S1L1244 is std_1c20:inst|cpu:the_cpu|F_ic_tag_rd_addr_nxt[4]~4250 at LC_X26_Y18_N9

--operation mode is normal

S1L1244 = AMPP_FUNCTION(S1_D_br_taken_waddr_partial[7], S1L343, S1L1303, S1L240);

--S1_M_pipe_flush_waddr[7] is std_1c20:inst|cpu:the_cpu|M_pipe_flush_waddr[7] at LC_X29_Y16_N2

--operation mode is normal

S1_M_pipe_flush_waddr[7] = AMPP_FUNCTION(QC2__clk0, S1L862, S1L56, S1_E_pc[7], S1_E_ctrl_jmp_indirect, F1_data_out, S1_E_hbreak_req, S1_W_stall);

--S1L1245 is std_1c20:inst|cpu:the_cpu|F_ic_tag_rd_addr_nxt[4]~4251 at LC_X26_Y17_N2

--operation mode is normal

S1L1245 = AMPP_FUNCTION(S1_M_pipe_flush, S1_M_pipe_flush_waddr[7], S1L1246);

--S1_F_pc[7] is std_1c20:inst|cpu:the_cpu|F_pc[7] at LC_X26_Y17_N2

--operation mode is normal

S1_F_pc[7] = AMPP_FUNCTION(QC2__clk0, S1_M_pipe_flush, S1_M_pipe_flush_waddr[7], S1L1246, F1_data_out, S1_W_stall);

--S1L1247 is std_1c20:inst|cpu:the_cpu|F_ic_tag_rd_addr_nxt[5]~4252 at LC_X25_Y17_N8

--operation mode is normal

S1L1247 = AMPP_FUNCTION(S1L343, S1L1306, S1_D_br_taken_waddr_partial[8], S1L240);

--S1_M_pipe_flush_waddr[8] is std_1c20:inst|cpu:the_cpu|M_pipe_flush_waddr[8] at LC_X29_Y16_N8

--operation mode is normal

S1_M_pipe_flush_waddr[8] = AMPP_FUNCTION(QC2__clk0, S1L57, S1L863, S1_E_pc[8], S1_E_ctrl_jmp_indirect, F1_data_out, S1_E_hbreak_req, S1_W_stall);

--S1L1248 is std_1c20:inst|cpu:the_cpu|F_ic_tag_rd_addr_nxt[5]~4253 at LC_X25_Y20_N6

--operation mode is normal

S1L1248 = AMPP_FUNCTION(S1_M_pipe_flush_waddr[8], S1L1249, S1_M_pipe_flush);

--S1_F_pc[8] is std_1c20:inst|cpu:the_cpu|F_pc[8] at LC_X25_Y20_N6

--operation mode is normal

S1_F_pc[8] = AMPP_FUNCTION(QC2__clk0, S1_M_pipe_flush_waddr[8], S1L1249, S1_M_pipe_flush, F1_data_out, S1_W_stall);

--S1L1250 is std_1c20:inst|cpu:the_cpu|F_ic_tag_rd_addr_nxt[6]~4254 at LC_X26_Y18_N6

--operation mode is normal

S1L1250 = AMPP_FUNCTION(S1L240, S1_D_br_taken_waddr_partial[9], S1L1309, S1L343);

--S1_M_pipe_flush_waddr[9] is std_1c20:inst|cpu:the_cpu|M_pipe_flush_waddr[9] at LC_X29_Y16_N9

--operation mode is normal

S1_M_pipe_flush_waddr[9] = AMPP_FUNCTION(QC2__clk0, S1L864, S1L58, S1_E_pc[9], S1_E_ctrl_jmp_indirect, F1_data_out, S1_E_hbreak_req, S1_W_stall);

--S1L1251 is std_1c20:inst|cpu:the_cpu|F_ic_tag_rd_addr_nxt[6]~4255 at LC_X26_Y17_N0

--operation mode is normal

S1L1251 = AMPP_FUNCTION(S1_M_pipe_flush, S1L1252, S1_M_pipe_flush_waddr[9]);

--S1_F_pc[9] is std_1c20:inst|cpu:the_cpu|F_pc[9] at LC_X26_Y17_N0

--operation mode is normal

S1_F_pc[9] = AMPP_FUNCTION(QC2__clk0, S1_M_pipe_flush, S1L1252, S1_M_pipe_flush_waddr[9], F1_data_out, S1_W_stall);

--S1L37 is std_1c20:inst|cpu:the_cpu|A_WE_StdLogicVector~14117 at LC_X25_Y17_N3

--operation mode is normal

S1L37 = AMPP_FUNCTION(S1L343, S1L84, S1L1340, S1L240);

--S1_M_pipe_flush_waddr[20] is std_1c20:inst|cpu:the_cpu|M_pipe_flush_waddr[20] at LC_X27_Y16_N3

--operation mode is normal

S1_M_pipe_flush_waddr[20] = AMPP_FUNCTION(QC2__clk0, S1L875, S1L59, S1_E_pc[20], S1_E_ctrl_jmp_indirect, F1_data_out, S1_E_hbreak_req, S1_W_stall);

--S1L38 is std_1c20:inst|cpu:the_cpu|A_WE_StdLogicVector~14118 at LC_X25_Y17_N2

--operation mode is normal

S1L38 = AMPP_FUNCTION(S1L240, S1L86, S1L1337, S1L343);

--S1_M_pipe_flush_waddr[19] is std_1c20:inst|cpu:the_cpu|M_pipe_flush_waddr[19] at LC_X29_Y18_N0

--operation mode is normal

S1_M_pipe_flush_waddr[19] = AMPP_FUNCTION(QC2__clk0, S1L60, S1_E_ctrl_jmp_indirect, S1_E_pc[19], S1L874, F1_data_out, S1_E_hbreak_req, S1_W_stall);

--S1L39 is std_1c20:inst|cpu:the_cpu|A_WE_StdLogicVector~14119 at LC_X25_Y17_N7

--operation mode is normal

S1L39 = AMPP_FUNCTION(S1L343, S1L115, S1L240, S1L1334);

--S1_M_pipe_flush_waddr[18] is std_1c20:inst|cpu:the_cpu|M_pipe_flush_waddr[18] at LC_X27_Y16_N4

--operation mode is normal

S1_M_pipe_flush_waddr[18] = AMPP_FUNCTION(QC2__clk0, S1L873, S1L62, S1_E_pc[18], S1_E_ctrl_jmp_indirect, F1_data_out, S1_E_hbreak_req, S1_W_stall);

--S1L40 is std_1c20:inst|cpu:the_cpu|A_WE_StdLogicVector~14120 at LC_X27_Y17_N7

--operation mode is normal

S1L40 = AMPP_FUNCTION(S1L240, S1L1331, S1L343, S1L89);

--S1_M_pipe_flush_waddr[17] is std_1c20:inst|cpu:the_cpu|M_pipe_flush_waddr[17] at LC_X29_Y16_N0

--operation mode is normal

S1_M_pipe_flush_waddr[17] = AMPP_FUNCTION(QC2__clk0, S1_E_ctrl_jmp_indirect, S1L63, S1_E_pc[17], S1L872, F1_data_out, S1_E_hbreak_req, S1_W_stall);

--S1L41 is std_1c20:inst|cpu:the_cpu|A_WE_StdLogicVector~14121 at LC_X27_Y17_N9

--operation mode is normal

S1L41 = AMPP_FUNCTION(S1L240, S1L1343, S1L118, S1L343);

--S1_M_pipe_flush_waddr[21] is std_1c20:inst|cpu:the_cpu|M_pipe_flush_waddr[21] at LC_X27_Y16_N2

--operation mode is normal

S1_M_pipe_flush_waddr[21] = AMPP_FUNCTION(QC2__clk0, S1L64, S1_E_ctrl_jmp_indirect, S1_E_pc[21], S1L876, F1_data_out, S1_E_hbreak_req, S1_W_stall);

--S1L42 is std_1c20:inst|cpu:the_cpu|A_WE_StdLogicVector~14122 at LC_X27_Y16_N5

--operation mode is normal

S1L42 = AMPP_FUNCTION(S1L240, S1L343, S1L1323, S1L98);

--S1_M_pipe_flush_waddr[14] is std_1c20:inst|cpu:the_cpu|M_pipe_flush_waddr[14] at LC_X27_Y16_N0

--operation mode is normal

S1_M_pipe_flush_waddr[14] = AMPP_FUNCTION(QC2__clk0, S1L65, S1L869, S1_E_pc[14], S1_E_ctrl_jmp_indirect, F1_data_out, S1_E_hbreak_req, S1_W_stall);

--S1L43 is std_1c20:inst|cpu:the_cpu|A_WE_StdLogicVector~14123 at LC_X26_Y19_N3

--operation mode is normal

S1L43 = AMPP_FUNCTION(S1L107, S1L1315, S1L240, S1L343);

--S1_M_pipe_flush_waddr[11] is std_1c20:inst|cpu:the_cpu|M_pipe_flush_waddr[11] at LC_X30_Y19_N3

--operation mode is normal

S1_M_pipe_flush_waddr[11] = AMPP_FUNCTION(QC2__clk0, S1L866, S1_E_ctrl_jmp_indirect, S1_E_pc[11], S1L66, F1_data_out, S1_E_hbreak_req, S1_W_stall);

--S1L44 is std_1c20:inst|cpu:the_cpu|A_WE_StdLogicVector~14124 at LC_X27_Y17_N8

--operation mode is normal

S1L44 = AMPP_FUNCTION(S1L95, S1L1345, S1L240, S1L343);

--S1_M_pipe_flush_waddr[22] is std_1c20:inst|cpu:the_cpu|M_pipe_flush_waddr[22] at LC_X30_Y19_N1

--operation mode is normal

S1_M_pipe_flush_waddr[22] = AMPP_FUNCTION(QC2__clk0, S1L68, S1_E_ctrl_jmp_indirect, S1_E_pc[22], S1L877, F1_data_out, S1_E_hbreak_req, S1_W_stall);

--S1L45 is std_1c20:inst|cpu:the_cpu|A_WE_StdLogicVector~14125 at LC_X28_Y19_N6

--operation mode is normal

S1L45 = AMPP_FUNCTION(S1L343, S1L1348, S1L240, S1L114);

--S1_M_pipe_flush_waddr[23] is std_1c20:inst|cpu:the_cpu|M_pipe_flush_waddr[23] at LC_X29_Y19_N2

--operation mode is normal

S1_M_pipe_flush_waddr[23] = AMPP_FUNCTION(QC2__clk0, S1_E_ctrl_jmp_indirect, S1L70, S1_E_pc[23], S1L878, F1_data_out, S1_E_hbreak_req, S1_W_stall);

--S1L46 is std_1c20:inst|cpu:the_cpu|A_WE_StdLogicVector~14126 at LC_X28_Y19_N3

--operation mode is normal

S1L46 = AMPP_FUNCTION(S1L343, S1L240, S1L1326, S1L112);

--S1_M_pipe_flush_waddr[15] is std_1c20:inst|cpu:the_cpu|M_pipe_flush_waddr[15] at LC_X30_Y19_N0

--operation mode is normal

S1_M_pipe_flush_waddr[15] = AMPP_FUNCTION(QC2__clk0, S1L72, S1_E_ctrl_jmp_indirect, S1_E_pc[15], S1L870, F1_data_out, S1_E_hbreak_req, S1_W_stall);

--S1L47 is std_1c20:inst|cpu:the_cpu|A_WE_StdLogicVector~14127 at LC_X28_Y19_N0

--operation mode is normal

S1L47 = AMPP_FUNCTION(S1L343, S1L1320, S1L240, S1L101);

--S1_M_pipe_flush_waddr[13] is std_1c20:inst|cpu:the_cpu|M_pipe_flush_waddr[13] at LC_X30_Y19_N6

--operation mode is normal

S1_M_pipe_flush_waddr[13] = AMPP_FUNCTION(QC2__clk0, S1L868, S1_E_ctrl_jmp_indirect, S1_E_pc[13], S1L73, F1_data_out, S1_E_hbreak_req, S1_W_stall);

--S1L48 is std_1c20:inst|cpu:the_cpu|A_WE_StdLogicVector~14128 at LC_X28_Y19_N1

--operation mode is normal

S1L48 = AMPP_FUNCTION(S1L110, S1L240, S1L1312, S1L343);

--S1_M_pipe_flush_waddr[10] is std_1c20:inst|cpu:the_cpu|M_pipe_flush_waddr[10] at LC_X30_Y17_N2

--operation mode is normal

S1_M_pipe_flush_waddr[10] = AMPP_FUNCTION(QC2__clk0, S1_E_ctrl_jmp_indirect, S1L74, S1_E_pc[10], S1L865, F1_data_out, S1_E_hbreak_req, S1_W_stall);

--S1_ic_fill_valid_bits[5] is std_1c20:inst|cpu:the_cpu|ic_fill_valid_bits[5] at LC_X22_Y20_N7

--operation mode is normal

S1_ic_fill_valid_bits[5] = AMPP_FUNCTION(QC2__clk0, S1_D_ic_fill_starting_d1, S1_ic_tag_clr_valid_bits_nxt, S1_ic_fill_valid_bits[5], S1L1661, F1_data_out, S1_ic_fill_valid_bits_en);

--S1L1202 is std_1c20:inst|cpu:the_cpu|F_ic_data_rd_addr_nxt[2]~1818 at LC_X26_Y19_N0

--operation mode is normal

S1L1202 = AMPP_FUNCTION(S1_D_br_taken_waddr_partial[2], S1L1289, S1L240, S1L343);

--S1_M_pipe_flush_waddr[2] is std_1c20:inst|cpu:the_cpu|M_pipe_flush_waddr[2] at LC_X29_Y19_N3

--operation mode is normal

S1_M_pipe_flush_waddr[2] = AMPP_FUNCTION(QC2__clk0, S1_E_ctrl_jmp_indirect, S1L75, S1_E_pc[2], S1L855, F1_data_out, S1_E_hbreak_req, S1_W_stall);

--S1L1203 is std_1c20:inst|cpu:the_cpu|F_ic_data_rd_addr_nxt[2]~1819 at LC_X23_Y19_N4

--operation mode is normal

S1L1203 = AMPP_FUNCTION(S1_M_pipe_flush, S1L1204, S1_M_pipe_flush_waddr[2]);

--S1_F_pc[2] is std_1c20:inst|cpu:the_cpu|F_pc[2] at LC_X23_Y19_N4

--operation mode is normal

S1_F_pc[2] = AMPP_FUNCTION(QC2__clk0, S1_M_pipe_flush, S1L1204, S1_M_pipe_flush_waddr[2], F1_data_out, S1_W_stall);

--S1_ic_fill_valid_bits[3] is std_1c20:inst|cpu:the_cpu|ic_fill_valid_bits[3] at LC_X21_Y20_N2

--operation mode is normal

S1_ic_fill_valid_bits[3] = AMPP_FUNCTION(QC2__clk0, S1_ic_fill_valid_bits[3], S1_ic_tag_clr_valid_bits_nxt, S1_D_ic_fill_starting_d1, S1L1659, F1_data_out, S1_ic_fill_valid_bits_en);

--S1L1199 is std_1c20:inst|cpu:the_cpu|F_ic_data_rd_addr_nxt[1]~1820 at LC_X26_Y19_N1

--operation mode is normal

S1L1199 = AMPP_FUNCTION(S1_D_br_taken_waddr_partial[1], S1L240, S1L343, S1L1287);

--S1_M_pipe_flush_waddr[1] is std_1c20:inst|cpu:the_cpu|M_pipe_flush_waddr[1] at LC_X30_Y17_N8

--operation mode is normal

S1_M_pipe_flush_waddr[1] = AMPP_FUNCTION(QC2__clk0, S1_E_ctrl_jmp_indirect, S1L854, S1_E_pc[1], S1L76, F1_data_out, S1_E_hbreak_req, S1_W_stall);

--S1L1200 is std_1c20:inst|cpu:the_cpu|F_ic_data_rd_addr_nxt[1]~1821 at LC_X23_Y19_N9

--operation mode is normal

S1L1200 = AMPP_FUNCTION(S1L1201, S1_M_pipe_flush_waddr[1], S1_M_pipe_flush);

--S1_F_pc[1] is std_1c20:inst|cpu:the_cpu|F_pc[1] at LC_X23_Y19_N9

--operation mode is normal

S1_F_pc[1] = AMPP_FUNCTION(QC2__clk0, S1L1201, S1_M_pipe_flush_waddr[1], S1_M_pipe_flush, F1_data_out, S1_W_stall);

--S1_ic_fill_valid_bits[1] is std_1c20:inst|cpu:the_cpu|ic_fill_valid_bits[1] at LC_X22_Y20_N9

--operation mode is normal

S1_ic_fill_valid_bits[1] = AMPP_FUNCTION(QC2__clk0, S1_D_ic_fill_starting_d1, S1_ic_tag_clr_valid_bits_nxt, S1_ic_fill_valid_bits[1], S1L1657, F1_data_out, S1_ic_fill_valid_bits_en);

--S1_ic_fill_valid_bits[7] is std_1c20:inst|cpu:the_cpu|ic_fill_valid_bits[7] at LC_X22_Y20_N1

--operation mode is normal

S1_ic_fill_valid_bits[7] = AMPP_FUNCTION(QC2__clk0, S1_ic_fill_valid_bits[7], S1_ic_tag_clr_valid_bits_nxt, S1_D_ic_fill_starting_d1, S1L1662, F1_data_out, S1_ic_fill_valid_bits_en);

--S1_ic_fill_valid_bits[2] is std_1c20:inst|cpu:the_cpu|ic_fill_valid_bits[2] at LC_X21_Y20_N8

--operation mode is normal

S1_ic_fill_valid_bits[2] = AMPP_FUNCTION(QC2__clk0, S1_ic_fill_valid_bits[2], S1L1658, S1_D_ic_fill_starting_d1, S1_ic_tag_clr_valid_bits_nxt, F1_data_out, S1_ic_fill_valid_bits_en);

--S1_ic_fill_valid_bits[4] is std_1c20:inst|cpu:the_cpu|ic_fill_valid_bits[4] at LC_X21_Y20_N7

--operation mode is normal

S1_ic_fill_valid_bits[4] = AMPP_FUNCTION(QC2__clk0, S1L1660, S1_D_ic_fill_starting_d1, S1_ic_fill_valid_bits[4], S1_ic_tag_clr_valid_bits_nxt, F1_data_out, S1_ic_fill_valid_bits_en);

--S1_ic_fill_valid_bits[0] is std_1c20:inst|cpu:the_cpu|ic_fill_valid_bits[0] at LC_X21_Y20_N4

--operation mode is normal

S1_ic_fill_valid_bits[0] = AMPP_FUNCTION(QC2__clk0, S1_D_ic_fill_starting_d1, S1_ic_tag_clr_valid_bits_nxt, S1_ic_fill_valid_bits[0], S1L1656, F1_data_out, S1_ic_fill_valid_bits_en);

--S1_ic_fill_valid_bits[6] is std_1c20:inst|cpu:the_cpu|ic_fill_valid_bits[6] at LC_X21_Y20_N5

--operation mode is normal

S1_ic_fill_valid_bits[6] = AMPP_FUNCTION(QC2__clk0, S1L1187, S1_ic_fill_valid_bits[6], S1_D_ic_fill_starting_d1, S1_ic_tag_clr_valid_bits_nxt, F1_data_out, S1_ic_fill_valid_bits_en);

--S1L1196 is std_1c20:inst|cpu:the_cpu|F_ic_data_rd_addr_nxt[0]~1822 at LC_X25_Y20_N1

--operation mode is normal

S1L1196 = AMPP_FUNCTION(S1_D_br_taken_waddr_partial[0], S1_F_pc[0], S1L343, S1L240);

--S1_M_pipe_flush_waddr[0] is std_1c20:inst|cpu:the_cpu|M_pipe_flush_waddr[0] at LC_X29_Y19_N6

--operation mode is normal

S1_M_pipe_flush_waddr[0] = AMPP_FUNCTION(QC2__clk0, S1_E_ctrl_jmp_indirect, S1L77, S1_E_pc[0], S1L853, F1_data_out, S1_E_hbreak_req, S1_W_stall);

--S1L1197 is std_1c20:inst|cpu:the_cpu|F_ic_data_rd_addr_nxt[0]~1823 at LC_X25_Y20_N8

--operation mode is normal

S1L1197 = AMPP_FUNCTION(S1_M_pipe_flush_waddr[0], S1L385, S1_M_pipe_flush);

--S1_F_pc[0] is std_1c20:inst|cpu:the_cpu|F_pc[0] at LC_X25_Y20_N8

--operation mode is normal

S1_F_pc[0] = AMPP_FUNCTION(QC2__clk0, S1_M_pipe_flush_waddr[0], S1L385, S1_M_pipe_flush, F1_data_out, S1_W_stall);

--S1L715 is std_1c20:inst|cpu:the_cpu|E_ctrl_invalidate_i~119 at LC_X30_Y15_N3

--operation mode is normal

S1L715 = AMPP_FUNCTION(S1_E_iw[11], S1_E_iw[13], S1_E_iw[15], S1_E_iw[16]);

--U1L9 is std_1c20:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_read_but_no_slave_selected~58 at LC_X26_Y25_N9

--operation mode is normal

U1L9 = U1L10Q & U1L12Q & U1L13Q & U1L14Q;

--U1_cpu_instruction_master_dbs_rdv_counter[1] is std_1c20:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_dbs_rdv_counter[1] at LC_X37_Y25_N5

--operation mode is normal

U1_cpu_instruction_master_dbs_rdv_counter[1]_lut_out = U1_cpu_instruction_master_dbs_rdv_counter[1] $ (U1_cpu_instruction_master_dbs_rdv_counter[0]);

U1_cpu_instruction_master_dbs_rdv_counter[1] = DFFEAS(U1_cpu_instruction_master_dbs_rdv_counter[1]_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , Y1_cpu_instruction_master_read_data_valid_ext_flash_s1_shift_register[1], , , , );

--U1_cpu_instruction_master_dbs_rdv_counter[0] is std_1c20:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_dbs_rdv_counter[0] at LC_X36_Y25_N7

--operation mode is normal

U1_cpu_instruction_master_dbs_rdv_counter[0]_lut_out = !U1_cpu_instruction_master_dbs_rdv_counter[0];

U1_cpu_instruction_master_dbs_rdv_counter[0] = DFFEAS(U1_cpu_instruction_master_dbs_rdv_counter[0]_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , Y1_cpu_instruction_master_read_data_valid_ext_flash_s1_shift_register[1], , , , );

--U1L141 is std_1c20:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_readdatavalid~148 at LC_X36_Y25_N6

--operation mode is normal

U1L141 = U1L9 # U1_cpu_instruction_master_dbs_rdv_counter[0] & U1_cpu_instruction_master_dbs_rdv_counter[1] & Y1_cpu_instruction_master_read_data_valid_ext_flash_s1_shift_register[1];

--NB1_cpu_instruction_master_read_data_valid_sdram_s1 is std_1c20:inst|sdram_s1_arbitrator:the_sdram_s1|cpu_instruction_master_read_data_valid_sdram_s1 at LC_X25_Y24_N0

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

KB1_za_valid_qfbk = KB1_za_valid;

NB1_cpu_instruction_master_read_data_valid_sdram_s1 = WE1L8Q & (KB1_za_valid_qfbk & WE1L37Q);

--KB1_za_valid is std_1c20:inst|sdram:the_sdram|za_valid at LC_X25_Y24_N0

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

KB1_za_valid = DFFEAS(NB1_cpu_instruction_master_read_data_valid_sdram_s1, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , KB1_rd_valid[2], , , VCC);

--U1L142 is std_1c20:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_readdatavalid~149 at LC_X37_Y24_N2

--operation mode is normal

U1L142 = U1L141 # Y1_cpu_instruction_master_read_data_valid_lan91c111_s1_shift_register[1] # Y1_cpu_instruction_master_read_data_valid_ext_ram_s1_shift_register[1] # NB1_cpu_instruction_master_read_data_valid_sdram_s1;

--U1L143 is std_1c20:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_readdatavalid~150 at LC_X33_Y23_N1

--operation mode is normal

U1L143 = !S1L1593Q & X1_cpu_instruction_master_granted_epcs_controller_epcs_control_port & !X1L27;

--U1L144 is std_1c20:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_readdatavalid~151 at LC_X34_Y24_N9

--operation mode is normal

U1L144 = !V1L46 & (U1L140);

--S1L1542 is std_1c20:inst|cpu:the_cpu|ic_fill_dp_offset_nxt[2]~153 at LC_X23_Y20_N3

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

S1L1542 = AMPP_FUNCTION(S1_D_ic_fill_starting_d1);

--S1_ic_fill_initial_offset[2] is std_1c20:inst|cpu:the_cpu|ic_fill_initial_offset[2] at LC_X23_Y20_N3

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

S1_ic_fill_initial_offset[2] = AMPP_FUNCTION(QC2__clk0, S1_D_pc[2], F1_data_out, GND, S1_D_ic_fill_starting);

--S1L1538 is std_1c20:inst|cpu:the_cpu|ic_fill_dp_offset_en~5 at LC_X23_Y20_N6

--operation mode is normal

S1L1538 = AMPP_FUNCTION(S1_D_ic_fill_starting_d1, S1_i_readdatavalid_d1);

--S1L1539 is std_1c20:inst|cpu:the_cpu|ic_fill_dp_offset_nxt[0]~154 at LC_X22_Y20_N3

--operation mode is normal

S1L1539 = AMPP_FUNCTION(S1_D_ic_fill_starting_d1, S1_ic_fill_initial_offset[0]);

--S1_ic_fill_dp_offset[0] is std_1c20:inst|cpu:the_cpu|ic_fill_dp_offset[0] at LC_X22_Y20_N3

--operation mode is normal

S1_ic_fill_dp_offset[0] = AMPP_FUNCTION(QC2__clk0, S1_D_ic_fill_starting_d1, S1_ic_fill_initial_offset[0], F1_data_out, S1L1538);

--S1L1540 is std_1c20:inst|cpu:the_cpu|ic_fill_dp_offset_nxt[1]~155 at LC_X22_Y20_N5

--operation mode is normal

S1L1540 = AMPP_FUNCTION(S1_ic_fill_initial_offset[1], S1_ic_fill_dp_offset[0], S1_D_ic_fill_starting_d1);

--S1_ic_fill_dp_offset[1] is std_1c20:inst|cpu:the_cpu|ic_fill_dp_offset[1] at LC_X22_Y20_N5

--operation mode is normal

S1_ic_fill_dp_offset[1] = AMPP_FUNCTION(QC2__clk0, S1_ic_fill_initial_offset[1], S1_ic_fill_dp_offset[0], S1_D_ic_fill_starting_d1, F1_data_out, S1L1538);

--Y1L709 is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_avalon_slave_arb_share_counter_next_value[0]~95 at LC_X27_Y25_N8

--operation mode is normal

Y1L709 = Y1L726 & Y1L705 & !Y1L690;

--KB1_rd_valid[1] is std_1c20:inst|sdram:the_sdram|rd_valid[1] at LC_X16_Y25_N2

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

KB1_rd_valid[1]_lut_out = GND;

KB1_rd_valid[1] = DFFEAS(KB1_rd_valid[1]_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , KB1_rd_valid[0], , , VCC);

--WE1L46 is std_1c20:inst|sdram_s1_arbitrator:the_sdram_s1|rdv_fifo_for_cpu_instruction_master_to_sdram_s1_module:rdv_fifo_for_cpu_instruction_master_to_sdram_s1|stage_2~5 at LC_X23_Y25_N0

--operation mode is normal

WE1L46 = WE1_full_3 & WE1L49Q # !WE1_full_3 & (NB1L24);

--WE1_full_2 is std_1c20:inst|sdram_s1_arbitrator:the_sdram_s1|rdv_fifo_for_cpu_instruction_master_to_sdram_s1_module:rdv_fifo_for_cpu_instruction_master_to_sdram_s1|full_2 at LC_X23_Y26_N4

--operation mode is normal

WE1_full_2_lut_out = NB1L37 & WE1_full_1 # !NB1L37 & (KB1_za_valid & (WE1_full_3) # !KB1_za_valid & WE1_full_1);

WE1_full_2 = DFFEAS(WE1_full_2_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , VE1L22, , , , );

--WE1L31 is std_1c20:inst|sdram_s1_arbitrator:the_sdram_s1|rdv_fifo_for_cpu_instruction_master_to_sdram_s1_module:rdv_fifo_for_cpu_instruction_master_to_sdram_s1|process10~1 at LC_X24_Y25_N0

--operation mode is normal

WE1L31 = KB1_za_valid # !WE1_full_1 & NB1L37;

--VE1L22 is std_1c20:inst|sdram_s1_arbitrator:the_sdram_s1|rdv_fifo_for_cpu_data_master_to_sdram_s1_module:rdv_fifo_for_cpu_data_master_to_sdram_s1|process1~3 at LC_X23_Y26_N2

--operation mode is normal

VE1L22 = NB1L37 & (!KB1_za_valid # !WE1_full_0) # !NB1L37 & (KB1_za_valid);

--LC1_internal_master_write_done is std_1c20:inst|clock_1:the_clock_1|clock_1_master_FSM:master_FSM|internal_master_write_done at LC_X48_Y28_N2

--operation mode is normal

LC1_internal_master_write_done_lut_out = LC1_internal_master_write_done $ (LC1_master_state[2] & !LC1_master_state[1] & LC1_master_state[0]);

LC1_internal_master_write_done = DFFEAS(LC1_internal_master_write_done_lut_out, GLOBAL(PLD_CLOCKINPUT[1]), E1_data_out, , , , , , );

--LC1_internal_master_read_done is std_1c20:inst|clock_1:the_clock_1|clock_1_master_FSM:master_FSM|internal_master_read_done at LC_X47_Y29_N5

--operation mode is normal

LC1_internal_master_read_done_lut_out = LC1_internal_master_read_done $ (!LC1_master_state[2] & LC1L2 & LC1L3);

LC1_internal_master_read_done = DFFEAS(LC1_internal_master_read_done_lut_out, GLOBAL(PLD_CLOCKINPUT[1]), E1_data_out, , , , , , );

--CC1_internal_master_write_done is std_1c20:inst|clock_0:the_clock_0|clock_0_master_FSM:master_FSM|internal_master_write_done at LC_X43_Y28_N2

--operation mode is normal

CC1_internal_master_write_done_lut_out = CC1_internal_master_write_done $ (CC1_master_state[2] & !CC1_master_state[1] & CC1_master_state[0]);

CC1_internal_master_write_done = DFFEAS(CC1_internal_master_write_done_lut_out, GLOBAL(PLD_CLKFB), GLOBAL(D1_data_out), , , , , , );

--CC1_internal_master_read_done is std_1c20:inst|clock_0:the_clock_0|clock_0_master_FSM:master_FSM|internal_master_read_done at LC_X44_Y28_N2

--operation mode is normal

CC1_internal_master_read_done_lut_out = CC1_internal_master_read_done $ (!CC1_master_state[2] & CC1L3 & CC1L2);

CC1_internal_master_read_done = DFFEAS(CC1_internal_master_read_done_lut_out, GLOBAL(PLD_CLKFB), GLOBAL(D1_data_out), , , , , , );

--VE1L33 is std_1c20:inst|sdram_s1_arbitrator:the_sdram_s1|rdv_fifo_for_cpu_data_master_to_sdram_s1_module:rdv_fifo_for_cpu_data_master_to_sdram_s1|stage_2~981 at LC_X23_Y25_N7

--operation mode is normal

VE1L33 = WE1_full_3 & VE1L36Q # !WE1_full_3 & (NB1L20);

--SD1_sr[22] is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|sr[22] at LC_X46_Y16_N2

--operation mode is normal

SD1_sr[22] = AMPP_FUNCTION(A1L5, SD1L9, SD1L21, SD1L22, SD1_sr[23], !C1_CLR_SIGNAL, SD1L12);

--KB1L661 is std_1c20:inst|sdram:the_sdram|Mux42~1481 at LC_X13_Y23_N0

--operation mode is normal

KB1L661 = KB1L615 & (KB1L660 & KB1L162 & !KB1_m_count[0] # !KB1L660 & (KB1_m_count[0])) # !KB1L615 & (KB1_m_count[0]);

--KB1L662 is std_1c20:inst|sdram:the_sdram|Mux42~1482 at LC_X13_Y23_N1

--operation mode is normal

KB1L662 = KB1_m_count[0] # KB1L660 & KB1L462 & KB1L615;

--KB1L663 is std_1c20:inst|sdram:the_sdram|Mux42~1483 at LC_X13_Y22_N6

--operation mode is normal

KB1L663 = !KB1_m_state[1] & !KB1_m_state[2] & KB1_m_state[0] & !KB1_m_state[7];

--KB1L664 is std_1c20:inst|sdram:the_sdram|Mux42~1484 at LC_X13_Y22_N7

--operation mode is normal

KB1L664 = KB1_refresh_request & TE1L152 & !KB1L991 & KB1L663;

--KB1L665 is std_1c20:inst|sdram:the_sdram|Mux42~1485 at LC_X13_Y23_N2

--operation mode is normal

KB1L665 = KB1L539 & (KB1_m_state[0] & (KB1L162) # !KB1_m_state[0] & KB1L253);

--KB1L666 is std_1c20:inst|sdram:the_sdram|Mux42~1486 at LC_X13_Y22_N5

--operation mode is normal

KB1L666 = KB1_m_state[2] # KB1_m_state[0] & (KB1_m_state[7] $ !KB1_m_state[1]);

--KB1L667 is std_1c20:inst|sdram:the_sdram|Mux42~1487 at LC_X11_Y23_N1

--operation mode is normal

KB1L667 = KB1_m_state[0] & (KB1_m_state[2] # KB1_m_state[7] $ KB1_m_state[1]);

--KB1L668 is std_1c20:inst|sdram:the_sdram|Mux42~1488 at LC_X13_Y23_N4

--operation mode is normal

KB1L668 = KB1L667 & (KB1_m_count[0] $ KB1L665 # !KB1L666) # !KB1L667 & KB1_m_count[0] & (KB1L666 # !KB1L665);

--KB1L669 is std_1c20:inst|sdram:the_sdram|Mux42~1489 at LC_X13_Y23_N8

--operation mode is normal

KB1L669 = KB1_m_state[5] & KB1_m_state[8] # !KB1_m_state[5] & (KB1_m_state[8] & (KB1L662) # !KB1_m_state[8] & KB1L671);

--KB1_i_refs[0] is std_1c20:inst|sdram:the_sdram|i_refs[0] at LC_X9_Y22_N3

--operation mode is normal

KB1_i_refs[0]_lut_out = KB1_i_refs[0] & (!KB1L152) # !KB1_i_refs[0] & KB1L155;

KB1_i_refs[0] = DFFEAS(KB1_i_refs[0]_lut_out, GLOBAL(QC2__clk0), VCC, , , , , , );

--RD1L35 is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|internal_MonDReg[1]~7323 at LC_X9_Y22_N0

--operation mode is normal

RD1L35 = AMPP_FUNCTION(KB1_i_state[1], KB1_i_refs[0]);

--KB1_i_refs[1] is std_1c20:inst|sdram:the_sdram|i_refs[1] at LC_X9_Y22_N8

--operation mode is normal

KB1_i_refs[1]_lut_out = KB1_i_refs[1] & (KB1L155 & !KB1_i_refs[0] # !KB1L152) # !KB1_i_refs[1] & (KB1L155 & KB1_i_refs[0]);

KB1_i_refs[1] = DFFEAS(KB1_i_refs[1]_lut_out, GLOBAL(QC2__clk0), VCC, , , , , , );

--KB1_i_refs[2] is std_1c20:inst|sdram:the_sdram|i_refs[2] at LC_X9_Y22_N6

--operation mode is normal

KB1_i_refs[2]_lut_out = KB1_i_refs[2] & (!KB1L108 & KB1L155 # !KB1L152) # !KB1_i_refs[2] & KB1L108 & KB1L155;

KB1_i_refs[2] = DFFEAS(KB1_i_refs[2]_lut_out, GLOBAL(QC2__clk0), VCC, , , , , , );

--RD1L36 is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|internal_MonDReg[1]~7325 at LC_X9_Y22_N2

--operation mode is normal

RD1L36 = AMPP_FUNCTION(KB1_i_state[2], KB1_i_state[1], KB1_i_state[0]);

--KB1_i_count[0] is std_1c20:inst|sdram:the_sdram|i_count[0] at LC_X10_Y22_N3

--operation mode is normal

KB1_i_count[0]_lut_out = KB1L480 & (KB1L161 $ KB1_i_count[0] # !KB1_i_state[0]);

KB1_i_count[0] = DFFEAS(KB1_i_count[0]_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , KB1L483, , , , );

--KB1L482 is std_1c20:inst|sdram:the_sdram|Mux10~94 at LC_X10_Y22_N4

--operation mode is normal

KB1L482 = KB1_i_count[2] & (KB1_i_count[1] # KB1_i_count[0]);

--KB1L483 is std_1c20:inst|sdram:the_sdram|Mux10~96 at LC_X10_Y22_N2

--operation mode is normal

KB1L483 = KB1_i_state[2] & (KB1_i_state[0] & KB1_i_state[1]) # !KB1_i_state[2] & (KB1_i_state[0] # KB1_i_state[1]);

--KB1L484 is std_1c20:inst|sdram:the_sdram|Mux11~67 at LC_X10_Y22_N0

--operation mode is normal

KB1L484 = KB1_i_count[1] & (KB1_i_count[0]) # !KB1_i_count[1] & KB1_i_count[2] & !KB1_i_count[0];

--ZE1_internal_tx_ready is std_1c20:inst|uart1:the_uart1|uart1_tx:the_uart1_tx|internal_tx_ready at LC_X47_Y24_N7

--operation mode is normal

ZE1_internal_tx_ready_lut_out = ZE1L42 & ZE1L43 & ZE1L44 # !ZE1L33;

ZE1_internal_tx_ready = DFFEAS(ZE1_internal_tx_ready_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--ZE1_baud_rate_counter[0] is std_1c20:inst|uart1:the_uart1|uart1_tx:the_uart1_tx|baud_rate_counter[0] at LC_X48_Y27_N0

--operation mode is arithmetic

ZE1_baud_rate_counter[0]_lut_out = !ZE1_baud_rate_counter[0];

ZE1_baud_rate_counter[0] = DFFEAS(ZE1_baud_rate_counter[0]_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , A1L277, , , ZE1L38);

--ZE1L4 is std_1c20:inst|uart1:the_uart1|uart1_tx:the_uart1_tx|baud_rate_counter[0]~54 at LC_X48_Y27_N0

--operation mode is arithmetic

ZE1L4_cout_0 = ZE1_baud_rate_counter[0];

ZE1L4 = CARRY(ZE1L4_cout_0);

--ZE1L5 is std_1c20:inst|uart1:the_uart1|uart1_tx:the_uart1_tx|baud_rate_counter[0]~54COUT1_406 at LC_X48_Y27_N0

--operation mode is arithmetic

ZE1L5_cout_1 = ZE1_baud_rate_counter[0];

ZE1L5 = CARRY(ZE1L5_cout_1);

--ZE1_baud_rate_counter[1] is std_1c20:inst|uart1:the_uart1|uart1_tx:the_uart1_tx|baud_rate_counter[1] at LC_X48_Y27_N1

--operation mode is arithmetic

ZE1_baud_rate_counter[1]_lut_out = ZE1_baud_rate_counter[1] $ (!ZE1L4);

ZE1_baud_rate_counter[1] = DFFEAS(ZE1_baud_rate_counter[1]_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , VCC, , , ZE1L38);

--ZE1L7 is std_1c20:inst|uart1:the_uart1|uart1_tx:the_uart1_tx|baud_rate_counter[1]~55 at LC_X48_Y27_N1

--operation mode is arithmetic

ZE1L7_cout_0 = !ZE1_baud_rate_counter[1] & (!ZE1L4);

ZE1L7 = CARRY(ZE1L7_cout_0);

--ZE1L8 is std_1c20:inst|uart1:the_uart1|uart1_tx:the_uart1_tx|baud_rate_counter[1]~55COUT1_408 at LC_X48_Y27_N1

--operation mode is arithmetic

ZE1L8_cout_1 = !ZE1_baud_rate_counter[1] & (!ZE1L5);

ZE1L8 = CARRY(ZE1L8_cout_1);

--ZE1_baud_rate_counter[2] is std_1c20:inst|uart1:the_uart1|uart1_tx:the_uart1_tx|baud_rate_counter[2] at LC_X48_Y27_N2

--operation mode is arithmetic

ZE1_baud_rate_counter[2]_lut_out = ZE1_baud_rate_counter[2] $ (ZE1L7);

ZE1_baud_rate_counter[2] = DFFEAS(ZE1_baud_rate_counter[2]_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , A1L277, , , ZE1L38);

--ZE1L10 is std_1c20:inst|uart1:the_uart1|uart1_tx:the_uart1_tx|baud_rate_counter[2]~56 at LC_X48_Y27_N2

--operation mode is arithmetic

ZE1L10_cout_0 = ZE1_baud_rate_counter[2] # !ZE1L7;

ZE1L10 = CARRY(ZE1L10_cout_0);

--ZE1L11 is std_1c20:inst|uart1:the_uart1|uart1_tx:the_uart1_tx|baud_rate_counter[2]~56COUT1_410 at LC_X48_Y27_N2

--operation mode is arithmetic

ZE1L11_cout_1 = ZE1_baud_rate_counter[2] # !ZE1L8;

ZE1L11 = CARRY(ZE1L11_cout_1);

--ZE1_baud_rate_counter[3] is std_1c20:inst|uart1:the_uart1|uart1_tx:the_uart1_tx|baud_rate_counter[3] at LC_X48_Y27_N3

--operation mode is arithmetic

ZE1_baud_rate_counter[3]_lut_out = ZE1_baud_rate_counter[3] $ !ZE1L10;

ZE1_baud_rate_counter[3] = DFFEAS(ZE1_baud_rate_counter[3]_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , A1L277, , , ZE1L38);

--ZE1L13 is std_1c20:inst|uart1:the_uart1|uart1_tx:the_uart1_tx|baud_rate_counter[3]~57 at LC_X48_Y27_N3

--operation mode is arithmetic

ZE1L13_cout_0 = !ZE1_baud_rate_counter[3] & !ZE1L10;

ZE1L13 = CARRY(ZE1L13_cout_0);

--ZE1L14 is std_1c20:inst|uart1:the_uart1|uart1_tx:the_uart1_tx|baud_rate_counter[3]~57COUT1_412 at LC_X48_Y27_N3

--operation mode is arithmetic

ZE1L14_cout_1 = !ZE1_baud_rate_counter[3] & !ZE1L11;

ZE1L14 = CARRY(ZE1L14_cout_1);

--ZE1L30 is std_1c20:inst|uart1:the_uart1|uart1_tx:the_uart1_tx|Equal0~137 at LC_X48_Y27_N9

--operation mode is normal

ZE1L30 = !ZE1_baud_rate_counter[1] & !ZE1_baud_rate_counter[3] & !ZE1_baud_rate_counter[2] & !ZE1_baud_rate_counter[0];

--ZE1_baud_rate_counter[4] is std_1c20:inst|uart1:the_uart1|uart1_tx:the_uart1_tx|baud_rate_counter[4] at LC_X48_Y27_N4

--operation mode is arithmetic

ZE1_baud_rate_counter[4]_lut_out = ZE1_baud_rate_counter[4] $ ZE1L13;

ZE1_baud_rate_counter[4] = DFFEAS(ZE1_baud_rate_counter[4]_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , VCC, , , ZE1L38);

--ZE1L16 is std_1c20:inst|uart1:the_uart1|uart1_tx:the_uart1_tx|baud_rate_counter[4]~58 at LC_X48_Y27_N4

--operation mode is arithmetic

ZE1L16 = ZE1L17;

--ZE1_baud_rate_counter[5] is std_1c20:inst|uart1:the_uart1|uart1_tx:the_uart1_tx|baud_rate_counter[5] at LC_X48_Y27_N5

--operation mode is arithmetic

ZE1_baud_rate_counter[5]_carry_eqn = ZE1L16;

ZE1_baud_rate_counter[5]_lut_out = ZE1_baud_rate_counter[5] $ !ZE1_baud_rate_counter[5]_carry_eqn;

ZE1_baud_rate_counter[5] = DFFEAS(ZE1_baud_rate_counter[5]_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , VCC, , , ZE1L38);

--ZE1L20 is std_1c20:inst|uart1:the_uart1|uart1_tx:the_uart1_tx|baud_rate_counter[5]~59 at LC_X48_Y27_N5

--operation mode is arithmetic

ZE1L20_cout_0 = !ZE1_baud_rate_counter[5] & !ZE1L16;

ZE1L20 = CARRY(ZE1L20_cout_0);

--ZE1L21 is std_1c20:inst|uart1:the_uart1|uart1_tx:the_uart1_tx|baud_rate_counter[5]~59COUT1_414 at LC_X48_Y27_N5

--operation mode is arithmetic

ZE1L21_cout_1 = !ZE1_baud_rate_counter[5] & !ZE1L16;

ZE1L21 = CARRY(ZE1L21_cout_1);

--ZE1_baud_rate_counter[6] is std_1c20:inst|uart1:the_uart1|uart1_tx:the_uart1_tx|baud_rate_counter[6] at LC_X48_Y27_N6

--operation mode is arithmetic

ZE1_baud_rate_counter[6]_carry_eqn = (!ZE1L16 & ZE1L20) # (ZE1L16 & ZE1L21);

ZE1_baud_rate_counter[6]_lut_out = ZE1_baud_rate_counter[6] $ (ZE1_baud_rate_counter[6]_carry_eqn);

ZE1_baud_rate_counter[6] = DFFEAS(ZE1_baud_rate_counter[6]_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , A1L277, , , ZE1L38);

--ZE1L23 is std_1c20:inst|uart1:the_uart1|uart1_tx:the_uart1_tx|baud_rate_counter[6]~60 at LC_X48_Y27_N6

--operation mode is arithmetic

ZE1L23_cout_0 = ZE1_baud_rate_counter[6] # !ZE1L20;

ZE1L23 = CARRY(ZE1L23_cout_0);

--ZE1L24 is std_1c20:inst|uart1:the_uart1|uart1_tx:the_uart1_tx|baud_rate_counter[6]~60COUT1_416 at LC_X48_Y27_N6

--operation mode is arithmetic

ZE1L24_cout_1 = ZE1_baud_rate_counter[6] # !ZE1L21;

ZE1L24 = CARRY(ZE1L24_cout_1);

--ZE1_baud_rate_counter[7] is std_1c20:inst|uart1:the_uart1|uart1_tx:the_uart1_tx|baud_rate_counter[7] at LC_X48_Y27_N7

--operation mode is arithmetic

ZE1_baud_rate_counter[7]_carry_eqn = (!ZE1L16 & ZE1L23) # (ZE1L16 & ZE1L24);

ZE1_baud_rate_counter[7]_lut_out = ZE1_baud_rate_counter[7] $ (!ZE1_baud_rate_counter[7]_carry_eqn);

ZE1_baud_rate_counter[7] = DFFEAS(ZE1_baud_rate_counter[7]_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , VCC, , , ZE1L38);

--ZE1L26 is std_1c20:inst|uart1:the_uart1|uart1_tx:the_uart1_tx|baud_rate_counter[7]~61 at LC_X48_Y27_N7

--operation mode is arithmetic

ZE1L26_cout_0 = !ZE1_baud_rate_counter[7] & (!ZE1L23);

ZE1L26 = CARRY(ZE1L26_cout_0);

--ZE1L27 is std_1c20:inst|uart1:the_uart1|uart1_tx:the_uart1_tx|baud_rate_counter[7]~61COUT1_418 at LC_X48_Y27_N7

--operation mode is arithmetic

ZE1L27_cout_1 = !ZE1_baud_rate_counter[7] & (!ZE1L24);

ZE1L27 = CARRY(ZE1L27_cout_1);

--ZE1L31 is std_1c20:inst|uart1:the_uart1|uart1_tx:the_uart1_tx|Equal0~138 at LC_X48_Y25_N9

--operation mode is normal

ZE1L31 = !ZE1_baud_rate_counter[5] & !ZE1_baud_rate_counter[6] & !ZE1_baud_rate_counter[7] & !ZE1_baud_rate_counter[4];

--ZE1_baud_rate_counter[8] is std_1c20:inst|uart1:the_uart1|uart1_tx:the_uart1_tx|baud_rate_counter[8] at LC_X48_Y27_N8

--operation mode is normal

ZE1_baud_rate_counter[8]_carry_eqn = (!ZE1L16 & ZE1L26) # (ZE1L16 & ZE1L27);

ZE1_baud_rate_counter[8]_lut_out = ZE1_baud_rate_counter[8] $ ZE1_baud_rate_counter[8]_carry_eqn;

ZE1_baud_rate_counter[8] = DFFEAS(ZE1_baud_rate_counter[8]_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , VCC, , , ZE1L38);

--XE1L18 is std_1c20:inst|uart1:the_uart1|uart1_regs:the_uart1_regs|Equal1~119 at LC_X47_Y23_N5

--operation mode is normal

XE1L18 = S1L1726Q & (!S1_M_alu_result[3] & !S1L1738Q);

--G1_d1_data_in[3] is std_1c20:inst|button_pio:the_button_pio|d1_data_in[3] at LC_X44_Y25_N4

--operation mode is normal

G1_d1_data_in[3]_lut_out = in_port_to_the_button_pio[3];

G1_d1_data_in[3] = DFFEAS(G1_d1_data_in[3]_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--G1L17 is std_1c20:inst|button_pio:the_button_pio|edge_capture~124 at LC_X44_Y20_N8

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

G1_d2_data_in[3]_qfbk = G1_d2_data_in[3];

G1L17 = G1_edge_capture[3] # G1_d2_data_in[3]_qfbk $ G1_d1_data_in[3];

--G1_d2_data_in[3] is std_1c20:inst|button_pio:the_button_pio|d2_data_in[3] at LC_X44_Y20_N8

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

G1_d2_data_in[3] = DFFEAS(G1L17, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , G1_d1_data_in[3], , , VCC);

--G1L16 is std_1c20:inst|button_pio:the_button_pio|edge_capture_wr_strobe~31 at LC_X45_Y22_N1

--operation mode is normal

G1L16 = S1_M_alu_result[3] & S1_internal_d_write & !T1_internal_cpu_data_master_waitrequest;

--G1_d1_data_in[1] is std_1c20:inst|button_pio:the_button_pio|d1_data_in[1] at LC_X44_Y20_N2

--operation mode is normal

G1_d1_data_in[1]_lut_out = in_port_to_the_button_pio[1];

G1_d1_data_in[1] = DFFEAS(G1_d1_data_in[1]_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--G1L18 is std_1c20:inst|button_pio:the_button_pio|edge_capture~126 at LC_X44_Y20_N6

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

G1_d2_data_in[1]_qfbk = G1_d2_data_in[1];

G1L18 = G1_edge_capture[1] # G1_d1_data_in[1] $ G1_d2_data_in[1]_qfbk;

--G1_d2_data_in[1] is std_1c20:inst|button_pio:the_button_pio|d2_data_in[1] at LC_X44_Y20_N6

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

G1_d2_data_in[1] = DFFEAS(G1L18, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , G1_d1_data_in[1], , , VCC);

--G1L26 is std_1c20:inst|button_pio:the_button_pio|process1~14 at LC_X45_Y20_N6

--operation mode is normal

G1L26 = S1L1743Q & !S1L1738Q & SB1L2 & G1L28;

--G1_d1_data_in[2] is std_1c20:inst|button_pio:the_button_pio|d1_data_in[2] at LC_X45_Y20_N8

--operation mode is normal

G1_d1_data_in[2]_lut_out = in_port_to_the_button_pio[2];

G1_d1_data_in[2] = DFFEAS(G1_d1_data_in[2]_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--G1L19 is std_1c20:inst|button_pio:the_button_pio|edge_capture~128 at LC_X45_Y20_N7

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

G1_d2_data_in[2]_qfbk = G1_d2_data_in[2];

G1L19 = G1_edge_capture[2] # G1_d1_data_in[2] $ G1_d2_data_in[2]_qfbk;

--G1_d2_data_in[2] is std_1c20:inst|button_pio:the_button_pio|d2_data_in[2] at LC_X45_Y20_N7

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

G1_d2_data_in[2] = DFFEAS(G1L19, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , G1_d1_data_in[2], , , VCC);

--G1_d1_data_in[0] is std_1c20:inst|button_pio:the_button_pio|d1_data_in[0] at LC_X45_Y22_N9

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

G1_d1_data_in[0]_lut_out = GND;

G1_d1_data_in[0] = DFFEAS(G1_d1_data_in[0]_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , in_port_to_the_button_pio[0], , , VCC);

--G1L20 is std_1c20:inst|button_pio:the_button_pio|edge_capture~130 at LC_X45_Y22_N7

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

G1_d2_data_in[0]_qfbk = G1_d2_data_in[0];

G1L20 = G1_edge_capture[0] # G1_d1_data_in[0] $ G1_d2_data_in[0]_qfbk;

--G1_d2_data_in[0] is std_1c20:inst|button_pio:the_button_pio|d2_data_in[0] at LC_X45_Y22_N7

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

G1_d2_data_in[0] = DFFEAS(G1L20, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , G1_d1_data_in[0], , , VCC);

--FD1L37 is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_avalon_reg:the_cpu_nios2_avalon_reg|take_action_oci_intr_mask_reg~10 at LC_X45_Y19_N4

--operation mode is normal

FD1L37 = AMPP_FUNCTION(FD1L2, FD1L1, RD1L70, V1L16);

--S1L1438 is std_1c20:inst|cpu:the_cpu|i_readdata_d1[8]~149 at LC_X42_Y22_N3

--operation mode is normal

S1L1438 = AMPP_FUNCTION(S1L1439Q, S1L524Q, S1L1450Q, S1L526Q);

--S1L824 is std_1c20:inst|cpu:the_cpu|E_op_eret~74 at LC_X30_Y15_N9

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

S1L824 = AMPP_FUNCTION(S1_E_iw[13], S1_E_iw[16]);

--S1_E_iw[15] is std_1c20:inst|cpu:the_cpu|E_iw[15] at LC_X30_Y15_N9

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

S1_E_iw[15] = AMPP_FUNCTION(QC2__clk0, S1_D_iw[15], F1_data_out, GND, S1_W_stall);

--S1L825 is std_1c20:inst|cpu:the_cpu|E_op_eret~75 at LC_X30_Y15_N8

--operation mode is normal

S1L825 = AMPP_FUNCTION(S1L824, S1L823, S1L822, S1_E_iw[11]);

--S1_E_wrctl_status is std_1c20:inst|cpu:the_cpu|E_wrctl_status at LC_X31_Y16_N4

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

S1_E_wrctl_status = AMPP_FUNCTION(S1_E_ctrl_wrctl_inst, S1_E_iw[8], S1_E_iw[7]);

--S1_E_iw[6] is std_1c20:inst|cpu:the_cpu|E_iw[6] at LC_X31_Y16_N4

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

S1_E_iw[6] = AMPP_FUNCTION(QC2__clk0, S1_D_iw[6], F1_data_out, GND, S1_W_stall);

--S1_E_ctrl_exception is std_1c20:inst|cpu:the_cpu|E_ctrl_exception at LC_X31_Y14_N6

--operation mode is normal

S1_E_ctrl_exception = AMPP_FUNCTION(QC2__clk0, S1L292, S1L1181, S1L1173, S1L306, F1_data_out, S1_W_stall);

--S1L2373 is std_1c20:inst|cpu:the_cpu|M_status_reg_pie_inst_nxt~0 at LC_X32_Y18_N9

--operation mode is normal

S1L2373 = AMPP_FUNCTION(S1_E_ctrl_break, S1_E_ctrl_exception);

--S1L2382Q is std_1c20:inst|cpu:the_cpu|M_status_reg_pie~165 at LC_X32_Y16_N3

--operation mode is normal

S1L2382Q = AMPP_FUNCTION(QC2__clk0, S1_W_stall, S1L1160, S1L2381, S1L2378, F1_data_out);

--S1L2375 is std_1c20:inst|cpu:the_cpu|M_status_reg_pie~157 at LC_X32_Y15_N7

--operation mode is normal

S1L2375 = AMPP_FUNCTION(S1L825, S1_E_wrctl_status);

--S1L2383Q is std_1c20:inst|cpu:the_cpu|M_status_reg_pie~166 at LC_X32_Y16_N7

--operation mode is normal

S1L2383Q = AMPP_FUNCTION(QC2__clk0, S1_E_ctrl_dst_data_sel_cmp, S1L675, S1L2375, S1L697, F1_data_out);

--S1L2384Q is std_1c20:inst|cpu:the_cpu|M_status_reg_pie~167 at LC_X32_Y15_N6

--operation mode is normal

S1L2384Q = AMPP_FUNCTION(QC2__clk0, S1L825, S1L2073, S1L2037, S1_E_iw[14], F1_data_out);

--BB1_fifo_AE is std_1c20:inst|jtag_uart:the_jtag_uart|fifo_AE at LC_X46_Y20_N8

--operation mode is normal

BB1_fifo_AE_lut_out = !RE1_safe_q[5] & !RE1_safe_q[4] & !BB1L65 & !NE1_b_full;

BB1_fifo_AE = DFFEAS(BB1_fifo_AE_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--BB1L64 is std_1c20:inst|jtag_uart:the_jtag_uart|ipen_AE~17 at LC_X45_Y24_N1

--operation mode is normal

BB1L64 = BB1_fifo_AE & (BB1_ien_AE);

--BB1_fifo_AF is std_1c20:inst|jtag_uart:the_jtag_uart|fifo_AF at LC_X47_Y21_N9

--operation mode is normal

BB1_fifo_AF_lut_out = BB1L22 & !BB1L66 & !BB1L67 & !BB1L3;

BB1_fifo_AF = DFFEAS(BB1_fifo_AF_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--BB1_pause_irq is std_1c20:inst|jtag_uart:the_jtag_uart|pause_irq at LC_X44_Y21_N0

--operation mode is normal

BB1_pause_irq_lut_out = NE2_b_non_empty & (GE1L39Q # !BB1_read_0 & BB1_pause_irq) # !NE2_b_non_empty & !BB1_read_0 & (BB1_pause_irq);

BB1_pause_irq = DFFEAS(BB1_pause_irq_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--T1L514 is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|p1_registered_cpu_data_master_readdata~2026 at LC_X44_Y21_N1

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

BB1_ien_AF_qfbk = BB1_ien_AF;

T1L514 = BB1_ien_AF_qfbk & (BB1_fifo_AF # BB1_pause_irq);

--BB1_ien_AF is std_1c20:inst|jtag_uart:the_jtag_uart|ien_AF at LC_X44_Y21_N1

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

BB1_ien_AF = DFFEAS(T1L514, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , BB1L61, S1_M_st_data[0], , , VCC);

--RB1_timeout_occurred is std_1c20:inst|sys_clk_timer:the_sys_clk_timer|timeout_occurred at LC_X53_Y23_N2

--operation mode is normal

RB1_timeout_occurred_lut_out = RB1L237 & (!SB1_cpu_data_master_requests_sys_clk_timer_s1 # !RB1L7 # !XE1L21);

RB1_timeout_occurred = DFFEAS(RB1_timeout_occurred_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--S1L1434 is std_1c20:inst|cpu:the_cpu|i_readdata_d1[7]~159 at LC_X42_Y24_N9

--operation mode is normal

S1L1434 = AMPP_FUNCTION(S1L1435Q, S1L1450Q, S1L518Q, S1L524Q);

--S1L1419Q is std_1c20:inst|cpu:the_cpu|i_readdata_d1[6]~99 at LC_X46_Y27_N3

--operation mode is normal

S1L1419Q = AMPP_FUNCTION(QC2__clk0, S1L1428, FE1_q_a[6], S1L1432, S1L1426, F1_data_out);

--S1L1420Q is std_1c20:inst|cpu:the_cpu|i_readdata_d1[6]~100 at LC_X38_Y21_N9

--operation mode is normal

S1L1420Q = AMPP_FUNCTION(QC2__clk0, S1L1424, S1L1451, FD1L1, S1L1422, F1_data_out);

--U1L35 is std_1c20:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_readdata[6]~2408 at LC_X37_Y23_N6

--operation mode is normal

U1L35 = S1L1420Q & (S1L1419Q);

--S1L1399Q is std_1c20:inst|cpu:the_cpu|i_readdata_d1[4]~86 at LC_X38_Y23_N7

--operation mode is normal

S1L1399Q = AMPP_FUNCTION(QC2__clk0, S1L1408, FE1_q_a[4], S1L1402, S1L1404, F1_data_out);

--S1L1400Q is std_1c20:inst|cpu:the_cpu|i_readdata_d1[4]~87 at LC_X38_Y20_N3

--operation mode is normal

S1L1400Q = AMPP_FUNCTION(QC2__clk0, FD1L28Q, S1L1451, WC1L7, WC1L21, F1_data_out);

--U1L29 is std_1c20:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_readdata[4]~2409 at LC_X38_Y20_N9

--operation mode is normal

U1L29 = S1L1399Q & S1L1400Q;

--S1L1470 is std_1c20:inst|cpu:the_cpu|i_readdata_d1[15]~146 at LC_X40_Y21_N8

--operation mode is normal

S1L1470 = AMPP_FUNCTION(S1L1450Q, S1L1471Q, S1L1472Q, S1L524Q);

--S1L1358Q is std_1c20:inst|cpu:the_cpu|i_readdata_d1[0]~90 at LC_X38_Y24_N8

--operation mode is normal

S1L1358Q = AMPP_FUNCTION(QC2__clk0, X1L10, U1L19, U1L18, U1L162, F1_data_out);

--S1L1386Q is std_1c20:inst|cpu:the_cpu|i_readdata_d1[3]~97 at LC_X34_Y24_N6

--operation mode is normal

S1L1386Q = AMPP_FUNCTION(QC2__clk0, V1L58, S1L1593Q, X1L16, F1_data_out);

--U1L17 is std_1c20:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_readdata[0]~2410 at LC_X38_Y24_N0

--operation mode is normal

U1L17 = S1L1358Q & (S1L1386Q # S1L1360);

--S1L1364Q is std_1c20:inst|cpu:the_cpu|i_readdata_d1[1]~92 at LC_X38_Y24_N1

--operation mode is normal

S1L1364Q = AMPP_FUNCTION(QC2__clk0, X1L10, U1L22, U1L163, U1L21, F1_data_out);

--U1L20 is std_1c20:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_readdata[1]~2411 at LC_X38_Y24_N3

--operation mode is normal

U1L20 = S1L1364Q & (S1L1366 # S1L1386Q);

--S1L1372Q is std_1c20:inst|cpu:the_cpu|i_readdata_d1[2]~94 at LC_X38_Y24_N5

--operation mode is normal

S1L1372Q = AMPP_FUNCTION(QC2__clk0, S1L1402, S1L1384, S1L1380, FE1_q_a[2], F1_data_out);

--U1L23 is std_1c20:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_readdata[2]~2412 at LC_X38_Y24_N9

--operation mode is normal

U1L23 = S1L1372Q & (S1L1386Q # S1L1374);

--S1L1385Q is std_1c20:inst|cpu:the_cpu|i_readdata_d1[3]~96 at LC_X44_Y24_N9

--operation mode is normal

S1L1385Q = AMPP_FUNCTION(QC2__clk0, S1L1398, FE1_q_a[3], S1L1392, S1L1394, F1_data_out);

--U1L26 is std_1c20:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_readdata[3]~2413 at LC_X43_Y24_N6

--operation mode is normal

U1L26 = S1L1385Q & (S1L1388 # S1L1386Q);

--S1L1409Q is std_1c20:inst|cpu:the_cpu|i_readdata_d1[5]~88 at LC_X46_Y23_N4

--operation mode is normal

S1L1409Q = AMPP_FUNCTION(QC2__clk0, FE1_q_a[5], S1L1412, S1L1418, S1L1414, F1_data_out);

--S1L1410Q is std_1c20:inst|cpu:the_cpu|i_readdata_d1[5]~89 at LC_X37_Y21_N8

--operation mode is normal

S1L1410Q = AMPP_FUNCTION(QC2__clk0, FD1L31Q, WC1L8, S1L1451, WC1L21, F1_data_out);

--U1L32 is std_1c20:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_readdata[5]~2414 at LC_X36_Y21_N0

--operation mode is normal

U1L32 = S1L1409Q & S1L1410Q;

--S1_i_readdata_d1[27] is std_1c20:inst|cpu:the_cpu|i_readdata_d1[27] at LC_X39_Y21_N3

--operation mode is normal

S1_i_readdata_d1[27] = AMPP_FUNCTION(QC2__clk0, WC1L31, S1L1451, U1L127, WC1L21, F1_data_out);

--S1_i_readdata_d1[28] is std_1c20:inst|cpu:the_cpu|i_readdata_d1[28] at LC_X38_Y20_N6

--operation mode is normal

S1_i_readdata_d1[28] = AMPP_FUNCTION(QC2__clk0, U1L130, S1L1451, WC1L32, WC1L21, F1_data_out);

--S1_i_readdata_d1[29] is std_1c20:inst|cpu:the_cpu|i_readdata_d1[29] at LC_X37_Y21_N4

--operation mode is normal

S1_i_readdata_d1[29] = AMPP_FUNCTION(QC2__clk0, S1L1451, WC1L33, U1L133, WC1L21, F1_data_out);

--S1_i_readdata_d1[30] is std_1c20:inst|cpu:the_cpu|i_readdata_d1[30] at LC_X38_Y21_N3

--operation mode is normal

S1_i_readdata_d1[30] = AMPP_FUNCTION(QC2__clk0, WC1L34, S1L1451, U1L136, WC1L21, F1_data_out);

--S1_i_readdata_d1[31] is std_1c20:inst|cpu:the_cpu|i_readdata_d1[31] at LC_X37_Y21_N1

--operation mode is normal

S1_i_readdata_d1[31] = AMPP_FUNCTION(QC2__clk0, S1L1451, U1L139, WC1L35, WC1L21, F1_data_out);

--G1L31 is std_1c20:inst|button_pio:the_button_pio|read_mux_out[2]~376 at LC_X45_Y20_N3

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

G1_irq_mask[2]_qfbk = G1_irq_mask[2];

G1L31 = S1L1726Q & (G1_edge_capture[2]) # !S1L1726Q & G1_irq_mask[2]_qfbk;

--G1_irq_mask[2] is std_1c20:inst|button_pio:the_button_pio|irq_mask[2] at LC_X45_Y20_N3

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

G1_irq_mask[2] = DFFEAS(G1L31, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , G1L26, S1_M_st_data[2], , , VCC);

--XE1_control_reg[2] is std_1c20:inst|uart1:the_uart1|uart1_regs:the_uart1_regs|control_reg[2] at LC_X48_Y22_N6

--operation mode is normal

XE1_control_reg[2]_lut_out = S1_M_st_data[2];

XE1_control_reg[2] = DFFEAS(XE1_control_reg[2]_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , XE1L14, , , , );

--XE1L52 is std_1c20:inst|uart1:the_uart1|uart1_regs:the_uart1_regs|selected_read_data[2]~677 at LC_X48_Y23_N7

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

XE1_internal_tx_data[2]_qfbk = XE1_internal_tx_data[2];

XE1L52 = S1_M_alu_result[3] & XE1_control_reg[2] # !S1_M_alu_result[3] & (XE1_internal_tx_data[2]_qfbk);

--XE1_internal_tx_data[2] is std_1c20:inst|uart1:the_uart1|uart1_regs:the_uart1_regs|internal_tx_data[2] at LC_X48_Y23_N7

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

XE1_internal_tx_data[2] = DFFEAS(XE1L52, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , XE1L64, S1_M_st_data[2], , , VCC);

--YE1_break_detect is std_1c20:inst|uart1:the_uart1|uart1_rx:the_uart1_rx|break_detect at LC_X52_Y22_N0

--operation mode is normal

YE1_break_detect_lut_out = YE1L40 & (!XE1L20 # !XE1L13);

YE1_break_detect = DFFEAS(YE1_break_detect_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--XE1L53 is std_1c20:inst|uart1:the_uart1|uart1_regs:the_uart1_regs|selected_read_data[2]~678 at LC_X52_Y22_N8

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

YE1_rx_data[2]_qfbk = YE1_rx_data[2];

XE1L53 = S1_M_alu_result[3] & (YE1_break_detect) # !S1_M_alu_result[3] & YE1_rx_data[2]_qfbk;

--YE1_rx_data[2] is std_1c20:inst|uart1:the_uart1|uart1_rx:the_uart1_rx|rx_data[2] at LC_X52_Y22_N8

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

YE1_rx_data[2] = DFFEAS(XE1L53, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , YE1_got_new_char, YE1_unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[3], , , VCC);

--RB1_counter_snapshot[2] is std_1c20:inst|sys_clk_timer:the_sys_clk_timer|counter_snapshot[2] at LC_X53_Y26_N4

--operation mode is normal

RB1_counter_snapshot[2]_lut_out = !RB1_internal_counter[2];

RB1_counter_snapshot[2] = DFFEAS(RB1_counter_snapshot[2]_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , RB1L235, , , , );

--XE1L19 is std_1c20:inst|uart1:the_uart1|uart1_regs:the_uart1_regs|Equal1~120 at LC_X54_Y25_N0

--operation mode is normal

XE1L19 = !S1_M_alu_result[3] & !S1L1726Q & S1L1738Q;

--RB1_period_h_register[2] is std_1c20:inst|sys_clk_timer:the_sys_clk_timer|period_h_register[2] at LC_X53_Y25_N2

--operation mode is normal

RB1_period_h_register[2]_lut_out = !S1_M_st_data[2];

RB1_period_h_register[2] = DFFEAS(RB1_period_h_register[2]_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , RB1_period_h_wr_strobe, , , , );

--RB1L190 is std_1c20:inst|sys_clk_timer:the_sys_clk_timer|read_mux_out[2]~1238 at LC_X53_Y25_N3

--operation mode is normal

RB1L190 = RB1_counter_snapshot[2] & (XE1L19 # !RB1_period_h_register[2] & XE1L15) # !RB1_counter_snapshot[2] & (!RB1_period_h_register[2] & XE1L15);

--RB1_counter_snapshot[18] is std_1c20:inst|sys_clk_timer:the_sys_clk_timer|counter_snapshot[18] at LC_X52_Y23_N3

--operation mode is normal

RB1_counter_snapshot[18]_lut_out = !RB1_internal_counter[18];

RB1_counter_snapshot[18] = DFFEAS(RB1_counter_snapshot[18]_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , RB1L235, , , , );

--RB1L191 is std_1c20:inst|sys_clk_timer:the_sys_clk_timer|read_mux_out[2]~1239 at LC_X52_Y23_N2

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

RB1_control_register[2]_qfbk = RB1_control_register[2];

RB1L191 = XE1L17 & (S1L1738Q & RB1_counter_snapshot[18] # !S1L1738Q & (RB1_control_register[2]_qfbk));

--RB1_control_register[2] is std_1c20:inst|sys_clk_timer:the_sys_clk_timer|control_register[2] at LC_X52_Y23_N2

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

RB1_control_register[2] = DFFEAS(RB1L191, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , RB1_control_wr_strobe, S1_M_st_data[2], , , VCC);

--XE1L20 is std_1c20:inst|uart1:the_uart1|uart1_regs:the_uart1_regs|Equal1~121 at LC_X51_Y23_N5

--operation mode is normal

XE1L20 = S1_M_alu_result[3] & (!S1L1726Q & !S1L1738Q);

--RB1_period_l_register[2] is std_1c20:inst|sys_clk_timer:the_sys_clk_timer|period_l_register[2] at LC_X51_Y27_N2

--operation mode is normal

RB1_period_l_register[2]_lut_out = !S1_M_st_data[2];

RB1_period_l_register[2] = DFFEAS(RB1_period_l_register[2]_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , RB1_period_l_wr_strobe, , , , );

--J1_slave_readdata[2] is std_1c20:inst|clock_0:the_clock_0|slave_readdata[2] at LC_X45_Y27_N0

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

J1_slave_readdata[2]_lut_out = GND;

J1_slave_readdata[2] = DFFEAS(J1_slave_readdata[2]_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , J1_slave_readdata_p1[2], , , VCC);

--T1L472 is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|p1_registered_cpu_data_master_readdata[2]~2027 at LC_X45_Y27_N9

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

M1_slave_readdata[2]_qfbk = M1_slave_readdata[2];

T1L472 = S1L1743Q & (M1_slave_readdata[2]_qfbk) # !S1L1743Q & J1_slave_readdata[2] # !K1L6;

--M1_slave_readdata[2] is std_1c20:inst|clock_1:the_clock_1|slave_readdata[2] at LC_X45_Y27_N9

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

M1_slave_readdata[2] = DFFEAS(T1L472, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , M1_slave_readdata_p1[2], , , VCC);

--SE2_q_b[2] is std_1c20:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_r:the_jtag_uart_scfifo_r|scfifo:rfifo|scfifo_jf21:auto_generated|a_dpfifo_ml21:dpfifo|dpram_j921:FIFOram|altsyncram_nll1:altsyncram1|q_b[2] at M4K_X49_Y21

--RAM Block Operation Mode: Simple Dual-Port

--Port A Depth: 64, Port A Width: 8, Port B Depth: 64, Port B Width: 8

--Port A Logical Depth: 64, Port A Logical Width: 8, Port B Logical Depth: 64, Port B Logical Width: 8

--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered

SE2_q_b[2]_PORT_A_data_in = BUS(GE1_wdata[2], GE1_wdata[3], GE1_wdata[7], GE1_wdata[6], GE1_wdata[4], GE1_wdata[5], GE1_wdata[0], GE1_wdata[1]);

SE2_q_b[2]_PORT_A_data_in_reg = DFFE(SE2_q_b[2]_PORT_A_data_in, SE2_q_b[2]_clock_0, , , SE2_q_b[2]_clock_enable_0);

SE2_q_b[2]_PORT_A_address = BUS(QE4_safe_q[0], QE4_safe_q[1], QE4_safe_q[2], QE4_safe_q[3], QE4_safe_q[4], QE4_safe_q[5]);

SE2_q_b[2]_PORT_A_address_reg = DFFE(SE2_q_b[2]_PORT_A_address, SE2_q_b[2]_clock_0, , , SE2_q_b[2]_clock_enable_0);

SE2_q_b[2]_PORT_B_address = BUS(QE3_safe_q[0], QE3_safe_q[1], QE3_safe_q[2], QE3_safe_q[3], QE3_safe_q[4], QE3_safe_q[5]);

SE2_q_b[2]_PORT_B_address_reg = DFFE(SE2_q_b[2]_PORT_B_address, SE2_q_b[2]_clock_1, , , SE2_q_b[2]_clock_enable_1);

SE2_q_b[2]_PORT_A_write_enable = VCC;

SE2_q_b[2]_PORT_A_write_enable_reg = DFFE(SE2_q_b[2]_PORT_A_write_enable, SE2_q_b[2]_clock_0, , , SE2_q_b[2]_clock_enable_0);

SE2_q_b[2]_PORT_B_read_enable = VCC;

SE2_q_b[2]_PORT_B_read_enable_reg = DFFE(SE2_q_b[2]_PORT_B_read_enable, SE2_q_b[2]_clock_1, , , SE2_q_b[2]_clock_enable_1);

SE2_q_b[2]_clock_0 = GLOBAL(QC2__clk0);

SE2_q_b[2]_clock_1 = GLOBAL(QC2__clk0);

SE2_q_b[2]_clock_enable_0 = BB1_wr_rfifo;

SE2_q_b[2]_clock_enable_1 = BB1L78;

SE2_q_b[2]_PORT_B_data_out = MEMORY(SE2_q_b[2]_PORT_A_data_in_reg, , SE2_q_b[2]_PORT_A_address_reg, SE2_q_b[2]_PORT_B_address_reg, SE2_q_b[2]_PORT_A_write_enable_reg, SE2_q_b[2]_PORT_B_read_enable_reg, , , SE2_q_b[2]_clock_0, SE2_q_b[2]_clock_1, SE2_q_b[2]_clock_enable_0, SE2_q_b[2]_clock_enable_1, , );

SE2_q_b[2] = SE2_q_b[2]_PORT_B_data_out[0];

--SE2_q_b[1] is std_1c20:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_r:the_jtag_uart_scfifo_r|scfifo:rfifo|scfifo_jf21:auto_generated|a_dpfifo_ml21:dpfifo|dpram_j921:FIFOram|altsyncram_nll1:altsyncram1|q_b[1] at M4K_X49_Y21

SE2_q_b[2]_PORT_A_data_in = BUS(GE1_wdata[2], GE1_wdata[3], GE1_wdata[7], GE1_wdata[6], GE1_wdata[4], GE1_wdata[5], GE1_wdata[0], GE1_wdata[1]);

SE2_q_b[2]_PORT_A_data_in_reg = DFFE(SE2_q_b[2]_PORT_A_data_in, SE2_q_b[2]_clock_0, , , SE2_q_b[2]_clock_enable_0);

SE2_q_b[2]_PORT_A_address = BUS(QE4_safe_q[0], QE4_safe_q[1], QE4_safe_q[2], QE4_safe_q[3], QE4_safe_q[4], QE4_safe_q[5]);

SE2_q_b[2]_PORT_A_address_reg = DFFE(SE2_q_b[2]_PORT_A_address, SE2_q_b[2]_clock_0, , , SE2_q_b[2]_clock_enable_0);

SE2_q_b[2]_PORT_B_address = BUS(QE3_safe_q[0], QE3_safe_q[1], QE3_safe_q[2], QE3_safe_q[3], QE3_safe_q[4], QE3_safe_q[5]);

SE2_q_b[2]_PORT_B_address_reg = DFFE(SE2_q_b[2]_PORT_B_address, SE2_q_b[2]_clock_1, , , SE2_q_b[2]_clock_enable_1);

SE2_q_b[2]_PORT_A_write_enable = VCC;

SE2_q_b[2]_PORT_A_write_enable_reg = DFFE(SE2_q_b[2]_PORT_A_write_enable, SE2_q_b[2]_clock_0, , , SE2_q_b[2]_clock_enable_0);

SE2_q_b[2]_PORT_B_read_enable = VCC;

SE2_q_b[2]_PORT_B_read_enable_reg = DFFE(SE2_q_b[2]_PORT_B_read_enable, SE2_q_b[2]_clock_1, , , SE2_q_b[2]_clock_enable_1);

SE2_q_b[2]_clock_0 = GLOBAL(QC2__clk0);

SE2_q_b[2]_clock_1 = GLOBAL(QC2__clk0);

SE2_q_b[2]_clock_enable_0 = BB1_wr_rfifo;

SE2_q_b[2]_clock_enable_1 = BB1L78;

SE2_q_b[2]_PORT_B_data_out = MEMORY(SE2_q_b[2]_PORT_A_data_in_reg, , SE2_q_b[2]_PORT_A_address_reg, SE2_q_b[2]_PORT_B_address_reg, SE2_q_b[2]_PORT_A_write_enable_reg, SE2_q_b[2]_PORT_B_read_enable_reg, , , SE2_q_b[2]_clock_0, SE2_q_b[2]_clock_1, SE2_q_b[2]_clock_enable_0, SE2_q_b[2]_clock_enable_1, , );

SE2_q_b[1] = SE2_q_b[2]_PORT_B_data_out[7];

--SE2_q_b[0] is std_1c20:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_r:the_jtag_uart_scfifo_r|scfifo:rfifo|scfifo_jf21:auto_generated|a_dpfifo_ml21:dpfifo|dpram_j921:FIFOram|altsyncram_nll1:altsyncram1|q_b[0] at M4K_X49_Y21

SE2_q_b[2]_PORT_A_data_in = BUS(GE1_wdata[2], GE1_wdata[3], GE1_wdata[7], GE1_wdata[6], GE1_wdata[4], GE1_wdata[5], GE1_wdata[0], GE1_wdata[1]);

SE2_q_b[2]_PORT_A_data_in_reg = DFFE(SE2_q_b[2]_PORT_A_data_in, SE2_q_b[2]_clock_0, , , SE2_q_b[2]_clock_enable_0);

SE2_q_b[2]_PORT_A_address = BUS(QE4_safe_q[0], QE4_safe_q[1], QE4_safe_q[2], QE4_safe_q[3], QE4_safe_q[4], QE4_safe_q[5]);

SE2_q_b[2]_PORT_A_address_reg = DFFE(SE2_q_b[2]_PORT_A_address, SE2_q_b[2]_clock_0, , , SE2_q_b[2]_clock_enable_0);

SE2_q_b[2]_PORT_B_address = BUS(QE3_safe_q[0], QE3_safe_q[1], QE3_safe_q[2], QE3_safe_q[3], QE3_safe_q[4], QE3_safe_q[5]);

SE2_q_b[2]_PORT_B_address_reg = DFFE(SE2_q_b[2]_PORT_B_address, SE2_q_b[2]_clock_1, , , SE2_q_b[2]_clock_enable_1);

SE2_q_b[2]_PORT_A_write_enable = VCC;

SE2_q_b[2]_PORT_A_write_enable_reg = DFFE(SE2_q_b[2]_PORT_A_write_enable, SE2_q_b[2]_clock_0, , , SE2_q_b[2]_clock_enable_0);

SE2_q_b[2]_PORT_B_read_enable = VCC;

SE2_q_b[2]_PORT_B_read_enable_reg = DFFE(SE2_q_b[2]_PORT_B_read_enable, SE2_q_b[2]_clock_1, , , SE2_q_b[2]_clock_enable_1);

SE2_q_b[2]_clock_0 = GLOBAL(QC2__clk0);

SE2_q_b[2]_clock_1 = GLOBAL(QC2__clk0);

SE2_q_b[2]_clock_enable_0 = BB1_wr_rfifo;

SE2_q_b[2]_clock_enable_1 = BB1L78;

SE2_q_b[2]_PORT_B_data_out = MEMORY(SE2_q_b[2]_PORT_A_data_in_reg, , SE2_q_b[2]_PORT_A_address_reg, SE2_q_b[2]_PORT_B_address_reg, SE2_q_b[2]_PORT_A_write_enable_reg, SE2_q_b[2]_PORT_B_read_enable_reg, , , SE2_q_b[2]_clock_0, SE2_q_b[2]_clock_1, SE2_q_b[2]_clock_enable_0, SE2_q_b[2]_clock_enable_1, , );

SE2_q_b[0] = SE2_q_b[2]_PORT_B_data_out[6];

--SE2_q_b[5] is std_1c20:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_r:the_jtag_uart_scfifo_r|scfifo:rfifo|scfifo_jf21:auto_generated|a_dpfifo_ml21:dpfifo|dpram_j921:FIFOram|altsyncram_nll1:altsyncram1|q_b[5] at M4K_X49_Y21

SE2_q_b[2]_PORT_A_data_in = BUS(GE1_wdata[2], GE1_wdata[3], GE1_wdata[7], GE1_wdata[6], GE1_wdata[4], GE1_wdata[5], GE1_wdata[0], GE1_wdata[1]);

SE2_q_b[2]_PORT_A_data_in_reg = DFFE(SE2_q_b[2]_PORT_A_data_in, SE2_q_b[2]_clock_0, , , SE2_q_b[2]_clock_enable_0);

SE2_q_b[2]_PORT_A_address = BUS(QE4_safe_q[0], QE4_safe_q[1], QE4_safe_q[2], QE4_safe_q[3], QE4_safe_q[4], QE4_safe_q[5]);

SE2_q_b[2]_PORT_A_address_reg = DFFE(SE2_q_b[2]_PORT_A_address, SE2_q_b[2]_clock_0, , , SE2_q_b[2]_clock_enable_0);

SE2_q_b[2]_PORT_B_address = BUS(QE3_safe_q[0], QE3_safe_q[1], QE3_safe_q[2], QE3_safe_q[3], QE3_safe_q[4], QE3_safe_q[5]);

SE2_q_b[2]_PORT_B_address_reg = DFFE(SE2_q_b[2]_PORT_B_address, SE2_q_b[2]_clock_1, , , SE2_q_b[2]_clock_enable_1);

SE2_q_b[2]_PORT_A_write_enable = VCC;

SE2_q_b[2]_PORT_A_write_enable_reg = DFFE(SE2_q_b[2]_PORT_A_write_enable, SE2_q_b[2]_clock_0, , , SE2_q_b[2]_clock_enable_0);

SE2_q_b[2]_PORT_B_read_enable = VCC;

SE2_q_b[2]_PORT_B_read_enable_reg = DFFE(SE2_q_b[2]_PORT_B_read_enable, SE2_q_b[2]_clock_1, , , SE2_q_b[2]_clock_enable_1);

SE2_q_b[2]_clock_0 = GLOBAL(QC2__clk0);

SE2_q_b[2]_clock_1 = GLOBAL(QC2__clk0);

SE2_q_b[2]_clock_enable_0 = BB1_wr_rfifo;

SE2_q_b[2]_clock_enable_1 = BB1L78;

SE2_q_b[2]_PORT_B_data_out = MEMORY(SE2_q_b[2]_PORT_A_data_in_reg, , SE2_q_b[2]_PORT_A_address_reg, SE2_q_b[2]_PORT_B_address_reg, SE2_q_b[2]_PORT_A_write_enable_reg, SE2_q_b[2]_PORT_B_read_enable_reg, , , SE2_q_b[2]_clock_0, SE2_q_b[2]_clock_1, SE2_q_b[2]_clock_enable_0, SE2_q_b[2]_clock_enable_1, , );

SE2_q_b[5] = SE2_q_b[2]_PORT_B_data_out[5];

--SE2_q_b[4] is std_1c20:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_r:the_jtag_uart_scfifo_r|scfifo:rfifo|scfifo_jf21:auto_generated|a_dpfifo_ml21:dpfifo|dpram_j921:FIFOram|altsyncram_nll1:altsyncram1|q_b[4] at M4K_X49_Y21

SE2_q_b[2]_PORT_A_data_in = BUS(GE1_wdata[2], GE1_wdata[3], GE1_wdata[7], GE1_wdata[6], GE1_wdata[4], GE1_wdata[5], GE1_wdata[0], GE1_wdata[1]);

SE2_q_b[2]_PORT_A_data_in_reg = DFFE(SE2_q_b[2]_PORT_A_data_in, SE2_q_b[2]_clock_0, , , SE2_q_b[2]_clock_enable_0);

SE2_q_b[2]_PORT_A_address = BUS(QE4_safe_q[0], QE4_safe_q[1], QE4_safe_q[2], QE4_safe_q[3], QE4_safe_q[4], QE4_safe_q[5]);

SE2_q_b[2]_PORT_A_address_reg = DFFE(SE2_q_b[2]_PORT_A_address, SE2_q_b[2]_clock_0, , , SE2_q_b[2]_clock_enable_0);

SE2_q_b[2]_PORT_B_address = BUS(QE3_safe_q[0], QE3_safe_q[1], QE3_safe_q[2], QE3_safe_q[3], QE3_safe_q[4], QE3_safe_q[5]);

SE2_q_b[2]_PORT_B_address_reg = DFFE(SE2_q_b[2]_PORT_B_address, SE2_q_b[2]_clock_1, , , SE2_q_b[2]_clock_enable_1);

SE2_q_b[2]_PORT_A_write_enable = VCC;

SE2_q_b[2]_PORT_A_write_enable_reg = DFFE(SE2_q_b[2]_PORT_A_write_enable, SE2_q_b[2]_clock_0, , , SE2_q_b[2]_clock_enable_0);

SE2_q_b[2]_PORT_B_read_enable = VCC;

SE2_q_b[2]_PORT_B_read_enable_reg = DFFE(SE2_q_b[2]_PORT_B_read_enable, SE2_q_b[2]_clock_1, , , SE2_q_b[2]_clock_enable_1);

SE2_q_b[2]_clock_0 = GLOBAL(QC2__clk0);

SE2_q_b[2]_clock_1 = GLOBAL(QC2__clk0);

SE2_q_b[2]_clock_enable_0 = BB1_wr_rfifo;

SE2_q_b[2]_clock_enable_1 = BB1L78;

SE2_q_b[2]_PORT_B_data_out = MEMORY(SE2_q_b[2]_PORT_A_data_in_reg, , SE2_q_b[2]_PORT_A_address_reg, SE2_q_b[2]_PORT_B_address_reg, SE2_q_b[2]_PORT_A_write_enable_reg, SE2_q_b[2]_PORT_B_read_enable_reg, , , SE2_q_b[2]_clock_0, SE2_q_b[2]_clock_1, SE2_q_b[2]_clock_enable_0, SE2_q_b[2]_clock_enable_1, , );

SE2_q_b[4] = SE2_q_b[2]_PORT_B_data_out[4];

--SE2_q_b[6] is std_1c20:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_r:the_jtag_uart_scfifo_r|scfifo:rfifo|scfifo_jf21:auto_generated|a_dpfifo_ml21:dpfifo|dpram_j921:FIFOram|altsyncram_nll1:altsyncram1|q_b[6] at M4K_X49_Y21

SE2_q_b[2]_PORT_A_data_in = BUS(GE1_wdata[2], GE1_wdata[3], GE1_wdata[7], GE1_wdata[6], GE1_wdata[4], GE1_wdata[5], GE1_wdata[0], GE1_wdata[1]);

SE2_q_b[2]_PORT_A_data_in_reg = DFFE(SE2_q_b[2]_PORT_A_data_in, SE2_q_b[2]_clock_0, , , SE2_q_b[2]_clock_enable_0);

SE2_q_b[2]_PORT_A_address = BUS(QE4_safe_q[0], QE4_safe_q[1], QE4_safe_q[2], QE4_safe_q[3], QE4_safe_q[4], QE4_safe_q[5]);

SE2_q_b[2]_PORT_A_address_reg = DFFE(SE2_q_b[2]_PORT_A_address, SE2_q_b[2]_clock_0, , , SE2_q_b[2]_clock_enable_0);

SE2_q_b[2]_PORT_B_address = BUS(QE3_safe_q[0], QE3_safe_q[1], QE3_safe_q[2], QE3_safe_q[3], QE3_safe_q[4], QE3_safe_q[5]);

SE2_q_b[2]_PORT_B_address_reg = DFFE(SE2_q_b[2]_PORT_B_address, SE2_q_b[2]_clock_1, , , SE2_q_b[2]_clock_enable_1);

SE2_q_b[2]_PORT_A_write_enable = VCC;

SE2_q_b[2]_PORT_A_write_enable_reg = DFFE(SE2_q_b[2]_PORT_A_write_enable, SE2_q_b[2]_clock_0, , , SE2_q_b[2]_clock_enable_0);

SE2_q_b[2]_PORT_B_read_enable = VCC;

SE2_q_b[2]_PORT_B_read_enable_reg = DFFE(SE2_q_b[2]_PORT_B_read_enable, SE2_q_b[2]_clock_1, , , SE2_q_b[2]_clock_enable_1);

SE2_q_b[2]_clock_0 = GLOBAL(QC2__clk0);

SE2_q_b[2]_clock_1 = GLOBAL(QC2__clk0);

SE2_q_b[2]_clock_enable_0 = BB1_wr_rfifo;

SE2_q_b[2]_clock_enable_1 = BB1L78;

SE2_q_b[2]_PORT_B_data_out = MEMORY(SE2_q_b[2]_PORT_A_data_in_reg, , SE2_q_b[2]_PORT_A_address_reg, SE2_q_b[2]_PORT_B_address_reg, SE2_q_b[2]_PORT_A_write_enable_reg, SE2_q_b[2]_PORT_B_read_enable_reg, , , SE2_q_b[2]_clock_0, SE2_q_b[2]_clock_1, SE2_q_b[2]_clock_enable_0, SE2_q_b[2]_clock_enable_1, , );

SE2_q_b[6] = SE2_q_b[2]_PORT_B_data_out[3];

--SE2_q_b[7] is std_1c20:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_r:the_jtag_uart_scfifo_r|scfifo:rfifo|scfifo_jf21:auto_generated|a_dpfifo_ml21:dpfifo|dpram_j921:FIFOram|altsyncram_nll1:altsyncram1|q_b[7] at M4K_X49_Y21

SE2_q_b[2]_PORT_A_data_in = BUS(GE1_wdata[2], GE1_wdata[3], GE1_wdata[7], GE1_wdata[6], GE1_wdata[4], GE1_wdata[5], GE1_wdata[0], GE1_wdata[1]);

SE2_q_b[2]_PORT_A_data_in_reg = DFFE(SE2_q_b[2]_PORT_A_data_in, SE2_q_b[2]_clock_0, , , SE2_q_b[2]_clock_enable_0);

SE2_q_b[2]_PORT_A_address = BUS(QE4_safe_q[0], QE4_safe_q[1], QE4_safe_q[2], QE4_safe_q[3], QE4_safe_q[4], QE4_safe_q[5]);

SE2_q_b[2]_PORT_A_address_reg = DFFE(SE2_q_b[2]_PORT_A_address, SE2_q_b[2]_clock_0, , , SE2_q_b[2]_clock_enable_0);

SE2_q_b[2]_PORT_B_address = BUS(QE3_safe_q[0], QE3_safe_q[1], QE3_safe_q[2], QE3_safe_q[3], QE3_safe_q[4], QE3_safe_q[5]);

SE2_q_b[2]_PORT_B_address_reg = DFFE(SE2_q_b[2]_PORT_B_address, SE2_q_b[2]_clock_1, , , SE2_q_b[2]_clock_enable_1);

SE2_q_b[2]_PORT_A_write_enable = VCC;

SE2_q_b[2]_PORT_A_write_enable_reg = DFFE(SE2_q_b[2]_PORT_A_write_enable, SE2_q_b[2]_clock_0, , , SE2_q_b[2]_clock_enable_0);

SE2_q_b[2]_PORT_B_read_enable = VCC;

SE2_q_b[2]_PORT_B_read_enable_reg = DFFE(SE2_q_b[2]_PORT_B_read_enable, SE2_q_b[2]_clock_1, , , SE2_q_b[2]_clock_enable_1);

SE2_q_b[2]_clock_0 = GLOBAL(QC2__clk0);

SE2_q_b[2]_clock_1 = GLOBAL(QC2__clk0);

SE2_q_b[2]_clock_enable_0 = BB1_wr_rfifo;

SE2_q_b[2]_clock_enable_1 = BB1L78;

SE2_q_b[2]_PORT_B_data_out = MEMORY(SE2_q_b[2]_PORT_A_data_in_reg, , SE2_q_b[2]_PORT_A_address_reg, SE2_q_b[2]_PORT_B_address_reg, SE2_q_b[2]_PORT_A_write_enable_reg, SE2_q_b[2]_PORT_B_read_enable_reg, , , SE2_q_b[2]_clock_0, SE2_q_b[2]_clock_1, SE2_q_b[2]_clock_enable_0, SE2_q_b[2]_clock_enable_1, , );

SE2_q_b[7] = SE2_q_b[2]_PORT_B_data_out[2];

--SE2_q_b[3] is std_1c20:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_r:the_jtag_uart_scfifo_r|scfifo:rfifo|scfifo_jf21:auto_generated|a_dpfifo_ml21:dpfifo|dpram_j921:FIFOram|altsyncram_nll1:altsyncram1|q_b[3] at M4K_X49_Y21

SE2_q_b[2]_PORT_A_data_in = BUS(GE1_wdata[2], GE1_wdata[3], GE1_wdata[7], GE1_wdata[6], GE1_wdata[4], GE1_wdata[5], GE1_wdata[0], GE1_wdata[1]);

SE2_q_b[2]_PORT_A_data_in_reg = DFFE(SE2_q_b[2]_PORT_A_data_in, SE2_q_b[2]_clock_0, , , SE2_q_b[2]_clock_enable_0);

SE2_q_b[2]_PORT_A_address = BUS(QE4_safe_q[0], QE4_safe_q[1], QE4_safe_q[2], QE4_safe_q[3], QE4_safe_q[4], QE4_safe_q[5]);

SE2_q_b[2]_PORT_A_address_reg = DFFE(SE2_q_b[2]_PORT_A_address, SE2_q_b[2]_clock_0, , , SE2_q_b[2]_clock_enable_0);

SE2_q_b[2]_PORT_B_address = BUS(QE3_safe_q[0], QE3_safe_q[1], QE3_safe_q[2], QE3_safe_q[3], QE3_safe_q[4], QE3_safe_q[5]);

SE2_q_b[2]_PORT_B_address_reg = DFFE(SE2_q_b[2]_PORT_B_address, SE2_q_b[2]_clock_1, , , SE2_q_b[2]_clock_enable_1);

SE2_q_b[2]_PORT_A_write_enable = VCC;

SE2_q_b[2]_PORT_A_write_enable_reg = DFFE(SE2_q_b[2]_PORT_A_write_enable, SE2_q_b[2]_clock_0, , , SE2_q_b[2]_clock_enable_0);

SE2_q_b[2]_PORT_B_read_enable = VCC;

SE2_q_b[2]_PORT_B_read_enable_reg = DFFE(SE2_q_b[2]_PORT_B_read_enable, SE2_q_b[2]_clock_1, , , SE2_q_b[2]_clock_enable_1);

SE2_q_b[2]_clock_0 = GLOBAL(QC2__clk0);

SE2_q_b[2]_clock_1 = GLOBAL(QC2__clk0);

SE2_q_b[2]_clock_enable_0 = BB1_wr_rfifo;

SE2_q_b[2]_clock_enable_1 = BB1L78;

SE2_q_b[2]_PORT_B_data_out = MEMORY(SE2_q_b[2]_PORT_A_data_in_reg, , SE2_q_b[2]_PORT_A_address_reg, SE2_q_b[2]_PORT_B_address_reg, SE2_q_b[2]_PORT_A_write_enable_reg, SE2_q_b[2]_PORT_B_read_enable_reg, , , SE2_q_b[2]_clock_0, SE2_q_b[2]_clock_1, SE2_q_b[2]_clock_enable_0, SE2_q_b[2]_clock_enable_1, , );

SE2_q_b[3] = SE2_q_b[2]_PORT_B_data_out[1];

--T1L502 is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|p1_registered_cpu_data_master_readdata~51 at LC_X45_Y26_N3

--operation mode is normal

T1L502 = SE2_q_b[2] & BB1_read_0 # !CB1L2 # !UB1L9;

--Z1_counter_snapshot[2] is std_1c20:inst|high_res_timer:the_high_res_timer|counter_snapshot[2] at LC_X56_Y25_N0

--operation mode is normal

Z1_counter_snapshot[2]_lut_out = !Z1_internal_counter[2];

Z1_counter_snapshot[2] = DFFEAS(Z1_counter_snapshot[2]_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , Z1L232, , , , );

--Z1L187 is std_1c20:inst|high_res_timer:the_high_res_timer|read_mux_out[2]~1249 at LC_X54_Y25_N5

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

Z1_period_h_register[2]_qfbk = Z1_period_h_register[2];

Z1L187 = Z1_counter_snapshot[2] & (XE1L19 # Z1_period_h_register[2]_qfbk & XE1L15) # !Z1_counter_snapshot[2] & (Z1_period_h_register[2]_qfbk & XE1L15);

--Z1_period_h_register[2] is std_1c20:inst|high_res_timer:the_high_res_timer|period_h_register[2] at LC_X54_Y25_N5

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

Z1_period_h_register[2] = DFFEAS(Z1L187, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , Z1_period_h_wr_strobe, S1_M_st_data[2], , , VCC);

--Z1_control_register[2] is std_1c20:inst|high_res_timer:the_high_res_timer|control_register[2] at LC_X54_Y23_N4

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

Z1_control_register[2]_lut_out = GND;

Z1_control_register[2] = DFFEAS(Z1_control_register[2]_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , Z1_control_wr_strobe, S1_M_st_data[2], , , VCC);

--Z1L188 is std_1c20:inst|high_res_timer:the_high_res_timer|read_mux_out[2]~1250 at LC_X54_Y24_N6

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

Z1_counter_snapshot[18]_qfbk = Z1_counter_snapshot[18];

Z1L188 = XE1L17 & (S1L1738Q & (Z1_counter_snapshot[18]_qfbk) # !S1L1738Q & Z1_control_register[2]);

--Z1_counter_snapshot[18] is std_1c20:inst|high_res_timer:the_high_res_timer|counter_snapshot[18] at LC_X54_Y24_N6

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

Z1_counter_snapshot[18] = DFFEAS(Z1L188, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , Z1L232, Z1_internal_counter[18], , , VCC);

--Z1_period_l_register[2] is std_1c20:inst|high_res_timer:the_high_res_timer|period_l_register[2] at LC_X54_Y26_N8

--operation mode is normal

Z1_period_l_register[2]_lut_out = !S1_M_st_data[2];

Z1_period_l_register[2] = DFFEAS(Z1_period_l_register[2]_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , Z1_period_l_wr_strobe, , , , );

--DE1_rx_holding_reg[2] is std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|rx_holding_reg[2] at LC_X38_Y29_N6

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

DE1_rx_holding_reg[2]_lut_out = GND;

DE1_rx_holding_reg[2] = DFFEAS(DE1_rx_holding_reg[2]_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , DE1L302, DE1_shift_reg[2], , , VCC);

--X1L28 is std_1c20:inst|epcs_controller_epcs_control_port_arbitrator:the_epcs_controller_epcs_control_port|epcs_controller_epcs_control_port_address[0]~67 at LC_X37_Y26_N0

--operation mode is normal

X1L28 = X1L32 & (S1_ic_fill_ap_offset[0]) # !X1L32 & (X1_cpu_data_master_requests_epcs_controller_epcs_control_port & S1_M_alu_result[2] # !X1_cpu_data_master_requests_epcs_controller_epcs_control_port & (S1_ic_fill_ap_offset[0]));

--DE1L69Q is std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|data_to_cpu[5]~33 at LC_X37_Y26_N0

--operation mode is normal

DE1L69Q = DFFEAS(X1L28, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--X1L33 is std_1c20:inst|epcs_controller_epcs_control_port_arbitrator:the_epcs_controller_epcs_control_port|epcs_controller_epcs_control_port_address[2]~68 at LC_X36_Y26_N3

--operation mode is normal

X1L33 = X1L4 & S1_M_alu_result[4] # !X1L4 & (S1_ic_fill_ap_offset[2]);

--DE1L252 is std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|Equal0~140 at LC_X37_Y28_N4

--operation mode is normal

DE1L252 = X1L33 & X1L28 & !DE1L21;

--DE1L52Q is std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|data_to_cpu[0]~49 at LC_X37_Y28_N4

--operation mode is normal

DE1L52Q = DFFEAS(DE1L252, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--DE1L277 is std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|p1_data_to_cpu[2]~867 at LC_X38_Y29_N5

--operation mode is normal

DE1L277 = DE1L252 & (DE1L220Q) # !DE1L252 & DE1_rx_holding_reg[2];

--DE1L253 is std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|Equal0~141 at LC_X37_Y28_N3

--operation mode is normal

DE1L253 = X1L33 & DE1L21 & !X1L28;

--DE1L46Q is std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|data_to_cpu[0]~38 at LC_X37_Y28_N3

--operation mode is normal

DE1L46Q = DFFEAS(DE1L253, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--X1L34 is std_1c20:inst|epcs_controller_epcs_control_port_arbitrator:the_epcs_controller_epcs_control_port|epcs_controller_epcs_control_port_address[3]~70 at LC_X35_Y23_N3

--operation mode is normal

X1L34 = X1L4 & S1_M_alu_result[5] # !X1L4 & (S1_ic_fill_line[0]);

--X1L35 is std_1c20:inst|epcs_controller_epcs_control_port_arbitrator:the_epcs_controller_epcs_control_port|epcs_controller_epcs_control_port_address[4]~71 at LC_X35_Y23_N9

--operation mode is normal

X1L35 = X1L4 & S1_M_alu_result[6] # !X1L4 & (S1_ic_fill_line[1]);

--X1L36 is std_1c20:inst|epcs_controller_epcs_control_port_arbitrator:the_epcs_controller_epcs_control_port|epcs_controller_epcs_control_port_address[5]~72 at LC_X35_Y23_N5

--operation mode is normal

X1L36 = X1L4 & S1_M_alu_result[7] # !X1L4 & (S1_ic_fill_line[2]);

--X1L37 is std_1c20:inst|epcs_controller_epcs_control_port_arbitrator:the_epcs_controller_epcs_control_port|epcs_controller_epcs_control_port_address[6]~73 at LC_X35_Y23_N0

--operation mode is normal

X1L37 = X1L4 & (S1_M_alu_result[8]) # !X1L4 & S1_ic_fill_line[3];

--SD1_internal_jdo1[23] is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|internal_jdo1[23] at LC_X46_Y18_N3

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

SD1_internal_jdo1[23] = AMPP_FUNCTION(A1L8, SD1_sr[23], VCC, GND, SD1L144);

--JD1L5 is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_debug:the_cpu_nios2_oci_debug|internal_monitor_go~102 at LC_X46_Y18_N7

--operation mode is normal

JD1L5 = AMPP_FUNCTION(SD1L189, A1L3, JD1_internal_monitor_go, SD1_internal_jdo1[34]);

--RD1_MonWr is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|MonWr at LC_X45_Y18_N4

--operation mode is normal

RD1_MonWr = AMPP_FUNCTION(QC2__clk0, RD1_MonWr, JD1_resetrequest, GND, V1L46, !C1_CLR_SIGNAL, SD1L191, SD1L189);

--V1L47 is std_1c20:inst|cpu_jtag_debug_module_arbitrator:the_cpu_jtag_debug_module|cpu_jtag_debug_module_byteenable[0]~4 at LC_X43_Y19_N2

--operation mode is normal

V1L47 = S1L2149Q # !V1L6;

--RD1_internal_MonDReg[0] is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|internal_MonDReg[0] at LC_X48_Y18_N2

--operation mode is normal

RD1_internal_MonDReg[0] = AMPP_FUNCTION(QC2__clk0, SD1L191, SD1_internal_jdo1[3], RD1_MonRd1, RD1L37, !C1_CLR_SIGNAL, RD1L38);

--RD1_internal_MonDReg[1] is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|internal_MonDReg[1] at LC_X51_Y19_N4

--operation mode is normal

RD1_internal_MonDReg[1] = AMPP_FUNCTION(QC2__clk0, RD1L28, RD1_MonAReg[10], SD1_internal_jdo1[4], CE1_q_b[1], !C1_CLR_SIGNAL, RD1L39, RD1L38);

--RD1_internal_MonDReg[2] is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|internal_MonDReg[2] at LC_X51_Y17_N7

--operation mode is normal

RD1_internal_MonDReg[2] = AMPP_FUNCTION(QC2__clk0, RD1L29, RD1_MonAReg[10], SD1_internal_jdo1[5], CE1_q_b[2], !C1_CLR_SIGNAL, RD1L39, RD1L38);

--RD1_internal_MonDReg[3] is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|internal_MonDReg[3] at LC_X51_Y19_N6

--operation mode is normal

RD1_internal_MonDReg[3] = AMPP_FUNCTION(QC2__clk0, CE1_q_b[3], RD1L1, SD1_internal_jdo1[6], RD1_MonAReg[10], !C1_CLR_SIGNAL, RD1L39, RD1L38);

--RD1_internal_MonDReg[4] is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|internal_MonDReg[4] at LC_X51_Y19_N8

--operation mode is normal

RD1_internal_MonDReg[4] = AMPP_FUNCTION(QC2__clk0, CE1_q_b[4], RD1L28, SD1_internal_jdo1[7], RD1_MonAReg[10], !C1_CLR_SIGNAL, RD1L39, RD1L38);

--RD1_internal_MonDReg[5] is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|internal_MonDReg[5] at LC_X51_Y18_N7

--operation mode is normal

RD1_internal_MonDReg[5] = AMPP_FUNCTION(QC2__clk0, RD1_MonAReg[10], CE1_q_b[5], SD1_internal_jdo1[8], RD1L30, !C1_CLR_SIGNAL, RD1L39, RD1L38);

--RD1_internal_MonDReg[6] is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|internal_MonDReg[6] at LC_X51_Y18_N6

--operation mode is normal

RD1_internal_MonDReg[6] = AMPP_FUNCTION(QC2__clk0, RD1_MonAReg[10], SD1_internal_jdo1[9], RD1L39, CE1_q_b[6], !C1_CLR_SIGNAL, RD1L38);

--RD1_internal_MonDReg[7] is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|internal_MonDReg[7] at LC_X51_Y17_N9

--operation mode is normal

RD1_internal_MonDReg[7] = AMPP_FUNCTION(QC2__clk0, SD1_internal_jdo1[10], RD1_MonAReg[10], RD1L39, CE1_q_b[7], !C1_CLR_SIGNAL, RD1L38);

--RD1_MonAReg[2] is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|MonAReg[2] at LC_X47_Y18_N7

--operation mode is normal

RD1_MonAReg[2] = AMPP_FUNCTION(QC2__clk0, SD1L190, SD1_internal_jdo1[26], RD1L2, RD1L82, !C1_CLR_SIGNAL, SD1L192);

--RD1_MonAReg[3] is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|MonAReg[3] at LC_X47_Y18_N5

--operation mode is normal

RD1_MonAReg[3] = AMPP_FUNCTION(QC2__clk0, SD1L190, SD1_internal_jdo1[27], RD1L5, RD1L83, !C1_CLR_SIGNAL, SD1L192);

--RD1_MonAReg[4] is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|MonAReg[4] at LC_X47_Y18_N0

--operation mode is normal

RD1_MonAReg[4] = AMPP_FUNCTION(QC2__clk0, SD1L190, RD1L84, RD1L8, SD1_internal_jdo1[28], !C1_CLR_SIGNAL, SD1L192);

--RD1_MonAReg[5] is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|MonAReg[5] at LC_X47_Y18_N2

--operation mode is normal

RD1_MonAReg[5] = AMPP_FUNCTION(QC2__clk0, SD1L190, SD1_internal_jdo1[29], RD1L11, RD1L85, !C1_CLR_SIGNAL, SD1L192);

--RD1_MonAReg[6] is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|MonAReg[6] at LC_X47_Y17_N2

--operation mode is normal

RD1_MonAReg[6] = AMPP_FUNCTION(QC2__clk0, SD1_internal_jdo1[30], RD1L86, RD1L14, SD1L190, !C1_CLR_SIGNAL, SD1L192);

--RD1_MonAReg[7] is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|MonAReg[7] at LC_X47_Y17_N1

--operation mode is normal

RD1_MonAReg[7] = AMPP_FUNCTION(QC2__clk0, RD1L87, SD1_internal_jdo1[31], RD1L18, SD1L190, !C1_CLR_SIGNAL, SD1L192);

--RD1_MonAReg[8] is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|MonAReg[8] at LC_X47_Y17_N3

--operation mode is normal

RD1_MonAReg[8] = AMPP_FUNCTION(QC2__clk0, SD1_internal_jdo1[32], RD1L88, RD1L21, SD1L190, !C1_CLR_SIGNAL, SD1L192);

--RD1_MonAReg[9] is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|MonAReg[9] at LC_X47_Y18_N9

--operation mode is normal

RD1_MonAReg[9] = AMPP_FUNCTION(QC2__clk0, SD1L190, RD1L89, RD1L24, SD1_internal_jdo1[33], !C1_CLR_SIGNAL, SD1L192);

--T1L411Q is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|dbs_8_reg_segment_2[2]~753 at LC_X33_Y26_N9

--operation mode is normal

T1L411Q_lut_out = T1_internal_cpu_data_master_dbs_address[1] & T1L524 & !T1_internal_cpu_data_master_dbs_address[0];

T1L411Q = DFFEAS(T1L411Q_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--T1L486 is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|p1_registered_cpu_data_master_readdata[18]~2029 at LC_X37_Y24_N4

--operation mode is normal

T1L486 = S1L207Q # KB1_za_data[18] # !S1L1866Q # !S1L1686Q;

--RE2_safe_q[2] is std_1c20:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_r:the_jtag_uart_scfifo_r|scfifo:rfifo|scfifo_jf21:auto_generated|a_dpfifo_ml21:dpfifo|a_fefifo_7cf:fifo_state|cntr_9c7:count_usedw|safe_q[2] at LC_X46_Y21_N4

--operation mode is arithmetic

RE2_safe_q[2]_lut_out = RE2_safe_q[2] $ !RE2L5;

RE2_safe_q[2] = DFFEAS(RE2_safe_q[2]_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , NE2L1, , , , );

--RE2L8 is std_1c20:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_r:the_jtag_uart_scfifo_r|scfifo:rfifo|scfifo_jf21:auto_generated|a_dpfifo_ml21:dpfifo|a_fefifo_7cf:fifo_state|cntr_9c7:count_usedw|counter_cella2~COUT at LC_X46_Y21_N4

--operation mode is arithmetic

RE2L8 = RE2L9;

--BB1L23 is std_1c20:inst|jtag_uart:the_jtag_uart|Add1~290 at LC_X46_Y20_N2

--operation mode is arithmetic

BB1L23 = RE1_safe_q[2] $ (BB1L43);

--BB1L24 is std_1c20:inst|jtag_uart:the_jtag_uart|Add1~291 at LC_X46_Y20_N2

--operation mode is arithmetic

BB1L24_cout_0 = !RE1_safe_q[2] & (!BB1L43);

BB1L24 = CARRY(BB1L24_cout_0);

--BB1L25 is std_1c20:inst|jtag_uart:the_jtag_uart|Add1~291COUT1_613 at LC_X46_Y20_N2

--operation mode is arithmetic

BB1L25_cout_1 = !RE1_safe_q[2] & (!BB1L44);

BB1L25 = CARRY(BB1L25_cout_1);

--BB1L26 is std_1c20:inst|jtag_uart:the_jtag_uart|Add1~292 at LC_X46_Y21_N9

--operation mode is normal

BB1L26 = BB1_read_0 & (RE2_safe_q[2]) # !BB1_read_0 & (BB1L23);

--V1L49 is std_1c20:inst|cpu_jtag_debug_module_arbitrator:the_cpu_jtag_debug_module|cpu_jtag_debug_module_byteenable[2]~5 at LC_X34_Y20_N2

--operation mode is normal

V1L49 = S1L2168Q # !V1L6;

--RD1_internal_MonDReg[16] is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|internal_MonDReg[16] at LC_X48_Y18_N7

--operation mode is normal

RD1_internal_MonDReg[16] = AMPP_FUNCTION(QC2__clk0, RD1L39, RD1_MonAReg[10], CE1_q_b[16], SD1_internal_jdo1[19], !C1_CLR_SIGNAL, RD1L38);

--RD1_internal_MonDReg[17] is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|internal_MonDReg[17] at LC_X51_Y17_N2

--operation mode is normal

RD1_internal_MonDReg[17] = AMPP_FUNCTION(QC2__clk0, SD1_internal_jdo1[20], RD1_MonAReg[10], RD1L39, CE1_q_b[17], !C1_CLR_SIGNAL, RD1L38);

--RD1_internal_MonDReg[18] is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|internal_MonDReg[18] at LC_X51_Y18_N4

--operation mode is normal

RD1_internal_MonDReg[18] = AMPP_FUNCTION(QC2__clk0, RD1_MonAReg[10], RD1L31, SD1_internal_jdo1[21], CE1_q_b[18], !C1_CLR_SIGNAL, RD1L39, RD1L38);

--RD1_internal_MonDReg[19] is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|internal_MonDReg[19] at LC_X48_Y17_N1

--operation mode is normal

RD1_internal_MonDReg[19] = AMPP_FUNCTION(QC2__clk0, SD1_internal_jdo1[22], CE1_q_b[19], RD1L39, RD1_MonAReg[10], !C1_CLR_SIGNAL, RD1L38);

--RD1_internal_MonDReg[20] is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|internal_MonDReg[20] at LC_X48_Y18_N5

--operation mode is normal

RD1_internal_MonDReg[20] = AMPP_FUNCTION(QC2__clk0, RD1L39, RD1_MonAReg[10], CE1_q_b[20], SD1_internal_jdo1[23], !C1_CLR_SIGNAL, RD1L38);

--RD1_internal_MonDReg[21] is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|internal_MonDReg[21] at LC_X48_Y17_N2

--operation mode is normal

RD1_internal_MonDReg[21] = AMPP_FUNCTION(QC2__clk0, CE1_q_b[21], SD1_internal_jdo1[24], RD1L39, RD1_MonAReg[10], !C1_CLR_SIGNAL, RD1L38);

--RD1_internal_MonDReg[22] is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|internal_MonDReg[22] at LC_X48_Y18_N6

--operation mode is normal

RD1_internal_MonDReg[22] = AMPP_FUNCTION(QC2__clk0, RD1L39, SD1_internal_jdo1[25], RD1_MonAReg[10], CE1_q_b[22], !C1_CLR_SIGNAL, RD1L38);

--RD1_internal_MonDReg[23] is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|internal_MonDReg[23] at LC_X48_Y18_N3

--operation mode is normal

RD1_internal_MonDReg[23] = AMPP_FUNCTION(QC2__clk0, RD1L39, RD1_MonAReg[10], CE1_q_b[23], SD1_internal_jdo1[26], !C1_CLR_SIGNAL, RD1L38);

--S1L1458 is std_1c20:inst|cpu:the_cpu|i_readdata_d1[12]~153 at LC_X40_Y21_N6

--operation mode is normal

S1L1458 = AMPP_FUNCTION(S1L1450Q, S1L1459Q, S1L546Q, S1L524Q);

--S1L1462 is std_1c20:inst|cpu:the_cpu|i_readdata_d1[13]~155 at LC_X38_Y22_N2

--operation mode is normal

S1L1462 = AMPP_FUNCTION(S1L1450Q, S1L552Q, S1L1463Q, S1L524Q);

--S1L1454 is std_1c20:inst|cpu:the_cpu|i_readdata_d1[11]~151 at LC_X38_Y22_N6

--operation mode is normal

S1L1454 = AMPP_FUNCTION(S1L1450Q, S1L524Q, S1L1455Q, S1L538Q);

--S1L1466 is std_1c20:inst|cpu:the_cpu|i_readdata_d1[14]~157 at LC_X42_Y24_N3

--operation mode is normal

S1L1466 = AMPP_FUNCTION(S1L558Q, S1L524Q, S1L1450Q, S1L1467Q);

--S1_i_readdata_d1[21] is std_1c20:inst|cpu:the_cpu|i_readdata_d1[21] at LC_X37_Y21_N3

--operation mode is normal

S1_i_readdata_d1[21] = AMPP_FUNCTION(QC2__clk0, S1L1451, WC1L25, U1L109, WC1L21, F1_data_out);

--S1_i_readdata_d1[16] is std_1c20:inst|cpu:the_cpu|i_readdata_d1[16] at LC_X42_Y20_N4

--operation mode is normal

S1_i_readdata_d1[16] = AMPP_FUNCTION(QC2__clk0, U1L94, S1L1451, WC1L21, WC1L19, F1_data_out);

--Z1_internal_counter[0] is std_1c20:inst|high_res_timer:the_high_res_timer|internal_counter[0] at LC_X55_Y26_N4

--operation mode is arithmetic

Z1_internal_counter[0]_lut_out = !Z1_internal_counter[0];

Z1_internal_counter[0] = DFFEAS(Z1_internal_counter[0]_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , Z1L179, Z1_period_l_register[0], , , Z1L180);

--Z1L57 is std_1c20:inst|high_res_timer:the_high_res_timer|internal_counter[0]~2944 at LC_X55_Y26_N4

--operation mode is arithmetic

Z1L57 = CARRY(!Z1_internal_counter[0]);

--Z1_internal_counter[1] is std_1c20:inst|high_res_timer:the_high_res_timer|internal_counter[1] at LC_X55_Y26_N5

--operation mode is arithmetic

Z1_internal_counter[1]_carry_eqn = Z1L57;

Z1_internal_counter[1]_lut_out = Z1_internal_counter[1] $ !Z1_internal_counter[1]_carry_eqn;

Z1_internal_counter[1] = DFFEAS(Z1_internal_counter[1]_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , Z1L179, Z1_period_l_register[1], , , Z1L180);

--Z1L59 is std_1c20:inst|high_res_timer:the_high_res_timer|internal_counter[1]~2945 at LC_X55_Y26_N5

--operation mode is arithmetic

Z1L59_cout_0 = Z1_internal_counter[1] & !Z1L57;

Z1L59 = CARRY(Z1L59_cout_0);

--Z1L60 is std_1c20:inst|high_res_timer:the_high_res_timer|internal_counter[1]~2945COUT1_4154 at LC_X55_Y26_N5

--operation mode is arithmetic

Z1L60_cout_1 = Z1_internal_counter[1] & !Z1L57;

Z1L60 = CARRY(Z1L60_cout_1);

--Z1_internal_counter[2] is std_1c20:inst|high_res_timer:the_high_res_timer|internal_counter[2] at LC_X55_Y26_N6

--operation mode is arithmetic

Z1_internal_counter[2]_carry_eqn = (!Z1L57 & Z1L59) # (Z1L57 & Z1L60);

Z1_internal_counter[2]_lut_out = Z1_internal_counter[2] $ (Z1_internal_counter[2]_carry_eqn);

Z1_internal_counter[2] = DFFEAS(Z1_internal_counter[2]_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , Z1L179, Z1_period_l_register[2], , , Z1L180);

--Z1L62 is std_1c20:inst|high_res_timer:the_high_res_timer|internal_counter[2]~2946 at LC_X55_Y26_N6

--operation mode is arithmetic

Z1L62_cout_0 = !Z1L59 # !Z1_internal_counter[2];

Z1L62 = CARRY(Z1L62_cout_0);

--Z1L63 is std_1c20:inst|high_res_timer:the_high_res_timer|internal_counter[2]~2946COUT1_4156 at LC_X55_Y26_N6

--operation mode is arithmetic

Z1L63_cout_1 = !Z1L60 # !Z1_internal_counter[2];

Z1L63 = CARRY(Z1L63_cout_1);

--Z1_internal_counter[3] is std_1c20:inst|high_res_timer:the_high_res_timer|internal_counter[3] at LC_X55_Y26_N7

--operation mode is arithmetic

Z1_internal_counter[3]_carry_eqn = (!Z1L57 & Z1L62) # (Z1L57 & Z1L63);

Z1_internal_counter[3]_lut_out = Z1_internal_counter[3] $ (!Z1_internal_counter[3]_carry_eqn);

Z1_internal_counter[3] = DFFEAS(Z1_internal_counter[3]_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , Z1L179, Z1_period_l_register[3], , , Z1L180);

--Z1L65 is std_1c20:inst|high_res_timer:the_high_res_timer|internal_counter[3]~2947 at LC_X55_Y26_N7

--operation mode is arithmetic

Z1L65_cout_0 = Z1_internal_counter[3] & (!Z1L62);

Z1L65 = CARRY(Z1L65_cout_0);

--Z1L66 is std_1c20:inst|high_res_timer:the_high_res_timer|internal_counter[3]~2947COUT1_4158 at LC_X55_Y26_N7

--operation mode is arithmetic

Z1L66_cout_1 = Z1_internal_counter[3] & (!Z1L63);

Z1L66 = CARRY(Z1L66_cout_1);

--Z1L44 is std_1c20:inst|high_res_timer:the_high_res_timer|Equal0~370 at LC_X55_Y26_N0

--operation mode is normal

Z1L44 = Z1_internal_counter[3] & Z1_internal_counter[1] & Z1_internal_counter[0] & Z1_internal_counter[2];

--Z1_internal_counter[6] is std_1c20:inst|high_res_timer:the_high_res_timer|internal_counter[6] at LC_X55_Y25_N0

--operation mode is arithmetic

Z1_internal_counter[6]_carry_eqn = Z1L71;

Z1_internal_counter[6]_lut_out = Z1_internal_counter[6] $ Z1_internal_counter[6]_carry_eqn;

Z1_internal_counter[6] = DFFEAS(Z1_internal_counter[6]_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , Z1L179, Z1_period_l_register[6], , , Z1L180);

--Z1L73 is std_1c20:inst|high_res_timer:the_high_res_timer|internal_counter[6]~2948 at LC_X55_Y25_N0

--operation mode is arithmetic

Z1L73_cout_0 = !Z1L71 # !Z1_internal_counter[6];

Z1L73 = CARRY(Z1L73_cout_0);

--Z1L74 is std_1c20:inst|high_res_timer:the_high_res_timer|internal_counter[6]~2948COUT1_4162 at LC_X55_Y25_N0

--operation mode is arithmetic

Z1L74_cout_1 = !Z1L71 # !Z1_internal_counter[6];

Z1L74 = CARRY(Z1L74_cout_1);

--Z1_internal_counter[4] is std_1c20:inst|high_res_timer:the_high_res_timer|internal_counter[4] at LC_X55_Y26_N8

--operation mode is arithmetic

Z1_internal_counter[4]_carry_eqn = (!Z1L57 & Z1L65) # (Z1L57 & Z1L66);

Z1_internal_counter[4]_lut_out = Z1_internal_counter[4] $ Z1_internal_counter[4]_carry_eqn;

Z1_internal_counter[4] = DFFEAS(Z1_internal_counter[4]_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , Z1L179, Z1_period_l_register[4], , , Z1L180);

--Z1L68 is std_1c20:inst|high_res_timer:the_high_res_timer|internal_counter[4]~2949 at LC_X55_Y26_N8

--operation mode is arithmetic

Z1L68_cout_0 = Z1_internal_counter[4] # !Z1L65;

Z1L68 = CARRY(Z1L68_cout_0);

--Z1L69 is std_1c20:inst|high_res_timer:the_high_res_timer|internal_counter[4]~2949COUT1_4160 at LC_X55_Y26_N8

--operation mode is arithmetic

Z1L69_cout_1 = Z1_internal_counter[4] # !Z1L66;

Z1L69 = CARRY(Z1L69_cout_1);

--Z1_internal_counter[5] is std_1c20:inst|high_res_timer:the_high_res_timer|internal_counter[5] at LC_X55_Y26_N9

--operation mode is arithmetic

Z1_internal_counter[5]_carry_eqn = (!Z1L57 & Z1L68) # (Z1L57 & Z1L69);

Z1_internal_counter[5]_lut_out = Z1_internal_counter[5] $ (!Z1_internal_counter[5]_carry_eqn);

Z1_internal_counter[5] = DFFEAS(Z1_internal_counter[5]_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , Z1L179, Z1_period_l_register[5], , , Z1L180);

--Z1L71 is std_1c20:inst|high_res_timer:the_high_res_timer|internal_counter[5]~2950 at LC_X55_Y26_N9

--operation mode is arithmetic

Z1L71 = CARRY(!Z1_internal_counter[5] & (!Z1L69));

--Z1_internal_counter[7] is std_1c20:inst|high_res_timer:the_high_res_timer|internal_counter[7] at LC_X55_Y25_N1

--operation mode is arithmetic

Z1_internal_counter[7]_carry_eqn = (!Z1L71 & Z1L73) # (Z1L71 & Z1L74);

Z1_internal_counter[7]_lut_out = Z1_internal_counter[7] $ (!Z1_internal_counter[7]_carry_eqn);

Z1_internal_counter[7] = DFFEAS(Z1_internal_counter[7]_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , Z1L179, Z1_period_l_register[7], , , Z1L180);

--Z1L76 is std_1c20:inst|high_res_timer:the_high_res_timer|internal_counter[7]~2951 at LC_X55_Y25_N1

--operation mode is arithmetic

Z1L76_cout_0 = !Z1_internal_counter[7] & (!Z1L73);

Z1L76 = CARRY(Z1L76_cout_0);

--Z1L77 is std_1c20:inst|high_res_timer:the_high_res_timer|internal_counter[7]~2951COUT1_4164 at LC_X55_Y25_N1

--operation mode is arithmetic

Z1L77_cout_1 = !Z1_internal_counter[7] & (!Z1L74);

Z1L77 = CARRY(Z1L77_cout_1);

--Z1L45 is std_1c20:inst|high_res_timer:the_high_res_timer|Equal0~371 at LC_X55_Y26_N3

--operation mode is normal

Z1L45 = Z1_internal_counter[6] & !Z1_internal_counter[4] & !Z1_internal_counter[5] & !Z1_internal_counter[7];

--Z1_internal_counter[8] is std_1c20:inst|high_res_timer:the_high_res_timer|internal_counter[8] at LC_X55_Y25_N2

--operation mode is arithmetic

Z1_internal_counter[8]_carry_eqn = (!Z1L71 & Z1L76) # (Z1L71 & Z1L77);

Z1_internal_counter[8]_lut_out = Z1_internal_counter[8] $ (Z1_internal_counter[8]_carry_eqn);

Z1_internal_counter[8] = DFFEAS(Z1_internal_counter[8]_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , Z1L179, Z1_period_l_register[8], , , Z1L180);

--Z1L79 is std_1c20:inst|high_res_timer:the_high_res_timer|internal_counter[8]~2952 at LC_X55_Y25_N2

--operation mode is arithmetic

Z1L79_cout_0 = !Z1L76 # !Z1_internal_counter[8];

Z1L79 = CARRY(Z1L79_cout_0);

--Z1L80 is std_1c20:inst|high_res_timer:the_high_res_timer|internal_counter[8]~2952COUT1_4166 at LC_X55_Y25_N2

--operation mode is arithmetic

Z1L80_cout_1 = !Z1L77 # !Z1_internal_counter[8];

Z1L80 = CARRY(Z1L80_cout_1);

--Z1_internal_counter[9] is std_1c20:inst|high_res_timer:the_high_res_timer|internal_counter[9] at LC_X55_Y25_N3

--operation mode is arithmetic

Z1_internal_counter[9]_carry_eqn = (!Z1L71 & Z1L79) # (Z1L71 & Z1L80);

Z1_internal_counter[9]_lut_out = Z1_internal_counter[9] $ !Z1_internal_counter[9]_carry_eqn;

Z1_internal_counter[9] = DFFEAS(Z1_internal_counter[9]_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , Z1L179, Z1_period_l_register[9], , , Z1L180);

--Z1L82 is std_1c20:inst|high_res_timer:the_high_res_timer|internal_counter[9]~2953 at LC_X55_Y25_N3

--operation mode is arithmetic

Z1L82_cout_0 = Z1_internal_counter[9] & !Z1L79;

Z1L82 = CARRY(Z1L82_cout_0);

--Z1L83 is std_1c20:inst|high_res_timer:the_high_res_timer|internal_counter[9]~2953COUT1_4168 at LC_X55_Y25_N3

--operation mode is arithmetic

Z1L83_cout_1 = Z1_internal_counter[9] & !Z1L80;

Z1L83 = CARRY(Z1L83_cout_1);

--Z1_internal_counter[10] is std_1c20:inst|high_res_timer:the_high_res_timer|internal_counter[10] at LC_X55_Y25_N4

--operation mode is arithmetic

Z1_internal_counter[10]_carry_eqn = (!Z1L71 & Z1L82) # (Z1L71 & Z1L83);

Z1_internal_counter[10]_lut_out = Z1_internal_counter[10] $ Z1_internal_counter[10]_carry_eqn;

Z1_internal_counter[10] = DFFEAS(Z1_internal_counter[10]_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , Z1L179, Z1_period_l_register[10], , , Z1L180);

--Z1L85 is std_1c20:inst|high_res_timer:the_high_res_timer|internal_counter[10]~2954 at LC_X55_Y25_N4

--operation mode is arithmetic

Z1L85 = CARRY(Z1_internal_counter[10] # !Z1L83);

--Z1_internal_counter[11] is std_1c20:inst|high_res_timer:the_high_res_timer|internal_counter[11] at LC_X55_Y25_N5

--operation mode is arithmetic

Z1_internal_counter[11]_carry_eqn = Z1L85;

Z1_internal_counter[11]_lut_out = Z1_internal_counter[11] $ !Z1_internal_counter[11]_carry_eqn;

Z1_internal_counter[11] = DFFEAS(Z1_internal_counter[11]_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , Z1L179, Z1_period_l_register[11], , , Z1L180);

--Z1L87 is std_1c20:inst|high_res_timer:the_high_res_timer|internal_counter[11]~2955 at LC_X55_Y25_N5

--operation mode is arithmetic

Z1L87_cout_0 = !Z1_internal_counter[11] & !Z1L85;

Z1L87 = CARRY(Z1L87_cout_0);

--Z1L88 is std_1c20:inst|high_res_timer:the_high_res_timer|internal_counter[11]~2955COUT1_4170 at LC_X55_Y25_N5

--operation mode is arithmetic

Z1L88_cout_1 = !Z1_internal_counter[11] & !Z1L85;

Z1L88 = CARRY(Z1L88_cout_1);

--Z1L46 is std_1c20:inst|high_res_timer:the_high_res_timer|Equal0~372 at LC_X56_Y25_N5

--operation mode is normal

Z1L46 = !Z1_internal_counter[10] & !Z1_internal_counter[11] & Z1_internal_counter[9] & Z1_internal_counter[8];

--Z1_internal_counter[14] is std_1c20:inst|high_res_timer:the_high_res_timer|internal_counter[14] at LC_X55_Y25_N8

--operation mode is arithmetic

Z1_internal_counter[14]_carry_eqn = (!Z1L85 & Z1L93) # (Z1L85 & Z1L94);

Z1_internal_counter[14]_lut_out = Z1_internal_counter[14] $ Z1_internal_counter[14]_carry_eqn;

Z1_internal_counter[14] = DFFEAS(Z1_internal_counter[14]_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , Z1L179, Z1_period_l_register[14], , , Z1L180);

--Z1L96 is std_1c20:inst|high_res_timer:the_high_res_timer|internal_counter[14]~2956 at LC_X55_Y25_N8

--operation mode is arithmetic

Z1L96_cout_0 = !Z1L93 # !Z1_internal_counter[14];

Z1L96 = CARRY(Z1L96_cout_0);

--Z1L97 is std_1c20:inst|high_res_timer:the_high_res_timer|internal_counter[14]~2956COUT1_4176 at LC_X55_Y25_N8

--operation mode is arithmetic

Z1L97_cout_1 = !Z1L94 # !Z1_internal_counter[14];

Z1L97 = CARRY(Z1L97_cout_1);

--Z1_internal_counter[15] is std_1c20:inst|high_res_timer:the_high_res_timer|internal_counter[15] at LC_X55_Y25_N9

--operation mode is arithmetic

Z1_internal_counter[15]_carry_eqn = (!Z1L85 & Z1L96) # (Z1L85 & Z1L97);

Z1_internal_counter[15]_lut_out = Z1_internal_counter[15] $ (!Z1_internal_counter[15]_carry_eqn);

Z1_internal_counter[15] = DFFEAS(Z1_internal_counter[15]_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , Z1L179, Z1_period_l_register[15], , , Z1L180);

--Z1L99 is std_1c20:inst|high_res_timer:the_high_res_timer|internal_counter[15]~2957 at LC_X55_Y25_N9

--operation mode is arithmetic

Z1L99 = CARRY(Z1_internal_counter[15] & (!Z1L97));

--Z1_internal_counter[12] is std_1c20:inst|high_res_timer:the_high_res_timer|internal_counter[12] at LC_X55_Y25_N6

--operation mode is arithmetic

Z1_internal_counter[12]_carry_eqn = (!Z1L85 & Z1L87) # (Z1L85 & Z1L88);

Z1_internal_counter[12]_lut_out = Z1_internal_counter[12] $ (Z1_internal_counter[12]_carry_eqn);

Z1_internal_counter[12] = DFFEAS(Z1_internal_counter[12]_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , Z1L179, Z1_period_l_register[12], , , Z1L180);

--Z1L90 is std_1c20:inst|high_res_timer:the_high_res_timer|internal_counter[12]~2958 at LC_X55_Y25_N6

--operation mode is arithmetic

Z1L90_cout_0 = Z1_internal_counter[12] # !Z1L87;

Z1L90 = CARRY(Z1L90_cout_0);

--Z1L91 is std_1c20:inst|high_res_timer:the_high_res_timer|internal_counter[12]~2958COUT1_4172 at LC_X55_Y25_N6

--operation mode is arithmetic

Z1L91_cout_1 = Z1_internal_counter[12] # !Z1L88;

Z1L91 = CARRY(Z1L91_cout_1);

--Z1_internal_counter[13] is std_1c20:inst|high_res_timer:the_high_res_timer|internal_counter[13] at LC_X55_Y25_N7

--operation mode is arithmetic

Z1_internal_counter[13]_carry_eqn = (!Z1L85 & Z1L90) # (Z1L85 & Z1L91);

Z1_internal_counter[13]_lut_out = Z1_internal_counter[13] $ (!Z1_internal_counter[13]_carry_eqn);

Z1_internal_counter[13] = DFFEAS(Z1_internal_counter[13]_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , Z1L179, Z1_period_l_register[13], , , Z1L180);

--Z1L93 is std_1c20:inst|high_res_timer:the_high_res_timer|internal_counter[13]~2959 at LC_X55_Y25_N7

--operation mode is arithmetic

Z1L93_cout_0 = !Z1_internal_counter[13] & (!Z1L90);

Z1L93 = CARRY(Z1L93_cout_0);

--Z1L94 is std_1c20:inst|high_res_timer:the_high_res_timer|internal_counter[13]~2959COUT1_4174 at LC_X55_Y25_N7

--operation mode is arithmetic

Z1L94_cout_1 = !Z1_internal_counter[13] & (!Z1L91);

Z1L94 = CARRY(Z1L94_cout_1);

--Z1L47 is std_1c20:inst|high_res_timer:the_high_res_timer|Equal0~373 at LC_X56_Y25_N2

--operation mode is normal

Z1L47 = !Z1_internal_counter[13] & !Z1_internal_counter[12] & Z1_internal_counter[14] & Z1_internal_counter[15];

--Z1L48 is std_1c20:inst|high_res_timer:the_high_res_timer|Equal0~374 at LC_X56_Y25_N3

--operation mode is normal

Z1L48 = Z1L44 & Z1L46 & Z1L45 & Z1L47;

--Z1_internal_counter[16] is std_1c20:inst|high_res_timer:the_high_res_timer|internal_counter[16] at LC_X55_Y24_N0

--operation mode is arithmetic

Z1_internal_counter[16]_carry_eqn = Z1L99;

Z1_internal_counter[16]_lut_out = Z1_internal_counter[16] $ Z1_internal_counter[16]_carry_eqn;

Z1_internal_counter[16] = DFFEAS(Z1_internal_counter[16]_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , Z1L179, Z1_period_h_register[0], , , Z1L180);

--Z1L101 is std_1c20:inst|high_res_timer:the_high_res_timer|internal_counter[16]~2960 at LC_X55_Y24_N0

--operation mode is arithmetic

Z1L101_cout_0 = Z1_internal_counter[16] # !Z1L99;

Z1L101 = CARRY(Z1L101_cout_0);

--Z1L102 is std_1c20:inst|high_res_timer:the_high_res_timer|internal_counter[16]~2960COUT1_4178 at LC_X55_Y24_N0

--operation mode is arithmetic

Z1L102_cout_1 = Z1_internal_counter[16] # !Z1L99;

Z1L102 = CARRY(Z1L102_cout_1);

--Z1_internal_counter[17] is std_1c20:inst|high_res_timer:the_high_res_timer|internal_counter[17] at LC_X55_Y24_N1

--operation mode is arithmetic

Z1_internal_counter[17]_carry_eqn = (!Z1L99 & Z1L101) # (Z1L99 & Z1L102);

Z1_internal_counter[17]_lut_out = Z1_internal_counter[17] $ (!Z1_internal_counter[17]_carry_eqn);

Z1_internal_counter[17] = DFFEAS(Z1_internal_counter[17]_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , Z1L179, Z1_period_h_register[1], , , Z1L180);

--Z1L104 is std_1c20:inst|high_res_timer:the_high_res_timer|internal_counter[17]~2961 at LC_X55_Y24_N1

--operation mode is arithmetic

Z1L104_cout_0 = !Z1_internal_counter[17] & (!Z1L101);

Z1L104 = CARRY(Z1L104_cout_0);

--Z1L105 is std_1c20:inst|high_res_timer:the_high_res_timer|internal_counter[17]~2961COUT1_4180 at LC_X55_Y24_N1

--operation mode is arithmetic

Z1L105_cout_1 = !Z1_internal_counter[17] & (!Z1L102);

Z1L105 = CARRY(Z1L105_cout_1);

--Z1_internal_counter[18] is std_1c20:inst|high_res_timer:the_high_res_timer|internal_counter[18] at LC_X55_Y24_N2

--operation mode is arithmetic

Z1_internal_counter[18]_carry_eqn = (!Z1L99 & Z1L104) # (Z1L99 & Z1L105);

Z1_internal_counter[18]_lut_out = Z1_internal_counter[18] $ (Z1_internal_counter[18]_carry_eqn);

Z1_internal_counter[18] = DFFEAS(Z1_internal_counter[18]_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , Z1L179, Z1_period_h_register[2], , , Z1L180);

--Z1L107 is std_1c20:inst|high_res_timer:the_high_res_timer|internal_counter[18]~2962 at LC_X55_Y24_N2

--operation mode is arithmetic

Z1L107_cout_0 = Z1_internal_counter[18] # !Z1L104;

Z1L107 = CARRY(Z1L107_cout_0);

--Z1L108 is std_1c20:inst|high_res_timer:the_high_res_timer|internal_counter[18]~2962COUT1_4182 at LC_X55_Y24_N2

--operation mode is arithmetic

Z1L108_cout_1 = Z1_internal_counter[18] # !Z1L105;

Z1L108 = CARRY(Z1L108_cout_1);

--Z1_internal_counter[19] is std_1c20:inst|high_res_timer:the_high_res_timer|internal_counter[19] at LC_X55_Y24_N3

--operation mode is arithmetic

Z1_internal_counter[19]_carry_eqn = (!Z1L99 & Z1L107) # (Z1L99 & Z1L108);

Z1_internal_counter[19]_lut_out = Z1_internal_counter[19] $ !Z1_internal_counter[19]_carry_eqn;

Z1_internal_counter[19] = DFFEAS(Z1_internal_counter[19]_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , Z1L179, Z1_period_h_register[3], , , Z1L180);

--Z1L110 is std_1c20:inst|high_res_timer:the_high_res_timer|internal_counter[19]~2963 at LC_X55_Y24_N3

--operation mode is arithmetic

Z1L110_cout_0 = !Z1_internal_counter[19] & !Z1L107;

Z1L110 = CARRY(Z1L110_cout_0);

--Z1L111 is std_1c20:inst|high_res_timer:the_high_res_timer|internal_counter[19]~2963COUT1_4184 at LC_X55_Y24_N3

--operation mode is arithmetic

Z1L111_cout_1 = !Z1_internal_counter[19] & !Z1L108;

Z1L111 = CARRY(Z1L111_cout_1);

--Z1L49 is std_1c20:inst|high_res_timer:the_high_res_timer|Equal0~375 at LC_X54_Y24_N4

--operation mode is normal

Z1L49 = !Z1_internal_counter[18] & !Z1_internal_counter[16] & !Z1_internal_counter[19] & !Z1_internal_counter[17];

--Z1_internal_counter[20] is std_1c20:inst|high_res_timer:the_high_res_timer|internal_counter[20] at LC_X55_Y24_N4

--operation mode is arithmetic

Z1_internal_counter[20]_carry_eqn = (!Z1L99 & Z1L110) # (Z1L99 & Z1L111);

Z1_internal_counter[20]_lut_out = Z1_internal_counter[20] $ Z1_internal_counter[20]_carry_eqn;

Z1_internal_counter[20] = DFFEAS(Z1_internal_counter[20]_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , Z1L179, Z1_period_h_register[4], , , Z1L180);

--Z1L113 is std_1c20:inst|high_res_timer:the_high_res_timer|internal_counter[20]~2964 at LC_X55_Y24_N4

--operation mode is arithmetic

Z1L113 = CARRY(Z1_internal_counter[20] # !Z1L111);

--Z1_internal_counter[21] is std_1c20:inst|high_res_timer:the_high_res_timer|internal_counter[21] at LC_X55_Y24_N5

--operation mode is arithmetic

Z1_internal_counter[21]_carry_eqn = Z1L113;

Z1_internal_counter[21]_lut_out = Z1_internal_counter[21] $ !Z1_internal_counter[21]_carry_eqn;

Z1_internal_counter[21] = DFFEAS(Z1_internal_counter[21]_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , Z1L179, Z1_period_h_register[5], , , Z1L180);

--Z1L115 is std_1c20:inst|high_res_timer:the_high_res_timer|internal_counter[21]~2965 at LC_X55_Y24_N5

--operation mode is arithmetic

Z1L115_cout_0 = !Z1_internal_counter[21] & !Z1L113;

Z1L115 = CARRY(Z1L115_cout_0);

--Z1L116 is std_1c20:inst|high_res_timer:the_high_res_timer|internal_counter[21]~2965COUT1_4186 at LC_X55_Y24_N5

--operation mode is arithmetic

Z1L116_cout_1 = !Z1_internal_counter[21] & !Z1L113;

Z1L116 = CARRY(Z1L116_cout_1);

--Z1_internal_counter[22] is std_1c20:inst|high_res_timer:the_high_res_timer|internal_counter[22] at LC_X55_Y24_N6

--operation mode is arithmetic

Z1_internal_counter[22]_carry_eqn = (!Z1L113 & Z1L115) # (Z1L113 & Z1L116);

Z1_internal_counter[22]_lut_out = Z1_internal_counter[22] $ (Z1_internal_counter[22]_carry_eqn);

Z1_internal_counter[22] = DFFEAS(Z1_internal_counter[22]_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , Z1L179, Z1_period_h_register[6], , , Z1L180);

--Z1L118 is std_1c20:inst|high_res_timer:the_high_res_timer|internal_counter[22]~2966 at LC_X55_Y24_N6

--operation mode is arithmetic

Z1L118_cout_0 = Z1_internal_counter[22] # !Z1L115;

Z1L118 = CARRY(Z1L118_cout_0);

--Z1L119 is std_1c20:inst|high_res_timer:the_high_res_timer|internal_counter[22]~2966COUT1_4188 at LC_X55_Y24_N6

--operation mode is arithmetic

Z1L119_cout_1 = Z1_internal_counter[22] # !Z1L116;

Z1L119 = CARRY(Z1L119_cout_1);

--Z1_internal_counter[23] is std_1c20:inst|high_res_timer:the_high_res_timer|internal_counter[23] at LC_X55_Y24_N7

--operation mode is arithmetic

Z1_internal_counter[23]_carry_eqn = (!Z1L113 & Z1L118) # (Z1L113 & Z1L119);

Z1_internal_counter[23]_lut_out = Z1_internal_counter[23] $ (!Z1_internal_counter[23]_carry_eqn);

Z1_internal_counter[23] = DFFEAS(Z1_internal_counter[23]_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , Z1L179, Z1_period_h_register[7], , , Z1L180);

--Z1L121 is std_1c20:inst|high_res_timer:the_high_res_timer|internal_counter[23]~2967 at LC_X55_Y24_N7

--operation mode is arithmetic

Z1L121_cout_0 = !Z1_internal_counter[23] & (!Z1L118);

Z1L121 = CARRY(Z1L121_cout_0);

--Z1L122 is std_1c20:inst|high_res_timer:the_high_res_timer|internal_counter[23]~2967COUT1_4190 at LC_X55_Y24_N7

--operation mode is arithmetic

Z1L122_cout_1 = !Z1_internal_counter[23] & (!Z1L119);

Z1L122 = CARRY(Z1L122_cout_1);

--Z1L50 is std_1c20:inst|high_res_timer:the_high_res_timer|Equal0~376 at LC_X54_Y24_N1

--operation mode is normal

Z1L50 = !Z1_internal_counter[23] & !Z1_internal_counter[20] & !Z1_internal_counter[21] & !Z1_internal_counter[22];

--Z1_internal_counter[24] is std_1c20:inst|high_res_timer:the_high_res_timer|internal_counter[24] at LC_X55_Y24_N8

--operation mode is arithmetic

Z1_internal_counter[24]_carry_eqn = (!Z1L113 & Z1L121) # (Z1L113 & Z1L122);

Z1_internal_counter[24]_lut_out = Z1_internal_counter[24] $ Z1_internal_counter[24]_carry_eqn;

Z1_internal_counter[24] = DFFEAS(Z1_internal_counter[24]_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , Z1L179, Z1_period_h_register[8], , , Z1L180);

--Z1L124 is std_1c20:inst|high_res_timer:the_high_res_timer|internal_counter[24]~2968 at LC_X55_Y24_N8

--operation mode is arithmetic

Z1L124_cout_0 = Z1_internal_counter[24] # !Z1L121;

Z1L124 = CARRY(Z1L124_cout_0);

--Z1L125 is std_1c20:inst|high_res_timer:the_high_res_timer|internal_counter[24]~2968COUT1_4192 at LC_X55_Y24_N8

--operation mode is arithmetic

Z1L125_cout_1 = Z1_internal_counter[24] # !Z1L122;

Z1L125 = CARRY(Z1L125_cout_1);

--Z1_internal_counter[25] is std_1c20:inst|high_res_timer:the_high_res_timer|internal_counter[25] at LC_X55_Y24_N9

--operation mode is arithmetic

Z1_internal_counter[25]_carry_eqn = (!Z1L113 & Z1L124) # (Z1L113 & Z1L125);

Z1_internal_counter[25]_lut_out = Z1_internal_counter[25] $ (!Z1_internal_counter[25]_carry_eqn);

Z1_internal_counter[25] = DFFEAS(Z1_internal_counter[25]_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , Z1L179, Z1_period_h_register[9], , , Z1L180);

--Z1L127 is std_1c20:inst|high_res_timer:the_high_res_timer|internal_counter[25]~2969 at LC_X55_Y24_N9

--operation mode is arithmetic

Z1L127 = CARRY(!Z1_internal_counter[25] & (!Z1L125));

--Z1_internal_counter[26] is std_1c20:inst|high_res_timer:the_high_res_timer|internal_counter[26] at LC_X55_Y23_N0

--operation mode is arithmetic

Z1_internal_counter[26]_carry_eqn = Z1L127;

Z1_internal_counter[26]_lut_out = Z1_internal_counter[26] $ Z1_internal_counter[26]_carry_eqn;

Z1_internal_counter[26] = DFFEAS(Z1_internal_counter[26]_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , Z1L179, Z1_period_h_register[10], , , Z1L180);

--Z1L129 is std_1c20:inst|high_res_timer:the_high_res_timer|internal_counter[26]~2970 at LC_X55_Y23_N0

--operation mode is arithmetic

Z1L129_cout_0 = Z1_internal_counter[26] # !Z1L127;

Z1L129 = CARRY(Z1L129_cout_0);

--Z1L130 is std_1c20:inst|high_res_timer:the_high_res_timer|internal_counter[26]~2970COUT1_4194 at LC_X55_Y23_N0

--operation mode is arithmetic

Z1L130_cout_1 = Z1_internal_counter[26] # !Z1L127;

Z1L130 = CARRY(Z1L130_cout_1);

--Z1_internal_counter[27] is std_1c20:inst|high_res_timer:the_high_res_timer|internal_counter[27] at LC_X55_Y23_N1

--operation mode is arithmetic

Z1_internal_counter[27]_carry_eqn = (!Z1L127 & Z1L129) # (Z1L127 & Z1L130);

Z1_internal_counter[27]_lut_out = Z1_internal_counter[27] $ (!Z1_internal_counter[27]_carry_eqn);

Z1_internal_counter[27] = DFFEAS(Z1_internal_counter[27]_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , Z1L179, Z1_period_h_register[11], , , Z1L180);

--Z1L132 is std_1c20:inst|high_res_timer:the_high_res_timer|internal_counter[27]~2971 at LC_X55_Y23_N1

--operation mode is arithmetic

Z1L132_cout_0 = !Z1_internal_counter[27] & (!Z1L129);

Z1L132 = CARRY(Z1L132_cout_0);

--Z1L133 is std_1c20:inst|high_res_timer:the_high_res_timer|internal_counter[27]~2971COUT1_4196 at LC_X55_Y23_N1

--operation mode is arithmetic

Z1L133_cout_1 = !Z1_internal_counter[27] & (!Z1L130);

Z1L133 = CARRY(Z1L133_cout_1);

--Z1L51 is std_1c20:inst|high_res_timer:the_high_res_timer|Equal0~377 at LC_X55_Y23_N7

--operation mode is normal

Z1L51 = !Z1_internal_counter[27] & !Z1_internal_counter[24] & !Z1_internal_counter[25] & !Z1_internal_counter[26];

--Z1_internal_counter[28] is std_1c20:inst|high_res_timer:the_high_res_timer|internal_counter[28] at LC_X55_Y23_N2

--operation mode is arithmetic

Z1_internal_counter[28]_carry_eqn = (!Z1L127 & Z1L132) # (Z1L127 & Z1L133);

Z1_internal_counter[28]_lut_out = Z1_internal_counter[28] $ (Z1_internal_counter[28]_carry_eqn);

Z1_internal_counter[28] = DFFEAS(Z1_internal_counter[28]_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , Z1L179, Z1_period_h_register[12], , , Z1L180);

--Z1L135 is std_1c20:inst|high_res_timer:the_high_res_timer|internal_counter[28]~2972 at LC_X55_Y23_N2

--operation mode is arithmetic

Z1L135_cout_0 = Z1_internal_counter[28] # !Z1L132;

Z1L135 = CARRY(Z1L135_cout_0);

--Z1L136 is std_1c20:inst|high_res_timer:the_high_res_timer|internal_counter[28]~2972COUT1_4198 at LC_X55_Y23_N2

--operation mode is arithmetic

Z1L136_cout_1 = Z1_internal_counter[28] # !Z1L133;

Z1L136 = CARRY(Z1L136_cout_1);

--Z1_internal_counter[29] is std_1c20:inst|high_res_timer:the_high_res_timer|internal_counter[29] at LC_X55_Y23_N3

--operation mode is arithmetic

Z1_internal_counter[29]_carry_eqn = (!Z1L127 & Z1L135) # (Z1L127 & Z1L136);

Z1_internal_counter[29]_lut_out = Z1_internal_counter[29] $ !Z1_internal_counter[29]_carry_eqn;

Z1_internal_counter[29] = DFFEAS(Z1_internal_counter[29]_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , Z1L179, Z1_period_h_register[13], , , Z1L180);

--Z1L138 is std_1c20:inst|high_res_timer:the_high_res_timer|internal_counter[29]~2973 at LC_X55_Y23_N3

--operation mode is arithmetic

Z1L138_cout_0 = !Z1_internal_counter[29] & !Z1L135;

Z1L138 = CARRY(Z1L138_cout_0);

--Z1L139 is std_1c20:inst|high_res_timer:the_high_res_timer|internal_counter[29]~2973COUT1_4200 at LC_X55_Y23_N3

--operation mode is arithmetic

Z1L139_cout_1 = !Z1_internal_counter[29] & !Z1L136;

Z1L139 = CARRY(Z1L139_cout_1);

--Z1_internal_counter[30] is std_1c20:inst|high_res_timer:the_high_res_timer|internal_counter[30] at LC_X55_Y23_N4

--operation mode is arithmetic

Z1_internal_counter[30]_carry_eqn = (!Z1L127 & Z1L138) # (Z1L127 & Z1L139);

Z1_internal_counter[30]_lut_out = Z1_internal_counter[30] $ Z1_internal_counter[30]_carry_eqn;

Z1_internal_counter[30] = DFFEAS(Z1_internal_counter[30]_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , Z1L179, Z1_period_h_register[14], , , Z1L180);

--Z1L141 is std_1c20:inst|high_res_timer:the_high_res_timer|internal_counter[30]~2974 at LC_X55_Y23_N4

--operation mode is arithmetic

Z1L141 = CARRY(Z1_internal_counter[30] # !Z1L139);

--Z1_internal_counter[31] is std_1c20:inst|high_res_timer:the_high_res_timer|internal_counter[31] at LC_X55_Y23_N5

--operation mode is normal

Z1_internal_counter[31]_carry_eqn = Z1L141;

Z1_internal_counter[31]_lut_out = Z1_internal_counter[31]_carry_eqn $ !Z1_internal_counter[31];

Z1_internal_counter[31] = DFFEAS(Z1_internal_counter[31]_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , Z1L179, Z1_period_h_register[15], , , Z1L180);

--Z1L52 is std_1c20:inst|high_res_timer:the_high_res_timer|Equal0~378 at LC_X55_Y23_N6

--operation mode is normal

Z1L52 = !Z1_internal_counter[28] & !Z1_internal_counter[31] & !Z1_internal_counter[30] & !Z1_internal_counter[29];

--Z1L53 is std_1c20:inst|high_res_timer:the_high_res_timer|Equal0~379 at LC_X55_Y23_N9

--operation mode is normal

Z1L53 = Z1L52 & Z1L49 & Z1L51 & Z1L50;

--Z1_delayed_unxcounter_is_zeroxx0 is std_1c20:inst|high_res_timer:the_high_res_timer|delayed_unxcounter_is_zeroxx0 at LC_X54_Y23_N3

--operation mode is normal

Z1_delayed_unxcounter_is_zeroxx0_lut_out = Z1L48 & Z1L53;

Z1_delayed_unxcounter_is_zeroxx0 = DFFEAS(Z1_delayed_unxcounter_is_zeroxx0_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--Z1L234 is std_1c20:inst|high_res_timer:the_high_res_timer|timeout_occurred~41 at LC_X54_Y23_N8

--operation mode is normal

Z1L234 = Z1_timeout_occurred # Z1L48 & !Z1_delayed_unxcounter_is_zeroxx0 & Z1L53;

--XE1L21 is std_1c20:inst|uart1:the_uart1|uart1_regs:the_uart1_regs|Equal1~122 at LC_X47_Y23_N8

--operation mode is normal

XE1L21 = !S1L1726Q & !S1_M_alu_result[3] & (!S1L1738Q);

--G1L32 is std_1c20:inst|button_pio:the_button_pio|read_mux_out[3]~378 at LC_X44_Y20_N7

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

G1_irq_mask[3]_qfbk = G1_irq_mask[3];

G1L32 = S1L1726Q & G1_edge_capture[3] # !S1L1726Q & (G1_irq_mask[3]_qfbk);

--G1_irq_mask[3] is std_1c20:inst|button_pio:the_button_pio|irq_mask[3] at LC_X44_Y20_N7

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

G1_irq_mask[3] = DFFEAS(G1L32, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , G1L26, S1_M_st_data[3], , , VCC);

--XE1L54 is std_1c20:inst|uart1:the_uart1|uart1_regs:the_uart1_regs|selected_read_data[3]~680 at LC_X47_Y22_N1

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

XE1_internal_tx_data[3]_qfbk = XE1_internal_tx_data[3];

XE1L54 = S1_M_alu_result[3] & (XE1_control_reg[3]) # !S1_M_alu_result[3] & (XE1_internal_tx_data[3]_qfbk);

--XE1_internal_tx_data[3] is std_1c20:inst|uart1:the_uart1|uart1_regs:the_uart1_regs|internal_tx_data[3] at LC_X47_Y22_N1

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

XE1_internal_tx_data[3] = DFFEAS(XE1L54, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , XE1L64, S1_M_st_data[3], , , VCC);

--YE1_rx_overrun is std_1c20:inst|uart1:the_uart1|uart1_rx:the_uart1_rx|rx_overrun at LC_X52_Y22_N9

--operation mode is normal

YE1_rx_overrun_lut_out = YE1L63 & (!XE1L13 # !XE1L20) # !YE1L63 & YE1_rx_overrun & (!XE1L13 # !XE1L20);

YE1_rx_overrun = DFFEAS(YE1_rx_overrun_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--XE1L55 is std_1c20:inst|uart1:the_uart1|uart1_regs:the_uart1_regs|selected_read_data[3]~681 at LC_X51_Y22_N4

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

YE1_rx_data[3]_qfbk = YE1_rx_data[3];

XE1L55 = S1_M_alu_result[3] & YE1_rx_overrun # !S1_M_alu_result[3] & (YE1_rx_data[3]_qfbk);

--YE1_rx_data[3] is std_1c20:inst|uart1:the_uart1|uart1_rx:the_uart1_rx|rx_data[3] at LC_X51_Y22_N4

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

YE1_rx_data[3] = DFFEAS(XE1L55, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , YE1_got_new_char, YE1_unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[4], , , VCC);

--RB1_counter_snapshot[3] is std_1c20:inst|sys_clk_timer:the_sys_clk_timer|counter_snapshot[3] at LC_X53_Y27_N3

--operation mode is normal

RB1_counter_snapshot[3]_lut_out = !RB1_internal_counter[3];

RB1_counter_snapshot[3] = DFFEAS(RB1_counter_snapshot[3]_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , RB1L235, , , , );

--RB1L192 is std_1c20:inst|sys_clk_timer:the_sys_clk_timer|read_mux_out[3]~1240 at LC_X53_Y25_N8

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

RB1_period_h_register[3]_qfbk = RB1_period_h_register[3];

RB1L192 = RB1_counter_snapshot[3] & (XE1L19 # RB1_period_h_register[3]_qfbk & XE1L15) # !RB1_counter_snapshot[3] & (RB1_period_h_register[3]_qfbk & XE1L15);

--RB1_period_h_register[3] is std_1c20:inst|sys_clk_timer:the_sys_clk_timer|period_h_register[3] at LC_X53_Y25_N8

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

RB1_period_h_register[3] = DFFEAS(RB1L192, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , RB1_period_h_wr_strobe, S1_M_st_data[3], , , VCC);

--RB1_control_register[3] is std_1c20:inst|sys_clk_timer:the_sys_clk_timer|control_register[3] at LC_X52_Y23_N6

--operation mode is normal

RB1_control_register[3]_lut_out = S1_M_st_data[3];

RB1_control_register[3] = DFFEAS(RB1_control_register[3]_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , RB1_control_wr_strobe, , , , );

--RB1L193 is std_1c20:inst|sys_clk_timer:the_sys_clk_timer|read_mux_out[3]~1241 at LC_X52_Y23_N8

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

RB1_counter_snapshot[19]_qfbk = RB1_counter_snapshot[19];

RB1L193 = XE1L17 & (S1L1738Q & (RB1_counter_snapshot[19]_qfbk) # !S1L1738Q & RB1_control_register[3]);

--RB1_counter_snapshot[19] is std_1c20:inst|sys_clk_timer:the_sys_clk_timer|counter_snapshot[19] at LC_X52_Y23_N8

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

RB1_counter_snapshot[19] = DFFEAS(RB1L193, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , RB1L235, RB1_internal_counter[19], , , VCC);

--RB1_period_l_register[3] is std_1c20:inst|sys_clk_timer:the_sys_clk_timer|period_l_register[3] at LC_X53_Y27_N2

--operation mode is normal

RB1_period_l_register[3]_lut_out = !S1_M_st_data[3];

RB1_period_l_register[3] = DFFEAS(RB1_period_l_register[3]_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , RB1_period_l_wr_strobe, , , , );

--J1_slave_readdata[3] is std_1c20:inst|clock_0:the_clock_0|slave_readdata[3] at LC_X45_Y27_N8

--operation mode is normal

J1_slave_readdata[3]_lut_out = J1_slave_readdata_p1[3];

J1_slave_readdata[3] = DFFEAS(J1_slave_readdata[3]_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--T1L473 is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|p1_registered_cpu_data_master_readdata[3]~2031 at LC_X45_Y27_N7

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

M1_slave_readdata[3]_qfbk = M1_slave_readdata[3];

T1L473 = S1L1743Q & (M1_slave_readdata[3]_qfbk) # !S1L1743Q & J1_slave_readdata[3] # !K1L6;

--M1_slave_readdata[3] is std_1c20:inst|clock_1:the_clock_1|slave_readdata[3] at LC_X45_Y27_N7

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

M1_slave_readdata[3] = DFFEAS(T1L473, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , M1_slave_readdata_p1[3], , , VCC);

--T1L503 is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|p1_registered_cpu_data_master_readdata~52 at LC_X45_Y25_N6

--operation mode is normal

T1L503 = BB1_read_0 & SE2_q_b[3] # !UB1L9 # !CB1L2;

--Z1_counter_snapshot[3] is std_1c20:inst|high_res_timer:the_high_res_timer|counter_snapshot[3] at LC_X54_Y27_N6

--operation mode is normal

Z1_counter_snapshot[3]_lut_out = !Z1_internal_counter[3];

Z1_counter_snapshot[3] = DFFEAS(Z1_counter_snapshot[3]_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , Z1L232, , , , );

--Z1L189 is std_1c20:inst|high_res_timer:the_high_res_timer|read_mux_out[3]~1251 at LC_X54_Y25_N6

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

Z1_period_h_register[3]_qfbk = Z1_period_h_register[3];

Z1L189 = XE1L15 & (Z1_period_h_register[3]_qfbk # XE1L19 & Z1_counter_snapshot[3]) # !XE1L15 & XE1L19 & (Z1_counter_snapshot[3]);

--Z1_period_h_register[3] is std_1c20:inst|high_res_timer:the_high_res_timer|period_h_register[3] at LC_X54_Y25_N6

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

Z1_period_h_register[3] = DFFEAS(Z1L189, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , Z1_period_h_wr_strobe, S1_M_st_data[3], , , VCC);

--Z1_control_register[3] is std_1c20:inst|high_res_timer:the_high_res_timer|control_register[3] at LC_X54_Y23_N2

--operation mode is normal

Z1_control_register[3]_lut_out = S1_M_st_data[3];

Z1_control_register[3] = DFFEAS(Z1_control_register[3]_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , Z1_control_wr_strobe, , , , );

--Z1L190 is std_1c20:inst|high_res_timer:the_high_res_timer|read_mux_out[3]~1252 at LC_X54_Y24_N0

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

Z1_counter_snapshot[19]_qfbk = Z1_counter_snapshot[19];

Z1L190 = XE1L17 & (S1L1738Q & (Z1_counter_snapshot[19]_qfbk) # !S1L1738Q & Z1_control_register[3]);

--Z1_counter_snapshot[19] is std_1c20:inst|high_res_timer:the_high_res_timer|counter_snapshot[19] at LC_X54_Y24_N0

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

Z1_counter_snapshot[19] = DFFEAS(Z1L190, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , Z1L232, Z1_internal_counter[19], , , VCC);

--Z1_period_l_register[3] is std_1c20:inst|high_res_timer:the_high_res_timer|period_l_register[3] at LC_X55_Y27_N3

--operation mode is normal

Z1_period_l_register[3]_lut_out = !S1_M_st_data[3];

Z1_period_l_register[3] = DFFEAS(Z1_period_l_register[3]_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , Z1_period_l_wr_strobe, , , , );

--DE1_iROE_reg is std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|iROE_reg at LC_X39_Y27_N9

--operation mode is normal

DE1_iROE_reg_lut_out = S1_M_st_data[3];

DE1_iROE_reg = DFFEAS(DE1_iROE_reg_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , DE1_control_wr_strobe, , , , );

--DE1_rx_holding_reg[3] is std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|rx_holding_reg[3] at LC_X39_Y28_N3

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

DE1_rx_holding_reg[3]_qfbk = DE1_rx_holding_reg[3];

DE1_rx_holding_reg[3]_lut_out = DE1_rx_holding_reg[3]_qfbk & (DE1L21 # !X1L33 # !X1L28);

DE1_rx_holding_reg[3] = DFFEAS(DE1_rx_holding_reg[3]_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , DE1L302, DE1_shift_reg[3], , , VCC);

--DE1L3 is std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|A_WE_StdLogicVector~1118 at LC_X39_Y28_N4

--operation mode is normal

DE1L3 = X1L33 & (DE1L25 # DE1_rx_holding_reg[3] & !DE1L23) # !X1L33 & DE1_rx_holding_reg[3];

--DE1_ROE is std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|ROE at LC_X39_Y27_N5

--operation mode is normal

DE1_ROE_lut_out = DE1_RRDY & (DE1L302 # !DE1_status_wr_strobe & DE1_ROE) # !DE1_RRDY & (!DE1_status_wr_strobe & DE1_ROE);

DE1_ROE = DFFEAS(DE1_ROE_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--DE1L255 is std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|Equal0~142 at LC_X36_Y27_N6

--operation mode is normal

DE1L255 = DE1L21 & !X1L33 & X1L28;

--DE1L256 is std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|Equal0~143 at LC_X36_Y26_N4

--operation mode is normal

DE1L256 = !X1L28 & (X1L4 & (DE1L258) # !X1L4 & DE1L260);

--DE1L61Q is std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|data_to_cpu[4]~43 at LC_X36_Y26_N4

--operation mode is normal

DE1L61Q = DFFEAS(DE1L256, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--T1L487 is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|p1_registered_cpu_data_master_readdata[19]~2033 at LC_X37_Y24_N1

--operation mode is normal

T1L487 = S1L207Q # KB1_za_data[19] # !S1L1866Q # !S1L1686Q;

--RE2_safe_q[3] is std_1c20:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_r:the_jtag_uart_scfifo_r|scfifo:rfifo|scfifo_jf21:auto_generated|a_dpfifo_ml21:dpfifo|a_fefifo_7cf:fifo_state|cntr_9c7:count_usedw|safe_q[3] at LC_X46_Y21_N5

--operation mode is arithmetic

RE2_safe_q[3]_carry_eqn = RE2L8;

RE2_safe_q[3]_lut_out = RE2_safe_q[3] $ RE2_safe_q[3]_carry_eqn;

RE2_safe_q[3] = DFFEAS(RE2_safe_q[3]_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , NE2L1, , , , );

--RE2L12 is std_1c20:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_r:the_jtag_uart_scfifo_r|scfifo:rfifo|scfifo_jf21:auto_generated|a_dpfifo_ml21:dpfifo|a_fefifo_7cf:fifo_state|cntr_9c7:count_usedw|counter_cella3~COUT at LC_X46_Y21_N5

--operation mode is arithmetic

RE2L12_cout_0 = BB1_wr_rfifo $ RE2_safe_q[3] # !RE2L8;

RE2L12 = CARRY(RE2L12_cout_0);

--RE2L13 is std_1c20:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_r:the_jtag_uart_scfifo_r|scfifo:rfifo|scfifo_jf21:auto_generated|a_dpfifo_ml21:dpfifo|a_fefifo_7cf:fifo_state|cntr_9c7:count_usedw|counter_cella3~COUTCOUT1_47 at LC_X46_Y21_N5

--operation mode is arithmetic

RE2L13_cout_1 = BB1_wr_rfifo $ RE2_safe_q[3] # !RE2L8;

RE2L13 = CARRY(RE2L13_cout_1);

--BB1L27 is std_1c20:inst|jtag_uart:the_jtag_uart|Add1~293 at LC_X46_Y20_N3

--operation mode is arithmetic

BB1L27 = RE1_safe_q[3] $ !BB1L24;

--BB1L28 is std_1c20:inst|jtag_uart:the_jtag_uart|Add1~294 at LC_X46_Y20_N3

--operation mode is arithmetic

BB1L28_cout_0 = RE1_safe_q[3] # !BB1L24;

BB1L28 = CARRY(BB1L28_cout_0);

--BB1L29 is std_1c20:inst|jtag_uart:the_jtag_uart|Add1~294COUT1_615 at LC_X46_Y20_N3

--operation mode is arithmetic

BB1L29_cout_1 = RE1_safe_q[3] # !BB1L25;

BB1L29 = CARRY(BB1L29_cout_1);

--BB1L30 is std_1c20:inst|jtag_uart:the_jtag_uart|Add1~295 at LC_X46_Y21_N0

--operation mode is normal

BB1L30 = BB1_read_0 & (RE2_safe_q[3]) # !BB1_read_0 & (BB1L27);

--S1L1442 is std_1c20:inst|cpu:the_cpu|i_readdata_d1[9]~143 at LC_X40_Y21_N9

--operation mode is normal

S1L1442 = AMPP_FUNCTION(S1L1444Q, S1L524Q, S1L1443Q, S1L1450Q);

--S1_E_src1_prelim[31] is std_1c20:inst|cpu:the_cpu|E_src1_prelim[31] at LC_X39_Y13_N6

--operation mode is normal

S1_E_src1_prelim[31] = AMPP_FUNCTION(QC2__clk0, S1_D_src1_hazard_W, S1_W_wr_data[31], S1L2495, CD1_q_b[31], F1_data_out, S1_D_src1_hazard_M, S1_W_stall);

--S1L2493 is std_1c20:inst|cpu:the_cpu|M_wr_data_unfiltered[31]~3699 at LC_X38_Y13_N7

--operation mode is normal

S1L2493 = AMPP_FUNCTION(S1_M_shift_rot_result[31], S1L2056Q);

--S1L228 is std_1c20:inst|cpu:the_cpu|av_ld_data_aligned_or_div[31]~86 at LC_X39_Y20_N2

--operation mode is normal

S1L228 = AMPP_FUNCTION(S1L239, S1L642, S1_M_iw[4], S1_M_ctrl_ld_signed);

--S1_av_ld_data_aligned_or_div[31] is std_1c20:inst|cpu:the_cpu|av_ld_data_aligned_or_div[31] at LC_X39_Y20_N2

--operation mode is normal

S1_av_ld_data_aligned_or_div[31] = AMPP_FUNCTION(QC2__clk0, S1L239, S1L642, S1_M_iw[4], S1_M_ctrl_ld_signed, F1_data_out);

--S1L2009 is std_1c20:inst|cpu:the_cpu|M_alu_result[31]~297 at LC_X34_Y13_N3

--operation mode is normal

S1L2009 = AMPP_FUNCTION(S1_E_logic_op[1], YC1_result[31], S1L2028, S1L2030);

--S1L2020Q is std_1c20:inst|cpu:the_cpu|M_alu_result[31]~314 at LC_X34_Y13_N3

--operation mode is normal

S1L2020Q = AMPP_FUNCTION(QC2__clk0, S1_E_logic_op[1], YC1_result[31], S1L2028, S1L2030, F1_data_out);

--S1L229Q is std_1c20:inst|cpu:the_cpu|av_ld_data_aligned_or_div[31]~87 at LC_X34_Y13_N2

--operation mode is normal

S1L229Q = AMPP_FUNCTION(QC2__clk0, S1L2504, S1L2502, S1L2497, S1L2009, F1_data_out);

--S1L884 is std_1c20:inst|cpu:the_cpu|E_src1[31]~2042 at LC_X37_Y13_N5

--operation mode is normal

S1L884 = AMPP_FUNCTION(S1L886Q, S1L229Q, S1L2493, S1_E_src1_prelim[31]);

--S1_E_src2_imm[31] is std_1c20:inst|cpu:the_cpu|E_src2_imm[31] at LC_X37_Y13_N3

--operation mode is normal

S1_E_src2_imm[31] = AMPP_FUNCTION(QC2__clk0, S1L311, S1_D_iw[21], F1_data_out, S1_W_stall);

--S1_E_src2_prelim[31] is std_1c20:inst|cpu:the_cpu|E_src2_prelim[31] at LC_X44_Y14_N7

--operation mode is normal

S1_E_src2_prelim[31] = AMPP_FUNCTION(QC2__clk0, DD1_q_b[31], S1_W_wr_data[31], S1L2495, S1L668, F1_data_out, S1L664, S1_W_stall);

--S1L1149 is std_1c20:inst|cpu:the_cpu|E_src2_reg[31]~474 at LC_X37_Y13_N0

--operation mode is normal

S1L1149 = AMPP_FUNCTION(S1_E_src2_hazard_M, S1L229Q, S1L2493, S1_E_src2_prelim[31]);

--S1L1070 is std_1c20:inst|cpu:the_cpu|E_src2[31]~1529 at LC_X37_Y13_N7

--operation mode is normal

S1L1070 = AMPP_FUNCTION(S1L2493, S1L229Q, S1L1074, S1L1072);

--XC1L6 is std_1c20:inst|cpu:the_cpu|cpu_test_bench:the_cpu_test_bench|Add0~563 at LC_X35_Y13_N4

--operation mode is arithmetic

XC1L6 = AMPP_FUNCTION(S1L1065, S1L883, XC1L20, XC1L8, XC1L9);

--S1_E_ctrl_alu_signed_cmp is std_1c20:inst|cpu:the_cpu|E_ctrl_alu_signed_cmp at LC_X30_Y13_N3

--operation mode is normal

S1_E_ctrl_alu_signed_cmp = AMPP_FUNCTION(QC2__clk0, S1L278, S1L277, S1_D_iw[5], S1L276, F1_data_out, S1_W_stall);

--S1L696 is std_1c20:inst|cpu:the_cpu|E_arith_src2~0 at LC_X37_Y13_N1

--operation mode is normal

S1L696 = AMPP_FUNCTION(S1_E_ctrl_alu_signed_cmp, S1_E_src2_imm[31], S1_E_ctrl_src2_is_imm, S1L1149);

--S1L691 is std_1c20:inst|cpu:the_cpu|E_arith_src1~0 at LC_X37_Y13_N9

--operation mode is normal

S1L691 = AMPP_FUNCTION(S1L2493, S1L693, S1_E_ctrl_alu_signed_cmp, S1L695);

--YC1_result[30] is std_1c20:inst|cpu:the_cpu|lpm_add_sub:Add8|alt_stratix_add_sub:stratix_adder|result[30] at LC_X36_Y13_N0

--operation mode is arithmetic

YC1_result[30] = AMPP_FUNCTION(S1L1065, S1L883, YC1L85, S1_E_ctrl_alu_subtract);

--YC1L87 is std_1c20:inst|cpu:the_cpu|lpm_add_sub:Add8|alt_stratix_add_sub:stratix_adder|add_sub_cell[30]~COUT at LC_X36_Y13_N0

--operation mode is arithmetic

YC1L87 = AMPP_FUNCTION(S1L1065, S1L883, S1_E_ctrl_alu_subtract);

--YC1L88 is std_1c20:inst|cpu:the_cpu|lpm_add_sub:Add8|alt_stratix_add_sub:stratix_adder|add_sub_cell[30]~COUTCOUT1_1343 at LC_X36_Y13_N0

--operation mode is arithmetic

YC1L88 = AMPP_FUNCTION(S1L1065, S1L883, S1_E_ctrl_alu_subtract);

--SD1_sr[19] is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|sr[19] at LC_X51_Y14_N7

--operation mode is normal

SD1_sr[19] = AMPP_FUNCTION(A1L5, SD1L23, SD1L24, SD1_sr[20], SD1L70, !C1_CLR_SIGNAL, SD1L12);

--SD1_sr[18] is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|sr[18] at LC_X47_Y15_N2

--operation mode is normal

SD1_sr[18] = AMPP_FUNCTION(A1L5, SD1L9, SD1_sr[19], SD1L27, SD1L26, !C1_CLR_SIGNAL, SD1L12);

--GD1_break_readreg[20] is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_break:the_cpu_nios2_oci_break|break_readreg[20] at LC_X48_Y16_N7

--operation mode is normal

GD1_break_readreg[20] = AMPP_FUNCTION(QC2__clk0, SD1L188, SD1_internal_jdo1[20], SD1_internal_jdo1[36], SD1_internal_jdo1[37], !C1_CLR_SIGNAL, SD1L188);

--SD1L7 is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|DRsize[0]~19972 at LC_X48_Y16_N6

--operation mode is normal

SD1L7 = AMPP_FUNCTION(SD1_ir[1], GD1_break_readreg[20], RD1_internal_MonDReg[20]);

--SD1L8 is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|DRsize[0]~19973 at LC_X47_Y16_N1

--operation mode is normal

SD1L8 = AMPP_FUNCTION(SD1L142, SD1_ir[0], SD1L144, SD1L7);

--SD1L9 is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|DRsize[0]~19974 at LC_X46_Y14_N0

--operation mode is normal

SD1L9 = AMPP_FUNCTION(SD1_ir[1], SD1L144, SD1_ir[0], A1L4);

--SD1L10 is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|DRsize[0]~19975 at LC_X47_Y16_N4

--operation mode is normal

SD1L10 = AMPP_FUNCTION(A1L4, SD1_ir[0], SD1L144, SD1L7);

--SD1L11 is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|DRsize[0]~19977 at LC_X52_Y15_N3

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

SD1L11 = AMPP_FUNCTION(SD1_ir[1]);

--SD1_ir[0] is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|ir[0] at LC_X52_Y15_N3

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

SD1_ir[0] = AMPP_FUNCTION(A1L5, BF5_Q[0], VCC, GND, SD1L117);

--SD1L12 is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|DRsize[0]~19978 at LC_X52_Y15_N4

--operation mode is normal

SD1L12 = AMPP_FUNCTION(SD1L141, SD1_st_updateir, SD1L143, SD1L11);

--C1L33 is sld_hub:sld_hub_inst|jtag_debug_mode~171 at LC_X57_Y15_N5

--operation mode is normal

C1L33 = AMPP_FUNCTION(FF1_state[2], A1L7, FF1_state[12]);

--FF1_state[15] is sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state[15] at LC_X58_Y15_N8

--operation mode is normal

FF1_state[15] = AMPP_FUNCTION(A1L5, FF1_state[14], FF1_state[12], VCC, !A1L7);

--GF1_dffe1a[1] is sld_hub:sld_hub_inst|lpm_decode:instruction_decoder|decode_ogi:auto_generated|dffe1a[1] at LC_X57_Y17_N4

--operation mode is normal

GF1_dffe1a[1] = AMPP_FUNCTION(A1L5, BF3_Q[2], BF3_Q[3], BF3_Q[1], C1L32, !C1_CLR_SIGNAL, C1L5);

--GF1_dffe1a[2] is sld_hub:sld_hub_inst|lpm_decode:instruction_decoder|decode_ogi:auto_generated|dffe1a[2] at LC_X57_Y17_N0

--operation mode is normal

GF1_dffe1a[2] = AMPP_FUNCTION(A1L5, BF3_Q[2], BF3_Q[3], BF3_Q[1], C1L32, !C1_CLR_SIGNAL, C1L5);

--C1L1 is sld_hub:sld_hub_inst|BROADCAST_ENA~32 at LC_X57_Y17_N8

--operation mode is normal

C1L1 = AMPP_FUNCTION(C1_OK_TO_UPDATE_IR_Q, GF1_dffe1a[2], GF1_dffe1a[1], FF1_state[8]);

--GD1_break_readreg[19] is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_break:the_cpu_nios2_oci_break|break_readreg[19] at LC_X48_Y16_N4

--operation mode is normal

GD1_break_readreg[19] = AMPP_FUNCTION(QC2__clk0, SD1_internal_jdo1[36], SD1_internal_jdo1[19], SD1L188, SD1_internal_jdo1[37], !C1_CLR_SIGNAL, SD1L188);

--SD1L13 is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|DRsize[0]~19979 at LC_X47_Y16_N5

--operation mode is normal

SD1L13 = AMPP_FUNCTION(RD1_internal_MonDReg[19], GD1_break_readreg[19], SD1_ir[1]);

--SD1L14 is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|DRsize[0]~19980 at LC_X47_Y16_N9

--operation mode is normal

SD1L14 = AMPP_FUNCTION(SD1L142, SD1_ir[0], SD1L144, SD1L13);

--SD1L15 is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|DRsize[0]~19981 at LC_X47_Y16_N3

--operation mode is normal

SD1L15 = AMPP_FUNCTION(SD1L144, SD1L13, SD1_ir[0], A1L4);

--GF1_dffe1a[7] is sld_hub:sld_hub_inst|lpm_decode:instruction_decoder|decode_ogi:auto_generated|dffe1a[7] at LC_X57_Y17_N2

--operation mode is normal

GF1_dffe1a[7] = AMPP_FUNCTION(A1L5, BF3_Q[2], BF3_Q[3], BF3_Q[1], C1L32, !C1_CLR_SIGNAL, C1L5);

--C1L2 is sld_hub:sld_hub_inst|BROADCAST_ENA~33 at LC_X56_Y17_N4

--operation mode is normal

C1L2 = AMPP_FUNCTION(C1_OK_TO_UPDATE_IR_Q, FF1_state[8]);

--JD1_internal_monitor_error is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_debug:the_cpu_nios2_oci_debug|internal_monitor_error at LC_X46_Y18_N5

--operation mode is normal

JD1_internal_monitor_error = AMPP_FUNCTION(QC2__clk0, JD1L3, SD1L190, S1_M_st_data[1], FD1L38, VCC);

--SD1L16 is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|DRsize[0]~19983 at LC_X46_Y15_N1

--operation mode is normal

SD1L16 = AMPP_FUNCTION(SD1_ir[1], SD1_ir[0], JD1_internal_monitor_error);

--SD1L17 is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|DRsize[0]~19984 at LC_X46_Y15_N7

--operation mode is normal

SD1L17 = AMPP_FUNCTION(SD1_ir[1], SD1_ir[0], A1L4, SD1L144);

--SD1_st_updatedr is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|st_updatedr at LC_X52_Y14_N2

--operation mode is normal

SD1_st_updatedr = AMPP_FUNCTION(A1L5, SD1L144, VCC, A1L8);

--SD1L131 is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|Mux41~110 at LC_X51_Y15_N4

--operation mode is normal

SD1L131 = AMPP_FUNCTION(SD1_DRsize[1], SD1_DRsize[2], SD1_DRsize[0], altera_internal_jtag);

--SD1_sr[36] is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|sr[36] at LC_X51_Y15_N3

--operation mode is normal

SD1_sr[36] = AMPP_FUNCTION(A1L5, A1L4, SD1L144, SD1L28, SD1_sr[37], !C1_CLR_SIGNAL, SD1L30);

--SD1L132 is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|Mux41~111 at LC_X51_Y15_N7

--operation mode is normal

SD1L132 = AMPP_FUNCTION(SD1_DRsize[1], SD1_sr[36], SD1_DRsize[0], SD1_DRsize[2]);

--SD1L18 is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|DRsize[0]~19986 at LC_X46_Y15_N6

--operation mode is normal

SD1L18 = AMPP_FUNCTION(A1L4, SD1L144, SD1L132, SD1L131);

--SD1L133 is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|Mux41~112 at LC_X46_Y15_N3

--operation mode is normal

SD1L133 = AMPP_FUNCTION(SD1L132, SD1L131);

--SD1L19 is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|DRsize[0]~19987 at LC_X46_Y15_N4

--operation mode is normal

SD1L19 = AMPP_FUNCTION(SD1_ir[1], S1_hbreak_enabled, SD1L143, SD1L133);

--BF7_Q[0] is sld_hub:sld_hub_inst|sld_dffex:\GEN_SHADOW_IRF:1:S_IRF|Q[0] at LC_X57_Y16_N3

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

BF7_Q[0] = AMPP_FUNCTION(A1L5, BF3_Q[0], !C1_CLR_SIGNAL, GND, C1L8);

--C1L9 is sld_hub:sld_hub_inst|GEN_SHADOW_IRF~22 at LC_X57_Y16_N5

--operation mode is normal

C1L9 = AMPP_FUNCTION(FF1_state[5], C1_OK_TO_UPDATE_IR_Q);

--C1L25 is sld_hub:sld_hub_inst|IRF_ENABLE[1]~135 at LC_X57_Y16_N1

--operation mode is normal

C1L25 = AMPP_FUNCTION(BF2_Q[0], GF1_dffe1a[2], BF9_Q[0]);

--C1L26 is sld_hub:sld_hub_inst|IRF_ENABLE[1]~136 at LC_X57_Y16_N2

--operation mode is normal

C1L26 = AMPP_FUNCTION(C1L25, C1L9, BF2_Q[0], BF8_Q[0]);

--SD1L145 is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|process4~0 at LC_X56_Y16_N1

--operation mode is normal

SD1L145 = AMPP_FUNCTION(BF2_Q[0], C1_jtag_debug_mode_usr1, BF8_Q[0], C1_jtag_debug_mode);

--BF7_Q[1] is sld_hub:sld_hub_inst|sld_dffex:\GEN_SHADOW_IRF:1:S_IRF|Q[1] at LC_X57_Y16_N6

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

BF7_Q[1] = AMPP_FUNCTION(A1L5, BF3_Q[1], !C1_CLR_SIGNAL, GND, C1L8);

--T1L490 is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|p1_registered_cpu_data_master_readdata[22]~2035 at LC_X37_Y22_N7

--operation mode is normal

T1L490 = KB1_za_data[22] # S1L207Q # !S1L1866Q # !S1L1686Q;

--NE2_b_full is std_1c20:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_r:the_jtag_uart_scfifo_r|scfifo:rfifo|scfifo_jf21:auto_generated|a_dpfifo_ml21:dpfifo|a_fefifo_7cf:fifo_state|b_full at LC_X45_Y21_N0

--operation mode is normal

NE2_b_full_lut_out = NE2_b_non_empty & !BB1L58 & (NE2_b_full # NE2L6) # !NE2_b_non_empty & NE2_b_full;

NE2_b_full = DFFEAS(NE2_b_full_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--BB1L31 is std_1c20:inst|jtag_uart:the_jtag_uart|Add1~296 at LC_X46_Y20_N6

--operation mode is arithmetic

BB1L31_carry_eqn = (!BB1L48 & BB1L37) # (BB1L48 & BB1L38);

BB1L31 = NE1_b_full $ !BB1L31_carry_eqn;

--BB1L32 is std_1c20:inst|jtag_uart:the_jtag_uart|Add1~297 at LC_X46_Y20_N6

--operation mode is arithmetic

BB1L32_cout_0 = !BB1L37 # !NE1_b_full;

BB1L32 = CARRY(BB1L32_cout_0);

--BB1L33 is std_1c20:inst|jtag_uart:the_jtag_uart|Add1~297COUT1_619 at LC_X46_Y20_N6

--operation mode is arithmetic

BB1L33_cout_1 = !BB1L38 # !NE1_b_full;

BB1L33 = CARRY(BB1L33_cout_1);

--BB1L34 is std_1c20:inst|jtag_uart:the_jtag_uart|Add1~298 at LC_X46_Y22_N4

--operation mode is normal

BB1L34 = BB1_read_0 & (NE2_b_full) # !BB1_read_0 & BB1L31;

--Z1_counter_snapshot[15] is std_1c20:inst|high_res_timer:the_high_res_timer|counter_snapshot[15] at LC_X56_Y24_N3

--operation mode is normal

Z1_counter_snapshot[15]_lut_out = !Z1_internal_counter[15];

Z1_counter_snapshot[15] = DFFEAS(Z1_counter_snapshot[15]_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , Z1L232, , , , );

--Z1L213 is std_1c20:inst|high_res_timer:the_high_res_timer|read_mux_out[15]~1253 at LC_X56_Y24_N0

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

Z1_counter_snapshot[31]_qfbk = Z1_counter_snapshot[31];

Z1L213 = S1L1738Q & (S1L1726Q & (Z1_counter_snapshot[31]_qfbk) # !S1L1726Q & Z1_counter_snapshot[15]) # !S1L1738Q & (S1L1726Q);

--Z1_counter_snapshot[31] is std_1c20:inst|high_res_timer:the_high_res_timer|counter_snapshot[31] at LC_X56_Y24_N0

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

Z1_counter_snapshot[31] = DFFEAS(Z1L213, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , Z1L232, Z1_internal_counter[31], , , VCC);

--Z1_period_l_register[15] is std_1c20:inst|high_res_timer:the_high_res_timer|period_l_register[15] at LC_X55_Y27_N5

--operation mode is normal

Z1_period_l_register[15]_lut_out = !S1L2319Q;

Z1_period_l_register[15] = DFFEAS(Z1_period_l_register[15]_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , Z1_period_l_wr_strobe, , , , );

--Z1L214 is std_1c20:inst|high_res_timer:the_high_res_timer|read_mux_out[15]~1254 at LC_X55_Y27_N7

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

Z1_period_h_register[15]_qfbk = Z1_period_h_register[15];

Z1L214 = Z1L213 & (Z1_period_h_register[15]_qfbk) # !Z1L213 & Z1_period_l_register[15];

--Z1_period_h_register[15] is std_1c20:inst|high_res_timer:the_high_res_timer|period_h_register[15] at LC_X55_Y27_N7

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

Z1_period_h_register[15] = DFFEAS(Z1L214, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , Z1_period_h_wr_strobe, S1L2319Q, , , VCC);

--RB1_counter_snapshot[15] is std_1c20:inst|sys_clk_timer:the_sys_clk_timer|counter_snapshot[15] at LC_X51_Y24_N2

--operation mode is normal

RB1_counter_snapshot[15]_lut_out = !RB1_internal_counter[15];

RB1_counter_snapshot[15] = DFFEAS(RB1_counter_snapshot[15]_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , RB1L235, , , , );

--RB1L216 is std_1c20:inst|sys_clk_timer:the_sys_clk_timer|read_mux_out[15]~1242 at LC_X51_Y24_N4

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

RB1_counter_snapshot[31]_qfbk = RB1_counter_snapshot[31];

RB1L216 = S1L1726Q & (RB1_counter_snapshot[31]_qfbk # !S1L1738Q) # !S1L1726Q & RB1_counter_snapshot[15] & (S1L1738Q);

--RB1_counter_snapshot[31] is std_1c20:inst|sys_clk_timer:the_sys_clk_timer|counter_snapshot[31] at LC_X51_Y24_N4

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

RB1_counter_snapshot[31] = DFFEAS(RB1L216, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , RB1L235, RB1_internal_counter[31], , , VCC);

--RB1_period_l_register[15] is std_1c20:inst|sys_clk_timer:the_sys_clk_timer|period_l_register[15] at LC_X51_Y27_N7

--operation mode is normal

RB1_period_l_register[15]_lut_out = !S1L2319Q;

RB1_period_l_register[15] = DFFEAS(RB1_period_l_register[15]_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , RB1_period_l_wr_strobe, , , , );

--RB1L217 is std_1c20:inst|sys_clk_timer:the_sys_clk_timer|read_mux_out[15]~1243 at LC_X51_Y25_N7

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

RB1_period_h_register[15]_qfbk = RB1_period_h_register[15];

RB1L217 = RB1L216 & (RB1_period_h_register[15]_qfbk) # !RB1L216 & RB1_period_l_register[15];

--RB1_period_h_register[15] is std_1c20:inst|sys_clk_timer:the_sys_clk_timer|period_h_register[15] at LC_X51_Y25_N7

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

RB1_period_h_register[15] = DFFEAS(RB1L217, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , RB1_period_h_wr_strobe, S1L2319Q, , , VCC);

--T1L392Q is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|dbs_8_reg_segment_1[6]~754 at LC_X33_Y26_N0

--operation mode is normal

T1L392Q_lut_out = !T1_internal_cpu_data_master_dbs_address[1] & T1L524 & T1_internal_cpu_data_master_dbs_address[0];

T1L392Q = DFFEAS(T1L392Q_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--J1_slave_readdata[15] is std_1c20:inst|clock_0:the_clock_0|slave_readdata[15] at LC_X44_Y27_N3

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

J1_slave_readdata[15]_lut_out = GND;

J1_slave_readdata[15] = DFFEAS(J1_slave_readdata[15]_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , J1_slave_readdata_p1[15], , , VCC);

--T1L485 is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|p1_registered_cpu_data_master_readdata[15]~2037 at LC_X44_Y27_N1

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

M1_slave_readdata[15]_qfbk = M1_slave_readdata[15];

T1L485 = S1L1743Q & (M1_slave_readdata[15]_qfbk) # !S1L1743Q & J1_slave_readdata[15] # !K1L6;

--M1_slave_readdata[15] is std_1c20:inst|clock_1:the_clock_1|slave_readdata[15] at LC_X44_Y27_N1

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

M1_slave_readdata[15] = DFFEAS(T1L485, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , M1_slave_readdata_p1[15], , , VCC);

--BB1_rvalid is std_1c20:inst|jtag_uart:the_jtag_uart|rvalid at LC_X44_Y21_N6

--operation mode is normal

BB1_rvalid_lut_out = BB1L58 & (NE2_b_non_empty) # !BB1L58 & BB1_rvalid;

BB1_rvalid = DFFEAS(BB1_rvalid_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--T1L513 is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|p1_registered_cpu_data_master_readdata~64 at LC_X44_Y22_N8

--operation mode is normal

T1L513 = BB1_rvalid # !CB1L2 # !UB1L9;

--V1L48 is std_1c20:inst|cpu_jtag_debug_module_arbitrator:the_cpu_jtag_debug_module|cpu_jtag_debug_module_byteenable[1]~6 at LC_X35_Y20_N5

--operation mode is normal

V1L48 = S1L2158Q # !V1L6;

--RD1_internal_MonDReg[8] is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|internal_MonDReg[8] at LC_X51_Y19_N7

--operation mode is normal

RD1_internal_MonDReg[8] = AMPP_FUNCTION(QC2__clk0, SD1_internal_jdo1[11], RD1_MonAReg[10], CE1_q_b[8], RD1L39, !C1_CLR_SIGNAL, RD1L38);

--RD1_internal_MonDReg[9] is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|internal_MonDReg[9] at LC_X51_Y19_N1

--operation mode is normal

RD1_internal_MonDReg[9] = AMPP_FUNCTION(QC2__clk0, CE1_q_b[9], RD1_MonAReg[10], SD1_internal_jdo1[12], RD1L28, !C1_CLR_SIGNAL, RD1L39, RD1L38);

--RD1_internal_MonDReg[10] is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|internal_MonDReg[10] at LC_X51_Y18_N5

--operation mode is normal

RD1_internal_MonDReg[10] = AMPP_FUNCTION(QC2__clk0, RD1_MonAReg[10], CE1_q_b[10], RD1L39, SD1_internal_jdo1[13], !C1_CLR_SIGNAL, RD1L38);

--RD1_internal_MonDReg[11] is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|internal_MonDReg[11] at LC_X51_Y19_N2

--operation mode is normal

RD1_internal_MonDReg[11] = AMPP_FUNCTION(QC2__clk0, CE1_q_b[11], RD1_MonAReg[10], SD1_internal_jdo1[14], RD1L28, !C1_CLR_SIGNAL, RD1L39, RD1L38);

--RD1_internal_MonDReg[12] is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|internal_MonDReg[12] at LC_X51_Y19_N9

--operation mode is normal

RD1_internal_MonDReg[12] = AMPP_FUNCTION(QC2__clk0, CE1_q_b[12], RD1L28, SD1_internal_jdo1[15], RD1_MonAReg[10], !C1_CLR_SIGNAL, RD1L39, RD1L38);

--RD1_internal_MonDReg[13] is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|internal_MonDReg[13] at LC_X51_Y17_N5

--operation mode is normal

RD1_internal_MonDReg[13] = AMPP_FUNCTION(QC2__clk0, RD1L39, SD1_internal_jdo1[16], RD1_MonAReg[10], CE1_q_b[13], !C1_CLR_SIGNAL, RD1L38);

--RD1_internal_MonDReg[14] is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|internal_MonDReg[14] at LC_X51_Y17_N8

--operation mode is normal

RD1_internal_MonDReg[14] = AMPP_FUNCTION(QC2__clk0, SD1_internal_jdo1[17], RD1_MonAReg[10], RD1L39, CE1_q_b[14], !C1_CLR_SIGNAL, RD1L38);

--RD1_internal_MonDReg[15] is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|internal_MonDReg[15] at LC_X48_Y17_N8

--operation mode is normal

RD1_internal_MonDReg[15] = AMPP_FUNCTION(QC2__clk0, RD1L39, RD1_MonAReg[10], SD1_internal_jdo1[18], CE1_q_b[15], !C1_CLR_SIGNAL, RD1L38);

--BB1L35 is std_1c20:inst|jtag_uart:the_jtag_uart|Add1~299 at LC_X46_Y20_N7

--operation mode is normal

BB1L35_carry_eqn = (!BB1L48 & BB1L32) # (BB1L48 & BB1L33);

BB1L35 = !BB1L35_carry_eqn;

--T1L491 is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|p1_registered_cpu_data_master_readdata[23]~2039 at LC_X46_Y22_N5

--operation mode is normal

T1L491 = BB1L35 & !BB1_read_0 # !UB1L9 # !CB1L2;

--RB1_counter_snapshot[23] is std_1c20:inst|sys_clk_timer:the_sys_clk_timer|counter_snapshot[23] at LC_X52_Y28_N9

--operation mode is normal

RB1_counter_snapshot[23]_lut_out = RB1_internal_counter[23];

RB1_counter_snapshot[23] = DFFEAS(RB1_counter_snapshot[23]_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , RB1L235, , , , );

--RB1L200 is std_1c20:inst|sys_clk_timer:the_sys_clk_timer|read_mux_out[7]~1245 at LC_X52_Y28_N6

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

RB1_counter_snapshot[7]_qfbk = RB1_counter_snapshot[7];

RB1L200 = S1L1726Q & (RB1_counter_snapshot[23] # !S1L1738Q) # !S1L1726Q & (RB1_counter_snapshot[7]_qfbk & S1L1738Q);

--RB1_counter_snapshot[7] is std_1c20:inst|sys_clk_timer:the_sys_clk_timer|counter_snapshot[7] at LC_X52_Y28_N6

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

RB1_counter_snapshot[7] = DFFEAS(RB1L200, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , RB1L235, RB1_internal_counter[7], , , VCC);

--RB1_period_l_register[7] is std_1c20:inst|sys_clk_timer:the_sys_clk_timer|period_l_register[7] at LC_X51_Y27_N6

--operation mode is normal

RB1_period_l_register[7]_lut_out = S1_M_st_data[7];

RB1_period_l_register[7] = DFFEAS(RB1_period_l_register[7]_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , RB1_period_l_wr_strobe, , , , );

--RB1L201 is std_1c20:inst|sys_clk_timer:the_sys_clk_timer|read_mux_out[7]~1246 at LC_X51_Y25_N0

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

RB1_period_h_register[7]_qfbk = RB1_period_h_register[7];

RB1L201 = RB1L200 & (RB1_period_h_register[7]_qfbk) # !RB1L200 & !RB1_period_l_register[7];

--RB1_period_h_register[7] is std_1c20:inst|sys_clk_timer:the_sys_clk_timer|period_h_register[7] at LC_X51_Y25_N0

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

RB1_period_h_register[7] = DFFEAS(RB1L201, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , RB1_period_h_wr_strobe, S1_M_st_data[7], , , VCC);

--Z1_counter_snapshot[23] is std_1c20:inst|high_res_timer:the_high_res_timer|counter_snapshot[23] at LC_X54_Y24_N7

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

Z1_counter_snapshot[23]_lut_out = GND;

Z1_counter_snapshot[23] = DFFEAS(Z1_counter_snapshot[23]_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , Z1L232, Z1_internal_counter[23], , , VCC);

--Z1L197 is std_1c20:inst|high_res_timer:the_high_res_timer|read_mux_out[7]~1256 at LC_X54_Y24_N2

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

Z1_counter_snapshot[7]_qfbk = Z1_counter_snapshot[7];

Z1L197 = S1L1738Q & (S1L1726Q & Z1_counter_snapshot[23] # !S1L1726Q & (Z1_counter_snapshot[7]_qfbk)) # !S1L1738Q & (S1L1726Q);

--Z1_counter_snapshot[7] is std_1c20:inst|high_res_timer:the_high_res_timer|counter_snapshot[7] at LC_X54_Y24_N2

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

Z1_counter_snapshot[7] = DFFEAS(Z1L197, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , Z1L232, Z1_internal_counter[7], , , VCC);

--Z1_period_l_register[7] is std_1c20:inst|high_res_timer:the_high_res_timer|period_l_register[7] at LC_X54_Y26_N0

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

Z1_period_l_register[7]_lut_out = GND;

Z1_period_l_register[7] = DFFEAS(Z1_period_l_register[7]_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , Z1_period_l_wr_strobe, S1_M_st_data[7], , , VCC);

--Z1L198 is std_1c20:inst|high_res_timer:the_high_res_timer|read_mux_out[7]~1257 at LC_X54_Y25_N2

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

Z1_period_h_register[7]_qfbk = Z1_period_h_register[7];

Z1L198 = Z1L197 & (Z1_period_h_register[7]_qfbk) # !Z1L197 & !Z1_period_l_register[7];

--Z1_period_h_register[7] is std_1c20:inst|high_res_timer:the_high_res_timer|period_h_register[7] at LC_X54_Y25_N2

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

Z1_period_h_register[7] = DFFEAS(Z1L198, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , Z1_period_h_wr_strobe, S1_M_st_data[7], , , VCC);

--XE1_control_reg[7] is std_1c20:inst|uart1:the_uart1|uart1_regs:the_uart1_regs|control_reg[7] at LC_X48_Y23_N5

--operation mode is normal

XE1_control_reg[7]_lut_out = S1_M_st_data[7];

XE1_control_reg[7] = DFFEAS(XE1_control_reg[7]_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , XE1L14, , , , );

--XE1L62 is std_1c20:inst|uart1:the_uart1|uart1_regs:the_uart1_regs|selected_read_data[7]~683 at LC_X48_Y23_N1

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

XE1_internal_tx_data[7]_qfbk = XE1_internal_tx_data[7];

XE1L62 = S1_M_alu_result[3] & XE1_control_reg[7] # !S1_M_alu_result[3] & (XE1_internal_tx_data[7]_qfbk);

--XE1_internal_tx_data[7] is std_1c20:inst|uart1:the_uart1|uart1_regs:the_uart1_regs|internal_tx_data[7] at LC_X48_Y23_N1

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

XE1_internal_tx_data[7] = DFFEAS(XE1L62, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , XE1L64, S1_M_st_data[7], , , VCC);

--YE1_internal_rx_char_ready is std_1c20:inst|uart1:the_uart1|uart1_rx:the_uart1_rx|internal_rx_char_ready at LC_X47_Y24_N9

--operation mode is normal

YE1_internal_rx_char_ready_lut_out = YE1L52 & (!YE1L64 # !ZE1L43 # !ZE1L42);

YE1_internal_rx_char_ready = DFFEAS(YE1_internal_rx_char_ready_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--XE1L63 is std_1c20:inst|uart1:the_uart1|uart1_regs:the_uart1_regs|selected_read_data[7]~684 at LC_X52_Y22_N3

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

YE1_rx_data[7]_qfbk = YE1_rx_data[7];

XE1L63 = S1_M_alu_result[3] & YE1_internal_rx_char_ready # !S1_M_alu_result[3] & (YE1_rx_data[7]_qfbk);

--YE1_rx_data[7] is std_1c20:inst|uart1:the_uart1|uart1_rx:the_uart1_rx|rx_data[7] at LC_X52_Y22_N3

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

YE1_rx_data[7] = DFFEAS(XE1L63, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , YE1_got_new_char, YE1_unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[8], , , VCC);

--J1_slave_readdata[7] is std_1c20:inst|clock_0:the_clock_0|slave_readdata[7] at LC_X45_Y28_N2

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

J1_slave_readdata[7]_lut_out = GND;

J1_slave_readdata[7] = DFFEAS(J1_slave_readdata[7]_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , J1_slave_readdata_p1[7], , , VCC);

--T1L477 is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|p1_registered_cpu_data_master_readdata[7]~2041 at LC_X45_Y28_N7

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

M1_slave_readdata[7]_qfbk = M1_slave_readdata[7];

T1L477 = S1L1743Q & (M1_slave_readdata[7]_qfbk) # !S1L1743Q & J1_slave_readdata[7] # !K1L6;

--M1_slave_readdata[7] is std_1c20:inst|clock_1:the_clock_1|slave_readdata[7] at LC_X45_Y28_N7

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

M1_slave_readdata[7] = DFFEAS(T1L477, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , M1_slave_readdata_p1[7], , , VCC);

--T1L507 is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|p1_registered_cpu_data_master_readdata~56 at LC_X46_Y22_N2

--operation mode is normal

T1L507 = BB1_read_0 & SE2_q_b[7] # !UB1L9 # !CB1L2;

--DE1_iRRDY_reg is std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|iRRDY_reg at LC_X39_Y27_N1

--operation mode is normal

DE1_iRRDY_reg_lut_out = S1_M_st_data[7];

DE1_iRRDY_reg = DFFEAS(DE1_iRRDY_reg_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , DE1_control_wr_strobe, , , , );

--DE1L4 is std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|A_WE_StdLogicVector~1120 at LC_X35_Y27_N8

--operation mode is normal

DE1L4 = !DE1L21 & DE1L230Q & X1L33 & X1L28;

--DE1L5 is std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|A_WE_StdLogicVector~1121 at LC_X39_Y28_N1

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

DE1_rx_holding_reg[7]_qfbk = DE1_rx_holding_reg[7];

DE1L5 = DE1_rx_holding_reg[7]_qfbk & (DE1L21 # !X1L28 # !X1L33);

--DE1_rx_holding_reg[7] is std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|rx_holding_reg[7] at LC_X39_Y28_N1

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

DE1_rx_holding_reg[7] = DFFEAS(DE1L5, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , DE1L302, DE1_shift_reg[7], , , VCC);

--DE1L6 is std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|A_WE_StdLogicVector~1122 at LC_X39_Y27_N3

--operation mode is normal

DE1L6 = DE1L47 & DE1L119Q # !DE1L47 & (DE1L4 # DE1L5);

--DE1_RRDY is std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|RRDY at LC_X39_Y27_N0

--operation mode is normal

DE1_RRDY_lut_out = DE1L302 # DE1_RRDY & !DE1_status_wr_strobe & !DE1L164Q;

DE1_RRDY = DFFEAS(DE1_RRDY_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--T1L499 is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|p1_registered_cpu_data_master_readdata[31]~2043 at LC_X36_Y22_N8

--operation mode is normal

T1L499 = S1L207Q # KB1_za_data[31] # !S1L1686Q # !S1L1866Q;

--V1L50 is std_1c20:inst|cpu_jtag_debug_module_arbitrator:the_cpu_jtag_debug_module|cpu_jtag_debug_module_byteenable[3]~7 at LC_X34_Y20_N9

--operation mode is normal

V1L50 = S1L2177Q # !V1L6;

--RD1_internal_MonDReg[24] is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|internal_MonDReg[24] at LC_X51_Y18_N2

--operation mode is normal

RD1_internal_MonDReg[24] = AMPP_FUNCTION(QC2__clk0, RD1_MonAReg[10], CE1_q_b[24], SD1_internal_jdo1[27], RD1L30, !C1_CLR_SIGNAL, RD1L39, RD1L38);

--RD1_internal_MonDReg[25] is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|internal_MonDReg[25] at LC_X48_Y18_N0

--operation mode is normal

RD1_internal_MonDReg[25] = AMPP_FUNCTION(QC2__clk0, RD1L39, RD1_MonAReg[10], CE1_q_b[25], SD1_internal_jdo1[28], !C1_CLR_SIGNAL, RD1L38);

--RD1_internal_MonDReg[26] is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|internal_MonDReg[26] at LC_X48_Y18_N4

--operation mode is normal

RD1_internal_MonDReg[26] = AMPP_FUNCTION(QC2__clk0, RD1L39, RD1_MonAReg[10], SD1_internal_jdo1[29], CE1_q_b[26], !C1_CLR_SIGNAL, RD1L38);

--RD1_internal_MonDReg[27] is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|internal_MonDReg[27] at LC_X51_Y17_N6

--operation mode is normal

RD1_internal_MonDReg[27] = AMPP_FUNCTION(QC2__clk0, RD1L29, RD1_MonAReg[10], SD1_internal_jdo1[30], CE1_q_b[27], !C1_CLR_SIGNAL, RD1L39, RD1L38);

--RD1_internal_MonDReg[28] is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|internal_MonDReg[28] at LC_X48_Y17_N3

--operation mode is normal

RD1_internal_MonDReg[28] = AMPP_FUNCTION(QC2__clk0, RD1L39, RD1_MonAReg[10], SD1_internal_jdo1[31], CE1_q_b[28], !C1_CLR_SIGNAL, RD1L38);

--RD1_internal_MonDReg[29] is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|internal_MonDReg[29] at LC_X51_Y17_N3

--operation mode is normal

RD1_internal_MonDReg[29] = AMPP_FUNCTION(QC2__clk0, RD1L29, RD1_MonAReg[10], SD1_internal_jdo1[32], CE1_q_b[29], !C1_CLR_SIGNAL, RD1L39, RD1L38);

--RD1_internal_MonDReg[30] is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|internal_MonDReg[30] at LC_X51_Y18_N9

--operation mode is normal

RD1_internal_MonDReg[30] = AMPP_FUNCTION(QC2__clk0, RD1_MonAReg[10], CE1_q_b[30], RD1L39, SD1_internal_jdo1[33], !C1_CLR_SIGNAL, RD1L38);

--RD1_internal_MonDReg[31] is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|internal_MonDReg[31] at LC_X51_Y18_N8

--operation mode is normal

RD1_internal_MonDReg[31] = AMPP_FUNCTION(QC2__clk0, RD1_MonAReg[10], SD1_internal_jdo1[34], RD1L39, CE1_q_b[31], !C1_CLR_SIGNAL, RD1L38);

--T1L489 is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|p1_registered_cpu_data_master_readdata[21]~2045 at LC_X36_Y23_N8

--operation mode is normal

T1L489 = S1L207Q # KB1_za_data[21] # !S1L1686Q # !S1L1866Q;

--RE2_safe_q[5] is std_1c20:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_r:the_jtag_uart_scfifo_r|scfifo:rfifo|scfifo_jf21:auto_generated|a_dpfifo_ml21:dpfifo|a_fefifo_7cf:fifo_state|cntr_9c7:count_usedw|safe_q[5] at LC_X46_Y21_N7

--operation mode is normal

RE2_safe_q[5]_carry_eqn = (!RE2L8 & RE2L15) # (RE2L8 & RE2L16);

RE2_safe_q[5]_lut_out = RE2_safe_q[5] $ (RE2_safe_q[5]_carry_eqn);

RE2_safe_q[5] = DFFEAS(RE2_safe_q[5]_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , NE2L1, , , , );

--BB1L36 is std_1c20:inst|jtag_uart:the_jtag_uart|Add1~301 at LC_X46_Y20_N5

--operation mode is arithmetic

BB1L36_carry_eqn = (!BB1L48 & GND) # (BB1L48 & VCC);

BB1L36 = RE1_safe_q[5] $ (!BB1L36_carry_eqn);

--BB1L37 is std_1c20:inst|jtag_uart:the_jtag_uart|Add1~302 at LC_X46_Y20_N5

--operation mode is arithmetic

BB1L37_cout_0 = RE1_safe_q[5] # !BB1L48;

BB1L37 = CARRY(BB1L37_cout_0);

--BB1L38 is std_1c20:inst|jtag_uart:the_jtag_uart|Add1~302COUT1_617 at LC_X46_Y20_N5

--operation mode is arithmetic

BB1L38_cout_1 = RE1_safe_q[5] # !BB1L48;

BB1L38 = CARRY(BB1L38_cout_1);

--BB1L39 is std_1c20:inst|jtag_uart:the_jtag_uart|Add1~303 at LC_X46_Y22_N8

--operation mode is normal

BB1L39 = BB1_read_0 & (RE2_safe_q[5]) # !BB1_read_0 & BB1L36;

--S1_i_readdata_d1[22] is std_1c20:inst|cpu:the_cpu|i_readdata_d1[22] at LC_X42_Y20_N2

--operation mode is normal

S1_i_readdata_d1[22] = AMPP_FUNCTION(QC2__clk0, U1L112, S1L1451, WC1L21, WC1L26, F1_data_out);

--S1_i_readdata_d1[23] is std_1c20:inst|cpu:the_cpu|i_readdata_d1[23] at LC_X43_Y20_N7

--operation mode is normal

S1_i_readdata_d1[23] = AMPP_FUNCTION(QC2__clk0, S1L1451, U1L115, WC1L27, WC1L21, F1_data_out);

--S1_i_readdata_d1[24] is std_1c20:inst|cpu:the_cpu|i_readdata_d1[24] at LC_X39_Y21_N9

--operation mode is normal

S1_i_readdata_d1[24] = AMPP_FUNCTION(QC2__clk0, U1L118, S1L1451, WC1L28, WC1L21, F1_data_out);

--S1_i_readdata_d1[25] is std_1c20:inst|cpu:the_cpu|i_readdata_d1[25] at LC_X43_Y21_N6

--operation mode is normal

S1_i_readdata_d1[25] = AMPP_FUNCTION(QC2__clk0, WC1L21, S1L1451, WC1L29, U1L121, F1_data_out);

--S1_i_readdata_d1[26] is std_1c20:inst|cpu:the_cpu|i_readdata_d1[26] at LC_X43_Y21_N2

--operation mode is normal

S1_i_readdata_d1[26] = AMPP_FUNCTION(QC2__clk0, WC1L21, S1L1451, WC1L30, U1L124, F1_data_out);

--T1L492 is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|p1_registered_cpu_data_master_readdata[24]~2047 at LC_X39_Y22_N5

--operation mode is normal

T1L492 = KB1_za_data[24] # S1L207Q # !S1L1686Q # !S1L1866Q;

--RE2_safe_q[0] is std_1c20:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_r:the_jtag_uart_scfifo_r|scfifo:rfifo|scfifo_jf21:auto_generated|a_dpfifo_ml21:dpfifo|a_fefifo_7cf:fifo_state|cntr_9c7:count_usedw|safe_q[0] at LC_X46_Y21_N2

--operation mode is arithmetic

RE2_safe_q[0]_lut_out = !RE2_safe_q[0];

RE2_safe_q[0] = DFFEAS(RE2_safe_q[0]_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , NE2L1, , , , );

--RE2L2 is std_1c20:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_r:the_jtag_uart_scfifo_r|scfifo:rfifo|scfifo_jf21:auto_generated|a_dpfifo_ml21:dpfifo|a_fefifo_7cf:fifo_state|cntr_9c7:count_usedw|counter_cella0~COUT at LC_X46_Y21_N2

--operation mode is arithmetic

RE2L2_cout_0 = RE2_safe_q[0] $ !BB1_wr_rfifo;

RE2L2 = CARRY(RE2L2_cout_0);

--RE2L3 is std_1c20:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_r:the_jtag_uart_scfifo_r|scfifo:rfifo|scfifo_jf21:auto_generated|a_dpfifo_ml21:dpfifo|a_fefifo_7cf:fifo_state|cntr_9c7:count_usedw|counter_cella0~COUTCOUT1_70 at LC_X46_Y21_N2

--operation mode is arithmetic

RE2L3_cout_1 = RE2_safe_q[0] $ !BB1_wr_rfifo;

RE2L3 = CARRY(RE2L3_cout_1);

--RE1_safe_q[0] is std_1c20:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_w:the_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_jf21:auto_generated|a_dpfifo_ml21:dpfifo|a_fefifo_7cf:fifo_state|cntr_9c7:count_usedw|safe_q[0] at LC_X47_Y20_N1

--operation mode is arithmetic

RE1_safe_q[0]_lut_out = !RE1_safe_q[0];

RE1_safe_q[0] = DFFEAS(RE1_safe_q[0]_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , NE1L1, , , , );

--RE1L2 is std_1c20:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_w:the_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_jf21:auto_generated|a_dpfifo_ml21:dpfifo|a_fefifo_7cf:fifo_state|cntr_9c7:count_usedw|counter_cella0~COUT at LC_X47_Y20_N1

--operation mode is arithmetic

RE1L2_cout_0 = RE1_safe_q[0] $ !BB1_fifo_wr;

RE1L2 = CARRY(RE1L2_cout_0);

--RE1L3 is std_1c20:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_w:the_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_jf21:auto_generated|a_dpfifo_ml21:dpfifo|a_fefifo_7cf:fifo_state|cntr_9c7:count_usedw|counter_cella0~COUTCOUT1_70 at LC_X47_Y20_N1

--operation mode is arithmetic

RE1L3_cout_1 = RE1_safe_q[0] $ !BB1_fifo_wr;

RE1L3 = CARRY(RE1L3_cout_1);

--BB1L40 is std_1c20:inst|jtag_uart:the_jtag_uart|Add1~304 at LC_X46_Y21_N8

--operation mode is normal

BB1L40 = BB1_read_0 & RE2_safe_q[0] # !BB1_read_0 & (RE1_safe_q[0]);

--BB1L41 is std_1c20:inst|jtag_uart:the_jtag_uart|Add1~305 at LC_X43_Y22_N3

--operation mode is normal

BB1L41 = BB1L40 # !UB1L9 # !CB1L2;

--S1_i_readdata_d1[20] is std_1c20:inst|cpu:the_cpu|i_readdata_d1[20] at LC_X39_Y21_N0

--operation mode is normal

S1_i_readdata_d1[20] = AMPP_FUNCTION(QC2__clk0, U1L106, S1L1451, WC1L24, WC1L21, F1_data_out);

--J1_slave_readdata[14] is std_1c20:inst|clock_0:the_clock_0|slave_readdata[14] at LC_X45_Y28_N0

--operation mode is normal

J1_slave_readdata[14]_lut_out = J1_slave_readdata_p1[14];

J1_slave_readdata[14] = DFFEAS(J1_slave_readdata[14]_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--T1L484 is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|p1_registered_cpu_data_master_readdata[14]~2050 at LC_X45_Y28_N9

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

M1_slave_readdata[14]_qfbk = M1_slave_readdata[14];

T1L484 = S1L1743Q & (M1_slave_readdata[14]_qfbk) # !S1L1743Q & J1_slave_readdata[14] # !K1L6;

--M1_slave_readdata[14] is std_1c20:inst|clock_1:the_clock_1|slave_readdata[14] at LC_X45_Y28_N9

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

M1_slave_readdata[14] = DFFEAS(T1L484, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , M1_slave_readdata_p1[14], , , VCC);

--BB1_woverflow is std_1c20:inst|jtag_uart:the_jtag_uart|woverflow at LC_X46_Y24_N9

--operation mode is normal

BB1_woverflow_lut_out = S1L1726Q & BB1_woverflow # !S1L1726Q & (BB1L71 & (NE1_b_full) # !BB1L71 & BB1_woverflow);

BB1_woverflow = DFFEAS(BB1_woverflow_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--T1L512 is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|p1_registered_cpu_data_master_readdata~63 at LC_X45_Y24_N5

--operation mode is normal

T1L512 = BB1_woverflow # !CB1L2 # !UB1L9;

--RB1_counter_snapshot[30] is std_1c20:inst|sys_clk_timer:the_sys_clk_timer|counter_snapshot[30] at LC_X53_Y24_N8

--operation mode is normal

RB1_counter_snapshot[30]_lut_out = RB1_internal_counter[30];

RB1_counter_snapshot[30] = DFFEAS(RB1_counter_snapshot[30]_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , RB1L235, , , , );

--RB1L214 is std_1c20:inst|sys_clk_timer:the_sys_clk_timer|read_mux_out[14]~1248 at LC_X51_Y24_N3

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

RB1_counter_snapshot[14]_qfbk = RB1_counter_snapshot[14];

RB1L214 = S1L1726Q & (RB1_counter_snapshot[30] # !S1L1738Q) # !S1L1726Q & (RB1_counter_snapshot[14]_qfbk & S1L1738Q);

--RB1_counter_snapshot[14] is std_1c20:inst|sys_clk_timer:the_sys_clk_timer|counter_snapshot[14] at LC_X51_Y24_N3

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

RB1_counter_snapshot[14] = DFFEAS(RB1L214, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , RB1L235, RB1_internal_counter[14], , , VCC);

--RB1_period_l_register[14] is std_1c20:inst|sys_clk_timer:the_sys_clk_timer|period_l_register[14] at LC_X51_Y26_N8

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

RB1_period_l_register[14]_lut_out = GND;

RB1_period_l_register[14] = DFFEAS(RB1_period_l_register[14]_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , RB1_period_l_wr_strobe, S1L2313Q, , , VCC);

--RB1L215 is std_1c20:inst|sys_clk_timer:the_sys_clk_timer|read_mux_out[14]~1249 at LC_X51_Y26_N0

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

RB1_period_h_register[14]_qfbk = RB1_period_h_register[14];

RB1L215 = RB1L214 & (RB1_period_h_register[14]_qfbk) # !RB1L214 & !RB1_period_l_register[14];

--RB1_period_h_register[14] is std_1c20:inst|sys_clk_timer:the_sys_clk_timer|period_h_register[14] at LC_X51_Y26_N0

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

RB1_period_h_register[14] = DFFEAS(RB1L215, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , RB1_period_h_wr_strobe, S1L2313Q, , , VCC);

--Z1_counter_snapshot[14] is std_1c20:inst|high_res_timer:the_high_res_timer|counter_snapshot[14] at LC_X56_Y25_N6

--operation mode is normal

Z1_counter_snapshot[14]_lut_out = !Z1_internal_counter[14];

Z1_counter_snapshot[14] = DFFEAS(Z1_counter_snapshot[14]_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , Z1L232, , , , );

--Z1L211 is std_1c20:inst|high_res_timer:the_high_res_timer|read_mux_out[14]~1259 at LC_X56_Y24_N7

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

Z1_counter_snapshot[30]_qfbk = Z1_counter_snapshot[30];

Z1L211 = S1L1738Q & (S1L1726Q & (Z1_counter_snapshot[30]_qfbk) # !S1L1726Q & Z1_counter_snapshot[14]) # !S1L1738Q & (S1L1726Q);

--Z1_counter_snapshot[30] is std_1c20:inst|high_res_timer:the_high_res_timer|counter_snapshot[30] at LC_X56_Y24_N7

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

Z1_counter_snapshot[30] = DFFEAS(Z1L211, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , Z1L232, Z1_internal_counter[30], , , VCC);

--Z1_period_l_register[14] is std_1c20:inst|high_res_timer:the_high_res_timer|period_l_register[14] at LC_X54_Y26_N5

--operation mode is normal

Z1_period_l_register[14]_lut_out = !S1L2313Q;

Z1_period_l_register[14] = DFFEAS(Z1_period_l_register[14]_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , Z1_period_l_wr_strobe, , , , );

--Z1L212 is std_1c20:inst|high_res_timer:the_high_res_timer|read_mux_out[14]~1260 at LC_X54_Y26_N4

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

Z1_period_h_register[14]_qfbk = Z1_period_h_register[14];

Z1L212 = Z1L211 & (Z1_period_h_register[14]_qfbk) # !Z1L211 & Z1_period_l_register[14];

--Z1_period_h_register[14] is std_1c20:inst|high_res_timer:the_high_res_timer|period_h_register[14] at LC_X54_Y26_N4

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

Z1_period_h_register[14] = DFFEAS(Z1L212, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , Z1_period_h_wr_strobe, S1L2313Q, , , VCC);

--T1L498 is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|p1_registered_cpu_data_master_readdata[30]~2052 at LC_X36_Y22_N2

--operation mode is normal

T1L498 = S1L207Q # KB1_za_data[30] # !S1L1686Q # !S1L1866Q;

--S1_i_readdata_d1[19] is std_1c20:inst|cpu:the_cpu|i_readdata_d1[19] at LC_X39_Y21_N6

--operation mode is normal

S1_i_readdata_d1[19] = AMPP_FUNCTION(QC2__clk0, U1L103, S1L1451, WC1L23, WC1L21, F1_data_out);

--J1_slave_readdata[13] is std_1c20:inst|clock_0:the_clock_0|slave_readdata[13] at LC_X45_Y27_N3

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

J1_slave_readdata[13]_lut_out = GND;

J1_slave_readdata[13] = DFFEAS(J1_slave_readdata[13]_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , J1_slave_readdata_p1[13], , , VCC);

--T1L483 is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|p1_registered_cpu_data_master_readdata[13]~2054 at LC_X45_Y27_N1

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

M1_slave_readdata[13]_qfbk = M1_slave_readdata[13];

T1L483 = S1L1743Q & (M1_slave_readdata[13]_qfbk) # !S1L1743Q & J1_slave_readdata[13] # !K1L6;

--M1_slave_readdata[13] is std_1c20:inst|clock_1:the_clock_1|slave_readdata[13] at LC_X45_Y27_N1

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

M1_slave_readdata[13] = DFFEAS(T1L483, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , M1_slave_readdata_p1[13], , , VCC);

--NE1_b_full is std_1c20:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_w:the_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_jf21:auto_generated|a_dpfifo_ml21:dpfifo|a_fefifo_7cf:fifo_state|b_full at LC_X48_Y20_N8

--operation mode is normal

NE1_b_full_lut_out = !BB1_rd_wfifo & (NE1_b_full # NE1L4 & NE1L3);

NE1_b_full = DFFEAS(NE1_b_full_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--T1L511 is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|p1_registered_cpu_data_master_readdata~62 at LC_X46_Y24_N8

--operation mode is normal

T1L511 = !CB1L2 # !UB1L9 # !NE1_b_full;

--Z1_counter_snapshot[29] is std_1c20:inst|high_res_timer:the_high_res_timer|counter_snapshot[29] at LC_X56_Y24_N2

--operation mode is normal

Z1_counter_snapshot[29]_lut_out = Z1_internal_counter[29];

Z1_counter_snapshot[29] = DFFEAS(Z1_counter_snapshot[29]_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , Z1L232, , , , );

--Z1L209 is std_1c20:inst|high_res_timer:the_high_res_timer|read_mux_out[13]~1262 at LC_X56_Y25_N1

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

Z1_counter_snapshot[13]_qfbk = Z1_counter_snapshot[13];

Z1L209 = S1L1726Q & (Z1_counter_snapshot[29] # !S1L1738Q) # !S1L1726Q & (Z1_counter_snapshot[13]_qfbk & S1L1738Q);

--Z1_counter_snapshot[13] is std_1c20:inst|high_res_timer:the_high_res_timer|counter_snapshot[13] at LC_X56_Y25_N1

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

Z1_counter_snapshot[13] = DFFEAS(Z1L209, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , Z1L232, Z1_internal_counter[13], , , VCC);

--Z1_period_l_register[13] is std_1c20:inst|high_res_timer:the_high_res_timer|period_l_register[13] at LC_X54_Y26_N3

--operation mode is normal

Z1_period_l_register[13]_lut_out = S1L2307Q;

Z1_period_l_register[13] = DFFEAS(Z1_period_l_register[13]_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , Z1_period_l_wr_strobe, , , , );

--Z1L210 is std_1c20:inst|high_res_timer:the_high_res_timer|read_mux_out[13]~1263 at LC_X54_Y26_N6

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

Z1_period_h_register[13]_qfbk = Z1_period_h_register[13];

Z1L210 = Z1L209 & (Z1_period_h_register[13]_qfbk) # !Z1L209 & !Z1_period_l_register[13];

--Z1_period_h_register[13] is std_1c20:inst|high_res_timer:the_high_res_timer|period_h_register[13] at LC_X54_Y26_N6

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

Z1_period_h_register[13] = DFFEAS(Z1L210, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , Z1_period_h_wr_strobe, S1L2307Q, , , VCC);

--RB1_counter_snapshot[13] is std_1c20:inst|sys_clk_timer:the_sys_clk_timer|counter_snapshot[13] at LC_X51_Y24_N7

--operation mode is normal

RB1_counter_snapshot[13]_lut_out = !RB1_internal_counter[13];

RB1_counter_snapshot[13] = DFFEAS(RB1_counter_snapshot[13]_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , RB1L235, , , , );

--RB1L212 is std_1c20:inst|sys_clk_timer:the_sys_clk_timer|read_mux_out[13]~1251 at LC_X51_Y24_N8

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

RB1_counter_snapshot[29]_qfbk = RB1_counter_snapshot[29];

RB1L212 = S1L1726Q & (RB1_counter_snapshot[29]_qfbk # !S1L1738Q) # !S1L1726Q & RB1_counter_snapshot[13] & (S1L1738Q);

--RB1_counter_snapshot[29] is std_1c20:inst|sys_clk_timer:the_sys_clk_timer|counter_snapshot[29] at LC_X51_Y24_N8

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

RB1_counter_snapshot[29] = DFFEAS(RB1L212, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , RB1L235, RB1_internal_counter[29], , , VCC);

--RB1_period_l_register[13] is std_1c20:inst|sys_clk_timer:the_sys_clk_timer|period_l_register[13] at LC_X51_Y27_N5

--operation mode is normal

RB1_period_l_register[13]_lut_out = !S1L2307Q;

RB1_period_l_register[13] = DFFEAS(RB1_period_l_register[13]_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , RB1_period_l_wr_strobe, , , , );

--RB1L213 is std_1c20:inst|sys_clk_timer:the_sys_clk_timer|read_mux_out[13]~1252 at LC_X51_Y25_N3

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

RB1_period_h_register[13]_qfbk = RB1_period_h_register[13];

RB1L213 = RB1L212 & (RB1_period_h_register[13]_qfbk) # !RB1L212 & RB1_period_l_register[13];

--RB1_period_h_register[13] is std_1c20:inst|sys_clk_timer:the_sys_clk_timer|period_h_register[13] at LC_X51_Y25_N3

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

RB1_period_h_register[13] = DFFEAS(RB1L213, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , RB1_period_h_wr_strobe, S1L2307Q, , , VCC);

--T1L497 is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|p1_registered_cpu_data_master_readdata[29]~2056 at LC_X36_Y23_N7

--operation mode is normal

T1L497 = S1L207Q # KB1_za_data[29] # !S1L1866Q # !S1L1686Q;

--S1_D_br_taken_waddr_partial[10] is std_1c20:inst|cpu:the_cpu|D_br_taken_waddr_partial[10] at LC_X26_Y18_N5

--operation mode is normal

S1_D_br_taken_waddr_partial[10] = AMPP_FUNCTION(QC2__clk0, F1_data_out, S1_W_stall, S1L269);

--S1_i_readdata_d1[18] is std_1c20:inst|cpu:the_cpu|i_readdata_d1[18] at LC_X43_Y20_N2

--operation mode is normal

S1_i_readdata_d1[18] = AMPP_FUNCTION(QC2__clk0, S1L1451, U1L100, WC1L22, WC1L21, F1_data_out);

--J1_slave_readdata[12] is std_1c20:inst|clock_0:the_clock_0|slave_readdata[12] at LC_X45_Y27_N4

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

J1_slave_readdata[12]_lut_out = GND;

J1_slave_readdata[12] = DFFEAS(J1_slave_readdata[12]_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , J1_slave_readdata_p1[12], , , VCC);

--T1L482 is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|p1_registered_cpu_data_master_readdata[12]~2058 at LC_X45_Y27_N6

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

M1_slave_readdata[12]_qfbk = M1_slave_readdata[12];

T1L482 = S1L1743Q & (M1_slave_readdata[12]_qfbk) # !S1L1743Q & J1_slave_readdata[12] # !K1L6;

--M1_slave_readdata[12] is std_1c20:inst|clock_1:the_clock_1|slave_readdata[12] at LC_X45_Y27_N6

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

M1_slave_readdata[12] = DFFEAS(T1L482, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , M1_slave_readdata_p1[12], , , VCC);

--NE2_b_non_empty is std_1c20:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_r:the_jtag_uart_scfifo_r|scfifo:rfifo|scfifo_jf21:auto_generated|a_dpfifo_ml21:dpfifo|a_fefifo_7cf:fifo_state|b_non_empty at LC_X45_Y21_N9

--operation mode is normal

NE2_b_non_empty_lut_out = NE2L8 # NE2_b_non_empty & (NE2L3 # !BB1L58);

NE2_b_non_empty = DFFEAS(NE2_b_non_empty_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--T1L510 is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|p1_registered_cpu_data_master_readdata~61 at LC_X44_Y21_N5

--operation mode is normal

T1L510 = NE2_b_non_empty # !UB1L9 # !CB1L2;

--Z1_counter_snapshot[28] is std_1c20:inst|high_res_timer:the_high_res_timer|counter_snapshot[28] at LC_X56_Y24_N5

--operation mode is normal

Z1_counter_snapshot[28]_lut_out = Z1_internal_counter[28];

Z1_counter_snapshot[28] = DFFEAS(Z1_counter_snapshot[28]_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , Z1L232, , , , );

--Z1L207 is std_1c20:inst|high_res_timer:the_high_res_timer|read_mux_out[12]~1265 at LC_X56_Y25_N7

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

Z1_counter_snapshot[12]_qfbk = Z1_counter_snapshot[12];

Z1L207 = S1L1726Q & (Z1_counter_snapshot[28] # !S1L1738Q) # !S1L1726Q & (Z1_counter_snapshot[12]_qfbk & S1L1738Q);

--Z1_counter_snapshot[12] is std_1c20:inst|high_res_timer:the_high_res_timer|counter_snapshot[12] at LC_X56_Y25_N7

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

Z1_counter_snapshot[12] = DFFEAS(Z1L207, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , Z1L232, Z1_internal_counter[12], , , VCC);

--Z1_period_l_register[12] is std_1c20:inst|high_res_timer:the_high_res_timer|period_l_register[12] at LC_X56_Y27_N6

--operation mode is normal

Z1_period_l_register[12]_lut_out = S1L2301Q;

Z1_period_l_register[12] = DFFEAS(Z1_period_l_register[12]_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , Z1_period_l_wr_strobe, , , , );

--Z1L208 is std_1c20:inst|high_res_timer:the_high_res_timer|read_mux_out[12]~1266 at LC_X56_Y27_N8

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

Z1_period_h_register[12]_qfbk = Z1_period_h_register[12];

Z1L208 = Z1L207 & (Z1_period_h_register[12]_qfbk) # !Z1L207 & !Z1_period_l_register[12];

--Z1_period_h_register[12] is std_1c20:inst|high_res_timer:the_high_res_timer|period_h_register[12] at LC_X56_Y27_N8

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

Z1_period_h_register[12] = DFFEAS(Z1L208, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , Z1_period_h_wr_strobe, S1L2301Q, , , VCC);

--RB1_counter_snapshot[28] is std_1c20:inst|sys_clk_timer:the_sys_clk_timer|counter_snapshot[28] at LC_X51_Y24_N9

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

RB1_counter_snapshot[28]_lut_out = GND;

RB1_counter_snapshot[28] = DFFEAS(RB1_counter_snapshot[28]_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , RB1L235, RB1_internal_counter[28], , , VCC);

--RB1L210 is std_1c20:inst|sys_clk_timer:the_sys_clk_timer|read_mux_out[12]~1254 at LC_X51_Y24_N1

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

RB1_counter_snapshot[12]_qfbk = RB1_counter_snapshot[12];

RB1L210 = S1L1726Q & (RB1_counter_snapshot[28] # !S1L1738Q) # !S1L1726Q & (RB1_counter_snapshot[12]_qfbk & S1L1738Q);

--RB1_counter_snapshot[12] is std_1c20:inst|sys_clk_timer:the_sys_clk_timer|counter_snapshot[12] at LC_X51_Y24_N1

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

RB1_counter_snapshot[12] = DFFEAS(RB1L210, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , RB1L235, RB1_internal_counter[12], , , VCC);

--RB1_period_l_register[12] is std_1c20:inst|sys_clk_timer:the_sys_clk_timer|period_l_register[12] at LC_X51_Y26_N2

--operation mode is normal

RB1_period_l_register[12]_lut_out = S1L2301Q;

RB1_period_l_register[12] = DFFEAS(RB1_period_l_register[12]_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , RB1_period_l_wr_strobe, , , , );

--RB1L211 is std_1c20:inst|sys_clk_timer:the_sys_clk_timer|read_mux_out[12]~1255 at LC_X51_Y26_N4

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

RB1_period_h_register[12]_qfbk = RB1_period_h_register[12];

RB1L211 = RB1L210 & (RB1_period_h_register[12]_qfbk) # !RB1L210 & !RB1_period_l_register[12];

--RB1_period_h_register[12] is std_1c20:inst|sys_clk_timer:the_sys_clk_timer|period_h_register[12] at LC_X51_Y26_N4

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

RB1_period_h_register[12] = DFFEAS(RB1L211, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , RB1_period_h_wr_strobe, S1L2301Q, , , VCC);

--T1L496 is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|p1_registered_cpu_data_master_readdata[28]~2060 at LC_X37_Y22_N0

--operation mode is normal

T1L496 = KB1_za_data[28] # S1L207Q # !S1L1866Q # !S1L1686Q;

--RE2_safe_q[1] is std_1c20:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_r:the_jtag_uart_scfifo_r|scfifo:rfifo|scfifo_jf21:auto_generated|a_dpfifo_ml21:dpfifo|a_fefifo_7cf:fifo_state|cntr_9c7:count_usedw|safe_q[1] at LC_X46_Y21_N3

--operation mode is arithmetic

RE2_safe_q[1]_lut_out = RE2_safe_q[1] $ RE2L2;

RE2_safe_q[1] = DFFEAS(RE2_safe_q[1]_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , NE2L1, , , , );

--RE2L5 is std_1c20:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_r:the_jtag_uart_scfifo_r|scfifo:rfifo|scfifo_jf21:auto_generated|a_dpfifo_ml21:dpfifo|a_fefifo_7cf:fifo_state|cntr_9c7:count_usedw|counter_cella1~COUT at LC_X46_Y21_N3

--operation mode is arithmetic

RE2L5_cout_0 = BB1_wr_rfifo $ RE2_safe_q[1] # !RE2L2;

RE2L5 = CARRY(RE2L5_cout_0);

--RE2L6 is std_1c20:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_r:the_jtag_uart_scfifo_r|scfifo:rfifo|scfifo_jf21:auto_generated|a_dpfifo_ml21:dpfifo|a_fefifo_7cf:fifo_state|cntr_9c7:count_usedw|counter_cella1~COUTCOUT1_61 at LC_X46_Y21_N3

--operation mode is arithmetic

RE2L6_cout_1 = BB1_wr_rfifo $ RE2_safe_q[1] # !RE2L3;

RE2L6 = CARRY(RE2L6_cout_1);

--BB1L42 is std_1c20:inst|jtag_uart:the_jtag_uart|Add1~306 at LC_X46_Y20_N1

--operation mode is arithmetic

BB1L42 = RE1_safe_q[1] $ (!BB1L53);

--BB1L43 is std_1c20:inst|jtag_uart:the_jtag_uart|Add1~307 at LC_X46_Y20_N1

--operation mode is arithmetic

BB1L43_cout_0 = RE1_safe_q[1] # !BB1L53;

BB1L43 = CARRY(BB1L43_cout_0);

--BB1L44 is std_1c20:inst|jtag_uart:the_jtag_uart|Add1~307COUT1_611 at LC_X46_Y20_N1

--operation mode is arithmetic

BB1L44_cout_1 = RE1_safe_q[1] # !BB1L54;

BB1L44 = CARRY(BB1L44_cout_1);

--BB1L45 is std_1c20:inst|jtag_uart:the_jtag_uart|Add1~308 at LC_X46_Y21_N1

--operation mode is normal

BB1L45 = BB1_read_0 & RE2_safe_q[1] # !BB1_read_0 & (BB1L42);

--BB1L46 is std_1c20:inst|jtag_uart:the_jtag_uart|Add1~309 at LC_X43_Y22_N7

--operation mode is normal

BB1L46 = BB1L45 # !UB1L9 # !CB1L2;

--S1_M_shift_rot_result[28] is std_1c20:inst|cpu:the_cpu|M_shift_rot_result[28] at LC_X40_Y12_N2

--operation mode is normal

S1_M_shift_rot_result[28] = AMPP_FUNCTION(QC2__clk0, S1_M_shift_rot_result[27], S1_M_shift_rot_result[29], S1L881, S1_M_ctrl_shift_rot_right, F1_data_out, !S1_M_shift_rot_stall);

--S1_E_src1_prelim[27] is std_1c20:inst|cpu:the_cpu|E_src1_prelim[27] at LC_X43_Y13_N0

--operation mode is normal

S1_E_src1_prelim[27] = AMPP_FUNCTION(QC2__clk0, S1_W_wr_data[27], S1_D_src1_hazard_W, S1L2473, CD1_q_b[27], F1_data_out, S1_D_src1_hazard_M, S1_W_stall);

--S1L2471 is std_1c20:inst|cpu:the_cpu|M_wr_data_unfiltered[27]~3701 at LC_X43_Y13_N7

--operation mode is normal

S1L2471 = AMPP_FUNCTION(S1L2062Q, S1_M_shift_rot_result[27]);

--S1L216 is std_1c20:inst|cpu:the_cpu|av_ld_data_aligned_or_div[27]~78 at LC_X41_Y19_N2

--operation mode is normal

S1L216 = AMPP_FUNCTION(S1_M_iw[4], S1L622, S1_M_ctrl_ld_signed, S1L239);

--S1_av_ld_data_aligned_or_div[27] is std_1c20:inst|cpu:the_cpu|av_ld_data_aligned_or_div[27] at LC_X41_Y19_N2

--operation mode is normal

S1_av_ld_data_aligned_or_div[27] = AMPP_FUNCTION(QC2__clk0, S1_M_iw[4], S1L622, S1_M_ctrl_ld_signed, S1L239, F1_data_out);

--S1L217Q is std_1c20:inst|cpu:the_cpu|av_ld_data_aligned_or_div[27]~79 at LC_X41_Y12_N4

--operation mode is normal

S1L217Q = AMPP_FUNCTION(QC2__clk0, S1_av_ld_aligning_data, S1L2057, S1L1917, S1L216, F1_data_out);

--S1L880 is std_1c20:inst|cpu:the_cpu|E_src1[27]~2043 at LC_X43_Y13_N2

--operation mode is normal

S1L880 = AMPP_FUNCTION(S1L886Q, S1_E_src1_prelim[27], S1L2471, S1L217Q);

--YC1_result[26] is std_1c20:inst|cpu:the_cpu|lpm_add_sub:Add8|alt_stratix_add_sub:stratix_adder|result[26] at LC_X36_Y14_N6

--operation mode is arithmetic

YC1_result[26] = AMPP_FUNCTION(S1L1045, S1L879, YC1L71, YC1L73, YC1L74, S1_E_ctrl_alu_subtract);

--YC1L76 is std_1c20:inst|cpu:the_cpu|lpm_add_sub:Add8|alt_stratix_add_sub:stratix_adder|add_sub_cell[26]~COUT at LC_X36_Y14_N6

--operation mode is arithmetic

YC1L76 = AMPP_FUNCTION(S1L1045, S1L879, YC1L73, S1_E_ctrl_alu_subtract);

--YC1L77 is std_1c20:inst|cpu:the_cpu|lpm_add_sub:Add8|alt_stratix_add_sub:stratix_adder|add_sub_cell[26]~COUTCOUT1_1337 at LC_X36_Y14_N6

--operation mode is arithmetic

YC1L77 = AMPP_FUNCTION(S1L1045, S1L879, YC1L74, S1_E_ctrl_alu_subtract);

--S1_E_src2_imm[26] is std_1c20:inst|cpu:the_cpu|E_src2_imm[26] at LC_X40_Y13_N1

--operation mode is normal

S1_E_src2_imm[26] = AMPP_FUNCTION(QC2__clk0, S1_D_iw[16], S1_D_iw[21], S1L311, S1L301, F1_data_out, S1_W_stall);

--S1_E_src2_prelim[26] is std_1c20:inst|cpu:the_cpu|E_src2_prelim[26] at LC_X44_Y14_N6

--operation mode is normal

S1_E_src2_prelim[26] = AMPP_FUNCTION(QC2__clk0, DD1_q_b[26], S1_W_wr_data[26], S1L2470, S1L668, F1_data_out, S1L664, S1_W_stall);

--S1L1144 is std_1c20:inst|cpu:the_cpu|E_src2_reg[26]~475 at LC_X44_Y13_N6

--operation mode is normal

S1L1144 = AMPP_FUNCTION(S1L214Q, S1_E_src2_prelim[26], S1L2468, S1_E_src2_hazard_M);

--S1L1045 is std_1c20:inst|cpu:the_cpu|E_src2[26]~1530 at LC_X44_Y13_N8

--operation mode is normal

S1L1045 = AMPP_FUNCTION(S1L2468, S1L1049, S1L214Q, S1L1047);

--T1L493 is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|p1_registered_cpu_data_master_readdata[25]~2063 at LC_X39_Y24_N5

--operation mode is normal

T1L493 = S1L207Q # KB1_za_data[25] # !S1L1866Q # !S1L1686Q;

--T1L488 is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|p1_registered_cpu_data_master_readdata[20]~2065 at LC_X37_Y22_N1

--operation mode is normal

T1L488 = KB1_za_data[20] # S1L207Q # !S1L1866Q # !S1L1686Q;

--RE2_safe_q[4] is std_1c20:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_r:the_jtag_uart_scfifo_r|scfifo:rfifo|scfifo_jf21:auto_generated|a_dpfifo_ml21:dpfifo|a_fefifo_7cf:fifo_state|cntr_9c7:count_usedw|safe_q[4] at LC_X46_Y21_N6

--operation mode is arithmetic

RE2_safe_q[4]_carry_eqn = (!RE2L8 & RE2L12) # (RE2L8 & RE2L13);

RE2_safe_q[4]_lut_out = RE2_safe_q[4] $ (!RE2_safe_q[4]_carry_eqn);

RE2_safe_q[4] = DFFEAS(RE2_safe_q[4]_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , NE2L1, , , , );

--RE2L15 is std_1c20:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_r:the_jtag_uart_scfifo_r|scfifo:rfifo|scfifo_jf21:auto_generated|a_dpfifo_ml21:dpfifo|a_fefifo_7cf:fifo_state|cntr_9c7:count_usedw|counter_cella4~COUT at LC_X46_Y21_N6

--operation mode is arithmetic

RE2L15_cout_0 = !RE2L12 & (RE2_safe_q[4] $ !BB1_wr_rfifo);

RE2L15 = CARRY(RE2L15_cout_0);

--RE2L16 is std_1c20:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_r:the_jtag_uart_scfifo_r|scfifo:rfifo|scfifo_jf21:auto_generated|a_dpfifo_ml21:dpfifo|a_fefifo_7cf:fifo_state|cntr_9c7:count_usedw|counter_cella4~COUTCOUT1_61 at LC_X46_Y21_N6

--operation mode is arithmetic

RE2L16_cout_1 = !RE2L13 & (RE2_safe_q[4] $ !BB1_wr_rfifo);

RE2L16 = CARRY(RE2L16_cout_1);

--BB1L47 is std_1c20:inst|jtag_uart:the_jtag_uart|Add1~310 at LC_X46_Y20_N4

--operation mode is arithmetic

BB1L47 = RE1_safe_q[4] $ BB1L28;

--BB1L48 is std_1c20:inst|jtag_uart:the_jtag_uart|Add1~311 at LC_X46_Y20_N4

--operation mode is arithmetic

BB1L48 = BB1L49;

--BB1L51 is std_1c20:inst|jtag_uart:the_jtag_uart|Add1~312 at LC_X46_Y22_N9

--operation mode is normal

BB1L51 = BB1_read_0 & RE2_safe_q[4] # !BB1_read_0 & (BB1L47);

--S1L1447 is std_1c20:inst|cpu:the_cpu|i_readdata_d1[10]~139 at LC_X42_Y22_N2

--operation mode is normal

S1L1447 = AMPP_FUNCTION(S1L524Q, S1L1449Q, S1L1450Q, S1L1448Q);

--S1_i_readdata_d1[17] is std_1c20:inst|cpu:the_cpu|i_readdata_d1[17] at LC_X41_Y21_N6

--operation mode is normal

S1_i_readdata_d1[17] = AMPP_FUNCTION(QC2__clk0, WC1L21, S1L1451, U1L97, WC1L20, F1_data_out);

--T1L481 is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|p1_registered_cpu_data_master_readdata[11]~2067 at LC_X41_Y25_N0

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

J1_slave_readdata[11]_qfbk = J1_slave_readdata[11];

T1L481 = K1_cpu_data_master_requests_clock_0_in & J1_slave_readdata[11]_qfbk & (KB1_za_data[11] # !S1L1693Q) # !K1_cpu_data_master_requests_clock_0_in & (KB1_za_data[11] # !S1L1693Q);

--J1_slave_readdata[11] is std_1c20:inst|clock_0:the_clock_0|slave_readdata[11] at LC_X41_Y25_N0

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

J1_slave_readdata[11] = DFFEAS(T1L481, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , J1_slave_readdata_p1[11], , , VCC);

--M1_slave_readdata[11] is std_1c20:inst|clock_1:the_clock_1|slave_readdata[11] at LC_X46_Y27_N8

--operation mode is normal

M1_slave_readdata[11]_lut_out = M1_slave_readdata_p1[11];

M1_slave_readdata[11] = DFFEAS(M1_slave_readdata[11]_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--Z1_counter_snapshot[27] is std_1c20:inst|high_res_timer:the_high_res_timer|counter_snapshot[27] at LC_X56_Y24_N9

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

Z1_counter_snapshot[27]_lut_out = GND;

Z1_counter_snapshot[27] = DFFEAS(Z1_counter_snapshot[27]_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , Z1L232, Z1_internal_counter[27], , , VCC);

--Z1L205 is std_1c20:inst|high_res_timer:the_high_res_timer|read_mux_out[11]~1268 at LC_X56_Y25_N8

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

Z1_counter_snapshot[11]_qfbk = Z1_counter_snapshot[11];

Z1L205 = S1L1726Q & (Z1_counter_snapshot[27] # !S1L1738Q) # !S1L1726Q & (Z1_counter_snapshot[11]_qfbk & S1L1738Q);

--Z1_counter_snapshot[11] is std_1c20:inst|high_res_timer:the_high_res_timer|counter_snapshot[11] at LC_X56_Y25_N8

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

Z1_counter_snapshot[11] = DFFEAS(Z1L205, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , Z1L232, Z1_internal_counter[11], , , VCC);

--Z1_period_l_register[11] is std_1c20:inst|high_res_timer:the_high_res_timer|period_l_register[11] at LC_X55_Y27_N4

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

Z1_period_l_register[11]_lut_out = GND;

Z1_period_l_register[11] = DFFEAS(Z1_period_l_register[11]_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , Z1_period_l_wr_strobe, S1L2294Q, , , VCC);

--Z1L206 is std_1c20:inst|high_res_timer:the_high_res_timer|read_mux_out[11]~1269 at LC_X55_Y27_N0

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

Z1_period_h_register[11]_qfbk = Z1_period_h_register[11];

Z1L206 = Z1L205 & (Z1_period_h_register[11]_qfbk) # !Z1L205 & !Z1_period_l_register[11];

--Z1_period_h_register[11] is std_1c20:inst|high_res_timer:the_high_res_timer|period_h_register[11] at LC_X55_Y27_N0

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

Z1_period_h_register[11] = DFFEAS(Z1L206, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , Z1_period_h_wr_strobe, S1L2294Q, , , VCC);

--RB1_counter_snapshot[27] is std_1c20:inst|sys_clk_timer:the_sys_clk_timer|counter_snapshot[27] at LC_X53_Y24_N7

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

RB1_counter_snapshot[27]_lut_out = GND;

RB1_counter_snapshot[27] = DFFEAS(RB1_counter_snapshot[27]_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , RB1L235, RB1_internal_counter[27], , , VCC);

--RB1L208 is std_1c20:inst|sys_clk_timer:the_sys_clk_timer|read_mux_out[11]~1257 at LC_X53_Y26_N5

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

RB1_counter_snapshot[11]_qfbk = RB1_counter_snapshot[11];

RB1L208 = S1L1726Q & (RB1_counter_snapshot[27] # !S1L1738Q) # !S1L1726Q & (RB1_counter_snapshot[11]_qfbk & S1L1738Q);

--RB1_counter_snapshot[11] is std_1c20:inst|sys_clk_timer:the_sys_clk_timer|counter_snapshot[11] at LC_X53_Y26_N5

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

RB1_counter_snapshot[11] = DFFEAS(RB1L208, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , RB1L235, RB1_internal_counter[11], , , VCC);

--RB1_period_l_register[11] is std_1c20:inst|sys_clk_timer:the_sys_clk_timer|period_l_register[11] at LC_X51_Y26_N7

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

RB1_period_l_register[11]_lut_out = GND;

RB1_period_l_register[11] = DFFEAS(RB1_period_l_register[11]_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , RB1_period_l_wr_strobe, S1L2294Q, , , VCC);

--RB1L209 is std_1c20:inst|sys_clk_timer:the_sys_clk_timer|read_mux_out[11]~1258 at LC_X51_Y26_N6

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

RB1_period_h_register[11]_qfbk = RB1_period_h_register[11];

RB1L209 = RB1L208 & (RB1_period_h_register[11]_qfbk) # !RB1L208 & !RB1_period_l_register[11];

--RB1_period_h_register[11] is std_1c20:inst|sys_clk_timer:the_sys_clk_timer|period_h_register[11] at LC_X51_Y26_N6

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

RB1_period_h_register[11] = DFFEAS(RB1L209, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , RB1_period_h_wr_strobe, S1L2294Q, , , VCC);

--T1L495 is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|p1_registered_cpu_data_master_readdata[27]~2069 at LC_X39_Y25_N2

--operation mode is normal

T1L495 = KB1_za_data[27] # S1L207Q # !S1L1686Q # !S1L1866Q;

--DE1L7 is std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|A_WE_StdLogicVector~1127 at LC_X36_Y27_N0

--operation mode is normal

DE1L7 = !DE1L21 & DE1L236Q & X1L28 & X1L33;

--Z1_counter_snapshot[26] is std_1c20:inst|high_res_timer:the_high_res_timer|counter_snapshot[26] at LC_X56_Y24_N8

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

Z1_counter_snapshot[26]_lut_out = GND;

Z1_counter_snapshot[26] = DFFEAS(Z1_counter_snapshot[26]_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , Z1L232, Z1_internal_counter[26], , , VCC);

--Z1L203 is std_1c20:inst|high_res_timer:the_high_res_timer|read_mux_out[10]~1271 at LC_X56_Y25_N4

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

Z1_counter_snapshot[10]_qfbk = Z1_counter_snapshot[10];

Z1L203 = S1L1726Q & (Z1_counter_snapshot[26] # !S1L1738Q) # !S1L1726Q & (Z1_counter_snapshot[10]_qfbk & S1L1738Q);

--Z1_counter_snapshot[10] is std_1c20:inst|high_res_timer:the_high_res_timer|counter_snapshot[10] at LC_X56_Y25_N4

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

Z1_counter_snapshot[10] = DFFEAS(Z1L203, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , Z1L232, Z1_internal_counter[10], , , VCC);

--Z1_period_l_register[10] is std_1c20:inst|high_res_timer:the_high_res_timer|period_l_register[10] at LC_X55_Y27_N9

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

Z1_period_l_register[10]_lut_out = GND;

Z1_period_l_register[10] = DFFEAS(Z1_period_l_register[10]_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , Z1_period_l_wr_strobe, S1L2288Q, , , VCC);

--Z1L204 is std_1c20:inst|high_res_timer:the_high_res_timer|read_mux_out[10]~1272 at LC_X55_Y27_N2

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

Z1_period_h_register[10]_qfbk = Z1_period_h_register[10];

Z1L204 = Z1L203 & (Z1_period_h_register[10]_qfbk) # !Z1L203 & !Z1_period_l_register[10];

--Z1_period_h_register[10] is std_1c20:inst|high_res_timer:the_high_res_timer|period_h_register[10] at LC_X55_Y27_N2

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

Z1_period_h_register[10] = DFFEAS(Z1L204, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , Z1_period_h_wr_strobe, S1L2288Q, , , VCC);

--RB1_counter_snapshot[26] is std_1c20:inst|sys_clk_timer:the_sys_clk_timer|counter_snapshot[26] at LC_X53_Y24_N2

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

RB1_counter_snapshot[26]_lut_out = GND;

RB1_counter_snapshot[26] = DFFEAS(RB1_counter_snapshot[26]_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , RB1L235, RB1_internal_counter[26], , , VCC);

--RB1L206 is std_1c20:inst|sys_clk_timer:the_sys_clk_timer|read_mux_out[10]~1260 at LC_X53_Y26_N6

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

RB1_counter_snapshot[10]_qfbk = RB1_counter_snapshot[10];

RB1L206 = S1L1738Q & (S1L1726Q & RB1_counter_snapshot[26] # !S1L1726Q & (RB1_counter_snapshot[10]_qfbk)) # !S1L1738Q & (S1L1726Q);

--RB1_counter_snapshot[10] is std_1c20:inst|sys_clk_timer:the_sys_clk_timer|counter_snapshot[10] at LC_X53_Y26_N6

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

RB1_counter_snapshot[10] = DFFEAS(RB1L206, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , RB1L235, RB1_internal_counter[10], , , VCC);

--RB1_period_l_register[10] is std_1c20:inst|sys_clk_timer:the_sys_clk_timer|period_l_register[10] at LC_X51_Y27_N3

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

RB1_period_l_register[10]_lut_out = GND;

RB1_period_l_register[10] = DFFEAS(RB1_period_l_register[10]_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , RB1_period_l_wr_strobe, S1L2288Q, , , VCC);

--RB1L207 is std_1c20:inst|sys_clk_timer:the_sys_clk_timer|read_mux_out[10]~1261 at LC_X48_Y26_N5

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

RB1_period_h_register[10]_qfbk = RB1_period_h_register[10];

RB1L207 = RB1L206 & (RB1_period_h_register[10]_qfbk) # !RB1L206 & !RB1_period_l_register[10];

--RB1_period_h_register[10] is std_1c20:inst|sys_clk_timer:the_sys_clk_timer|period_h_register[10] at LC_X48_Y26_N5

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

RB1_period_h_register[10] = DFFEAS(RB1L207, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , RB1_period_h_wr_strobe, S1L2288Q, , , VCC);

--J1_slave_readdata[10] is std_1c20:inst|clock_0:the_clock_0|slave_readdata[10] at LC_X45_Y27_N5

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

J1_slave_readdata[10]_lut_out = GND;

J1_slave_readdata[10] = DFFEAS(J1_slave_readdata[10]_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , J1_slave_readdata_p1[10], , , VCC);

--T1L480 is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|p1_registered_cpu_data_master_readdata[10]~2071 at LC_X45_Y27_N2

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

M1_slave_readdata[10]_qfbk = M1_slave_readdata[10];

T1L480 = S1L1743Q & (M1_slave_readdata[10]_qfbk) # !S1L1743Q & J1_slave_readdata[10] # !K1L6;

--M1_slave_readdata[10] is std_1c20:inst|clock_1:the_clock_1|slave_readdata[10] at LC_X45_Y27_N2

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

M1_slave_readdata[10] = DFFEAS(T1L480, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , M1_slave_readdata_p1[10], , , VCC);

--BB1_ac is std_1c20:inst|jtag_uart:the_jtag_uart|ac at LC_X44_Y22_N6

--operation mode is normal

BB1_ac_lut_out = BB1L2 # BB1_ac & (!BB1L61 # !S1L2288Q);

BB1_ac = DFFEAS(BB1_ac_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--T1L509 is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|p1_registered_cpu_data_master_readdata~59 at LC_X44_Y22_N2

--operation mode is normal

T1L509 = BB1_ac # !CB1L2 # !UB1L9;

--T1L494 is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|p1_registered_cpu_data_master_readdata[26]~2073 at LC_X37_Y24_N9

--operation mode is normal

T1L494 = S1L207Q # KB1_za_data[26] # !S1L1866Q # !S1L1686Q;

--DE1L8 is std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|A_WE_StdLogicVector~1128 at LC_X37_Y26_N3

--operation mode is normal

DE1L8 = X1L28 & (DE1L19) # !X1L28 & DE1L124Q & DE1L17 & !DE1L19;

--DE1L157 is std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|EOP~168 at LC_X37_Y27_N6

--operation mode is normal

DE1L157 = !DE1L159Q & (DE1L158Q # DE1L160Q & DE1L153);

--DE1L158Q is std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|EOP~169 at LC_X37_Y27_N6

--operation mode is normal

DE1L158Q = DFFEAS(DE1L157, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--Z1_counter_snapshot[9] is std_1c20:inst|high_res_timer:the_high_res_timer|counter_snapshot[9] at LC_X56_Y24_N6

--operation mode is normal

Z1_counter_snapshot[9]_lut_out = !Z1_internal_counter[9];

Z1_counter_snapshot[9] = DFFEAS(Z1_counter_snapshot[9]_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , Z1L232, , , , );

--Z1L201 is std_1c20:inst|high_res_timer:the_high_res_timer|read_mux_out[9]~1274 at LC_X56_Y24_N4

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

Z1_counter_snapshot[25]_qfbk = Z1_counter_snapshot[25];

Z1L201 = S1L1726Q & (Z1_counter_snapshot[25]_qfbk # !S1L1738Q) # !S1L1726Q & Z1_counter_snapshot[9] & (S1L1738Q);

--Z1_counter_snapshot[25] is std_1c20:inst|high_res_timer:the_high_res_timer|counter_snapshot[25] at LC_X56_Y24_N4

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

Z1_counter_snapshot[25] = DFFEAS(Z1L201, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , Z1L232, Z1_internal_counter[25], , , VCC);

--Z1_period_l_register[9] is std_1c20:inst|high_res_timer:the_high_res_timer|period_l_register[9] at LC_X56_Y27_N5

--operation mode is normal

Z1_period_l_register[9]_lut_out = !S1L2281Q;

Z1_period_l_register[9] = DFFEAS(Z1_period_l_register[9]_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , Z1_period_l_wr_strobe, , , , );

--Z1L202 is std_1c20:inst|high_res_timer:the_high_res_timer|read_mux_out[9]~1275 at LC_X56_Y27_N2

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

Z1_period_h_register[9]_qfbk = Z1_period_h_register[9];

Z1L202 = Z1L201 & (Z1_period_h_register[9]_qfbk) # !Z1L201 & Z1_period_l_register[9];

--Z1_period_h_register[9] is std_1c20:inst|high_res_timer:the_high_res_timer|period_h_register[9] at LC_X56_Y27_N2

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

Z1_period_h_register[9] = DFFEAS(Z1L202, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , Z1_period_h_wr_strobe, S1L2281Q, , , VCC);

--RB1_counter_snapshot[25] is std_1c20:inst|sys_clk_timer:the_sys_clk_timer|counter_snapshot[25] at LC_X53_Y26_N3

--operation mode is normal

RB1_counter_snapshot[25]_lut_out = RB1_internal_counter[25];

RB1_counter_snapshot[25] = DFFEAS(RB1_counter_snapshot[25]_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , RB1L235, , , , );

--RB1L204 is std_1c20:inst|sys_clk_timer:the_sys_clk_timer|read_mux_out[9]~1263 at LC_X53_Y26_N7

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

RB1_counter_snapshot[9]_qfbk = RB1_counter_snapshot[9];

RB1L204 = S1L1726Q & (RB1_counter_snapshot[25] # !S1L1738Q) # !S1L1726Q & (RB1_counter_snapshot[9]_qfbk & S1L1738Q);

--RB1_counter_snapshot[9] is std_1c20:inst|sys_clk_timer:the_sys_clk_timer|counter_snapshot[9] at LC_X53_Y26_N7

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

RB1_counter_snapshot[9] = DFFEAS(RB1L204, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , RB1L235, RB1_internal_counter[9], , , VCC);

--RB1_period_l_register[9] is std_1c20:inst|sys_clk_timer:the_sys_clk_timer|period_l_register[9] at LC_X51_Y27_N0

--operation mode is normal

RB1_period_l_register[9]_lut_out = S1L2281Q;

RB1_period_l_register[9] = DFFEAS(RB1_period_l_register[9]_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , RB1_period_l_wr_strobe, , , , );

--RB1L205 is std_1c20:inst|sys_clk_timer:the_sys_clk_timer|read_mux_out[9]~1264 at LC_X51_Y25_N5

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

RB1_period_h_register[9]_qfbk = RB1_period_h_register[9];

RB1L205 = RB1L204 & (RB1_period_h_register[9]_qfbk) # !RB1L204 & !RB1_period_l_register[9];

--RB1_period_h_register[9] is std_1c20:inst|sys_clk_timer:the_sys_clk_timer|period_h_register[9] at LC_X51_Y25_N5

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

RB1_period_h_register[9] = DFFEAS(RB1L205, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , RB1_period_h_wr_strobe, S1L2281Q, , , VCC);

--J1_slave_readdata[9] is std_1c20:inst|clock_0:the_clock_0|slave_readdata[9] at LC_X44_Y27_N4

--operation mode is normal

J1_slave_readdata[9]_lut_out = J1_slave_readdata_p1[9];

J1_slave_readdata[9] = DFFEAS(J1_slave_readdata[9]_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--T1L479 is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|p1_registered_cpu_data_master_readdata[9]~2075 at LC_X44_Y27_N6

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

M1_slave_readdata[9]_qfbk = M1_slave_readdata[9];

T1L479 = S1L1743Q & (M1_slave_readdata[9]_qfbk) # !S1L1743Q & J1_slave_readdata[9] # !K1L6;

--M1_slave_readdata[9] is std_1c20:inst|clock_1:the_clock_1|slave_readdata[9] at LC_X44_Y27_N6

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

M1_slave_readdata[9] = DFFEAS(T1L479, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , M1_slave_readdata_p1[9], , , VCC);

--Z1_counter_snapshot[8] is std_1c20:inst|high_res_timer:the_high_res_timer|counter_snapshot[8] at LC_X56_Y25_N9

--operation mode is normal

Z1_counter_snapshot[8]_lut_out = !Z1_internal_counter[8];

Z1_counter_snapshot[8] = DFFEAS(Z1_counter_snapshot[8]_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , Z1L232, , , , );

--Z1L199 is std_1c20:inst|high_res_timer:the_high_res_timer|read_mux_out[8]~1277 at LC_X56_Y24_N1

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

Z1_counter_snapshot[24]_qfbk = Z1_counter_snapshot[24];

Z1L199 = S1L1738Q & (S1L1726Q & (Z1_counter_snapshot[24]_qfbk) # !S1L1726Q & Z1_counter_snapshot[8]) # !S1L1738Q & (S1L1726Q);

--Z1_counter_snapshot[24] is std_1c20:inst|high_res_timer:the_high_res_timer|counter_snapshot[24] at LC_X56_Y24_N1

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

Z1_counter_snapshot[24] = DFFEAS(Z1L199, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , Z1L232, Z1_internal_counter[24], , , VCC);

--Z1_period_l_register[8] is std_1c20:inst|high_res_timer:the_high_res_timer|period_l_register[8] at LC_X54_Y28_N8

--operation mode is normal

Z1_period_l_register[8]_lut_out = !S1L2275Q;

Z1_period_l_register[8] = DFFEAS(Z1_period_l_register[8]_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , Z1_period_l_wr_strobe, , , , );

--Z1L200 is std_1c20:inst|high_res_timer:the_high_res_timer|read_mux_out[8]~1278 at LC_X51_Y23_N8

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

Z1_period_h_register[8]_qfbk = Z1_period_h_register[8];

Z1L200 = Z1L199 & (Z1_period_h_register[8]_qfbk) # !Z1L199 & Z1_period_l_register[8];

--Z1_period_h_register[8] is std_1c20:inst|high_res_timer:the_high_res_timer|period_h_register[8] at LC_X51_Y23_N8

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

Z1_period_h_register[8] = DFFEAS(Z1L200, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , Z1_period_h_wr_strobe, S1L2275Q, , , VCC);

--XE1L22 is std_1c20:inst|uart1:the_uart1|uart1_regs:the_uart1_regs|Equal1~123 at LC_X48_Y22_N2

--operation mode is normal

XE1L22 = !S1L1738Q & S1_M_alu_result[3];

--YE1_framing_error is std_1c20:inst|uart1:the_uart1|uart1_rx:the_uart1_rx|framing_error at LC_X51_Y22_N9

--operation mode is normal

YE1_framing_error_lut_out = YE1L49 & (!XE1L13 # !XE1L20);

YE1_framing_error = DFFEAS(YE1_framing_error_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--ZE1_tx_overrun is std_1c20:inst|uart1:the_uart1|uart1_tx:the_uart1_tx|tx_overrun at LC_X51_Y22_N7

--operation mode is normal

ZE1_tx_overrun_lut_out = XE1L13 & !XE1L20 & (ZE1_tx_overrun # ZE1L40) # !XE1L13 & (ZE1_tx_overrun # ZE1L40);

ZE1_tx_overrun = DFFEAS(ZE1_tx_overrun_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--XE1L1 is std_1c20:inst|uart1:the_uart1|uart1_regs:the_uart1_regs|any_error~21 at LC_X48_Y22_N7

--operation mode is normal

XE1L1 = YE1_rx_overrun # YE1_framing_error # ZE1_tx_overrun # YE1_break_detect;

--J1_slave_readdata[8] is std_1c20:inst|clock_0:the_clock_0|slave_readdata[8] at LC_X44_Y27_N5

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

J1_slave_readdata[8]_lut_out = GND;

J1_slave_readdata[8] = DFFEAS(J1_slave_readdata[8]_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , J1_slave_readdata_p1[8], , , VCC);

--T1L478 is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|p1_registered_cpu_data_master_readdata[8]~2077 at LC_X44_Y27_N8

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

M1_slave_readdata[8]_qfbk = M1_slave_readdata[8];

T1L478 = S1L1743Q & (M1_slave_readdata[8]_qfbk) # !S1L1743Q & J1_slave_readdata[8] # !K1L6;

--M1_slave_readdata[8] is std_1c20:inst|clock_1:the_clock_1|slave_readdata[8] at LC_X44_Y27_N8

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

M1_slave_readdata[8] = DFFEAS(T1L478, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , M1_slave_readdata_p1[8], , , VCC);

--T1L515 is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|p1_registered_cpu_data_master_readdata~2078 at LC_X44_Y21_N9

--operation mode is normal

T1L515 = T1L514 # !UB1L9 # !CB1L2;

--RB1_counter_snapshot[8] is std_1c20:inst|sys_clk_timer:the_sys_clk_timer|counter_snapshot[8] at LC_X53_Y26_N0

--operation mode is normal

RB1_counter_snapshot[8]_lut_out = !RB1_internal_counter[8];

RB1_counter_snapshot[8] = DFFEAS(RB1_counter_snapshot[8]_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , RB1L235, , , , );

--RB1L202 is std_1c20:inst|sys_clk_timer:the_sys_clk_timer|read_mux_out[8]~1266 at LC_X53_Y26_N8

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

RB1_counter_snapshot[24]_qfbk = RB1_counter_snapshot[24];

RB1L202 = S1L1726Q & (RB1_counter_snapshot[24]_qfbk # !S1L1738Q) # !S1L1726Q & RB1_counter_snapshot[8] & (S1L1738Q);

--RB1_counter_snapshot[24] is std_1c20:inst|sys_clk_timer:the_sys_clk_timer|counter_snapshot[24] at LC_X53_Y26_N8

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

RB1_counter_snapshot[24] = DFFEAS(RB1L202, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , RB1L235, RB1_internal_counter[24], , , VCC);

--RB1_period_l_register[8] is std_1c20:inst|sys_clk_timer:the_sys_clk_timer|period_l_register[8] at LC_X51_Y26_N3

--operation mode is normal

RB1_period_l_register[8]_lut_out = !S1L2275Q;

RB1_period_l_register[8] = DFFEAS(RB1_period_l_register[8]_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , RB1_period_l_wr_strobe, , , , );

--RB1L203 is std_1c20:inst|sys_clk_timer:the_sys_clk_timer|read_mux_out[8]~1267 at LC_X51_Y26_N9

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

RB1_period_h_register[8]_qfbk = RB1_period_h_register[8];

RB1L203 = RB1L202 & (RB1_period_h_register[8]_qfbk) # !RB1L202 & RB1_period_l_register[8];

--RB1_period_h_register[8] is std_1c20:inst|sys_clk_timer:the_sys_clk_timer|period_h_register[8] at LC_X51_Y26_N9

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

RB1_period_h_register[8] = DFFEAS(RB1L203, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , RB1_period_h_wr_strobe, S1L2275Q, , , VCC);

--DE1L9 is std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|A_WE_StdLogicVector~1129 at LC_X38_Y27_N2

--operation mode is normal

DE1L9 = DE1L47 & DE1L121Q # !DE1L47 & (DE1L232Q & DE1L74);

--DE1_TOE is std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|TOE at LC_X38_Y28_N9

--operation mode is normal

DE1_TOE_lut_out = !DE1_status_wr_strobe & (DE1_TOE # !DE1L339 & DE1L163Q);

DE1_TOE = DFFEAS(DE1_TOE_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--DE1_E is std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|E at LC_X39_Y27_N2

--operation mode is normal

DE1_E = DE1_TOE # DE1_ROE;

--RB1_counter_snapshot[22] is std_1c20:inst|sys_clk_timer:the_sys_clk_timer|counter_snapshot[22] at LC_X52_Y28_N7

--operation mode is normal

RB1_counter_snapshot[22]_lut_out = RB1_internal_counter[22];

RB1_counter_snapshot[22] = DFFEAS(RB1_counter_snapshot[22]_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , RB1L235, , , , );

--RB1L198 is std_1c20:inst|sys_clk_timer:the_sys_clk_timer|read_mux_out[6]~1269 at LC_X52_Y28_N1

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

RB1_counter_snapshot[6]_qfbk = RB1_counter_snapshot[6];

RB1L198 = S1L1726Q & (RB1_counter_snapshot[22] # !S1L1738Q) # !S1L1726Q & (RB1_counter_snapshot[6]_qfbk & S1L1738Q);

--RB1_counter_snapshot[6] is std_1c20:inst|sys_clk_timer:the_sys_clk_timer|counter_snapshot[6] at LC_X52_Y28_N1

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

RB1_counter_snapshot[6] = DFFEAS(RB1L198, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , RB1L235, RB1_internal_counter[6], , , VCC);

--RB1_period_l_register[6] is std_1c20:inst|sys_clk_timer:the_sys_clk_timer|period_l_register[6] at LC_X51_Y27_N1

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

RB1_period_l_register[6]_lut_out = GND;

RB1_period_l_register[6] = DFFEAS(RB1_period_l_register[6]_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , RB1_period_l_wr_strobe, S1_M_st_data[6], , , VCC);

--RB1L199 is std_1c20:inst|sys_clk_timer:the_sys_clk_timer|read_mux_out[6]~1270 at LC_X47_Y26_N8

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

RB1_period_h_register[6]_qfbk = RB1_period_h_register[6];

RB1L199 = RB1L198 & (RB1_period_h_register[6]_qfbk) # !RB1L198 & !RB1_period_l_register[6];

--RB1_period_h_register[6] is std_1c20:inst|sys_clk_timer:the_sys_clk_timer|period_h_register[6] at LC_X47_Y26_N8

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

RB1_period_h_register[6] = DFFEAS(RB1L199, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , RB1_period_h_wr_strobe, S1_M_st_data[6], , , VCC);

--Z1_counter_snapshot[6] is std_1c20:inst|high_res_timer:the_high_res_timer|counter_snapshot[6] at LC_X53_Y24_N3

--operation mode is normal

Z1_counter_snapshot[6]_lut_out = !Z1_internal_counter[6];

Z1_counter_snapshot[6] = DFFEAS(Z1_counter_snapshot[6]_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , Z1L232, , , , );

--Z1L195 is std_1c20:inst|high_res_timer:the_high_res_timer|read_mux_out[6]~1280 at LC_X53_Y24_N0

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

Z1_counter_snapshot[22]_qfbk = Z1_counter_snapshot[22];

Z1L195 = S1L1726Q & (Z1_counter_snapshot[22]_qfbk # !S1L1738Q) # !S1L1726Q & Z1_counter_snapshot[6] & (S1L1738Q);

--Z1_counter_snapshot[22] is std_1c20:inst|high_res_timer:the_high_res_timer|counter_snapshot[22] at LC_X53_Y24_N0

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

Z1_counter_snapshot[22] = DFFEAS(Z1L195, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , Z1L232, Z1_internal_counter[22], , , VCC);

--Z1_period_l_register[6] is std_1c20:inst|high_res_timer:the_high_res_timer|period_l_register[6] at LC_X55_Y27_N8

--operation mode is normal

Z1_period_l_register[6]_lut_out = !S1_M_st_data[6];

Z1_period_l_register[6] = DFFEAS(Z1_period_l_register[6]_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , Z1_period_l_wr_strobe, , , , );

--Z1L196 is std_1c20:inst|high_res_timer:the_high_res_timer|read_mux_out[6]~1281 at LC_X55_Y27_N6

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

Z1_period_h_register[6]_qfbk = Z1_period_h_register[6];

Z1L196 = Z1L195 & (Z1_period_h_register[6]_qfbk) # !Z1L195 & Z1_period_l_register[6];

--Z1_period_h_register[6] is std_1c20:inst|high_res_timer:the_high_res_timer|period_h_register[6] at LC_X55_Y27_N6

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

Z1_period_h_register[6] = DFFEAS(Z1L196, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , Z1_period_h_wr_strobe, S1_M_st_data[6], , , VCC);

--XE1_control_reg[6] is std_1c20:inst|uart1:the_uart1|uart1_regs:the_uart1_regs|control_reg[6] at LC_X48_Y23_N8

--operation mode is normal

XE1_control_reg[6]_lut_out = S1_M_st_data[6];

XE1_control_reg[6] = DFFEAS(XE1_control_reg[6]_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , XE1L14, , , , );

--XE1L60 is std_1c20:inst|uart1:the_uart1|uart1_regs:the_uart1_regs|selected_read_data[6]~686 at LC_X48_Y23_N3

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

XE1_internal_tx_data[6]_qfbk = XE1_internal_tx_data[6];

XE1L60 = S1_M_alu_result[3] & XE1_control_reg[6] # !S1_M_alu_result[3] & (XE1_internal_tx_data[6]_qfbk);

--XE1_internal_tx_data[6] is std_1c20:inst|uart1:the_uart1|uart1_regs:the_uart1_regs|internal_tx_data[6] at LC_X48_Y23_N3

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

XE1_internal_tx_data[6] = DFFEAS(XE1L60, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , XE1L64, S1_M_st_data[6], , , VCC);

--XE1L61 is std_1c20:inst|uart1:the_uart1|uart1_regs:the_uart1_regs|selected_read_data[6]~687 at LC_X51_Y22_N8

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

YE1_rx_data[6]_qfbk = YE1_rx_data[6];

XE1L61 = S1_M_alu_result[3] & !ZE1_internal_tx_ready # !S1_M_alu_result[3] & (YE1_rx_data[6]_qfbk);

--YE1_rx_data[6] is std_1c20:inst|uart1:the_uart1|uart1_rx:the_uart1_rx|rx_data[6] at LC_X51_Y22_N8

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

YE1_rx_data[6] = DFFEAS(XE1L61, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , YE1_got_new_char, YE1_unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[7], , , VCC);

--J1_slave_readdata[6] is std_1c20:inst|clock_0:the_clock_0|slave_readdata[6] at LC_X45_Y28_N3

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

J1_slave_readdata[6]_lut_out = GND;

J1_slave_readdata[6] = DFFEAS(J1_slave_readdata[6]_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , J1_slave_readdata_p1[6], , , VCC);

--T1L476 is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|p1_registered_cpu_data_master_readdata[6]~2080 at LC_X45_Y28_N1

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

M1_slave_readdata[6]_qfbk = M1_slave_readdata[6];

T1L476 = S1L1743Q & (M1_slave_readdata[6]_qfbk) # !S1L1743Q & J1_slave_readdata[6] # !K1L6;

--M1_slave_readdata[6] is std_1c20:inst|clock_1:the_clock_1|slave_readdata[6] at LC_X45_Y28_N1

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

M1_slave_readdata[6] = DFFEAS(T1L476, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , M1_slave_readdata_p1[6], , , VCC);

--T1L506 is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|p1_registered_cpu_data_master_readdata~55 at LC_X45_Y26_N0

--operation mode is normal

T1L506 = BB1_read_0 & SE2_q_b[6] # !CB1L2 # !UB1L9;

--DE1L10 is std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|A_WE_StdLogicVector~1130 at LC_X39_Y28_N0

--operation mode is normal

DE1L10 = X1L28 & !DE1L21 & X1L33 & DE1L228Q;

--DE1L11 is std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|A_WE_StdLogicVector~1131 at LC_X39_Y28_N5

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

DE1_rx_holding_reg[6]_qfbk = DE1_rx_holding_reg[6];

DE1L11 = DE1_rx_holding_reg[6]_qfbk & (DE1L21 # !X1L28 # !X1L33);

--DE1_rx_holding_reg[6] is std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|rx_holding_reg[6] at LC_X39_Y28_N5

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

DE1_rx_holding_reg[6] = DFFEAS(DE1L11, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , DE1L302, DE1_shift_reg[6], , , VCC);

--DE1L12 is std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|A_WE_StdLogicVector~1132 at LC_X39_Y28_N8

--operation mode is normal

DE1L12 = DE1L253 & DE1L117Q # !DE1L253 & (DE1L11 # DE1L10);

--DE1_tx_holding_primed is std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|tx_holding_primed at LC_X38_Y28_N6

--operation mode is normal

DE1_tx_holding_primed_lut_out = DE1L163Q # DE1_transmitting & (DE1_tx_holding_primed);

DE1_tx_holding_primed = DFFEAS(DE1_tx_holding_primed_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--DE1_transmitting is std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|transmitting at LC_X41_Y28_N7

--operation mode is normal

DE1_transmitting_lut_out = !DE1L338 & (!DE1L262 # !DE1_state[4] # !DE1_slowcount[0]);

DE1_transmitting = DFFEAS(DE1_transmitting_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--DE1L339 is std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|TRDY~0 at LC_X38_Y28_N8

--operation mode is normal

DE1L339 = !DE1_tx_holding_primed # !DE1_transmitting;

--DE1L83Q is std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|data_to_cpu[6]~46 at LC_X38_Y28_N8

--operation mode is normal

DE1L83Q = DFFEAS(DE1L339, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--XE1_control_reg[5] is std_1c20:inst|uart1:the_uart1|uart1_regs:the_uart1_regs|control_reg[5] at LC_X48_Y23_N0

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

XE1_control_reg[5]_lut_out = GND;

XE1_control_reg[5] = DFFEAS(XE1_control_reg[5]_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , XE1L14, S1_M_st_data[5], , , VCC);

--ZE1_tx_shift_empty is std_1c20:inst|uart1:the_uart1|uart1_tx:the_uart1_tx|tx_shift_empty at LC_X48_Y25_N2

--operation mode is normal

ZE1_tx_shift_empty_lut_out = ZE1_internal_tx_ready # ZE1_unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out[0] # !ZE1L37;

ZE1_tx_shift_empty = DFFEAS(ZE1_tx_shift_empty_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--XE1L34 is std_1c20:inst|uart1:the_uart1|uart1_regs:the_uart1_regs|qualified_irq~115 at LC_X48_Y23_N6

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

XE1_control_reg[4]_qfbk = XE1_control_reg[4];

XE1L34 = ZE1_tx_shift_empty & ZE1_tx_overrun & XE1_control_reg[4]_qfbk # !ZE1_tx_shift_empty & (XE1_control_reg[5] # ZE1_tx_overrun & XE1_control_reg[4]_qfbk);

--XE1_control_reg[4] is std_1c20:inst|uart1:the_uart1|uart1_regs:the_uart1_regs|control_reg[4] at LC_X48_Y23_N6

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

XE1_control_reg[4] = DFFEAS(XE1L34, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , XE1L14, S1_M_st_data[4], , , VCC);

--XE1L35 is std_1c20:inst|uart1:the_uart1|uart1_regs:the_uart1_regs|qualified_irq~116 at LC_X48_Y22_N0

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

XE1_control_reg[1]_qfbk = XE1_control_reg[1];

XE1L35 = XE1_control_reg[6] & (XE1_control_reg[1]_qfbk & YE1_framing_error # !ZE1_internal_tx_ready) # !XE1_control_reg[6] & (XE1_control_reg[1]_qfbk & YE1_framing_error);

--XE1_control_reg[1] is std_1c20:inst|uart1:the_uart1|uart1_regs:the_uart1_regs|control_reg[1] at LC_X48_Y22_N0

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

XE1_control_reg[1] = DFFEAS(XE1L35, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , XE1L14, S1_M_st_data[1], , , VCC);

--XE1L36 is std_1c20:inst|uart1:the_uart1|uart1_regs:the_uart1_regs|qualified_irq~117 at LC_X48_Y22_N5

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

XE1_control_reg[8]_qfbk = XE1_control_reg[8];

XE1L36 = XE1L35 # XE1L34 # XE1L1 & XE1_control_reg[8]_qfbk;

--XE1_control_reg[8] is std_1c20:inst|uart1:the_uart1|uart1_regs:the_uart1_regs|control_reg[8] at LC_X48_Y22_N5

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

XE1_control_reg[8] = DFFEAS(XE1L36, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , XE1L14, S1L2275Q, , , VCC);

--XE1L37 is std_1c20:inst|uart1:the_uart1|uart1_regs:the_uart1_regs|qualified_irq~118 at LC_X48_Y22_N8

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

XE1_control_reg[3]_qfbk = XE1_control_reg[3];

XE1L37 = YE1_rx_overrun & (XE1_control_reg[3]_qfbk # XE1_control_reg[2] & YE1_break_detect) # !YE1_rx_overrun & XE1_control_reg[2] & (YE1_break_detect);

--XE1_control_reg[3] is std_1c20:inst|uart1:the_uart1|uart1_regs:the_uart1_regs|control_reg[3] at LC_X48_Y22_N8

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

XE1_control_reg[3] = DFFEAS(XE1L37, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , XE1L14, S1_M_st_data[3], , , VCC);

--Z1_counter_snapshot[20] is std_1c20:inst|high_res_timer:the_high_res_timer|counter_snapshot[20] at LC_X54_Y24_N9

--operation mode is normal

Z1_counter_snapshot[20]_lut_out = Z1_internal_counter[20];

Z1_counter_snapshot[20] = DFFEAS(Z1_counter_snapshot[20]_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , Z1L232, , , , );

--Z1L191 is std_1c20:inst|high_res_timer:the_high_res_timer|read_mux_out[4]~1283 at LC_X54_Y24_N5

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

Z1_counter_snapshot[4]_qfbk = Z1_counter_snapshot[4];

Z1L191 = S1L1738Q & (S1L1726Q & Z1_counter_snapshot[20] # !S1L1726Q & (Z1_counter_snapshot[4]_qfbk)) # !S1L1738Q & (S1L1726Q);

--Z1_counter_snapshot[4] is std_1c20:inst|high_res_timer:the_high_res_timer|counter_snapshot[4] at LC_X54_Y24_N5

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

Z1_counter_snapshot[4] = DFFEAS(Z1L191, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , Z1L232, Z1_internal_counter[4], , , VCC);

--Z1_period_l_register[4] is std_1c20:inst|high_res_timer:the_high_res_timer|period_l_register[4] at LC_X54_Y26_N7

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

Z1_period_l_register[4]_lut_out = GND;

Z1_period_l_register[4] = DFFEAS(Z1_period_l_register[4]_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , Z1_period_l_wr_strobe, S1_M_st_data[4], , , VCC);

--Z1L192 is std_1c20:inst|high_res_timer:the_high_res_timer|read_mux_out[4]~1284 at LC_X54_Y26_N9

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

Z1_period_h_register[4]_qfbk = Z1_period_h_register[4];

Z1L192 = Z1L191 & (Z1_period_h_register[4]_qfbk) # !Z1L191 & !Z1_period_l_register[4];

--Z1_period_h_register[4] is std_1c20:inst|high_res_timer:the_high_res_timer|period_h_register[4] at LC_X54_Y26_N9

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

Z1_period_h_register[4] = DFFEAS(Z1L192, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , Z1_period_h_wr_strobe, S1_M_st_data[4], , , VCC);

--XE1L56 is std_1c20:inst|uart1:the_uart1|uart1_regs:the_uart1_regs|selected_read_data[4]~689 at LC_X48_Y23_N2

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

XE1_internal_tx_data[4]_qfbk = XE1_internal_tx_data[4];

XE1L56 = S1_M_alu_result[3] & XE1_control_reg[4] # !S1_M_alu_result[3] & (XE1_internal_tx_data[4]_qfbk);

--XE1_internal_tx_data[4] is std_1c20:inst|uart1:the_uart1|uart1_regs:the_uart1_regs|internal_tx_data[4] at LC_X48_Y23_N2

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

XE1_internal_tx_data[4] = DFFEAS(XE1L56, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , XE1L64, S1_M_st_data[4], , , VCC);

--XE1L57 is std_1c20:inst|uart1:the_uart1|uart1_regs:the_uart1_regs|selected_read_data[4]~690 at LC_X51_Y22_N3

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

YE1_rx_data[4]_qfbk = YE1_rx_data[4];

XE1L57 = S1_M_alu_result[3] & ZE1_tx_overrun # !S1_M_alu_result[3] & (YE1_rx_data[4]_qfbk);

--YE1_rx_data[4] is std_1c20:inst|uart1:the_uart1|uart1_rx:the_uart1_rx|rx_data[4] at LC_X51_Y22_N3

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

YE1_rx_data[4] = DFFEAS(XE1L57, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , YE1_got_new_char, YE1_unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[5], , , VCC);

--RB1_counter_snapshot[4] is std_1c20:inst|sys_clk_timer:the_sys_clk_timer|counter_snapshot[4] at LC_X52_Y28_N2

--operation mode is normal

RB1_counter_snapshot[4]_lut_out = !RB1_internal_counter[4];

RB1_counter_snapshot[4] = DFFEAS(RB1_counter_snapshot[4]_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , RB1L235, , , , );

--RB1L194 is std_1c20:inst|sys_clk_timer:the_sys_clk_timer|read_mux_out[4]~1272 at LC_X52_Y28_N3

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

RB1_counter_snapshot[20]_qfbk = RB1_counter_snapshot[20];

RB1L194 = S1L1726Q & (RB1_counter_snapshot[20]_qfbk # !S1L1738Q) # !S1L1726Q & RB1_counter_snapshot[4] & (S1L1738Q);

--RB1_counter_snapshot[20] is std_1c20:inst|sys_clk_timer:the_sys_clk_timer|counter_snapshot[20] at LC_X52_Y28_N3

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

RB1_counter_snapshot[20] = DFFEAS(RB1L194, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , RB1L235, RB1_internal_counter[20], , , VCC);

--RB1_period_l_register[4] is std_1c20:inst|sys_clk_timer:the_sys_clk_timer|period_l_register[4] at LC_X51_Y27_N9

--operation mode is normal

RB1_period_l_register[4]_lut_out = !S1_M_st_data[4];

RB1_period_l_register[4] = DFFEAS(RB1_period_l_register[4]_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , RB1_period_l_wr_strobe, , , , );

--RB1L195 is std_1c20:inst|sys_clk_timer:the_sys_clk_timer|read_mux_out[4]~1273 at LC_X51_Y25_N8

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

RB1_period_h_register[4]_qfbk = RB1_period_h_register[4];

RB1L195 = RB1L194 & (RB1_period_h_register[4]_qfbk) # !RB1L194 & RB1_period_l_register[4];

--RB1_period_h_register[4] is std_1c20:inst|sys_clk_timer:the_sys_clk_timer|period_h_register[4] at LC_X51_Y25_N8

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

RB1_period_h_register[4] = DFFEAS(RB1L195, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , RB1_period_h_wr_strobe, S1_M_st_data[4], , , VCC);

--J1_slave_readdata[4] is std_1c20:inst|clock_0:the_clock_0|slave_readdata[4] at LC_X46_Y28_N2

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

J1_slave_readdata[4]_lut_out = GND;

J1_slave_readdata[4] = DFFEAS(J1_slave_readdata[4]_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , J1_slave_readdata_p1[4], , , VCC);

--T1L474 is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|p1_registered_cpu_data_master_readdata[4]~2082 at LC_X46_Y28_N3

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

M1_slave_readdata[4]_qfbk = M1_slave_readdata[4];

T1L474 = S1L1743Q & (M1_slave_readdata[4]_qfbk) # !S1L1743Q & J1_slave_readdata[4] # !K1L6;

--M1_slave_readdata[4] is std_1c20:inst|clock_1:the_clock_1|slave_readdata[4] at LC_X46_Y28_N3

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

M1_slave_readdata[4] = DFFEAS(T1L474, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , M1_slave_readdata_p1[4], , , VCC);

--T1L504 is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|p1_registered_cpu_data_master_readdata~53 at LC_X46_Y22_N6

--operation mode is normal

T1L504 = BB1_read_0 & SE2_q_b[4] # !UB1L9 # !CB1L2;

--DE1_iTOE_reg is std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|iTOE_reg at LC_X39_Y27_N8

--operation mode is normal

DE1_iTOE_reg_lut_out = S1_M_st_data[4];

DE1_iTOE_reg = DFFEAS(DE1_iTOE_reg_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , DE1_control_wr_strobe, , , , );

--DE1L13 is std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|A_WE_StdLogicVector~1133 at LC_X37_Y28_N0

--operation mode is normal

DE1L13 = DE1L224Q & !DE1L21 & X1L33 & X1L28;

--DE1L14 is std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|A_WE_StdLogicVector~1134 at LC_X37_Y28_N8

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

DE1_rx_holding_reg[4]_qfbk = DE1_rx_holding_reg[4];

DE1L14 = DE1_rx_holding_reg[4]_qfbk & (DE1L21 # !X1L28 # !X1L33);

--DE1_rx_holding_reg[4] is std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|rx_holding_reg[4] at LC_X37_Y28_N8

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

DE1_rx_holding_reg[4] = DFFEAS(DE1L14, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , DE1L302, DE1_shift_reg[4], , , VCC);

--DE1L15 is std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|A_WE_StdLogicVector~1135 at LC_X37_Y28_N1

--operation mode is normal

DE1L15 = DE1L253 & DE1L113Q # !DE1L253 & (DE1L14 # DE1L13);

--DE1L267 is std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|irq_reg~134 at LC_X38_Y27_N5

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

DE1_iEOP_reg_qfbk = DE1_iEOP_reg;

DE1L267 = DE1_iRRDY_reg & (DE1_RRDY # DE1_iEOP_reg_qfbk & DE1L157) # !DE1_iRRDY_reg & (DE1_iEOP_reg_qfbk & DE1L157);

--DE1_iEOP_reg is std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|iEOP_reg at LC_X38_Y27_N5

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

DE1_iEOP_reg = DFFEAS(DE1L267, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , DE1_control_wr_strobe, S1L2281Q, , , VCC);

--DE1L268 is std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|irq_reg~135 at LC_X38_Y27_N9

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

DE1_iTRDY_reg_qfbk = DE1_iTRDY_reg;

DE1L268 = DE1L267 # DE1_iTRDY_reg_qfbk & (!DE1_tx_holding_primed # !DE1_transmitting);

--DE1_iTRDY_reg is std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|iTRDY_reg at LC_X38_Y27_N9

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

DE1_iTRDY_reg = DFFEAS(DE1L268, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , DE1_control_wr_strobe, S1_M_st_data[6], , , VCC);

--DE1L269 is std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|irq_reg~136 at LC_X38_Y27_N8

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

DE1_iE_reg_qfbk = DE1_iE_reg;

DE1L269 = DE1_iE_reg_qfbk & (DE1_ROE # DE1_TOE) # !DE1_iE_reg_qfbk & DE1_iTOE_reg & (DE1_TOE);

--DE1_iE_reg is std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|iE_reg at LC_X38_Y27_N8

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

DE1_iE_reg = DFFEAS(DE1L269, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , DE1_control_wr_strobe, S1L2275Q, , , VCC);

--Z1_counter_snapshot[21] is std_1c20:inst|high_res_timer:the_high_res_timer|counter_snapshot[21] at LC_X53_Y24_N6

--operation mode is normal

Z1_counter_snapshot[21]_lut_out = Z1_internal_counter[21];

Z1_counter_snapshot[21] = DFFEAS(Z1_counter_snapshot[21]_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , Z1L232, , , , );

--Z1L193 is std_1c20:inst|high_res_timer:the_high_res_timer|read_mux_out[5]~1286 at LC_X53_Y24_N1

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

Z1_counter_snapshot[5]_qfbk = Z1_counter_snapshot[5];

Z1L193 = S1L1738Q & (S1L1726Q & Z1_counter_snapshot[21] # !S1L1726Q & (Z1_counter_snapshot[5]_qfbk)) # !S1L1738Q & (S1L1726Q);

--Z1_counter_snapshot[5] is std_1c20:inst|high_res_timer:the_high_res_timer|counter_snapshot[5] at LC_X53_Y24_N1

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

Z1_counter_snapshot[5] = DFFEAS(Z1L193, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , Z1L232, Z1_internal_counter[5], , , VCC);

--Z1_period_l_register[5] is std_1c20:inst|high_res_timer:the_high_res_timer|period_l_register[5] at LC_X56_Y26_N0

--operation mode is normal

Z1_period_l_register[5]_lut_out = S1_M_st_data[5];

Z1_period_l_register[5] = DFFEAS(Z1_period_l_register[5]_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , Z1_period_l_wr_strobe, , , , );

--Z1L194 is std_1c20:inst|high_res_timer:the_high_res_timer|read_mux_out[5]~1287 at LC_X51_Y23_N6

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

Z1_period_h_register[5]_qfbk = Z1_period_h_register[5];

Z1L194 = Z1L193 & (Z1_period_h_register[5]_qfbk) # !Z1L193 & !Z1_period_l_register[5];

--Z1_period_h_register[5] is std_1c20:inst|high_res_timer:the_high_res_timer|period_h_register[5] at LC_X51_Y23_N6

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

Z1_period_h_register[5] = DFFEAS(Z1L194, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , Z1_period_h_wr_strobe, S1_M_st_data[5], , , VCC);

--XE1L58 is std_1c20:inst|uart1:the_uart1|uart1_regs:the_uart1_regs|selected_read_data[5]~692 at LC_X48_Y23_N4

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

XE1_internal_tx_data[5]_qfbk = XE1_internal_tx_data[5];

XE1L58 = S1_M_alu_result[3] & XE1_control_reg[5] # !S1_M_alu_result[3] & (XE1_internal_tx_data[5]_qfbk);

--XE1_internal_tx_data[5] is std_1c20:inst|uart1:the_uart1|uart1_regs:the_uart1_regs|internal_tx_data[5] at LC_X48_Y23_N4

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

XE1_internal_tx_data[5] = DFFEAS(XE1L58, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , XE1L64, S1_M_st_data[5], , , VCC);

--XE1L59 is std_1c20:inst|uart1:the_uart1|uart1_regs:the_uart1_regs|selected_read_data[5]~693 at LC_X51_Y22_N5

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

YE1_rx_data[5]_qfbk = YE1_rx_data[5];

XE1L59 = S1_M_alu_result[3] & !ZE1_tx_shift_empty # !S1_M_alu_result[3] & (YE1_rx_data[5]_qfbk);

--YE1_rx_data[5] is std_1c20:inst|uart1:the_uart1|uart1_rx:the_uart1_rx|rx_data[5] at LC_X51_Y22_N5

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

YE1_rx_data[5] = DFFEAS(XE1L59, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , YE1_got_new_char, YE1_unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[6], , , VCC);

--J1_slave_readdata[5] is std_1c20:inst|clock_0:the_clock_0|slave_readdata[5] at LC_X46_Y28_N1

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

J1_slave_readdata[5]_lut_out = GND;

J1_slave_readdata[5] = DFFEAS(J1_slave_readdata[5]_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , J1_slave_readdata_p1[5], , , VCC);

--T1L475 is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|p1_registered_cpu_data_master_readdata[5]~2084 at LC_X46_Y28_N6

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

M1_slave_readdata[5]_qfbk = M1_slave_readdata[5];

T1L475 = S1L1743Q & (M1_slave_readdata[5]_qfbk) # !S1L1743Q & J1_slave_readdata[5] # !K1L6;

--M1_slave_readdata[5] is std_1c20:inst|clock_1:the_clock_1|slave_readdata[5] at LC_X46_Y28_N6

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

M1_slave_readdata[5] = DFFEAS(T1L475, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , M1_slave_readdata_p1[5], , , VCC);

--T1L505 is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|p1_registered_cpu_data_master_readdata~54 at LC_X45_Y25_N4

--operation mode is normal

T1L505 = BB1_read_0 & SE2_q_b[5] # !UB1L9 # !CB1L2;

--RB1_counter_snapshot[21] is std_1c20:inst|sys_clk_timer:the_sys_clk_timer|counter_snapshot[21] at LC_X52_Y28_N5

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

RB1_counter_snapshot[21]_lut_out = GND;

RB1_counter_snapshot[21] = DFFEAS(RB1_counter_snapshot[21]_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , RB1L235, RB1_internal_counter[21], , , VCC);

--RB1L196 is std_1c20:inst|sys_clk_timer:the_sys_clk_timer|read_mux_out[5]~1275 at LC_X52_Y28_N8

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

RB1_counter_snapshot[5]_qfbk = RB1_counter_snapshot[5];

RB1L196 = S1L1726Q & (RB1_counter_snapshot[21] # !S1L1738Q) # !S1L1726Q & (RB1_counter_snapshot[5]_qfbk & S1L1738Q);

--RB1_counter_snapshot[5] is std_1c20:inst|sys_clk_timer:the_sys_clk_timer|counter_snapshot[5] at LC_X52_Y28_N8

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

RB1_counter_snapshot[5] = DFFEAS(RB1L196, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , RB1L235, RB1_internal_counter[5], , , VCC);

--RB1_period_l_register[5] is std_1c20:inst|sys_clk_timer:the_sys_clk_timer|period_l_register[5] at LC_X51_Y26_N5

--operation mode is normal

RB1_period_l_register[5]_lut_out = S1_M_st_data[5];

RB1_period_l_register[5] = DFFEAS(RB1_period_l_register[5]_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , RB1_period_l_wr_strobe, , , , );

--RB1L197 is std_1c20:inst|sys_clk_timer:the_sys_clk_timer|read_mux_out[5]~1276 at LC_X51_Y26_N1

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

RB1_period_h_register[5]_qfbk = RB1_period_h_register[5];

RB1L197 = RB1L196 & (RB1_period_h_register[5]_qfbk) # !RB1L196 & !RB1_period_l_register[5];

--RB1_period_h_register[5] is std_1c20:inst|sys_clk_timer:the_sys_clk_timer|period_h_register[5] at LC_X51_Y26_N1

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

RB1_period_h_register[5] = DFFEAS(RB1L197, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , RB1_period_h_wr_strobe, S1_M_st_data[5], , , VCC);

--DE1L338 is std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|transmitting~81 at LC_X40_Y28_N9

--operation mode is normal

DE1L338 = !DE1_transmitting & !DE1_tx_holding_primed;

--DE1L71Q is std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|data_to_cpu[5]~35 at LC_X40_Y28_N9

--operation mode is normal

DE1L71Q = DFFEAS(DE1L338, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--S1_M_shift_rot_result[30] is std_1c20:inst|cpu:the_cpu|M_shift_rot_result[30] at LC_X40_Y12_N6

--operation mode is normal

S1_M_shift_rot_result[30] = AMPP_FUNCTION(QC2__clk0, S1_M_ctrl_shift_rot_right, S1_M_shift_rot_result[29], S1L883, S1_M_shift_rot_result[31], F1_data_out, !S1_M_shift_rot_stall);

--S1_E_ctrl_rot_right is std_1c20:inst|cpu:the_cpu|E_ctrl_rot_right at LC_X38_Y14_N3

--operation mode is normal

S1_E_ctrl_rot_right = AMPP_FUNCTION(QC2__clk0, S1_D_iw[15], S1_D_iw[14], S1L307, F1_data_out, S1_W_stall);

--S1_E_ctrl_shift_logical is std_1c20:inst|cpu:the_cpu|E_ctrl_shift_logical at LC_X38_Y14_N9

--operation mode is normal

S1_E_ctrl_shift_logical = AMPP_FUNCTION(QC2__clk0, S1_D_iw[15], S1L307, S1_D_iw[16], F1_data_out, S1_W_stall);

--Z1_readdata[0] is std_1c20:inst|high_res_timer:the_high_res_timer|readdata[0] at LC_X52_Y24_N7

--operation mode is normal

Z1_readdata[0]_lut_out = Z1L181 # Z1L183 # Z1L182;

Z1_readdata[0] = DFFEAS(Z1_readdata[0]_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--RB1_readdata[0] is std_1c20:inst|sys_clk_timer:the_sys_clk_timer|readdata[0] at LC_X53_Y25_N9

--operation mode is normal

RB1_readdata[0]_lut_out = RB1L186 # RB1L184 # RB1L185;

RB1_readdata[0] = DFFEAS(RB1_readdata[0]_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--G1_readdata[0] is std_1c20:inst|button_pio:the_button_pio|readdata[0] at LC_X45_Y22_N5

--operation mode is normal

G1_readdata[0]_lut_out = S1_M_alu_result[3] & G1L29 # !S1_M_alu_result[3] & (!S1L1726Q & in_port_to_the_button_pio[0]);

G1_readdata[0] = DFFEAS(G1_readdata[0]_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--XE1_readdata[0] is std_1c20:inst|uart1:the_uart1|uart1_regs:the_uart1_regs|readdata[0] at LC_X45_Y22_N6

--operation mode is normal

XE1_readdata[0]_lut_out = XE1_control_reg[0] & (XE1L15 # !S1L1738Q & XE1L49) # !XE1_control_reg[0] & (!S1L1738Q & XE1L49);

XE1_readdata[0] = DFFEAS(XE1_readdata[0]_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--HB1_readdata is std_1c20:inst|reconfig_request_pio:the_reconfig_request_pio|readdata at LC_X47_Y22_N2

--operation mode is normal

HB1_readdata_lut_out = !S1_M_alu_result[3] & (S1L1726Q & (HB1_data_dir) # !S1L1726Q & A1L20);

HB1_readdata = DFFEAS(HB1_readdata_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--T1_registered_cpu_data_master_readdata[0] is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|registered_cpu_data_master_readdata[0] at LC_X41_Y23_N9

--operation mode is normal

T1_registered_cpu_data_master_readdata[0]_lut_out = T1L470 & T1L500 & (KB1_za_data[0] # !S1L1693Q);

T1_registered_cpu_data_master_readdata[0] = DFFEAS(T1_registered_cpu_data_master_readdata[0]_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--T1L35 is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[0]~5323 at LC_X40_Y25_N8

--operation mode is normal

T1L35 = !Y1_internal_incoming_ext_ram_bus_data[0] & (Y1L146 # Y1_cpu_data_master_requests_ext_ram_s1);

--DE1L45 is std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|data_to_cpu[0]~37 at LC_X37_Y28_N6

--operation mode is normal

DE1L45 = !DE1L72Q & (DE1L46Q & (DE1L48Q) # !DE1L46Q & DE1L51);

--U1L162 is std_1c20:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_readdata~2415 at LC_X38_Y24_N7

--operation mode is normal

U1L162 = W1L1 & (DE1L45) # !W1L1 & FE1_q_a[0];

--WC1L1 is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|readdata[0]~1369 at LC_X46_Y19_N8

--operation mode is normal

WC1L1 = AMPP_FUNCTION(S1L1362Q, S1L1367Q, S1L1363Q, S1L1369Q);

--Z1_readdata[1] is std_1c20:inst|high_res_timer:the_high_res_timer|readdata[1] at LC_X53_Y26_N9

--operation mode is normal

Z1_readdata[1]_lut_out = Z1L184 # Z1L186 # Z1L185;

Z1_readdata[1] = DFFEAS(Z1_readdata[1]_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--G1_readdata[1] is std_1c20:inst|button_pio:the_button_pio|readdata[1] at LC_X44_Y20_N5

--operation mode is normal

G1_readdata[1]_lut_out = S1_M_alu_result[3] & (G1L30) # !S1_M_alu_result[3] & in_port_to_the_button_pio[1] & (!S1L1726Q);

G1_readdata[1] = DFFEAS(G1_readdata[1]_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--XE1_readdata[1] is std_1c20:inst|uart1:the_uart1|uart1_regs:the_uart1_regs|readdata[1] at LC_X47_Y22_N7

--operation mode is normal

XE1_readdata[1]_lut_out = !S1L1738Q & (S1L1726Q & (XE1L50) # !S1L1726Q & XE1L51);

XE1_readdata[1] = DFFEAS(XE1_readdata[1]_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--RB1_readdata[1] is std_1c20:inst|sys_clk_timer:the_sys_clk_timer|readdata[1] at LC_X53_Y26_N1

--operation mode is normal

RB1_readdata[1]_lut_out = RB1L187 # RB1L189 # RB1L188;

RB1_readdata[1] = DFFEAS(RB1_readdata[1]_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--T1L41 is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[1]~5329 at LC_X44_Y24_N3

--operation mode is normal

T1L41 = S1_M_alu_result[6] & (XE1_readdata[1]) # !S1_M_alu_result[6] & RB1_readdata[1] # !SB1L3;

--T1_registered_cpu_data_master_readdata[1] is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|registered_cpu_data_master_readdata[1] at LC_X45_Y24_N3

--operation mode is normal

T1_registered_cpu_data_master_readdata[1]_lut_out = T1L471 & T1L501 & (KB1_za_data[1] # !S1L1693Q);

T1_registered_cpu_data_master_readdata[1] = DFFEAS(T1_registered_cpu_data_master_readdata[1]_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--T1L42 is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[1]~5330 at LC_X45_Y24_N9

--operation mode is normal

T1L42 = T1_registered_cpu_data_master_readdata[1] # !K1_cpu_data_master_requests_clock_0_in & (!UB1L9 # !CB1L2);

--T1L43 is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[1]~5331 at LC_X40_Y25_N4

--operation mode is normal

T1L43 = !T1L49 & (S1L1726Q # !UB1L9 # !UB1L10);

--T1L45 is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[1]~5333 at LC_X45_Y24_N8

--operation mode is normal

T1L45 = !T1L47 & (T1_registered_cpu_data_master_readdata[1] # !S1L1693Q & !N1_cpu_data_master_requests_clock_1_in);

--DE1_data_to_cpu[1] is std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|data_to_cpu[1] at LC_X38_Y29_N4

--operation mode is normal

DE1_data_to_cpu[1]_lut_out = !DE1L278 & (DE1L253 & DE1L106Q # !DE1L253 & (DE1L276));

DE1_data_to_cpu[1] = DFFEAS(DE1_data_to_cpu[1]_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--U1L163 is std_1c20:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_readdata~2416 at LC_X43_Y24_N2

--operation mode is normal

U1L163 = W1L1 & DE1_data_to_cpu[1] # !W1L1 & (FE1_q_a[1]);

--WC1L2 is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|readdata[1]~1371 at LC_X46_Y19_N1

--operation mode is normal

WC1L2 = AMPP_FUNCTION(S1L1370Q, S1L1367Q, S1L1371Q, S1L1369Q);

--S1L2042Q is std_1c20:inst|cpu:the_cpu|M_bstatus_reg~12 at LC_X31_Y16_N2

--operation mode is normal

S1L2042Q = AMPP_FUNCTION(QC2__clk0, S1_E_ctrl_wrctl_inst, S1_E_iw[8], S1_E_iw[6], S1_E_iw[7], F1_data_out);

--S1L2076Q is std_1c20:inst|cpu:the_cpu|M_estatus_reg~10 at LC_X31_Y16_N9

--operation mode is normal

S1L2076Q = AMPP_FUNCTION(QC2__clk0, S1_E_ctrl_wrctl_inst, S1_E_iw[8], S1_E_iw[6], S1_E_iw[7], F1_data_out);

--FF1_state[11] is sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state[11] at LC_X57_Y15_N7

--operation mode is normal

FF1_state[11] = AMPP_FUNCTION(A1L5, FF1_state[11], FF1_state[10], FF1_state[14], VCC, A1L7);

--FF1_state[9] is sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state[9] at LC_X57_Y15_N3

--operation mode is normal

FF1_state[9] = AMPP_FUNCTION(A1L5, A1L7, FF1_state[2], VCC);

--FF1_tms_cnt[2] is sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|tms_cnt[2] at LC_X58_Y15_N3

--operation mode is normal

FF1_tms_cnt[2] = AMPP_FUNCTION(A1L5, FF1_tms_cnt[0], FF1_tms_cnt[1], FF1_tms_cnt[2], VCC, !A1L7);

--FF1_tms_cnt[1] is sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|tms_cnt[1] at LC_X58_Y15_N7

--operation mode is normal

FF1_tms_cnt[1] = AMPP_FUNCTION(A1L5, FF1_tms_cnt[0], FF1_tms_cnt[1], VCC, !A1L7);

--FF1_tms_cnt[0] is sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|tms_cnt[0] at LC_X58_Y15_N0

--operation mode is normal

FF1_tms_cnt[0] = AMPP_FUNCTION(A1L5, A1L7, FF1_tms_cnt[0], VCC);

--FF1L19 is sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state~233 at LC_X58_Y15_N4

--operation mode is normal

FF1L19 = AMPP_FUNCTION(FF1_tms_cnt[0], FF1_tms_cnt[1], FF1_tms_cnt[2]);

--FF1_state[10] is sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state[10] at LC_X57_Y15_N4

--operation mode is normal

FF1_state[10] = AMPP_FUNCTION(A1L5, A1L7, FF1_state[9], VCC);

--FF1_state[6] is sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state[6] at LC_X58_Y17_N6

--operation mode is normal

FF1_state[6] = AMPP_FUNCTION(A1L5, FF1_state[6], FF1_state[5], VCC, A1L7);

--CF1_WORD_SR[2] is sld_hub:sld_hub_inst|sld_rom_sr:HUB_INFO_REG|WORD_SR[2] at LC_X59_Y18_N1

--operation mode is normal

CF1_WORD_SR[2] = AMPP_FUNCTION(A1L5, CF1_word_counter[2], CF1L17, CF1_WORD_SR[3], CF1L16, VCC, CF1_clear_signal, FF1_state[4], CF1L25);

--CF1L19 is sld_hub:sld_hub_inst|sld_rom_sr:HUB_INFO_REG|Mux2~28 at LC_X59_Y18_N2

--operation mode is normal

CF1L19 = AMPP_FUNCTION(CF1_word_counter[2], CF1_word_counter[1], CF1_word_counter[3], CF1_word_counter[0]);

--CF1L1 is sld_hub:sld_hub_inst|sld_rom_sr:HUB_INFO_REG|Add0~72 at LC_X58_Y18_N4

--operation mode is normal

CF1L1 = AMPP_FUNCTION(CF1_word_counter[4], CF1L12, CF1L13);

--CF1L15 is sld_hub:sld_hub_inst|sld_rom_sr:HUB_INFO_REG|Equal0~43 at LC_X59_Y18_N9

--operation mode is normal

CF1L15 = AMPP_FUNCTION(CF1_word_counter[2], CF1_word_counter[1], CF1_word_counter[4], CF1_word_counter[0]);

--CF1L24 is sld_hub:sld_hub_inst|sld_rom_sr:HUB_INFO_REG|word_counter[0]~1278 at LC_X58_Y17_N1

--operation mode is normal

CF1L24 = AMPP_FUNCTION(C1_jtag_debug_mode_usr0, FF1_state[4], FF1_state[3], CF1_clear_signal);

--CF1L3 is sld_hub:sld_hub_inst|sld_rom_sr:HUB_INFO_REG|Add0~75 at LC_X58_Y18_N0

--operation mode is arithmetic

CF1L3 = AMPP_FUNCTION(CF1_word_counter[0]);

--CF1L4 is sld_hub:sld_hub_inst|sld_rom_sr:HUB_INFO_REG|Add0~75COUT1_278 at LC_X58_Y18_N0

--operation mode is arithmetic

CF1L4 = AMPP_FUNCTION(CF1_word_counter[0]);

--CF1L5 is sld_hub:sld_hub_inst|sld_rom_sr:HUB_INFO_REG|Add0~76 at LC_X58_Y18_N1

--operation mode is arithmetic

CF1L5 = AMPP_FUNCTION(CF1_word_counter[1], CF1L3, CF1L4);

--CF1L6 is sld_hub:sld_hub_inst|sld_rom_sr:HUB_INFO_REG|Add0~77 at LC_X58_Y18_N1

--operation mode is arithmetic

CF1L6 = AMPP_FUNCTION(CF1_word_counter[1], CF1L3);

--CF1L7 is sld_hub:sld_hub_inst|sld_rom_sr:HUB_INFO_REG|Add0~77COUT1_280 at LC_X58_Y18_N1

--operation mode is arithmetic

CF1L7 = AMPP_FUNCTION(CF1_word_counter[1], CF1L4);

--CF1L8 is sld_hub:sld_hub_inst|sld_rom_sr:HUB_INFO_REG|Add0~78 at LC_X58_Y18_N2

--operation mode is arithmetic

CF1L8 = AMPP_FUNCTION(CF1_word_counter[2], CF1L6, CF1L7);

--CF1L9 is sld_hub:sld_hub_inst|sld_rom_sr:HUB_INFO_REG|Add0~79 at LC_X58_Y18_N2

--operation mode is arithmetic

CF1L9 = AMPP_FUNCTION(CF1_word_counter[2], CF1L6);

--CF1L10 is sld_hub:sld_hub_inst|sld_rom_sr:HUB_INFO_REG|Add0~79COUT1_282 at LC_X58_Y18_N2

--operation mode is arithmetic

CF1L10 = AMPP_FUNCTION(CF1_word_counter[2], CF1L7);

--CF1L11 is sld_hub:sld_hub_inst|sld_rom_sr:HUB_INFO_REG|Add0~80 at LC_X58_Y18_N3

--operation mode is arithmetic

CF1L11 = AMPP_FUNCTION(CF1_word_counter[3], CF1L9, CF1L10);

--CF1L12 is sld_hub:sld_hub_inst|sld_rom_sr:HUB_INFO_REG|Add0~81 at LC_X58_Y18_N3

--operation mode is arithmetic

CF1L12 = AMPP_FUNCTION(CF1_word_counter[3], CF1L9);

--CF1L13 is sld_hub:sld_hub_inst|sld_rom_sr:HUB_INFO_REG|Add0~81COUT1_284 at LC_X58_Y18_N3

--operation mode is arithmetic

CF1L13 = AMPP_FUNCTION(CF1_word_counter[3], CF1L10);

--SD1L120Q is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|ir_out[1]~reg0 at LC_X44_Y18_N8

--operation mode is normal

SD1L120Q = AMPP_FUNCTION(A1L5, S1_hbreak_enabled, !C1_CLR_SIGNAL);

--GD1_break_readreg[0] is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_break:the_cpu_nios2_oci_break|break_readreg[0] at LC_X52_Y17_N8

--operation mode is normal

GD1_break_readreg[0] = AMPP_FUNCTION(QC2__clk0, SD1_internal_jdo1[36], SD1_internal_jdo1[37], SD1_internal_jdo1[0], SD1L188, !C1_CLR_SIGNAL, SD1L188);

--SD1L130 is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|Mux39~14 at LC_X52_Y17_N9

--operation mode is normal

SD1L130 = AMPP_FUNCTION(SD1_ir[0], SD1_ir[1], GD1_break_readreg[0], RD1_internal_MonDReg[0]);

--SD1_sr[2] is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|sr[2] at LC_X52_Y16_N9

--operation mode is normal

SD1_sr[2] = AMPP_FUNCTION(A1L5, SD1L143, SD1L141, SD1_sr[3], SD1L129, !C1_CLR_SIGNAL, SD1L6);

--SD1_DRsize[1] is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|DRsize[1] at LC_X52_Y15_N1

--operation mode is normal

SD1_DRsize[1] = AMPP_FUNCTION(A1L5, BF5_Q[0], BF5_Q[1], !C1_CLR_SIGNAL, SD1_st_updateir);

--SD1_internal_jdo1[25] is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|internal_jdo1[25] at LC_X46_Y17_N9

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

SD1_internal_jdo1[25] = AMPP_FUNCTION(A1L8, SD1_sr[25], VCC, GND, SD1L144);

--SD1_st_shiftdr is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|st_shiftdr at LC_X53_Y14_N2

--operation mode is normal

SD1_st_shiftdr = AMPP_FUNCTION(A1L5, SD1L143, !A1L8);

--GE1_rvalid0 is std_1c20:inst|jtag_uart:the_jtag_uart|alt_jtag_atlantic:jtag_uart_alt_jtag_atlantic|rvalid0 at LC_X52_Y20_N5

--operation mode is normal

GE1_rvalid0 = AMPP_FUNCTION(QC2__clk0, GE1_read_req, GE1_user_saw_rvalid, GE1L19, GE1L2, F1_data_out);

--GE1L53 is std_1c20:inst|jtag_uart:the_jtag_uart|alt_jtag_atlantic:jtag_uart_alt_jtag_atlantic|td_shift[9]~3552 at LC_X55_Y19_N9

--operation mode is normal

GE1L53 = AMPP_FUNCTION(BF4_Q[0], FF1_state[3], FF1_state[4]);

--GE1_write_stalled is std_1c20:inst|jtag_uart:the_jtag_uart|alt_jtag_atlantic:jtag_uart_alt_jtag_atlantic|write_stalled at LC_X52_Y19_N3

--operation mode is normal

GE1_write_stalled = AMPP_FUNCTION(A1L5, GE1_td_shift[10], altera_internal_jtag, GE1_write_stalled, BB1_t_dav, !C1_CLR_SIGNAL, GE1L72);

--GE1_td_shift[2] is std_1c20:inst|jtag_uart:the_jtag_uart|alt_jtag_atlantic:jtag_uart_alt_jtag_atlantic|td_shift[2] at LC_X53_Y19_N6

--operation mode is normal

GE1_td_shift[2] = AMPP_FUNCTION(A1L5, GE1L53, GE1L56, GE1L63, !C1_CLR_SIGNAL, GE1L52);

--GE1L54 is std_1c20:inst|jtag_uart:the_jtag_uart|alt_jtag_atlantic:jtag_uart_alt_jtag_atlantic|td_shift[9]~3553 at LC_X53_Y19_N9

--operation mode is normal

GE1L54 = AMPP_FUNCTION(GE1_count[9], GE1_write_stalled, GE1_td_shift[2]);

--GE1_count[8] is std_1c20:inst|jtag_uart:the_jtag_uart|alt_jtag_atlantic:jtag_uart_alt_jtag_atlantic|count[8] at LC_X54_Y19_N5

--operation mode is normal

GE1_count[8] = AMPP_FUNCTION(A1L5, GE1_count[7], FF1_state[4], !C1_CLR_SIGNAL, GE1L52);

--GE1L55 is std_1c20:inst|jtag_uart:the_jtag_uart|alt_jtag_atlantic:jtag_uart_alt_jtag_atlantic|td_shift[9]~3555 at LC_X54_Y19_N8

--operation mode is normal

GE1L55 = AMPP_FUNCTION(BF4_Q[0], GE1_count[8], GE1L66, FF1_state[4]);

--GE1L36 is std_1c20:inst|jtag_uart:the_jtag_uart|alt_jtag_atlantic:jtag_uart_alt_jtag_atlantic|state~198 at LC_X55_Y19_N4

--operation mode is normal

GE1L36 = AMPP_FUNCTION(BF4_Q[0], FF1_state[3], GE1_state);

--GE1_count[0] is std_1c20:inst|jtag_uart:the_jtag_uart|alt_jtag_atlantic:jtag_uart_alt_jtag_atlantic|count[0] at LC_X54_Y19_N2

--operation mode is normal

GE1_count[0] = AMPP_FUNCTION(A1L5, GE1_count[9], FF1_state[4], !C1_CLR_SIGNAL, GE1L52);

--GE1_rdata[7] is std_1c20:inst|jtag_uart:the_jtag_uart|alt_jtag_atlantic:jtag_uart_alt_jtag_atlantic|rdata[7] at LC_X53_Y19_N0

--operation mode is normal

GE1_rdata[7] = AMPP_FUNCTION(QC2__clk0, SE1_q_b[7], F1_data_out, GE1L18);

--GE1L69 is std_1c20:inst|jtag_uart:the_jtag_uart|alt_jtag_atlantic:jtag_uart_alt_jtag_atlantic|user_saw_rvalid~148 at LC_X55_Y19_N8

--operation mode is normal

GE1L69 = AMPP_FUNCTION(FF1_state[4], BF4_Q[0], GE1L1, GE1_state);

--BF6_Q[0] is sld_hub:sld_hub_inst|sld_dffex:\GEN_SHADOW_IRF:2:S_IRF|Q[0] at LC_X56_Y16_N8

--operation mode is normal

BF6_Q[0] = AMPP_FUNCTION(A1L5, BF8_Q[1], BF6_Q[0], C1L9, BF3_Q[0], !C1_CLR_SIGNAL);

--BF4L3 is sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:2:IRF|Q[0]~207 at LC_X56_Y16_N3

--operation mode is normal

BF4L3 = AMPP_FUNCTION(BF2_Q[0], BF6_Q[0], BF3_Q[0]);

--C1L27 is sld_hub:sld_hub_inst|IRF_ENABLE[2]~137 at LC_X57_Y16_N8

--operation mode is normal

C1L27 = AMPP_FUNCTION(C1L25, C1L9, BF2_Q[0], BF8_Q[1]);

--S1_E_src2_prelim[30] is std_1c20:inst|cpu:the_cpu|E_src2_prelim[30] at LC_X43_Y15_N9

--operation mode is normal

S1_E_src2_prelim[30] = AMPP_FUNCTION(QC2__clk0, S1L668, S1_W_wr_data[30], S1L2482, DD1_q_b[30], F1_data_out, S1L664, S1_W_stall);

--S1L2480 is std_1c20:inst|cpu:the_cpu|M_wr_data_unfiltered[30]~3703 at LC_X40_Y13_N3

--operation mode is normal

S1L2480 = AMPP_FUNCTION(S1_M_shift_rot_result[30], S1L2062Q);

--S1_av_ld_data_aligned_or_div[30] is std_1c20:inst|cpu:the_cpu|av_ld_data_aligned_or_div[30] at LC_X41_Y20_N6

--operation mode is normal

S1_av_ld_data_aligned_or_div[30] = AMPP_FUNCTION(QC2__clk0, S1L239, S1L637, S1_M_iw[4], S1_M_ctrl_ld_signed, F1_data_out);

--S1L1988 is std_1c20:inst|cpu:the_cpu|M_alu_result[30]~299 at LC_X34_Y14_N4

--operation mode is normal

S1L1988 = AMPP_FUNCTION(S1_E_logic_op[1], S1L2004, YC1_result[30], S1L2002);

--S1L1995Q is std_1c20:inst|cpu:the_cpu|M_alu_result[30]~313 at LC_X34_Y14_N4

--operation mode is normal

S1L1995Q = AMPP_FUNCTION(QC2__clk0, S1_E_logic_op[1], S1L2004, YC1_result[30], S1L2002, F1_data_out);

--S1L226Q is std_1c20:inst|cpu:the_cpu|av_ld_data_aligned_or_div[30]~85 at LC_X35_Y18_N6

--operation mode is normal

S1L226Q = AMPP_FUNCTION(QC2__clk0, S1L2490, S1L2484, S1L1988, S1L2492, F1_data_out);

--S1L1148 is std_1c20:inst|cpu:the_cpu|E_src2_reg[30]~476 at LC_X40_Y13_N6

--operation mode is normal

S1L1148 = AMPP_FUNCTION(S1_E_src2_prelim[30], S1L2480, S1L226Q, S1_E_src2_hazard_M);

--S1_E_src2_prelim[29] is std_1c20:inst|cpu:the_cpu|E_src2_prelim[29] at LC_X44_Y14_N0

--operation mode is normal

S1_E_src2_prelim[29] = AMPP_FUNCTION(QC2__clk0, S1_W_wr_data[29], S1L668, S1L2479, DD1_q_b[29], F1_data_out, S1L664, S1_W_stall);

--S1_M_shift_rot_result[29] is std_1c20:inst|cpu:the_cpu|M_shift_rot_result[29] at LC_X40_Y12_N4

--operation mode is normal

S1_M_shift_rot_result[29] = AMPP_FUNCTION(QC2__clk0, S1_M_shift_rot_result[28], S1_M_shift_rot_result[30], S1L882, S1_M_ctrl_shift_rot_right, F1_data_out, !S1_M_shift_rot_stall);

--S1L2477 is std_1c20:inst|cpu:the_cpu|M_wr_data_unfiltered[29]~3705 at LC_X44_Y14_N5

--operation mode is normal

S1L2477 = AMPP_FUNCTION(S1L2062Q, S1_M_shift_rot_result[29]);

--S1L222 is std_1c20:inst|cpu:the_cpu|av_ld_data_aligned_or_div[29]~82 at LC_X41_Y18_N5

--operation mode is normal

S1L222 = AMPP_FUNCTION(S1_M_ctrl_ld_signed, S1_M_iw[4], S1L632, S1L239);

--S1_av_ld_data_aligned_or_div[29] is std_1c20:inst|cpu:the_cpu|av_ld_data_aligned_or_div[29] at LC_X41_Y18_N5

--operation mode is normal

S1_av_ld_data_aligned_or_div[29] = AMPP_FUNCTION(QC2__clk0, S1_M_ctrl_ld_signed, S1_M_iw[4], S1L632, S1L239, F1_data_out);

--S1L223Q is std_1c20:inst|cpu:the_cpu|av_ld_data_aligned_or_div[29]~83 at LC_X41_Y12_N0

--operation mode is normal

S1L223Q = AMPP_FUNCTION(QC2__clk0, S1_av_ld_aligning_data, S1L2057, S1L1966, S1L222, F1_data_out);

--S1L1147 is std_1c20:inst|cpu:the_cpu|E_src2_reg[29]~477 at LC_X44_Y14_N2

--operation mode is normal

S1L1147 = AMPP_FUNCTION(S1_E_src2_hazard_M, S1L2477, S1L223Q, S1_E_src2_prelim[29]);

--S1_E_src2_prelim[28] is std_1c20:inst|cpu:the_cpu|E_src2_prelim[28] at LC_X43_Y14_N6

--operation mode is normal

S1_E_src2_prelim[28] = AMPP_FUNCTION(QC2__clk0, S1_W_wr_data[28], DD1_q_b[28], S1L2476, S1L668, F1_data_out, S1L664, S1_W_stall);

--S1L2474 is std_1c20:inst|cpu:the_cpu|M_wr_data_unfiltered[28]~3707 at LC_X42_Y13_N5

--operation mode is normal

S1L2474 = AMPP_FUNCTION(S1_M_shift_rot_result[28], S1L2062Q);

--S1L219 is std_1c20:inst|cpu:the_cpu|av_ld_data_aligned_or_div[28]~80 at LC_X41_Y18_N2

--operation mode is normal

S1L219 = AMPP_FUNCTION(S1_M_ctrl_ld_signed, S1_M_iw[4], S1L627, S1L239);

--S1_av_ld_data_aligned_or_div[28] is std_1c20:inst|cpu:the_cpu|av_ld_data_aligned_or_div[28] at LC_X41_Y18_N2

--operation mode is normal

S1_av_ld_data_aligned_or_div[28] = AMPP_FUNCTION(QC2__clk0, S1_M_ctrl_ld_signed, S1_M_iw[4], S1L627, S1L239, F1_data_out);

--S1L220Q is std_1c20:inst|cpu:the_cpu|av_ld_data_aligned_or_div[28]~81 at LC_X41_Y12_N2

--operation mode is normal

S1L220Q = AMPP_FUNCTION(QC2__clk0, S1_av_ld_aligning_data, S1L2057, S1L1942, S1L219, F1_data_out);

--S1L1146 is std_1c20:inst|cpu:the_cpu|E_src2_reg[28]~478 at LC_X42_Y13_N2

--operation mode is normal

S1L1146 = AMPP_FUNCTION(S1_E_src2_prelim[28], S1L220Q, S1_E_src2_hazard_M, S1L2474);

--S1_E_src2_prelim[27] is std_1c20:inst|cpu:the_cpu|E_src2_prelim[27] at LC_X43_Y14_N5

--operation mode is normal

S1_E_src2_prelim[27] = AMPP_FUNCTION(QC2__clk0, S1_W_wr_data[27], DD1_q_b[27], S1L2473, S1L668, F1_data_out, S1L664, S1_W_stall);

--S1L1145 is std_1c20:inst|cpu:the_cpu|E_src2_reg[27]~479 at LC_X43_Y13_N4

--operation mode is normal

S1L1145 = AMPP_FUNCTION(S1_E_src2_prelim[27], S1_E_src2_hazard_M, S1L2471, S1L217Q);

--KB1L65 is std_1c20:inst|sdram:the_sdram|active_data[30]~6664 at LC_X16_Y20_N7

--operation mode is normal

KB1L65 = F1_data_out & KB1L676 & (KB1L704 # !KB1L674);

--KB1L66 is std_1c20:inst|sdram:the_sdram|active_data[30]~6665 at LC_X16_Y22_N3

--operation mode is normal

KB1L66 = KB1L674 & (!KB1_m_state[0] # !KB1L991) # !KB1L674 & (KB1_m_state[0] & KB1L677);

--S1L50 is std_1c20:inst|cpu:the_cpu|A_WE_StdLogicVector~14130 at LC_X29_Y17_N5

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

S1L50 = AMPP_FUNCTION(S1_E_extra_pc[12], S1_E_ctrl_jmp_direct, S1L2373);

--S1_E_iw[18] is std_1c20:inst|cpu:the_cpu|E_iw[18] at LC_X29_Y17_N5

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

S1_E_iw[18] = AMPP_FUNCTION(QC2__clk0, S1_D_iw[18], F1_data_out, GND, S1_W_stall);

--S1_E_pc[12] is std_1c20:inst|cpu:the_cpu|E_pc[12] at LC_X29_Y18_N9

--operation mode is normal

S1_E_pc[12] = AMPP_FUNCTION(QC2__clk0, S1_D_pc[12], F1_data_out, S1_W_stall);

--S1_E_ctrl_jmp_indirect is std_1c20:inst|cpu:the_cpu|E_ctrl_jmp_indirect at LC_X29_Y14_N0

--operation mode is normal

S1_E_ctrl_jmp_indirect = AMPP_FUNCTION(QC2__clk0, S1L1168, S1L305, S1L1171, S1_D_iw[12], F1_data_out, S1_W_stall);

--S1L51 is std_1c20:inst|cpu:the_cpu|A_WE_StdLogicVector~14131 at LC_X31_Y16_N5

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

S1L51 = AMPP_FUNCTION(S1L2373, S1_E_extra_pc[16], S1_E_ctrl_jmp_direct);

--S1_E_iw[22] is std_1c20:inst|cpu:the_cpu|E_iw[22] at LC_X31_Y16_N5

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

S1_E_iw[22] = AMPP_FUNCTION(QC2__clk0, S1_D_iw[22], F1_data_out, GND, S1_W_stall);

--S1_E_pc[16] is std_1c20:inst|cpu:the_cpu|E_pc[16] at LC_X29_Y20_N2

--operation mode is normal

S1_E_pc[16] = AMPP_FUNCTION(QC2__clk0, S1_D_pc[16], F1_data_out, S1_W_stall);

--S1_ic_tag_clr_valid_bits_nxt is std_1c20:inst|cpu:the_cpu|ic_tag_clr_valid_bits_nxt at LC_X23_Y20_N2

--operation mode is normal

S1_ic_tag_clr_valid_bits_nxt = AMPP_FUNCTION(S1_reset_d1, S1L323, S1L322, S1L1562);

--S1L52 is std_1c20:inst|cpu:the_cpu|A_WE_StdLogicVector~14132 at LC_X31_Y17_N9

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

S1L52 = AMPP_FUNCTION(S1_E_extra_pc[3], S1_E_ctrl_jmp_direct, S1L2373);

--S1_E_iw[9] is std_1c20:inst|cpu:the_cpu|E_iw[9] at LC_X31_Y17_N9

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

S1_E_iw[9] = AMPP_FUNCTION(QC2__clk0, S1_D_iw[9], F1_data_out, GND, S1_W_stall);

--S1_E_pc[3] is std_1c20:inst|cpu:the_cpu|E_pc[3] at LC_X29_Y19_N9

--operation mode is normal

S1_E_pc[3] = AMPP_FUNCTION(QC2__clk0, S1_D_pc[3], F1_data_out, S1_W_stall);

--S1L53 is std_1c20:inst|cpu:the_cpu|A_WE_StdLogicVector~14133 at LC_X31_Y17_N5

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

S1L53 = AMPP_FUNCTION(S1_E_extra_pc[4], S1_E_ctrl_jmp_direct, S1L2373);

--S1_E_iw[10] is std_1c20:inst|cpu:the_cpu|E_iw[10] at LC_X31_Y17_N5

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

S1_E_iw[10] = AMPP_FUNCTION(QC2__clk0, S1_D_iw[10], F1_data_out, GND, S1_W_stall);

--S1_E_pc[4] is std_1c20:inst|cpu:the_cpu|E_pc[4] at LC_X30_Y20_N6

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

S1_E_pc[4] = AMPP_FUNCTION(QC2__clk0, S1_D_pc[4], F1_data_out, GND, S1_W_stall);

--S1L54 is std_1c20:inst|cpu:the_cpu|A_WE_StdLogicVector~14134 at LC_X29_Y17_N1

--operation mode is normal

S1L54 = AMPP_FUNCTION(S1_E_extra_pc[5], S1_E_iw[11], S1_E_ctrl_jmp_direct, S1L2373);

--S1_E_pc[5] is std_1c20:inst|cpu:the_cpu|E_pc[5] at LC_X29_Y18_N4

--operation mode is normal

S1_E_pc[5] = AMPP_FUNCTION(QC2__clk0, S1_D_pc[5], F1_data_out, S1_W_stall);

--S1L55 is std_1c20:inst|cpu:the_cpu|A_WE_StdLogicVector~14135 at LC_X29_Y15_N1

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

S1L55 = AMPP_FUNCTION(S1_E_extra_pc[6], S1_E_ctrl_jmp_direct, S1L2373);

--S1_E_iw[12] is std_1c20:inst|cpu:the_cpu|E_iw[12] at LC_X29_Y15_N1

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

S1_E_iw[12] = AMPP_FUNCTION(QC2__clk0, S1_D_iw[12], F1_data_out, GND, S1_W_stall);

--S1_E_pc[6] is std_1c20:inst|cpu:the_cpu|E_pc[6] at LC_X29_Y18_N7

--operation mode is normal

S1_E_pc[6] = AMPP_FUNCTION(QC2__clk0, S1_D_pc[6], F1_data_out, S1_W_stall);

--S1L56 is std_1c20:inst|cpu:the_cpu|A_WE_StdLogicVector~14136 at LC_X29_Y16_N5

--operation mode is normal

S1L56 = AMPP_FUNCTION(S1_E_ctrl_jmp_direct, S1_E_iw[13], S1_E_extra_pc[7], S1L2373);

--S1_E_pc[7] is std_1c20:inst|cpu:the_cpu|E_pc[7] at LC_X29_Y16_N4

--operation mode is normal

S1_E_pc[7] = AMPP_FUNCTION(QC2__clk0, S1_D_pc[7], F1_data_out, S1_W_stall);

--S1L57 is std_1c20:inst|cpu:the_cpu|A_WE_StdLogicVector~14137 at LC_X29_Y16_N7

--operation mode is normal

S1L57 = AMPP_FUNCTION(S1L2373, S1_E_extra_pc[8], S1_E_iw[14], S1_E_ctrl_jmp_direct);

--S1_E_pc[8] is std_1c20:inst|cpu:the_cpu|E_pc[8] at LC_X26_Y20_N3

--operation mode is normal

S1_E_pc[8] = AMPP_FUNCTION(QC2__clk0, S1_D_pc[8], F1_data_out, S1_W_stall);

--S1L58 is std_1c20:inst|cpu:the_cpu|A_WE_StdLogicVector~14138 at LC_X29_Y16_N3

--operation mode is normal

S1L58 = AMPP_FUNCTION(S1L2373, S1_E_extra_pc[9], S1_E_iw[15], S1_E_ctrl_jmp_direct);

--S1_E_pc[9] is std_1c20:inst|cpu:the_cpu|E_pc[9] at LC_X26_Y16_N6

--operation mode is normal

S1_E_pc[9] = AMPP_FUNCTION(QC2__clk0, S1_D_pc[9], F1_data_out, S1_W_stall);

--S1L59 is std_1c20:inst|cpu:the_cpu|A_WE_StdLogicVector~14139 at LC_X30_Y16_N0

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

S1L59 = AMPP_FUNCTION(S1L2373, S1_E_extra_pc[20], S1_E_ctrl_jmp_direct);

--S1_E_iw[26] is std_1c20:inst|cpu:the_cpu|E_iw[26] at LC_X30_Y16_N0

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

S1_E_iw[26] = AMPP_FUNCTION(QC2__clk0, S1_D_iw[26], F1_data_out, GND, S1_W_stall);

--S1_E_pc[20] is std_1c20:inst|cpu:the_cpu|E_pc[20] at LC_X27_Y16_N9

--operation mode is normal

S1_E_pc[20] = AMPP_FUNCTION(QC2__clk0, S1_D_pc[20], F1_data_out, S1_W_stall);

--S1L60 is std_1c20:inst|cpu:the_cpu|A_WE_StdLogicVector~14140 at LC_X29_Y17_N2

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

S1L60 = AMPP_FUNCTION(S1L2373, S1_E_ctrl_jmp_direct, S1_E_extra_pc[19]);

--S1_E_iw[25] is std_1c20:inst|cpu:the_cpu|E_iw[25] at LC_X29_Y17_N2

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

S1_E_iw[25] = AMPP_FUNCTION(QC2__clk0, S1_D_iw[25], F1_data_out, GND, S1_W_stall);

--S1_E_pc[19] is std_1c20:inst|cpu:the_cpu|E_pc[19] at LC_X29_Y18_N8

--operation mode is normal

S1_E_pc[19] = AMPP_FUNCTION(QC2__clk0, S1_D_pc[19], F1_data_out, S1_W_stall);

--S1L61 is std_1c20:inst|cpu:the_cpu|A_WE_StdLogicVector~14141 at LC_X32_Y17_N7

--operation mode is normal

S1L61 = AMPP_FUNCTION(S1_E_extra_pc[18], S1_E_ctrl_break);

--S1L62 is std_1c20:inst|cpu:the_cpu|A_WE_StdLogicVector~14142 at LC_X30_Y16_N1

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

S1L62 = AMPP_FUNCTION(S1L61, S1_E_ctrl_exception, S1_E_ctrl_jmp_direct);

--S1_E_iw[24] is std_1c20:inst|cpu:the_cpu|E_iw[24] at LC_X30_Y16_N1

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

S1_E_iw[24] = AMPP_FUNCTION(QC2__clk0, S1_D_iw[24], F1_data_out, GND, S1_W_stall);

--S1_E_pc[18] is std_1c20:inst|cpu:the_cpu|E_pc[18] at LC_X27_Y16_N7

--operation mode is normal

S1_E_pc[18] = AMPP_FUNCTION(QC2__clk0, S1_D_pc[18], F1_data_out, S1_W_stall);

--S1L63 is std_1c20:inst|cpu:the_cpu|A_WE_StdLogicVector~14143 at LC_X29_Y17_N9

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

S1L63 = AMPP_FUNCTION(S1_E_extra_pc[17], S1_E_ctrl_jmp_direct, S1L2373);

--S1_E_iw[23] is std_1c20:inst|cpu:the_cpu|E_iw[23] at LC_X29_Y17_N9

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

S1_E_iw[23] = AMPP_FUNCTION(QC2__clk0, S1_D_iw[23], F1_data_out, GND, S1_W_stall);

--S1_E_pc[17] is std_1c20:inst|cpu:the_cpu|E_pc[17] at LC_X25_Y16_N4

--operation mode is normal

S1_E_pc[17] = AMPP_FUNCTION(QC2__clk0, S1_D_pc[17], F1_data_out, S1_W_stall);

--S1L64 is std_1c20:inst|cpu:the_cpu|A_WE_StdLogicVector~14144 at LC_X30_Y16_N4

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

S1L64 = AMPP_FUNCTION(S1L2373, S1_E_extra_pc[21], S1_E_ctrl_jmp_direct);

--S1_E_iw[27] is std_1c20:inst|cpu:the_cpu|E_iw[27] at LC_X30_Y16_N4

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

S1_E_iw[27] = AMPP_FUNCTION(QC2__clk0, S1_D_iw[27], F1_data_out, GND, S1_W_stall);

--S1_E_pc[21] is std_1c20:inst|cpu:the_cpu|E_pc[21] at LC_X27_Y16_N8

--operation mode is normal

S1_E_pc[21] = AMPP_FUNCTION(QC2__clk0, S1_D_pc[21], F1_data_out, S1_W_stall);

--S1L65 is std_1c20:inst|cpu:the_cpu|A_WE_StdLogicVector~14145 at LC_X30_Y16_N6

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

S1L65 = AMPP_FUNCTION(S1L2373, S1_E_extra_pc[14], S1_E_ctrl_jmp_direct);

--S1_E_iw[20] is std_1c20:inst|cpu:the_cpu|E_iw[20] at LC_X30_Y16_N6

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

S1_E_iw[20] = AMPP_FUNCTION(QC2__clk0, S1_D_iw[20], F1_data_out, GND, S1_W_stall);

--S1_E_pc[14] is std_1c20:inst|cpu:the_cpu|E_pc[14] at LC_X26_Y16_N8

--operation mode is normal

S1_E_pc[14] = AMPP_FUNCTION(QC2__clk0, S1_D_pc[14], F1_data_out, S1_W_stall);

--S1L66 is std_1c20:inst|cpu:the_cpu|A_WE_StdLogicVector~14146 at LC_X31_Y17_N4

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

S1L66 = AMPP_FUNCTION(S1_E_extra_pc[11], S1_E_ctrl_jmp_direct, S1L2373);

--S1_E_iw[17] is std_1c20:inst|cpu:the_cpu|E_iw[17] at LC_X31_Y17_N4

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

S1_E_iw[17] = AMPP_FUNCTION(QC2__clk0, S1_D_iw[17], F1_data_out, GND, S1_W_stall);

--S1_E_pc[11] is std_1c20:inst|cpu:the_cpu|E_pc[11] at LC_X30_Y19_N7

--operation mode is normal

S1_E_pc[11] = AMPP_FUNCTION(QC2__clk0, S1_D_pc[11], F1_data_out, S1_W_stall);

--S1L67 is std_1c20:inst|cpu:the_cpu|A_WE_StdLogicVector~14147 at LC_X30_Y17_N9

--operation mode is normal

S1L67 = AMPP_FUNCTION(S1_E_extra_pc[22], S1_E_ctrl_break);

--S1L68 is std_1c20:inst|cpu:the_cpu|A_WE_StdLogicVector~14148 at LC_X30_Y16_N9

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

S1L68 = AMPP_FUNCTION(S1L67, S1_E_ctrl_exception, S1_E_ctrl_jmp_direct);

--S1_E_iw[28] is std_1c20:inst|cpu:the_cpu|E_iw[28] at LC_X30_Y16_N9

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

S1_E_iw[28] = AMPP_FUNCTION(QC2__clk0, S1_D_iw[28], F1_data_out, GND, S1_W_stall);

--S1_E_pc[22] is std_1c20:inst|cpu:the_cpu|E_pc[22] at LC_X30_Y19_N4

--operation mode is normal

S1_E_pc[22] = AMPP_FUNCTION(QC2__clk0, S1_D_pc[22], F1_data_out, S1_W_stall);

--S1L69 is std_1c20:inst|cpu:the_cpu|A_WE_StdLogicVector~14149 at LC_X32_Y18_N3

--operation mode is normal

S1L69 = AMPP_FUNCTION(S1_E_extra_pc[23], S1_E_ctrl_break);

--S1L70 is std_1c20:inst|cpu:the_cpu|A_WE_StdLogicVector~14150 at LC_X32_Y18_N6

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

S1L70 = AMPP_FUNCTION(S1_E_ctrl_exception, S1_E_ctrl_jmp_direct, S1L69);

--S1_E_iw[29] is std_1c20:inst|cpu:the_cpu|E_iw[29] at LC_X32_Y18_N6

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

S1_E_iw[29] = AMPP_FUNCTION(QC2__clk0, S1_D_iw[29], F1_data_out, GND, S1_W_stall);

--S1_E_pc[23] is std_1c20:inst|cpu:the_cpu|E_pc[23] at LC_X29_Y19_N8

--operation mode is normal

S1_E_pc[23] = AMPP_FUNCTION(QC2__clk0, S1_D_pc[23], F1_data_out, S1_W_stall);

--S1L71 is std_1c20:inst|cpu:the_cpu|A_WE_StdLogicVector~14151 at LC_X30_Y18_N5

--operation mode is normal

S1L71 = AMPP_FUNCTION(S1_E_extra_pc[15], S1_E_ctrl_break);

--S1L72 is std_1c20:inst|cpu:the_cpu|A_WE_StdLogicVector~14152 at LC_X30_Y18_N1

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

S1L72 = AMPP_FUNCTION(S1_E_ctrl_exception, S1_E_ctrl_jmp_direct, S1L71);

--S1_E_iw[21] is std_1c20:inst|cpu:the_cpu|E_iw[21] at LC_X30_Y18_N1

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

S1_E_iw[21] = AMPP_FUNCTION(QC2__clk0, S1_D_iw[21], F1_data_out, GND, S1_W_stall);

--S1_E_pc[15] is std_1c20:inst|cpu:the_cpu|E_pc[15] at LC_X30_Y19_N9

--operation mode is normal

S1_E_pc[15] = AMPP_FUNCTION(QC2__clk0, S1_D_pc[15], F1_data_out, S1_W_stall);

--S1L73 is std_1c20:inst|cpu:the_cpu|A_WE_StdLogicVector~14153 at LC_X32_Y18_N7

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

S1L73 = AMPP_FUNCTION(S1L2373, S1_E_extra_pc[13], S1_E_ctrl_jmp_direct);

--S1_E_iw[19] is std_1c20:inst|cpu:the_cpu|E_iw[19] at LC_X32_Y18_N7

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

S1_E_iw[19] = AMPP_FUNCTION(QC2__clk0, S1_D_iw[19], F1_data_out, GND, S1_W_stall);

--S1_E_pc[13] is std_1c20:inst|cpu:the_cpu|E_pc[13] at LC_X30_Y19_N8

--operation mode is normal

S1_E_pc[13] = AMPP_FUNCTION(QC2__clk0, S1_D_pc[13], F1_data_out, S1_W_stall);

--S1L74 is std_1c20:inst|cpu:the_cpu|A_WE_StdLogicVector~14154 at LC_X30_Y17_N5

--operation mode is normal

S1L74 = AMPP_FUNCTION(S1L2373, S1_E_ctrl_jmp_direct, S1_E_iw[16], S1_E_extra_pc[10]);

--S1_E_pc[10] is std_1c20:inst|cpu:the_cpu|E_pc[10] at LC_X29_Y19_N1

--operation mode is normal

S1_E_pc[10] = AMPP_FUNCTION(QC2__clk0, S1_D_pc[10], F1_data_out, S1_W_stall);

--S1L1661 is std_1c20:inst|cpu:the_cpu|ic_fill_valid_bits_nxt[5]~321 at LC_X22_Y20_N6

--operation mode is normal

S1L1661 = AMPP_FUNCTION(S1L1541, S1L1539, S1L1540, S1L1542);

--S1L1665 is std_1c20:inst|cpu:the_cpu|ic_tag_clr_valid_bits_nxt~34 at LC_X23_Y20_N1

--operation mode is normal

S1L1665 = AMPP_FUNCTION(S1_reset_d1, S1_M_ctrl_invalidate_i, S1_M_valid_from_E);

--S1_ic_fill_valid_bits_en is std_1c20:inst|cpu:the_cpu|ic_fill_valid_bits_en at LC_X23_Y20_N4

--operation mode is normal

S1_ic_fill_valid_bits_en = AMPP_FUNCTION(S1L1665, S1L323, S1L322, S1L1538);

--S1L75 is std_1c20:inst|cpu:the_cpu|A_WE_StdLogicVector~14155 at LC_X31_Y18_N5

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

S1L75 = AMPP_FUNCTION(S1L2373, S1_E_extra_pc[2], S1_E_ctrl_jmp_direct);

--S1_E_iw[8] is std_1c20:inst|cpu:the_cpu|E_iw[8] at LC_X31_Y18_N5

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

S1_E_iw[8] = AMPP_FUNCTION(QC2__clk0, S1_D_iw[8], F1_data_out, GND, S1_W_stall);

--S1_E_pc[2] is std_1c20:inst|cpu:the_cpu|E_pc[2] at LC_X29_Y19_N7

--operation mode is normal

S1_E_pc[2] = AMPP_FUNCTION(QC2__clk0, S1_D_pc[2], F1_data_out, S1_W_stall);

--S1L1659 is std_1c20:inst|cpu:the_cpu|ic_fill_valid_bits_nxt[3]~323 at LC_X21_Y20_N1

--operation mode is normal

S1L1659 = AMPP_FUNCTION(S1L1542, S1L1540, S1L1541, S1L1539);

--S1L76 is std_1c20:inst|cpu:the_cpu|A_WE_StdLogicVector~14156 at LC_X30_Y17_N7

--operation mode is normal

S1L76 = AMPP_FUNCTION(S1L2373, S1_E_ctrl_jmp_direct, S1_E_iw[7], S1_E_extra_pc[1]);

--S1_E_pc[1] is std_1c20:inst|cpu:the_cpu|E_pc[1] at LC_X26_Y20_N1

--operation mode is normal

S1_E_pc[1] = AMPP_FUNCTION(QC2__clk0, S1_D_pc[1], F1_data_out, S1_W_stall);

--S1L1657 is std_1c20:inst|cpu:the_cpu|ic_fill_valid_bits_nxt[1]~325 at LC_X22_Y20_N8

--operation mode is normal

S1L1657 = AMPP_FUNCTION(S1L1541, S1L1539, S1L1540, S1L1542);

--S1L1662 is std_1c20:inst|cpu:the_cpu|ic_fill_valid_bits_nxt[7]~327 at LC_X22_Y20_N0

--operation mode is normal

S1L1662 = AMPP_FUNCTION(S1L1541, S1L1539, S1L1540, S1L1542);

--S1L1658 is std_1c20:inst|cpu:the_cpu|ic_fill_valid_bits_nxt[2]~329 at LC_X21_Y20_N3

--operation mode is normal

S1L1658 = AMPP_FUNCTION(S1L1542, S1L1540, S1L1541, S1L1539);

--S1L1660 is std_1c20:inst|cpu:the_cpu|ic_fill_valid_bits_nxt[4]~331 at LC_X21_Y20_N6

--operation mode is normal

S1L1660 = AMPP_FUNCTION(S1L1542, S1L1540, S1L1541, S1L1539);

--S1L1656 is std_1c20:inst|cpu:the_cpu|ic_fill_valid_bits_nxt[0]~333 at LC_X21_Y20_N0

--operation mode is normal

S1L1656 = AMPP_FUNCTION(S1L1542, S1L1540, S1L1541, S1L1539);

--S1L1187 is std_1c20:inst|cpu:the_cpu|Equal158~63 at LC_X21_Y20_N9

--operation mode is normal

S1L1187 = AMPP_FUNCTION(S1L1542, S1L1540, S1L1541, S1L1539);

--S1L77 is std_1c20:inst|cpu:the_cpu|A_WE_StdLogicVector~14157 at LC_X31_Y18_N2

--operation mode is normal

S1L77 = AMPP_FUNCTION(S1_E_extra_pc[0], S1L2373, S1_E_iw[6], S1_E_ctrl_jmp_direct);

--S1_E_pc[0] is std_1c20:inst|cpu:the_cpu|E_pc[0] at LC_X29_Y19_N4

--operation mode is normal

S1_E_pc[0] = AMPP_FUNCTION(QC2__clk0, S1_D_pc[0], F1_data_out, S1_W_stall);

--U1L7 is std_1c20:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_read_but_no_slave_selected~56 at LC_X27_Y24_N5

--operation mode is normal

U1L7 = !NB1L24 & !X1L8 & (!V1L40);

--U1L13Q is std_1c20:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_read_but_no_slave_selected~61 at LC_X27_Y25_N7

--operation mode is normal

U1L13Q_lut_out = !Y1L742 & U1L7 & !Y1L14 & !Y1L176;

U1L13Q = DFFEAS(U1L13Q_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--Y1_cpu_instruction_master_read_data_valid_ext_flash_s1_shift_register[0] is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|cpu_instruction_master_read_data_valid_ext_flash_s1_shift_register[0] at LC_X30_Y24_N8

--operation mode is normal

Y1_cpu_instruction_master_read_data_valid_ext_flash_s1_shift_register[0]_lut_out = U1L223 & Y1L181 & (Y1L43 # Y1L40);

Y1_cpu_instruction_master_read_data_valid_ext_flash_s1_shift_register[0] = DFFEAS(Y1_cpu_instruction_master_read_data_valid_ext_flash_s1_shift_register[0]_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--Y1_cpu_instruction_master_read_data_valid_lan91c111_s1_shift_register[0] is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|cpu_instruction_master_read_data_valid_lan91c111_s1_shift_register[0] at LC_X32_Y24_N4

--operation mode is normal

Y1_cpu_instruction_master_read_data_valid_lan91c111_s1_shift_register[0]_lut_out = Y1L874 & Y1L188 & (Y1L25 # !Y1L5);

Y1_cpu_instruction_master_read_data_valid_lan91c111_s1_shift_register[0] = DFFEAS(Y1_cpu_instruction_master_read_data_valid_lan91c111_s1_shift_register[0]_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--Y1_cpu_instruction_master_read_data_valid_ext_ram_s1_shift_register[0] is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|cpu_instruction_master_read_data_valid_ext_ram_s1_shift_register[0] at LC_X31_Y22_N6

--operation mode is normal

Y1_cpu_instruction_master_read_data_valid_ext_ram_s1_shift_register[0]_lut_out = Y1L1007 & (Y1L46 # Y1L49);

Y1_cpu_instruction_master_read_data_valid_ext_ram_s1_shift_register[0] = DFFEAS(Y1_cpu_instruction_master_read_data_valid_ext_ram_s1_shift_register[0]_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--KB1_rd_valid[0] is std_1c20:inst|sdram:the_sdram|rd_valid[0] at LC_X13_Y25_N8

--operation mode is normal

KB1_rd_valid[0]_lut_out = !KB1L231Q & !KB1L240Q & KB1L235Q;

KB1_rd_valid[0] = DFFEAS(KB1_rd_valid[0]_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--WE1L50 is std_1c20:inst|sdram_s1_arbitrator:the_sdram_s1|rdv_fifo_for_cpu_instruction_master_to_sdram_s1_module:rdv_fifo_for_cpu_instruction_master_to_sdram_s1|stage_3~5 at LC_X23_Y25_N9

--operation mode is normal

WE1L50 = WE1_full_4 & WE1L53Q # !WE1_full_4 & (NB1L24);

--WE1_full_3 is std_1c20:inst|sdram_s1_arbitrator:the_sdram_s1|rdv_fifo_for_cpu_instruction_master_to_sdram_s1_module:rdv_fifo_for_cpu_instruction_master_to_sdram_s1|full_3 at LC_X23_Y26_N7

--operation mode is normal

WE1_full_3_lut_out = NB1L37 & (WE1_full_2) # !NB1L37 & (KB1_za_valid & WE1_full_4 # !KB1_za_valid & (WE1_full_2));

WE1_full_3 = DFFEAS(WE1_full_3_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , VE1L22, , , , );

--WE1L30 is std_1c20:inst|sdram_s1_arbitrator:the_sdram_s1|rdv_fifo_for_cpu_instruction_master_to_sdram_s1_module:rdv_fifo_for_cpu_instruction_master_to_sdram_s1|process8~1 at LC_X24_Y25_N7

--operation mode is normal

WE1L30 = KB1_za_valid # !WE1_full_2 & NB1L37;

--LC1_master_state[1] is std_1c20:inst|clock_1:the_clock_1|clock_1_master_FSM:master_FSM|master_state[1] at LC_X47_Y29_N7

--operation mode is normal

LC1_master_state[1]_lut_out = !LC1_master_state[2] & (LC1L10 # LC1L2 & !LC1L3);

LC1_master_state[1] = DFFEAS(LC1_master_state[1]_lut_out, GLOBAL(PLD_CLOCKINPUT[1]), E1_data_out, , , , , , );

--LC1_master_state[2] is std_1c20:inst|clock_1:the_clock_1|clock_1_master_FSM:master_FSM|master_state[2] at LC_X48_Y28_N6

--operation mode is normal

LC1_master_state[2]_lut_out = !LC1L9 & !LC1_master_state[0] & (MC4_data_in_d1 $ JC1_data_out);

LC1_master_state[2] = DFFEAS(LC1_master_state[2]_lut_out, GLOBAL(PLD_CLOCKINPUT[1]), E1_data_out, , , , , , );

--LC1_master_state[0] is std_1c20:inst|clock_1:the_clock_1|clock_1_master_FSM:master_FSM|master_state[0] at LC_X48_Y28_N3

--operation mode is normal

LC1_master_state[0]_lut_out = !LC1L11 & (LC1_master_state[1] # !LC1L12 & !LC1_master_state[0]);

LC1_master_state[0] = DFFEAS(LC1_master_state[0]_lut_out, GLOBAL(PLD_CLOCKINPUT[1]), E1_data_out, , , , , , );

--E1_data_out is std_1c20:inst|std_1c20_reset_PLD_CLOCKINPUT_domain_synch_module:std_1c20_reset_PLD_CLOCKINPUT_domain_synch|data_out at LC_X48_Y28_N0

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

E1_data_out_lut_out = GND;

E1_data_out = DFFEAS(E1_data_out_lut_out, GLOBAL(PLD_CLOCKINPUT[1]), !B1L1, , , E1_data_in_d1, , , VCC);

--LC1L2 is std_1c20:inst|clock_1:the_clock_1|clock_1_master_FSM:master_FSM|internal_master_read_done~53 at LC_X48_Y29_N5

--operation mode is normal

LC1L2 = LC1_master_state[0] & LC1_master_state[1];

--R1_d1_reasons_to_wait is std_1c20:inst|connector_pll_s1_arbitrator:the_connector_pll_s1|d1_reasons_to_wait at LC_X47_Y29_N0

--operation mode is normal

R1_d1_reasons_to_wait_lut_out = !LC1L3;

R1_d1_reasons_to_wait = DFFEAS(R1_d1_reasons_to_wait_lut_out, GLOBAL(PLD_CLOCKINPUT[1]), E1_data_out, , , , , , );

--LC1L3 is std_1c20:inst|clock_1:the_clock_1|clock_1_master_FSM:master_FSM|internal_master_read_done~54 at LC_X47_Y29_N4

--operation mode is normal

LC1L3 = R1_d1_reasons_to_wait # !LC1_master_state[1];

--CC1_master_state[1] is std_1c20:inst|clock_0:the_clock_0|clock_0_master_FSM:master_FSM|master_state[1] at LC_X44_Y28_N4

--operation mode is normal

CC1_master_state[1]_lut_out = !CC1_master_state[2] & (CC1L10 # !CC1L3 & CC1L2);

CC1_master_state[1] = DFFEAS(CC1_master_state[1]_lut_out, GLOBAL(PLD_CLKFB), GLOBAL(D1_data_out), , , , , , );

--CC1_master_state[2] is std_1c20:inst|clock_0:the_clock_0|clock_0_master_FSM:master_FSM|master_state[2] at LC_X43_Y28_N1

--operation mode is normal

CC1_master_state[2]_lut_out = !CC1_master_state[0] & !CC1L9 & (AC1_data_out $ DC4_data_in_d1);

CC1_master_state[2] = DFFEAS(CC1_master_state[2]_lut_out, GLOBAL(PLD_CLKFB), GLOBAL(D1_data_out), , , , , , );

--CC1_master_state[0] is std_1c20:inst|clock_0:the_clock_0|clock_0_master_FSM:master_FSM|master_state[0] at LC_X43_Y28_N3

--operation mode is normal

CC1_master_state[0]_lut_out = !CC1L11 & (CC1_master_state[1] # !CC1L12 & !CC1_master_state[0]);

CC1_master_state[0] = DFFEAS(CC1_master_state[0]_lut_out, GLOBAL(PLD_CLKFB), GLOBAL(D1_data_out), , , , , , );

--D1_data_out is std_1c20:inst|std_1c20_reset_PLD_CLKFB_domain_synch_module:std_1c20_reset_PLD_CLKFB_domain_synch|data_out at LC_X61_Y16_N4

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

D1_data_out_lut_out = GND;

D1_data_out = DFFEAS(D1_data_out_lut_out, GLOBAL(PLD_CLKFB), !B1L1, , , D1_data_in_d1, , , VCC);

--CC1L2 is std_1c20:inst|clock_0:the_clock_0|clock_0_master_FSM:master_FSM|internal_master_read_done~53 at LC_X44_Y28_N5

--operation mode is normal

CC1L2 = CC1_master_state[0] & (CC1_master_state[1]);

--MB1_d1_reasons_to_wait is std_1c20:inst|sdram_pll_s1_arbitrator:the_sdram_pll_s1|d1_reasons_to_wait at LC_X44_Y28_N6

--operation mode is normal

MB1_d1_reasons_to_wait_lut_out = !CC1L3;

MB1_d1_reasons_to_wait = DFFEAS(MB1_d1_reasons_to_wait_lut_out, GLOBAL(PLD_CLKFB), GLOBAL(D1_data_out), , , , , , );

--CC1L3 is std_1c20:inst|clock_0:the_clock_0|clock_0_master_FSM:master_FSM|internal_master_read_done~54 at LC_X44_Y28_N0

--operation mode is normal

CC1L3 = MB1_d1_reasons_to_wait # !CC1_master_state[1];

--VE1L37 is std_1c20:inst|sdram_s1_arbitrator:the_sdram_s1|rdv_fifo_for_cpu_data_master_to_sdram_s1_module:rdv_fifo_for_cpu_data_master_to_sdram_s1|stage_3~7021 at LC_X23_Y25_N4

--operation mode is normal

VE1L37 = WE1_full_4 & (VE1L40Q) # !WE1_full_4 & NB1L20;

--GD1_break_readreg[21] is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_break:the_cpu_nios2_oci_break|break_readreg[21] at LC_X48_Y16_N3

--operation mode is normal

GD1_break_readreg[21] = AMPP_FUNCTION(QC2__clk0, SD1L188, SD1_internal_jdo1[21], SD1_internal_jdo1[36], SD1_internal_jdo1[37], !C1_CLR_SIGNAL, SD1L188);

--SD1L20 is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|DRsize[0]~19989 at LC_X46_Y16_N1

--operation mode is normal

SD1L20 = AMPP_FUNCTION(RD1_internal_MonDReg[21], GD1_break_readreg[21], SD1_ir[1]);

--SD1L21 is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|DRsize[0]~19990 at LC_X46_Y16_N4

--operation mode is normal

SD1L21 = AMPP_FUNCTION(SD1L20, SD1L142, SD1L144, SD1_ir[0]);

--SD1_sr[23] is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|sr[23] at LC_X46_Y16_N3

--operation mode is normal

SD1_sr[23] = AMPP_FUNCTION(A1L5, SD1L32, SD1L33, SD1_sr[24], SD1L9, !C1_CLR_SIGNAL, SD1L12);

--SD1L22 is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|DRsize[0]~19991 at LC_X46_Y16_N8

--operation mode is normal

SD1L22 = AMPP_FUNCTION(SD1L20, A1L4, SD1L144, SD1_ir[0]);

--KB1L155 is std_1c20:inst|sdram:the_sdram|i_refs[2]~287 at LC_X9_Y22_N5

--operation mode is normal

KB1L155 = !KB1_i_state[0] & KB1_i_state[1] & F1_data_out & !KB1_i_state[2];

--KB1L152 is std_1c20:inst|sdram:the_sdram|i_refs[0]~288 at LC_X9_Y22_N9

--operation mode is normal

KB1L152 = !KB1_i_state[0] & (F1_data_out & !KB1_i_state[2]);

--KB1L108 is std_1c20:inst|sdram:the_sdram|Add1~39 at LC_X9_Y22_N1

--operation mode is normal

KB1L108 = KB1_i_refs[1] & KB1_i_refs[0];

--ZE1L33 is std_1c20:inst|uart1:the_uart1|uart1_tx:the_uart1_tx|internal_tx_ready~40 at LC_X47_Y24_N1

--operation mode is normal

ZE1L33 = ZE1_do_load_shifter # !ZE1_internal_tx_ready;

--WB1_d1_reasons_to_wait is std_1c20:inst|uart1_s1_arbitrator:the_uart1_s1|d1_reasons_to_wait at LC_X42_Y19_N3

--operation mode is normal

WB1_d1_reasons_to_wait_lut_out = S1_M_alu_result[6] & SB1L2 & !S1L1743Q & !WB1_d1_reasons_to_wait;

WB1_d1_reasons_to_wait = DFFEAS(WB1_d1_reasons_to_wait_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--ZE1L43 is std_1c20:inst|uart1:the_uart1|uart1_tx:the_uart1_tx|tx_wr_strobe_onset~35 at LC_X42_Y19_N8

--operation mode is normal

ZE1L43 = !WB1_d1_reasons_to_wait & (!S1L1743Q);

--ZE1L44 is std_1c20:inst|uart1:the_uart1|uart1_tx:the_uart1_tx|tx_wr_strobe_onset~36 at LC_X47_Y24_N5

--operation mode is normal

ZE1L44 = !S1L1738Q & !S1_M_alu_result[3] & S1_internal_d_write & S1L1726Q;

--ZE1L38 is std_1c20:inst|uart1:the_uart1|uart1_tx:the_uart1_tx|process4~0 at LC_X48_Y25_N7

--operation mode is normal

ZE1L38 = ZE1_do_load_shifter # !ZE1_baud_rate_counter[8] & ZE1L30 & ZE1L31;

--U1L41 is std_1c20:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_readdata[8]~2417 at LC_X39_Y22_N0

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

U1_dbs_latent_8_reg_segment_1[0]_qfbk = U1_dbs_latent_8_reg_segment_1[0];

U1L41 = Y1_cpu_instruction_master_read_data_valid_ext_flash_s1_shift_register[1] & (NB1_cpu_instruction_master_read_data_valid_sdram_s1 & !KB1_za_data[8] # !U1_dbs_latent_8_reg_segment_1[0]_qfbk) # !Y1_cpu_instruction_master_read_data_valid_ext_flash_s1_shift_register[1] & NB1_cpu_instruction_master_read_data_valid_sdram_s1 & (!KB1_za_data[8]);

--U1_dbs_latent_8_reg_segment_1[0] is std_1c20:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|dbs_latent_8_reg_segment_1[0] at LC_X39_Y22_N0

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

U1_dbs_latent_8_reg_segment_1[0] = DFFEAS(U1L41, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , U1L247, Y1_internal_incoming_ext_ram_bus_data[0], , , VCC);

--U1L42 is std_1c20:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_readdata[8]~2418 at LC_X42_Y21_N1

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

Y1_cpu_instruction_master_read_data_valid_ext_ram_s1_shift_register[1]_qfbk = Y1_cpu_instruction_master_read_data_valid_ext_ram_s1_shift_register[1];

U1L42 = !U1L41 & (Y1_internal_incoming_ext_ram_bus_data[8] # !Y1_cpu_instruction_master_read_data_valid_lan91c111_s1_shift_register[1] & !Y1_cpu_instruction_master_read_data_valid_ext_ram_s1_shift_register[1]_qfbk);

--Y1_cpu_instruction_master_read_data_valid_ext_ram_s1_shift_register[1] is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|cpu_instruction_master_read_data_valid_ext_ram_s1_shift_register[1] at LC_X42_Y21_N1

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

Y1_cpu_instruction_master_read_data_valid_ext_ram_s1_shift_register[1] = DFFEAS(U1L42, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , Y1_cpu_instruction_master_read_data_valid_ext_ram_s1_shift_register[0], , , VCC);

--S1L1439Q is std_1c20:inst|cpu:the_cpu|i_readdata_d1[8]~150 at LC_X42_Y21_N2

--operation mode is normal

S1L1439Q = AMPP_FUNCTION(QC2__clk0, X1L10, U1L158, U1L42, F1_data_out);

--S1L292 is std_1c20:inst|cpu:the_cpu|D_ctrl_exception~77 at LC_X31_Y14_N2

--operation mode is normal

S1L292 = AMPP_FUNCTION(S1_D_iw[14], S1_D_iw[15], S1_D_iw[13], S1_D_iw[16]);

--BB1L71 is std_1c20:inst|jtag_uart:the_jtag_uart|process2~48 at LC_X46_Y24_N5

--operation mode is normal

BB1L71 = S1_internal_d_write & CB1L2 & UB1L9 & BB1L69;

--BB1L61 is std_1c20:inst|jtag_uart:the_jtag_uart|ien_AE~19 at LC_X46_Y24_N2

--operation mode is normal

BB1L61 = S1L1726Q & BB1L71;

--RE1_safe_q[5] is std_1c20:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_w:the_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_jf21:auto_generated|a_dpfifo_ml21:dpfifo|a_fefifo_7cf:fifo_state|cntr_9c7:count_usedw|safe_q[5] at LC_X47_Y20_N6

--operation mode is normal

RE1_safe_q[5]_carry_eqn = (!RE1L11 & RE1L15) # (RE1L11 & RE1L16);

RE1_safe_q[5]_lut_out = RE1_safe_q[5]_carry_eqn $ RE1_safe_q[5];

RE1_safe_q[5] = DFFEAS(RE1_safe_q[5]_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , NE1L1, , , , );

--RE1_safe_q[4] is std_1c20:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_w:the_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_jf21:auto_generated|a_dpfifo_ml21:dpfifo|a_fefifo_7cf:fifo_state|cntr_9c7:count_usedw|safe_q[4] at LC_X47_Y20_N5

--operation mode is arithmetic

RE1_safe_q[4]_carry_eqn = RE1L11;

RE1_safe_q[4]_lut_out = RE1_safe_q[4] $ (!RE1_safe_q[4]_carry_eqn);

RE1_safe_q[4] = DFFEAS(RE1_safe_q[4]_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , NE1L1, , , , );

--RE1L15 is std_1c20:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_w:the_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_jf21:auto_generated|a_dpfifo_ml21:dpfifo|a_fefifo_7cf:fifo_state|cntr_9c7:count_usedw|counter_cella4~COUT at LC_X47_Y20_N5

--operation mode is arithmetic

RE1L15_cout_0 = !RE1L11 & (RE1_safe_q[4] $ !BB1_fifo_wr);

RE1L15 = CARRY(RE1L15_cout_0);

--RE1L16 is std_1c20:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_w:the_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_jf21:auto_generated|a_dpfifo_ml21:dpfifo|a_fefifo_7cf:fifo_state|cntr_9c7:count_usedw|counter_cella4~COUTCOUT1_66 at LC_X47_Y20_N5

--operation mode is arithmetic

RE1L16_cout_1 = !RE1L11 & (RE1_safe_q[4] $ !BB1_fifo_wr);

RE1L16 = CARRY(RE1L16_cout_1);

--RE1_safe_q[3] is std_1c20:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_w:the_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_jf21:auto_generated|a_dpfifo_ml21:dpfifo|a_fefifo_7cf:fifo_state|cntr_9c7:count_usedw|safe_q[3] at LC_X47_Y20_N4

--operation mode is arithmetic

RE1_safe_q[3]_lut_out = RE1_safe_q[3] $ RE1L8;

RE1_safe_q[3] = DFFEAS(RE1_safe_q[3]_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , NE1L1, , , , );

--RE1L11 is std_1c20:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_w:the_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_jf21:auto_generated|a_dpfifo_ml21:dpfifo|a_fefifo_7cf:fifo_state|cntr_9c7:count_usedw|counter_cella3~COUT at LC_X47_Y20_N4

--operation mode is arithmetic

RE1L11 = RE1L12;

--RE1_safe_q[2] is std_1c20:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_w:the_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_jf21:auto_generated|a_dpfifo_ml21:dpfifo|a_fefifo_7cf:fifo_state|cntr_9c7:count_usedw|safe_q[2] at LC_X47_Y20_N3

--operation mode is arithmetic

RE1_safe_q[2]_lut_out = RE1_safe_q[2] $ !RE1L5;

RE1_safe_q[2] = DFFEAS(RE1_safe_q[2]_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , NE1L1, , , , );

--RE1L8 is std_1c20:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_w:the_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_jf21:auto_generated|a_dpfifo_ml21:dpfifo|a_fefifo_7cf:fifo_state|cntr_9c7:count_usedw|counter_cella2~COUT at LC_X47_Y20_N3

--operation mode is arithmetic

RE1L8_cout_0 = !RE1L5 & (BB1_fifo_wr $ !RE1_safe_q[2]);

RE1L8 = CARRY(RE1L8_cout_0);

--RE1L9 is std_1c20:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_w:the_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_jf21:auto_generated|a_dpfifo_ml21:dpfifo|a_fefifo_7cf:fifo_state|cntr_9c7:count_usedw|counter_cella2~COUTCOUT1_62 at LC_X47_Y20_N3

--operation mode is arithmetic

RE1L9_cout_1 = !RE1L6 & (BB1_fifo_wr $ !RE1_safe_q[2]);

RE1L9 = CARRY(RE1L9_cout_1);

--RE1_safe_q[1] is std_1c20:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_w:the_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_jf21:auto_generated|a_dpfifo_ml21:dpfifo|a_fefifo_7cf:fifo_state|cntr_9c7:count_usedw|safe_q[1] at LC_X47_Y20_N2

--operation mode is arithmetic

RE1_safe_q[1]_lut_out = RE1_safe_q[1] $ (RE1L2);

RE1_safe_q[1] = DFFEAS(RE1_safe_q[1]_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , NE1L1, , , , );

--RE1L5 is std_1c20:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_w:the_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_jf21:auto_generated|a_dpfifo_ml21:dpfifo|a_fefifo_7cf:fifo_state|cntr_9c7:count_usedw|counter_cella1~COUT at LC_X47_Y20_N2

--operation mode is arithmetic

RE1L5_cout_0 = RE1_safe_q[1] $ BB1_fifo_wr # !RE1L2;

RE1L5 = CARRY(RE1L5_cout_0);

--RE1L6 is std_1c20:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_w:the_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_jf21:auto_generated|a_dpfifo_ml21:dpfifo|a_fefifo_7cf:fifo_state|cntr_9c7:count_usedw|counter_cella1~COUTCOUT1_64 at LC_X47_Y20_N2

--operation mode is arithmetic

RE1L6_cout_1 = RE1_safe_q[1] $ BB1_fifo_wr # !RE1L3;

RE1L6 = CARRY(RE1L6_cout_1);

--BB1L65 is std_1c20:inst|jtag_uart:the_jtag_uart|LessThan0~96 at LC_X46_Y20_N9

--operation mode is normal

BB1L65 = RE1_safe_q[3] & (RE1_safe_q[0] # RE1_safe_q[1] # RE1_safe_q[2]);

--BB1L3 is std_1c20:inst|jtag_uart:the_jtag_uart|Add0~180 at LC_X47_Y21_N6

--operation mode is arithmetic

BB1L3_carry_eqn = (!BB1L16 & BB1L20) # (BB1L16 & BB1L21);

BB1L3 = NE2_b_full $ (BB1L3_carry_eqn);

--BB1L4 is std_1c20:inst|jtag_uart:the_jtag_uart|Add0~181 at LC_X47_Y21_N6

--operation mode is arithmetic

BB1L4_cout_0 = NE2_b_full & (!BB1L20);

BB1L4 = CARRY(BB1L4_cout_0);

--BB1L5 is std_1c20:inst|jtag_uart:the_jtag_uart|Add0~181COUT1_447 at LC_X47_Y21_N6

--operation mode is arithmetic

BB1L5_cout_1 = NE2_b_full & (!BB1L21);

BB1L5 = CARRY(BB1L5_cout_1);

--BB1L6 is std_1c20:inst|jtag_uart:the_jtag_uart|Add0~182 at LC_X47_Y21_N3

--operation mode is arithmetic

BB1L6 = RE2_safe_q[3] $ BB1L13;

--BB1L7 is std_1c20:inst|jtag_uart:the_jtag_uart|Add0~183 at LC_X47_Y21_N3

--operation mode is arithmetic

BB1L7_cout_0 = !RE2_safe_q[3] & !BB1L13;

BB1L7 = CARRY(BB1L7_cout_0);

--BB1L8 is std_1c20:inst|jtag_uart:the_jtag_uart|Add0~183COUT1_443 at LC_X47_Y21_N3

--operation mode is arithmetic

BB1L8_cout_1 = !RE2_safe_q[3] & !BB1L14;

BB1L8 = CARRY(BB1L8_cout_1);

--BB1L10 is std_1c20:inst|jtag_uart:the_jtag_uart|Add0~185 at LC_X47_Y21_N1

--operation mode is arithmetic

BB1L10_cout_0 = !RE2_safe_q[1] & !RE2_safe_q[0];

BB1L10 = CARRY(BB1L10_cout_0);

--BB1L11 is std_1c20:inst|jtag_uart:the_jtag_uart|Add0~185COUT1_439 at LC_X47_Y21_N1

--operation mode is arithmetic

BB1L11_cout_1 = !RE2_safe_q[1] & !RE2_safe_q[0];

BB1L11 = CARRY(BB1L11_cout_1);

--BB1L12 is std_1c20:inst|jtag_uart:the_jtag_uart|Add0~186 at LC_X47_Y21_N2

--operation mode is arithmetic

BB1L12 = RE2_safe_q[2] $ !BB1L10;

--BB1L13 is std_1c20:inst|jtag_uart:the_jtag_uart|Add0~187 at LC_X47_Y21_N2

--operation mode is arithmetic

BB1L13_cout_0 = RE2_safe_q[2] # !BB1L10;

BB1L13 = CARRY(BB1L13_cout_0);

--BB1L14 is std_1c20:inst|jtag_uart:the_jtag_uart|Add0~187COUT1_441 at LC_X47_Y21_N2

--operation mode is arithmetic

BB1L14_cout_1 = RE2_safe_q[2] # !BB1L11;

BB1L14 = CARRY(BB1L14_cout_1);

--BB1L66 is std_1c20:inst|jtag_uart:the_jtag_uart|LessThan1~117 at LC_X47_Y21_N0

--operation mode is normal

BB1L66 = BB1L6 & (BB1L12 # RE2_safe_q[0] # RE2_safe_q[1]);

--BB1L15 is std_1c20:inst|jtag_uart:the_jtag_uart|Add0~188 at LC_X47_Y21_N4

--operation mode is arithmetic

BB1L15 = RE2_safe_q[4] $ (!BB1L7);

--BB1L16 is std_1c20:inst|jtag_uart:the_jtag_uart|Add0~189 at LC_X47_Y21_N4

--operation mode is arithmetic

BB1L16 = BB1L17;

--BB1L19 is std_1c20:inst|jtag_uart:the_jtag_uart|Add0~190 at LC_X47_Y21_N5

--operation mode is arithmetic

BB1L19_carry_eqn = (!BB1L16 & GND) # (BB1L16 & VCC);

BB1L19 = RE2_safe_q[5] $ BB1L19_carry_eqn;

--BB1L20 is std_1c20:inst|jtag_uart:the_jtag_uart|Add0~191 at LC_X47_Y21_N5

--operation mode is arithmetic

BB1L20_cout_0 = !RE2_safe_q[5] & !BB1L16;

BB1L20 = CARRY(BB1L20_cout_0);

--BB1L21 is std_1c20:inst|jtag_uart:the_jtag_uart|Add0~191COUT1_445 at LC_X47_Y21_N5

--operation mode is arithmetic

BB1L21_cout_1 = !RE2_safe_q[5] & !BB1L16;

BB1L21 = CARRY(BB1L21_cout_1);

--BB1L67 is std_1c20:inst|jtag_uart:the_jtag_uart|LessThan1~118 at LC_X47_Y21_N8

--operation mode is normal

BB1L67 = BB1L19 # BB1L15;

--BB1L22 is std_1c20:inst|jtag_uart:the_jtag_uart|Add0~192 at LC_X47_Y21_N7

--operation mode is normal

BB1L22_carry_eqn = (!BB1L16 & BB1L4) # (BB1L16 & BB1L5);

BB1L22 = !BB1L22_carry_eqn;

--GE1L39Q is std_1c20:inst|jtag_uart:the_jtag_uart|alt_jtag_atlantic:jtag_uart_alt_jtag_atlantic|t_pause~reg0 at LC_X52_Y21_N7

--operation mode is normal

GE1L39Q = AMPP_FUNCTION(QC2__clk0, GE1L2, GE1L38, GE1_jupdate1, GE1_jupdate2, F1_data_out);

--RB1_internal_counter[0] is std_1c20:inst|sys_clk_timer:the_sys_clk_timer|internal_counter[0] at LC_X52_Y27_N4

--operation mode is arithmetic

RB1_internal_counter[0]_lut_out = !RB1_internal_counter[0];

RB1_internal_counter[0] = DFFEAS(RB1_internal_counter[0]_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , RB1L182, RB1_period_l_register[0], , , RB1L183);

--RB1L60 is std_1c20:inst|sys_clk_timer:the_sys_clk_timer|internal_counter[0]~7696 at LC_X52_Y27_N4

--operation mode is arithmetic

RB1L60 = CARRY(!RB1_internal_counter[0]);

--RB1_internal_counter[1] is std_1c20:inst|sys_clk_timer:the_sys_clk_timer|internal_counter[1] at LC_X52_Y27_N5

--operation mode is arithmetic

RB1_internal_counter[1]_carry_eqn = RB1L60;

RB1_internal_counter[1]_lut_out = RB1_internal_counter[1] $ !RB1_internal_counter[1]_carry_eqn;

RB1_internal_counter[1] = DFFEAS(RB1_internal_counter[1]_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , RB1L182, RB1_period_l_register[1], , , RB1L183);

--RB1L62 is std_1c20:inst|sys_clk_timer:the_sys_clk_timer|internal_counter[1]~7697 at LC_X52_Y27_N5

--operation mode is arithmetic

RB1L62_cout_0 = RB1_internal_counter[1] & !RB1L60;

RB1L62 = CARRY(RB1L62_cout_0);

--RB1L63 is std_1c20:inst|sys_clk_timer:the_sys_clk_timer|internal_counter[1]~7697COUT1_8906 at LC_X52_Y27_N5

--operation mode is arithmetic

RB1L63_cout_1 = RB1_internal_counter[1] & !RB1L60;

RB1L63 = CARRY(RB1L63_cout_1);

--RB1_internal_counter[2] is std_1c20:inst|sys_clk_timer:the_sys_clk_timer|internal_counter[2] at LC_X52_Y27_N6

--operation mode is arithmetic

RB1_internal_counter[2]_carry_eqn = (!RB1L60 & RB1L62) # (RB1L60 & RB1L63);

RB1_internal_counter[2]_lut_out = RB1_internal_counter[2] $ (RB1_internal_counter[2]_carry_eqn);

RB1_internal_counter[2] = DFFEAS(RB1_internal_counter[2]_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , RB1L182, RB1_period_l_register[2], , , RB1L183);

--RB1L65 is std_1c20:inst|sys_clk_timer:the_sys_clk_timer|internal_counter[2]~7698 at LC_X52_Y27_N6

--operation mode is arithmetic

RB1L65_cout_0 = !RB1L62 # !RB1_internal_counter[2];

RB1L65 = CARRY(RB1L65_cout_0);

--RB1L66 is std_1c20:inst|sys_clk_timer:the_sys_clk_timer|internal_counter[2]~7698COUT1_8908 at LC_X52_Y27_N6

--operation mode is arithmetic

RB1L66_cout_1 = !RB1L63 # !RB1_internal_counter[2];

RB1L66 = CARRY(RB1L66_cout_1);

--RB1_internal_counter[3] is std_1c20:inst|sys_clk_timer:the_sys_clk_timer|internal_counter[3] at LC_X52_Y27_N7

--operation mode is arithmetic

RB1_internal_counter[3]_carry_eqn = (!RB1L60 & RB1L65) # (RB1L60 & RB1L66);

RB1_internal_counter[3]_lut_out = RB1_internal_counter[3] $ (!RB1_internal_counter[3]_carry_eqn);

RB1_internal_counter[3] = DFFEAS(RB1_internal_counter[3]_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , RB1L182, RB1_period_l_register[3], , , RB1L183);

--RB1L68 is std_1c20:inst|sys_clk_timer:the_sys_clk_timer|internal_counter[3]~7699 at LC_X52_Y27_N7

--operation mode is arithmetic

RB1L68_cout_0 = RB1_internal_counter[3] & (!RB1L65);

RB1L68 = CARRY(RB1L68_cout_0);

--RB1L69 is std_1c20:inst|sys_clk_timer:the_sys_clk_timer|internal_counter[3]~7699COUT1_8910 at LC_X52_Y27_N7

--operation mode is arithmetic

RB1L69_cout_1 = RB1_internal_counter[3] & (!RB1L66);

RB1L69 = CARRY(RB1L69_cout_1);

--RB1L47 is std_1c20:inst|sys_clk_timer:the_sys_clk_timer|Equal0~370 at LC_X52_Y27_N3

--operation mode is normal

RB1L47 = RB1_internal_counter[2] & RB1_internal_counter[0] & RB1_internal_counter[3] & RB1_internal_counter[1];

--RB1_internal_counter[4] is std_1c20:inst|sys_clk_timer:the_sys_clk_timer|internal_counter[4] at LC_X52_Y27_N8

--operation mode is arithmetic

RB1_internal_counter[4]_carry_eqn = (!RB1L60 & RB1L68) # (RB1L60 & RB1L69);

RB1_internal_counter[4]_lut_out = RB1_internal_counter[4] $ RB1_internal_counter[4]_carry_eqn;

RB1_internal_counter[4] = DFFEAS(RB1_internal_counter[4]_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , RB1L182, RB1_period_l_register[4], , , RB1L183);

--RB1L71 is std_1c20:inst|sys_clk_timer:the_sys_clk_timer|internal_counter[4]~7700 at LC_X52_Y27_N8

--operation mode is arithmetic

RB1L71_cout_0 = !RB1L68 # !RB1_internal_counter[4];

RB1L71 = CARRY(RB1L71_cout_0);

--RB1L72 is std_1c20:inst|sys_clk_timer:the_sys_clk_timer|internal_counter[4]~7700COUT1_8912 at LC_X52_Y27_N8

--operation mode is arithmetic

RB1L72_cout_1 = !RB1L69 # !RB1_internal_counter[4];

RB1L72 = CARRY(RB1L72_cout_1);

--RB1_internal_counter[5] is std_1c20:inst|sys_clk_timer:the_sys_clk_timer|internal_counter[5] at LC_X52_Y27_N9

--operation mode is arithmetic

RB1_internal_counter[5]_carry_eqn = (!RB1L60 & RB1L71) # (RB1L60 & RB1L72);

RB1_internal_counter[5]_lut_out = RB1_internal_counter[5] $ (!RB1_internal_counter[5]_carry_eqn);

RB1_internal_counter[5] = DFFEAS(RB1_internal_counter[5]_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , RB1L182, RB1_period_l_register[5], , , RB1L183);

--RB1L74 is std_1c20:inst|sys_clk_timer:the_sys_clk_timer|internal_counter[5]~7701 at LC_X52_Y27_N9

--operation mode is arithmetic

RB1L74 = CARRY(!RB1_internal_counter[5] & (!RB1L72));

--RB1_internal_counter[6] is std_1c20:inst|sys_clk_timer:the_sys_clk_timer|internal_counter[6] at LC_X52_Y26_N0

--operation mode is arithmetic

RB1_internal_counter[6]_carry_eqn = RB1L74;

RB1_internal_counter[6]_lut_out = RB1_internal_counter[6] $ RB1_internal_counter[6]_carry_eqn;

RB1_internal_counter[6] = DFFEAS(RB1_internal_counter[6]_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , RB1L182, RB1_period_l_register[6], , , RB1L183);

--RB1L76 is std_1c20:inst|sys_clk_timer:the_sys_clk_timer|internal_counter[6]~7702 at LC_X52_Y26_N0

--operation mode is arithmetic

RB1L76_cout_0 = RB1_internal_counter[6] # !RB1L74;

RB1L76 = CARRY(RB1L76_cout_0);

--RB1L77 is std_1c20:inst|sys_clk_timer:the_sys_clk_timer|internal_counter[6]~7702COUT1_8914 at LC_X52_Y26_N0

--operation mode is arithmetic

RB1L77_cout_1 = RB1_internal_counter[6] # !RB1L74;

RB1L77 = CARRY(RB1L77_cout_1);

--RB1_internal_counter[7] is std_1c20:inst|sys_clk_timer:the_sys_clk_timer|internal_counter[7] at LC_X52_Y26_N1

--operation mode is arithmetic

RB1_internal_counter[7]_carry_eqn = (!RB1L74 & RB1L76) # (RB1L74 & RB1L77);

RB1_internal_counter[7]_lut_out = RB1_internal_counter[7] $ (!RB1_internal_counter[7]_carry_eqn);

RB1_internal_counter[7] = DFFEAS(RB1_internal_counter[7]_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , RB1L182, RB1_period_l_register[7], , , RB1L183);

--RB1L79 is std_1c20:inst|sys_clk_timer:the_sys_clk_timer|internal_counter[7]~7703 at LC_X52_Y26_N1

--operation mode is arithmetic

RB1L79_cout_0 = !RB1_internal_counter[7] & (!RB1L76);

RB1L79 = CARRY(RB1L79_cout_0);

--RB1L80 is std_1c20:inst|sys_clk_timer:the_sys_clk_timer|internal_counter[7]~7703COUT1_8916 at LC_X52_Y26_N1

--operation mode is arithmetic

RB1L80_cout_1 = !RB1_internal_counter[7] & (!RB1L77);

RB1L80 = CARRY(RB1L80_cout_1);

--RB1L48 is std_1c20:inst|sys_clk_timer:the_sys_clk_timer|Equal0~371 at LC_X52_Y28_N0

--operation mode is normal

RB1L48 = !RB1_internal_counter[6] & !RB1_internal_counter[7] & !RB1_internal_counter[5] & RB1_internal_counter[4];

--RB1_internal_counter[8] is std_1c20:inst|sys_clk_timer:the_sys_clk_timer|internal_counter[8] at LC_X52_Y26_N2

--operation mode is arithmetic

RB1_internal_counter[8]_carry_eqn = (!RB1L74 & RB1L79) # (RB1L74 & RB1L80);

RB1_internal_counter[8]_lut_out = RB1_internal_counter[8] $ (RB1_internal_counter[8]_carry_eqn);

RB1_internal_counter[8] = DFFEAS(RB1_internal_counter[8]_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , RB1L182, RB1_period_l_register[8], , , RB1L183);

--RB1L82 is std_1c20:inst|sys_clk_timer:the_sys_clk_timer|internal_counter[8]~7704 at LC_X52_Y26_N2

--operation mode is arithmetic

RB1L82_cout_0 = !RB1L79 # !RB1_internal_counter[8];

RB1L82 = CARRY(RB1L82_cout_0);

--RB1L83 is std_1c20:inst|sys_clk_timer:the_sys_clk_timer|internal_counter[8]~7704COUT1_8918 at LC_X52_Y26_N2

--operation mode is arithmetic

RB1L83_cout_1 = !RB1L80 # !RB1_internal_counter[8];

RB1L83 = CARRY(RB1L83_cout_1);

--RB1_internal_counter[9] is std_1c20:inst|sys_clk_timer:the_sys_clk_timer|internal_counter[9] at LC_X52_Y26_N3

--operation mode is arithmetic

RB1_internal_counter[9]_carry_eqn = (!RB1L74 & RB1L82) # (RB1L74 & RB1L83);

RB1_internal_counter[9]_lut_out = RB1_internal_counter[9] $ !RB1_internal_counter[9]_carry_eqn;

RB1_internal_counter[9] = DFFEAS(RB1_internal_counter[9]_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , RB1L182, RB1_period_l_register[9], , , RB1L183);

--RB1L85 is std_1c20:inst|sys_clk_timer:the_sys_clk_timer|internal_counter[9]~7705 at LC_X52_Y26_N3

--operation mode is arithmetic

RB1L85_cout_0 = !RB1_internal_counter[9] & !RB1L82;

RB1L85 = CARRY(RB1L85_cout_0);

--RB1L86 is std_1c20:inst|sys_clk_timer:the_sys_clk_timer|internal_counter[9]~7705COUT1_8920 at LC_X52_Y26_N3

--operation mode is arithmetic

RB1L86_cout_1 = !RB1_internal_counter[9] & !RB1L83;

RB1L86 = CARRY(RB1L86_cout_1);

--RB1_internal_counter[10] is std_1c20:inst|sys_clk_timer:the_sys_clk_timer|internal_counter[10] at LC_X52_Y26_N4

--operation mode is arithmetic

RB1_internal_counter[10]_carry_eqn = (!RB1L74 & RB1L85) # (RB1L74 & RB1L86);

RB1_internal_counter[10]_lut_out = RB1_internal_counter[10] $ RB1_internal_counter[10]_carry_eqn;

RB1_internal_counter[10] = DFFEAS(RB1_internal_counter[10]_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , RB1L182, RB1_period_l_register[10], , , RB1L183);

--RB1L88 is std_1c20:inst|sys_clk_timer:the_sys_clk_timer|internal_counter[10]~7706 at LC_X52_Y26_N4

--operation mode is arithmetic

RB1L88 = CARRY(RB1_internal_counter[10] # !RB1L86);

--RB1_internal_counter[11] is std_1c20:inst|sys_clk_timer:the_sys_clk_timer|internal_counter[11] at LC_X52_Y26_N5

--operation mode is arithmetic

RB1_internal_counter[11]_carry_eqn = RB1L88;

RB1_internal_counter[11]_lut_out = RB1_internal_counter[11] $ !RB1_internal_counter[11]_carry_eqn;

RB1_internal_counter[11] = DFFEAS(RB1_internal_counter[11]_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , RB1L182, RB1_period_l_register[11], , , RB1L183);

--RB1L90 is std_1c20:inst|sys_clk_timer:the_sys_clk_timer|internal_counter[11]~7707 at LC_X52_Y26_N5

--operation mode is arithmetic

RB1L90_cout_0 = !RB1_internal_counter[11] & !RB1L88;

RB1L90 = CARRY(RB1L90_cout_0);

--RB1L91 is std_1c20:inst|sys_clk_timer:the_sys_clk_timer|internal_counter[11]~7707COUT1_8922 at LC_X52_Y26_N5

--operation mode is arithmetic

RB1L91_cout_1 = !RB1_internal_counter[11] & !RB1L88;

RB1L91 = CARRY(RB1L91_cout_1);

--RB1L49 is std_1c20:inst|sys_clk_timer:the_sys_clk_timer|Equal0~372 at LC_X53_Y26_N2

--operation mode is normal

RB1L49 = !RB1_internal_counter[9] & !RB1_internal_counter[10] & !RB1_internal_counter[11] & RB1_internal_counter[8];

--RB1_internal_counter[13] is std_1c20:inst|sys_clk_timer:the_sys_clk_timer|internal_counter[13] at LC_X52_Y26_N7

--operation mode is arithmetic

RB1_internal_counter[13]_carry_eqn = (!RB1L88 & RB1L93) # (RB1L88 & RB1L94);

RB1_internal_counter[13]_lut_out = RB1_internal_counter[13] $ (!RB1_internal_counter[13]_carry_eqn);

RB1_internal_counter[13] = DFFEAS(RB1_internal_counter[13]_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , RB1L182, RB1_period_l_register[13], , , RB1L183);

--RB1L96 is std_1c20:inst|sys_clk_timer:the_sys_clk_timer|internal_counter[13]~7708 at LC_X52_Y26_N7

--operation mode is arithmetic

RB1L96_cout_0 = RB1_internal_counter[13] & (!RB1L93);

RB1L96 = CARRY(RB1L96_cout_0);

--RB1L97 is std_1c20:inst|sys_clk_timer:the_sys_clk_timer|internal_counter[13]~7708COUT1_8926 at LC_X52_Y26_N7

--operation mode is arithmetic

RB1L97_cout_1 = RB1_internal_counter[13] & (!RB1L94);

RB1L97 = CARRY(RB1L97_cout_1);

--RB1_internal_counter[15] is std_1c20:inst|sys_clk_timer:the_sys_clk_timer|internal_counter[15] at LC_X52_Y26_N9

--operation mode is arithmetic

RB1_internal_counter[15]_carry_eqn = (!RB1L88 & RB1L99) # (RB1L88 & RB1L100);

RB1_internal_counter[15]_lut_out = RB1_internal_counter[15] $ (!RB1_internal_counter[15]_carry_eqn);

RB1_internal_counter[15] = DFFEAS(RB1_internal_counter[15]_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , RB1L182, RB1_period_l_register[15], , , RB1L183);

--RB1L102 is std_1c20:inst|sys_clk_timer:the_sys_clk_timer|internal_counter[15]~7709 at LC_X52_Y26_N9

--operation mode is arithmetic

RB1L102 = CARRY(RB1_internal_counter[15] & (!RB1L100));

--RB1_internal_counter[12] is std_1c20:inst|sys_clk_timer:the_sys_clk_timer|internal_counter[12] at LC_X52_Y26_N6

--operation mode is arithmetic

RB1_internal_counter[12]_carry_eqn = (!RB1L88 & RB1L90) # (RB1L88 & RB1L91);

RB1_internal_counter[12]_lut_out = RB1_internal_counter[12] $ (RB1_internal_counter[12]_carry_eqn);

RB1_internal_counter[12] = DFFEAS(RB1_internal_counter[12]_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , RB1L182, RB1_period_l_register[12], , , RB1L183);

--RB1L93 is std_1c20:inst|sys_clk_timer:the_sys_clk_timer|internal_counter[12]~7710 at LC_X52_Y26_N6

--operation mode is arithmetic

RB1L93_cout_0 = RB1_internal_counter[12] # !RB1L90;

RB1L93 = CARRY(RB1L93_cout_0);

--RB1L94 is std_1c20:inst|sys_clk_timer:the_sys_clk_timer|internal_counter[12]~7710COUT1_8924 at LC_X52_Y26_N6

--operation mode is arithmetic

RB1L94_cout_1 = RB1_internal_counter[12] # !RB1L91;

RB1L94 = CARRY(RB1L94_cout_1);

--RB1_internal_counter[14] is std_1c20:inst|sys_clk_timer:the_sys_clk_timer|internal_counter[14] at LC_X52_Y26_N8

--operation mode is arithmetic

RB1_internal_counter[14]_carry_eqn = (!RB1L88 & RB1L96) # (RB1L88 & RB1L97);

RB1_internal_counter[14]_lut_out = RB1_internal_counter[14] $ RB1_internal_counter[14]_carry_eqn;

RB1_internal_counter[14] = DFFEAS(RB1_internal_counter[14]_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , RB1L182, RB1_period_l_register[14], , , RB1L183);

--RB1L99 is std_1c20:inst|sys_clk_timer:the_sys_clk_timer|internal_counter[14]~7711 at LC_X52_Y26_N8

--operation mode is arithmetic

RB1L99_cout_0 = RB1_internal_counter[14] # !RB1L96;

RB1L99 = CARRY(RB1L99_cout_0);

--RB1L100 is std_1c20:inst|sys_clk_timer:the_sys_clk_timer|internal_counter[14]~7711COUT1_8928 at LC_X52_Y26_N8

--operation mode is arithmetic

RB1L100_cout_1 = RB1_internal_counter[14] # !RB1L97;

RB1L100 = CARRY(RB1L100_cout_1);

--RB1L50 is std_1c20:inst|sys_clk_timer:the_sys_clk_timer|Equal0~373 at LC_X51_Y24_N6

--operation mode is normal

RB1L50 = !RB1_internal_counter[12] & RB1_internal_counter[13] & RB1_internal_counter[15] & !RB1_internal_counter[14];

--RB1L51 is std_1c20:inst|sys_clk_timer:the_sys_clk_timer|Equal0~374 at LC_X52_Y27_N2

--operation mode is normal

RB1L51 = RB1L50 & RB1L49 & RB1L48 & RB1L47;

--RB1_internal_counter[16] is std_1c20:inst|sys_clk_timer:the_sys_clk_timer|internal_counter[16] at LC_X52_Y25_N0

--operation mode is arithmetic

RB1_internal_counter[16]_carry_eqn = RB1L102;

RB1_internal_counter[16]_lut_out = RB1_internal_counter[16] $ RB1_internal_counter[16]_carry_eqn;

RB1_internal_counter[16] = DFFEAS(RB1_internal_counter[16]_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , RB1L182, RB1_period_h_register[0], , , RB1L183);

--RB1L104 is std_1c20:inst|sys_clk_timer:the_sys_clk_timer|internal_counter[16]~7712 at LC_X52_Y25_N0

--operation mode is arithmetic

RB1L104_cout_0 = !RB1L102 # !RB1_internal_counter[16];

RB1L104 = CARRY(RB1L104_cout_0);

--RB1L105 is std_1c20:inst|sys_clk_timer:the_sys_clk_timer|internal_counter[16]~7712COUT1_8930 at LC_X52_Y25_N0

--operation mode is arithmetic

RB1L105_cout_1 = !RB1L102 # !RB1_internal_counter[16];

RB1L105 = CARRY(RB1L105_cout_1);

--RB1_internal_counter[17] is std_1c20:inst|sys_clk_timer:the_sys_clk_timer|internal_counter[17] at LC_X52_Y25_N1

--operation mode is arithmetic

RB1_internal_counter[17]_carry_eqn = (!RB1L102 & RB1L104) # (RB1L102 & RB1L105);

RB1_internal_counter[17]_lut_out = RB1_internal_counter[17] $ (!RB1_internal_counter[17]_carry_eqn);

RB1_internal_counter[17] = DFFEAS(RB1_internal_counter[17]_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , RB1L182, RB1_period_h_register[1], , , RB1L183);

--RB1L107 is std_1c20:inst|sys_clk_timer:the_sys_clk_timer|internal_counter[17]~7713 at LC_X52_Y25_N1

--operation mode is arithmetic

RB1L107_cout_0 = RB1_internal_counter[17] & (!RB1L104);

RB1L107 = CARRY(RB1L107_cout_0);

--RB1L108 is std_1c20:inst|sys_clk_timer:the_sys_clk_timer|internal_counter[17]~7713COUT1_8932 at LC_X52_Y25_N1

--operation mode is arithmetic

RB1L108_cout_1 = RB1_internal_counter[17] & (!RB1L105);

RB1L108 = CARRY(RB1L108_cout_1);

--RB1_internal_counter[18] is std_1c20:inst|sys_clk_timer:the_sys_clk_timer|internal_counter[18] at LC_X52_Y25_N2

--operation mode is arithmetic

RB1_internal_counter[18]_carry_eqn = (!RB1L102 & RB1L107) # (RB1L102 & RB1L108);

RB1_internal_counter[18]_lut_out = RB1_internal_counter[18] $ (RB1_internal_counter[18]_carry_eqn);

RB1_internal_counter[18] = DFFEAS(RB1_internal_counter[18]_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , RB1L182, RB1_period_h_register[2], , , RB1L183);

--RB1L110 is std_1c20:inst|sys_clk_timer:the_sys_clk_timer|internal_counter[18]~7714 at LC_X52_Y25_N2

--operation mode is arithmetic

RB1L110_cout_0 = !RB1L107 # !RB1_internal_counter[18];

RB1L110 = CARRY(RB1L110_cout_0);

--RB1L111 is std_1c20:inst|sys_clk_timer:the_sys_clk_timer|internal_counter[18]~7714COUT1_8934 at LC_X52_Y25_N2

--operation mode is arithmetic

RB1L111_cout_1 = !RB1L108 # !RB1_internal_counter[18];

RB1L111 = CARRY(RB1L111_cout_1);

--RB1_internal_counter[19] is std_1c20:inst|sys_clk_timer:the_sys_clk_timer|internal_counter[19] at LC_X52_Y25_N3

--operation mode is arithmetic

RB1_internal_counter[19]_carry_eqn = (!RB1L102 & RB1L110) # (RB1L102 & RB1L111);

RB1_internal_counter[19]_lut_out = RB1_internal_counter[19] $ !RB1_internal_counter[19]_carry_eqn;

RB1_internal_counter[19] = DFFEAS(RB1_internal_counter[19]_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , RB1L182, RB1_period_h_register[3], , , RB1L183);

--RB1L113 is std_1c20:inst|sys_clk_timer:the_sys_clk_timer|internal_counter[19]~7715 at LC_X52_Y25_N3

--operation mode is arithmetic

RB1L113_cout_0 = !RB1_internal_counter[19] & !RB1L110;

RB1L113 = CARRY(RB1L113_cout_0);

--RB1L114 is std_1c20:inst|sys_clk_timer:the_sys_clk_timer|internal_counter[19]~7715COUT1_8936 at LC_X52_Y25_N3

--operation mode is arithmetic

RB1L114_cout_1 = !RB1_internal_counter[19] & !RB1L111;

RB1L114 = CARRY(RB1L114_cout_1);

--RB1L52 is std_1c20:inst|sys_clk_timer:the_sys_clk_timer|Equal0~375 at LC_X52_Y23_N4

--operation mode is normal

RB1L52 = RB1_internal_counter[17] & !RB1_internal_counter[19] & RB1_internal_counter[16] & RB1_internal_counter[18];

--RB1_internal_counter[20] is std_1c20:inst|sys_clk_timer:the_sys_clk_timer|internal_counter[20] at LC_X52_Y25_N4

--operation mode is arithmetic

RB1_internal_counter[20]_carry_eqn = (!RB1L102 & RB1L113) # (RB1L102 & RB1L114);

RB1_internal_counter[20]_lut_out = RB1_internal_counter[20] $ RB1_internal_counter[20]_carry_eqn;

RB1_internal_counter[20] = DFFEAS(RB1_internal_counter[20]_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , RB1L182, RB1_period_h_register[4], , , RB1L183);

--RB1L116 is std_1c20:inst|sys_clk_timer:the_sys_clk_timer|internal_counter[20]~7716 at LC_X52_Y25_N4

--operation mode is arithmetic

RB1L116 = CARRY(RB1_internal_counter[20] # !RB1L114);

--RB1_internal_counter[21] is std_1c20:inst|sys_clk_timer:the_sys_clk_timer|internal_counter[21] at LC_X52_Y25_N5

--operation mode is arithmetic

RB1_internal_counter[21]_carry_eqn = RB1L116;

RB1_internal_counter[21]_lut_out = RB1_internal_counter[21] $ !RB1_internal_counter[21]_carry_eqn;

RB1_internal_counter[21] = DFFEAS(RB1_internal_counter[21]_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , RB1L182, RB1_period_h_register[5], , , RB1L183);

--RB1L118 is std_1c20:inst|sys_clk_timer:the_sys_clk_timer|internal_counter[21]~7717 at LC_X52_Y25_N5

--operation mode is arithmetic

RB1L118_cout_0 = !RB1_internal_counter[21] & !RB1L116;

RB1L118 = CARRY(RB1L118_cout_0);

--RB1L119 is std_1c20:inst|sys_clk_timer:the_sys_clk_timer|internal_counter[21]~7717COUT1_8938 at LC_X52_Y25_N5

--operation mode is arithmetic

RB1L119_cout_1 = !RB1_internal_counter[21] & !RB1L116;

RB1L119 = CARRY(RB1L119_cout_1);

--RB1_internal_counter[22] is std_1c20:inst|sys_clk_timer:the_sys_clk_timer|internal_counter[22] at LC_X52_Y25_N6

--operation mode is arithmetic

RB1_internal_counter[22]_carry_eqn = (!RB1L116 & RB1L118) # (RB1L116 & RB1L119);

RB1_internal_counter[22]_lut_out = RB1_internal_counter[22] $ (RB1_internal_counter[22]_carry_eqn);

RB1_internal_counter[22] = DFFEAS(RB1_internal_counter[22]_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , RB1L182, RB1_period_h_register[6], , , RB1L183);

--RB1L121 is std_1c20:inst|sys_clk_timer:the_sys_clk_timer|internal_counter[22]~7718 at LC_X52_Y25_N6

--operation mode is arithmetic

RB1L121_cout_0 = RB1_internal_counter[22] # !RB1L118;

RB1L121 = CARRY(RB1L121_cout_0);

--RB1L122 is std_1c20:inst|sys_clk_timer:the_sys_clk_timer|internal_counter[22]~7718COUT1_8940 at LC_X52_Y25_N6

--operation mode is arithmetic

RB1L122_cout_1 = RB1_internal_counter[22] # !RB1L119;

RB1L122 = CARRY(RB1L122_cout_1);

--RB1_internal_counter[23] is std_1c20:inst|sys_clk_timer:the_sys_clk_timer|internal_counter[23] at LC_X52_Y25_N7

--operation mode is arithmetic

RB1_internal_counter[23]_carry_eqn = (!RB1L116 & RB1L121) # (RB1L116 & RB1L122);

RB1_internal_counter[23]_lut_out = RB1_internal_counter[23] $ (!RB1_internal_counter[23]_carry_eqn);

RB1_internal_counter[23] = DFFEAS(RB1_internal_counter[23]_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , RB1L182, RB1_period_h_register[7], , , RB1L183);

--RB1L124 is std_1c20:inst|sys_clk_timer:the_sys_clk_timer|internal_counter[23]~7719 at LC_X52_Y25_N7

--operation mode is arithmetic

RB1L124_cout_0 = !RB1_internal_counter[23] & (!RB1L121);

RB1L124 = CARRY(RB1L124_cout_0);

--RB1L125 is std_1c20:inst|sys_clk_timer:the_sys_clk_timer|internal_counter[23]~7719COUT1_8942 at LC_X52_Y25_N7

--operation mode is arithmetic

RB1L125_cout_1 = !RB1_internal_counter[23] & (!RB1L122);

RB1L125 = CARRY(RB1L125_cout_1);

--RB1L53 is std_1c20:inst|sys_clk_timer:the_sys_clk_timer|Equal0~376 at LC_X52_Y28_N4

--operation mode is normal

RB1L53 = !RB1_internal_counter[22] & !RB1_internal_counter[20] & !RB1_internal_counter[21] & !RB1_internal_counter[23];

--RB1_internal_counter[24] is std_1c20:inst|sys_clk_timer:the_sys_clk_timer|internal_counter[24] at LC_X52_Y25_N8

--operation mode is arithmetic

RB1_internal_counter[24]_carry_eqn = (!RB1L116 & RB1L124) # (RB1L116 & RB1L125);

RB1_internal_counter[24]_lut_out = RB1_internal_counter[24] $ RB1_internal_counter[24]_carry_eqn;

RB1_internal_counter[24] = DFFEAS(RB1_internal_counter[24]_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , RB1L182, RB1_period_h_register[8], , , RB1L183);

--RB1L127 is std_1c20:inst|sys_clk_timer:the_sys_clk_timer|internal_counter[24]~7720 at LC_X52_Y25_N8

--operation mode is arithmetic

RB1L127_cout_0 = RB1_internal_counter[24] # !RB1L124;

RB1L127 = CARRY(RB1L127_cout_0);

--RB1L128 is std_1c20:inst|sys_clk_timer:the_sys_clk_timer|internal_counter[24]~7720COUT1_8944 at LC_X52_Y25_N8

--operation mode is arithmetic

RB1L128_cout_1 = RB1_internal_counter[24] # !RB1L125;

RB1L128 = CARRY(RB1L128_cout_1);

--RB1_internal_counter[25] is std_1c20:inst|sys_clk_timer:the_sys_clk_timer|internal_counter[25] at LC_X52_Y25_N9

--operation mode is arithmetic

RB1_internal_counter[25]_carry_eqn = (!RB1L116 & RB1L127) # (RB1L116 & RB1L128);

RB1_internal_counter[25]_lut_out = RB1_internal_counter[25] $ (!RB1_internal_counter[25]_carry_eqn);

RB1_internal_counter[25] = DFFEAS(RB1_internal_counter[25]_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , RB1L182, RB1_period_h_register[9], , , RB1L183);

--RB1L130 is std_1c20:inst|sys_clk_timer:the_sys_clk_timer|internal_counter[25]~7721 at LC_X52_Y25_N9

--operation mode is arithmetic

RB1L130 = CARRY(!RB1_internal_counter[25] & (!RB1L128));

--RB1_internal_counter[26] is std_1c20:inst|sys_clk_timer:the_sys_clk_timer|internal_counter[26] at LC_X52_Y24_N0

--operation mode is arithmetic

RB1_internal_counter[26]_carry_eqn = RB1L130;

RB1_internal_counter[26]_lut_out = RB1_internal_counter[26] $ RB1_internal_counter[26]_carry_eqn;

RB1_internal_counter[26] = DFFEAS(RB1_internal_counter[26]_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , RB1L182, RB1_period_h_register[10], , , RB1L183);

--RB1L132 is std_1c20:inst|sys_clk_timer:the_sys_clk_timer|internal_counter[26]~7722 at LC_X52_Y24_N0

--operation mode is arithmetic

RB1L132_cout_0 = RB1_internal_counter[26] # !RB1L130;

RB1L132 = CARRY(RB1L132_cout_0);

--RB1L133 is std_1c20:inst|sys_clk_timer:the_sys_clk_timer|internal_counter[26]~7722COUT1_8946 at LC_X52_Y24_N0

--operation mode is arithmetic

RB1L133_cout_1 = RB1_internal_counter[26] # !RB1L130;

RB1L133 = CARRY(RB1L133_cout_1);

--RB1_internal_counter[27] is std_1c20:inst|sys_clk_timer:the_sys_clk_timer|internal_counter[27] at LC_X52_Y24_N1

--operation mode is arithmetic

RB1_internal_counter[27]_carry_eqn = (!RB1L130 & RB1L132) # (RB1L130 & RB1L133);

RB1_internal_counter[27]_lut_out = RB1_internal_counter[27] $ (!RB1_internal_counter[27]_carry_eqn);

RB1_internal_counter[27] = DFFEAS(RB1_internal_counter[27]_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , RB1L182, RB1_period_h_register[11], , , RB1L183);

--RB1L135 is std_1c20:inst|sys_clk_timer:the_sys_clk_timer|internal_counter[27]~7723 at LC_X52_Y24_N1

--operation mode is arithmetic

RB1L135_cout_0 = !RB1_internal_counter[27] & (!RB1L132);

RB1L135 = CARRY(RB1L135_cout_0);

--RB1L136 is std_1c20:inst|sys_clk_timer:the_sys_clk_timer|internal_counter[27]~7723COUT1_8948 at LC_X52_Y24_N1

--operation mode is arithmetic

RB1L136_cout_1 = !RB1_internal_counter[27] & (!RB1L133);

RB1L136 = CARRY(RB1L136_cout_1);

--RB1L54 is std_1c20:inst|sys_clk_timer:the_sys_clk_timer|Equal0~377 at LC_X52_Y24_N8

--operation mode is normal

RB1L54 = !RB1_internal_counter[25] & !RB1_internal_counter[26] & !RB1_internal_counter[24] & !RB1_internal_counter[27];

--RB1_internal_counter[28] is std_1c20:inst|sys_clk_timer:the_sys_clk_timer|internal_counter[28] at LC_X52_Y24_N2

--operation mode is arithmetic

RB1_internal_counter[28]_carry_eqn = (!RB1L130 & RB1L135) # (RB1L130 & RB1L136);

RB1_internal_counter[28]_lut_out = RB1_internal_counter[28] $ (RB1_internal_counter[28]_carry_eqn);

RB1_internal_counter[28] = DFFEAS(RB1_internal_counter[28]_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , RB1L182, RB1_period_h_register[12], , , RB1L183);

--RB1L138 is std_1c20:inst|sys_clk_timer:the_sys_clk_timer|internal_counter[28]~7724 at LC_X52_Y24_N2

--operation mode is arithmetic

RB1L138_cout_0 = RB1_internal_counter[28] # !RB1L135;

RB1L138 = CARRY(RB1L138_cout_0);

--RB1L139 is std_1c20:inst|sys_clk_timer:the_sys_clk_timer|internal_counter[28]~7724COUT1_8950 at LC_X52_Y24_N2

--operation mode is arithmetic

RB1L139_cout_1 = RB1_internal_counter[28] # !RB1L136;

RB1L139 = CARRY(RB1L139_cout_1);

--RB1_internal_counter[29] is std_1c20:inst|sys_clk_timer:the_sys_clk_timer|internal_counter[29] at LC_X52_Y24_N3

--operation mode is arithmetic

RB1_internal_counter[29]_carry_eqn = (!RB1L130 & RB1L138) # (RB1L130 & RB1L139);

RB1_internal_counter[29]_lut_out = RB1_internal_counter[29] $ !RB1_internal_counter[29]_carry_eqn;

RB1_internal_counter[29] = DFFEAS(RB1_internal_counter[29]_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , RB1L182, RB1_period_h_register[13], , , RB1L183);

--RB1L141 is std_1c20:inst|sys_clk_timer:the_sys_clk_timer|internal_counter[29]~7725 at LC_X52_Y24_N3

--operation mode is arithmetic

RB1L141_cout_0 = !RB1_internal_counter[29] & !RB1L138;

RB1L141 = CARRY(RB1L141_cout_0);

--RB1L142 is std_1c20:inst|sys_clk_timer:the_sys_clk_timer|internal_counter[29]~7725COUT1_8952 at LC_X52_Y24_N3

--operation mode is arithmetic

RB1L142_cout_1 = !RB1_internal_counter[29] & !RB1L139;

RB1L142 = CARRY(RB1L142_cout_1);

--RB1_internal_counter[30] is std_1c20:inst|sys_clk_timer:the_sys_clk_timer|internal_counter[30] at LC_X52_Y24_N4

--operation mode is arithmetic

RB1_internal_counter[30]_carry_eqn = (!RB1L130 & RB1L141) # (RB1L130 & RB1L142);

RB1_internal_counter[30]_lut_out = RB1_internal_counter[30] $ RB1_internal_counter[30]_carry_eqn;

RB1_internal_counter[30] = DFFEAS(RB1_internal_counter[30]_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , RB1L182, RB1_period_h_register[14], , , RB1L183);

--RB1L144 is std_1c20:inst|sys_clk_timer:the_sys_clk_timer|internal_counter[30]~7726 at LC_X52_Y24_N4

--operation mode is arithmetic

RB1L144 = CARRY(RB1_internal_counter[30] # !RB1L142);

--RB1_internal_counter[31] is std_1c20:inst|sys_clk_timer:the_sys_clk_timer|internal_counter[31] at LC_X52_Y24_N5

--operation mode is normal

RB1_internal_counter[31]_carry_eqn = RB1L144;

RB1_internal_counter[31]_lut_out = RB1_internal_counter[31]_carry_eqn $ !RB1_internal_counter[31];

RB1_internal_counter[31] = DFFEAS(RB1_internal_counter[31]_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , RB1L182, RB1_period_h_register[15], , , RB1L183);

--RB1L55 is std_1c20:inst|sys_clk_timer:the_sys_clk_timer|Equal0~378 at LC_X52_Y24_N6

--operation mode is normal

RB1L55 = !RB1_internal_counter[28] & !RB1_internal_counter[29] & !RB1_internal_counter[30] & !RB1_internal_counter[31];

--RB1L56 is std_1c20:inst|sys_clk_timer:the_sys_clk_timer|Equal0~379 at LC_X52_Y24_N9

--operation mode is normal

RB1L56 = RB1L55 & RB1L53 & RB1L52 & RB1L54;

--RB1_delayed_unxcounter_is_zeroxx0 is std_1c20:inst|sys_clk_timer:the_sys_clk_timer|delayed_unxcounter_is_zeroxx0 at LC_X53_Y23_N0

--operation mode is normal

RB1_delayed_unxcounter_is_zeroxx0_lut_out = RB1L56 & (RB1L51);

RB1_delayed_unxcounter_is_zeroxx0 = DFFEAS(RB1_delayed_unxcounter_is_zeroxx0_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--RB1L237 is std_1c20:inst|sys_clk_timer:the_sys_clk_timer|timeout_occurred~41 at LC_X53_Y23_N1

--operation mode is normal

RB1L237 = RB1_timeout_occurred # RB1L51 & RB1L56 & !RB1_delayed_unxcounter_is_zeroxx0;

--U1L38 is std_1c20:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_readdata[7]~2421 at LC_X42_Y26_N4

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

U1_dbs_latent_8_reg_segment_0[7]_qfbk = U1_dbs_latent_8_reg_segment_0[7];

U1L38 = NB1_cpu_instruction_master_read_data_valid_sdram_s1 & (Y1_cpu_instruction_master_read_data_valid_ext_flash_s1_shift_register[1] & !U1_dbs_latent_8_reg_segment_0[7]_qfbk # !KB1_za_data[7]) # !NB1_cpu_instruction_master_read_data_valid_sdram_s1 & Y1_cpu_instruction_master_read_data_valid_ext_flash_s1_shift_register[1] & !U1_dbs_latent_8_reg_segment_0[7]_qfbk;

--U1_dbs_latent_8_reg_segment_0[7] is std_1c20:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|dbs_latent_8_reg_segment_0[7] at LC_X42_Y26_N4

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

U1_dbs_latent_8_reg_segment_0[7] = DFFEAS(U1L38, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , U1L246, Y1_internal_incoming_ext_ram_bus_data[7], , , VCC);

--U1L39 is std_1c20:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_readdata[7]~2422 at LC_X42_Y26_N5

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

Y1_cpu_instruction_master_read_data_valid_lan91c111_s1_shift_register[1]_qfbk = Y1_cpu_instruction_master_read_data_valid_lan91c111_s1_shift_register[1];

U1L39 = !U1L38 & (Y1_internal_incoming_ext_ram_bus_data[7] # !Y1_cpu_instruction_master_read_data_valid_ext_ram_s1_shift_register[1] & !Y1_cpu_instruction_master_read_data_valid_lan91c111_s1_shift_register[1]_qfbk);

--Y1_cpu_instruction_master_read_data_valid_lan91c111_s1_shift_register[1] is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|cpu_instruction_master_read_data_valid_lan91c111_s1_shift_register[1] at LC_X42_Y26_N5

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

Y1_cpu_instruction_master_read_data_valid_lan91c111_s1_shift_register[1] = DFFEAS(U1L39, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , Y1_cpu_instruction_master_read_data_valid_lan91c111_s1_shift_register[0], , , VCC);

--S1L1435Q is std_1c20:inst|cpu:the_cpu|i_readdata_d1[7]~160 at LC_X42_Y26_N8

--operation mode is normal

S1L1435Q = AMPP_FUNCTION(QC2__clk0, X1L10, U1L153, U1L39, F1_data_out);

--U1_dbs_latent_8_reg_segment_0[6] is std_1c20:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|dbs_latent_8_reg_segment_0[6] at LC_X45_Y26_N6

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

U1_dbs_latent_8_reg_segment_0[6]_qfbk = U1_dbs_latent_8_reg_segment_0[6];

U1_dbs_latent_8_reg_segment_0[6]_lut_out = Y1_cpu_instruction_master_read_data_valid_ext_flash_s1_shift_register[1] & (!KB1_za_data[6] & NB1_cpu_instruction_master_read_data_valid_sdram_s1 # !U1_dbs_latent_8_reg_segment_0[6]_qfbk) # !Y1_cpu_instruction_master_read_data_valid_ext_flash_s1_shift_register[1] & !KB1_za_data[6] & (NB1_cpu_instruction_master_read_data_valid_sdram_s1);

U1_dbs_latent_8_reg_segment_0[6] = DFFEAS(U1_dbs_latent_8_reg_segment_0[6]_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , U1L246, Y1_internal_incoming_ext_ram_bus_data[6], , , VCC);

--U1_dbs_latent_8_reg_segment_0[4] is std_1c20:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|dbs_latent_8_reg_segment_0[4] at LC_X38_Y23_N3

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

U1_dbs_latent_8_reg_segment_0[4]_qfbk = U1_dbs_latent_8_reg_segment_0[4];

U1_dbs_latent_8_reg_segment_0[4]_lut_out = Y1_cpu_instruction_master_read_data_valid_ext_flash_s1_shift_register[1] & (NB1_cpu_instruction_master_read_data_valid_sdram_s1 & !KB1_za_data[4] # !U1_dbs_latent_8_reg_segment_0[4]_qfbk) # !Y1_cpu_instruction_master_read_data_valid_ext_flash_s1_shift_register[1] & NB1_cpu_instruction_master_read_data_valid_sdram_s1 & (!KB1_za_data[4]);

U1_dbs_latent_8_reg_segment_0[4] = DFFEAS(U1_dbs_latent_8_reg_segment_0[4]_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , U1L246, Y1_internal_incoming_ext_ram_bus_data[4], , , VCC);

--U1_dbs_latent_8_reg_segment_1[7] is std_1c20:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|dbs_latent_8_reg_segment_1[7] at LC_X41_Y25_N6

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

U1_dbs_latent_8_reg_segment_1[7]_qfbk = U1_dbs_latent_8_reg_segment_1[7];

U1_dbs_latent_8_reg_segment_1[7]_lut_out = U1_dbs_latent_8_reg_segment_1[7]_qfbk # !Y1_cpu_instruction_master_read_data_valid_ext_flash_s1_shift_register[1];

U1_dbs_latent_8_reg_segment_1[7] = DFFEAS(U1_dbs_latent_8_reg_segment_1[7]_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , U1L247, Y1_internal_incoming_ext_ram_bus_data[7], , , VCC);

--S1L1472Q is std_1c20:inst|cpu:the_cpu|i_readdata_d1[15]~148 at LC_X40_Y26_N6

--operation mode is normal

S1L1472Q = AMPP_FUNCTION(QC2__clk0, U1L91, FE1_q_a[15], U1L87, U1L85, F1_data_out);

--U1L18 is std_1c20:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_readdata[0]~2434 at LC_X38_Y25_N8

--operation mode is normal

U1L18 = !Y1_internal_incoming_ext_ram_bus_data[0] & (Y1_cpu_instruction_master_read_data_valid_ext_ram_s1_shift_register[1] # Y1_cpu_instruction_master_read_data_valid_lan91c111_s1_shift_register[1]);

--U1L19 is std_1c20:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_readdata[0]~2435 at LC_X38_Y25_N1

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

U1_dbs_latent_8_reg_segment_0[0]_qfbk = U1_dbs_latent_8_reg_segment_0[0];

U1L19 = Y1_cpu_instruction_master_read_data_valid_ext_flash_s1_shift_register[1] & (NB1_cpu_instruction_master_read_data_valid_sdram_s1 & !KB1_za_data[0] # !U1_dbs_latent_8_reg_segment_0[0]_qfbk) # !Y1_cpu_instruction_master_read_data_valid_ext_flash_s1_shift_register[1] & NB1_cpu_instruction_master_read_data_valid_sdram_s1 & (!KB1_za_data[0]);

--U1_dbs_latent_8_reg_segment_0[0] is std_1c20:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|dbs_latent_8_reg_segment_0[0] at LC_X38_Y25_N1

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

U1_dbs_latent_8_reg_segment_0[0] = DFFEAS(U1L19, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , U1L246, Y1_internal_incoming_ext_ram_bus_data[0], , , VCC);

--U1L21 is std_1c20:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_readdata[1]~2437 at LC_X38_Y25_N9

--operation mode is normal

U1L21 = !Y1_internal_incoming_ext_ram_bus_data[1] & (Y1_cpu_instruction_master_read_data_valid_ext_ram_s1_shift_register[1] # Y1_cpu_instruction_master_read_data_valid_lan91c111_s1_shift_register[1]);

--U1L22 is std_1c20:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_readdata[1]~2438 at LC_X38_Y25_N2

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

U1_dbs_latent_8_reg_segment_0[1]_qfbk = U1_dbs_latent_8_reg_segment_0[1];

U1L22 = Y1_cpu_instruction_master_read_data_valid_ext_flash_s1_shift_register[1] & (NB1_cpu_instruction_master_read_data_valid_sdram_s1 & !KB1_za_data[1] # !U1_dbs_latent_8_reg_segment_0[1]_qfbk) # !Y1_cpu_instruction_master_read_data_valid_ext_flash_s1_shift_register[1] & NB1_cpu_instruction_master_read_data_valid_sdram_s1 & (!KB1_za_data[1]);

--U1_dbs_latent_8_reg_segment_0[1] is std_1c20:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|dbs_latent_8_reg_segment_0[1] at LC_X38_Y25_N2

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

U1_dbs_latent_8_reg_segment_0[1] = DFFEAS(U1L22, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , U1L246, Y1_internal_incoming_ext_ram_bus_data[1], , , VCC);

--U1_dbs_latent_8_reg_segment_0[2] is std_1c20:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|dbs_latent_8_reg_segment_0[2] at LC_X37_Y24_N3

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

U1_dbs_latent_8_reg_segment_0[2]_qfbk = U1_dbs_latent_8_reg_segment_0[2];

U1_dbs_latent_8_reg_segment_0[2]_lut_out = NB1_cpu_instruction_master_read_data_valid_sdram_s1 & (Y1_cpu_instruction_master_read_data_valid_ext_flash_s1_shift_register[1] & !U1_dbs_latent_8_reg_segment_0[2]_qfbk # !KB1_za_data[2]) # !NB1_cpu_instruction_master_read_data_valid_sdram_s1 & Y1_cpu_instruction_master_read_data_valid_ext_flash_s1_shift_register[1] & !U1_dbs_latent_8_reg_segment_0[2]_qfbk;

U1_dbs_latent_8_reg_segment_0[2] = DFFEAS(U1_dbs_latent_8_reg_segment_0[2]_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , U1L246, Y1_internal_incoming_ext_ram_bus_data[2], , , VCC);

--U1_dbs_latent_8_reg_segment_0[3] is std_1c20:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|dbs_latent_8_reg_segment_0[3] at LC_X38_Y25_N0

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

U1_dbs_latent_8_reg_segment_0[3]_qfbk = U1_dbs_latent_8_reg_segment_0[3];

U1_dbs_latent_8_reg_segment_0[3]_lut_out = Y1_cpu_instruction_master_read_data_valid_ext_flash_s1_shift_register[1] & (!KB1_za_data[3] & NB1_cpu_instruction_master_read_data_valid_sdram_s1 # !U1_dbs_latent_8_reg_segment_0[3]_qfbk) # !Y1_cpu_instruction_master_read_data_valid_ext_flash_s1_shift_register[1] & !KB1_za_data[3] & (NB1_cpu_instruction_master_read_data_valid_sdram_s1);

U1_dbs_latent_8_reg_segment_0[3] = DFFEAS(U1_dbs_latent_8_reg_segment_0[3]_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , U1L246, Y1_internal_incoming_ext_ram_bus_data[3], , , VCC);

--U1_dbs_latent_8_reg_segment_0[5] is std_1c20:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|dbs_latent_8_reg_segment_0[5] at LC_X45_Y25_N7

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

U1_dbs_latent_8_reg_segment_0[5]_qfbk = U1_dbs_latent_8_reg_segment_0[5];

U1_dbs_latent_8_reg_segment_0[5]_lut_out = Y1_cpu_instruction_master_read_data_valid_ext_flash_s1_shift_register[1] & (NB1_cpu_instruction_master_read_data_valid_sdram_s1 & !KB1_za_data[5] # !U1_dbs_latent_8_reg_segment_0[5]_qfbk) # !Y1_cpu_instruction_master_read_data_valid_ext_flash_s1_shift_register[1] & NB1_cpu_instruction_master_read_data_valid_sdram_s1 & (!KB1_za_data[5]);

U1_dbs_latent_8_reg_segment_0[5] = DFFEAS(U1_dbs_latent_8_reg_segment_0[5]_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , U1L246, Y1_internal_incoming_ext_ram_bus_data[5], , , VCC);

--U1L125 is std_1c20:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_readdata[27]~2449 at LC_X39_Y25_N0

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

Y1_cpu_instruction_master_read_data_valid_ext_flash_s1_shift_register[1]_qfbk = Y1_cpu_instruction_master_read_data_valid_ext_flash_s1_shift_register[1];

U1L125 = NB1_cpu_instruction_master_read_data_valid_sdram_s1 & (Y1_cpu_instruction_master_read_data_valid_ext_flash_s1_shift_register[1]_qfbk & !Y1_internal_incoming_ext_ram_bus_data[3] # !KB1_za_data[27]) # !NB1_cpu_instruction_master_read_data_valid_sdram_s1 & (Y1_cpu_instruction_master_read_data_valid_ext_flash_s1_shift_register[1]_qfbk & !Y1_internal_incoming_ext_ram_bus_data[3]);

--Y1_cpu_instruction_master_read_data_valid_ext_flash_s1_shift_register[1] is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|cpu_instruction_master_read_data_valid_ext_flash_s1_shift_register[1] at LC_X39_Y25_N0

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

Y1_cpu_instruction_master_read_data_valid_ext_flash_s1_shift_register[1] = DFFEAS(U1L125, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , Y1_cpu_instruction_master_read_data_valid_ext_flash_s1_shift_register[0], , , VCC);

--U1L126 is std_1c20:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_readdata[27]~2450 at LC_X39_Y25_N4

--operation mode is normal

U1L126 = !U1L125 & (Y1_internal_incoming_ext_ram_bus_data[27] # !Y1_cpu_instruction_master_read_data_valid_ext_ram_s1_shift_register[1] & !Y1_cpu_instruction_master_read_data_valid_lan91c111_s1_shift_register[1]);

--U1L127 is std_1c20:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_readdata[27]~2451 at LC_X40_Y21_N0

--operation mode is normal

U1L127 = U1L126 & (FE1_q_a[27] & !W1L1 # !X1L10);

--U1L128 is std_1c20:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_readdata[28]~2453 at LC_X37_Y22_N3

--operation mode is normal

U1L128 = Y1_internal_incoming_ext_ram_bus_data[4] & (!KB1_za_data[28] & NB1_cpu_instruction_master_read_data_valid_sdram_s1) # !Y1_internal_incoming_ext_ram_bus_data[4] & (Y1_cpu_instruction_master_read_data_valid_ext_flash_s1_shift_register[1] # !KB1_za_data[28] & NB1_cpu_instruction_master_read_data_valid_sdram_s1);

--U1L129 is std_1c20:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_readdata[28]~2454 at LC_X37_Y23_N7

--operation mode is normal

U1L129 = !U1L128 & (Y1_internal_incoming_ext_ram_bus_data[28] # !Y1_cpu_instruction_master_read_data_valid_ext_ram_s1_shift_register[1] & !Y1_cpu_instruction_master_read_data_valid_lan91c111_s1_shift_register[1]);

--U1L130 is std_1c20:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_readdata[28]~2455 at LC_X38_Y23_N8

--operation mode is normal

U1L130 = U1L129 & (FE1_q_a[28] & !W1L1 # !X1L10);

--U1L131 is std_1c20:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_readdata[29]~2457 at LC_X36_Y23_N6

--operation mode is normal

U1L131 = Y1_cpu_instruction_master_read_data_valid_ext_flash_s1_shift_register[1] & (NB1_cpu_instruction_master_read_data_valid_sdram_s1 & !KB1_za_data[29] # !Y1_internal_incoming_ext_ram_bus_data[5]) # !Y1_cpu_instruction_master_read_data_valid_ext_flash_s1_shift_register[1] & NB1_cpu_instruction_master_read_data_valid_sdram_s1 & !KB1_za_data[29];

--U1L132 is std_1c20:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_readdata[29]~2458 at LC_X36_Y23_N0

--operation mode is normal

U1L132 = !U1L131 & (Y1_internal_incoming_ext_ram_bus_data[29] # !Y1_cpu_instruction_master_read_data_valid_lan91c111_s1_shift_register[1] & !Y1_cpu_instruction_master_read_data_valid_ext_ram_s1_shift_register[1]);

--U1L133 is std_1c20:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_readdata[29]~2459 at LC_X37_Y21_N2

--operation mode is normal

U1L133 = U1L132 & (FE1_q_a[29] & !W1L1 # !X1L10);

--U1L134 is std_1c20:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_readdata[30]~2461 at LC_X36_Y22_N4

--operation mode is normal

U1L134 = Y1_cpu_instruction_master_read_data_valid_ext_flash_s1_shift_register[1] & (NB1_cpu_instruction_master_read_data_valid_sdram_s1 & !KB1_za_data[30] # !Y1_internal_incoming_ext_ram_bus_data[6]) # !Y1_cpu_instruction_master_read_data_valid_ext_flash_s1_shift_register[1] & NB1_cpu_instruction_master_read_data_valid_sdram_s1 & (!KB1_za_data[30]);

--U1L135 is std_1c20:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_readdata[30]~2462 at LC_X36_Y22_N5

--operation mode is normal

U1L135 = !U1L134 & (Y1_internal_incoming_ext_ram_bus_data[30] # !Y1_cpu_instruction_master_read_data_valid_lan91c111_s1_shift_register[1] & !Y1_cpu_instruction_master_read_data_valid_ext_ram_s1_shift_register[1]);

--U1L136 is std_1c20:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_readdata[30]~2463 at LC_X38_Y22_N5

--operation mode is normal

U1L136 = U1L135 & (!W1L1 & FE1_q_a[30] # !X1L10);

--U1L137 is std_1c20:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_readdata[31]~2465 at LC_X36_Y22_N7

--operation mode is normal

U1L137 = Y1_cpu_instruction_master_read_data_valid_ext_flash_s1_shift_register[1] & (NB1_cpu_instruction_master_read_data_valid_sdram_s1 & !KB1_za_data[31] # !Y1_internal_incoming_ext_ram_bus_data[7]) # !Y1_cpu_instruction_master_read_data_valid_ext_flash_s1_shift_register[1] & NB1_cpu_instruction_master_read_data_valid_sdram_s1 & (!KB1_za_data[31]);

--U1L138 is std_1c20:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_readdata[31]~2466 at LC_X37_Y23_N2

--operation mode is normal

U1L138 = !U1L137 & (Y1_internal_incoming_ext_ram_bus_data[31] # !Y1_cpu_instruction_master_read_data_valid_ext_ram_s1_shift_register[1] & !Y1_cpu_instruction_master_read_data_valid_lan91c111_s1_shift_register[1]);

--U1L139 is std_1c20:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_readdata[31]~2467 at LC_X37_Y21_N6

--operation mode is normal

U1L139 = U1L138 & (!W1L1 & FE1_q_a[31] # !X1L10);

--YE1_unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[0] is std_1c20:inst|uart1:the_uart1|uart1_rx:the_uart1_rx|unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[0] at LC_X53_Y22_N4

--operation mode is normal

YE1_unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[0]_lut_out = YE1_unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[1] # YE1_do_start_rx;

YE1_unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[0] = DFFEAS(YE1_unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[0]_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , YE1L72, , , , );

--YE1_got_new_char is std_1c20:inst|uart1:the_uart1|uart1_rx:the_uart1_rx|got_new_char at LC_X52_Y22_N7

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

YE1_delayed_unxrx_in_processxx3_qfbk = YE1_delayed_unxrx_in_processxx3;

YE1_got_new_char = YE1_delayed_unxrx_in_processxx3_qfbk & !YE1_unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[0];

--YE1_delayed_unxrx_in_processxx3 is std_1c20:inst|uart1:the_uart1|uart1_rx:the_uart1_rx|delayed_unxrx_in_processxx3 at LC_X52_Y22_N7

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

YE1_delayed_unxrx_in_processxx3 = DFFEAS(YE1_got_new_char, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , YE1_unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[0], , , VCC);

--YE1_unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[1] is std_1c20:inst|uart1:the_uart1|uart1_rx:the_uart1_rx|unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[1] at LC_X53_Y22_N8

--operation mode is normal

YE1_unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[1]_lut_out = YE1_unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[2] # YE1_do_start_rx;

YE1_unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[1] = DFFEAS(YE1_unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[1]_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , YE1L72, , , , );

--YE1_unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[8] is std_1c20:inst|uart1:the_uart1|uart1_rx:the_uart1_rx|unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[8] at LC_X53_Y22_N5

--operation mode is normal

YE1_unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[8]_lut_out = YE1_unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[9] # YE1_do_start_rx;

YE1_unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[8] = DFFEAS(YE1_unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[8]_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , YE1L72, , , , );

--YE1_unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[3] is std_1c20:inst|uart1:the_uart1|uart1_rx:the_uart1_rx|unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[3] at LC_X53_Y22_N9

--operation mode is normal

YE1_unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[3]_lut_out = YE1_unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[4] # YE1_do_start_rx;

YE1_unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[3] = DFFEAS(YE1_unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[3]_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , YE1L72, , , , );

--YE1L79 is std_1c20:inst|uart1:the_uart1|uart1_rx:the_uart1_rx|WideOr0~60 at LC_X52_Y22_N4

--operation mode is normal

YE1L79 = YE1_unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[1] # YE1_unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[0] # YE1_unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[8] # YE1_unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[3];

--YE1_unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[2] is std_1c20:inst|uart1:the_uart1|uart1_rx:the_uart1_rx|unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[2] at LC_X53_Y22_N7

--operation mode is normal

YE1_unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[2]_lut_out = YE1_unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[3] # YE1_do_start_rx;

YE1_unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[2] = DFFEAS(YE1_unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[2]_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , YE1L72, , , , );

--YE1_unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[4] is std_1c20:inst|uart1:the_uart1|uart1_rx:the_uart1_rx|unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[4] at LC_X53_Y22_N0

--operation mode is normal

YE1_unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[4]_lut_out = YE1_unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[5] # YE1_do_start_rx;

YE1_unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[4] = DFFEAS(YE1_unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[4]_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , YE1L72, , , , );

--YE1_unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[5] is std_1c20:inst|uart1:the_uart1|uart1_rx:the_uart1_rx|unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[5] at LC_X53_Y22_N3

--operation mode is normal

YE1_unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[5]_lut_out = YE1_unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[6] # YE1_do_start_rx;

YE1_unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[5] = DFFEAS(YE1_unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[5]_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , YE1L72, , , , );

--YE1_unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[6] is std_1c20:inst|uart1:the_uart1|uart1_rx:the_uart1_rx|unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[6] at LC_X53_Y22_N1

--operation mode is normal

YE1_unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[6]_lut_out = YE1_unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[7] # YE1_do_start_rx;

YE1_unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[6] = DFFEAS(YE1_unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[6]_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , YE1L72, , , , );

--YE1L80 is std_1c20:inst|uart1:the_uart1|uart1_rx:the_uart1_rx|WideOr0~61 at LC_X51_Y22_N2

--operation mode is normal

YE1L80 = YE1_unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[4] # YE1_unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[5] # YE1_unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[6] # YE1_unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[2];

--YE1_unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[7] is std_1c20:inst|uart1:the_uart1|uart1_rx:the_uart1_rx|unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[7] at LC_X53_Y22_N6

--operation mode is normal

YE1_unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[7]_lut_out = YE1_unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[8] # YE1_do_start_rx;

YE1_unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[7] = DFFEAS(YE1_unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[7]_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , YE1L72, , , , );

--YE1_unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[9] is std_1c20:inst|uart1:the_uart1|uart1_rx:the_uart1_rx|unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[9] at LC_X57_Y22_N1

--operation mode is normal

YE1_unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[9]_lut_out = YE1_do_start_rx # YE1L1 & YE1_sync_rxd # !YE1L1 & (YE1_unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[9]);

YE1_unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[9] = DFFEAS(YE1_unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[9]_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--YE1L81 is std_1c20:inst|uart1:the_uart1|uart1_rx:the_uart1_rx|WideOr0~62 at LC_X51_Y22_N6

--operation mode is normal

YE1L81 = YE1_unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[9] # YE1L79 # YE1L80 # YE1_unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[7];

--RB1L235 is std_1c20:inst|sys_clk_timer:the_sys_clk_timer|snap_strobe~24 at LC_X53_Y24_N4

--operation mode is normal

RB1L235 = S1L1738Q & SB1_cpu_data_master_requests_sys_clk_timer_s1 & !S1_M_alu_result[3] & RB1L7;

--M1_slave_readdata_p1[2] is std_1c20:inst|clock_1:the_clock_1|slave_readdata_p1[2] at LC_X46_Y28_N0

--operation mode is normal

M1_slave_readdata_p1[2]_lut_out = Q1_control_reg_out[2] & M1_master_nativeaddress[0];

M1_slave_readdata_p1[2] = DFFEAS(M1_slave_readdata_p1[2]_lut_out, GLOBAL(PLD_CLOCKINPUT[1]), E1_data_out, , M1L22, , , , );

--J1_slave_readdata_p1[2] is std_1c20:inst|clock_0:the_clock_0|slave_readdata_p1[2] at LC_X45_Y29_N1

--operation mode is normal

J1_slave_readdata_p1[2]_lut_out = J1_master_nativeaddress[0] & (LB1_control_reg_out[2]);

J1_slave_readdata_p1[2] = DFFEAS(J1_slave_readdata_p1[2]_lut_out, GLOBAL(PLD_CLKFB), GLOBAL(D1_data_out), , J1L22, , , , );

--GE1L37Q is std_1c20:inst|jtag_uart:the_jtag_uart|alt_jtag_atlantic:jtag_uart_alt_jtag_atlantic|t_ena~reg0 at LC_X52_Y21_N9

--operation mode is normal

GE1L37Q = AMPP_FUNCTION(QC2__clk0, GE1_read_write2, GE1L38, GE1_read_write1, GE1L37Q, F1_data_out);

--BB1_wr_rfifo is std_1c20:inst|jtag_uart:the_jtag_uart|wr_rfifo at LC_X45_Y21_N7

--operation mode is normal

BB1_wr_rfifo = GE1L37Q & !NE2_b_full;

--BB1L57 is std_1c20:inst|jtag_uart:the_jtag_uart|fifo_rd~34 at LC_X45_Y20_N5

--operation mode is normal

BB1L57 = !S1L1726Q & S1_internal_d_read;

--BB1L58 is std_1c20:inst|jtag_uart:the_jtag_uart|fifo_rd~35 at LC_X44_Y21_N7

--operation mode is normal

BB1L58 = BB1L69 & BB1L57 & CB1L2 & UB1L9;

--BB1_read_0 is std_1c20:inst|jtag_uart:the_jtag_uart|read_0 at LC_X44_Y21_N7

--operation mode is normal

BB1_read_0 = DFFEAS(BB1L58, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--BB1L78 is std_1c20:inst|jtag_uart:the_jtag_uart|rvalid~26 at LC_X44_Y21_N4

--operation mode is normal

BB1L78 = BB1L69 & BB1L57 & UB1L9 & BB1L80;

--GE1_wdata[2] is std_1c20:inst|jtag_uart:the_jtag_uart|alt_jtag_atlantic:jtag_uart_alt_jtag_atlantic|wdata[2] at LC_X51_Y20_N8

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

GE1_wdata[2] = AMPP_FUNCTION(A1L5, GE1_td_shift[6], !C1_CLR_SIGNAL, GND, GE1L74);

--QE4_safe_q[0] is std_1c20:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_r:the_jtag_uart_scfifo_r|scfifo:rfifo|scfifo_jf21:auto_generated|a_dpfifo_ml21:dpfifo|cntr_rd8:wr_ptr|safe_q[0] at LC_X48_Y21_N1

--operation mode is arithmetic

QE4_safe_q[0]_lut_out = QE4_safe_q[0] $ BB1_wr_rfifo;

QE4_safe_q[0] = DFFEAS(QE4_safe_q[0]_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--QE4L2 is std_1c20:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_r:the_jtag_uart_scfifo_r|scfifo:rfifo|scfifo_jf21:auto_generated|a_dpfifo_ml21:dpfifo|cntr_rd8:wr_ptr|counter_cella0~COUT at LC_X48_Y21_N1

--operation mode is arithmetic

QE4L2_cout_0 = QE4_safe_q[0];

QE4L2 = CARRY(QE4L2_cout_0);

--QE4L3 is std_1c20:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_r:the_jtag_uart_scfifo_r|scfifo:rfifo|scfifo_jf21:auto_generated|a_dpfifo_ml21:dpfifo|cntr_rd8:wr_ptr|counter_cella0~COUTCOUT1_53 at LC_X48_Y21_N1

--operation mode is arithmetic

QE4L3_cout_1 = QE4_safe_q[0];

QE4L3 = CARRY(QE4L3_cout_1);

--QE4_safe_q[1] is std_1c20:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_r:the_jtag_uart_scfifo_r|scfifo:rfifo|scfifo_jf21:auto_generated|a_dpfifo_ml21:dpfifo|cntr_rd8:wr_ptr|safe_q[1] at LC_X48_Y21_N2

--operation mode is arithmetic

QE4_safe_q[1]_lut_out = QE4_safe_q[1] $ (BB1_wr_rfifo & QE4L2);

QE4_safe_q[1] = DFFEAS(QE4_safe_q[1]_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--QE4L5 is std_1c20:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_r:the_jtag_uart_scfifo_r|scfifo:rfifo|scfifo_jf21:auto_generated|a_dpfifo_ml21:dpfifo|cntr_rd8:wr_ptr|counter_cella1~COUT at LC_X48_Y21_N2

--operation mode is arithmetic

QE4L5_cout_0 = !QE4L2 # !QE4_safe_q[1];

QE4L5 = CARRY(QE4L5_cout_0);

--QE4L6 is std_1c20:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_r:the_jtag_uart_scfifo_r|scfifo:rfifo|scfifo_jf21:auto_generated|a_dpfifo_ml21:dpfifo|cntr_rd8:wr_ptr|counter_cella1~COUTCOUT1_52 at LC_X48_Y21_N2

--operation mode is arithmetic

QE4L6_cout_1 = !QE4L3 # !QE4_safe_q[1];

QE4L6 = CARRY(QE4L6_cout_1);

--QE4_safe_q[2] is std_1c20:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_r:the_jtag_uart_scfifo_r|scfifo:rfifo|scfifo_jf21:auto_generated|a_dpfifo_ml21:dpfifo|cntr_rd8:wr_ptr|safe_q[2] at LC_X48_Y21_N3

--operation mode is arithmetic

QE4_safe_q[2]_lut_out = QE4_safe_q[2] $ (BB1_wr_rfifo & !QE4L5);

QE4_safe_q[2] = DFFEAS(QE4_safe_q[2]_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--QE4L8 is std_1c20:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_r:the_jtag_uart_scfifo_r|scfifo:rfifo|scfifo_jf21:auto_generated|a_dpfifo_ml21:dpfifo|cntr_rd8:wr_ptr|counter_cella2~COUT at LC_X48_Y21_N3

--operation mode is arithmetic

QE4L8_cout_0 = QE4_safe_q[2] & !QE4L5;

QE4L8 = CARRY(QE4L8_cout_0);

--QE4L9 is std_1c20:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_r:the_jtag_uart_scfifo_r|scfifo:rfifo|scfifo_jf21:auto_generated|a_dpfifo_ml21:dpfifo|cntr_rd8:wr_ptr|counter_cella2~COUTCOUT1_50 at LC_X48_Y21_N3

--operation mode is arithmetic

QE4L9_cout_1 = QE4_safe_q[2] & !QE4L6;

QE4L9 = CARRY(QE4L9_cout_1);

--QE4_safe_q[3] is std_1c20:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_r:the_jtag_uart_scfifo_r|scfifo:rfifo|scfifo_jf21:auto_generated|a_dpfifo_ml21:dpfifo|cntr_rd8:wr_ptr|safe_q[3] at LC_X48_Y21_N4

--operation mode is arithmetic

QE4_safe_q[3]_lut_out = QE4_safe_q[3] $ (BB1_wr_rfifo & QE4L8);

QE4_safe_q[3] = DFFEAS(QE4_safe_q[3]_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--QE4L11 is std_1c20:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_r:the_jtag_uart_scfifo_r|scfifo:rfifo|scfifo_jf21:auto_generated|a_dpfifo_ml21:dpfifo|cntr_rd8:wr_ptr|counter_cella3~COUT at LC_X48_Y21_N4

--operation mode is arithmetic

QE4L11 = QE4L12;

--QE4_safe_q[4] is std_1c20:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_r:the_jtag_uart_scfifo_r|scfifo:rfifo|scfifo_jf21:auto_generated|a_dpfifo_ml21:dpfifo|cntr_rd8:wr_ptr|safe_q[4] at LC_X48_Y21_N5

--operation mode is arithmetic

QE4_safe_q[4]_carry_eqn = QE4L11;

QE4_safe_q[4]_lut_out = QE4_safe_q[4] $ (BB1_wr_rfifo & !QE4_safe_q[4]_carry_eqn);

QE4_safe_q[4] = DFFEAS(QE4_safe_q[4]_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--QE4L15 is std_1c20:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_r:the_jtag_uart_scfifo_r|scfifo:rfifo|scfifo_jf21:auto_generated|a_dpfifo_ml21:dpfifo|cntr_rd8:wr_ptr|counter_cella4~COUT at LC_X48_Y21_N5

--operation mode is arithmetic

QE4L15_cout_0 = QE4_safe_q[4] & (!QE4L11);

QE4L15 = CARRY(QE4L15_cout_0);

--QE4L16 is std_1c20:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_r:the_jtag_uart_scfifo_r|scfifo:rfifo|scfifo_jf21:auto_generated|a_dpfifo_ml21:dpfifo|cntr_rd8:wr_ptr|counter_cella4~COUTCOUT1_52 at LC_X48_Y21_N5

--operation mode is arithmetic

QE4L16_cout_1 = QE4_safe_q[4] & (!QE4L11);

QE4L16 = CARRY(QE4L16_cout_1);

--QE4_safe_q[5] is std_1c20:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_r:the_jtag_uart_scfifo_r|scfifo:rfifo|scfifo_jf21:auto_generated|a_dpfifo_ml21:dpfifo|cntr_rd8:wr_ptr|safe_q[5] at LC_X48_Y21_N6

--operation mode is normal

QE4_safe_q[5]_carry_eqn = (!QE4L11 & QE4L15) # (QE4L11 & QE4L16);

QE4_safe_q[5]_lut_out = QE4_safe_q[5] $ (BB1_wr_rfifo & QE4_safe_q[5]_carry_eqn);

QE4_safe_q[5] = DFFEAS(QE4_safe_q[5]_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--QE3_safe_q[0] is std_1c20:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_r:the_jtag_uart_scfifo_r|scfifo:rfifo|scfifo_jf21:auto_generated|a_dpfifo_ml21:dpfifo|cntr_rd8:rd_ptr_count|safe_q[0] at LC_X51_Y21_N1

--operation mode is arithmetic

QE3_safe_q[0]_lut_out = QE3_safe_q[0] $ BB1L78;

QE3_safe_q[0] = DFFEAS(QE3_safe_q[0]_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--QE3L2 is std_1c20:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_r:the_jtag_uart_scfifo_r|scfifo:rfifo|scfifo_jf21:auto_generated|a_dpfifo_ml21:dpfifo|cntr_rd8:rd_ptr_count|counter_cella0~COUT at LC_X51_Y21_N1

--operation mode is arithmetic

QE3L2_cout_0 = QE3_safe_q[0];

QE3L2 = CARRY(QE3L2_cout_0);

--QE3L3 is std_1c20:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_r:the_jtag_uart_scfifo_r|scfifo:rfifo|scfifo_jf21:auto_generated|a_dpfifo_ml21:dpfifo|cntr_rd8:rd_ptr_count|counter_cella0~COUTCOUT1_53 at LC_X51_Y21_N1

--operation mode is arithmetic

QE3L3_cout_1 = QE3_safe_q[0];

QE3L3 = CARRY(QE3L3_cout_1);

--QE3_safe_q[1] is std_1c20:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_r:the_jtag_uart_scfifo_r|scfifo:rfifo|scfifo_jf21:auto_generated|a_dpfifo_ml21:dpfifo|cntr_rd8:rd_ptr_count|safe_q[1] at LC_X51_Y21_N2

--operation mode is arithmetic

QE3_safe_q[1]_lut_out = QE3_safe_q[1] $ (BB1L78 & QE3L2);

QE3_safe_q[1] = DFFEAS(QE3_safe_q[1]_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--QE3L5 is std_1c20:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_r:the_jtag_uart_scfifo_r|scfifo:rfifo|scfifo_jf21:auto_generated|a_dpfifo_ml21:dpfifo|cntr_rd8:rd_ptr_count|counter_cella1~COUT at LC_X51_Y21_N2

--operation mode is arithmetic

QE3L5_cout_0 = !QE3L2 # !QE3_safe_q[1];

QE3L5 = CARRY(QE3L5_cout_0);

--QE3L6 is std_1c20:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_r:the_jtag_uart_scfifo_r|scfifo:rfifo|scfifo_jf21:auto_generated|a_dpfifo_ml21:dpfifo|cntr_rd8:rd_ptr_count|counter_cella1~COUTCOUT1_52 at LC_X51_Y21_N2

--operation mode is arithmetic

QE3L6_cout_1 = !QE3L3 # !QE3_safe_q[1];

QE3L6 = CARRY(QE3L6_cout_1);

--QE3_safe_q[2] is std_1c20:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_r:the_jtag_uart_scfifo_r|scfifo:rfifo|scfifo_jf21:auto_generated|a_dpfifo_ml21:dpfifo|cntr_rd8:rd_ptr_count|safe_q[2] at LC_X51_Y21_N3

--operation mode is arithmetic

QE3_safe_q[2]_lut_out = QE3_safe_q[2] $ (BB1L78 & !QE3L5);

QE3_safe_q[2] = DFFEAS(QE3_safe_q[2]_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--QE3L8 is std_1c20:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_r:the_jtag_uart_scfifo_r|scfifo:rfifo|scfifo_jf21:auto_generated|a_dpfifo_ml21:dpfifo|cntr_rd8:rd_ptr_count|counter_cella2~COUT at LC_X51_Y21_N3

--operation mode is arithmetic

QE3L8_cout_0 = QE3_safe_q[2] & (!QE3L5);

QE3L8 = CARRY(QE3L8_cout_0);

--QE3L9 is std_1c20:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_r:the_jtag_uart_scfifo_r|scfifo:rfifo|scfifo_jf21:auto_generated|a_dpfifo_ml21:dpfifo|cntr_rd8:rd_ptr_count|counter_cella2~COUTCOUT1_50 at LC_X51_Y21_N3

--operation mode is arithmetic

QE3L9_cout_1 = QE3_safe_q[2] & (!QE3L6);

QE3L9 = CARRY(QE3L9_cout_1);

--QE3_safe_q[3] is std_1c20:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_r:the_jtag_uart_scfifo_r|scfifo:rfifo|scfifo_jf21:auto_generated|a_dpfifo_ml21:dpfifo|cntr_rd8:rd_ptr_count|safe_q[3] at LC_X51_Y21_N4

--operation mode is arithmetic

QE3_safe_q[3]_lut_out = QE3_safe_q[3] $ (BB1L78 & QE3L8);

QE3_safe_q[3] = DFFEAS(QE3_safe_q[3]_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--QE3L11 is std_1c20:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_r:the_jtag_uart_scfifo_r|scfifo:rfifo|scfifo_jf21:auto_generated|a_dpfifo_ml21:dpfifo|cntr_rd8:rd_ptr_count|counter_cella3~COUT at LC_X51_Y21_N4

--operation mode is arithmetic

QE3L11 = QE3L12;

--QE3_safe_q[4] is std_1c20:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_r:the_jtag_uart_scfifo_r|scfifo:rfifo|scfifo_jf21:auto_generated|a_dpfifo_ml21:dpfifo|cntr_rd8:rd_ptr_count|safe_q[4] at LC_X51_Y21_N5

--operation mode is arithmetic

QE3_safe_q[4]_carry_eqn = QE3L11;

QE3_safe_q[4]_lut_out = QE3_safe_q[4] $ (BB1L78 & !QE3_safe_q[4]_carry_eqn);

QE3_safe_q[4] = DFFEAS(QE3_safe_q[4]_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--QE3L15 is std_1c20:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_r:the_jtag_uart_scfifo_r|scfifo:rfifo|scfifo_jf21:auto_generated|a_dpfifo_ml21:dpfifo|cntr_rd8:rd_ptr_count|counter_cella4~COUT at LC_X51_Y21_N5

--operation mode is arithmetic

QE3L15_cout_0 = QE3_safe_q[4] & (!QE3L11);

QE3L15 = CARRY(QE3L15_cout_0);

--QE3L16 is std_1c20:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_r:the_jtag_uart_scfifo_r|scfifo:rfifo|scfifo_jf21:auto_generated|a_dpfifo_ml21:dpfifo|cntr_rd8:rd_ptr_count|counter_cella4~COUTCOUT1_52 at LC_X51_Y21_N5

--operation mode is arithmetic

QE3L16_cout_1 = QE3_safe_q[4] & (!QE3L11);

QE3L16 = CARRY(QE3L16_cout_1);

--QE3_safe_q[5] is std_1c20:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_r:the_jtag_uart_scfifo_r|scfifo:rfifo|scfifo_jf21:auto_generated|a_dpfifo_ml21:dpfifo|cntr_rd8:rd_ptr_count|safe_q[5] at LC_X51_Y21_N6

--operation mode is normal

QE3_safe_q[5]_carry_eqn = (!QE3L11 & QE3L15) # (QE3L11 & QE3L16);

QE3_safe_q[5]_lut_out = QE3_safe_q[5] $ (BB1L78 & QE3_safe_q[5]_carry_eqn);

QE3_safe_q[5] = DFFEAS(QE3_safe_q[5]_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--Z1L232 is std_1c20:inst|high_res_timer:the_high_res_timer|snap_strobe~18 at LC_X53_Y24_N9

--operation mode is normal

Z1L232 = S1L1738Q & AB1_cpu_data_master_requests_high_res_timer_s1 & !S1_M_alu_result[3] & RB1L7;

--DE1_endofpacketvalue_wr_strobe is std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|endofpacketvalue_wr_strobe at LC_X36_Y27_N8

--operation mode is normal

DE1_endofpacketvalue_wr_strobe = DE1L21 & X1L33 & !X1L28 & DE1_wr_strobe;

--DE1_write_shift_reg is std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|write_shift_reg at LC_X37_Y27_N2

--operation mode is normal

DE1_write_shift_reg = !DE1_transmitting & DE1_tx_holding_primed;

--DE1_control_wr_strobe is std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|control_wr_strobe at LC_X37_Y27_N0

--operation mode is normal

DE1_control_wr_strobe = X1L28 & DE1_wr_strobe & DE1L21 & !X1L33;

--DE1L286 is std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|process6~2 at LC_X37_Y27_N1

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

DE1_SSO_reg_qfbk = DE1_SSO_reg;

DE1L286 = DE1_write_shift_reg # S1L2288Q & !DE1_SSO_reg_qfbk & DE1_control_wr_strobe;

--DE1_SSO_reg is std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|SSO_reg at LC_X37_Y27_N1

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

DE1_SSO_reg = DFFEAS(DE1L286, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , DE1_control_wr_strobe, S1L2288Q, , , VCC);

--DE1_shift_reg[2] is std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|shift_reg[2] at LC_X40_Y29_N2

--operation mode is normal

DE1_shift_reg[2]_lut_out = DE1_SCLK_reg & (DE1_shift_reg[1]) # !DE1_SCLK_reg & DE1L315;

DE1_shift_reg[2] = DFFEAS(DE1_shift_reg[2]_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , DE1L315, , , !DE1_slowcount[0]);

--DE1_slowcount[0] is std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|slowcount[0] at LC_X41_Y28_N2

--operation mode is normal

DE1_slowcount[0]_lut_out = !DE1_slowcount[0] & (DE1_transmitting);

DE1_slowcount[0] = DFFEAS(DE1_slowcount[0]_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--DE1_state[4] is std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|state[4] at LC_X41_Y29_N9

--operation mode is normal

DE1_state[4]_lut_out = DE1L26 & (!DE1L261 # !DE1_state[0] # !DE1_state[4]);

DE1_state[4] = DFFEAS(DE1_state[4]_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , DE1L287, , , , );

--DE1_state[1] is std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|state[1] at LC_X41_Y29_N6

--operation mode is normal

DE1_state[1]_lut_out = DE1L30 & (!DE1_state[0] # !DE1L261 # !DE1_state[4]);

DE1_state[1] = DFFEAS(DE1_state[1]_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , DE1L287, , , , );

--DE1L261 is std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|Equal9~103 at LC_X41_Y29_N8

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

DE1_state[2]_qfbk = DE1_state[2];

DE1L261 = !DE1_state[3] & !DE1_state[2]_qfbk & !DE1_state[1];

--DE1_state[2] is std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|state[2] at LC_X41_Y29_N8

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

DE1_state[2] = DFFEAS(DE1L261, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , DE1L287, DE1L33, , , VCC);

--DE1L302 is std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|rx_holding_reg[7]~7 at LC_X41_Y29_N7

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

DE1_state[0]_qfbk = DE1_state[0];

DE1L302 = DE1_state[4] & DE1L261 & DE1_state[0]_qfbk & DE1_slowcount[0];

--DE1_state[0] is std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|state[0] at LC_X41_Y29_N7

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

DE1_state[0] = DFFEAS(DE1L302, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , DE1L287, DE1L27, , , VCC);

--SD1L191 is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|take_action_ocimem_b~30 at LC_X46_Y17_N8

--operation mode is normal

SD1L191 = AMPP_FUNCTION(SD1_ir[1], SD1_internal_jdo1[35], SD1_jxdr, SD1_ir[0]);

--SD1_internal_jdo1[3] is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|internal_jdo1[3] at LC_X52_Y16_N0

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

SD1_internal_jdo1[3] = AMPP_FUNCTION(A1L8, SD1_sr[3], VCC, GND, SD1L144);

--RD1_MonAReg[10] is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|MonAReg[10] at LC_X47_Y17_N7

--operation mode is normal

RD1_MonAReg[10] = AMPP_FUNCTION(QC2__clk0, RD1L90, SD1_internal_jdo1[17], RD1L27, SD1L190, !C1_CLR_SIGNAL, SD1L192);

--RD1L37 is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|internal_MonDReg[1]~7326 at LC_X48_Y18_N1

--operation mode is normal

RD1L37 = AMPP_FUNCTION(RD1_MonAReg[10], CE1_q_b[0]);

--RD1L38 is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|internal_MonDReg[1]~7328 at LC_X48_Y18_N8

--operation mode is normal

RD1L38 = AMPP_FUNCTION(RD1_MonRd1, SD1L189, SD1L191);

--RD1L28 is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|Equal0~98 at LC_X51_Y19_N3

--operation mode is normal

RD1L28 = AMPP_FUNCTION(RD1_MonAReg[2], RD1_MonAReg[3], RD1_MonAReg[4]);

--SD1_internal_jdo1[4] is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|internal_jdo1[4] at LC_X52_Y18_N9

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

SD1_internal_jdo1[4] = AMPP_FUNCTION(A1L8, SD1_sr[4], VCC, GND, SD1L144);

--RD1L39 is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|internal_MonDReg[1]~7329 at LC_X48_Y18_N9

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

RD1L39 = AMPP_FUNCTION(SD1L191);

--RD1_MonRd1 is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|MonRd1 at LC_X48_Y18_N9

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

RD1_MonRd1 = AMPP_FUNCTION(QC2__clk0, RD1_MonRd, !C1_CLR_SIGNAL, GND);

--RD1L29 is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|Equal0~99 at LC_X52_Y18_N4

--operation mode is normal

RD1L29 = AMPP_FUNCTION(RD1_MonAReg[3], RD1_MonAReg[2], RD1_MonAReg[4]);

--SD1_internal_jdo1[5] is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|internal_jdo1[5] at LC_X52_Y16_N6

--operation mode is normal

SD1_internal_jdo1[5] = AMPP_FUNCTION(A1L8, SD1_sr[5], VCC, SD1L144);

--RD1L1 is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|A_WE_StdLogicVector~140 at LC_X51_Y19_N5

--operation mode is normal

RD1L1 = AMPP_FUNCTION(RD1_MonAReg[2], RD1_MonAReg[3], RD1_MonAReg[4]);

--SD1_internal_jdo1[6] is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|internal_jdo1[6] at LC_X51_Y16_N7

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

SD1_internal_jdo1[6] = AMPP_FUNCTION(A1L8, SD1_sr[6], VCC, GND, SD1L144);

--SD1_internal_jdo1[7] is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|internal_jdo1[7] at LC_X51_Y16_N0

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

SD1_internal_jdo1[7] = AMPP_FUNCTION(A1L8, SD1_sr[7], VCC, GND, SD1L144);

--RD1L30 is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|Equal0~100 at LC_X52_Y18_N8

--operation mode is normal

RD1L30 = AMPP_FUNCTION(RD1_MonAReg[3], RD1_MonAReg[2], RD1_MonAReg[4]);

--SD1_internal_jdo1[8] is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|internal_jdo1[8] at LC_X53_Y18_N4

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

SD1_internal_jdo1[8] = AMPP_FUNCTION(A1L8, SD1_sr[8], VCC, GND, SD1L144);

--SD1_internal_jdo1[9] is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|internal_jdo1[9] at LC_X53_Y18_N2

--operation mode is normal

SD1_internal_jdo1[9] = AMPP_FUNCTION(A1L8, SD1_sr[9], VCC, SD1L144);

--SD1_internal_jdo1[10] is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|internal_jdo1[10] at LC_X53_Y18_N8

--operation mode is normal

SD1_internal_jdo1[10] = AMPP_FUNCTION(A1L8, SD1_sr[10], VCC, SD1L144);

--SD1_internal_jdo1[26] is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|internal_jdo1[26] at LC_X46_Y14_N2

--operation mode is normal

SD1_internal_jdo1[26] = AMPP_FUNCTION(A1L8, SD1_sr[26], VCC, SD1L144);

--RD1L2 is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|Add0~132 at LC_X47_Y19_N0

--operation mode is arithmetic

RD1L2 = AMPP_FUNCTION(RD1_MonAReg[2]);

--RD1L3 is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|Add0~133 at LC_X47_Y19_N0

--operation mode is arithmetic

RD1L3 = AMPP_FUNCTION(RD1_MonAReg[2]);

--RD1L4 is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|Add0~133COUT1_493 at LC_X47_Y19_N0

--operation mode is arithmetic

RD1L4 = AMPP_FUNCTION(RD1_MonAReg[2]);

--RD1L82 is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|MonAReg~1144 at LC_X47_Y18_N6

--operation mode is normal

RD1L82 = AMPP_FUNCTION(RD1_MonAReg[2], SD1L191);

--SD1L192 is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|take_no_action_ocimem_a~20 at LC_X46_Y18_N9

--operation mode is normal

SD1L192 = AMPP_FUNCTION(SD1L189, SD1_internal_jdo1[34]);

--SD1_internal_jdo1[27] is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|internal_jdo1[27] at LC_X48_Y13_N6

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

SD1_internal_jdo1[27] = AMPP_FUNCTION(A1L8, SD1_sr[27], VCC, GND, SD1L144);

--RD1L5 is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|Add0~134 at LC_X47_Y19_N1

--operation mode is arithmetic

RD1L5 = AMPP_FUNCTION(RD1_MonAReg[3], RD1L3, RD1L4);

--RD1L6 is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|Add0~135 at LC_X47_Y19_N1

--operation mode is arithmetic

RD1L6 = AMPP_FUNCTION(RD1_MonAReg[3], RD1L3);

--RD1L7 is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|Add0~135COUT1_495 at LC_X47_Y19_N1

--operation mode is arithmetic

RD1L7 = AMPP_FUNCTION(RD1_MonAReg[3], RD1L4);

--RD1L83 is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|MonAReg~1145 at LC_X47_Y18_N4

--operation mode is normal

RD1L83 = AMPP_FUNCTION(RD1L5, SD1L191, RD1_MonAReg[3]);

--SD1_internal_jdo1[28] is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|internal_jdo1[28] at LC_X46_Y17_N7

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

SD1_internal_jdo1[28] = AMPP_FUNCTION(A1L8, SD1_sr[28], VCC, GND, SD1L144);

--RD1L8 is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|Add0~136 at LC_X47_Y19_N2

--operation mode is arithmetic

RD1L8 = AMPP_FUNCTION(RD1_MonAReg[4], RD1L6, RD1L7);

--RD1L9 is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|Add0~137 at LC_X47_Y19_N2

--operation mode is arithmetic

RD1L9 = AMPP_FUNCTION(RD1_MonAReg[4], RD1L6);

--RD1L10 is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|Add0~137COUT1_497 at LC_X47_Y19_N2

--operation mode is arithmetic

RD1L10 = AMPP_FUNCTION(RD1_MonAReg[4], RD1L7);

--RD1L84 is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|MonAReg~1146 at LC_X47_Y18_N8

--operation mode is normal

RD1L84 = AMPP_FUNCTION(SD1L191, RD1L8, RD1_MonAReg[4]);

--SD1_internal_jdo1[29] is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|internal_jdo1[29] at LC_X47_Y14_N4

--operation mode is normal

SD1_internal_jdo1[29] = AMPP_FUNCTION(A1L8, SD1_sr[29], VCC, SD1L144);

--RD1L11 is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|Add0~138 at LC_X47_Y19_N3

--operation mode is arithmetic

RD1L11 = AMPP_FUNCTION(RD1_MonAReg[5], RD1L9, RD1L10);

--RD1L12 is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|Add0~139 at LC_X47_Y19_N3

--operation mode is arithmetic

RD1L12 = AMPP_FUNCTION(RD1_MonAReg[5], RD1L9);

--RD1L13 is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|Add0~139COUT1_499 at LC_X47_Y19_N3

--operation mode is arithmetic

RD1L13 = AMPP_FUNCTION(RD1_MonAReg[5], RD1L10);

--RD1L85 is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|MonAReg~1147 at LC_X47_Y18_N1

--operation mode is normal

RD1L85 = AMPP_FUNCTION(RD1_MonAReg[5], RD1L11, SD1L191);

--SD1_internal_jdo1[30] is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|internal_jdo1[30] at LC_X48_Y13_N2

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

SD1_internal_jdo1[30] = AMPP_FUNCTION(A1L8, SD1_sr[30], VCC, GND, SD1L144);

--RD1L14 is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|Add0~140 at LC_X47_Y19_N4

--operation mode is arithmetic

RD1L14 = AMPP_FUNCTION(RD1_MonAReg[6], RD1L12, RD1L13);

--RD1L15 is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|Add0~141 at LC_X47_Y19_N4

--operation mode is arithmetic

RD1L15 = AMPP_FUNCTION(RD1_MonAReg[6], RD1L12, RD1L13);

--RD1L86 is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|MonAReg~1148 at LC_X47_Y17_N5

--operation mode is normal

RD1L86 = AMPP_FUNCTION(RD1L14, RD1_MonAReg[6], SD1L191);

--SD1_internal_jdo1[31] is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|internal_jdo1[31] at LC_X48_Y13_N5

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

SD1_internal_jdo1[31] = AMPP_FUNCTION(A1L8, SD1_sr[31], VCC, GND, SD1L144);

--RD1L18 is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|Add0~142 at LC_X47_Y19_N5

--operation mode is arithmetic

RD1L18 = AMPP_FUNCTION(RD1_MonAReg[7], RD1L15);

--RD1L19 is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|Add0~143 at LC_X47_Y19_N5

--operation mode is arithmetic

RD1L19 = AMPP_FUNCTION(RD1_MonAReg[7]);

--RD1L20 is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|Add0~143COUT1_501 at LC_X47_Y19_N5

--operation mode is arithmetic

RD1L20 = AMPP_FUNCTION(RD1_MonAReg[7]);

--RD1L87 is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|MonAReg~1149 at LC_X47_Y17_N9

--operation mode is normal

RD1L87 = AMPP_FUNCTION(SD1L191, RD1L18, RD1_MonAReg[7]);

--SD1_internal_jdo1[32] is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|internal_jdo1[32] at LC_X47_Y15_N5

--operation mode is normal

SD1_internal_jdo1[32] = AMPP_FUNCTION(A1L8, SD1_sr[32], VCC, SD1L144);

--RD1L21 is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|Add0~144 at LC_X47_Y19_N6

--operation mode is arithmetic

RD1L21 = AMPP_FUNCTION(RD1_MonAReg[8], RD1L15, RD1L19, RD1L20);

--RD1L22 is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|Add0~145 at LC_X47_Y19_N6

--operation mode is arithmetic

RD1L22 = AMPP_FUNCTION(RD1_MonAReg[8], RD1L19);

--RD1L23 is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|Add0~145COUT1_503 at LC_X47_Y19_N6

--operation mode is arithmetic

RD1L23 = AMPP_FUNCTION(RD1_MonAReg[8], RD1L20);

--RD1L88 is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|MonAReg~1150 at LC_X47_Y17_N0

--operation mode is normal

RD1L88 = AMPP_FUNCTION(SD1L191, RD1L21, RD1_MonAReg[8]);

--SD1_internal_jdo1[33] is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|internal_jdo1[33] at LC_X47_Y15_N1

--operation mode is normal

SD1_internal_jdo1[33] = AMPP_FUNCTION(A1L8, SD1_sr[33], VCC, SD1L144);

--RD1L24 is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|Add0~146 at LC_X47_Y19_N7

--operation mode is arithmetic

RD1L24 = AMPP_FUNCTION(RD1_MonAReg[9], RD1L15, RD1L22, RD1L23);

--RD1L25 is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|Add0~147 at LC_X47_Y19_N7

--operation mode is arithmetic

RD1L25 = AMPP_FUNCTION(RD1_MonAReg[9], RD1L22);

--RD1L26 is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|Add0~147COUT1_505 at LC_X47_Y19_N7

--operation mode is arithmetic

RD1L26 = AMPP_FUNCTION(RD1_MonAReg[9], RD1L23);

--RD1L89 is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|MonAReg~1151 at LC_X47_Y18_N3

--operation mode is normal

RD1L89 = AMPP_FUNCTION(RD1_MonAReg[9], RD1L24, SD1L191);

--RD1L31 is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|Equal0~101 at LC_X52_Y18_N6

--operation mode is normal

RD1L31 = AMPP_FUNCTION(RD1_MonAReg[3], RD1_MonAReg[2], RD1_MonAReg[4]);

--SD1_internal_jdo1[24] is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|internal_jdo1[24] at LC_X46_Y16_N9

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

SD1_internal_jdo1[24] = AMPP_FUNCTION(A1L8, SD1_sr[24], VCC, GND, SD1L144);

--U1L71 is std_1c20:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_readdata[12]~2469 at LC_X37_Y22_N5

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

U1_dbs_latent_8_reg_segment_1[4]_qfbk = U1_dbs_latent_8_reg_segment_1[4];

U1L71 = Y1_cpu_instruction_master_read_data_valid_ext_flash_s1_shift_register[1] & (NB1_cpu_instruction_master_read_data_valid_sdram_s1 & !KB1_za_data[12] # !U1_dbs_latent_8_reg_segment_1[4]_qfbk) # !Y1_cpu_instruction_master_read_data_valid_ext_flash_s1_shift_register[1] & NB1_cpu_instruction_master_read_data_valid_sdram_s1 & (!KB1_za_data[12]);

--U1_dbs_latent_8_reg_segment_1[4] is std_1c20:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|dbs_latent_8_reg_segment_1[4] at LC_X37_Y22_N5

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

U1_dbs_latent_8_reg_segment_1[4] = DFFEAS(U1L71, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , U1L247, Y1_internal_incoming_ext_ram_bus_data[4], , , VCC);

--U1L72 is std_1c20:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_readdata[12]~2470 at LC_X39_Y26_N0

--operation mode is normal

U1L72 = !U1L71 & (Y1_internal_incoming_ext_ram_bus_data[12] # !Y1_cpu_instruction_master_read_data_valid_lan91c111_s1_shift_register[1] & !Y1_cpu_instruction_master_read_data_valid_ext_ram_s1_shift_register[1]);

--S1L1459Q is std_1c20:inst|cpu:the_cpu|i_readdata_d1[12]~154 at LC_X40_Y26_N1

--operation mode is normal

S1L1459Q = AMPP_FUNCTION(QC2__clk0, X1L10, U1L72, U1L156, F1_data_out);

--U1L74 is std_1c20:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_readdata[13]~2473 at LC_X39_Y22_N8

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

U1_dbs_latent_8_reg_segment_1[5]_qfbk = U1_dbs_latent_8_reg_segment_1[5];

U1L74 = Y1_cpu_instruction_master_read_data_valid_ext_flash_s1_shift_register[1] & (NB1_cpu_instruction_master_read_data_valid_sdram_s1 & !KB1_za_data[13] # !U1_dbs_latent_8_reg_segment_1[5]_qfbk) # !Y1_cpu_instruction_master_read_data_valid_ext_flash_s1_shift_register[1] & NB1_cpu_instruction_master_read_data_valid_sdram_s1 & (!KB1_za_data[13]);

--U1_dbs_latent_8_reg_segment_1[5] is std_1c20:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|dbs_latent_8_reg_segment_1[5] at LC_X39_Y22_N8

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

U1_dbs_latent_8_reg_segment_1[5] = DFFEAS(U1L74, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , U1L247, Y1_internal_incoming_ext_ram_bus_data[5], , , VCC);

--U1L75 is std_1c20:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_readdata[13]~2474 at LC_X39_Y22_N9

--operation mode is normal

U1L75 = !U1L74 & (Y1_internal_incoming_ext_ram_bus_data[13] # !Y1_cpu_instruction_master_read_data_valid_lan91c111_s1_shift_register[1] & !Y1_cpu_instruction_master_read_data_valid_ext_ram_s1_shift_register[1]);

--S1L1463Q is std_1c20:inst|cpu:the_cpu|i_readdata_d1[13]~156 at LC_X38_Y22_N7

--operation mode is normal

S1L1463Q = AMPP_FUNCTION(QC2__clk0, X1L10, U1L155, U1L75, F1_data_out);

--U1L68 is std_1c20:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_readdata[11]~2477 at LC_X38_Y25_N3

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

U1_dbs_latent_8_reg_segment_1[3]_qfbk = U1_dbs_latent_8_reg_segment_1[3];

U1L68 = Y1_cpu_instruction_master_read_data_valid_ext_flash_s1_shift_register[1] & (!KB1_za_data[11] & NB1_cpu_instruction_master_read_data_valid_sdram_s1 # !U1_dbs_latent_8_reg_segment_1[3]_qfbk) # !Y1_cpu_instruction_master_read_data_valid_ext_flash_s1_shift_register[1] & !KB1_za_data[11] & (NB1_cpu_instruction_master_read_data_valid_sdram_s1);

--U1_dbs_latent_8_reg_segment_1[3] is std_1c20:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|dbs_latent_8_reg_segment_1[3] at LC_X38_Y25_N3

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

U1_dbs_latent_8_reg_segment_1[3] = DFFEAS(U1L68, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , U1L247, Y1_internal_incoming_ext_ram_bus_data[3], , , VCC);

--U1L69 is std_1c20:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_readdata[11]~2478 at LC_X38_Y25_N5

--operation mode is normal

U1L69 = !U1L68 & (Y1_internal_incoming_ext_ram_bus_data[11] # !Y1_cpu_instruction_master_read_data_valid_ext_ram_s1_shift_register[1] & !Y1_cpu_instruction_master_read_data_valid_lan91c111_s1_shift_register[1]);

--S1L1455Q is std_1c20:inst|cpu:the_cpu|i_readdata_d1[11]~152 at LC_X38_Y22_N9

--operation mode is normal

S1L1455Q = AMPP_FUNCTION(QC2__clk0, X1L10, U1L69, U1L157, F1_data_out);

--U1L77 is std_1c20:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_readdata[14]~2481 at LC_X37_Y22_N6

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

U1_dbs_latent_8_reg_segment_1[6]_qfbk = U1_dbs_latent_8_reg_segment_1[6];

U1L77 = KB1_za_data[14] & Y1_cpu_instruction_master_read_data_valid_ext_flash_s1_shift_register[1] & !U1_dbs_latent_8_reg_segment_1[6]_qfbk # !KB1_za_data[14] & (NB1_cpu_instruction_master_read_data_valid_sdram_s1 # Y1_cpu_instruction_master_read_data_valid_ext_flash_s1_shift_register[1] & !U1_dbs_latent_8_reg_segment_1[6]_qfbk);

--U1_dbs_latent_8_reg_segment_1[6] is std_1c20:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|dbs_latent_8_reg_segment_1[6] at LC_X37_Y22_N6

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

U1_dbs_latent_8_reg_segment_1[6] = DFFEAS(U1L77, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , U1L247, Y1_internal_incoming_ext_ram_bus_data[6], , , VCC);

--U1L78 is std_1c20:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_readdata[14]~2482 at LC_X41_Y24_N5

--operation mode is normal

U1L78 = !U1L77 & (Y1_internal_incoming_ext_ram_bus_data[14] # !Y1_cpu_instruction_master_read_data_valid_lan91c111_s1_shift_register[1] & !Y1_cpu_instruction_master_read_data_valid_ext_ram_s1_shift_register[1]);

--S1L1467Q is std_1c20:inst|cpu:the_cpu|i_readdata_d1[14]~158 at LC_X42_Y24_N1

--operation mode is normal

S1L1467Q = AMPP_FUNCTION(QC2__clk0, X1L10, U1L78, U1L154, F1_data_out);

--U1L107 is std_1c20:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_readdata[21]~2485 at LC_X36_Y23_N2

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

U1_dbs_latent_8_reg_segment_2[5]_qfbk = U1_dbs_latent_8_reg_segment_2[5];

U1L107 = Y1_cpu_instruction_master_read_data_valid_ext_flash_s1_shift_register[1] & (NB1_cpu_instruction_master_read_data_valid_sdram_s1 & !KB1_za_data[21] # !U1_dbs_latent_8_reg_segment_2[5]_qfbk) # !Y1_cpu_instruction_master_read_data_valid_ext_flash_s1_shift_register[1] & NB1_cpu_instruction_master_read_data_valid_sdram_s1 & (!KB1_za_data[21]);

--U1_dbs_latent_8_reg_segment_2[5] is std_1c20:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|dbs_latent_8_reg_segment_2[5] at LC_X36_Y23_N2

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

U1_dbs_latent_8_reg_segment_2[5] = DFFEAS(U1L107, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , U1L248, Y1_internal_incoming_ext_ram_bus_data[5], , , VCC);

--U1L108 is std_1c20:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_readdata[21]~2486 at LC_X36_Y23_N3

--operation mode is normal

U1L108 = !U1L107 & (Y1_internal_incoming_ext_ram_bus_data[21] # !Y1_cpu_instruction_master_read_data_valid_lan91c111_s1_shift_register[1] & !Y1_cpu_instruction_master_read_data_valid_ext_ram_s1_shift_register[1]);

--U1L109 is std_1c20:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_readdata[21]~2487 at LC_X37_Y21_N9

--operation mode is normal

U1L109 = U1L108 & (!W1L1 & FE1_q_a[21] # !X1L10);

--U1L92 is std_1c20:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_readdata[16]~2489 at LC_X39_Y22_N3

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

U1_dbs_latent_8_reg_segment_2[0]_qfbk = U1_dbs_latent_8_reg_segment_2[0];

U1L92 = Y1_cpu_instruction_master_read_data_valid_ext_flash_s1_shift_register[1] & (!KB1_za_data[16] & NB1_cpu_instruction_master_read_data_valid_sdram_s1 # !U1_dbs_latent_8_reg_segment_2[0]_qfbk) # !Y1_cpu_instruction_master_read_data_valid_ext_flash_s1_shift_register[1] & !KB1_za_data[16] & (NB1_cpu_instruction_master_read_data_valid_sdram_s1);

--U1_dbs_latent_8_reg_segment_2[0] is std_1c20:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|dbs_latent_8_reg_segment_2[0] at LC_X39_Y22_N3

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

U1_dbs_latent_8_reg_segment_2[0] = DFFEAS(U1L92, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , U1L248, Y1_internal_incoming_ext_ram_bus_data[0], , , VCC);

--U1L93 is std_1c20:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_readdata[16]~2490 at LC_X39_Y22_N4

--operation mode is normal

U1L93 = !U1L92 & (Y1_internal_incoming_ext_ram_bus_data[16] # !Y1_cpu_instruction_master_read_data_valid_lan91c111_s1_shift_register[1] & !Y1_cpu_instruction_master_read_data_valid_ext_ram_s1_shift_register[1]);

--U1L94 is std_1c20:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_readdata[16]~2491 at LC_X41_Y22_N8

--operation mode is normal

U1L94 = U1L93 & (FE1_q_a[16] & !W1L1 # !X1L10);

--Z1_period_l_register[0] is std_1c20:inst|high_res_timer:the_high_res_timer|period_l_register[0] at LC_X55_Y27_N1

--operation mode is normal

Z1_period_l_register[0]_lut_out = !S1_M_st_data[0];

Z1_period_l_register[0] = DFFEAS(Z1_period_l_register[0]_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , Z1_period_l_wr_strobe, , , , );

--Z1_force_reload is std_1c20:inst|high_res_timer:the_high_res_timer|force_reload at LC_X47_Y23_N3

--operation mode is normal

Z1_force_reload_lut_out = XE1L22 & !T1_internal_cpu_data_master_waitrequest & S1_internal_d_write & AB1_cpu_data_master_requests_high_res_timer_s1;

Z1_force_reload = DFFEAS(Z1_force_reload_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--Z1L180 is std_1c20:inst|high_res_timer:the_high_res_timer|process0~1 at LC_X54_Y23_N7

--operation mode is normal

Z1L180 = Z1_force_reload # Z1L48 & Z1L53;

--Z1_counter_is_running is std_1c20:inst|high_res_timer:the_high_res_timer|counter_is_running at LC_X54_Y23_N1

--operation mode is normal

Z1_counter_is_running_lut_out = Z1_control_wr_strobe & (S1_M_st_data[2] # Z1L9 & !S1_M_st_data[3]) # !Z1_control_wr_strobe & Z1L9;

Z1_counter_is_running = DFFEAS(Z1_counter_is_running_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--Z1L179 is std_1c20:inst|high_res_timer:the_high_res_timer|process0~0 at LC_X54_Y23_N5

--operation mode is normal

Z1L179 = Z1_force_reload # Z1_counter_is_running;

--Z1_period_l_register[1] is std_1c20:inst|high_res_timer:the_high_res_timer|period_l_register[1] at LC_X54_Y26_N1

--operation mode is normal

Z1_period_l_register[1]_lut_out = !S1_M_st_data[1];

Z1_period_l_register[1] = DFFEAS(Z1_period_l_register[1]_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , Z1_period_l_wr_strobe, , , , );

--Z1_period_h_register[0] is std_1c20:inst|high_res_timer:the_high_res_timer|period_h_register[0] at LC_X54_Y25_N9

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

Z1_period_h_register[0]_lut_out = GND;

Z1_period_h_register[0] = DFFEAS(Z1_period_h_register[0]_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , Z1_period_h_wr_strobe, S1_M_st_data[0], , , VCC);

--Z1_period_h_register[1] is std_1c20:inst|high_res_timer:the_high_res_timer|period_h_register[1] at LC_X54_Y26_N2

--operation mode is normal

Z1_period_h_register[1]_lut_out = S1_M_st_data[1];

Z1_period_h_register[1] = DFFEAS(Z1_period_h_register[1]_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , Z1_period_h_wr_strobe, , , , );

--YE1L63 is std_1c20:inst|uart1:the_uart1|uart1_rx:the_uart1_rx|rx_overrun~45 at LC_X52_Y22_N1

--operation mode is normal

YE1L63 = YE1_internal_rx_char_ready & YE1_delayed_unxrx_in_processxx3 & !YE1_unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[0];

--M1_slave_readdata_p1[3] is std_1c20:inst|clock_1:the_clock_1|slave_readdata_p1[3] at LC_X46_Y29_N6

--operation mode is normal

M1_slave_readdata_p1[3]_lut_out = M1_master_nativeaddress[0] & Q1_control_reg_out[3];

M1_slave_readdata_p1[3] = DFFEAS(M1_slave_readdata_p1[3]_lut_out, GLOBAL(PLD_CLOCKINPUT[1]), E1_data_out, , M1L22, , , , );

--J1_slave_readdata_p1[3] is std_1c20:inst|clock_0:the_clock_0|slave_readdata_p1[3] at LC_X45_Y29_N4

--operation mode is normal

J1_slave_readdata_p1[3]_lut_out = J1_master_nativeaddress[0] & (LB1_control_reg_out[3]);

J1_slave_readdata_p1[3] = DFFEAS(J1_slave_readdata_p1[3]_lut_out, GLOBAL(PLD_CLKFB), GLOBAL(D1_data_out), , J1L22, , , , );

--GE1_wdata[3] is std_1c20:inst|jtag_uart:the_jtag_uart|alt_jtag_atlantic:jtag_uart_alt_jtag_atlantic|wdata[3] at LC_X51_Y20_N6

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

GE1_wdata[3] = AMPP_FUNCTION(A1L5, GE1_td_shift[7], !C1_CLR_SIGNAL, GND, GE1L74);

--DE1_shift_reg[3] is std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|shift_reg[3] at LC_X40_Y29_N1

--operation mode is normal

DE1_shift_reg[3]_lut_out = DE1_SCLK_reg & DE1_shift_reg[2] # !DE1_SCLK_reg & (DE1L316);

DE1_shift_reg[3] = DFFEAS(DE1_shift_reg[3]_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , DE1L316, , , !DE1_slowcount[0]);

--DE1_status_wr_strobe is std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|status_wr_strobe at LC_X37_Y27_N8

--operation mode is normal

DE1_status_wr_strobe = !X1L28 & DE1_wr_strobe & DE1L21 & !X1L33;

--DE1L159Q is std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|EOP~170 at LC_X37_Y27_N8

--operation mode is normal

DE1L159Q = DFFEAS(DE1_status_wr_strobe, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--U1_dbs_latent_8_reg_segment_1[1] is std_1c20:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|dbs_latent_8_reg_segment_1[1] at LC_X38_Y25_N4

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

U1_dbs_latent_8_reg_segment_1[1]_qfbk = U1_dbs_latent_8_reg_segment_1[1];

U1_dbs_latent_8_reg_segment_1[1]_lut_out = U1_dbs_latent_8_reg_segment_1[1]_qfbk # !Y1_cpu_instruction_master_read_data_valid_ext_flash_s1_shift_register[1];

U1_dbs_latent_8_reg_segment_1[1] = DFFEAS(U1_dbs_latent_8_reg_segment_1[1]_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , U1L247, Y1_internal_incoming_ext_ram_bus_data[1], , , VCC);

--S1L1444Q is std_1c20:inst|cpu:the_cpu|i_readdata_d1[9]~145 at LC_X40_Y26_N4

--operation mode is normal

S1L1444Q = AMPP_FUNCTION(QC2__clk0, FE1_q_a[9], U1L55, U1L51, U1L49, F1_data_out);

--S1L821 is std_1c20:inst|cpu:the_cpu|E_logic_result[31]~15615 at LC_X35_Y13_N9

--operation mode is normal

S1L821 = AMPP_FUNCTION(S1L1070, S1L884, S1_E_logic_op[0], S1_E_logic_op[1]);

--S1_E_src1_prelim[30] is std_1c20:inst|cpu:the_cpu|E_src1_prelim[30] at LC_X44_Y16_N2

--operation mode is normal

S1_E_src1_prelim[30] = AMPP_FUNCTION(QC2__clk0, CD1_q_b[30], S1_W_wr_data[30], S1L2482, S1_D_src1_hazard_W, F1_data_out, S1_D_src1_hazard_M, S1_W_stall);

--S1L883 is std_1c20:inst|cpu:the_cpu|E_src1[30]~2044 at LC_X40_Y13_N5

--operation mode is normal

S1L883 = AMPP_FUNCTION(S1_E_src1_prelim[30], S1L2480, S1L226Q, S1L886Q);

--S1_E_src2_imm[30] is std_1c20:inst|cpu:the_cpu|E_src2_imm[30] at LC_X40_Y15_N9

--operation mode is normal

S1_E_src2_imm[30] = AMPP_FUNCTION(QC2__clk0, S1_D_iw[20], S1_D_iw[21], S1L301, S1L311, F1_data_out, S1_W_stall);

--S1L1065 is std_1c20:inst|cpu:the_cpu|E_src2[30]~1531 at LC_X40_Y13_N4

--operation mode is normal

S1L1065 = AMPP_FUNCTION(S1L1067, S1L226Q, S1L1069, S1L2480);

--XC1L8 is std_1c20:inst|cpu:the_cpu|cpu_test_bench:the_cpu_test_bench|Add0~565 at LC_X35_Y13_N3

--operation mode is arithmetic

XC1L8 = AMPP_FUNCTION(S1L1060, S1L882, XC1L11);

--XC1L9 is std_1c20:inst|cpu:the_cpu|cpu_test_bench:the_cpu_test_bench|Add0~565COUT1_1897 at LC_X35_Y13_N3

--operation mode is arithmetic

XC1L9 = AMPP_FUNCTION(S1L1060, S1L882, XC1L12);

--S1L276 is std_1c20:inst|cpu:the_cpu|D_ctrl_alu_signed_cmp~293 at LC_X29_Y14_N1

--operation mode is normal

S1L276 = AMPP_FUNCTION(S1_D_iw[14], S1_D_iw[16], S1_D_iw[15]);

--S1L277 is std_1c20:inst|cpu:the_cpu|D_ctrl_alu_signed_cmp~294 at LC_X30_Y13_N4

--operation mode is normal

S1L277 = AMPP_FUNCTION(S1L1176, S1L281, S1_D_iw[4], S1L1178);

--YC1_result[29] is std_1c20:inst|cpu:the_cpu|lpm_add_sub:Add8|alt_stratix_add_sub:stratix_adder|result[29] at LC_X36_Y14_N9

--operation mode is arithmetic

YC1_result[29] = AMPP_FUNCTION(S1L1060, S1L882, YC1L71, YC1L82, YC1L83, S1_E_ctrl_alu_subtract);

--YC1L85 is std_1c20:inst|cpu:the_cpu|lpm_add_sub:Add8|alt_stratix_add_sub:stratix_adder|add_sub_cell[29]~COUT at LC_X36_Y14_N9

--operation mode is arithmetic

YC1L85 = AMPP_FUNCTION(S1L1060, S1L882, YC1L71, YC1L82, YC1L83, S1_E_ctrl_alu_subtract);

--GD1_break_readreg[18] is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_break:the_cpu_nios2_oci_break|break_readreg[18] at LC_X48_Y15_N4

--operation mode is normal

GD1_break_readreg[18] = AMPP_FUNCTION(QC2__clk0, SD1_internal_jdo1[36], SD1_internal_jdo1[37], SD1_internal_jdo1[18], SD1L188, !C1_CLR_SIGNAL, SD1L188);

--SD1L23 is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|DRsize[0]~19993 at LC_X51_Y14_N1

--operation mode is normal

SD1L23 = AMPP_FUNCTION(RD1_internal_MonDReg[18], GD1_break_readreg[18], SD1_ir[1]);

--SD1L24 is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|DRsize[0]~19994 at LC_X51_Y14_N4

--operation mode is normal

SD1L24 = AMPP_FUNCTION(SD1L143, SD1_ir[0], SD1_ir[1], SD1L23);

--GD1_break_readreg[17] is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_break:the_cpu_nios2_oci_break|break_readreg[17] at LC_X48_Y15_N0

--operation mode is normal

GD1_break_readreg[17] = AMPP_FUNCTION(QC2__clk0, SD1L188, SD1_internal_jdo1[37], SD1_internal_jdo1[36], SD1_internal_jdo1[17], !C1_CLR_SIGNAL, SD1L188);

--SD1L25 is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|DRsize[0]~19996 at LC_X48_Y15_N9

--operation mode is normal

SD1L25 = AMPP_FUNCTION(SD1_ir[1], RD1_internal_MonDReg[17], GD1_break_readreg[17]);

--SD1L26 is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|DRsize[0]~19997 at LC_X47_Y15_N0

--operation mode is normal

SD1L26 = AMPP_FUNCTION(SD1L144, SD1L142, SD1_ir[0], SD1L25);

--SD1L27 is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|DRsize[0]~19998 at LC_X47_Y15_N4

--operation mode is normal

SD1L27 = AMPP_FUNCTION(SD1L144, SD1_ir[0], A1L4, SD1L25);

--SD1_internal_jdo1[36] is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|internal_jdo1[36] at LC_X51_Y15_N1

--operation mode is normal

SD1_internal_jdo1[36] = AMPP_FUNCTION(A1L8, SD1_sr[36], VCC, SD1L144);

--SD1_internal_jdo1[37] is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|internal_jdo1[37] at LC_X51_Y15_N0

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

SD1_internal_jdo1[37] = AMPP_FUNCTION(A1L8, SD1_sr[37], VCC, GND, SD1L144);

--SD1L188 is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|take_action_break_c~48 at LC_X46_Y17_N4

--operation mode is normal

SD1L188 = AMPP_FUNCTION(SD1_ir[1], SD1_jxdr, SD1_ir[0]);

--FF1_state[14] is sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state[14] at LC_X57_Y15_N2

--operation mode is normal

FF1_state[14] = AMPP_FUNCTION(A1L5, FF1_state[13], A1L7, VCC);

--JD1L3 is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_debug:the_cpu_nios2_oci_debug|internal_monitor_error~106 at LC_X46_Y18_N2

--operation mode is normal

JD1L3 = AMPP_FUNCTION(SD1_internal_jdo1[34], SD1L189, JD1_internal_monitor_error, SD1_internal_jdo1[25]);

--SD1_sr[37] is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|sr[37] at LC_X51_Y15_N8

--operation mode is normal

SD1_sr[37] = AMPP_FUNCTION(A1L5, altera_internal_jtag, SD1L28, A1L4, SD1L144, !C1_CLR_SIGNAL, SD1L30);

--SD1L28 is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|DRsize[0]~20000 at LC_X51_Y14_N9

--operation mode is normal

SD1L28 = AMPP_FUNCTION(SD1_ir[0], SD1_ir[1]);

--SD1L29 is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|DRsize[0]~20002 at LC_X52_Y15_N5

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

SD1L29 = AMPP_FUNCTION(SD1_ir[0]);

--SD1_ir[1] is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|ir[1] at LC_X52_Y15_N5

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

SD1_ir[1] = AMPP_FUNCTION(A1L5, BF5_Q[1], VCC, GND, SD1L117);

--SD1L30 is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|DRsize[0]~20003 at LC_X52_Y15_N6

--operation mode is normal

SD1L30 = AMPP_FUNCTION(SD1L141, SD1_st_updateir, SD1L143, SD1L29);

--C1L8 is sld_hub:sld_hub_inst|GEN_SHADOW_IRF~1 at LC_X57_Y16_N9

--operation mode is normal

C1L8 = AMPP_FUNCTION(FF1_state[5], BF8_Q[0], C1_OK_TO_UPDATE_IR_Q);

--NE2L5 is std_1c20:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_r:the_jtag_uart_scfifo_r|scfifo:rfifo|scfifo_jf21:auto_generated|a_dpfifo_ml21:dpfifo|a_fefifo_7cf:fifo_state|b_full~104 at LC_X45_Y21_N3

--operation mode is normal

NE2L5 = RE2_safe_q[0] & RE2_safe_q[4] & GE1L37Q & RE2_safe_q[3];

--NE2L6 is std_1c20:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_r:the_jtag_uart_scfifo_r|scfifo:rfifo|scfifo_jf21:auto_generated|a_dpfifo_ml21:dpfifo|a_fefifo_7cf:fifo_state|b_full~105 at LC_X45_Y21_N4

--operation mode is normal

NE2L6 = RE2_safe_q[1] & RE2_safe_q[2] & RE2_safe_q[5] & NE2L5;

--M1_slave_readdata_p1[15] is std_1c20:inst|clock_1:the_clock_1|slave_readdata_p1[15] at LC_X46_Y29_N9

--operation mode is normal

M1_slave_readdata_p1[15]_lut_out = M1_master_nativeaddress[0] & Q1_control_reg_out[15];

M1_slave_readdata_p1[15] = DFFEAS(M1_slave_readdata_p1[15]_lut_out, GLOBAL(PLD_CLOCKINPUT[1]), E1_data_out, , M1L22, , , , );

--J1_slave_readdata_p1[15] is std_1c20:inst|clock_0:the_clock_0|slave_readdata_p1[15] at LC_X44_Y29_N8

--operation mode is normal

J1_slave_readdata_p1[15]_lut_out = J1_master_nativeaddress[0] & LB1_control_reg_out[15];

J1_slave_readdata_p1[15] = DFFEAS(J1_slave_readdata_p1[15]_lut_out, GLOBAL(PLD_CLKFB), GLOBAL(D1_data_out), , J1L22, , , , );

--SD1_internal_jdo1[11] is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|internal_jdo1[11] at LC_X53_Y18_N5

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

SD1_internal_jdo1[11] = AMPP_FUNCTION(A1L8, SD1_sr[11], VCC, GND, SD1L144);

--SD1_internal_jdo1[12] is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|internal_jdo1[12] at LC_X53_Y18_N6

--operation mode is normal

SD1_internal_jdo1[12] = AMPP_FUNCTION(A1L8, SD1_sr[12], VCC, SD1L144);

--SD1_internal_jdo1[13] is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|internal_jdo1[13] at LC_X52_Y18_N2

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

SD1_internal_jdo1[13] = AMPP_FUNCTION(A1L8, SD1_sr[13], VCC, GND, SD1L144);

--SD1_internal_jdo1[14] is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|internal_jdo1[14] at LC_X52_Y18_N5

--operation mode is normal

SD1_internal_jdo1[14] = AMPP_FUNCTION(A1L8, SD1_sr[14], VCC, SD1L144);

--SD1_internal_jdo1[15] is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|internal_jdo1[15] at LC_X51_Y15_N9

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

SD1_internal_jdo1[15] = AMPP_FUNCTION(A1L8, SD1_sr[15], VCC, GND, SD1L144);

--SD1_internal_jdo1[16] is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|internal_jdo1[16] at LC_X48_Y14_N6

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

SD1_internal_jdo1[16] = AMPP_FUNCTION(A1L8, SD1_sr[16], VCC, GND, SD1L144);

--SD1_internal_jdo1[17] is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|internal_jdo1[17] at LC_X48_Y14_N4

--operation mode is normal

SD1_internal_jdo1[17] = AMPP_FUNCTION(A1L8, SD1_sr[17], VCC, SD1L144);

--YE1L52 is std_1c20:inst|uart1:the_uart1|uart1_rx:the_uart1_rx|internal_rx_char_ready~34 at LC_X52_Y22_N2

--operation mode is normal

YE1L52 = YE1_internal_rx_char_ready # YE1_delayed_unxrx_in_processxx3 & !YE1_unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[0];

--YE1L64 is std_1c20:inst|uart1:the_uart1|uart1_rx:the_uart1_rx|rx_rd_strobe_onset~18 at LC_X47_Y24_N0

--operation mode is normal

YE1L64 = !S1L1738Q & S1_internal_d_read & !S1_M_alu_result[3] & !S1L1726Q;

--M1_slave_readdata_p1[7] is std_1c20:inst|clock_1:the_clock_1|slave_readdata_p1[7] at LC_X47_Y29_N6

--operation mode is normal

M1_slave_readdata_p1[7]_lut_out = M1_master_nativeaddress[0] & (Q1_control_reg_out[7]);

M1_slave_readdata_p1[7] = DFFEAS(M1_slave_readdata_p1[7]_lut_out, GLOBAL(PLD_CLOCKINPUT[1]), E1_data_out, , M1L22, , , , );

--J1_slave_readdata_p1[7] is std_1c20:inst|clock_0:the_clock_0|slave_readdata_p1[7] at LC_X45_Y29_N7

--operation mode is normal

J1_slave_readdata_p1[7]_lut_out = J1_master_nativeaddress[0] & (LB1_control_reg_out[7]);

J1_slave_readdata_p1[7] = DFFEAS(J1_slave_readdata_p1[7]_lut_out, GLOBAL(PLD_CLKFB), GLOBAL(D1_data_out), , J1L22, , , , );

--GE1_wdata[7] is std_1c20:inst|jtag_uart:the_jtag_uart|alt_jtag_atlantic:jtag_uart_alt_jtag_atlantic|wdata[7] at LC_X51_Y20_N2

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

GE1_wdata[7] = AMPP_FUNCTION(A1L5, altera_internal_jtag, !C1_CLR_SIGNAL, GND, GE1L74);

--DE1_shift_reg[7] is std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|shift_reg[7] at LC_X40_Y29_N8

--operation mode is normal

DE1_shift_reg[7]_lut_out = DE1_SCLK_reg & (DE1_shift_reg[6]) # !DE1_SCLK_reg & DE1L317;

DE1_shift_reg[7] = DFFEAS(DE1_shift_reg[7]_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , DE1L317, , , !DE1_slowcount[0]);

--U1L110 is std_1c20:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_readdata[22]~2496 at LC_X37_Y22_N2

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

U1_dbs_latent_8_reg_segment_2[6]_qfbk = U1_dbs_latent_8_reg_segment_2[6];

U1L110 = KB1_za_data[22] & Y1_cpu_instruction_master_read_data_valid_ext_flash_s1_shift_register[1] & !U1_dbs_latent_8_reg_segment_2[6]_qfbk # !KB1_za_data[22] & (NB1_cpu_instruction_master_read_data_valid_sdram_s1 # Y1_cpu_instruction_master_read_data_valid_ext_flash_s1_shift_register[1] & !U1_dbs_latent_8_reg_segment_2[6]_qfbk);

--U1_dbs_latent_8_reg_segment_2[6] is std_1c20:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|dbs_latent_8_reg_segment_2[6] at LC_X37_Y22_N2

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

U1_dbs_latent_8_reg_segment_2[6] = DFFEAS(U1L110, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , U1L248, Y1_internal_incoming_ext_ram_bus_data[6], , , VCC);

--U1L111 is std_1c20:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_readdata[22]~2497 at LC_X37_Y22_N4

--operation mode is normal

U1L111 = !U1L110 & (Y1_internal_incoming_ext_ram_bus_data[22] # !Y1_cpu_instruction_master_read_data_valid_ext_ram_s1_shift_register[1] & !Y1_cpu_instruction_master_read_data_valid_lan91c111_s1_shift_register[1]);

--U1L112 is std_1c20:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_readdata[22]~2498 at LC_X41_Y22_N5

--operation mode is normal

U1L112 = U1L111 & (!W1L1 & FE1_q_a[22] # !X1L10);

--U1L113 is std_1c20:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_readdata[23]~2500 at LC_X36_Y22_N0

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

U1_dbs_latent_8_reg_segment_2[7]_qfbk = U1_dbs_latent_8_reg_segment_2[7];

U1L113 = Y1_cpu_instruction_master_read_data_valid_ext_flash_s1_shift_register[1] & (NB1_cpu_instruction_master_read_data_valid_sdram_s1 & !KB1_za_data[23] # !U1_dbs_latent_8_reg_segment_2[7]_qfbk) # !Y1_cpu_instruction_master_read_data_valid_ext_flash_s1_shift_register[1] & NB1_cpu_instruction_master_read_data_valid_sdram_s1 & (!KB1_za_data[23]);

--U1_dbs_latent_8_reg_segment_2[7] is std_1c20:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|dbs_latent_8_reg_segment_2[7] at LC_X36_Y22_N0

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

U1_dbs_latent_8_reg_segment_2[7] = DFFEAS(U1L113, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , U1L248, Y1_internal_incoming_ext_ram_bus_data[7], , , VCC);

--U1L114 is std_1c20:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_readdata[23]~2501 at LC_X36_Y22_N1

--operation mode is normal

U1L114 = !U1L113 & (Y1_internal_incoming_ext_ram_bus_data[23] # !Y1_cpu_instruction_master_read_data_valid_ext_ram_s1_shift_register[1] & !Y1_cpu_instruction_master_read_data_valid_lan91c111_s1_shift_register[1]);

--U1L115 is std_1c20:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_readdata[23]~2502 at LC_X42_Y22_N9

--operation mode is normal

U1L115 = U1L114 & (!W1L1 & FE1_q_a[23] # !X1L10);

--U1L116 is std_1c20:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_readdata[24]~2504 at LC_X39_Y22_N2

--operation mode is normal

U1L116 = Y1_cpu_instruction_master_read_data_valid_ext_flash_s1_shift_register[1] & (!KB1_za_data[24] & NB1_cpu_instruction_master_read_data_valid_sdram_s1 # !Y1_internal_incoming_ext_ram_bus_data[0]) # !Y1_cpu_instruction_master_read_data_valid_ext_flash_s1_shift_register[1] & !KB1_za_data[24] & (NB1_cpu_instruction_master_read_data_valid_sdram_s1);

--U1L117 is std_1c20:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_readdata[24]~2505 at LC_X39_Y22_N1

--operation mode is normal

U1L117 = !U1L116 & (Y1_internal_incoming_ext_ram_bus_data[24] # !Y1_cpu_instruction_master_read_data_valid_ext_ram_s1_shift_register[1] & !Y1_cpu_instruction_master_read_data_valid_lan91c111_s1_shift_register[1]);

--U1L118 is std_1c20:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_readdata[24]~2506 at LC_X40_Y21_N1

--operation mode is normal

U1L118 = U1L117 & (!W1L1 & FE1_q_a[24] # !X1L10);

--U1L119 is std_1c20:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_readdata[25]~2508 at LC_X39_Y24_N6

--operation mode is normal

U1L119 = Y1_cpu_instruction_master_read_data_valid_ext_flash_s1_shift_register[1] & (!KB1_za_data[25] & NB1_cpu_instruction_master_read_data_valid_sdram_s1 # !Y1_internal_incoming_ext_ram_bus_data[1]) # !Y1_cpu_instruction_master_read_data_valid_ext_flash_s1_shift_register[1] & (!KB1_za_data[25] & NB1_cpu_instruction_master_read_data_valid_sdram_s1);

--U1L120 is std_1c20:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_readdata[25]~2509 at LC_X39_Y24_N7

--operation mode is normal

U1L120 = !U1L119 & (Y1_internal_incoming_ext_ram_bus_data[25] # !Y1_cpu_instruction_master_read_data_valid_lan91c111_s1_shift_register[1] & !Y1_cpu_instruction_master_read_data_valid_ext_ram_s1_shift_register[1]);

--U1L121 is std_1c20:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_readdata[25]~2510 at LC_X43_Y21_N5

--operation mode is normal

U1L121 = U1L120 & (FE1_q_a[25] & !W1L1 # !X1L10);

--U1L122 is std_1c20:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_readdata[26]~2512 at LC_X37_Y24_N5

--operation mode is normal

U1L122 = NB1_cpu_instruction_master_read_data_valid_sdram_s1 & (Y1_cpu_instruction_master_read_data_valid_ext_flash_s1_shift_register[1] & !Y1_internal_incoming_ext_ram_bus_data[2] # !KB1_za_data[26]) # !NB1_cpu_instruction_master_read_data_valid_sdram_s1 & Y1_cpu_instruction_master_read_data_valid_ext_flash_s1_shift_register[1] & !Y1_internal_incoming_ext_ram_bus_data[2];

--U1L123 is std_1c20:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_readdata[26]~2513 at LC_X41_Y24_N7

--operation mode is normal

U1L123 = !U1L122 & (Y1_internal_incoming_ext_ram_bus_data[26] # !Y1_cpu_instruction_master_read_data_valid_lan91c111_s1_shift_register[1] & !Y1_cpu_instruction_master_read_data_valid_ext_ram_s1_shift_register[1]);

--U1L124 is std_1c20:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_readdata[26]~2514 at LC_X42_Y24_N2

--operation mode is normal

U1L124 = U1L123 & (!W1L1 & FE1_q_a[26] # !X1L10);

--BB1_fifo_wr is std_1c20:inst|jtag_uart:the_jtag_uart|fifo_wr at LC_X46_Y24_N4

--operation mode is normal

BB1_fifo_wr_lut_out = !S1L1726Q & !NE1_b_full & (BB1L71);

BB1_fifo_wr = DFFEAS(BB1_fifo_wr_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--NE1_b_non_empty is std_1c20:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_w:the_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_jf21:auto_generated|a_dpfifo_ml21:dpfifo|a_fefifo_7cf:fifo_state|b_non_empty at LC_X48_Y20_N7

--operation mode is normal

NE1_b_non_empty_lut_out = NE1_b_full # BB1_fifo_wr # NE1_b_non_empty & NE1L7;

NE1_b_non_empty = DFFEAS(NE1_b_non_empty_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--GE1_r_ena1 is std_1c20:inst|jtag_uart:the_jtag_uart|alt_jtag_atlantic:jtag_uart_alt_jtag_atlantic|r_ena1 at LC_X52_Y20_N6

--operation mode is normal

GE1_r_ena1 = AMPP_FUNCTION(QC2__clk0, GE1L19, F1_data_out);

--BB1_rd_wfifo is std_1c20:inst|jtag_uart:the_jtag_uart|rd_wfifo at LC_X52_Y20_N2

--operation mode is normal

BB1_r_val_qfbk = BB1_r_val;

BB1_rd_wfifo = NE1_b_non_empty & !GE1_rvalid0 & (!GE1_r_ena1 # !BB1_r_val_qfbk);

--BB1_r_val is std_1c20:inst|jtag_uart:the_jtag_uart|r_val at LC_X52_Y20_N2

--operation mode is normal

BB1_r_val = DFFEAS(BB1_rd_wfifo, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--NE1L1 is std_1c20:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_w:the_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_jf21:auto_generated|a_dpfifo_ml21:dpfifo|a_fefifo_7cf:fifo_state|_~28 at LC_X47_Y20_N7

--operation mode is normal

NE1L1 = BB1_fifo_wr $ BB1_rd_wfifo;

--U1L104 is std_1c20:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_readdata[20]~2516 at LC_X37_Y22_N8

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

U1_dbs_latent_8_reg_segment_2[4]_qfbk = U1_dbs_latent_8_reg_segment_2[4];

U1L104 = KB1_za_data[20] & Y1_cpu_instruction_master_read_data_valid_ext_flash_s1_shift_register[1] & !U1_dbs_latent_8_reg_segment_2[4]_qfbk # !KB1_za_data[20] & (NB1_cpu_instruction_master_read_data_valid_sdram_s1 # Y1_cpu_instruction_master_read_data_valid_ext_flash_s1_shift_register[1] & !U1_dbs_latent_8_reg_segment_2[4]_qfbk);

--U1_dbs_latent_8_reg_segment_2[4] is std_1c20:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|dbs_latent_8_reg_segment_2[4] at LC_X37_Y22_N8

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

U1_dbs_latent_8_reg_segment_2[4] = DFFEAS(U1L104, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , U1L248, Y1_internal_incoming_ext_ram_bus_data[4], , , VCC);

--U1L105 is std_1c20:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_readdata[20]~2517 at LC_X37_Y22_N9

--operation mode is normal

U1L105 = !U1L104 & (Y1_internal_incoming_ext_ram_bus_data[20] # !Y1_cpu_instruction_master_read_data_valid_ext_ram_s1_shift_register[1] & !Y1_cpu_instruction_master_read_data_valid_lan91c111_s1_shift_register[1]);

--U1L106 is std_1c20:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_readdata[20]~2518 at LC_X39_Y21_N7

--operation mode is normal

U1L106 = U1L105 & (FE1_q_a[20] & !W1L1 # !X1L10);

--M1_slave_readdata_p1[14] is std_1c20:inst|clock_1:the_clock_1|slave_readdata_p1[14] at LC_X46_Y29_N4

--operation mode is normal

M1_slave_readdata_p1[14]_lut_out = M1_master_nativeaddress[0] & Q1_control_reg_out[14];

M1_slave_readdata_p1[14] = DFFEAS(M1_slave_readdata_p1[14]_lut_out, GLOBAL(PLD_CLOCKINPUT[1]), E1_data_out, , M1L22, , , , );

--J1_slave_readdata_p1[14] is std_1c20:inst|clock_0:the_clock_0|slave_readdata_p1[14] at LC_X45_Y29_N9

--operation mode is normal

J1_slave_readdata_p1[14]_lut_out = J1_master_nativeaddress[0] & (LB1_control_reg_out[14]);

J1_slave_readdata_p1[14] = DFFEAS(J1_slave_readdata_p1[14]_lut_out, GLOBAL(PLD_CLKFB), GLOBAL(D1_data_out), , J1L22, , , , );

--U1L101 is std_1c20:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_readdata[19]~2520 at LC_X37_Y24_N8

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

U1_dbs_latent_8_reg_segment_2[3]_qfbk = U1_dbs_latent_8_reg_segment_2[3];

U1L101 = NB1_cpu_instruction_master_read_data_valid_sdram_s1 & (Y1_cpu_instruction_master_read_data_valid_ext_flash_s1_shift_register[1] & !U1_dbs_latent_8_reg_segment_2[3]_qfbk # !KB1_za_data[19]) # !NB1_cpu_instruction_master_read_data_valid_sdram_s1 & Y1_cpu_instruction_master_read_data_valid_ext_flash_s1_shift_register[1] & !U1_dbs_latent_8_reg_segment_2[3]_qfbk;

--U1_dbs_latent_8_reg_segment_2[3] is std_1c20:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|dbs_latent_8_reg_segment_2[3] at LC_X37_Y24_N8

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

U1_dbs_latent_8_reg_segment_2[3] = DFFEAS(U1L101, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , U1L248, Y1_internal_incoming_ext_ram_bus_data[3], , , VCC);

--U1L102 is std_1c20:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_readdata[19]~2521 at LC_X40_Y24_N5

--operation mode is normal

U1L102 = !U1L101 & (Y1_internal_incoming_ext_ram_bus_data[19] # !Y1_cpu_instruction_master_read_data_valid_ext_ram_s1_shift_register[1] & !Y1_cpu_instruction_master_read_data_valid_lan91c111_s1_shift_register[1]);

--U1L103 is std_1c20:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_readdata[19]~2522 at LC_X40_Y24_N6

--operation mode is normal

U1L103 = U1L102 & (FE1_q_a[19] & !W1L1 # !X1L10);

--M1_slave_readdata_p1[13] is std_1c20:inst|clock_1:the_clock_1|slave_readdata_p1[13] at LC_X46_Y29_N2

--operation mode is normal

M1_slave_readdata_p1[13]_lut_out = M1_master_nativeaddress[0] & Q1_control_reg_out[13];

M1_slave_readdata_p1[13] = DFFEAS(M1_slave_readdata_p1[13]_lut_out, GLOBAL(PLD_CLOCKINPUT[1]), E1_data_out, , M1L22, , , , );

--J1_slave_readdata_p1[13] is std_1c20:inst|clock_0:the_clock_0|slave_readdata_p1[13] at LC_X44_Y29_N4

--operation mode is normal

J1_slave_readdata_p1[13]_lut_out = J1_master_nativeaddress[0] & LB1_control_reg_out[13];

J1_slave_readdata_p1[13] = DFFEAS(J1_slave_readdata_p1[13]_lut_out, GLOBAL(PLD_CLKFB), GLOBAL(D1_data_out), , J1L22, , , , );

--NE1L3 is std_1c20:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_w:the_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_jf21:auto_generated|a_dpfifo_ml21:dpfifo|a_fefifo_7cf:fifo_state|b_full~134 at LC_X47_Y20_N9

--operation mode is normal

NE1L3 = RE1_safe_q[0] & RE1_safe_q[3] & RE1_safe_q[1] & RE1_safe_q[2];

--NE1L4 is std_1c20:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_w:the_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_jf21:auto_generated|a_dpfifo_ml21:dpfifo|a_fefifo_7cf:fifo_state|b_full~135 at LC_X48_Y20_N9

--operation mode is normal

NE1L4 = RE1_safe_q[5] & RE1_safe_q[4] & NE1_b_non_empty & BB1_fifo_wr;

--U1L98 is std_1c20:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_readdata[18]~2524 at LC_X37_Y24_N0

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

U1_dbs_latent_8_reg_segment_2[2]_qfbk = U1_dbs_latent_8_reg_segment_2[2];

U1L98 = NB1_cpu_instruction_master_read_data_valid_sdram_s1 & (Y1_cpu_instruction_master_read_data_valid_ext_flash_s1_shift_register[1] & !U1_dbs_latent_8_reg_segment_2[2]_qfbk # !KB1_za_data[18]) # !NB1_cpu_instruction_master_read_data_valid_sdram_s1 & Y1_cpu_instruction_master_read_data_valid_ext_flash_s1_shift_register[1] & !U1_dbs_latent_8_reg_segment_2[2]_qfbk;

--U1_dbs_latent_8_reg_segment_2[2] is std_1c20:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|dbs_latent_8_reg_segment_2[2] at LC_X37_Y24_N0

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

U1_dbs_latent_8_reg_segment_2[2] = DFFEAS(U1L98, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , U1L248, Y1_internal_incoming_ext_ram_bus_data[2], , , VCC);

--U1L99 is std_1c20:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_readdata[18]~2525 at LC_X37_Y23_N9

--operation mode is normal

U1L99 = !U1L98 & (Y1_internal_incoming_ext_ram_bus_data[18] # !Y1_cpu_instruction_master_read_data_valid_ext_ram_s1_shift_register[1] & !Y1_cpu_instruction_master_read_data_valid_lan91c111_s1_shift_register[1]);

--U1L100 is std_1c20:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_readdata[18]~2526 at LC_X42_Y23_N0

--operation mode is normal

U1L100 = U1L99 & (FE1_q_a[18] & !W1L1 # !X1L10);

--M1_slave_readdata_p1[12] is std_1c20:inst|clock_1:the_clock_1|slave_readdata_p1[12] at LC_X47_Y29_N3

--operation mode is normal

M1_slave_readdata_p1[12]_lut_out = M1_master_nativeaddress[0] & (Q1_control_reg_out[12]);

M1_slave_readdata_p1[12] = DFFEAS(M1_slave_readdata_p1[12]_lut_out, GLOBAL(PLD_CLOCKINPUT[1]), E1_data_out, , M1L22, , , , );

--J1_slave_readdata_p1[12] is std_1c20:inst|clock_0:the_clock_0|slave_readdata_p1[12] at LC_X44_Y29_N5

--operation mode is normal

J1_slave_readdata_p1[12]_lut_out = J1_master_nativeaddress[0] & (LB1_control_reg_out[12]);

J1_slave_readdata_p1[12] = DFFEAS(J1_slave_readdata_p1[12]_lut_out, GLOBAL(PLD_CLKFB), GLOBAL(D1_data_out), , J1L22, , , , );

--NE2L8 is std_1c20:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_r:the_jtag_uart_scfifo_r|scfifo:rfifo|scfifo_jf21:auto_generated|a_dpfifo_ml21:dpfifo|a_fefifo_7cf:fifo_state|b_non_empty~100 at LC_X45_Y21_N1

--operation mode is normal

NE2L8 = NE2_b_full # GE1L37Q & !NE2_b_non_empty;

--NE2L2 is std_1c20:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_r:the_jtag_uart_scfifo_r|scfifo:rfifo|scfifo_jf21:auto_generated|a_dpfifo_ml21:dpfifo|a_fefifo_7cf:fifo_state|_~85 at LC_X45_Y21_N2

--operation mode is normal

NE2L2 = RE2_safe_q[4] # RE2_safe_q[5] # RE2_safe_q[1] # !RE2_safe_q[0];

--NE2L3 is std_1c20:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_r:the_jtag_uart_scfifo_r|scfifo:rfifo|scfifo_jf21:auto_generated|a_dpfifo_ml21:dpfifo|a_fefifo_7cf:fifo_state|_~86 at LC_X45_Y21_N8

--operation mode is normal

NE2L3 = BB1_wr_rfifo # RE2_safe_q[2] # NE2L2 # RE2_safe_q[3];

--BB1L53 is std_1c20:inst|jtag_uart:the_jtag_uart|Add1~314 at LC_X46_Y20_N0

--operation mode is arithmetic

BB1L53_cout_0 = !RE1_safe_q[0];

BB1L53 = CARRY(BB1L53_cout_0);

--BB1L54 is std_1c20:inst|jtag_uart:the_jtag_uart|Add1~314COUT1_609 at LC_X46_Y20_N0

--operation mode is arithmetic

BB1L54_cout_1 = !RE1_safe_q[0];

BB1L54 = CARRY(BB1L54_cout_1);

--S1_E_src1_prelim[28] is std_1c20:inst|cpu:the_cpu|E_src1_prelim[28] at LC_X43_Y13_N8

--operation mode is normal

S1_E_src1_prelim[28] = AMPP_FUNCTION(QC2__clk0, S1_W_wr_data[28], S1_D_src1_hazard_W, S1L2476, CD1_q_b[28], F1_data_out, S1_D_src1_hazard_M, S1_W_stall);

--S1L881 is std_1c20:inst|cpu:the_cpu|E_src1[28]~2045 at LC_X42_Y13_N6

--operation mode is normal

S1L881 = AMPP_FUNCTION(S1_E_src1_prelim[28], S1L886Q, S1L220Q, S1L2474);

--YC1_result[27] is std_1c20:inst|cpu:the_cpu|lpm_add_sub:Add8|alt_stratix_add_sub:stratix_adder|result[27] at LC_X36_Y14_N7

--operation mode is arithmetic

YC1_result[27] = AMPP_FUNCTION(S1L1050, S1L880, YC1L71, YC1L76, YC1L77, S1_E_ctrl_alu_subtract);

--YC1L79 is std_1c20:inst|cpu:the_cpu|lpm_add_sub:Add8|alt_stratix_add_sub:stratix_adder|add_sub_cell[27]~COUT at LC_X36_Y14_N7

--operation mode is arithmetic

YC1L79 = AMPP_FUNCTION(S1L1050, S1L880, YC1L76, S1_E_ctrl_alu_subtract);

--YC1L80 is std_1c20:inst|cpu:the_cpu|lpm_add_sub:Add8|alt_stratix_add_sub:stratix_adder|add_sub_cell[27]~COUTCOUT1_1339 at LC_X36_Y14_N7

--operation mode is arithmetic

YC1L80 = AMPP_FUNCTION(S1L1050, S1L880, YC1L77, S1_E_ctrl_alu_subtract);

--S1_E_src2_imm[27] is std_1c20:inst|cpu:the_cpu|E_src2_imm[27] at LC_X40_Y13_N8

--operation mode is normal

S1_E_src2_imm[27] = AMPP_FUNCTION(QC2__clk0, S1_D_iw[17], S1_D_iw[21], S1L311, S1L301, F1_data_out, S1_W_stall);

--S1L1050 is std_1c20:inst|cpu:the_cpu|E_src2[27]~1532 at LC_X43_Y13_N6

--operation mode is normal

S1L1050 = AMPP_FUNCTION(S1L217Q, S1L1052, S1L2471, S1L1054);

--U1_dbs_latent_8_reg_segment_1[2] is std_1c20:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|dbs_latent_8_reg_segment_1[2] at LC_X41_Y25_N3

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

U1_dbs_latent_8_reg_segment_1[2]_qfbk = U1_dbs_latent_8_reg_segment_1[2];

U1_dbs_latent_8_reg_segment_1[2]_lut_out = U1_dbs_latent_8_reg_segment_1[2]_qfbk # !Y1_cpu_instruction_master_read_data_valid_ext_flash_s1_shift_register[1];

U1_dbs_latent_8_reg_segment_1[2] = DFFEAS(U1_dbs_latent_8_reg_segment_1[2]_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , U1L247, Y1_internal_incoming_ext_ram_bus_data[2], , , VCC);

--S1L1449Q is std_1c20:inst|cpu:the_cpu|i_readdata_d1[10]~141 at LC_X45_Y23_N6

--operation mode is normal

S1L1449Q = AMPP_FUNCTION(QC2__clk0, U1L61, U1L67, FE1_q_a[10], U1L63, F1_data_out);

--U1L95 is std_1c20:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_readdata[17]~2531 at LC_X39_Y24_N1

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

U1_dbs_latent_8_reg_segment_2[1]_qfbk = U1_dbs_latent_8_reg_segment_2[1];

U1L95 = Y1_cpu_instruction_master_read_data_valid_ext_flash_s1_shift_register[1] & (!KB1_za_data[17] & NB1_cpu_instruction_master_read_data_valid_sdram_s1 # !U1_dbs_latent_8_reg_segment_2[1]_qfbk) # !Y1_cpu_instruction_master_read_data_valid_ext_flash_s1_shift_register[1] & !KB1_za_data[17] & (NB1_cpu_instruction_master_read_data_valid_sdram_s1);

--U1_dbs_latent_8_reg_segment_2[1] is std_1c20:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|dbs_latent_8_reg_segment_2[1] at LC_X39_Y24_N1

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

U1_dbs_latent_8_reg_segment_2[1] = DFFEAS(U1L95, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , U1L248, Y1_internal_incoming_ext_ram_bus_data[1], , , VCC);

--U1L96 is std_1c20:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_readdata[17]~2532 at LC_X41_Y24_N0

--operation mode is normal

U1L96 = !U1L95 & (Y1_internal_incoming_ext_ram_bus_data[17] # !Y1_cpu_instruction_master_read_data_valid_lan91c111_s1_shift_register[1] & !Y1_cpu_instruction_master_read_data_valid_ext_ram_s1_shift_register[1]);

--U1L97 is std_1c20:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_readdata[17]~2533 at LC_X41_Y21_N7

--operation mode is normal

U1L97 = U1L96 & (FE1_q_a[17] & !W1L1 # !X1L10);

--J1_slave_readdata_p1[11] is std_1c20:inst|clock_0:the_clock_0|slave_readdata_p1[11] at LC_X44_Y29_N2

--operation mode is normal

J1_slave_readdata_p1[11]_lut_out = J1_master_nativeaddress[0] & LB1_control_reg_out[11];

J1_slave_readdata_p1[11] = DFFEAS(J1_slave_readdata_p1[11]_lut_out, GLOBAL(PLD_CLKFB), GLOBAL(D1_data_out), , J1L22, , , , );

--M1_slave_readdata_p1[11] is std_1c20:inst|clock_1:the_clock_1|slave_readdata_p1[11] at LC_X47_Y29_N1

--operation mode is normal

M1_slave_readdata_p1[11]_lut_out = Q1_control_reg_out[11] & (M1_master_nativeaddress[0]);

M1_slave_readdata_p1[11] = DFFEAS(M1_slave_readdata_p1[11]_lut_out, GLOBAL(PLD_CLOCKINPUT[1]), E1_data_out, , M1L22, , , , );

--M1_slave_readdata_p1[10] is std_1c20:inst|clock_1:the_clock_1|slave_readdata_p1[10] at LC_X46_Y29_N7

--operation mode is normal

M1_slave_readdata_p1[10]_lut_out = M1_master_nativeaddress[0] & Q1_control_reg_out[10];

M1_slave_readdata_p1[10] = DFFEAS(M1_slave_readdata_p1[10]_lut_out, GLOBAL(PLD_CLOCKINPUT[1]), E1_data_out, , M1L22, , , , );

--J1_slave_readdata_p1[10] is std_1c20:inst|clock_0:the_clock_0|slave_readdata_p1[10] at LC_X44_Y29_N3

--operation mode is normal

J1_slave_readdata_p1[10]_lut_out = J1_master_nativeaddress[0] & LB1_control_reg_out[10];

J1_slave_readdata_p1[10] = DFFEAS(J1_slave_readdata_p1[10]_lut_out, GLOBAL(PLD_CLKFB), GLOBAL(D1_data_out), , J1L22, , , , );

--BB1L2 is std_1c20:inst|jtag_uart:the_jtag_uart|ac~75 at LC_X45_Y21_N6

--operation mode is normal

BB1L2 = GE1L39Q # GE1L37Q;

--DE1_p1_rd_strobe is std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|p1_rd_strobe at LC_X35_Y27_N6

--operation mode is normal

DE1_rd_strobe_qfbk = DE1_rd_strobe;

DE1_p1_rd_strobe = W1L1 & !DE1_rd_strobe_qfbk & (X1L13 # X1L45);

--DE1_rd_strobe is std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|rd_strobe at LC_X35_Y27_N6

--operation mode is normal

DE1_rd_strobe = DFFEAS(DE1_p1_rd_strobe, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--DE1_data_rd_strobe is std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|data_rd_strobe at LC_X35_Y27_N0

--operation mode is normal

DE1_data_rd_strobe_lut_out = DE1_p1_rd_strobe & !DE1L21 & !X1L33 & !X1L28;

DE1_data_rd_strobe = DFFEAS(DE1_data_rd_strobe_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--DE1_data_wr_strobe is std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|data_wr_strobe at LC_X37_Y28_N2

--operation mode is normal

DE1_data_wr_strobe_lut_out = DE1L285 & X1L28 & !X1L33 & !DE1L21;

DE1_data_wr_strobe = DFFEAS(DE1_data_wr_strobe_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--DE1L143 is std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|EOP~153 at LC_X37_Y29_N2

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

S1_M_st_data[4]_qfbk = S1_M_st_data[4];

DE1L143 = S1_M_st_data[2] & DE1L109Q & (DE1L113Q $ !S1_M_st_data[4]_qfbk) # !S1_M_st_data[2] & !DE1L109Q & (DE1L113Q $ !S1_M_st_data[4]_qfbk);

--S1_M_st_data[4] is std_1c20:inst|cpu:the_cpu|M_st_data[4] at LC_X37_Y29_N2

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

S1_M_st_data[4] = AMPP_FUNCTION(QC2__clk0, S1L2303, F1_data_out, GND, S1_W_stall);

--DE1L144 is std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|EOP~154 at LC_X39_Y29_N3

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

S1_M_st_data[7]_qfbk = S1_M_st_data[7];

DE1L144 = DE1L103Q & S1_M_st_data[0] & (DE1L119Q $ !S1_M_st_data[7]_qfbk) # !DE1L103Q & !S1_M_st_data[0] & (DE1L119Q $ !S1_M_st_data[7]_qfbk);

--S1_M_st_data[7] is std_1c20:inst|cpu:the_cpu|M_st_data[7] at LC_X39_Y29_N3

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

S1_M_st_data[7] = AMPP_FUNCTION(QC2__clk0, S1L2321, F1_data_out, GND, S1_W_stall);

--DE1L145 is std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|EOP~155 at LC_X39_Y29_N6

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

S1_M_st_data[6]_qfbk = S1_M_st_data[6];

DE1L145 = DE1L111Q & S1_M_st_data[3] & (S1_M_st_data[6]_qfbk $ !DE1L117Q) # !DE1L111Q & !S1_M_st_data[3] & (S1_M_st_data[6]_qfbk $ !DE1L117Q);

--S1_M_st_data[6] is std_1c20:inst|cpu:the_cpu|M_st_data[6] at LC_X39_Y29_N6

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

S1_M_st_data[6] = AMPP_FUNCTION(QC2__clk0, S1L2314, F1_data_out, GND, S1_W_stall);

--DE1L146 is std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|EOP~156 at LC_X39_Y29_N7

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

S1_M_st_data[5]_qfbk = S1_M_st_data[5];

DE1L146 = DE1L115Q & S1_M_st_data[5]_qfbk & (S1_M_st_data[1] $ !DE1L106Q) # !DE1L115Q & !S1_M_st_data[5]_qfbk & (S1_M_st_data[1] $ !DE1L106Q);

--S1_M_st_data[5] is std_1c20:inst|cpu:the_cpu|M_st_data[5] at LC_X39_Y29_N7

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

S1_M_st_data[5] = AMPP_FUNCTION(QC2__clk0, S1L2309, F1_data_out, GND, S1_W_stall);

--DE1L161Q is std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|EOP~173 at LC_X39_Y29_N8

--operation mode is normal

DE1L161Q_lut_out = DE1L145 & DE1L144 & DE1L143 & DE1L146;

DE1L161Q = DFFEAS(DE1L161Q_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--DE1L148 is std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|EOP~158 at LC_X37_Y29_N6

--operation mode is normal

DE1L148 = DE1_rx_holding_reg[2] & DE1L109Q & (DE1_rx_holding_reg[4] $ !DE1L113Q) # !DE1_rx_holding_reg[2] & !DE1L109Q & (DE1_rx_holding_reg[4] $ !DE1L113Q);

--DE1L149 is std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|EOP~159 at LC_X39_Y29_N9

--operation mode is normal

DE1L149 = DE1L294Q & DE1L103Q & (DE1L119Q $ !DE1_rx_holding_reg[7]) # !DE1L294Q & !DE1L103Q & (DE1L119Q $ !DE1_rx_holding_reg[7]);

--DE1L150 is std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|EOP~160 at LC_X39_Y28_N7

--operation mode is normal

DE1L150 = DE1L111Q & DE1_rx_holding_reg[3] & (DE1L117Q $ !DE1_rx_holding_reg[6]) # !DE1L111Q & !DE1_rx_holding_reg[3] & (DE1L117Q $ !DE1_rx_holding_reg[6]);

--DE1_rx_holding_reg[1] is std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|rx_holding_reg[1] at LC_X38_Y29_N2

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

DE1_rx_holding_reg[1]_lut_out = GND;

DE1_rx_holding_reg[1] = DFFEAS(DE1_rx_holding_reg[1]_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , DE1L302, DE1_shift_reg[1], , , VCC);

--DE1L151 is std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|EOP~161 at LC_X38_Y29_N8

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

DE1_rx_holding_reg[5]_qfbk = DE1_rx_holding_reg[5];

DE1L151 = DE1_rx_holding_reg[1] & DE1L106Q & (DE1_rx_holding_reg[5]_qfbk $ !DE1L115Q) # !DE1_rx_holding_reg[1] & !DE1L106Q & (DE1_rx_holding_reg[5]_qfbk $ !DE1L115Q);

--DE1_rx_holding_reg[5] is std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|rx_holding_reg[5] at LC_X38_Y29_N8

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

DE1_rx_holding_reg[5] = DFFEAS(DE1L151, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , DE1L302, DE1_shift_reg[5], , , VCC);

--DE1L162Q is std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|EOP~174 at LC_X38_Y29_N9

--operation mode is normal

DE1L162Q_lut_out = DE1L150 & DE1L149 & DE1L151 & DE1L148;

DE1L162Q = DFFEAS(DE1L162Q_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--DE1L153 is std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|EOP~163 at LC_X37_Y27_N5

--operation mode is normal

DE1L153 = DE1L164Q & (DE1L162Q # DE1L161Q & DE1L163Q) # !DE1L164Q & DE1L161Q & DE1L163Q;

--DE1L154 is std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|EOP~164 at LC_X36_Y29_N9

--operation mode is normal

DE1L154 = !DE1L130Q & (!DE1L140Q);

--DE1L155 is std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|EOP~165 at LC_X36_Y27_N5

--operation mode is normal

DE1L155 = !DE1L127Q & !DE1L121Q & !DE1L133Q & !DE1L124Q;

--M1_slave_readdata_p1[9] is std_1c20:inst|clock_1:the_clock_1|slave_readdata_p1[9] at LC_X46_Y29_N1

--operation mode is normal

M1_slave_readdata_p1[9]_lut_out = M1_master_nativeaddress[0] & Q1_control_reg_out[9];

M1_slave_readdata_p1[9] = DFFEAS(M1_slave_readdata_p1[9]_lut_out, GLOBAL(PLD_CLOCKINPUT[1]), E1_data_out, , M1L22, , , , );

--J1_slave_readdata_p1[9] is std_1c20:inst|clock_0:the_clock_0|slave_readdata_p1[9] at LC_X44_Y29_N6

--operation mode is normal

J1_slave_readdata_p1[9]_lut_out = J1_master_nativeaddress[0] & LB1_control_reg_out[9];

J1_slave_readdata_p1[9] = DFFEAS(J1_slave_readdata_p1[9]_lut_out, GLOBAL(PLD_CLKFB), GLOBAL(D1_data_out), , J1L22, , , , );

--YE1L49 is std_1c20:inst|uart1:the_uart1|uart1_rx:the_uart1_rx|framing_error~100 at LC_X51_Y22_N0

--operation mode is normal

YE1L49 = YE1_framing_error # !YE1_unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[9] & YE1_got_new_char & YE1L81;

--ZE1L40 is std_1c20:inst|uart1:the_uart1|uart1_tx:the_uart1_tx|tx_overrun~45 at LC_X47_Y24_N6

--operation mode is normal

ZE1L40 = ZE1_internal_tx_ready & ZE1L42 & ZE1L43 & ZE1L44;

--M1_slave_readdata_p1[8] is std_1c20:inst|clock_1:the_clock_1|slave_readdata_p1[8] at LC_X47_Y29_N9

--operation mode is normal

M1_slave_readdata_p1[8]_lut_out = M1_master_nativeaddress[0] & (Q1_control_reg_out[8]);

M1_slave_readdata_p1[8] = DFFEAS(M1_slave_readdata_p1[8]_lut_out, GLOBAL(PLD_CLOCKINPUT[1]), E1_data_out, , M1L22, , , , );

--J1_slave_readdata_p1[8] is std_1c20:inst|clock_0:the_clock_0|slave_readdata_p1[8] at LC_X44_Y29_N0

--operation mode is normal

J1_slave_readdata_p1[8]_lut_out = J1_master_nativeaddress[0] & (LB1_control_reg_out[8]);

J1_slave_readdata_p1[8] = DFFEAS(J1_slave_readdata_p1[8]_lut_out, GLOBAL(PLD_CLKFB), GLOBAL(D1_data_out), , J1L22, , , , );

--M1_slave_readdata_p1[6] is std_1c20:inst|clock_1:the_clock_1|slave_readdata_p1[6] at LC_X46_Y29_N8

--operation mode is normal

M1_slave_readdata_p1[6]_lut_out = M1_master_nativeaddress[0] & Q1_control_reg_out[6];

M1_slave_readdata_p1[6] = DFFEAS(M1_slave_readdata_p1[6]_lut_out, GLOBAL(PLD_CLOCKINPUT[1]), E1_data_out, , M1L22, , , , );

--J1_slave_readdata_p1[6] is std_1c20:inst|clock_0:the_clock_0|slave_readdata_p1[6] at LC_X45_Y28_N4

--operation mode is normal

J1_slave_readdata_p1[6]_lut_out = J1_master_nativeaddress[0] & LB1_control_reg_out[6];

J1_slave_readdata_p1[6] = DFFEAS(J1_slave_readdata_p1[6]_lut_out, GLOBAL(PLD_CLKFB), GLOBAL(D1_data_out), , J1L22, , , , );

--GE1_wdata[6] is std_1c20:inst|jtag_uart:the_jtag_uart|alt_jtag_atlantic:jtag_uart_alt_jtag_atlantic|wdata[6] at LC_X51_Y20_N5

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

GE1_wdata[6] = AMPP_FUNCTION(A1L5, GE1_td_shift[10], !C1_CLR_SIGNAL, GND, GE1L74);

--DE1_shift_reg[6] is std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|shift_reg[6] at LC_X40_Y29_N4

--operation mode is normal

DE1_shift_reg[6]_lut_out = DE1_SCLK_reg & DE1_shift_reg[5] # !DE1_SCLK_reg & (DE1L318);

DE1_shift_reg[6] = DFFEAS(DE1_shift_reg[6]_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , DE1L318, , , !DE1_slowcount[0]);

--DE1L262 is std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|Equal9~104 at LC_X41_Y29_N5

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

DE1_state[3]_qfbk = DE1_state[3];

DE1L262 = DE1_state[0] & !DE1_state[2] & !DE1_state[3]_qfbk & !DE1_state[1];

--DE1_state[3] is std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|state[3] at LC_X41_Y29_N5

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

DE1_state[3] = DFFEAS(DE1L262, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , DE1L287, DE1L36, , , VCC);

--M1_slave_readdata_p1[4] is std_1c20:inst|clock_1:the_clock_1|slave_readdata_p1[4] at LC_X46_Y28_N9

--operation mode is normal

M1_slave_readdata_p1[4]_lut_out = M1_master_nativeaddress[0] & Q1_control_reg_out[4];

M1_slave_readdata_p1[4] = DFFEAS(M1_slave_readdata_p1[4]_lut_out, GLOBAL(PLD_CLOCKINPUT[1]), E1_data_out, , M1L22, , , , );

--J1_slave_readdata_p1[4] is std_1c20:inst|clock_0:the_clock_0|slave_readdata_p1[4] at LC_X45_Y29_N2

--operation mode is normal

J1_slave_readdata_p1[4]_lut_out = J1_master_nativeaddress[0] & LB1_control_reg_out[4];

J1_slave_readdata_p1[4] = DFFEAS(J1_slave_readdata_p1[4]_lut_out, GLOBAL(PLD_CLKFB), GLOBAL(D1_data_out), , J1L22, , , , );

--GE1_wdata[4] is std_1c20:inst|jtag_uart:the_jtag_uart|alt_jtag_atlantic:jtag_uart_alt_jtag_atlantic|wdata[4] at LC_X52_Y21_N6

--operation mode is normal

GE1_wdata[4] = AMPP_FUNCTION(A1L5, GE1_td_shift[8], !C1_CLR_SIGNAL, GE1L74);

--DE1_shift_reg[4] is std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|shift_reg[4] at LC_X40_Y29_N7

--operation mode is normal

DE1_shift_reg[4]_lut_out = DE1_SCLK_reg & DE1_shift_reg[3] # !DE1_SCLK_reg & (DE1L319);

DE1_shift_reg[4] = DFFEAS(DE1_shift_reg[4]_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , DE1L319, , , !DE1_slowcount[0]);

--M1_slave_readdata_p1[5] is std_1c20:inst|clock_1:the_clock_1|slave_readdata_p1[5] at LC_X46_Y28_N8

--operation mode is normal

M1_slave_readdata_p1[5]_lut_out = Q1_control_reg_out[5] & M1_master_nativeaddress[0];

M1_slave_readdata_p1[5] = DFFEAS(M1_slave_readdata_p1[5]_lut_out, GLOBAL(PLD_CLOCKINPUT[1]), E1_data_out, , M1L22, , , , );

--J1_slave_readdata_p1[5] is std_1c20:inst|clock_0:the_clock_0|slave_readdata_p1[5] at LC_X44_Y29_N9

--operation mode is normal

J1_slave_readdata_p1[5]_lut_out = J1_master_nativeaddress[0] & (LB1_control_reg_out[5]);

J1_slave_readdata_p1[5] = DFFEAS(J1_slave_readdata_p1[5]_lut_out, GLOBAL(PLD_CLKFB), GLOBAL(D1_data_out), , J1L22, , , , );

--GE1_wdata[5] is std_1c20:inst|jtag_uart:the_jtag_uart|alt_jtag_atlantic:jtag_uart_alt_jtag_atlantic|wdata[5] at LC_X51_Y20_N4

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

GE1_wdata[5] = AMPP_FUNCTION(A1L5, GE1_td_shift[9], !C1_CLR_SIGNAL, GND, GE1L74);

--DE1_shift_reg[5] is std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|shift_reg[5] at LC_X40_Y29_N6

--operation mode is normal

DE1_shift_reg[5]_lut_out = DE1_SCLK_reg & DE1_shift_reg[4] # !DE1_SCLK_reg & (DE1L320);

DE1_shift_reg[5] = DFFEAS(DE1_shift_reg[5]_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , DE1L320, , , !DE1_slowcount[0]);

--XE1L23 is std_1c20:inst|uart1:the_uart1|uart1_regs:the_uart1_regs|Equal1~124 at LC_X53_Y24_N5

--operation mode is normal

XE1L23 = S1L1726Q & (!S1_M_alu_result[3] & S1L1738Q);

--Z1L181 is std_1c20:inst|high_res_timer:the_high_res_timer|read_mux_out[0]~1289 at LC_X54_Y24_N3

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

Z1_counter_snapshot[16]_qfbk = Z1_counter_snapshot[16];

Z1L181 = Z1_period_h_register[0] & (XE1L15 # Z1_counter_snapshot[16]_qfbk & XE1L23) # !Z1_period_h_register[0] & (Z1_counter_snapshot[16]_qfbk & XE1L23);

--Z1_counter_snapshot[16] is std_1c20:inst|high_res_timer:the_high_res_timer|counter_snapshot[16] at LC_X54_Y24_N3

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

Z1_counter_snapshot[16] = DFFEAS(Z1L181, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , Z1L232, Z1_internal_counter[16], , , VCC);

--Z1L182 is std_1c20:inst|high_res_timer:the_high_res_timer|read_mux_out[0]~1290 at LC_X47_Y23_N6

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

Z1_control_register[0]_qfbk = Z1_control_register[0];

Z1L182 = Z1_timeout_occurred & (XE1L21 # XE1L18 & Z1_control_register[0]_qfbk) # !Z1_timeout_occurred & XE1L18 & Z1_control_register[0]_qfbk;

--Z1_control_register[0] is std_1c20:inst|high_res_timer:the_high_res_timer|control_register[0] at LC_X47_Y23_N6

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

Z1_control_register[0] = DFFEAS(Z1L182, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , Z1_control_wr_strobe, S1_M_st_data[0], , , VCC);

--Z1_counter_snapshot[0] is std_1c20:inst|high_res_timer:the_high_res_timer|counter_snapshot[0] at LC_X54_Y27_N5

--operation mode is normal

Z1_counter_snapshot[0]_lut_out = !Z1_internal_counter[0];

Z1_counter_snapshot[0] = DFFEAS(Z1_counter_snapshot[0]_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , Z1L232, , , , );

--Z1L183 is std_1c20:inst|high_res_timer:the_high_res_timer|read_mux_out[0]~1291 at LC_X54_Y27_N4

--operation mode is normal

Z1L183 = Z1_period_l_register[0] & Z1_counter_snapshot[0] & (XE1L19) # !Z1_period_l_register[0] & (XE1L20 # Z1_counter_snapshot[0] & XE1L19);

--RB1_counter_snapshot[16] is std_1c20:inst|sys_clk_timer:the_sys_clk_timer|counter_snapshot[16] at LC_X52_Y23_N1

--operation mode is normal

RB1_counter_snapshot[16]_lut_out = !RB1_internal_counter[16];

RB1_counter_snapshot[16] = DFFEAS(RB1_counter_snapshot[16]_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , RB1L235, , , , );

--RB1_period_h_register[0] is std_1c20:inst|sys_clk_timer:the_sys_clk_timer|period_h_register[0] at LC_X53_Y25_N5

--operation mode is normal

RB1_period_h_register[0]_lut_out = !S1_M_st_data[0];

RB1_period_h_register[0] = DFFEAS(RB1_period_h_register[0]_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , RB1_period_h_wr_strobe, , , , );

--RB1L184 is std_1c20:inst|sys_clk_timer:the_sys_clk_timer|read_mux_out[0]~1278 at LC_X53_Y25_N4

--operation mode is normal

RB1L184 = RB1_period_h_register[0] & XE1L23 & RB1_counter_snapshot[16] # !RB1_period_h_register[0] & (XE1L15 # XE1L23 & RB1_counter_snapshot[16]);

--RB1L185 is std_1c20:inst|sys_clk_timer:the_sys_clk_timer|read_mux_out[0]~1279 at LC_X53_Y23_N9

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

RB1_control_register[0]_qfbk = RB1_control_register[0];

RB1L185 = RB1_timeout_occurred & (XE1L21 # XE1L18 & RB1_control_register[0]_qfbk) # !RB1_timeout_occurred & XE1L18 & RB1_control_register[0]_qfbk;

--RB1_control_register[0] is std_1c20:inst|sys_clk_timer:the_sys_clk_timer|control_register[0] at LC_X53_Y23_N9

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

RB1_control_register[0] = DFFEAS(RB1L185, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , RB1_control_wr_strobe, S1_M_st_data[0], , , VCC);

--RB1_counter_snapshot[0] is std_1c20:inst|sys_clk_timer:the_sys_clk_timer|counter_snapshot[0] at LC_X53_Y27_N6

--operation mode is normal

RB1_counter_snapshot[0]_lut_out = !RB1_internal_counter[0];

RB1_counter_snapshot[0] = DFFEAS(RB1_counter_snapshot[0]_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , RB1L235, , , , );

--RB1_period_l_register[0] is std_1c20:inst|sys_clk_timer:the_sys_clk_timer|period_l_register[0] at LC_X53_Y27_N8

--operation mode is normal

RB1_period_l_register[0]_lut_out = !S1_M_st_data[0];

RB1_period_l_register[0] = DFFEAS(RB1_period_l_register[0]_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , RB1_period_l_wr_strobe, , , , );

--RB1L186 is std_1c20:inst|sys_clk_timer:the_sys_clk_timer|read_mux_out[0]~1280 at LC_X53_Y27_N7

--operation mode is normal

RB1L186 = RB1_counter_snapshot[0] & (XE1L19 # !RB1_period_l_register[0] & XE1L20) # !RB1_counter_snapshot[0] & !RB1_period_l_register[0] & (XE1L20);

--G1L29 is std_1c20:inst|button_pio:the_button_pio|read_mux_out[0]~380 at LC_X45_Y20_N4

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

G1_irq_mask[0]_qfbk = G1_irq_mask[0];

G1L29 = S1L1726Q & (G1_edge_capture[0]) # !S1L1726Q & G1_irq_mask[0]_qfbk;

--G1_irq_mask[0] is std_1c20:inst|button_pio:the_button_pio|irq_mask[0] at LC_X45_Y20_N4

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

G1_irq_mask[0] = DFFEAS(G1L29, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , G1L26, S1_M_st_data[0], , , VCC);

--XE1_control_reg[0] is std_1c20:inst|uart1:the_uart1|uart1_regs:the_uart1_regs|control_reg[0] at LC_X48_Y22_N4

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

XE1_control_reg[0]_lut_out = GND;

XE1_control_reg[0] = DFFEAS(XE1_control_reg[0]_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , XE1L14, S1_M_st_data[0], , , VCC);

--XE1L49 is std_1c20:inst|uart1:the_uart1|uart1_regs:the_uart1_regs|selected_read_data[0]~695 at LC_X52_Y22_N6

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

YE1_rx_data[0]_qfbk = YE1_rx_data[0];

XE1L49 = !S1_M_alu_result[3] & (S1L1726Q & XE1_internal_tx_data[0] # !S1L1726Q & (YE1_rx_data[0]_qfbk));

--YE1_rx_data[0] is std_1c20:inst|uart1:the_uart1|uart1_rx:the_uart1_rx|rx_data[0] at LC_X52_Y22_N6

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

YE1_rx_data[0] = DFFEAS(XE1L49, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , YE1_got_new_char, YE1_unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[1], , , VCC);

--J1_slave_readdata[0] is std_1c20:inst|clock_0:the_clock_0|slave_readdata[0] at LC_X45_Y28_N8

--operation mode is normal

J1_slave_readdata[0]_lut_out = J1_slave_readdata_p1[0];

J1_slave_readdata[0] = DFFEAS(J1_slave_readdata[0]_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--T1L470 is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|p1_registered_cpu_data_master_readdata[0]~2086 at LC_X45_Y28_N6

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

M1_slave_readdata[0]_qfbk = M1_slave_readdata[0];

T1L470 = S1L1743Q & (M1_slave_readdata[0]_qfbk) # !S1L1743Q & J1_slave_readdata[0] # !K1L6;

--M1_slave_readdata[0] is std_1c20:inst|clock_1:the_clock_1|slave_readdata[0] at LC_X45_Y28_N6

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

M1_slave_readdata[0] = DFFEAS(T1L470, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , M1_slave_readdata_p1[0], , , VCC);

--T1L500 is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|p1_registered_cpu_data_master_readdata~49 at LC_X44_Y21_N2

--operation mode is normal

T1L500 = BB1_read_0 & (SE2_q_b[0]) # !BB1_read_0 & BB1_ien_AF # !T1L519;

--Z1L184 is std_1c20:inst|high_res_timer:the_high_res_timer|read_mux_out[1]~1292 at LC_X54_Y24_N8

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

Z1_counter_snapshot[17]_qfbk = Z1_counter_snapshot[17];

Z1L184 = XE1L23 & (Z1_counter_snapshot[17]_qfbk # Z1_period_h_register[1] & XE1L15) # !XE1L23 & Z1_period_h_register[1] & (XE1L15);

--Z1_counter_snapshot[17] is std_1c20:inst|high_res_timer:the_high_res_timer|counter_snapshot[17] at LC_X54_Y24_N8

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

Z1_counter_snapshot[17] = DFFEAS(Z1L184, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , Z1L232, Z1_internal_counter[17], , , VCC);

--Z1L185 is std_1c20:inst|high_res_timer:the_high_res_timer|read_mux_out[1]~1293 at LC_X53_Y23_N8

--operation mode is normal

Z1L185 = Z1_counter_is_running & (XE1L21 # Z1_control_register[1] & XE1L18) # !Z1_counter_is_running & Z1_control_register[1] & XE1L18;

--Z1_counter_snapshot[1] is std_1c20:inst|high_res_timer:the_high_res_timer|counter_snapshot[1] at LC_X54_Y27_N3

--operation mode is normal

Z1_counter_snapshot[1]_lut_out = !Z1_internal_counter[1];

Z1_counter_snapshot[1] = DFFEAS(Z1_counter_snapshot[1]_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , Z1L232, , , , );

--Z1L186 is std_1c20:inst|high_res_timer:the_high_res_timer|read_mux_out[1]~1294 at LC_X54_Y27_N8

--operation mode is normal

Z1L186 = Z1_period_l_register[1] & Z1_counter_snapshot[1] & (XE1L19) # !Z1_period_l_register[1] & (XE1L20 # Z1_counter_snapshot[1] & XE1L19);

--G1L30 is std_1c20:inst|button_pio:the_button_pio|read_mux_out[1]~382 at LC_X44_Y20_N9

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

G1_irq_mask[1]_qfbk = G1_irq_mask[1];

G1L30 = S1L1726Q & (G1_edge_capture[1]) # !S1L1726Q & (G1_irq_mask[1]_qfbk);

--G1_irq_mask[1] is std_1c20:inst|button_pio:the_button_pio|irq_mask[1] at LC_X44_Y20_N9

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

G1_irq_mask[1] = DFFEAS(G1L30, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , G1L26, S1_M_st_data[1], , , VCC);

--XE1L50 is std_1c20:inst|uart1:the_uart1|uart1_regs:the_uart1_regs|selected_read_data[1]~697 at LC_X47_Y22_N4

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

XE1_internal_tx_data[1]_qfbk = XE1_internal_tx_data[1];

XE1L50 = S1_M_alu_result[3] & XE1_control_reg[1] # !S1_M_alu_result[3] & (XE1_internal_tx_data[1]_qfbk);

--XE1_internal_tx_data[1] is std_1c20:inst|uart1:the_uart1|uart1_regs:the_uart1_regs|internal_tx_data[1] at LC_X47_Y22_N4

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

XE1_internal_tx_data[1] = DFFEAS(XE1L50, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , XE1L64, S1_M_st_data[1], , , VCC);

--XE1L51 is std_1c20:inst|uart1:the_uart1|uart1_regs:the_uart1_regs|selected_read_data[1]~698 at LC_X51_Y22_N1

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

YE1_rx_data[1]_qfbk = YE1_rx_data[1];

XE1L51 = S1_M_alu_result[3] & YE1_framing_error # !S1_M_alu_result[3] & (YE1_rx_data[1]_qfbk);

--YE1_rx_data[1] is std_1c20:inst|uart1:the_uart1|uart1_rx:the_uart1_rx|rx_data[1] at LC_X51_Y22_N1

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

YE1_rx_data[1] = DFFEAS(XE1L51, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , YE1_got_new_char, YE1_unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[2], , , VCC);

--RB1_counter_snapshot[17] is std_1c20:inst|sys_clk_timer:the_sys_clk_timer|counter_snapshot[17] at LC_X52_Y23_N7

--operation mode is normal

RB1_counter_snapshot[17]_lut_out = !RB1_internal_counter[17];

RB1_counter_snapshot[17] = DFFEAS(RB1_counter_snapshot[17]_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , RB1L235, , , , );

--RB1_period_h_register[1] is std_1c20:inst|sys_clk_timer:the_sys_clk_timer|period_h_register[1] at LC_X53_Y25_N0

--operation mode is normal

RB1_period_h_register[1]_lut_out = !S1_M_st_data[1];

RB1_period_h_register[1] = DFFEAS(RB1_period_h_register[1]_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , RB1_period_h_wr_strobe, , , , );

--RB1L187 is std_1c20:inst|sys_clk_timer:the_sys_clk_timer|read_mux_out[1]~1281 at LC_X53_Y25_N7

--operation mode is normal

RB1L187 = RB1_counter_snapshot[17] & (XE1L23 # !RB1_period_h_register[1] & XE1L15) # !RB1_counter_snapshot[17] & !RB1_period_h_register[1] & (XE1L15);

--RB1_counter_is_running is std_1c20:inst|sys_clk_timer:the_sys_clk_timer|counter_is_running at LC_X54_Y23_N6

--operation mode is normal

RB1_counter_is_running_lut_out = RB1_control_wr_strobe & (S1_M_st_data[2] # !S1_M_st_data[3] & RB1L12) # !RB1_control_wr_strobe & (RB1L12);

RB1_counter_is_running = DFFEAS(RB1_counter_is_running_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--RB1L188 is std_1c20:inst|sys_clk_timer:the_sys_clk_timer|read_mux_out[1]~1282 at LC_X53_Y23_N3

--operation mode is normal

RB1L188 = RB1_control_register[1] & (XE1L18 # RB1_counter_is_running & XE1L21) # !RB1_control_register[1] & (RB1_counter_is_running & XE1L21);

--RB1_counter_snapshot[1] is std_1c20:inst|sys_clk_timer:the_sys_clk_timer|counter_snapshot[1] at LC_X53_Y27_N9

--operation mode is normal

RB1_counter_snapshot[1]_lut_out = !RB1_internal_counter[1];

RB1_counter_snapshot[1] = DFFEAS(RB1_counter_snapshot[1]_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , RB1L235, , , , );

--RB1_period_l_register[1] is std_1c20:inst|sys_clk_timer:the_sys_clk_timer|period_l_register[1] at LC_X53_Y27_N4

--operation mode is normal

RB1_period_l_register[1]_lut_out = !S1_M_st_data[1];

RB1_period_l_register[1] = DFFEAS(RB1_period_l_register[1]_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , RB1_period_l_wr_strobe, , , , );

--RB1L189 is std_1c20:inst|sys_clk_timer:the_sys_clk_timer|read_mux_out[1]~1283 at LC_X53_Y27_N5

--operation mode is normal

RB1L189 = RB1_counter_snapshot[1] & (XE1L19 # !RB1_period_l_register[1] & XE1L20) # !RB1_counter_snapshot[1] & !RB1_period_l_register[1] & (XE1L20);

--J1_slave_readdata[1] is std_1c20:inst|clock_0:the_clock_0|slave_readdata[1] at LC_X44_Y28_N8

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

J1_slave_readdata[1]_lut_out = GND;

J1_slave_readdata[1] = DFFEAS(J1_slave_readdata[1]_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , J1_slave_readdata_p1[1], , , VCC);

--T1L471 is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|p1_registered_cpu_data_master_readdata[1]~2089 at LC_X46_Y28_N5

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

M1_slave_readdata[1]_qfbk = M1_slave_readdata[1];

T1L471 = S1L1743Q & (M1_slave_readdata[1]_qfbk) # !S1L1743Q & J1_slave_readdata[1] # !K1L6;

--M1_slave_readdata[1] is std_1c20:inst|clock_1:the_clock_1|slave_readdata[1] at LC_X46_Y28_N5

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

M1_slave_readdata[1] = DFFEAS(T1L471, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , M1_slave_readdata_p1[1], , , VCC);

--BB1_ien_AE is std_1c20:inst|jtag_uart:the_jtag_uart|ien_AE at LC_X46_Y24_N3

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

BB1_ien_AE_qfbk = BB1_ien_AE;

BB1_ien_AE_lut_out = BB1_read_0 & SE2_q_b[1] # !BB1_read_0 & (BB1_ien_AE_qfbk);

BB1_ien_AE = DFFEAS(BB1_ien_AE_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , BB1L61, S1_M_st_data[1], , , VCC);

--T1L501 is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|p1_registered_cpu_data_master_readdata~50 at LC_X46_Y24_N1

--operation mode is normal

T1L501 = BB1_read_0 & (SE2_q_b[1]) # !BB1_read_0 & BB1_ien_AE # !T1L521;

--DE1L276 is std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|p1_data_to_cpu[1]~875 at LC_X38_Y29_N3

--operation mode is normal

DE1L276 = DE1L252 & (DE1L218Q) # !DE1L252 & DE1_rx_holding_reg[1];

--CF1L16 is sld_hub:sld_hub_inst|sld_rom_sr:HUB_INFO_REG|Mux1~67 at LC_X59_Y18_N6

--operation mode is normal

CF1L16 = AMPP_FUNCTION(CF1_word_counter[3], CF1_word_counter[1], CF1_word_counter[4], CF1_word_counter[0]);

--CF1L17 is sld_hub:sld_hub_inst|sld_rom_sr:HUB_INFO_REG|Mux1~68 at LC_X59_Y18_N0

--operation mode is normal

CF1L17 = AMPP_FUNCTION(CF1_word_counter[3], CF1_word_counter[1], CF1_word_counter[4], CF1_word_counter[0]);

--CF1_WORD_SR[3] is sld_hub:sld_hub_inst|sld_rom_sr:HUB_INFO_REG|WORD_SR[3] at LC_X59_Y18_N8

--operation mode is normal

CF1_WORD_SR[3] = AMPP_FUNCTION(A1L5, FF1_state[4], CF1L18, CF1_clear_signal, altera_internal_jtag, VCC, CF1L25);

--SD1_internal_jdo1[0] is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|internal_jdo1[0] at LC_X54_Y16_N2

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

SD1_internal_jdo1[0] = AMPP_FUNCTION(A1L8, SD1_sr[0], VCC, GND, SD1L144);

--GD1_break_readreg[1] is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_break:the_cpu_nios2_oci_break|break_readreg[1] at LC_X51_Y16_N5

--operation mode is normal

GD1_break_readreg[1] = AMPP_FUNCTION(QC2__clk0, SD1_internal_jdo1[37], SD1L188, SD1_internal_jdo1[1], SD1_internal_jdo1[36], !C1_CLR_SIGNAL, SD1L188);

--SD1L129 is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|Mux38~14 at LC_X51_Y16_N9

--operation mode is normal

SD1L129 = AMPP_FUNCTION(SD1_ir[0], SD1_ir[1], RD1_internal_MonDReg[1], GD1_break_readreg[1]);

--SD1_sr[3] is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|sr[3] at LC_X52_Y16_N7

--operation mode is normal

SD1_sr[3] = AMPP_FUNCTION(A1L5, SD1L143, SD1L141, SD1L128, SD1_sr[4], !C1_CLR_SIGNAL, SD1L6);

--SD1_sr[25] is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|sr[25] at LC_X46_Y14_N4

--operation mode is normal

SD1_sr[25] = AMPP_FUNCTION(A1L5, SD1L35, SD1L34, SD1L70, SD1_sr[26], !C1_CLR_SIGNAL, SD1L12);

--GE1L19 is std_1c20:inst|jtag_uart:the_jtag_uart|alt_jtag_atlantic:jtag_uart_alt_jtag_atlantic|r_ena~1 at LC_X52_Y20_N4

--operation mode is normal

GE1L19 = AMPP_FUNCTION(GE1_r_ena1, GE1_rvalid0, BB1_r_val);

--GE1_read_write2 is std_1c20:inst|jtag_uart:the_jtag_uart|alt_jtag_atlantic:jtag_uart_alt_jtag_atlantic|read_write2 at LC_X52_Y21_N2

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

GE1_read_write2 = AMPP_FUNCTION(QC2__clk0, GE1_read_write1, F1_data_out, GND);

--GE1L2 is std_1c20:inst|jtag_uart:the_jtag_uart|alt_jtag_atlantic:jtag_uart_alt_jtag_atlantic|always2~2 at LC_X52_Y21_N8

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

GE1L2 = AMPP_FUNCTION(GE1_read_write2);

--GE1_read_write1 is std_1c20:inst|jtag_uart:the_jtag_uart|alt_jtag_atlantic:jtag_uart_alt_jtag_atlantic|read_write1 at LC_X52_Y21_N8

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

GE1_read_write1 = AMPP_FUNCTION(QC2__clk0, GE1_read_write, F1_data_out, GND);

--GE1_read_req is std_1c20:inst|jtag_uart:the_jtag_uart|alt_jtag_atlantic:jtag_uart_alt_jtag_atlantic|read_req at LC_X52_Y19_N9

--operation mode is normal

GE1_read_req = AMPP_FUNCTION(A1L5, GE1_td_shift[9], !C1_CLR_SIGNAL, GE1L72);

--GE1L72 is std_1c20:inst|jtag_uart:the_jtag_uart|alt_jtag_atlantic:jtag_uart_alt_jtag_atlantic|wdata[0]~7 at LC_X52_Y19_N6

--operation mode is normal

GE1L72 = AMPP_FUNCTION(GE1_count[1], GE1L69);

--GE1_td_shift[3] is std_1c20:inst|jtag_uart:the_jtag_uart|alt_jtag_atlantic:jtag_uart_alt_jtag_atlantic|td_shift[3] at LC_X53_Y20_N4

--operation mode is normal

GE1_td_shift[3] = AMPP_FUNCTION(A1L5, FF1_state[4], GE1L57, GE1L62, BF4_Q[0], !C1_CLR_SIGNAL, GE1L52);

--GE1L56 is std_1c20:inst|jtag_uart:the_jtag_uart|alt_jtag_atlantic:jtag_uart_alt_jtag_atlantic|td_shift[9]~3557 at LC_X53_Y20_N1

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

GE1L56 = AMPP_FUNCTION(GE1_count[9], GE1_td_shift[3]);

--GE1_rdata[0] is std_1c20:inst|jtag_uart:the_jtag_uart|alt_jtag_atlantic:jtag_uart_alt_jtag_atlantic|rdata[0] at LC_X53_Y20_N1

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

GE1_rdata[0] = AMPP_FUNCTION(QC2__clk0, SE1_q_b[0], F1_data_out, GND, GE1L18);

--GE1_count[7] is std_1c20:inst|jtag_uart:the_jtag_uart|alt_jtag_atlantic:jtag_uart_alt_jtag_atlantic|count[7] at LC_X54_Y20_N4

--operation mode is normal

GE1_count[7] = AMPP_FUNCTION(A1L5, GE1_count[6], FF1_state[4], !C1_CLR_SIGNAL, GE1L52);

--SE1_q_b[7] is std_1c20:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_w:the_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_jf21:auto_generated|a_dpfifo_ml21:dpfifo|dpram_j921:FIFOram|altsyncram_nll1:altsyncram1|q_b[7] at M4K_X49_Y20

--RAM Block Operation Mode: Simple Dual-Port

--Port A Depth: 64, Port A Width: 8, Port B Depth: 64, Port B Width: 8

--Port A Logical Depth: 64, Port A Logical Width: 8, Port B Logical Depth: 64, Port B Logical Width: 8

--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered

SE1_q_b[7]_PORT_A_data_in = BUS(S1_M_st_data[7], S1_M_st_data[0], S1_M_st_data[1], S1_M_st_data[4], S1_M_st_data[5], S1_M_st_data[6], S1_M_st_data[2], S1_M_st_data[3]);

SE1_q_b[7]_PORT_A_data_in_reg = DFFE(SE1_q_b[7]_PORT_A_data_in, SE1_q_b[7]_clock_0, , , SE1_q_b[7]_clock_enable_0);

SE1_q_b[7]_PORT_A_address = BUS(QE2_safe_q[0], QE2_safe_q[1], QE2_safe_q[2], QE2_safe_q[3], QE2_safe_q[4], QE2_safe_q[5]);

SE1_q_b[7]_PORT_A_address_reg = DFFE(SE1_q_b[7]_PORT_A_address, SE1_q_b[7]_clock_0, , , SE1_q_b[7]_clock_enable_0);

SE1_q_b[7]_PORT_B_address = BUS(QE1_safe_q[0], QE1_safe_q[1], QE1_safe_q[2], QE1_safe_q[3], QE1_safe_q[4], QE1_safe_q[5]);

SE1_q_b[7]_PORT_B_address_reg = DFFE(SE1_q_b[7]_PORT_B_address, SE1_q_b[7]_clock_1, , , SE1_q_b[7]_clock_enable_1);

SE1_q_b[7]_PORT_A_write_enable = VCC;

SE1_q_b[7]_PORT_A_write_enable_reg = DFFE(SE1_q_b[7]_PORT_A_write_enable, SE1_q_b[7]_clock_0, , , SE1_q_b[7]_clock_enable_0);

SE1_q_b[7]_PORT_B_read_enable = VCC;

SE1_q_b[7]_PORT_B_read_enable_reg = DFFE(SE1_q_b[7]_PORT_B_read_enable, SE1_q_b[7]_clock_1, , , SE1_q_b[7]_clock_enable_1);

SE1_q_b[7]_clock_0 = GLOBAL(QC2__clk0);

SE1_q_b[7]_clock_1 = GLOBAL(QC2__clk0);

SE1_q_b[7]_clock_enable_0 = BB1_fifo_wr;

SE1_q_b[7]_clock_enable_1 = BB1_rd_wfifo;

SE1_q_b[7]_PORT_B_data_out = MEMORY(SE1_q_b[7]_PORT_A_data_in_reg, , SE1_q_b[7]_PORT_A_address_reg, SE1_q_b[7]_PORT_B_address_reg, SE1_q_b[7]_PORT_A_write_enable_reg, SE1_q_b[7]_PORT_B_read_enable_reg, , , SE1_q_b[7]_clock_0, SE1_q_b[7]_clock_1, SE1_q_b[7]_clock_enable_0, SE1_q_b[7]_clock_enable_1, , );

SE1_q_b[7] = SE1_q_b[7]_PORT_B_data_out[0];

--SE1_q_b[3] is std_1c20:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_w:the_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_jf21:auto_generated|a_dpfifo_ml21:dpfifo|dpram_j921:FIFOram|altsyncram_nll1:altsyncram1|q_b[3] at M4K_X49_Y20

SE1_q_b[7]_PORT_A_data_in = BUS(S1_M_st_data[7], S1_M_st_data[0], S1_M_st_data[1], S1_M_st_data[4], S1_M_st_data[5], S1_M_st_data[6], S1_M_st_data[2], S1_M_st_data[3]);

SE1_q_b[7]_PORT_A_data_in_reg = DFFE(SE1_q_b[7]_PORT_A_data_in, SE1_q_b[7]_clock_0, , , SE1_q_b[7]_clock_enable_0);

SE1_q_b[7]_PORT_A_address = BUS(QE2_safe_q[0], QE2_safe_q[1], QE2_safe_q[2], QE2_safe_q[3], QE2_safe_q[4], QE2_safe_q[5]);

SE1_q_b[7]_PORT_A_address_reg = DFFE(SE1_q_b[7]_PORT_A_address, SE1_q_b[7]_clock_0, , , SE1_q_b[7]_clock_enable_0);

SE1_q_b[7]_PORT_B_address = BUS(QE1_safe_q[0], QE1_safe_q[1], QE1_safe_q[2], QE1_safe_q[3], QE1_safe_q[4], QE1_safe_q[5]);

SE1_q_b[7]_PORT_B_address_reg = DFFE(SE1_q_b[7]_PORT_B_address, SE1_q_b[7]_clock_1, , , SE1_q_b[7]_clock_enable_1);

SE1_q_b[7]_PORT_A_write_enable = VCC;

SE1_q_b[7]_PORT_A_write_enable_reg = DFFE(SE1_q_b[7]_PORT_A_write_enable, SE1_q_b[7]_clock_0, , , SE1_q_b[7]_clock_enable_0);

SE1_q_b[7]_PORT_B_read_enable = VCC;

SE1_q_b[7]_PORT_B_read_enable_reg = DFFE(SE1_q_b[7]_PORT_B_read_enable, SE1_q_b[7]_clock_1, , , SE1_q_b[7]_clock_enable_1);

SE1_q_b[7]_clock_0 = GLOBAL(QC2__clk0);

SE1_q_b[7]_clock_1 = GLOBAL(QC2__clk0);

SE1_q_b[7]_clock_enable_0 = BB1_fifo_wr;

SE1_q_b[7]_clock_enable_1 = BB1_rd_wfifo;

SE1_q_b[7]_PORT_B_data_out = MEMORY(SE1_q_b[7]_PORT_A_data_in_reg, , SE1_q_b[7]_PORT_A_address_reg, SE1_q_b[7]_PORT_B_address_reg, SE1_q_b[7]_PORT_A_write_enable_reg, SE1_q_b[7]_PORT_B_read_enable_reg, , , SE1_q_b[7]_clock_0, SE1_q_b[7]_clock_1, SE1_q_b[7]_clock_enable_0, SE1_q_b[7]_clock_enable_1, , );

SE1_q_b[3] = SE1_q_b[7]_PORT_B_data_out[7];

--SE1_q_b[2] is std_1c20:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_w:the_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_jf21:auto_generated|a_dpfifo_ml21:dpfifo|dpram_j921:FIFOram|altsyncram_nll1:altsyncram1|q_b[2] at M4K_X49_Y20

SE1_q_b[7]_PORT_A_data_in = BUS(S1_M_st_data[7], S1_M_st_data[0], S1_M_st_data[1], S1_M_st_data[4], S1_M_st_data[5], S1_M_st_data[6], S1_M_st_data[2], S1_M_st_data[3]);

SE1_q_b[7]_PORT_A_data_in_reg = DFFE(SE1_q_b[7]_PORT_A_data_in, SE1_q_b[7]_clock_0, , , SE1_q_b[7]_clock_enable_0);

SE1_q_b[7]_PORT_A_address = BUS(QE2_safe_q[0], QE2_safe_q[1], QE2_safe_q[2], QE2_safe_q[3], QE2_safe_q[4], QE2_safe_q[5]);

SE1_q_b[7]_PORT_A_address_reg = DFFE(SE1_q_b[7]_PORT_A_address, SE1_q_b[7]_clock_0, , , SE1_q_b[7]_clock_enable_0);

SE1_q_b[7]_PORT_B_address = BUS(QE1_safe_q[0], QE1_safe_q[1], QE1_safe_q[2], QE1_safe_q[3], QE1_safe_q[4], QE1_safe_q[5]);

SE1_q_b[7]_PORT_B_address_reg = DFFE(SE1_q_b[7]_PORT_B_address, SE1_q_b[7]_clock_1, , , SE1_q_b[7]_clock_enable_1);

SE1_q_b[7]_PORT_A_write_enable = VCC;

SE1_q_b[7]_PORT_A_write_enable_reg = DFFE(SE1_q_b[7]_PORT_A_write_enable, SE1_q_b[7]_clock_0, , , SE1_q_b[7]_clock_enable_0);

SE1_q_b[7]_PORT_B_read_enable = VCC;

SE1_q_b[7]_PORT_B_read_enable_reg = DFFE(SE1_q_b[7]_PORT_B_read_enable, SE1_q_b[7]_clock_1, , , SE1_q_b[7]_clock_enable_1);

SE1_q_b[7]_clock_0 = GLOBAL(QC2__clk0);

SE1_q_b[7]_clock_1 = GLOBAL(QC2__clk0);

SE1_q_b[7]_clock_enable_0 = BB1_fifo_wr;

SE1_q_b[7]_clock_enable_1 = BB1_rd_wfifo;

SE1_q_b[7]_PORT_B_data_out = MEMORY(SE1_q_b[7]_PORT_A_data_in_reg, , SE1_q_b[7]_PORT_A_address_reg, SE1_q_b[7]_PORT_B_address_reg, SE1_q_b[7]_PORT_A_write_enable_reg, SE1_q_b[7]_PORT_B_read_enable_reg, , , SE1_q_b[7]_clock_0, SE1_q_b[7]_clock_1, SE1_q_b[7]_clock_enable_0, SE1_q_b[7]_clock_enable_1, , );

SE1_q_b[2] = SE1_q_b[7]_PORT_B_data_out[6];

--SE1_q_b[6] is std_1c20:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_w:the_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_jf21:auto_generated|a_dpfifo_ml21:dpfifo|dpram_j921:FIFOram|altsyncram_nll1:altsyncram1|q_b[6] at M4K_X49_Y20

SE1_q_b[7]_PORT_A_data_in = BUS(S1_M_st_data[7], S1_M_st_data[0], S1_M_st_data[1], S1_M_st_data[4], S1_M_st_data[5], S1_M_st_data[6], S1_M_st_data[2], S1_M_st_data[3]);

SE1_q_b[7]_PORT_A_data_in_reg = DFFE(SE1_q_b[7]_PORT_A_data_in, SE1_q_b[7]_clock_0, , , SE1_q_b[7]_clock_enable_0);

SE1_q_b[7]_PORT_A_address = BUS(QE2_safe_q[0], QE2_safe_q[1], QE2_safe_q[2], QE2_safe_q[3], QE2_safe_q[4], QE2_safe_q[5]);

SE1_q_b[7]_PORT_A_address_reg = DFFE(SE1_q_b[7]_PORT_A_address, SE1_q_b[7]_clock_0, , , SE1_q_b[7]_clock_enable_0);

SE1_q_b[7]_PORT_B_address = BUS(QE1_safe_q[0], QE1_safe_q[1], QE1_safe_q[2], QE1_safe_q[3], QE1_safe_q[4], QE1_safe_q[5]);

SE1_q_b[7]_PORT_B_address_reg = DFFE(SE1_q_b[7]_PORT_B_address, SE1_q_b[7]_clock_1, , , SE1_q_b[7]_clock_enable_1);

SE1_q_b[7]_PORT_A_write_enable = VCC;

SE1_q_b[7]_PORT_A_write_enable_reg = DFFE(SE1_q_b[7]_PORT_A_write_enable, SE1_q_b[7]_clock_0, , , SE1_q_b[7]_clock_enable_0);

SE1_q_b[7]_PORT_B_read_enable = VCC;

SE1_q_b[7]_PORT_B_read_enable_reg = DFFE(SE1_q_b[7]_PORT_B_read_enable, SE1_q_b[7]_clock_1, , , SE1_q_b[7]_clock_enable_1);

SE1_q_b[7]_clock_0 = GLOBAL(QC2__clk0);

SE1_q_b[7]_clock_1 = GLOBAL(QC2__clk0);

SE1_q_b[7]_clock_enable_0 = BB1_fifo_wr;

SE1_q_b[7]_clock_enable_1 = BB1_rd_wfifo;

SE1_q_b[7]_PORT_B_data_out = MEMORY(SE1_q_b[7]_PORT_A_data_in_reg, , SE1_q_b[7]_PORT_A_address_reg, SE1_q_b[7]_PORT_B_address_reg, SE1_q_b[7]_PORT_A_write_enable_reg, SE1_q_b[7]_PORT_B_read_enable_reg, , , SE1_q_b[7]_clock_0, SE1_q_b[7]_clock_1, SE1_q_b[7]_clock_enable_0, SE1_q_b[7]_clock_enable_1, , );

SE1_q_b[6] = SE1_q_b[7]_PORT_B_data_out[5];

--SE1_q_b[5] is std_1c20:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_w:the_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_jf21:auto_generated|a_dpfifo_ml21:dpfifo|dpram_j921:FIFOram|altsyncram_nll1:altsyncram1|q_b[5] at M4K_X49_Y20

SE1_q_b[7]_PORT_A_data_in = BUS(S1_M_st_data[7], S1_M_st_data[0], S1_M_st_data[1], S1_M_st_data[4], S1_M_st_data[5], S1_M_st_data[6], S1_M_st_data[2], S1_M_st_data[3]);

SE1_q_b[7]_PORT_A_data_in_reg = DFFE(SE1_q_b[7]_PORT_A_data_in, SE1_q_b[7]_clock_0, , , SE1_q_b[7]_clock_enable_0);

SE1_q_b[7]_PORT_A_address = BUS(QE2_safe_q[0], QE2_safe_q[1], QE2_safe_q[2], QE2_safe_q[3], QE2_safe_q[4], QE2_safe_q[5]);

SE1_q_b[7]_PORT_A_address_reg = DFFE(SE1_q_b[7]_PORT_A_address, SE1_q_b[7]_clock_0, , , SE1_q_b[7]_clock_enable_0);

SE1_q_b[7]_PORT_B_address = BUS(QE1_safe_q[0], QE1_safe_q[1], QE1_safe_q[2], QE1_safe_q[3], QE1_safe_q[4], QE1_safe_q[5]);

SE1_q_b[7]_PORT_B_address_reg = DFFE(SE1_q_b[7]_PORT_B_address, SE1_q_b[7]_clock_1, , , SE1_q_b[7]_clock_enable_1);

SE1_q_b[7]_PORT_A_write_enable = VCC;

SE1_q_b[7]_PORT_A_write_enable_reg = DFFE(SE1_q_b[7]_PORT_A_write_enable, SE1_q_b[7]_clock_0, , , SE1_q_b[7]_clock_enable_0);

SE1_q_b[7]_PORT_B_read_enable = VCC;

SE1_q_b[7]_PORT_B_read_enable_reg = DFFE(SE1_q_b[7]_PORT_B_read_enable, SE1_q_b[7]_clock_1, , , SE1_q_b[7]_clock_enable_1);

SE1_q_b[7]_clock_0 = GLOBAL(QC2__clk0);

SE1_q_b[7]_clock_1 = GLOBAL(QC2__clk0);

SE1_q_b[7]_clock_enable_0 = BB1_fifo_wr;

SE1_q_b[7]_clock_enable_1 = BB1_rd_wfifo;

SE1_q_b[7]_PORT_B_data_out = MEMORY(SE1_q_b[7]_PORT_A_data_in_reg, , SE1_q_b[7]_PORT_A_address_reg, SE1_q_b[7]_PORT_B_address_reg, SE1_q_b[7]_PORT_A_write_enable_reg, SE1_q_b[7]_PORT_B_read_enable_reg, , , SE1_q_b[7]_clock_0, SE1_q_b[7]_clock_1, SE1_q_b[7]_clock_enable_0, SE1_q_b[7]_clock_enable_1, , );

SE1_q_b[5] = SE1_q_b[7]_PORT_B_data_out[4];

--SE1_q_b[4] is std_1c20:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_w:the_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_jf21:auto_generated|a_dpfifo_ml21:dpfifo|dpram_j921:FIFOram|altsyncram_nll1:altsyncram1|q_b[4] at M4K_X49_Y20

SE1_q_b[7]_PORT_A_data_in = BUS(S1_M_st_data[7], S1_M_st_data[0], S1_M_st_data[1], S1_M_st_data[4], S1_M_st_data[5], S1_M_st_data[6], S1_M_st_data[2], S1_M_st_data[3]);

SE1_q_b[7]_PORT_A_data_in_reg = DFFE(SE1_q_b[7]_PORT_A_data_in, SE1_q_b[7]_clock_0, , , SE1_q_b[7]_clock_enable_0);

SE1_q_b[7]_PORT_A_address = BUS(QE2_safe_q[0], QE2_safe_q[1], QE2_safe_q[2], QE2_safe_q[3], QE2_safe_q[4], QE2_safe_q[5]);

SE1_q_b[7]_PORT_A_address_reg = DFFE(SE1_q_b[7]_PORT_A_address, SE1_q_b[7]_clock_0, , , SE1_q_b[7]_clock_enable_0);

SE1_q_b[7]_PORT_B_address = BUS(QE1_safe_q[0], QE1_safe_q[1], QE1_safe_q[2], QE1_safe_q[3], QE1_safe_q[4], QE1_safe_q[5]);

SE1_q_b[7]_PORT_B_address_reg = DFFE(SE1_q_b[7]_PORT_B_address, SE1_q_b[7]_clock_1, , , SE1_q_b[7]_clock_enable_1);

SE1_q_b[7]_PORT_A_write_enable = VCC;

SE1_q_b[7]_PORT_A_write_enable_reg = DFFE(SE1_q_b[7]_PORT_A_write_enable, SE1_q_b[7]_clock_0, , , SE1_q_b[7]_clock_enable_0);

SE1_q_b[7]_PORT_B_read_enable = VCC;

SE1_q_b[7]_PORT_B_read_enable_reg = DFFE(SE1_q_b[7]_PORT_B_read_enable, SE1_q_b[7]_clock_1, , , SE1_q_b[7]_clock_enable_1);

SE1_q_b[7]_clock_0 = GLOBAL(QC2__clk0);

SE1_q_b[7]_clock_1 = GLOBAL(QC2__clk0);

SE1_q_b[7]_clock_enable_0 = BB1_fifo_wr;

SE1_q_b[7]_clock_enable_1 = BB1_rd_wfifo;

SE1_q_b[7]_PORT_B_data_out = MEMORY(SE1_q_b[7]_PORT_A_data_in_reg, , SE1_q_b[7]_PORT_A_address_reg, SE1_q_b[7]_PORT_B_address_reg, SE1_q_b[7]_PORT_A_write_enable_reg, SE1_q_b[7]_PORT_B_read_enable_reg, , , SE1_q_b[7]_clock_0, SE1_q_b[7]_clock_1, SE1_q_b[7]_clock_enable_0, SE1_q_b[7]_clock_enable_1, , );

SE1_q_b[4] = SE1_q_b[7]_PORT_B_data_out[3];

--SE1_q_b[1] is std_1c20:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_w:the_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_jf21:auto_generated|a_dpfifo_ml21:dpfifo|dpram_j921:FIFOram|altsyncram_nll1:altsyncram1|q_b[1] at M4K_X49_Y20

SE1_q_b[7]_PORT_A_data_in = BUS(S1_M_st_data[7], S1_M_st_data[0], S1_M_st_data[1], S1_M_st_data[4], S1_M_st_data[5], S1_M_st_data[6], S1_M_st_data[2], S1_M_st_data[3]);

SE1_q_b[7]_PORT_A_data_in_reg = DFFE(SE1_q_b[7]_PORT_A_data_in, SE1_q_b[7]_clock_0, , , SE1_q_b[7]_clock_enable_0);

SE1_q_b[7]_PORT_A_address = BUS(QE2_safe_q[0], QE2_safe_q[1], QE2_safe_q[2], QE2_safe_q[3], QE2_safe_q[4], QE2_safe_q[5]);

SE1_q_b[7]_PORT_A_address_reg = DFFE(SE1_q_b[7]_PORT_A_address, SE1_q_b[7]_clock_0, , , SE1_q_b[7]_clock_enable_0);

SE1_q_b[7]_PORT_B_address = BUS(QE1_safe_q[0], QE1_safe_q[1], QE1_safe_q[2], QE1_safe_q[3], QE1_safe_q[4], QE1_safe_q[5]);

SE1_q_b[7]_PORT_B_address_reg = DFFE(SE1_q_b[7]_PORT_B_address, SE1_q_b[7]_clock_1, , , SE1_q_b[7]_clock_enable_1);

SE1_q_b[7]_PORT_A_write_enable = VCC;

SE1_q_b[7]_PORT_A_write_enable_reg = DFFE(SE1_q_b[7]_PORT_A_write_enable, SE1_q_b[7]_clock_0, , , SE1_q_b[7]_clock_enable_0);

SE1_q_b[7]_PORT_B_read_enable = VCC;

SE1_q_b[7]_PORT_B_read_enable_reg = DFFE(SE1_q_b[7]_PORT_B_read_enable, SE1_q_b[7]_clock_1, , , SE1_q_b[7]_clock_enable_1);

SE1_q_b[7]_clock_0 = GLOBAL(QC2__clk0);

SE1_q_b[7]_clock_1 = GLOBAL(QC2__clk0);

SE1_q_b[7]_clock_enable_0 = BB1_fifo_wr;

SE1_q_b[7]_clock_enable_1 = BB1_rd_wfifo;

SE1_q_b[7]_PORT_B_data_out = MEMORY(SE1_q_b[7]_PORT_A_data_in_reg, , SE1_q_b[7]_PORT_A_address_reg, SE1_q_b[7]_PORT_B_address_reg, SE1_q_b[7]_PORT_A_write_enable_reg, SE1_q_b[7]_PORT_B_read_enable_reg, , , SE1_q_b[7]_clock_0, SE1_q_b[7]_clock_1, SE1_q_b[7]_clock_enable_0, SE1_q_b[7]_clock_enable_1, , );

SE1_q_b[1] = SE1_q_b[7]_PORT_B_data_out[2];

--SE1_q_b[0] is std_1c20:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_w:the_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_jf21:auto_generated|a_dpfifo_ml21:dpfifo|dpram_j921:FIFOram|altsyncram_nll1:altsyncram1|q_b[0] at M4K_X49_Y20

SE1_q_b[7]_PORT_A_data_in = BUS(S1_M_st_data[7], S1_M_st_data[0], S1_M_st_data[1], S1_M_st_data[4], S1_M_st_data[5], S1_M_st_data[6], S1_M_st_data[2], S1_M_st_data[3]);

SE1_q_b[7]_PORT_A_data_in_reg = DFFE(SE1_q_b[7]_PORT_A_data_in, SE1_q_b[7]_clock_0, , , SE1_q_b[7]_clock_enable_0);

SE1_q_b[7]_PORT_A_address = BUS(QE2_safe_q[0], QE2_safe_q[1], QE2_safe_q[2], QE2_safe_q[3], QE2_safe_q[4], QE2_safe_q[5]);

SE1_q_b[7]_PORT_A_address_reg = DFFE(SE1_q_b[7]_PORT_A_address, SE1_q_b[7]_clock_0, , , SE1_q_b[7]_clock_enable_0);

SE1_q_b[7]_PORT_B_address = BUS(QE1_safe_q[0], QE1_safe_q[1], QE1_safe_q[2], QE1_safe_q[3], QE1_safe_q[4], QE1_safe_q[5]);

SE1_q_b[7]_PORT_B_address_reg = DFFE(SE1_q_b[7]_PORT_B_address, SE1_q_b[7]_clock_1, , , SE1_q_b[7]_clock_enable_1);

SE1_q_b[7]_PORT_A_write_enable = VCC;

SE1_q_b[7]_PORT_A_write_enable_reg = DFFE(SE1_q_b[7]_PORT_A_write_enable, SE1_q_b[7]_clock_0, , , SE1_q_b[7]_clock_enable_0);

SE1_q_b[7]_PORT_B_read_enable = VCC;

SE1_q_b[7]_PORT_B_read_enable_reg = DFFE(SE1_q_b[7]_PORT_B_read_enable, SE1_q_b[7]_clock_1, , , SE1_q_b[7]_clock_enable_1);

SE1_q_b[7]_clock_0 = GLOBAL(QC2__clk0);

SE1_q_b[7]_clock_1 = GLOBAL(QC2__clk0);

SE1_q_b[7]_clock_enable_0 = BB1_fifo_wr;

SE1_q_b[7]_clock_enable_1 = BB1_rd_wfifo;

SE1_q_b[7]_PORT_B_data_out = MEMORY(SE1_q_b[7]_PORT_A_data_in_reg, , SE1_q_b[7]_PORT_A_address_reg, SE1_q_b[7]_PORT_B_address_reg, SE1_q_b[7]_PORT_A_write_enable_reg, SE1_q_b[7]_PORT_B_read_enable_reg, , , SE1_q_b[7]_clock_0, SE1_q_b[7]_clock_1, SE1_q_b[7]_clock_enable_0, SE1_q_b[7]_clock_enable_1, , );

SE1_q_b[0] = SE1_q_b[7]_PORT_B_data_out[1];

--GE1L18 is std_1c20:inst|jtag_uart:the_jtag_uart|alt_jtag_atlantic:jtag_uart_alt_jtag_atlantic|r_ena~0 at LC_X52_Y20_N8

--operation mode is normal

GE1L18 = AMPP_FUNCTION(GE1_r_ena1, BB1_r_val);

--S1L820 is std_1c20:inst|cpu:the_cpu|E_logic_result[30]~15617 at LC_X34_Y14_N3

--operation mode is normal

S1L820 = AMPP_FUNCTION(S1L883, S1_E_logic_op[0], S1L1065, S1_E_logic_op[1]);

--S1_E_src1_prelim[29] is std_1c20:inst|cpu:the_cpu|E_src1_prelim[29] at LC_X44_Y15_N6

--operation mode is normal

S1_E_src1_prelim[29] = AMPP_FUNCTION(QC2__clk0, CD1_q_b[29], S1_W_wr_data[29], S1L2479, S1_D_src1_hazard_W, F1_data_out, S1_D_src1_hazard_M, S1_W_stall);

--S1L882 is std_1c20:inst|cpu:the_cpu|E_src1[29]~2046 at LC_X44_Y14_N8

--operation mode is normal

S1L882 = AMPP_FUNCTION(S1_E_src1_prelim[29], S1L2477, S1L223Q, S1L886Q);

--S1_E_src2_imm[29] is std_1c20:inst|cpu:the_cpu|E_src2_imm[29] at LC_X38_Y14_N6

--operation mode is normal

S1_E_src2_imm[29] = AMPP_FUNCTION(QC2__clk0, S1_D_iw[19], S1L311, S1_D_iw[21], S1L301, F1_data_out, S1_W_stall);

--S1L1060 is std_1c20:inst|cpu:the_cpu|E_src2[29]~1533 at LC_X44_Y14_N4

--operation mode is normal

S1L1060 = AMPP_FUNCTION(S1L1062, S1L2477, S1L223Q, S1L1064);

--YC1_result[28] is std_1c20:inst|cpu:the_cpu|lpm_add_sub:Add8|alt_stratix_add_sub:stratix_adder|result[28] at LC_X36_Y14_N8

--operation mode is arithmetic

YC1_result[28] = AMPP_FUNCTION(S1L1055, S1L881, YC1L71, YC1L79, YC1L80, S1_E_ctrl_alu_subtract);

--YC1L82 is std_1c20:inst|cpu:the_cpu|lpm_add_sub:Add8|alt_stratix_add_sub:stratix_adder|add_sub_cell[28]~COUT at LC_X36_Y14_N8

--operation mode is arithmetic

YC1L82 = AMPP_FUNCTION(S1L1055, S1L881, YC1L79, S1_E_ctrl_alu_subtract);

--YC1L83 is std_1c20:inst|cpu:the_cpu|lpm_add_sub:Add8|alt_stratix_add_sub:stratix_adder|add_sub_cell[28]~COUTCOUT1_1341 at LC_X36_Y14_N8

--operation mode is arithmetic

YC1L83 = AMPP_FUNCTION(S1L1055, S1L881, YC1L80, S1_E_ctrl_alu_subtract);

--S1_E_src2_imm[28] is std_1c20:inst|cpu:the_cpu|E_src2_imm[28] at LC_X40_Y13_N9

--operation mode is normal

S1_E_src2_imm[28] = AMPP_FUNCTION(QC2__clk0, S1_D_iw[18], S1_D_iw[21], S1L311, S1L301, F1_data_out, S1_W_stall);

--S1L1055 is std_1c20:inst|cpu:the_cpu|E_src2[28]~1534 at LC_X42_Y13_N8

--operation mode is normal

S1L1055 = AMPP_FUNCTION(S1L1057, S1L220Q, S1L1059, S1L2474);

--WE1L54 is std_1c20:inst|sdram_s1_arbitrator:the_sdram_s1|rdv_fifo_for_cpu_instruction_master_to_sdram_s1_module:rdv_fifo_for_cpu_instruction_master_to_sdram_s1|stage_4~5 at LC_X22_Y25_N5

--operation mode is normal

WE1L54 = WE1_full_5 & (WE1L57Q) # !WE1_full_5 & NB1L24;

--WE1_full_4 is std_1c20:inst|sdram_s1_arbitrator:the_sdram_s1|rdv_fifo_for_cpu_instruction_master_to_sdram_s1_module:rdv_fifo_for_cpu_instruction_master_to_sdram_s1|full_4 at LC_X23_Y26_N6

--operation mode is normal

WE1_full_4_lut_out = NB1L37 & (WE1_full_3) # !NB1L37 & (KB1_za_valid & WE1_full_5 # !KB1_za_valid & (WE1_full_3));

WE1_full_4 = DFFEAS(WE1_full_4_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , VE1L22, , , , );

--WE1L29 is std_1c20:inst|sdram_s1_arbitrator:the_sdram_s1|rdv_fifo_for_cpu_instruction_master_to_sdram_s1_module:rdv_fifo_for_cpu_instruction_master_to_sdram_s1|process6~1 at LC_X23_Y25_N1

--operation mode is normal

WE1L29 = KB1_za_valid # !WE1_full_3 & NB1L37;

--LC1L10 is std_1c20:inst|clock_1:the_clock_1|clock_1_master_FSM:master_FSM|Mux1~126 at LC_X48_Y28_N5

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

MC3_data_in_d1_qfbk = MC3_data_in_d1;

LC1L10 = !LC1_master_state[1] & !LC1_master_state[0] & (HC1_data_out $ MC3_data_in_d1_qfbk);

--MC3_data_in_d1 is std_1c20:inst|clock_1:the_clock_1|clock_1_edge_to_pulse:read_request_edge_to_pulse|data_in_d1 at LC_X48_Y28_N5

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

MC3_data_in_d1 = DFFEAS(LC1L10, GLOBAL(PLD_CLOCKINPUT[1]), E1_data_out, , , HC1_data_out, , , VCC);

--JC1_data_out is std_1c20:inst|clock_1:the_clock_1|clock_1_slave_write_request_sync_module:clock_1_slave_write_request_sync|data_out at LC_X48_Y28_N7

--operation mode is normal

JC1_data_out_lut_out = JC1_data_in_d1;

JC1_data_out = DFFEAS(JC1_data_out_lut_out, GLOBAL(PLD_CLOCKINPUT[1]), E1_data_out, , , , , , );

--LC1L9 is std_1c20:inst|clock_1:the_clock_1|clock_1_master_FSM:master_FSM|Mux0~178 at LC_X48_Y28_N1

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

HC1_data_out_qfbk = HC1_data_out;

LC1L9 = LC1_master_state[2] # LC1_master_state[1] # HC1_data_out_qfbk $ MC3_data_in_d1;

--HC1_data_out is std_1c20:inst|clock_1:the_clock_1|clock_1_slave_read_request_sync_module:clock_1_slave_read_request_sync|data_out at LC_X48_Y28_N1

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

HC1_data_out = DFFEAS(LC1L9, GLOBAL(PLD_CLOCKINPUT[1]), E1_data_out, , , HC1_data_in_d1, , , VCC);

--LC1L11 is std_1c20:inst|clock_1:the_clock_1|clock_1_master_FSM:master_FSM|Mux2~236 at LC_X48_Y28_N9

--operation mode is normal

LC1L11 = LC1_master_state[2] # LC1_master_state[1] & (R1_d1_reasons_to_wait # !LC1_master_state[0]);

--LC1L12 is std_1c20:inst|clock_1:the_clock_1|clock_1_master_FSM:master_FSM|Mux2~237 at LC_X48_Y28_N8

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

MC4_data_in_d1_qfbk = MC4_data_in_d1;

LC1L12 = JC1_data_out & MC4_data_in_d1_qfbk & (MC3_data_in_d1 $ !HC1_data_out) # !JC1_data_out & !MC4_data_in_d1_qfbk & (MC3_data_in_d1 $ !HC1_data_out);

--MC4_data_in_d1 is std_1c20:inst|clock_1:the_clock_1|clock_1_edge_to_pulse:write_request_edge_to_pulse|data_in_d1 at LC_X48_Y28_N8

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

MC4_data_in_d1 = DFFEAS(LC1L12, GLOBAL(PLD_CLOCKINPUT[1]), E1_data_out, , , JC1_data_out, , , VCC);

--E1_data_in_d1 is std_1c20:inst|std_1c20_reset_PLD_CLOCKINPUT_domain_synch_module:std_1c20_reset_PLD_CLOCKINPUT_domain_synch|data_in_d1 at LC_X48_Y28_N4

--operation mode is normal

E1_data_in_d1_lut_out = VCC;

E1_data_in_d1 = DFFEAS(E1_data_in_d1_lut_out, GLOBAL(PLD_CLOCKINPUT[1]), !B1L1, , , , , , );

--CC1L10 is std_1c20:inst|clock_0:the_clock_0|clock_0_master_FSM:master_FSM|Mux1~126 at LC_X43_Y28_N5

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

DC3_data_in_d1_qfbk = DC3_data_in_d1;

CC1L10 = !CC1_master_state[1] & !CC1_master_state[0] & (ZB1_data_out $ DC3_data_in_d1_qfbk);

--DC3_data_in_d1 is std_1c20:inst|clock_0:the_clock_0|clock_0_edge_to_pulse:read_request_edge_to_pulse|data_in_d1 at LC_X43_Y28_N5

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

DC3_data_in_d1 = DFFEAS(CC1L10, GLOBAL(PLD_CLKFB), GLOBAL(D1_data_out), , , ZB1_data_out, , , VCC);

--AC1_data_out is std_1c20:inst|clock_0:the_clock_0|clock_0_slave_write_request_sync_module:clock_0_slave_write_request_sync|data_out at LC_X43_Y28_N9

--operation mode is normal

AC1_data_out_lut_out = AC1_data_in_d1;

AC1_data_out = DFFEAS(AC1_data_out_lut_out, GLOBAL(PLD_CLKFB), GLOBAL(D1_data_out), , , , , , );

--CC1L9 is std_1c20:inst|clock_0:the_clock_0|clock_0_master_FSM:master_FSM|Mux0~173 at LC_X43_Y28_N0

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

ZB1_data_out_qfbk = ZB1_data_out;

CC1L9 = CC1_master_state[2] # CC1_master_state[1] # ZB1_data_out_qfbk $ DC3_data_in_d1;

--ZB1_data_out is std_1c20:inst|clock_0:the_clock_0|clock_0_slave_read_request_sync_module:clock_0_slave_read_request_sync|data_out at LC_X43_Y28_N0

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

ZB1_data_out = DFFEAS(CC1L9, GLOBAL(PLD_CLKFB), GLOBAL(D1_data_out), , , ZB1_data_in_d1, , , VCC);

--CC1L11 is std_1c20:inst|clock_0:the_clock_0|clock_0_master_FSM:master_FSM|Mux2~236 at LC_X43_Y28_N8

--operation mode is normal

CC1L11 = CC1_master_state[2] # CC1_master_state[1] & (MB1_d1_reasons_to_wait # !CC1_master_state[0]);

--CC1L12 is std_1c20:inst|clock_0:the_clock_0|clock_0_master_FSM:master_FSM|Mux2~237 at LC_X43_Y28_N6

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

DC4_data_in_d1_qfbk = DC4_data_in_d1;

CC1L12 = AC1_data_out & DC4_data_in_d1_qfbk & (ZB1_data_out $ !DC3_data_in_d1) # !AC1_data_out & !DC4_data_in_d1_qfbk & (ZB1_data_out $ !DC3_data_in_d1);

--DC4_data_in_d1 is std_1c20:inst|clock_0:the_clock_0|clock_0_edge_to_pulse:write_request_edge_to_pulse|data_in_d1 at LC_X43_Y28_N6

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

DC4_data_in_d1 = DFFEAS(CC1L12, GLOBAL(PLD_CLKFB), GLOBAL(D1_data_out), , , AC1_data_out, , , VCC);

--D1_data_in_d1 is std_1c20:inst|std_1c20_reset_PLD_CLKFB_domain_synch_module:std_1c20_reset_PLD_CLKFB_domain_synch|data_in_d1 at LC_X61_Y16_N2

--operation mode is normal

D1_data_in_d1_lut_out = VCC;

D1_data_in_d1 = DFFEAS(D1_data_in_d1_lut_out, GLOBAL(PLD_CLKFB), !B1L1, , , , , , );

--VE1L41 is std_1c20:inst|sdram_s1_arbitrator:the_sdram_s1|rdv_fifo_for_cpu_data_master_to_sdram_s1_module:rdv_fifo_for_cpu_data_master_to_sdram_s1|stage_4~7021 at LC_X22_Y25_N0

--operation mode is normal

VE1L41 = WE1_full_5 & VE1L44Q # !WE1_full_5 & (NB1L20);

--GD1_break_readreg[22] is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_break:the_cpu_nios2_oci_break|break_readreg[22] at LC_X48_Y16_N2

--operation mode is normal

GD1_break_readreg[22] = AMPP_FUNCTION(QC2__clk0, SD1L188, SD1_internal_jdo1[37], SD1_internal_jdo1[36], SD1_internal_jdo1[22], !C1_CLR_SIGNAL, SD1L188);

--SD1L31 is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|DRsize[0]~20005 at LC_X46_Y16_N0

--operation mode is normal

SD1L31 = AMPP_FUNCTION(RD1_internal_MonDReg[22], GD1_break_readreg[22], SD1_ir[1]);

--SD1L32 is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|DRsize[0]~20006 at LC_X46_Y16_N6

--operation mode is normal

SD1L32 = AMPP_FUNCTION(SD1L144, SD1_ir[0], SD1L142, SD1L31);

--SD1_sr[24] is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|sr[24] at LC_X46_Y14_N9

--operation mode is normal

SD1_sr[24] = AMPP_FUNCTION(A1L5, SD1L38, SD1L9, SD1_sr[25], SD1L37, !C1_CLR_SIGNAL, SD1L12);

--SD1L33 is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|DRsize[0]~20007 at LC_X46_Y16_N5

--operation mode is normal

SD1L33 = AMPP_FUNCTION(SD1L144, SD1L31, A1L4, SD1_ir[0]);

--U1L247 is std_1c20:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|process3~0 at LC_X37_Y25_N1

--operation mode is normal

U1L247 = !U1_cpu_instruction_master_dbs_rdv_counter[1] & Y1_cpu_instruction_master_read_data_valid_ext_flash_s1_shift_register[1] & U1_cpu_instruction_master_dbs_rdv_counter[0];

--GE1L38 is std_1c20:inst|jtag_uart:the_jtag_uart|alt_jtag_atlantic:jtag_uart_alt_jtag_atlantic|t_pause~74 at LC_X52_Y19_N7

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

GE1L38 = AMPP_FUNCTION(BB1_t_dav, GE1_write_stalled);

--GE1_write_valid is std_1c20:inst|jtag_uart:the_jtag_uart|alt_jtag_atlantic:jtag_uart_alt_jtag_atlantic|write_valid at LC_X52_Y19_N7

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

GE1_write_valid = AMPP_FUNCTION(A1L5, GE1_td_shift[10], !C1_CLR_SIGNAL, GND, GE1L72);

--GE1_jupdate1 is std_1c20:inst|jtag_uart:the_jtag_uart|alt_jtag_atlantic:jtag_uart_alt_jtag_atlantic|jupdate1 at LC_X52_Y21_N4

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

GE1_jupdate1 = AMPP_FUNCTION(QC2__clk0, GE1_jupdate, F1_data_out, GND);

--GE1_jupdate2 is std_1c20:inst|jtag_uart:the_jtag_uart|alt_jtag_atlantic:jtag_uart_alt_jtag_atlantic|jupdate2 at LC_X52_Y21_N5

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

GE1_jupdate2 = AMPP_FUNCTION(QC2__clk0, GE1_jupdate1, F1_data_out, GND);

--RB1_force_reload is std_1c20:inst|sys_clk_timer:the_sys_clk_timer|force_reload at LC_X47_Y23_N1

--operation mode is normal

RB1_force_reload_lut_out = XE1L22 & SB1_cpu_data_master_requests_sys_clk_timer_s1 & S1_internal_d_write & !T1_internal_cpu_data_master_waitrequest;

RB1_force_reload = DFFEAS(RB1_force_reload_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--RB1L183 is std_1c20:inst|sys_clk_timer:the_sys_clk_timer|process0~1 at LC_X53_Y23_N6

--operation mode is normal

RB1L183 = RB1_force_reload # RB1L51 & (RB1L56);

--RB1L182 is std_1c20:inst|sys_clk_timer:the_sys_clk_timer|process0~0 at LC_X52_Y23_N5

--operation mode is normal

RB1L182 = RB1_counter_is_running # RB1_force_reload;

--U1L246 is std_1c20:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|process2~0 at LC_X37_Y25_N4

--operation mode is normal

U1L246 = !U1_cpu_instruction_master_dbs_rdv_counter[1] & Y1_cpu_instruction_master_read_data_valid_ext_flash_s1_shift_register[1] & !U1_cpu_instruction_master_dbs_rdv_counter[0];

--YE1_do_start_rx is std_1c20:inst|uart1:the_uart1|uart1_rx:the_uart1_rx|do_start_rx at LC_X57_Y22_N6

--operation mode is normal

YE1_do_start_rx_lut_out = !YE1_unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[0] & !YE1_sync_rxd & YE1_delayed_unxsync_rxdxx2;

YE1_do_start_rx = DFFEAS(YE1_do_start_rx_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--YE1_baud_clk_en is std_1c20:inst|uart1:the_uart1|uart1_rx:the_uart1_rx|baud_clk_en at LC_X57_Y22_N2

--operation mode is normal

YE1_baud_clk_en_lut_out = !YE1_rxd_edge & YE1L46 & !YE1_baud_rate_counter[8] & YE1L45;

YE1_baud_clk_en = DFFEAS(YE1_baud_clk_en_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--YE1L72 is std_1c20:inst|uart1:the_uart1|uart1_rx:the_uart1_rx|unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[3]~7355 at LC_X53_Y22_N2

--operation mode is normal

YE1L72 = YE1_do_start_rx # YE1_baud_clk_en & YE1_unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[0];

--YE1L1 is std_1c20:inst|uart1:the_uart1|uart1_rx:the_uart1_rx|A_WE_StdLogicVector~26 at LC_X57_Y22_N8

--operation mode is normal

YE1L1 = YE1_unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[0] & YE1_baud_clk_en;

--M1_master_nativeaddress[0] is std_1c20:inst|clock_1:the_clock_1|master_nativeaddress[0] at LC_X48_Y29_N0

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

M1_master_nativeaddress[0]_lut_out = GND;

M1_master_nativeaddress[0] = DFFEAS(M1_master_nativeaddress[0]_lut_out, GLOBAL(PLD_CLOCKINPUT[1]), E1_data_out, , , M1_slave_nativeaddress_d1[0], , , VCC);

--Q1_control_reg_out[2] is std_1c20:inst|connector_pll:the_connector_pll|control_reg_out[2] at LC_X46_Y30_N6

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

Q1_control_reg_out[2]_lut_out = GND;

Q1_control_reg_out[2] = DFFEAS(Q1_control_reg_out[2]_lut_out, GLOBAL(PLD_CLOCKINPUT[1]), E1_data_out, , Q1L1, M1_master_writedata[2], , , VCC);

--M1L22 is std_1c20:inst|clock_1:the_clock_1|process0~11 at LC_X47_Y29_N2

--operation mode is normal

M1L22 = LC1_master_state[1] & R1_d1_reasons_to_wait;

--J1_master_nativeaddress[0] is std_1c20:inst|clock_0:the_clock_0|master_nativeaddress[0] at LC_X43_Y29_N2

--operation mode is normal

J1_master_nativeaddress[0]_lut_out = J1_slave_nativeaddress_d1[0];

J1_master_nativeaddress[0] = DFFEAS(J1_master_nativeaddress[0]_lut_out, GLOBAL(PLD_CLKFB), GLOBAL(D1_data_out), , , , , , );

--LB1_control_reg_out[2] is std_1c20:inst|sdram_pll:the_sdram_pll|control_reg_out[2] at LC_X45_Y29_N6

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

LB1_control_reg_out[2]_lut_out = GND;

LB1_control_reg_out[2] = DFFEAS(LB1_control_reg_out[2]_lut_out, GLOBAL(PLD_CLKFB), GLOBAL(D1_data_out), , LB1L1, J1_master_writedata[2], , , VCC);

--J1L22 is std_1c20:inst|clock_0:the_clock_0|process0~11 at LC_X44_Y28_N7

--operation mode is normal

J1L22 = CC1_master_state[1] & MB1_d1_reasons_to_wait;

--GE1_td_shift[6] is std_1c20:inst|jtag_uart:the_jtag_uart|alt_jtag_atlantic:jtag_uart_alt_jtag_atlantic|td_shift[6] at LC_X53_Y19_N7

--operation mode is normal

GE1_td_shift[6] = AMPP_FUNCTION(A1L5, GE1L53, GE1L58, GE1L63, !C1_CLR_SIGNAL, GE1L52);

--GE1L74 is std_1c20:inst|jtag_uart:the_jtag_uart|alt_jtag_atlantic:jtag_uart_alt_jtag_atlantic|wdata[1]~6 at LC_X54_Y19_N7

--operation mode is normal

GE1L74 = AMPP_FUNCTION(GE1L69, GE1_count[8]);

--DE1_slaveselect_wr_strobe is std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|slaveselect_wr_strobe at LC_X35_Y27_N2

--operation mode is normal

DE1_slaveselect_wr_strobe = !DE1L21 & X1L33 & DE1_wr_strobe & X1L28;

--DE1_shift_reg[1] is std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|shift_reg[1] at LC_X40_Y29_N5

--operation mode is normal

DE1_shift_reg[1]_lut_out = DE1_SCLK_reg & DE1_shift_reg[0] # !DE1_SCLK_reg & (DE1L321);

DE1_shift_reg[1] = DFFEAS(DE1_shift_reg[1]_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , DE1L321, , , !DE1_slowcount[0]);

--DE1_SCLK_reg is std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|SCLK_reg at LC_X41_Y28_N6

--operation mode is normal

DE1_SCLK_reg_lut_out = DE1_SCLK_reg & (!DE1_slowcount[0] # !DE1L305) # !DE1_SCLK_reg & DE1L305 & DE1_slowcount[0] & !DE1L304;

DE1_SCLK_reg = DFFEAS(DE1_SCLK_reg_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--DE1L26 is std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|Add1~72 at LC_X41_Y29_N4

--operation mode is normal

DE1L26 = DE1_state[4] $ (!DE1L37);

--DE1_stateZero is std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|stateZero at LC_X41_Y28_N4

--operation mode is normal

DE1_stateZero_lut_out = !DE1L261 # !DE1_state[4] # !DE1_state[0];

DE1_stateZero = DFFEAS(DE1_stateZero_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , DE1L287, , , , );

--DE1L287 is std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|process11~0 at LC_X41_Y28_N9

--operation mode is normal

DE1L287 = DE1_slowcount[0] & (DE1_transmitting);

--DE1L27 is std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|Add1~74 at LC_X41_Y29_N0

--operation mode is arithmetic

DE1L27 = !DE1_state[0];

--DE1L28 is std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|Add1~75 at LC_X41_Y29_N0

--operation mode is arithmetic

DE1L28_cout_0 = DE1_state[0];

DE1L28 = CARRY(DE1L28_cout_0);

--DE1L29 is std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|Add1~75COUT1_278 at LC_X41_Y29_N0

--operation mode is arithmetic

DE1L29_cout_1 = DE1_state[0];

DE1L29 = CARRY(DE1L29_cout_1);

--DE1L30 is std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|Add1~76 at LC_X41_Y29_N1

--operation mode is arithmetic

DE1L30 = DE1_state[1] $ (DE1L28);

--DE1L31 is std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|Add1~77 at LC_X41_Y29_N1

--operation mode is arithmetic

DE1L31_cout_0 = !DE1L28 # !DE1_state[1];

DE1L31 = CARRY(DE1L31_cout_0);

--DE1L32 is std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|Add1~77COUT1_280 at LC_X41_Y29_N1

--operation mode is arithmetic

DE1L32_cout_1 = !DE1L29 # !DE1_state[1];

DE1L32 = CARRY(DE1L32_cout_1);

--DE1L33 is std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|Add1~78 at LC_X41_Y29_N2

--operation mode is arithmetic

DE1L33 = DE1_state[2] $ !DE1L31;

--DE1L34 is std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|Add1~79 at LC_X41_Y29_N2

--operation mode is arithmetic

DE1L34_cout_0 = DE1_state[2] & !DE1L31;

DE1L34 = CARRY(DE1L34_cout_0);

--DE1L35 is std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|Add1~79COUT1_282 at LC_X41_Y29_N2

--operation mode is arithmetic

DE1L35_cout_1 = DE1_state[2] & !DE1L32;

DE1L35 = CARRY(DE1L35_cout_1);

--DE1L36 is std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|Add1~80 at LC_X41_Y29_N3

--operation mode is arithmetic

DE1L36 = DE1_state[3] $ DE1L34;

--DE1L37 is std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|Add1~81 at LC_X41_Y29_N3

--operation mode is arithmetic

DE1L37_cout_0 = !DE1L34 # !DE1_state[3];

DE1L37 = CARRY(DE1L37_cout_0);

--DE1L38 is std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|Add1~81COUT1_284 at LC_X41_Y29_N3

--operation mode is arithmetic

DE1L38_cout_1 = !DE1L35 # !DE1_state[3];

DE1L38 = CARRY(DE1L38_cout_1);

--RD1L27 is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|Add0~148 at LC_X47_Y19_N8

--operation mode is normal

RD1L27 = AMPP_FUNCTION(RD1_MonAReg[10], RD1L15, RD1L25, RD1L26);

--RD1L90 is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|MonAReg~1152 at LC_X47_Y17_N6

--operation mode is normal

RD1L90 = AMPP_FUNCTION(RD1L27, RD1_MonAReg[10], SD1L191);

--RD1_MonRd is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|MonRd at LC_X46_Y17_N6

--operation mode is normal

RD1_MonRd = AMPP_FUNCTION(QC2__clk0, RD1_MonRd, SD1L189, SD1L191, RD1L93, !C1_CLR_SIGNAL);

--SD1_sr[4] is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|sr[4] at LC_X52_Y16_N1

--operation mode is normal

SD1_sr[4] = AMPP_FUNCTION(A1L5, SD1L143, SD1L141, SD1L127, SD1_sr[5], !C1_CLR_SIGNAL, SD1L6);

--SD1_sr[5] is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|sr[5] at LC_X52_Y16_N3

--operation mode is normal

SD1_sr[5] = AMPP_FUNCTION(A1L5, SD1_sr[6], SD1L126, SD1L143, SD1L141, !C1_CLR_SIGNAL, SD1L6);

--SD1_sr[6] is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|sr[6] at LC_X52_Y16_N2

--operation mode is normal

SD1_sr[6] = AMPP_FUNCTION(A1L5, SD1L143, SD1L141, SD1L125, SD1_sr[7], !C1_CLR_SIGNAL, SD1L6);

--SD1_sr[7] is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|sr[7] at LC_X53_Y16_N9

--operation mode is normal

SD1_sr[7] = AMPP_FUNCTION(A1L5, SD1L138, altera_internal_jtag, SD1L124, SD1_sr[8], !C1_CLR_SIGNAL, SD1L143, SD1L6);

--SD1_sr[8] is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|sr[8] at LC_X53_Y16_N6

--operation mode is normal

SD1_sr[8] = AMPP_FUNCTION(A1L5, SD1_sr[9], SD1L141, SD1L143, SD1L123, !C1_CLR_SIGNAL, SD1L6);

--SD1_sr[9] is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|sr[9] at LC_X53_Y16_N8

--operation mode is normal

SD1_sr[9] = AMPP_FUNCTION(A1L5, SD1L141, SD1_sr[10], SD1L143, SD1L39, !C1_CLR_SIGNAL, SD1L6);

--SD1_sr[10] is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|sr[10] at LC_X53_Y16_N5

--operation mode is normal

SD1_sr[10] = AMPP_FUNCTION(A1L5, SD1L141, SD1_sr[11], SD1L143, SD1L40, !C1_CLR_SIGNAL, SD1L6);

--SD1_sr[26] is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|sr[26] at LC_X47_Y14_N9

--operation mode is normal

SD1_sr[26] = AMPP_FUNCTION(A1L5, SD1L42, SD1_sr[27], SD1L9, SD1L43, !C1_CLR_SIGNAL, SD1L12);

--SD1_sr[27] is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|sr[27] at LC_X47_Y14_N3

--operation mode is normal

SD1_sr[27] = AMPP_FUNCTION(A1L5, SD1L46, SD1_sr[28], SD1L9, SD1L45, !C1_CLR_SIGNAL, SD1L12);

--SD1_sr[28] is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|sr[28] at LC_X46_Y14_N7

--operation mode is normal

SD1_sr[28] = AMPP_FUNCTION(A1L5, SD1L70, SD1L47, SD1_sr[29], SD1L48, !C1_CLR_SIGNAL, SD1L12);

--SD1_sr[29] is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|sr[29] at LC_X47_Y14_N0

--operation mode is normal

SD1_sr[29] = AMPP_FUNCTION(A1L5, SD1_sr[30], SD1L50, SD1L9, SD1L51, !C1_CLR_SIGNAL, SD1L12);

--SD1_sr[30] is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|sr[30] at LC_X51_Y14_N0

--operation mode is normal

SD1_sr[30] = AMPP_FUNCTION(A1L5, SD1L52, SD1L53, SD1_sr[31], SD1L70, !C1_CLR_SIGNAL, SD1L12);

--SD1_sr[31] is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|sr[31] at LC_X51_Y14_N2

--operation mode is normal

SD1_sr[31] = AMPP_FUNCTION(A1L5, SD1L54, SD1_ir[1], SD1L71, SD1L136, !C1_CLR_SIGNAL, !SD1_ir[0], SD1L12);

--SD1_sr[32] is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|sr[32] at LC_X47_Y15_N3

--operation mode is normal

SD1_sr[32] = AMPP_FUNCTION(A1L5, SD1L9, SD1_sr[33], SD1L58, SD1L57, !C1_CLR_SIGNAL, SD1L12);

--SD1_sr[33] is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|sr[33] at LC_X46_Y15_N2

--operation mode is normal

SD1_sr[33] = AMPP_FUNCTION(A1L5, SD1L17, SD1L141, SD1_sr[34], SD1L59, !C1_CLR_SIGNAL, SD1L12);

--U1L248 is std_1c20:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|process4~0 at LC_X37_Y25_N3

--operation mode is normal

U1L248 = U1_cpu_instruction_master_dbs_rdv_counter[1] & Y1_cpu_instruction_master_read_data_valid_ext_flash_s1_shift_register[1] & !U1_cpu_instruction_master_dbs_rdv_counter[0];

--Z1L8 is std_1c20:inst|high_res_timer:the_high_res_timer|counter_is_running~93 at LC_X54_Y23_N0

--operation mode is normal

Z1L8 = !Z1_force_reload & Z1_counter_is_running;

--Z1L9 is std_1c20:inst|high_res_timer:the_high_res_timer|counter_is_running~94 at LC_X54_Y23_N9

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

Z1_control_register[1]_qfbk = Z1_control_register[1];

Z1L9 = Z1L8 & (Z1_control_register[1]_qfbk # !Z1L53 # !Z1L48);

--Z1_control_register[1] is std_1c20:inst|high_res_timer:the_high_res_timer|control_register[1] at LC_X54_Y23_N9

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

Z1_control_register[1] = DFFEAS(Z1L9, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , Z1_control_wr_strobe, S1_M_st_data[1], , , VCC);

--Q1_control_reg_out[3] is std_1c20:inst|connector_pll:the_connector_pll|control_reg_out[3] at LC_X46_Y30_N9

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

Q1_control_reg_out[3]_lut_out = GND;

Q1_control_reg_out[3] = DFFEAS(Q1_control_reg_out[3]_lut_out, GLOBAL(PLD_CLOCKINPUT[1]), E1_data_out, , Q1L1, M1_master_writedata[3], , , VCC);

--LB1_control_reg_out[3] is std_1c20:inst|sdram_pll:the_sdram_pll|control_reg_out[3] at LC_X45_Y29_N5

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

LB1_control_reg_out[3]_lut_out = GND;

LB1_control_reg_out[3] = DFFEAS(LB1_control_reg_out[3]_lut_out, GLOBAL(PLD_CLKFB), GLOBAL(D1_data_out), , LB1L1, J1_master_writedata[3], , , VCC);

--GE1_td_shift[7] is std_1c20:inst|jtag_uart:the_jtag_uart|alt_jtag_atlantic:jtag_uart_alt_jtag_atlantic|td_shift[7] at LC_X53_Y20_N9

--operation mode is normal

GE1_td_shift[7] = AMPP_FUNCTION(A1L5, FF1_state[4], GE1L59, GE1L62, BF4_Q[0], !C1_CLR_SIGNAL, GE1L52);

--XC1L11 is std_1c20:inst|cpu:the_cpu|cpu_test_bench:the_cpu_test_bench|Add0~567 at LC_X35_Y13_N2

--operation mode is arithmetic

XC1L11 = AMPP_FUNCTION(S1L1055, S1L881, XC1L14);

--XC1L12 is std_1c20:inst|cpu:the_cpu|cpu_test_bench:the_cpu_test_bench|Add0~567COUT1_1895 at LC_X35_Y13_N2

--operation mode is arithmetic

XC1L12 = AMPP_FUNCTION(S1L1055, S1L881, XC1L15);

--FF1_state[13] is sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state[13] at LC_X57_Y15_N9

--operation mode is normal

FF1_state[13] = AMPP_FUNCTION(A1L5, FF1_state[12], FF1_state[13], VCC, A1L7);

--Q1_control_reg_out[15] is std_1c20:inst|connector_pll:the_connector_pll|control_reg_out[15] at LC_X46_Y29_N5

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

Q1_control_reg_out[15]_lut_out = GND;

Q1_control_reg_out[15] = DFFEAS(Q1_control_reg_out[15]_lut_out, GLOBAL(PLD_CLOCKINPUT[1]), E1_data_out, , Q1L1, M1_master_writedata[15], , , VCC);

--LB1_control_reg_out[15] is std_1c20:inst|sdram_pll:the_sdram_pll|control_reg_out[15] at LC_X43_Y29_N3

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

LB1_control_reg_out[15]_lut_out = GND;

LB1_control_reg_out[15] = DFFEAS(LB1_control_reg_out[15]_lut_out, GLOBAL(PLD_CLKFB), GLOBAL(D1_data_out), , LB1L1, J1_master_writedata[15], , , VCC);

--SD1_sr[11] is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|sr[11] at LC_X53_Y16_N4

--operation mode is normal

SD1_sr[11] = AMPP_FUNCTION(A1L5, SD1_sr[12], SD1L141, SD1L143, SD1L60, !C1_CLR_SIGNAL, SD1L6);

--SD1_sr[12] is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|sr[12] at LC_X53_Y16_N2

--operation mode is normal

SD1_sr[12] = AMPP_FUNCTION(A1L5, SD1L141, SD1_sr[13], SD1L143, SD1L61, !C1_CLR_SIGNAL, SD1L6);

--SD1_sr[13] is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|sr[13] at LC_X53_Y16_N3

--operation mode is normal

SD1_sr[13] = AMPP_FUNCTION(A1L5, SD1L62, SD1L141, SD1L143, SD1_sr[14], !C1_CLR_SIGNAL, SD1L6);

--SD1_sr[14] is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|sr[14] at LC_X52_Y16_N4

--operation mode is normal

SD1_sr[14] = AMPP_FUNCTION(A1L5, SD1L143, SD1L141, SD1_sr[15], SD1L63, !C1_CLR_SIGNAL, SD1L6);

--SD1_sr[15] is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|sr[15] at LC_X53_Y16_N7

--operation mode is normal

SD1_sr[15] = AMPP_FUNCTION(A1L5, SD1L137, altera_internal_jtag, SD1L122, SD1_sr[16], !C1_CLR_SIGNAL, SD1L143, SD1L6);

--SD1_sr[16] is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|sr[16] at LC_X48_Y14_N7

--operation mode is normal

SD1_sr[16] = AMPP_FUNCTION(A1L5, SD1L9, SD1L66, SD1L65, SD1_sr[17], !C1_CLR_SIGNAL, SD1L12);

--SD1_sr[17] is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|sr[17] at LC_X48_Y14_N3

--operation mode is normal

SD1_sr[17] = AMPP_FUNCTION(A1L5, SD1L68, SD1L69, SD1L9, SD1_sr[18], !C1_CLR_SIGNAL, SD1L12);

--Q1_control_reg_out[7] is std_1c20:inst|connector_pll:the_connector_pll|control_reg_out[7] at LC_X47_Y30_N6

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

Q1_control_reg_out[7]_lut_out = GND;

Q1_control_reg_out[7] = DFFEAS(Q1_control_reg_out[7]_lut_out, GLOBAL(PLD_CLOCKINPUT[1]), E1_data_out, , Q1L1, M1_master_writedata[7], , , VCC);

--LB1_control_reg_out[7] is std_1c20:inst|sdram_pll:the_sdram_pll|control_reg_out[7] at LC_X45_Y29_N0

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

LB1_control_reg_out[7]_lut_out = GND;

LB1_control_reg_out[7] = DFFEAS(LB1_control_reg_out[7]_lut_out, GLOBAL(PLD_CLKFB), GLOBAL(D1_data_out), , LB1L1, J1_master_writedata[7], , , VCC);

--NE1L6 is std_1c20:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_w:the_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_jf21:auto_generated|a_dpfifo_ml21:dpfifo|a_fefifo_7cf:fifo_state|b_non_empty~141 at LC_X47_Y20_N0

--operation mode is normal

NE1L6 = RE1_safe_q[4] # RE1_safe_q[2] # RE1_safe_q[1] # RE1_safe_q[5];

--NE1L7 is std_1c20:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_w:the_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_jf21:auto_generated|a_dpfifo_ml21:dpfifo|a_fefifo_7cf:fifo_state|b_non_empty~142 at LC_X47_Y20_N8

--operation mode is normal

NE1L7 = RE1_safe_q[3] # NE1L6 # !BB1_rd_wfifo # !RE1_safe_q[0];

--Q1_control_reg_out[14] is std_1c20:inst|connector_pll:the_connector_pll|control_reg_out[14] at LC_X46_Y30_N0

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

Q1_control_reg_out[14]_lut_out = GND;

Q1_control_reg_out[14] = DFFEAS(Q1_control_reg_out[14]_lut_out, GLOBAL(PLD_CLOCKINPUT[1]), E1_data_out, , Q1L1, M1_master_writedata[14], , , VCC);

--LB1_control_reg_out[14] is std_1c20:inst|sdram_pll:the_sdram_pll|control_reg_out[14] at LC_X45_Y29_N3

--operation mode is normal

LB1_control_reg_out[14]_lut_out = J1_master_writedata[14];

LB1_control_reg_out[14] = DFFEAS(LB1_control_reg_out[14]_lut_out, GLOBAL(PLD_CLKFB), GLOBAL(D1_data_out), , LB1L1, , , , );

--Q1_control_reg_out[13] is std_1c20:inst|connector_pll:the_connector_pll|control_reg_out[13] at LC_X48_Y29_N6

--operation mode is normal

Q1_control_reg_out[13]_lut_out = M1_master_writedata[13];

Q1_control_reg_out[13] = DFFEAS(Q1_control_reg_out[13]_lut_out, GLOBAL(PLD_CLOCKINPUT[1]), E1_data_out, , Q1L1, , , , );

--LB1_control_reg_out[13] is std_1c20:inst|sdram_pll:the_sdram_pll|control_reg_out[13] at LC_X43_Y29_N5

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

LB1_control_reg_out[13]_lut_out = GND;

LB1_control_reg_out[13] = DFFEAS(LB1_control_reg_out[13]_lut_out, GLOBAL(PLD_CLKFB), GLOBAL(D1_data_out), , LB1L1, J1_master_writedata[13], , , VCC);

--Q1_control_reg_out[12] is std_1c20:inst|connector_pll:the_connector_pll|control_reg_out[12] at LC_X47_Y30_N5

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

Q1_control_reg_out[12]_lut_out = GND;

Q1_control_reg_out[12] = DFFEAS(Q1_control_reg_out[12]_lut_out, GLOBAL(PLD_CLOCKINPUT[1]), E1_data_out, , Q1L1, M1_master_writedata[12], , , VCC);

--LB1_control_reg_out[12] is std_1c20:inst|sdram_pll:the_sdram_pll|control_reg_out[12] at LC_X44_Y30_N5

--operation mode is normal

LB1_control_reg_out[12]_lut_out = J1_master_writedata[12];

LB1_control_reg_out[12] = DFFEAS(LB1_control_reg_out[12]_lut_out, GLOBAL(PLD_CLKFB), GLOBAL(D1_data_out), , LB1L1, , , , );

--LB1_control_reg_out[11] is std_1c20:inst|sdram_pll:the_sdram_pll|control_reg_out[11] at LC_X44_Y30_N6

--operation mode is normal

LB1_control_reg_out[11]_lut_out = J1_master_writedata[11];

LB1_control_reg_out[11] = DFFEAS(LB1_control_reg_out[11]_lut_out, GLOBAL(PLD_CLKFB), GLOBAL(D1_data_out), , LB1L1, , , , );

--Q1_control_reg_out[11] is std_1c20:inst|connector_pll:the_connector_pll|control_reg_out[11] at LC_X47_Y30_N8

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

Q1_control_reg_out[11]_lut_out = GND;

Q1_control_reg_out[11] = DFFEAS(Q1_control_reg_out[11]_lut_out, GLOBAL(PLD_CLOCKINPUT[1]), E1_data_out, , Q1L1, M1_master_writedata[11], , , VCC);

--Q1_control_reg_out[10] is std_1c20:inst|connector_pll:the_connector_pll|control_reg_out[10] at LC_X46_Y29_N0

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

Q1_control_reg_out[10]_lut_out = GND;

Q1_control_reg_out[10] = DFFEAS(Q1_control_reg_out[10]_lut_out, GLOBAL(PLD_CLOCKINPUT[1]), E1_data_out, , Q1L1, M1_master_writedata[10], , , VCC);

--LB1_control_reg_out[10] is std_1c20:inst|sdram_pll:the_sdram_pll|control_reg_out[10] at LC_X44_Y30_N4

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

LB1_control_reg_out[10]_lut_out = GND;

LB1_control_reg_out[10] = DFFEAS(LB1_control_reg_out[10]_lut_out, GLOBAL(PLD_CLKFB), GLOBAL(D1_data_out), , LB1L1, J1_master_writedata[10], , , VCC);

--DE1_shift_reg[0] is std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|shift_reg[0] at LC_X40_Y29_N0

--operation mode is normal

DE1_shift_reg[0]_lut_out = DE1_SCLK_reg & DE1_MISO_reg # !DE1_SCLK_reg & (DE1L322);

DE1_shift_reg[0] = DFFEAS(DE1_shift_reg[0]_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , DE1L322, , , !DE1_slowcount[0]);

--Q1_control_reg_out[9] is std_1c20:inst|connector_pll:the_connector_pll|control_reg_out[9] at LC_X46_Y29_N3

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

Q1_control_reg_out[9]_lut_out = GND;

Q1_control_reg_out[9] = DFFEAS(Q1_control_reg_out[9]_lut_out, GLOBAL(PLD_CLOCKINPUT[1]), E1_data_out, , Q1L1, M1_master_writedata[9], , , VCC);

--LB1_control_reg_out[9] is std_1c20:inst|sdram_pll:the_sdram_pll|control_reg_out[9] at LC_X43_Y29_N8

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

LB1_control_reg_out[9]_lut_out = GND;

LB1_control_reg_out[9] = DFFEAS(LB1_control_reg_out[9]_lut_out, GLOBAL(PLD_CLKFB), GLOBAL(D1_data_out), , LB1L1, J1_master_writedata[9], , , VCC);

--Q1_control_reg_out[8] is std_1c20:inst|connector_pll:the_connector_pll|control_reg_out[8] at LC_X48_Y29_N9

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

Q1_control_reg_out[8]_lut_out = GND;

Q1_control_reg_out[8] = DFFEAS(Q1_control_reg_out[8]_lut_out, GLOBAL(PLD_CLOCKINPUT[1]), E1_data_out, , Q1L1, M1_master_writedata[8], , , VCC);

--LB1_control_reg_out[8] is std_1c20:inst|sdram_pll:the_sdram_pll|control_reg_out[8] at LC_X45_Y29_N8

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

LB1_control_reg_out[8]_lut_out = GND;

LB1_control_reg_out[8] = DFFEAS(LB1_control_reg_out[8]_lut_out, GLOBAL(PLD_CLKFB), GLOBAL(D1_data_out), , LB1L1, J1_master_writedata[8], , , VCC);

--Q1_control_reg_out[6] is std_1c20:inst|connector_pll:the_connector_pll|control_reg_out[6] at LC_X48_Y29_N3

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

Q1_control_reg_out[6]_lut_out = GND;

Q1_control_reg_out[6] = DFFEAS(Q1_control_reg_out[6]_lut_out, GLOBAL(PLD_CLOCKINPUT[1]), E1_data_out, , Q1L1, M1_master_writedata[6], , , VCC);

--LB1_control_reg_out[6] is std_1c20:inst|sdram_pll:the_sdram_pll|control_reg_out[6] at LC_X45_Y30_N5

--operation mode is normal

LB1_control_reg_out[6]_lut_out = J1_master_writedata[6];

LB1_control_reg_out[6] = DFFEAS(LB1_control_reg_out[6]_lut_out, GLOBAL(PLD_CLKFB), GLOBAL(D1_data_out), , LB1L1, , , , );

--Q1_control_reg_out[4] is std_1c20:inst|connector_pll:the_connector_pll|control_reg_out[4] at LC_X48_Y29_N4

--operation mode is normal

Q1_control_reg_out[4]_lut_out = M1_master_writedata[4];

Q1_control_reg_out[4] = DFFEAS(Q1_control_reg_out[4]_lut_out, GLOBAL(PLD_CLOCKINPUT[1]), E1_data_out, , Q1L1, , , , );

--LB1_control_reg_out[4] is std_1c20:inst|sdram_pll:the_sdram_pll|control_reg_out[4] at LC_X45_Y30_N4

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

LB1_control_reg_out[4]_lut_out = GND;

LB1_control_reg_out[4] = DFFEAS(LB1_control_reg_out[4]_lut_out, GLOBAL(PLD_CLKFB), GLOBAL(D1_data_out), , LB1L1, J1_master_writedata[4], , , VCC);

--GE1_td_shift[8] is std_1c20:inst|jtag_uart:the_jtag_uart|alt_jtag_atlantic:jtag_uart_alt_jtag_atlantic|td_shift[8] at LC_X53_Y19_N4

--operation mode is normal

GE1_td_shift[8] = AMPP_FUNCTION(A1L5, GE1_count[9], GE1_td_shift[9], GE1_rdata[6], !C1_CLR_SIGNAL, !FF1_state[4], GE1L52);

--Q1_control_reg_out[5] is std_1c20:inst|connector_pll:the_connector_pll|control_reg_out[5] at LC_X46_Y30_N1

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

Q1_control_reg_out[5]_lut_out = GND;

Q1_control_reg_out[5] = DFFEAS(Q1_control_reg_out[5]_lut_out, GLOBAL(PLD_CLOCKINPUT[1]), E1_data_out, , Q1L1, M1_master_writedata[5], , , VCC);

--LB1_control_reg_out[5] is std_1c20:inst|sdram_pll:the_sdram_pll|control_reg_out[5] at LC_X43_Y29_N7

--operation mode is normal

LB1_control_reg_out[5]_lut_out = J1_master_writedata[5];

LB1_control_reg_out[5] = DFFEAS(LB1_control_reg_out[5]_lut_out, GLOBAL(PLD_CLKFB), GLOBAL(D1_data_out), , LB1L1, , , , );

--M1_slave_readdata_p1[0] is std_1c20:inst|clock_1:the_clock_1|slave_readdata_p1[0] at LC_X47_Y29_N8

--operation mode is normal

M1_slave_readdata_p1[0]_lut_out = M1_master_nativeaddress[0] & Q1_control_reg_out[0];

M1_slave_readdata_p1[0] = DFFEAS(M1_slave_readdata_p1[0]_lut_out, GLOBAL(PLD_CLOCKINPUT[1]), E1_data_out, , M1L22, , , , );

--J1_slave_readdata_p1[0] is std_1c20:inst|clock_0:the_clock_0|slave_readdata_p1[0] at LC_X45_Y28_N5

--operation mode is normal

J1_slave_readdata_p1[0]_lut_out = J1_master_nativeaddress[0] & LB1_control_reg_out[0];

J1_slave_readdata_p1[0] = DFFEAS(J1_slave_readdata_p1[0]_lut_out, GLOBAL(PLD_CLKFB), GLOBAL(D1_data_out), , J1L22, , , , );

--GE1_wdata[0] is std_1c20:inst|jtag_uart:the_jtag_uart|alt_jtag_atlantic:jtag_uart_alt_jtag_atlantic|wdata[0] at LC_X51_Y20_N9

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

GE1_wdata[0] = AMPP_FUNCTION(A1L5, altera_internal_jtag, !C1_CLR_SIGNAL, GND, GE1L72);

--RB1L11 is std_1c20:inst|sys_clk_timer:the_sys_clk_timer|counter_is_running~93 at LC_X53_Y23_N4

--operation mode is normal

RB1L11 = RB1_counter_is_running & !RB1_force_reload;

--RB1L12 is std_1c20:inst|sys_clk_timer:the_sys_clk_timer|counter_is_running~94 at LC_X53_Y23_N7

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

RB1_control_register[1]_qfbk = RB1_control_register[1];

RB1L12 = RB1L11 & (RB1_control_register[1]_qfbk # !RB1L56 # !RB1L51);

--RB1_control_register[1] is std_1c20:inst|sys_clk_timer:the_sys_clk_timer|control_register[1] at LC_X53_Y23_N7

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

RB1_control_register[1] = DFFEAS(RB1L12, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , RB1_control_wr_strobe, S1_M_st_data[1], , , VCC);

--M1_slave_readdata_p1[1] is std_1c20:inst|clock_1:the_clock_1|slave_readdata_p1[1] at LC_X46_Y28_N7

--operation mode is normal

M1_slave_readdata_p1[1]_lut_out = !Q1_control_reg_out[1] & (M1_master_nativeaddress[0]);

M1_slave_readdata_p1[1] = DFFEAS(M1_slave_readdata_p1[1]_lut_out, GLOBAL(PLD_CLOCKINPUT[1]), E1_data_out, , M1L22, , , , );

--J1_slave_readdata_p1[1] is std_1c20:inst|clock_0:the_clock_0|slave_readdata_p1[1] at LC_X44_Y29_N1

--operation mode is normal

J1_slave_readdata_p1[1]_lut_out = J1_master_nativeaddress[0] & (!LB1_control_reg_out[1]);

J1_slave_readdata_p1[1] = DFFEAS(J1_slave_readdata_p1[1]_lut_out, GLOBAL(PLD_CLKFB), GLOBAL(D1_data_out), , J1L22, , , , );

--GE1_wdata[1] is std_1c20:inst|jtag_uart:the_jtag_uart|alt_jtag_atlantic:jtag_uart_alt_jtag_atlantic|wdata[1] at LC_X51_Y20_N7

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

GE1_wdata[1] = AMPP_FUNCTION(A1L5, GE1_td_shift[5], !C1_CLR_SIGNAL, GND, GE1L74);

--CF1L18 is sld_hub:sld_hub_inst|sld_rom_sr:HUB_INFO_REG|Mux1~69 at LC_X59_Y18_N5

--operation mode is normal

CF1L18 = AMPP_FUNCTION(CF1_word_counter[1], CF1_word_counter[3], CF1_word_counter[0]);

--SD1_internal_jdo1[1] is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|internal_jdo1[1] at LC_X54_Y16_N6

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

SD1_internal_jdo1[1] = AMPP_FUNCTION(A1L8, SD1_sr[1], VCC, GND, SD1L144);

--GD1_break_readreg[2] is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_break:the_cpu_nios2_oci_break|break_readreg[2] at LC_X51_Y16_N1

--operation mode is normal

GD1_break_readreg[2] = AMPP_FUNCTION(QC2__clk0, SD1_internal_jdo1[37], SD1_internal_jdo1[36], SD1L188, SD1_internal_jdo1[2], !C1_CLR_SIGNAL, SD1L188);

--SD1L128 is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|Mux37~14 at LC_X51_Y16_N8

--operation mode is normal

SD1L128 = AMPP_FUNCTION(GD1_break_readreg[2], SD1_ir[1], RD1_internal_MonDReg[2], SD1_ir[0]);

--GD1_break_readreg[24] is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_break:the_cpu_nios2_oci_break|break_readreg[24] at LC_X48_Y17_N0

--operation mode is normal

GD1_break_readreg[24] = AMPP_FUNCTION(QC2__clk0, SD1_internal_jdo1[37], SD1L188, SD1_internal_jdo1[36], SD1_internal_jdo1[24], !C1_CLR_SIGNAL, SD1L188);

--SD1L34 is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|DRsize[0]~20011 at LC_X48_Y17_N6

--operation mode is normal

SD1L34 = AMPP_FUNCTION(RD1_internal_MonDReg[24], GD1_break_readreg[24], SD1_ir[1]);

--SD1L35 is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|DRsize[0]~20012 at LC_X46_Y14_N1

--operation mode is normal

SD1L35 = AMPP_FUNCTION(SD1_ir[1], SD1L34, SD1_ir[0], SD1L143);

--GE1_read_write is std_1c20:inst|jtag_uart:the_jtag_uart|alt_jtag_atlantic:jtag_uart_alt_jtag_atlantic|read_write at LC_X52_Y21_N3

--operation mode is normal

GE1_read_write = AMPP_FUNCTION(A1L5, GE1_read_write, !C1_CLR_SIGNAL, GE1L74);

--GE1_td_shift[4] is std_1c20:inst|jtag_uart:the_jtag_uart|alt_jtag_atlantic:jtag_uart_alt_jtag_atlantic|td_shift[4] at LC_X53_Y20_N6

--operation mode is normal

GE1_td_shift[4] = AMPP_FUNCTION(A1L5, FF1_state[4], GE1L60, GE1L62, BF4_Q[0], !C1_CLR_SIGNAL, GE1L52);

--GE1L57 is std_1c20:inst|jtag_uart:the_jtag_uart|alt_jtag_atlantic:jtag_uart_alt_jtag_atlantic|td_shift[9]~3561 at LC_X53_Y20_N8

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

GE1L57 = AMPP_FUNCTION(GE1_count[9], GE1_td_shift[4]);

--GE1_rdata[1] is std_1c20:inst|jtag_uart:the_jtag_uart|alt_jtag_atlantic:jtag_uart_alt_jtag_atlantic|rdata[1] at LC_X53_Y20_N8

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

GE1_rdata[1] = AMPP_FUNCTION(QC2__clk0, SE1_q_b[1], F1_data_out, GND, GE1L18);

--GE1_count[6] is std_1c20:inst|jtag_uart:the_jtag_uart|alt_jtag_atlantic:jtag_uart_alt_jtag_atlantic|count[6] at LC_X54_Y20_N6

--operation mode is normal

GE1_count[6] = AMPP_FUNCTION(A1L5, GE1_count[5], FF1_state[4], !C1_CLR_SIGNAL, GE1L52);

--QE2_safe_q[0] is std_1c20:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_w:the_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_jf21:auto_generated|a_dpfifo_ml21:dpfifo|cntr_rd8:wr_ptr|safe_q[0] at LC_X48_Y20_N1

--operation mode is arithmetic

QE2_safe_q[0]_lut_out = QE2_safe_q[0] $ BB1_fifo_wr;

QE2_safe_q[0] = DFFEAS(QE2_safe_q[0]_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--QE2L2 is std_1c20:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_w:the_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_jf21:auto_generated|a_dpfifo_ml21:dpfifo|cntr_rd8:wr_ptr|counter_cella0~COUT at LC_X48_Y20_N1

--operation mode is arithmetic

QE2L2_cout_0 = QE2_safe_q[0];

QE2L2 = CARRY(QE2L2_cout_0);

--QE2L3 is std_1c20:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_w:the_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_jf21:auto_generated|a_dpfifo_ml21:dpfifo|cntr_rd8:wr_ptr|counter_cella0~COUTCOUT1_53 at LC_X48_Y20_N1

--operation mode is arithmetic

QE2L3_cout_1 = QE2_safe_q[0];

QE2L3 = CARRY(QE2L3_cout_1);

--QE2_safe_q[1] is std_1c20:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_w:the_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_jf21:auto_generated|a_dpfifo_ml21:dpfifo|cntr_rd8:wr_ptr|safe_q[1] at LC_X48_Y20_N2

--operation mode is arithmetic

QE2_safe_q[1]_lut_out = QE2_safe_q[1] $ (BB1_fifo_wr & QE2L2);

QE2_safe_q[1] = DFFEAS(QE2_safe_q[1]_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--QE2L5 is std_1c20:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_w:the_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_jf21:auto_generated|a_dpfifo_ml21:dpfifo|cntr_rd8:wr_ptr|counter_cella1~COUT at LC_X48_Y20_N2

--operation mode is arithmetic

QE2L5_cout_0 = !QE2L2 # !QE2_safe_q[1];

QE2L5 = CARRY(QE2L5_cout_0);

--QE2L6 is std_1c20:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_w:the_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_jf21:auto_generated|a_dpfifo_ml21:dpfifo|cntr_rd8:wr_ptr|counter_cella1~COUTCOUT1_52 at LC_X48_Y20_N2

--operation mode is arithmetic

QE2L6_cout_1 = !QE2L3 # !QE2_safe_q[1];

QE2L6 = CARRY(QE2L6_cout_1);

--QE2_safe_q[2] is std_1c20:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_w:the_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_jf21:auto_generated|a_dpfifo_ml21:dpfifo|cntr_rd8:wr_ptr|safe_q[2] at LC_X48_Y20_N3

--operation mode is arithmetic

QE2_safe_q[2]_lut_out = QE2_safe_q[2] $ (BB1_fifo_wr & !QE2L5);

QE2_safe_q[2] = DFFEAS(QE2_safe_q[2]_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--QE2L8 is std_1c20:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_w:the_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_jf21:auto_generated|a_dpfifo_ml21:dpfifo|cntr_rd8:wr_ptr|counter_cella2~COUT at LC_X48_Y20_N3

--operation mode is arithmetic

QE2L8_cout_0 = QE2_safe_q[2] & !QE2L5;

QE2L8 = CARRY(QE2L8_cout_0);

--QE2L9 is std_1c20:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_w:the_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_jf21:auto_generated|a_dpfifo_ml21:dpfifo|cntr_rd8:wr_ptr|counter_cella2~COUTCOUT1_50 at LC_X48_Y20_N3

--operation mode is arithmetic

QE2L9_cout_1 = QE2_safe_q[2] & !QE2L6;

QE2L9 = CARRY(QE2L9_cout_1);

--QE2_safe_q[3] is std_1c20:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_w:the_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_jf21:auto_generated|a_dpfifo_ml21:dpfifo|cntr_rd8:wr_ptr|safe_q[3] at LC_X48_Y20_N4

--operation mode is arithmetic

QE2_safe_q[3]_lut_out = QE2_safe_q[3] $ (BB1_fifo_wr & QE2L8);

QE2_safe_q[3] = DFFEAS(QE2_safe_q[3]_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--QE2L11 is std_1c20:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_w:the_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_jf21:auto_generated|a_dpfifo_ml21:dpfifo|cntr_rd8:wr_ptr|counter_cella3~COUT at LC_X48_Y20_N4

--operation mode is arithmetic

QE2L11 = QE2L12;

--QE2_safe_q[4] is std_1c20:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_w:the_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_jf21:auto_generated|a_dpfifo_ml21:dpfifo|cntr_rd8:wr_ptr|safe_q[4] at LC_X48_Y20_N5

--operation mode is arithmetic

QE2_safe_q[4]_carry_eqn = QE2L11;

QE2_safe_q[4]_lut_out = QE2_safe_q[4] $ (BB1_fifo_wr & !QE2_safe_q[4]_carry_eqn);

QE2_safe_q[4] = DFFEAS(QE2_safe_q[4]_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--QE2L15 is std_1c20:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_w:the_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_jf21:auto_generated|a_dpfifo_ml21:dpfifo|cntr_rd8:wr_ptr|counter_cella4~COUT at LC_X48_Y20_N5

--operation mode is arithmetic

QE2L15_cout_0 = QE2_safe_q[4] & (!QE2L11);

QE2L15 = CARRY(QE2L15_cout_0);

--QE2L16 is std_1c20:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_w:the_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_jf21:auto_generated|a_dpfifo_ml21:dpfifo|cntr_rd8:wr_ptr|counter_cella4~COUTCOUT1_52 at LC_X48_Y20_N5

--operation mode is arithmetic

QE2L16_cout_1 = QE2_safe_q[4] & (!QE2L11);

QE2L16 = CARRY(QE2L16_cout_1);

--QE2_safe_q[5] is std_1c20:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_w:the_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_jf21:auto_generated|a_dpfifo_ml21:dpfifo|cntr_rd8:wr_ptr|safe_q[5] at LC_X48_Y20_N6

--operation mode is normal

QE2_safe_q[5]_carry_eqn = (!QE2L11 & QE2L15) # (QE2L11 & QE2L16);

QE2_safe_q[5]_lut_out = QE2_safe_q[5] $ (BB1_fifo_wr & QE2_safe_q[5]_carry_eqn);

QE2_safe_q[5] = DFFEAS(QE2_safe_q[5]_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--QE1_safe_q[0] is std_1c20:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_w:the_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_jf21:auto_generated|a_dpfifo_ml21:dpfifo|cntr_rd8:rd_ptr_count|safe_q[0] at LC_X48_Y19_N1

--operation mode is arithmetic

QE1_safe_q[0]_lut_out = QE1_safe_q[0] $ BB1_rd_wfifo;

QE1_safe_q[0] = DFFEAS(QE1_safe_q[0]_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--QE1L2 is std_1c20:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_w:the_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_jf21:auto_generated|a_dpfifo_ml21:dpfifo|cntr_rd8:rd_ptr_count|counter_cella0~COUT at LC_X48_Y19_N1

--operation mode is arithmetic

QE1L2_cout_0 = QE1_safe_q[0];

QE1L2 = CARRY(QE1L2_cout_0);

--QE1L3 is std_1c20:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_w:the_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_jf21:auto_generated|a_dpfifo_ml21:dpfifo|cntr_rd8:rd_ptr_count|counter_cella0~COUTCOUT1_53 at LC_X48_Y19_N1

--operation mode is arithmetic

QE1L3_cout_1 = QE1_safe_q[0];

QE1L3 = CARRY(QE1L3_cout_1);

--QE1_safe_q[1] is std_1c20:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_w:the_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_jf21:auto_generated|a_dpfifo_ml21:dpfifo|cntr_rd8:rd_ptr_count|safe_q[1] at LC_X48_Y19_N2

--operation mode is arithmetic

QE1_safe_q[1]_lut_out = QE1_safe_q[1] $ (BB1_rd_wfifo & QE1L2);

QE1_safe_q[1] = DFFEAS(QE1_safe_q[1]_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--QE1L5 is std_1c20:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_w:the_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_jf21:auto_generated|a_dpfifo_ml21:dpfifo|cntr_rd8:rd_ptr_count|counter_cella1~COUT at LC_X48_Y19_N2

--operation mode is arithmetic

QE1L5_cout_0 = !QE1L2 # !QE1_safe_q[1];

QE1L5 = CARRY(QE1L5_cout_0);

--QE1L6 is std_1c20:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_w:the_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_jf21:auto_generated|a_dpfifo_ml21:dpfifo|cntr_rd8:rd_ptr_count|counter_cella1~COUTCOUT1_52 at LC_X48_Y19_N2

--operation mode is arithmetic

QE1L6_cout_1 = !QE1L3 # !QE1_safe_q[1];

QE1L6 = CARRY(QE1L6_cout_1);

--QE1_safe_q[2] is std_1c20:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_w:the_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_jf21:auto_generated|a_dpfifo_ml21:dpfifo|cntr_rd8:rd_ptr_count|safe_q[2] at LC_X48_Y19_N3

--operation mode is arithmetic

QE1_safe_q[2]_lut_out = QE1_safe_q[2] $ (BB1_rd_wfifo & !QE1L5);

QE1_safe_q[2] = DFFEAS(QE1_safe_q[2]_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--QE1L8 is std_1c20:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_w:the_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_jf21:auto_generated|a_dpfifo_ml21:dpfifo|cntr_rd8:rd_ptr_count|counter_cella2~COUT at LC_X48_Y19_N3

--operation mode is arithmetic

QE1L8_cout_0 = QE1_safe_q[2] & (!QE1L5);

QE1L8 = CARRY(QE1L8_cout_0);

--QE1L9 is std_1c20:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_w:the_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_jf21:auto_generated|a_dpfifo_ml21:dpfifo|cntr_rd8:rd_ptr_count|counter_cella2~COUTCOUT1_50 at LC_X48_Y19_N3

--operation mode is arithmetic

QE1L9_cout_1 = QE1_safe_q[2] & (!QE1L6);

QE1L9 = CARRY(QE1L9_cout_1);

--QE1_safe_q[3] is std_1c20:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_w:the_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_jf21:auto_generated|a_dpfifo_ml21:dpfifo|cntr_rd8:rd_ptr_count|safe_q[3] at LC_X48_Y19_N4

--operation mode is arithmetic

QE1_safe_q[3]_lut_out = QE1_safe_q[3] $ (BB1_rd_wfifo & QE1L8);

QE1_safe_q[3] = DFFEAS(QE1_safe_q[3]_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--QE1L11 is std_1c20:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_w:the_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_jf21:auto_generated|a_dpfifo_ml21:dpfifo|cntr_rd8:rd_ptr_count|counter_cella3~COUT at LC_X48_Y19_N4

--operation mode is arithmetic

QE1L11 = QE1L12;

--QE1_safe_q[4] is std_1c20:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_w:the_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_jf21:auto_generated|a_dpfifo_ml21:dpfifo|cntr_rd8:rd_ptr_count|safe_q[4] at LC_X48_Y19_N5

--operation mode is arithmetic

QE1_safe_q[4]_carry_eqn = QE1L11;

QE1_safe_q[4]_lut_out = QE1_safe_q[4] $ (BB1_rd_wfifo & !QE1_safe_q[4]_carry_eqn);

QE1_safe_q[4] = DFFEAS(QE1_safe_q[4]_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--QE1L15 is std_1c20:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_w:the_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_jf21:auto_generated|a_dpfifo_ml21:dpfifo|cntr_rd8:rd_ptr_count|counter_cella4~COUT at LC_X48_Y19_N5

--operation mode is arithmetic

QE1L15_cout_0 = QE1_safe_q[4] & (!QE1L11);

QE1L15 = CARRY(QE1L15_cout_0);

--QE1L16 is std_1c20:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_w:the_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_jf21:auto_generated|a_dpfifo_ml21:dpfifo|cntr_rd8:rd_ptr_count|counter_cella4~COUTCOUT1_52 at LC_X48_Y19_N5

--operation mode is arithmetic

QE1L16_cout_1 = QE1_safe_q[4] & (!QE1L11);

QE1L16 = CARRY(QE1L16_cout_1);

--QE1_safe_q[5] is std_1c20:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_w:the_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_jf21:auto_generated|a_dpfifo_ml21:dpfifo|cntr_rd8:rd_ptr_count|safe_q[5] at LC_X48_Y19_N6

--operation mode is normal

QE1_safe_q[5]_carry_eqn = (!QE1L11 & QE1L15) # (QE1L11 & QE1L16);

QE1_safe_q[5]_lut_out = QE1_safe_q[5] $ (BB1_rd_wfifo & QE1_safe_q[5]_carry_eqn);

QE1_safe_q[5] = DFFEAS(QE1_safe_q[5]_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--WE1L58 is std_1c20:inst|sdram_s1_arbitrator:the_sdram_s1|rdv_fifo_for_cpu_instruction_master_to_sdram_s1_module:rdv_fifo_for_cpu_instruction_master_to_sdram_s1|stage_5~5 at LC_X22_Y25_N9

--operation mode is normal

WE1L58 = WE1_full_6 & (WE1L61Q) # !WE1_full_6 & NB1L24;

--WE1_full_5 is std_1c20:inst|sdram_s1_arbitrator:the_sdram_s1|rdv_fifo_for_cpu_instruction_master_to_sdram_s1_module:rdv_fifo_for_cpu_instruction_master_to_sdram_s1|full_5 at LC_X23_Y26_N3

--operation mode is normal

WE1_full_5_lut_out = NB1L37 & WE1_full_4 # !NB1L37 & (KB1_za_valid & (WE1_full_6) # !KB1_za_valid & WE1_full_4);

WE1_full_5 = DFFEAS(WE1_full_5_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , VE1L22, , , , );

--WE1L28 is std_1c20:inst|sdram_s1_arbitrator:the_sdram_s1|rdv_fifo_for_cpu_instruction_master_to_sdram_s1_module:rdv_fifo_for_cpu_instruction_master_to_sdram_s1|process4~1 at LC_X23_Y25_N5

--operation mode is normal

WE1L28 = KB1_za_valid # !WE1_full_4 & NB1L37;

--HC1_data_in_d1 is std_1c20:inst|clock_1:the_clock_1|clock_1_slave_read_request_sync_module:clock_1_slave_read_request_sync|data_in_d1 at LC_X47_Y27_N7

--operation mode is normal

HC1_data_in_d1_lut_out = NC1_internal_slave_read_request;

HC1_data_in_d1 = DFFEAS(HC1_data_in_d1_lut_out, GLOBAL(PLD_CLOCKINPUT[1]), E1_data_out, , , , , , );

--JC1_data_in_d1 is std_1c20:inst|clock_1:the_clock_1|clock_1_slave_write_request_sync_module:clock_1_slave_write_request_sync|data_in_d1 at LC_X47_Y27_N2

--operation mode is normal

JC1_data_in_d1_lut_out = NC1_internal_slave_write_request;

JC1_data_in_d1 = DFFEAS(JC1_data_in_d1_lut_out, GLOBAL(PLD_CLOCKINPUT[1]), E1_data_out, , , , , , );

--ZB1_data_in_d1 is std_1c20:inst|clock_0:the_clock_0|clock_0_slave_read_request_sync_module:clock_0_slave_read_request_sync|data_in_d1 at LC_X42_Y27_N9

--operation mode is normal

ZB1_data_in_d1_lut_out = EC1_internal_slave_read_request;

ZB1_data_in_d1 = DFFEAS(ZB1_data_in_d1_lut_out, GLOBAL(PLD_CLKFB), GLOBAL(D1_data_out), , , , , , );

--AC1_data_in_d1 is std_1c20:inst|clock_0:the_clock_0|clock_0_slave_write_request_sync_module:clock_0_slave_write_request_sync|data_in_d1 at LC_X42_Y27_N6

--operation mode is normal

AC1_data_in_d1_lut_out = EC1_internal_slave_write_request;

AC1_data_in_d1 = DFFEAS(AC1_data_in_d1_lut_out, GLOBAL(PLD_CLKFB), GLOBAL(D1_data_out), , , , , , );

--VE1L45 is std_1c20:inst|sdram_s1_arbitrator:the_sdram_s1|rdv_fifo_for_cpu_data_master_to_sdram_s1_module:rdv_fifo_for_cpu_data_master_to_sdram_s1|stage_5~7021 at LC_X22_Y25_N7

--operation mode is normal

VE1L45 = WE1_full_6 & VE1L48Q # !WE1_full_6 & (NB1L20);

--GD1_break_readreg[23] is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_break:the_cpu_nios2_oci_break|break_readreg[23] at LC_X48_Y17_N4

--operation mode is normal

GD1_break_readreg[23] = AMPP_FUNCTION(QC2__clk0, SD1_internal_jdo1[37], SD1L188, SD1_internal_jdo1[36], SD1_internal_jdo1[23], !C1_CLR_SIGNAL, SD1L188);

--SD1L36 is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|DRsize[0]~20014 at LC_X47_Y17_N8

--operation mode is normal

SD1L36 = AMPP_FUNCTION(GD1_break_readreg[23], SD1_ir[1], RD1_internal_MonDReg[23]);

--SD1L37 is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|DRsize[0]~20015 at LC_X46_Y14_N3

--operation mode is normal

SD1L37 = AMPP_FUNCTION(SD1L36, SD1L144, SD1_ir[0], SD1L142);

--SD1L38 is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|DRsize[0]~20016 at LC_X46_Y14_N6

--operation mode is normal

SD1L38 = AMPP_FUNCTION(SD1L36, SD1L144, SD1_ir[0], A1L4);

--GE1_jupdate is std_1c20:inst|jtag_uart:the_jtag_uart|alt_jtag_atlantic:jtag_uart_alt_jtag_atlantic|jupdate at LC_X55_Y19_N2

--operation mode is normal

GE1_jupdate = AMPP_FUNCTION(!A1L5, GE1L1, FF1_state[8], GE1_jupdate, BF4_Q[0], !C1_CLR_SIGNAL);

--YE1_delayed_unxsync_rxdxx2 is std_1c20:inst|uart1:the_uart1|uart1_rx:the_uart1_rx|delayed_unxsync_rxdxx2 at LC_X57_Y22_N3

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

YE1_delayed_unxsync_rxdxx2_lut_out = GND;

YE1_delayed_unxsync_rxdxx2 = DFFEAS(YE1_delayed_unxsync_rxdxx2_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , YE1_sync_rxd, , , VCC);

--YE1_baud_rate_counter[0] is std_1c20:inst|uart1:the_uart1|uart1_rx:the_uart1_rx|baud_rate_counter[0] at LC_X57_Y23_N0

--operation mode is normal

YE1_baud_rate_counter[0]_lut_out = YE1L47 & (YE1_delayed_unxsync_rxdxx2 $ YE1_sync_rxd) # !YE1L47 & (YE1_delayed_unxsync_rxdxx2 $ YE1_sync_rxd # !YE1_baud_rate_counter[0]);

YE1_baud_rate_counter[0] = DFFEAS(YE1_baud_rate_counter[0]_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--YE1_baud_rate_counter[1] is std_1c20:inst|uart1:the_uart1|uart1_rx:the_uart1_rx|baud_rate_counter[1] at LC_X57_Y23_N4

--operation mode is normal

YE1_baud_rate_counter[1]_lut_out = YE1L2 & (YE1_delayed_unxsync_rxdxx2 $ (!YE1_sync_rxd)) # !YE1L2 & YE1L47 & (YE1_delayed_unxsync_rxdxx2 $ !YE1_sync_rxd);

YE1_baud_rate_counter[1] = DFFEAS(YE1_baud_rate_counter[1]_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--YE1_baud_rate_counter[2] is std_1c20:inst|uart1:the_uart1|uart1_rx:the_uart1_rx|baud_rate_counter[2] at LC_X57_Y23_N2

--operation mode is normal

YE1_baud_rate_counter[2]_lut_out = !YE1L47 & YE1L5 & (YE1_delayed_unxsync_rxdxx2 $ !YE1_sync_rxd);

YE1_baud_rate_counter[2] = DFFEAS(YE1_baud_rate_counter[2]_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--YE1_baud_rate_counter[3] is std_1c20:inst|uart1:the_uart1|uart1_rx:the_uart1_rx|baud_rate_counter[3] at LC_X57_Y23_N8

--operation mode is normal

YE1_baud_rate_counter[3]_lut_out = YE1L8 & (YE1_delayed_unxsync_rxdxx2 $ YE1_sync_rxd # !YE1L47) # !YE1L8 & (YE1_delayed_unxsync_rxdxx2 $ (YE1_sync_rxd));

YE1_baud_rate_counter[3] = DFFEAS(YE1_baud_rate_counter[3]_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--YE1L45 is std_1c20:inst|uart1:the_uart1|uart1_rx:the_uart1_rx|Equal0~170 at LC_X57_Y23_N7

--operation mode is normal

YE1L45 = !YE1_baud_rate_counter[2] & !YE1_baud_rate_counter[0] & !YE1_baud_rate_counter[1] & !YE1_baud_rate_counter[3];

--YE1_baud_rate_counter[4] is std_1c20:inst|uart1:the_uart1|uart1_rx:the_uart1_rx|baud_rate_counter[4] at LC_X57_Y23_N5

--operation mode is normal

YE1_baud_rate_counter[4]_lut_out = YE1L47 # YE1L11 # YE1_delayed_unxsync_rxdxx2 $ YE1_sync_rxd;

YE1_baud_rate_counter[4] = DFFEAS(YE1_baud_rate_counter[4]_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--YE1_baud_rate_counter[5] is std_1c20:inst|uart1:the_uart1|uart1_rx:the_uart1_rx|baud_rate_counter[5] at LC_X57_Y23_N6

--operation mode is normal

YE1_baud_rate_counter[5]_lut_out = YE1L47 & (YE1_delayed_unxsync_rxdxx2 $ !YE1_sync_rxd) # !YE1L47 & YE1L15 & (YE1_delayed_unxsync_rxdxx2 $ !YE1_sync_rxd);

YE1_baud_rate_counter[5] = DFFEAS(YE1_baud_rate_counter[5]_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--YE1_baud_rate_counter[6] is std_1c20:inst|uart1:the_uart1|uart1_rx:the_uart1_rx|baud_rate_counter[6] at LC_X57_Y23_N9

--operation mode is normal

YE1_baud_rate_counter[6]_lut_out = YE1L18 & (YE1_delayed_unxsync_rxdxx2 $ YE1_sync_rxd # !YE1L47) # !YE1L18 & (YE1_delayed_unxsync_rxdxx2 $ (YE1_sync_rxd));

YE1_baud_rate_counter[6] = DFFEAS(YE1_baud_rate_counter[6]_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--YE1_baud_rate_counter[7] is std_1c20:inst|uart1:the_uart1|uart1_rx:the_uart1_rx|baud_rate_counter[7] at LC_X57_Y23_N3

--operation mode is normal

YE1_baud_rate_counter[7]_lut_out = YE1L47 # YE1L21 # YE1_delayed_unxsync_rxdxx2 $ YE1_sync_rxd;

YE1_baud_rate_counter[7] = DFFEAS(YE1_baud_rate_counter[7]_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--YE1L46 is std_1c20:inst|uart1:the_uart1|uart1_rx:the_uart1_rx|Equal0~171 at LC_X57_Y23_N1

--operation mode is normal

YE1L46 = !YE1_baud_rate_counter[6] & !YE1_baud_rate_counter[4] & !YE1_baud_rate_counter[5] & !YE1_baud_rate_counter[7];

--YE1_rxd_edge is std_1c20:inst|uart1:the_uart1|uart1_rx:the_uart1_rx|rxd_edge at LC_X57_Y22_N9

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

YE1_sync_rxd_qfbk = YE1_sync_rxd;

YE1_rxd_edge = YE1_sync_rxd_qfbk $ YE1_delayed_unxsync_rxdxx2;

--YE1_sync_rxd is std_1c20:inst|uart1:the_uart1|uart1_rx:the_uart1_rx|sync_rxd at LC_X57_Y22_N9

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

YE1_sync_rxd = DFFEAS(YE1_rxd_edge, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , YE1_d1_source_rxd, , , VCC);

--YE1_baud_rate_counter[8] is std_1c20:inst|uart1:the_uart1|uart1_rx:the_uart1_rx|baud_rate_counter[8] at LC_X57_Y22_N4

--operation mode is normal

YE1_baud_rate_counter[8]_lut_out = YE1L24 & (YE1_sync_rxd $ !YE1_delayed_unxsync_rxdxx2) # !YE1L24 & YE1L47 & (YE1_sync_rxd $ !YE1_delayed_unxsync_rxdxx2);

YE1_baud_rate_counter[8] = DFFEAS(YE1_baud_rate_counter[8]_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--YE1_d1_source_rxd is std_1c20:inst|uart1:the_uart1|uart1_rx:the_uart1_rx|d1_source_rxd at LC_X57_Y22_N7

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

YE1_d1_source_rxd_lut_out = GND;

YE1_d1_source_rxd = DFFEAS(YE1_d1_source_rxd_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , rxd_to_the_uart1, , , VCC);

--M1_slave_nativeaddress_d1[0] is std_1c20:inst|clock_1:the_clock_1|slave_nativeaddress_d1[0] at LC_X51_Y29_N1

--operation mode is normal

M1_slave_nativeaddress_d1[0]_lut_out = S1L1726Q;

M1_slave_nativeaddress_d1[0] = DFFEAS(M1_slave_nativeaddress_d1[0]_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--M1_master_writedata[2] is std_1c20:inst|clock_1:the_clock_1|master_writedata[2] at LC_X46_Y30_N4

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

M1_master_writedata[2]_lut_out = GND;

M1_master_writedata[2] = DFFEAS(M1_master_writedata[2]_lut_out, GLOBAL(PLD_CLOCKINPUT[1]), E1_data_out, , , M1_slave_writedata_d1[2], , , VCC);

--M1_master_nativeaddress[2] is std_1c20:inst|clock_1:the_clock_1|master_nativeaddress[2] at LC_X48_Y29_N2

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

M1_master_nativeaddress[2]_lut_out = GND;

M1_master_nativeaddress[2] = DFFEAS(M1_master_nativeaddress[2]_lut_out, GLOBAL(PLD_CLOCKINPUT[1]), E1_data_out, , , M1_slave_nativeaddress_d1[2], , , VCC);

--Q1L1 is std_1c20:inst|connector_pll:the_connector_pll|control_reg_en~18 at LC_X48_Y29_N1

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

M1_master_nativeaddress[1]_qfbk = M1_master_nativeaddress[1];

Q1L1 = !M1_master_nativeaddress[2] & LC1_master_state[2] & !M1_master_nativeaddress[1]_qfbk & M1_master_nativeaddress[0];

--M1_master_nativeaddress[1] is std_1c20:inst|clock_1:the_clock_1|master_nativeaddress[1] at LC_X48_Y29_N1

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

M1_master_nativeaddress[1] = DFFEAS(Q1L1, GLOBAL(PLD_CLOCKINPUT[1]), E1_data_out, , , M1_slave_nativeaddress_d1[1], , , VCC);

--J1_slave_nativeaddress_d1[0] is std_1c20:inst|clock_0:the_clock_0|slave_nativeaddress_d1[0] at LC_X42_Y29_N4

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

J1_slave_nativeaddress_d1[0]_lut_out = GND;

J1_slave_nativeaddress_d1[0] = DFFEAS(J1_slave_nativeaddress_d1[0]_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , S1L1726Q, , , VCC);

--J1_master_writedata[2] is std_1c20:inst|clock_0:the_clock_0|master_writedata[2] at LC_X51_Y30_N2

--operation mode is normal

J1_master_writedata[2]_lut_out = J1_slave_writedata_d1[2];

J1_master_writedata[2] = DFFEAS(J1_master_writedata[2]_lut_out, GLOBAL(PLD_CLKFB), GLOBAL(D1_data_out), , , , , , );

--J1_master_nativeaddress[2] is std_1c20:inst|clock_0:the_clock_0|master_nativeaddress[2] at LC_X43_Y29_N0

--operation mode is normal

J1_master_nativeaddress[2]_lut_out = J1_slave_nativeaddress_d1[2];

J1_master_nativeaddress[2] = DFFEAS(J1_master_nativeaddress[2]_lut_out, GLOBAL(PLD_CLKFB), GLOBAL(D1_data_out), , , , , , );

--LB1L1 is std_1c20:inst|sdram_pll:the_sdram_pll|control_reg_en~18 at LC_X43_Y29_N1

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

J1_master_nativeaddress[1]_qfbk = J1_master_nativeaddress[1];

LB1L1 = J1_master_nativeaddress[0] & !J1_master_nativeaddress[2] & !J1_master_nativeaddress[1]_qfbk & CC1_master_state[2];

--J1_master_nativeaddress[1] is std_1c20:inst|clock_0:the_clock_0|master_nativeaddress[1] at LC_X43_Y29_N1

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

J1_master_nativeaddress[1] = DFFEAS(LB1L1, GLOBAL(PLD_CLKFB), GLOBAL(D1_data_out), , , J1_slave_nativeaddress_d1[1], , , VCC);

--GE1L58 is std_1c20:inst|jtag_uart:the_jtag_uart|alt_jtag_atlantic:jtag_uart_alt_jtag_atlantic|td_shift[9]~3564 at LC_X53_Y20_N7

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

GE1L58 = AMPP_FUNCTION(GE1_td_shift[7], GE1_count[9]);

--GE1_rdata[4] is std_1c20:inst|jtag_uart:the_jtag_uart|alt_jtag_atlantic:jtag_uart_alt_jtag_atlantic|rdata[4] at LC_X53_Y20_N7

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

GE1_rdata[4] = AMPP_FUNCTION(QC2__clk0, SE1_q_b[4], F1_data_out, GND, GE1L18);

--DE1_write_tx_holding is std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|write_tx_holding at LC_X38_Y28_N3

--operation mode is normal

DE1_write_tx_holding = DE1L163Q & (!DE1_tx_holding_primed # !DE1_transmitting);

--DE1L304 is std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|SCLK_reg~289 at LC_X41_Y28_N5

--operation mode is normal

DE1L304 = DE1L261 & (DE1_state[0] $ !DE1_state[4]);

--RD1L93 is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|MonRd~104 at LC_X45_Y17_N4

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

RD1L93 = AMPP_FUNCTION(V1L46);

--JD1_resetrequest is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_debug:the_cpu_nios2_oci_debug|resetrequest at LC_X45_Y17_N4

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

JD1_resetrequest = AMPP_FUNCTION(QC2__clk0, SD1_internal_jdo1[22], !C1_CLR_SIGNAL, GND, SD1L190);

--GD1_break_readreg[3] is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_break:the_cpu_nios2_oci_break|break_readreg[3] at LC_X48_Y16_N1

--operation mode is normal

GD1_break_readreg[3] = AMPP_FUNCTION(QC2__clk0, SD1L188, SD1_internal_jdo1[37], SD1_internal_jdo1[36], SD1_internal_jdo1[3], !C1_CLR_SIGNAL, SD1L188);

--SD1L127 is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|Mux36~14 at LC_X48_Y16_N5

--operation mode is normal

SD1L127 = AMPP_FUNCTION(SD1_ir[0], SD1_ir[1], RD1_internal_MonDReg[3], GD1_break_readreg[3]);

--GD1_break_readreg[4] is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_break:the_cpu_nios2_oci_break|break_readreg[4] at LC_X52_Y17_N3

--operation mode is normal

GD1_break_readreg[4] = AMPP_FUNCTION(QC2__clk0, SD1_internal_jdo1[36], SD1_internal_jdo1[37], SD1_internal_jdo1[4], SD1L188, !C1_CLR_SIGNAL, SD1L188);

--SD1L126 is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|Mux35~14 at LC_X52_Y17_N2

--operation mode is normal

SD1L126 = AMPP_FUNCTION(SD1_ir[0], SD1_ir[1], RD1_internal_MonDReg[4], GD1_break_readreg[4]);

--GD1_break_readreg[5] is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_break:the_cpu_nios2_oci_break|break_readreg[5] at LC_X52_Y17_N1

--operation mode is normal

GD1_break_readreg[5] = AMPP_FUNCTION(QC2__clk0, SD1L188, SD1_internal_jdo1[37], SD1_internal_jdo1[36], SD1_internal_jdo1[5], !C1_CLR_SIGNAL, SD1L188);

--SD1L125 is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|Mux34~14 at LC_X52_Y17_N6

--operation mode is normal

SD1L125 = AMPP_FUNCTION(SD1_ir[0], RD1_internal_MonDReg[5], SD1_ir[1], GD1_break_readreg[5]);

--GD1_break_readreg[6] is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_break:the_cpu_nios2_oci_break|break_readreg[6] at LC_X51_Y16_N6

--operation mode is normal

GD1_break_readreg[6] = AMPP_FUNCTION(QC2__clk0, SD1_internal_jdo1[37], SD1L188, SD1_internal_jdo1[6], SD1_internal_jdo1[36], !C1_CLR_SIGNAL, SD1L188);

--SD1L124 is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|Mux33~12 at LC_X51_Y16_N4

--operation mode is normal

SD1L124 = AMPP_FUNCTION(GD1_break_readreg[6], SD1_ir[1], RD1_internal_MonDReg[6], SD1_ir[0]);

--SD1L138 is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|Mux44~43 at LC_X53_Y15_N2

--operation mode is normal

SD1L138 = AMPP_FUNCTION(SD1L73Q, SD1_DRsize[0]);

--GD1_break_readreg[7] is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_break:the_cpu_nios2_oci_break|break_readreg[7] at LC_X51_Y16_N3

--operation mode is normal

GD1_break_readreg[7] = AMPP_FUNCTION(QC2__clk0, SD1_internal_jdo1[37], SD1L188, SD1_internal_jdo1[7], SD1_internal_jdo1[36], !C1_CLR_SIGNAL, SD1L188);

--SD1L123 is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|Mux32~14 at LC_X51_Y16_N2

--operation mode is normal

SD1L123 = AMPP_FUNCTION(SD1_ir[1], GD1_break_readreg[7], RD1_internal_MonDReg[7], SD1_ir[0]);

--GD1_break_readreg[8] is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_break:the_cpu_nios2_oci_break|break_readreg[8] at LC_X53_Y17_N8

--operation mode is normal

GD1_break_readreg[8] = AMPP_FUNCTION(QC2__clk0, SD1L188, SD1_internal_jdo1[37], SD1_internal_jdo1[36], SD1_internal_jdo1[8], !C1_CLR_SIGNAL, SD1L188);

--SD1L39 is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|DRsize[0]~20022 at LC_X53_Y17_N1

--operation mode is normal

SD1L39 = AMPP_FUNCTION(SD1_ir[0], SD1_ir[1], GD1_break_readreg[8], RD1_internal_MonDReg[8]);

--GD1_break_readreg[9] is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_break:the_cpu_nios2_oci_break|break_readreg[9] at LC_X53_Y17_N7

--operation mode is normal

GD1_break_readreg[9] = AMPP_FUNCTION(QC2__clk0, SD1_internal_jdo1[36], SD1_internal_jdo1[37], SD1_internal_jdo1[9], SD1L188, !C1_CLR_SIGNAL, SD1L188);

--SD1L40 is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|DRsize[0]~20024 at LC_X53_Y17_N4

--operation mode is normal

SD1L40 = AMPP_FUNCTION(SD1_ir[0], SD1_ir[1], GD1_break_readreg[9], RD1_internal_MonDReg[9]);

--GD1_break_readreg[25] is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_break:the_cpu_nios2_oci_break|break_readreg[25] at LC_X48_Y17_N7

--operation mode is normal

GD1_break_readreg[25] = AMPP_FUNCTION(QC2__clk0, SD1_internal_jdo1[37], SD1_internal_jdo1[25], SD1_internal_jdo1[36], SD1L188, !C1_CLR_SIGNAL, SD1L188);

--SD1L41 is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|DRsize[0]~20026 at LC_X47_Y17_N4

--operation mode is normal

SD1L41 = AMPP_FUNCTION(GD1_break_readreg[25], SD1_ir[1], RD1_internal_MonDReg[25]);

--SD1L42 is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|DRsize[0]~20027 at LC_X47_Y14_N6

--operation mode is normal

SD1L42 = AMPP_FUNCTION(SD1L142, SD1L41, SD1_ir[0], SD1L144);

--SD1L43 is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|DRsize[0]~20028 at LC_X47_Y14_N8

--operation mode is normal

SD1L43 = AMPP_FUNCTION(A1L4, SD1L41, SD1_ir[0], SD1L144);

--GD1_break_readreg[26] is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_break:the_cpu_nios2_oci_break|break_readreg[26] at LC_X48_Y15_N5

--operation mode is normal

GD1_break_readreg[26] = AMPP_FUNCTION(QC2__clk0, SD1L188, SD1_internal_jdo1[37], SD1_internal_jdo1[36], SD1_internal_jdo1[26], !C1_CLR_SIGNAL, SD1L188);

--SD1L44 is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|DRsize[0]~20030 at LC_X48_Y15_N8

--operation mode is normal

SD1L44 = AMPP_FUNCTION(GD1_break_readreg[26], SD1_ir[1], RD1_internal_MonDReg[26]);

--SD1L45 is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|DRsize[0]~20031 at LC_X47_Y14_N2

--operation mode is normal

SD1L45 = AMPP_FUNCTION(SD1L142, SD1L44, SD1_ir[0], SD1L144);

--SD1L46 is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|DRsize[0]~20032 at LC_X47_Y14_N7

--operation mode is normal

SD1L46 = AMPP_FUNCTION(A1L4, SD1L44, SD1_ir[0], SD1L144);

--GD1_break_readreg[27] is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_break:the_cpu_nios2_oci_break|break_readreg[27] at LC_X48_Y16_N0

--operation mode is normal

GD1_break_readreg[27] = AMPP_FUNCTION(QC2__clk0, SD1L188, SD1_internal_jdo1[27], SD1_internal_jdo1[36], SD1_internal_jdo1[37], !C1_CLR_SIGNAL, SD1L188);

--SD1L47 is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|DRsize[0]~20034 at LC_X47_Y16_N2

--operation mode is normal

SD1L47 = AMPP_FUNCTION(GD1_break_readreg[27], RD1_internal_MonDReg[27], SD1_ir[1]);

--SD1L48 is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|DRsize[0]~20035 at LC_X46_Y14_N5

--operation mode is normal

SD1L48 = AMPP_FUNCTION(SD1_ir[1], SD1L47, SD1_ir[0], SD1L143);

--GD1_break_readreg[28] is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_break:the_cpu_nios2_oci_break|break_readreg[28] at LC_X48_Y17_N5

--operation mode is normal

GD1_break_readreg[28] = AMPP_FUNCTION(QC2__clk0, SD1_internal_jdo1[37], SD1L188, SD1_internal_jdo1[36], SD1_internal_jdo1[28], !C1_CLR_SIGNAL, SD1L188);

--SD1L49 is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|DRsize[0]~20037 at LC_X48_Y17_N9

--operation mode is normal

SD1L49 = AMPP_FUNCTION(GD1_break_readreg[28], SD1_ir[1], RD1_internal_MonDReg[28]);

--SD1L50 is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|DRsize[0]~20038 at LC_X47_Y14_N5

--operation mode is normal

SD1L50 = AMPP_FUNCTION(SD1L142, SD1L49, SD1_ir[0], SD1L144);

--SD1L51 is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|DRsize[0]~20039 at LC_X47_Y14_N1

--operation mode is normal

SD1L51 = AMPP_FUNCTION(SD1_ir[0], SD1L144, SD1L49, A1L4);

--GD1_break_readreg[29] is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_break:the_cpu_nios2_oci_break|break_readreg[29] at LC_X48_Y15_N2

--operation mode is normal

GD1_break_readreg[29] = AMPP_FUNCTION(QC2__clk0, SD1L188, SD1_internal_jdo1[37], SD1_internal_jdo1[36], SD1_internal_jdo1[29], !C1_CLR_SIGNAL, SD1L188);

--SD1L52 is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|DRsize[0]~20041 at LC_X51_Y14_N6

--operation mode is normal

SD1L52 = AMPP_FUNCTION(SD1_ir[1], RD1_internal_MonDReg[29], GD1_break_readreg[29]);

--SD1L53 is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|DRsize[0]~20042 at LC_X51_Y14_N3

--operation mode is normal

SD1L53 = AMPP_FUNCTION(SD1L143, SD1_ir[0], SD1_ir[1], SD1L52);

--SD1L134 is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|Mux42~97 at LC_X51_Y15_N5

--operation mode is normal

SD1L134 = AMPP_FUNCTION(SD1_DRsize[1], SD1_DRsize[2], SD1_DRsize[0], altera_internal_jtag);

--SD1L135 is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|Mux42~98 at LC_X51_Y15_N6

--operation mode is normal

SD1L135 = AMPP_FUNCTION(SD1_DRsize[1], SD1_sr[32], SD1_DRsize[0], SD1_DRsize[2]);

--SD1L54 is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|DRsize[0]~20044 at LC_X51_Y15_N2

--operation mode is normal

SD1L54 = AMPP_FUNCTION(SD1L135, SD1L144, A1L4, SD1L134);

--SD1L136 is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|Mux42~99 at LC_X51_Y14_N5

--operation mode is normal

SD1L136 = AMPP_FUNCTION(SD1L135, SD1L134);

--GD1_break_readreg[30] is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_break:the_cpu_nios2_oci_break|break_readreg[30] at LC_X48_Y16_N8

--operation mode is normal

GD1_break_readreg[30] = AMPP_FUNCTION(QC2__clk0, SD1_internal_jdo1[30], SD1L188, SD1_internal_jdo1[36], SD1_internal_jdo1[37], !C1_CLR_SIGNAL, SD1L188);

--SD1L55 is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|DRsize[0]~20045 at LC_X48_Y16_N9

--operation mode is normal

SD1L55 = AMPP_FUNCTION(SD1_ir[1], GD1_break_readreg[30], RD1_internal_MonDReg[30]);

--GD1_break_readreg[31] is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_break:the_cpu_nios2_oci_break|break_readreg[31] at LC_X48_Y15_N3

--operation mode is normal

GD1_break_readreg[31] = AMPP_FUNCTION(QC2__clk0, SD1L188, SD1_internal_jdo1[37], SD1_internal_jdo1[36], SD1_internal_jdo1[31], !C1_CLR_SIGNAL, SD1L188);

--SD1L56 is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|DRsize[0]~20046 at LC_X48_Y15_N6

--operation mode is normal

SD1L56 = AMPP_FUNCTION(RD1_internal_MonDReg[31], SD1_ir[1], GD1_break_readreg[31]);

--SD1L57 is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|DRsize[0]~20047 at LC_X47_Y15_N6

--operation mode is normal

SD1L57 = AMPP_FUNCTION(SD1L56, SD1L144, SD1_ir[0], SD1L142);

--SD1L58 is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|DRsize[0]~20048 at LC_X47_Y15_N9

--operation mode is normal

SD1L58 = AMPP_FUNCTION(SD1L144, SD1_ir[0], A1L4, SD1L56);

--JD1_internal_resetlatch is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_debug:the_cpu_nios2_oci_debug|internal_resetlatch at LC_X45_Y16_N4

--operation mode is normal

JD1_internal_resetlatch = AMPP_FUNCTION(QC2__clk0, SD1L190, SD1_internal_jdo1[24], JD1_internal_resetlatch, JD1L12, VCC);

--SD1L59 is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|DRsize[0]~20050 at LC_X46_Y15_N5

--operation mode is normal

SD1L59 = AMPP_FUNCTION(SD1_ir[1], SD1_ir[0], JD1_internal_resetlatch);

--M1_master_writedata[3] is std_1c20:inst|clock_1:the_clock_1|master_writedata[3] at LC_X46_Y30_N8

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

M1_master_writedata[3]_lut_out = GND;

M1_master_writedata[3] = DFFEAS(M1_master_writedata[3]_lut_out, GLOBAL(PLD_CLOCKINPUT[1]), E1_data_out, , , M1_slave_writedata_d1[3], , , VCC);

--J1_master_writedata[3] is std_1c20:inst|clock_0:the_clock_0|master_writedata[3] at LC_X45_Y31_N4

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

J1_master_writedata[3]_lut_out = GND;

J1_master_writedata[3] = DFFEAS(J1_master_writedata[3]_lut_out, GLOBAL(PLD_CLKFB), GLOBAL(D1_data_out), , , J1_slave_writedata_d1[3], , , VCC);

--GE1L59 is std_1c20:inst|jtag_uart:the_jtag_uart|alt_jtag_atlantic:jtag_uart_alt_jtag_atlantic|td_shift[9]~3566 at LC_X53_Y20_N5

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

GE1L59 = AMPP_FUNCTION(GE1_count[9], GE1_td_shift[8]);

--GE1_rdata[5] is std_1c20:inst|jtag_uart:the_jtag_uart|alt_jtag_atlantic:jtag_uart_alt_jtag_atlantic|rdata[5] at LC_X53_Y20_N5

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

GE1_rdata[5] = AMPP_FUNCTION(QC2__clk0, SE1_q_b[5], F1_data_out, GND, GE1L18);

--XC1L14 is std_1c20:inst|cpu:the_cpu|cpu_test_bench:the_cpu_test_bench|Add0~569 at LC_X35_Y13_N1

--operation mode is arithmetic

XC1L14 = AMPP_FUNCTION(S1L1050, S1L880, XC1L17);

--XC1L15 is std_1c20:inst|cpu:the_cpu|cpu_test_bench:the_cpu_test_bench|Add0~569COUT1_1893 at LC_X35_Y13_N1

--operation mode is arithmetic

XC1L15 = AMPP_FUNCTION(S1L1050, S1L880, XC1L18);

--M1_master_writedata[15] is std_1c20:inst|clock_1:the_clock_1|master_writedata[15] at LC_X51_Y29_N5

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

M1_master_writedata[15]_lut_out = GND;

M1_master_writedata[15] = DFFEAS(M1_master_writedata[15]_lut_out, GLOBAL(PLD_CLOCKINPUT[1]), E1_data_out, , , M1_slave_writedata_d1[15], , , VCC);

--J1_master_writedata[15] is std_1c20:inst|clock_0:the_clock_0|master_writedata[15] at LC_X43_Y29_N9

--operation mode is normal

J1_master_writedata[15]_lut_out = J1_slave_writedata_d1[15];

J1_master_writedata[15] = DFFEAS(J1_master_writedata[15]_lut_out, GLOBAL(PLD_CLKFB), GLOBAL(D1_data_out), , , , , , );

--GD1_break_readreg[10] is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_break:the_cpu_nios2_oci_break|break_readreg[10] at LC_X53_Y17_N3

--operation mode is normal

GD1_break_readreg[10] = AMPP_FUNCTION(QC2__clk0, SD1_internal_jdo1[36], SD1_internal_jdo1[37], SD1_internal_jdo1[10], SD1L188, !C1_CLR_SIGNAL, SD1L188);

--SD1L60 is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|DRsize[0]~20052 at LC_X53_Y17_N6

--operation mode is normal

SD1L60 = AMPP_FUNCTION(SD1_ir[0], SD1_ir[1], RD1_internal_MonDReg[10], GD1_break_readreg[10]);

--GD1_break_readreg[11] is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_break:the_cpu_nios2_oci_break|break_readreg[11] at LC_X53_Y17_N9

--operation mode is normal

GD1_break_readreg[11] = AMPP_FUNCTION(QC2__clk0, SD1_internal_jdo1[36], SD1_internal_jdo1[37], SD1_internal_jdo1[11], SD1L188, !C1_CLR_SIGNAL, SD1L188);

--SD1L61 is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|DRsize[0]~20054 at LC_X53_Y17_N0

--operation mode is normal

SD1L61 = AMPP_FUNCTION(SD1_ir[0], SD1_ir[1], GD1_break_readreg[11], RD1_internal_MonDReg[11]);

--GD1_break_readreg[12] is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_break:the_cpu_nios2_oci_break|break_readreg[12] at LC_X53_Y17_N2

--operation mode is normal

GD1_break_readreg[12] = AMPP_FUNCTION(QC2__clk0, SD1L188, SD1_internal_jdo1[37], SD1_internal_jdo1[36], SD1_internal_jdo1[12], !C1_CLR_SIGNAL, SD1L188);

--SD1L62 is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|DRsize[0]~20056 at LC_X53_Y17_N5

--operation mode is normal

SD1L62 = AMPP_FUNCTION(SD1_ir[0], SD1_ir[1], GD1_break_readreg[12], RD1_internal_MonDReg[12]);

--GD1_break_readreg[13] is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_break:the_cpu_nios2_oci_break|break_readreg[13] at LC_X52_Y17_N0

--operation mode is normal

GD1_break_readreg[13] = AMPP_FUNCTION(QC2__clk0, SD1L188, SD1_internal_jdo1[37], SD1_internal_jdo1[36], SD1_internal_jdo1[13], !C1_CLR_SIGNAL, SD1L188);

--SD1L63 is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|DRsize[0]~20058 at LC_X52_Y17_N4

--operation mode is normal

SD1L63 = AMPP_FUNCTION(SD1_ir[0], SD1_ir[1], RD1_internal_MonDReg[13], GD1_break_readreg[13]);

--GD1_break_readreg[14] is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_break:the_cpu_nios2_oci_break|break_readreg[14] at LC_X52_Y17_N5

--operation mode is normal

GD1_break_readreg[14] = AMPP_FUNCTION(QC2__clk0, SD1_internal_jdo1[36], SD1_internal_jdo1[37], SD1_internal_jdo1[14], SD1L188, !C1_CLR_SIGNAL, SD1L188);

--SD1L122 is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|Mux25~52 at LC_X52_Y17_N7

--operation mode is normal

SD1L122 = AMPP_FUNCTION(SD1_ir[0], SD1_ir[1], RD1_internal_MonDReg[14], GD1_break_readreg[14]);

--SD1L137 is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|Mux43~45 at LC_X52_Y15_N2

--operation mode is normal

SD1L137 = AMPP_FUNCTION(SD1_DRsize[0], SD1_DRsize[2], SD1_DRsize[1]);

--GD1_break_readreg[15] is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_break:the_cpu_nios2_oci_break|break_readreg[15] at LC_X48_Y15_N1

--operation mode is normal

GD1_break_readreg[15] = AMPP_FUNCTION(QC2__clk0, SD1L188, SD1_internal_jdo1[37], SD1_internal_jdo1[36], SD1_internal_jdo1[15], !C1_CLR_SIGNAL, SD1L188);

--SD1L64 is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|DRsize[0]~20060 at LC_X48_Y14_N1

--operation mode is normal

SD1L64 = AMPP_FUNCTION(GD1_break_readreg[15], SD1_ir[1], RD1_internal_MonDReg[15]);

--SD1L65 is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|DRsize[0]~20061 at LC_X48_Y14_N2

--operation mode is normal

SD1L65 = AMPP_FUNCTION(SD1_ir[0], SD1L142, SD1L144, SD1L64);

--SD1L66 is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|DRsize[0]~20062 at LC_X48_Y14_N0

--operation mode is normal

SD1L66 = AMPP_FUNCTION(SD1_ir[0], A1L4, SD1L144, SD1L64);

--GD1_break_readreg[16] is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_break:the_cpu_nios2_oci_break|break_readreg[16] at LC_X48_Y15_N7

--operation mode is normal

GD1_break_readreg[16] = AMPP_FUNCTION(QC2__clk0, SD1_internal_jdo1[16], SD1_internal_jdo1[37], SD1_internal_jdo1[36], SD1L188, !C1_CLR_SIGNAL, SD1L188);

--SD1L67 is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|DRsize[0]~20064 at LC_X48_Y14_N8

--operation mode is normal

SD1L67 = AMPP_FUNCTION(GD1_break_readreg[16], SD1_ir[1], RD1_internal_MonDReg[16]);

--SD1L68 is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|DRsize[0]~20065 at LC_X48_Y14_N9

--operation mode is normal

SD1L68 = AMPP_FUNCTION(SD1_ir[0], SD1L67, SD1L144, SD1L142);

--SD1L69 is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|DRsize[0]~20066 at LC_X48_Y14_N5

--operation mode is normal

SD1L69 = AMPP_FUNCTION(SD1_ir[0], SD1L67, SD1L144, A1L4);

--M1_master_writedata[7] is std_1c20:inst|clock_1:the_clock_1|master_writedata[7] at LC_X47_Y30_N4

--operation mode is normal

M1_master_writedata[7]_lut_out = M1_slave_writedata_d1[7];

M1_master_writedata[7] = DFFEAS(M1_master_writedata[7]_lut_out, GLOBAL(PLD_CLOCKINPUT[1]), E1_data_out, , , , , , );

--J1_master_writedata[7] is std_1c20:inst|clock_0:the_clock_0|master_writedata[7] at LC_X46_Y31_N5

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

J1_master_writedata[7]_lut_out = GND;

J1_master_writedata[7] = DFFEAS(J1_master_writedata[7]_lut_out, GLOBAL(PLD_CLKFB), GLOBAL(D1_data_out), , , J1_slave_writedata_d1[7], , , VCC);

--M1_master_writedata[14] is std_1c20:inst|clock_1:the_clock_1|master_writedata[14] at LC_X46_Y30_N2

--operation mode is normal

M1_master_writedata[14]_lut_out = M1_slave_writedata_d1[14];

M1_master_writedata[14] = DFFEAS(M1_master_writedata[14]_lut_out, GLOBAL(PLD_CLOCKINPUT[1]), E1_data_out, , , , , , );

--J1_master_writedata[14] is std_1c20:inst|clock_0:the_clock_0|master_writedata[14] at LC_X54_Y22_N4

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

J1_master_writedata[14]_lut_out = GND;

J1_master_writedata[14] = DFFEAS(J1_master_writedata[14]_lut_out, GLOBAL(PLD_CLKFB), GLOBAL(D1_data_out), , , J1_slave_writedata_d1[14], , , VCC);

--M1_master_writedata[13] is std_1c20:inst|clock_1:the_clock_1|master_writedata[13] at LC_X51_Y29_N6

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

M1_master_writedata[13]_lut_out = GND;

M1_master_writedata[13] = DFFEAS(M1_master_writedata[13]_lut_out, GLOBAL(PLD_CLOCKINPUT[1]), E1_data_out, , , M1_slave_writedata_d1[13], , , VCC);

--J1_master_writedata[13] is std_1c20:inst|clock_0:the_clock_0|master_writedata[13] at LC_X42_Y29_N5

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

J1_master_writedata[13]_lut_out = GND;

J1_master_writedata[13] = DFFEAS(J1_master_writedata[13]_lut_out, GLOBAL(PLD_CLKFB), GLOBAL(D1_data_out), , , J1_slave_writedata_d1[13], , , VCC);

--M1_master_writedata[12] is std_1c20:inst|clock_1:the_clock_1|master_writedata[12] at LC_X47_Y30_N7

--operation mode is normal

M1_master_writedata[12]_lut_out = M1_slave_writedata_d1[12];

M1_master_writedata[12] = DFFEAS(M1_master_writedata[12]_lut_out, GLOBAL(PLD_CLOCKINPUT[1]), E1_data_out, , , , , , );

--J1_master_writedata[12] is std_1c20:inst|clock_0:the_clock_0|master_writedata[12] at LC_X44_Y31_N4

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

J1_master_writedata[12]_lut_out = GND;

J1_master_writedata[12] = DFFEAS(J1_master_writedata[12]_lut_out, GLOBAL(PLD_CLKFB), GLOBAL(D1_data_out), , , J1_slave_writedata_d1[12], , , VCC);

--J1_master_writedata[11] is std_1c20:inst|clock_0:the_clock_0|master_writedata[11] at LC_X43_Y30_N6

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

J1_master_writedata[11]_lut_out = GND;

J1_master_writedata[11] = DFFEAS(J1_master_writedata[11]_lut_out, GLOBAL(PLD_CLKFB), GLOBAL(D1_data_out), , , J1_slave_writedata_d1[11], , , VCC);

--M1_master_writedata[11] is std_1c20:inst|clock_1:the_clock_1|master_writedata[11] at LC_X47_Y30_N9

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

M1_master_writedata[11]_lut_out = GND;

M1_master_writedata[11] = DFFEAS(M1_master_writedata[11]_lut_out, GLOBAL(PLD_CLOCKINPUT[1]), E1_data_out, , , M1_slave_writedata_d1[11], , , VCC);

--M1_master_writedata[10] is std_1c20:inst|clock_1:the_clock_1|master_writedata[10] at LC_X51_Y29_N4

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

M1_master_writedata[10]_lut_out = GND;

M1_master_writedata[10] = DFFEAS(M1_master_writedata[10]_lut_out, GLOBAL(PLD_CLOCKINPUT[1]), E1_data_out, , , M1_slave_writedata_d1[10], , , VCC);

--J1_master_writedata[10] is std_1c20:inst|clock_0:the_clock_0|master_writedata[10] at LC_X44_Y30_N2

--operation mode is normal

J1_master_writedata[10]_lut_out = J1_slave_writedata_d1[10];

J1_master_writedata[10] = DFFEAS(J1_master_writedata[10]_lut_out, GLOBAL(PLD_CLKFB), GLOBAL(D1_data_out), , , , , , );

--DE1_MISO_reg is std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|MISO_reg at LC_X40_Y29_N9

--operation mode is normal

DE1_MISO_reg_lut_out = DE1_slowcount[0] & (DE1_SCLK_reg & (DE1_MISO_reg) # !DE1_SCLK_reg & EE1_internal_data0out) # !DE1_slowcount[0] & (DE1_MISO_reg);

DE1_MISO_reg = DFFEAS(DE1_MISO_reg_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--M1_master_writedata[9] is std_1c20:inst|clock_1:the_clock_1|master_writedata[9] at LC_X51_Y29_N3

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

M1_master_writedata[9]_lut_out = GND;

M1_master_writedata[9] = DFFEAS(M1_master_writedata[9]_lut_out, GLOBAL(PLD_CLOCKINPUT[1]), E1_data_out, , , M1_slave_writedata_d1[9], , , VCC);

--J1_master_writedata[9] is std_1c20:inst|clock_0:the_clock_0|master_writedata[9] at LC_X52_Y29_N5

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

J1_master_writedata[9]_lut_out = GND;

J1_master_writedata[9] = DFFEAS(J1_master_writedata[9]_lut_out, GLOBAL(PLD_CLKFB), GLOBAL(D1_data_out), , , J1_slave_writedata_d1[9], , , VCC);

--M1_master_writedata[8] is std_1c20:inst|clock_1:the_clock_1|master_writedata[8] at LC_X48_Y29_N7

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

M1_master_writedata[8]_lut_out = GND;

M1_master_writedata[8] = DFFEAS(M1_master_writedata[8]_lut_out, GLOBAL(PLD_CLOCKINPUT[1]), E1_data_out, , , M1_slave_writedata_d1[8], , , VCC);

--J1_master_writedata[8] is std_1c20:inst|clock_0:the_clock_0|master_writedata[8] at LC_X51_Y28_N4

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

J1_master_writedata[8]_lut_out = GND;

J1_master_writedata[8] = DFFEAS(J1_master_writedata[8]_lut_out, GLOBAL(PLD_CLKFB), GLOBAL(D1_data_out), , , J1_slave_writedata_d1[8], , , VCC);

--M1_master_writedata[6] is std_1c20:inst|clock_1:the_clock_1|master_writedata[6] at LC_X48_Y29_N8

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

M1_master_writedata[6]_lut_out = GND;

M1_master_writedata[6] = DFFEAS(M1_master_writedata[6]_lut_out, GLOBAL(PLD_CLOCKINPUT[1]), E1_data_out, , , M1_slave_writedata_d1[6], , , VCC);

--J1_master_writedata[6] is std_1c20:inst|clock_0:the_clock_0|master_writedata[6] at LC_X45_Y30_N6

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

J1_master_writedata[6]_lut_out = GND;

J1_master_writedata[6] = DFFEAS(J1_master_writedata[6]_lut_out, GLOBAL(PLD_CLKFB), GLOBAL(D1_data_out), , , J1_slave_writedata_d1[6], , , VCC);

--M1_master_writedata[4] is std_1c20:inst|clock_1:the_clock_1|master_writedata[4] at LC_X51_Y29_N0

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

M1_master_writedata[4]_lut_out = GND;

M1_master_writedata[4] = DFFEAS(M1_master_writedata[4]_lut_out, GLOBAL(PLD_CLOCKINPUT[1]), E1_data_out, , , M1_slave_writedata_d1[4], , , VCC);

--J1_master_writedata[4] is std_1c20:inst|clock_0:the_clock_0|master_writedata[4] at LC_X45_Y30_N2

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

J1_master_writedata[4]_lut_out = GND;

J1_master_writedata[4] = DFFEAS(J1_master_writedata[4]_lut_out, GLOBAL(PLD_CLKFB), GLOBAL(D1_data_out), , , J1_slave_writedata_d1[4], , , VCC);

--GE1_rdata[6] is std_1c20:inst|jtag_uart:the_jtag_uart|alt_jtag_atlantic:jtag_uart_alt_jtag_atlantic|rdata[6] at LC_X53_Y19_N3

--operation mode is normal

GE1_rdata[6] = AMPP_FUNCTION(QC2__clk0, SE1_q_b[6], F1_data_out, GE1L18);

--M1_master_writedata[5] is std_1c20:inst|clock_1:the_clock_1|master_writedata[5] at LC_X46_Y30_N7

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

M1_master_writedata[5]_lut_out = GND;

M1_master_writedata[5] = DFFEAS(M1_master_writedata[5]_lut_out, GLOBAL(PLD_CLOCKINPUT[1]), E1_data_out, , , M1_slave_writedata_d1[5], , , VCC);

--J1_master_writedata[5] is std_1c20:inst|clock_0:the_clock_0|master_writedata[5] at LC_X43_Y30_N5

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

J1_master_writedata[5]_lut_out = GND;

J1_master_writedata[5] = DFFEAS(J1_master_writedata[5]_lut_out, GLOBAL(PLD_CLKFB), GLOBAL(D1_data_out), , , J1_slave_writedata_d1[5], , , VCC);

--Q1_control_reg_out[0] is std_1c20:inst|connector_pll:the_connector_pll|control_reg_out[0] at LC_X47_Y30_N3

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

Q1_control_reg_out[0]_lut_out = GND;

Q1_control_reg_out[0] = DFFEAS(Q1_control_reg_out[0]_lut_out, GLOBAL(PLD_CLOCKINPUT[1]), E1_data_out, , Q1L1, M1_master_writedata[0], , , VCC);

--LB1_control_reg_out[0] is std_1c20:inst|sdram_pll:the_sdram_pll|control_reg_out[0] at LC_X43_Y29_N4

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

LB1_control_reg_out[0]_lut_out = GND;

LB1_control_reg_out[0] = DFFEAS(LB1_control_reg_out[0]_lut_out, GLOBAL(PLD_CLKFB), GLOBAL(D1_data_out), , LB1L1, J1_master_writedata[0], , , VCC);

--Q1_control_reg_out[1] is std_1c20:inst|connector_pll:the_connector_pll|control_reg_out[1] at LC_X46_Y30_N3

--operation mode is normal

Q1_control_reg_out[1]_lut_out = !M1_master_writedata[1];

Q1_control_reg_out[1] = DFFEAS(Q1_control_reg_out[1]_lut_out, GLOBAL(PLD_CLOCKINPUT[1]), E1_data_out, , Q1L1, , , , );

--LB1_control_reg_out[1] is std_1c20:inst|sdram_pll:the_sdram_pll|control_reg_out[1] at LC_X43_Y29_N6

--operation mode is normal

LB1_control_reg_out[1]_lut_out = !J1_master_writedata[1];

LB1_control_reg_out[1] = DFFEAS(LB1_control_reg_out[1]_lut_out, GLOBAL(PLD_CLKFB), GLOBAL(D1_data_out), , LB1L1, , , , );

--GE1_td_shift[5] is std_1c20:inst|jtag_uart:the_jtag_uart|alt_jtag_atlantic:jtag_uart_alt_jtag_atlantic|td_shift[5] at LC_X53_Y20_N3

--operation mode is normal

GE1_td_shift[5] = AMPP_FUNCTION(A1L5, GE1L53, GE1L63, GE1L61, !C1_CLR_SIGNAL, GE1L52);

--SD1_internal_jdo1[2] is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|internal_jdo1[2] at LC_X52_Y16_N8

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

SD1_internal_jdo1[2] = AMPP_FUNCTION(A1L8, SD1_sr[2], VCC, GND, SD1L144);

--GE1L60 is std_1c20:inst|jtag_uart:the_jtag_uart|alt_jtag_atlantic:jtag_uart_alt_jtag_atlantic|td_shift[9]~3568 at LC_X53_Y20_N0

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

GE1L60 = AMPP_FUNCTION(GE1_count[9], GE1_td_shift[5]);

--GE1_rdata[2] is std_1c20:inst|jtag_uart:the_jtag_uart|alt_jtag_atlantic:jtag_uart_alt_jtag_atlantic|rdata[2] at LC_X53_Y20_N0

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

GE1_rdata[2] = AMPP_FUNCTION(QC2__clk0, SE1_q_b[2], F1_data_out, GND, GE1L18);

--GE1_count[5] is std_1c20:inst|jtag_uart:the_jtag_uart|alt_jtag_atlantic:jtag_uart_alt_jtag_atlantic|count[5] at LC_X54_Y20_N5

--operation mode is normal

GE1_count[5] = AMPP_FUNCTION(A1L5, GE1_count[4], FF1_state[4], !C1_CLR_SIGNAL, GE1L52);

--WE1_full_6 is std_1c20:inst|sdram_s1_arbitrator:the_sdram_s1|rdv_fifo_for_cpu_instruction_master_to_sdram_s1_module:rdv_fifo_for_cpu_instruction_master_to_sdram_s1|full_6 at LC_X23_Y26_N9

--operation mode is normal

WE1_full_6_lut_out = WE1_full_5 & (NB1L37 # !KB1_za_valid);

WE1_full_6 = DFFEAS(WE1_full_6_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , VE1L22, , , , );

--WE1L27 is std_1c20:inst|sdram_s1_arbitrator:the_sdram_s1|rdv_fifo_for_cpu_instruction_master_to_sdram_s1_module:rdv_fifo_for_cpu_instruction_master_to_sdram_s1|process2~1 at LC_X22_Y25_N1

--operation mode is normal

WE1L27 = KB1_za_valid # !WE1_full_5 & NB1L37;

--NC1_internal_slave_read_request is std_1c20:inst|clock_1:the_clock_1|clock_1_slave_FSM:slave_FSM|internal_slave_read_request at LC_X47_Y27_N3

--operation mode is normal

NC1_internal_slave_read_request_lut_out = NC1_internal_slave_read_request $ (NC1L2 & N1L1);

NC1_internal_slave_read_request = DFFEAS(NC1_internal_slave_read_request_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--NC1_internal_slave_write_request is std_1c20:inst|clock_1:the_clock_1|clock_1_slave_FSM:slave_FSM|internal_slave_write_request at LC_X47_Y27_N6

--operation mode is normal

NC1_internal_slave_write_request_lut_out = NC1_internal_slave_write_request $ (NC1L2 & NC1L4);

NC1_internal_slave_write_request = DFFEAS(NC1_internal_slave_write_request_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--EC1_internal_slave_read_request is std_1c20:inst|clock_0:the_clock_0|clock_0_slave_FSM:slave_FSM|internal_slave_read_request at LC_X42_Y27_N3

--operation mode is normal

EC1_internal_slave_read_request_lut_out = EC1_internal_slave_read_request $ (EC1L2 & K1L1);

EC1_internal_slave_read_request = DFFEAS(EC1_internal_slave_read_request_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--EC1_internal_slave_write_request is std_1c20:inst|clock_0:the_clock_0|clock_0_slave_FSM:slave_FSM|internal_slave_write_request at LC_X42_Y27_N5

--operation mode is normal

EC1_internal_slave_write_request_lut_out = EC1_internal_slave_write_request $ (EC1L2 & EC1L4);

EC1_internal_slave_write_request = DFFEAS(EC1_internal_slave_write_request_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--YE1L47 is std_1c20:inst|uart1:the_uart1|uart1_rx:the_uart1_rx|Equal0~172 at LC_X57_Y22_N5

--operation mode is normal

YE1L47 = YE1L46 & !YE1_baud_rate_counter[8] & YE1L45;

--YE1L2 is std_1c20:inst|uart1:the_uart1|uart1_rx:the_uart1_rx|Add0~168 at LC_X58_Y23_N1

--operation mode is arithmetic

YE1L2 = YE1_baud_rate_counter[1] $ !YE1L26;

--YE1L3 is std_1c20:inst|uart1:the_uart1|uart1_rx:the_uart1_rx|Add0~169 at LC_X58_Y23_N1

--operation mode is arithmetic

YE1L3_cout_0 = !YE1_baud_rate_counter[1] & !YE1L26;

YE1L3 = CARRY(YE1L3_cout_0);

--YE1L4 is std_1c20:inst|uart1:the_uart1|uart1_rx:the_uart1_rx|Add0~169COUT1_531 at LC_X58_Y23_N1

--operation mode is arithmetic

YE1L4_cout_1 = !YE1_baud_rate_counter[1] & !YE1L27;

YE1L4 = CARRY(YE1L4_cout_1);

--YE1L5 is std_1c20:inst|uart1:the_uart1|uart1_rx:the_uart1_rx|Add0~170 at LC_X58_Y23_N2

--operation mode is arithmetic

YE1L5 = YE1_baud_rate_counter[2] $ YE1L3;

--YE1L6 is std_1c20:inst|uart1:the_uart1|uart1_rx:the_uart1_rx|Add0~171 at LC_X58_Y23_N2

--operation mode is arithmetic

YE1L6_cout_0 = YE1_baud_rate_counter[2] # !YE1L3;

YE1L6 = CARRY(YE1L6_cout_0);

--YE1L7 is std_1c20:inst|uart1:the_uart1|uart1_rx:the_uart1_rx|Add0~171COUT1_533 at LC_X58_Y23_N2

--operation mode is arithmetic

YE1L7_cout_1 = YE1_baud_rate_counter[2] # !YE1L4;

YE1L7 = CARRY(YE1L7_cout_1);

--YE1L8 is std_1c20:inst|uart1:the_uart1|uart1_rx:the_uart1_rx|Add0~172 at LC_X58_Y23_N3

--operation mode is arithmetic

YE1L8 = YE1_baud_rate_counter[3] $ (!YE1L6);

--YE1L9 is std_1c20:inst|uart1:the_uart1|uart1_rx:the_uart1_rx|Add0~173 at LC_X58_Y23_N3

--operation mode is arithmetic

YE1L9_cout_0 = !YE1_baud_rate_counter[3] & (!YE1L6);

YE1L9 = CARRY(YE1L9_cout_0);

--YE1L10 is std_1c20:inst|uart1:the_uart1|uart1_rx:the_uart1_rx|Add0~173COUT1_535 at LC_X58_Y23_N3

--operation mode is arithmetic

YE1L10_cout_1 = !YE1_baud_rate_counter[3] & (!YE1L7);

YE1L10 = CARRY(YE1L10_cout_1);

--YE1L11 is std_1c20:inst|uart1:the_uart1|uart1_rx:the_uart1_rx|Add0~174 at LC_X58_Y23_N4

--operation mode is arithmetic

YE1L11 = YE1_baud_rate_counter[4] $ YE1L9;

--YE1L12 is std_1c20:inst|uart1:the_uart1|uart1_rx:the_uart1_rx|Add0~175 at LC_X58_Y23_N4

--operation mode is arithmetic

YE1L12 = YE1L13;

--YE1L15 is std_1c20:inst|uart1:the_uart1|uart1_rx:the_uart1_rx|Add0~176 at LC_X58_Y23_N5

--operation mode is arithmetic

YE1L15_carry_eqn = (!YE1L12 & GND) # (YE1L12 & VCC);

YE1L15 = YE1_baud_rate_counter[5] $ (!YE1L15_carry_eqn);

--YE1L16 is std_1c20:inst|uart1:the_uart1|uart1_rx:the_uart1_rx|Add0~177 at LC_X58_Y23_N5

--operation mode is arithmetic

YE1L16_cout_0 = !YE1_baud_rate_counter[5] & (!YE1L12);

YE1L16 = CARRY(YE1L16_cout_0);

--YE1L17 is std_1c20:inst|uart1:the_uart1|uart1_rx:the_uart1_rx|Add0~177COUT1_537 at LC_X58_Y23_N5

--operation mode is arithmetic

YE1L17_cout_1 = !YE1_baud_rate_counter[5] & (!YE1L12);

YE1L17 = CARRY(YE1L17_cout_1);

--YE1L18 is std_1c20:inst|uart1:the_uart1|uart1_rx:the_uart1_rx|Add0~178 at LC_X58_Y23_N6

--operation mode is arithmetic

YE1L18_carry_eqn = (!YE1L12 & YE1L16) # (YE1L12 & YE1L17);

YE1L18 = YE1_baud_rate_counter[6] $ YE1L18_carry_eqn;

--YE1L19 is std_1c20:inst|uart1:the_uart1|uart1_rx:the_uart1_rx|Add0~179 at LC_X58_Y23_N6

--operation mode is arithmetic

YE1L19_cout_0 = YE1_baud_rate_counter[6] # !YE1L16;

YE1L19 = CARRY(YE1L19_cout_0);

--YE1L20 is std_1c20:inst|uart1:the_uart1|uart1_rx:the_uart1_rx|Add0~179COUT1_539 at LC_X58_Y23_N6

--operation mode is arithmetic

YE1L20_cout_1 = YE1_baud_rate_counter[6] # !YE1L17;

YE1L20 = CARRY(YE1L20_cout_1);

--YE1L21 is std_1c20:inst|uart1:the_uart1|uart1_rx:the_uart1_rx|Add0~180 at LC_X58_Y23_N7

--operation mode is arithmetic

YE1L21_carry_eqn = (!YE1L12 & YE1L19) # (YE1L12 & YE1L20);

YE1L21 = YE1_baud_rate_counter[7] $ (!YE1L21_carry_eqn);

--YE1L22 is std_1c20:inst|uart1:the_uart1|uart1_rx:the_uart1_rx|Add0~181 at LC_X58_Y23_N7

--operation mode is arithmetic

YE1L22_cout_0 = !YE1_baud_rate_counter[7] & (!YE1L19);

YE1L22 = CARRY(YE1L22_cout_0);

--YE1L23 is std_1c20:inst|uart1:the_uart1|uart1_rx:the_uart1_rx|Add0~181COUT1_541 at LC_X58_Y23_N7

--operation mode is arithmetic

YE1L23_cout_1 = !YE1_baud_rate_counter[7] & (!YE1L20);

YE1L23 = CARRY(YE1L23_cout_1);

--YE1L24 is std_1c20:inst|uart1:the_uart1|uart1_rx:the_uart1_rx|Add0~182 at LC_X58_Y23_N8

--operation mode is normal

YE1L24_carry_eqn = (!YE1L12 & YE1L22) # (YE1L12 & YE1L23);

YE1L24 = YE1L24_carry_eqn $ YE1_baud_rate_counter[8];

--M1_slave_writedata_d1[2] is std_1c20:inst|clock_1:the_clock_1|slave_writedata_d1[2] at LC_X51_Y30_N4

--operation mode is normal

M1_slave_writedata_d1[2]_lut_out = S1_M_st_data[2];

M1_slave_writedata_d1[2] = DFFEAS(M1_slave_writedata_d1[2]_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--M1_slave_nativeaddress_d1[1] is std_1c20:inst|clock_1:the_clock_1|slave_nativeaddress_d1[1] at LC_X47_Y26_N6

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

M1_slave_nativeaddress_d1[1]_lut_out = GND;

M1_slave_nativeaddress_d1[1] = DFFEAS(M1_slave_nativeaddress_d1[1]_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , S1_M_alu_result[3], , , VCC);

--M1_slave_nativeaddress_d1[2] is std_1c20:inst|clock_1:the_clock_1|slave_nativeaddress_d1[2] at LC_X48_Y26_N2

--operation mode is normal

M1_slave_nativeaddress_d1[2]_lut_out = S1L1738Q;

M1_slave_nativeaddress_d1[2] = DFFEAS(M1_slave_nativeaddress_d1[2]_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--J1_slave_writedata_d1[2] is std_1c20:inst|clock_0:the_clock_0|slave_writedata_d1[2] at LC_X51_Y30_N5

--operation mode is normal

J1_slave_writedata_d1[2]_lut_out = S1_M_st_data[2];

J1_slave_writedata_d1[2] = DFFEAS(J1_slave_writedata_d1[2]_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--J1_slave_nativeaddress_d1[1] is std_1c20:inst|clock_0:the_clock_0|slave_nativeaddress_d1[1] at LC_X47_Y26_N9

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

J1_slave_nativeaddress_d1[1]_lut_out = GND;

J1_slave_nativeaddress_d1[1] = DFFEAS(J1_slave_nativeaddress_d1[1]_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , S1_M_alu_result[3], , , VCC);

--J1_slave_nativeaddress_d1[2] is std_1c20:inst|clock_0:the_clock_0|slave_nativeaddress_d1[2] at LC_X43_Y28_N4

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

J1_slave_nativeaddress_d1[2]_lut_out = GND;

J1_slave_nativeaddress_d1[2] = DFFEAS(J1_slave_nativeaddress_d1[2]_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , S1L1738Q, , , VCC);

--JD1L12 is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_debug:the_cpu_nios2_oci_debug|internal_resetlatch~185 at LC_X45_Y16_N3

--operation mode is normal

JD1L12 = AMPP_FUNCTION(JD1_internal_resetlatch, F1_data_out, C1_CLR_SIGNAL);

--M1_slave_writedata_d1[3] is std_1c20:inst|clock_1:the_clock_1|slave_writedata_d1[3] at LC_X45_Y31_N5

--operation mode is normal

M1_slave_writedata_d1[3]_lut_out = S1_M_st_data[3];

M1_slave_writedata_d1[3] = DFFEAS(M1_slave_writedata_d1[3]_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--J1_slave_writedata_d1[3] is std_1c20:inst|clock_0:the_clock_0|slave_writedata_d1[3] at LC_X45_Y31_N2

--operation mode is normal

J1_slave_writedata_d1[3]_lut_out = S1_M_st_data[3];

J1_slave_writedata_d1[3] = DFFEAS(J1_slave_writedata_d1[3]_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--XC1L17 is std_1c20:inst|cpu:the_cpu|cpu_test_bench:the_cpu_test_bench|Add0~571 at LC_X35_Y13_N0

--operation mode is arithmetic

XC1L17 = AMPP_FUNCTION(S1L1045, S1L879);

--XC1L18 is std_1c20:inst|cpu:the_cpu|cpu_test_bench:the_cpu_test_bench|Add0~571COUT1_1891 at LC_X35_Y13_N0

--operation mode is arithmetic

XC1L18 = AMPP_FUNCTION(S1L1045, S1L879);

--M1_slave_writedata_d1[15] is std_1c20:inst|clock_1:the_clock_1|slave_writedata_d1[15] at LC_X51_Y29_N7

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

M1_slave_writedata_d1[15]_lut_out = GND;

M1_slave_writedata_d1[15] = DFFEAS(M1_slave_writedata_d1[15]_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , S1L2319Q, , , VCC);

--J1_slave_writedata_d1[15] is std_1c20:inst|clock_0:the_clock_0|slave_writedata_d1[15] at LC_X36_Y29_N1

--operation mode is normal

J1_slave_writedata_d1[15]_lut_out = S1L2319Q;

J1_slave_writedata_d1[15] = DFFEAS(J1_slave_writedata_d1[15]_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--M1_slave_writedata_d1[7] is std_1c20:inst|clock_1:the_clock_1|slave_writedata_d1[7] at LC_X46_Y31_N4

--operation mode is normal

M1_slave_writedata_d1[7]_lut_out = S1_M_st_data[7];

M1_slave_writedata_d1[7] = DFFEAS(M1_slave_writedata_d1[7]_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--J1_slave_writedata_d1[7] is std_1c20:inst|clock_0:the_clock_0|slave_writedata_d1[7] at LC_X46_Y31_N2

--operation mode is normal

J1_slave_writedata_d1[7]_lut_out = S1_M_st_data[7];

J1_slave_writedata_d1[7] = DFFEAS(J1_slave_writedata_d1[7]_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--M1_slave_writedata_d1[14] is std_1c20:inst|clock_1:the_clock_1|slave_writedata_d1[14] at LC_X46_Y28_N4

--operation mode is normal

M1_slave_writedata_d1[14]_lut_out = S1L2313Q;

M1_slave_writedata_d1[14] = DFFEAS(M1_slave_writedata_d1[14]_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--J1_slave_writedata_d1[14] is std_1c20:inst|clock_0:the_clock_0|slave_writedata_d1[14] at LC_X54_Y22_N2

--operation mode is normal

J1_slave_writedata_d1[14]_lut_out = S1L2313Q;

J1_slave_writedata_d1[14] = DFFEAS(J1_slave_writedata_d1[14]_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--M1_slave_writedata_d1[13] is std_1c20:inst|clock_1:the_clock_1|slave_writedata_d1[13] at LC_X51_Y29_N8

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

M1_slave_writedata_d1[13]_lut_out = GND;

M1_slave_writedata_d1[13] = DFFEAS(M1_slave_writedata_d1[13]_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , S1L2307Q, , , VCC);

--J1_slave_writedata_d1[13] is std_1c20:inst|clock_0:the_clock_0|slave_writedata_d1[13] at LC_X42_Y29_N2

--operation mode is normal

J1_slave_writedata_d1[13]_lut_out = S1L2307Q;

J1_slave_writedata_d1[13] = DFFEAS(J1_slave_writedata_d1[13]_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--M1_slave_writedata_d1[12] is std_1c20:inst|clock_1:the_clock_1|slave_writedata_d1[12] at LC_X44_Y31_N5

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

M1_slave_writedata_d1[12]_lut_out = GND;

M1_slave_writedata_d1[12] = DFFEAS(M1_slave_writedata_d1[12]_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , S1L2301Q, , , VCC);

--J1_slave_writedata_d1[12] is std_1c20:inst|clock_0:the_clock_0|slave_writedata_d1[12] at LC_X44_Y31_N2

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

J1_slave_writedata_d1[12]_lut_out = GND;

J1_slave_writedata_d1[12] = DFFEAS(J1_slave_writedata_d1[12]_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , S1L2301Q, , , VCC);

--J1_slave_writedata_d1[11] is std_1c20:inst|clock_0:the_clock_0|slave_writedata_d1[11] at LC_X43_Y30_N4

--operation mode is normal

J1_slave_writedata_d1[11]_lut_out = S1L2294Q;

J1_slave_writedata_d1[11] = DFFEAS(J1_slave_writedata_d1[11]_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--M1_slave_writedata_d1[11] is std_1c20:inst|clock_1:the_clock_1|slave_writedata_d1[11] at LC_X43_Y30_N7

--operation mode is normal

M1_slave_writedata_d1[11]_lut_out = S1L2294Q;

M1_slave_writedata_d1[11] = DFFEAS(M1_slave_writedata_d1[11]_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--M1_slave_writedata_d1[10] is std_1c20:inst|clock_1:the_clock_1|slave_writedata_d1[10] at LC_X51_Y29_N2

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

M1_slave_writedata_d1[10]_lut_out = GND;

M1_slave_writedata_d1[10] = DFFEAS(M1_slave_writedata_d1[10]_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , S1L2288Q, , , VCC);

--J1_slave_writedata_d1[10] is std_1c20:inst|clock_0:the_clock_0|slave_writedata_d1[10] at LC_X44_Y29_N7

--operation mode is normal

J1_slave_writedata_d1[10]_lut_out = S1L2288Q;

J1_slave_writedata_d1[10] = DFFEAS(J1_slave_writedata_d1[10]_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--EE1_internal_data0out is std_1c20:inst|epcs_controller:the_epcs_controller|tornado_epcs_controller_atom:the_tornado_epcs_controller_atom|internal_data0out at ASMIBLOCK_X1_Y16_N3

EE1_internal_data0out = ASMIBLOCK(DE1_SCLK_reg, DE1L326, DE1_shift_reg[7], GND).DATA0OUT;

--M1_slave_writedata_d1[9] is std_1c20:inst|clock_1:the_clock_1|slave_writedata_d1[9] at LC_X52_Y29_N2

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

M1_slave_writedata_d1[9]_lut_out = GND;

M1_slave_writedata_d1[9] = DFFEAS(M1_slave_writedata_d1[9]_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , S1L2281Q, , , VCC);

--J1_slave_writedata_d1[9] is std_1c20:inst|clock_0:the_clock_0|slave_writedata_d1[9] at LC_X52_Y29_N4

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

J1_slave_writedata_d1[9]_lut_out = GND;

J1_slave_writedata_d1[9] = DFFEAS(J1_slave_writedata_d1[9]_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , S1L2281Q, , , VCC);

--M1_slave_writedata_d1[8] is std_1c20:inst|clock_1:the_clock_1|slave_writedata_d1[8] at LC_X51_Y28_N5

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

M1_slave_writedata_d1[8]_lut_out = GND;

M1_slave_writedata_d1[8] = DFFEAS(M1_slave_writedata_d1[8]_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , S1L2275Q, , , VCC);

--J1_slave_writedata_d1[8] is std_1c20:inst|clock_0:the_clock_0|slave_writedata_d1[8] at LC_X51_Y28_N2

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

J1_slave_writedata_d1[8]_lut_out = GND;

J1_slave_writedata_d1[8] = DFFEAS(J1_slave_writedata_d1[8]_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , S1L2275Q, , , VCC);

--M1_slave_writedata_d1[6] is std_1c20:inst|clock_1:the_clock_1|slave_writedata_d1[6] at LC_X51_Y27_N4

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

M1_slave_writedata_d1[6]_lut_out = GND;

M1_slave_writedata_d1[6] = DFFEAS(M1_slave_writedata_d1[6]_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , S1_M_st_data[6], , , VCC);

--J1_slave_writedata_d1[6] is std_1c20:inst|clock_0:the_clock_0|slave_writedata_d1[6] at LC_X47_Y26_N4

--operation mode is normal

J1_slave_writedata_d1[6]_lut_out = S1_M_st_data[6];

J1_slave_writedata_d1[6] = DFFEAS(J1_slave_writedata_d1[6]_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--M1_slave_writedata_d1[4] is std_1c20:inst|clock_1:the_clock_1|slave_writedata_d1[4] at LC_X51_Y29_N9

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

M1_slave_writedata_d1[4]_lut_out = GND;

M1_slave_writedata_d1[4] = DFFEAS(M1_slave_writedata_d1[4]_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , S1_M_st_data[4], , , VCC);

--J1_slave_writedata_d1[4] is std_1c20:inst|clock_0:the_clock_0|slave_writedata_d1[4] at LC_X48_Y30_N4

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

J1_slave_writedata_d1[4]_lut_out = GND;

J1_slave_writedata_d1[4] = DFFEAS(J1_slave_writedata_d1[4]_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , S1_M_st_data[4], , , VCC);

--M1_slave_writedata_d1[5] is std_1c20:inst|clock_1:the_clock_1|slave_writedata_d1[5] at LC_X48_Y30_N5

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

M1_slave_writedata_d1[5]_lut_out = GND;

M1_slave_writedata_d1[5] = DFFEAS(M1_slave_writedata_d1[5]_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , S1_M_st_data[5], , , VCC);

--J1_slave_writedata_d1[5] is std_1c20:inst|clock_0:the_clock_0|slave_writedata_d1[5] at LC_X43_Y30_N8

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

J1_slave_writedata_d1[5]_lut_out = GND;

J1_slave_writedata_d1[5] = DFFEAS(J1_slave_writedata_d1[5]_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , S1_M_st_data[5], , , VCC);

--M1_master_writedata[0] is std_1c20:inst|clock_1:the_clock_1|master_writedata[0] at LC_X47_Y30_N2

--operation mode is normal

M1_master_writedata[0]_lut_out = M1_slave_writedata_d1[0];

M1_master_writedata[0] = DFFEAS(M1_master_writedata[0]_lut_out, GLOBAL(PLD_CLOCKINPUT[1]), E1_data_out, , , , , , );

--J1_master_writedata[0] is std_1c20:inst|clock_0:the_clock_0|master_writedata[0] at LC_X43_Y30_N9

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

J1_master_writedata[0]_lut_out = GND;

J1_master_writedata[0] = DFFEAS(J1_master_writedata[0]_lut_out, GLOBAL(PLD_CLKFB), GLOBAL(D1_data_out), , , J1_slave_writedata_d1[0], , , VCC);

--M1_master_writedata[1] is std_1c20:inst|clock_1:the_clock_1|master_writedata[1] at LC_X46_Y30_N5

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

M1_master_writedata[1]_lut_out = GND;

M1_master_writedata[1] = DFFEAS(M1_master_writedata[1]_lut_out, GLOBAL(PLD_CLOCKINPUT[1]), E1_data_out, , , M1_slave_writedata_d1[1], , , VCC);

--J1_master_writedata[1] is std_1c20:inst|clock_0:the_clock_0|master_writedata[1] at LC_X43_Y31_N4

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

J1_master_writedata[1]_lut_out = GND;

J1_master_writedata[1] = DFFEAS(J1_master_writedata[1]_lut_out, GLOBAL(PLD_CLKFB), GLOBAL(D1_data_out), , , J1_slave_writedata_d1[1], , , VCC);

--GE1L61 is std_1c20:inst|jtag_uart:the_jtag_uart|alt_jtag_atlantic:jtag_uart_alt_jtag_atlantic|td_shift[9]~3571 at LC_X53_Y20_N2

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

GE1L61 = AMPP_FUNCTION(GE1_count[9], GE1_td_shift[6]);

--GE1_rdata[3] is std_1c20:inst|jtag_uart:the_jtag_uart|alt_jtag_atlantic:jtag_uart_alt_jtag_atlantic|rdata[3] at LC_X53_Y20_N2

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

GE1_rdata[3] = AMPP_FUNCTION(QC2__clk0, SE1_q_b[3], F1_data_out, GND, GE1L18);

--GE1_count[4] is std_1c20:inst|jtag_uart:the_jtag_uart|alt_jtag_atlantic:jtag_uart_alt_jtag_atlantic|count[4] at LC_X54_Y20_N8

--operation mode is normal

GE1_count[4] = AMPP_FUNCTION(A1L5, GE1_count[3], FF1_state[4], !C1_CLR_SIGNAL, GE1L52);

--WE1L26 is std_1c20:inst|sdram_s1_arbitrator:the_sdram_s1|rdv_fifo_for_cpu_instruction_master_to_sdram_s1_module:rdv_fifo_for_cpu_instruction_master_to_sdram_s1|process0~1 at LC_X22_Y25_N3

--operation mode is normal

WE1L26 = KB1_za_valid # !WE1_full_6 & NB1L37;

--NC1L2 is std_1c20:inst|clock_1:the_clock_1|clock_1_slave_FSM:slave_FSM|internal_slave_read_request~33 at LC_X47_Y27_N8

--operation mode is normal

NC1L2 = !NC1_slave_state[1] & !NC1_slave_state[0] & !NC1_slave_state[2];

--EC1L2 is std_1c20:inst|clock_0:the_clock_0|clock_0_slave_FSM:slave_FSM|internal_slave_read_request~33 at LC_X42_Y27_N8

--operation mode is normal

EC1L2 = !EC1_slave_state[2] & !EC1_slave_state[0] & !EC1_slave_state[1];

--YE1L26 is std_1c20:inst|uart1:the_uart1|uart1_rx:the_uart1_rx|Add0~185 at LC_X58_Y23_N0

--operation mode is arithmetic

YE1L26_cout_0 = YE1_baud_rate_counter[0];

YE1L26 = CARRY(YE1L26_cout_0);

--YE1L27 is std_1c20:inst|uart1:the_uart1|uart1_rx:the_uart1_rx|Add0~185COUT1_529 at LC_X58_Y23_N0

--operation mode is arithmetic

YE1L27_cout_1 = YE1_baud_rate_counter[0];

YE1L27 = CARRY(YE1L27_cout_1);

--XC1L20 is std_1c20:inst|cpu:the_cpu|cpu_test_bench:the_cpu_test_bench|Add0~573 at LC_X35_Y14_N9

--operation mode is arithmetic

XC1L20 = AMPP_FUNCTION(S1L878, S1L1040, XC1L34, XC1L22, XC1L23);

--DE1L326 is std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|SS_n~16 at LC_X37_Y27_N4

--operation mode is normal

DE1L326 = DE1L216Q # !DE1_SSO_reg & (!DE1_transmitting # !DE1_stateZero);

--M1_slave_writedata_d1[0] is std_1c20:inst|clock_1:the_clock_1|slave_writedata_d1[0] at LC_X47_Y27_N1

--operation mode is normal

M1_slave_writedata_d1[0]_lut_out = S1_M_st_data[0];

M1_slave_writedata_d1[0] = DFFEAS(M1_slave_writedata_d1[0]_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--J1_slave_writedata_d1[0] is std_1c20:inst|clock_0:the_clock_0|slave_writedata_d1[0] at LC_X43_Y30_N2

--operation mode is normal

J1_slave_writedata_d1[0]_lut_out = S1_M_st_data[0];

J1_slave_writedata_d1[0] = DFFEAS(J1_slave_writedata_d1[0]_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--M1_slave_writedata_d1[1] is std_1c20:inst|clock_1:the_clock_1|slave_writedata_d1[1] at LC_X43_Y31_N5

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

M1_slave_writedata_d1[1]_lut_out = GND;

M1_slave_writedata_d1[1] = DFFEAS(M1_slave_writedata_d1[1]_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , S1_M_st_data[1], , , VCC);

--J1_slave_writedata_d1[1] is std_1c20:inst|clock_0:the_clock_0|slave_writedata_d1[1] at LC_X43_Y31_N2

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

J1_slave_writedata_d1[1]_lut_out = GND;

J1_slave_writedata_d1[1] = DFFEAS(J1_slave_writedata_d1[1]_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , S1_M_st_data[1], , , VCC);

--GE1_count[3] is std_1c20:inst|jtag_uart:the_jtag_uart|alt_jtag_atlantic:jtag_uart_alt_jtag_atlantic|count[3] at LC_X54_Y20_N2

--operation mode is normal

GE1_count[3] = AMPP_FUNCTION(A1L5, GE1_count[2], FF1_state[4], !C1_CLR_SIGNAL, GE1L52);

--XC1L22 is std_1c20:inst|cpu:the_cpu|cpu_test_bench:the_cpu_test_bench|Add0~575 at LC_X35_Y14_N8

--operation mode is arithmetic

XC1L22 = AMPP_FUNCTION(S1L877, S1L1035, XC1L25);

--XC1L23 is std_1c20:inst|cpu:the_cpu|cpu_test_bench:the_cpu_test_bench|Add0~575COUT1_1889 at LC_X35_Y14_N8

--operation mode is arithmetic

XC1L23 = AMPP_FUNCTION(S1L877, S1L1035, XC1L26);

--GE1_count[2] is std_1c20:inst|jtag_uart:the_jtag_uart|alt_jtag_atlantic:jtag_uart_alt_jtag_atlantic|count[2] at LC_X54_Y19_N4

--operation mode is normal

GE1_count[2] = AMPP_FUNCTION(A1L5, GE1_count[1], FF1_state[4], !C1_CLR_SIGNAL, GE1L52);

--XC1L25 is std_1c20:inst|cpu:the_cpu|cpu_test_bench:the_cpu_test_bench|Add0~577 at LC_X35_Y14_N7

--operation mode is arithmetic

XC1L25 = AMPP_FUNCTION(S1L1030, S1L876, XC1L28);

--XC1L26 is std_1c20:inst|cpu:the_cpu|cpu_test_bench:the_cpu_test_bench|Add0~577COUT1_1887 at LC_X35_Y14_N7

--operation mode is arithmetic

XC1L26 = AMPP_FUNCTION(S1L1030, S1L876, XC1L29);

--XC1L28 is std_1c20:inst|cpu:the_cpu|cpu_test_bench:the_cpu_test_bench|Add0~579 at LC_X35_Y14_N6

--operation mode is arithmetic

XC1L28 = AMPP_FUNCTION(S1L1025, S1L875, XC1L31);

--XC1L29 is std_1c20:inst|cpu:the_cpu|cpu_test_bench:the_cpu_test_bench|Add0~579COUT1_1885 at LC_X35_Y14_N6

--operation mode is arithmetic

XC1L29 = AMPP_FUNCTION(S1L1025, S1L875, XC1L32);

--XC1L31 is std_1c20:inst|cpu:the_cpu|cpu_test_bench:the_cpu_test_bench|Add0~581 at LC_X35_Y14_N5

--operation mode is arithmetic

XC1L31 = AMPP_FUNCTION(S1L1020, S1L874);

--XC1L32 is std_1c20:inst|cpu:the_cpu|cpu_test_bench:the_cpu_test_bench|Add0~581COUT1_1883 at LC_X35_Y14_N5

--operation mode is arithmetic

XC1L32 = AMPP_FUNCTION(S1L1020, S1L874);

--XC1L34 is std_1c20:inst|cpu:the_cpu|cpu_test_bench:the_cpu_test_bench|Add0~583 at LC_X35_Y14_N4

--operation mode is arithmetic

XC1L34 = AMPP_FUNCTION(S1L1015, S1L873, XC1L48, XC1L36, XC1L37);

--XC1L36 is std_1c20:inst|cpu:the_cpu|cpu_test_bench:the_cpu_test_bench|Add0~585 at LC_X35_Y14_N3

--operation mode is arithmetic

XC1L36 = AMPP_FUNCTION(S1L1007, S1L872, XC1L39);

--XC1L37 is std_1c20:inst|cpu:the_cpu|cpu_test_bench:the_cpu_test_bench|Add0~585COUT1_1881 at LC_X35_Y14_N3

--operation mode is arithmetic

XC1L37 = AMPP_FUNCTION(S1L1007, S1L872, XC1L40);

--XC1L39 is std_1c20:inst|cpu:the_cpu|cpu_test_bench:the_cpu_test_bench|Add0~587 at LC_X35_Y14_N2

--operation mode is arithmetic

XC1L39 = AMPP_FUNCTION(S1L998, S1L871, XC1L42);

--XC1L40 is std_1c20:inst|cpu:the_cpu|cpu_test_bench:the_cpu_test_bench|Add0~587COUT1_1879 at LC_X35_Y14_N2

--operation mode is arithmetic

XC1L40 = AMPP_FUNCTION(S1L998, S1L871, XC1L43);

--XC1L42 is std_1c20:inst|cpu:the_cpu|cpu_test_bench:the_cpu_test_bench|Add0~589 at LC_X35_Y14_N1

--operation mode is arithmetic

XC1L42 = AMPP_FUNCTION(S1L989, S1L870, XC1L45);

--XC1L43 is std_1c20:inst|cpu:the_cpu|cpu_test_bench:the_cpu_test_bench|Add0~589COUT1_1877 at LC_X35_Y14_N1

--operation mode is arithmetic

XC1L43 = AMPP_FUNCTION(S1L989, S1L870, XC1L46);

--XC1L45 is std_1c20:inst|cpu:the_cpu|cpu_test_bench:the_cpu_test_bench|Add0~591 at LC_X35_Y14_N0

--operation mode is arithmetic

XC1L45 = AMPP_FUNCTION(S1L869, S1L980);

--XC1L46 is std_1c20:inst|cpu:the_cpu|cpu_test_bench:the_cpu_test_bench|Add0~591COUT1_1875 at LC_X35_Y14_N0

--operation mode is arithmetic

XC1L46 = AMPP_FUNCTION(S1L869, S1L980);

--XC1L48 is std_1c20:inst|cpu:the_cpu|cpu_test_bench:the_cpu_test_bench|Add0~593 at LC_X35_Y15_N9

--operation mode is arithmetic

XC1L48 = AMPP_FUNCTION(S1L979, S1L868, XC1L62, XC1L50, XC1L51);

--XC1L50 is std_1c20:inst|cpu:the_cpu|cpu_test_bench:the_cpu_test_bench|Add0~595 at LC_X35_Y15_N8

--operation mode is arithmetic

XC1L50 = AMPP_FUNCTION(S1L974, S1L867, XC1L53);

--XC1L51 is std_1c20:inst|cpu:the_cpu|cpu_test_bench:the_cpu_test_bench|Add0~595COUT1_1873 at LC_X35_Y15_N8

--operation mode is arithmetic

XC1L51 = AMPP_FUNCTION(S1L974, S1L867, XC1L54);

--XC1L53 is std_1c20:inst|cpu:the_cpu|cpu_test_bench:the_cpu_test_bench|Add0~597 at LC_X35_Y15_N7

--operation mode is arithmetic

XC1L53 = AMPP_FUNCTION(S1L866, S1L967, XC1L56);

--XC1L54 is std_1c20:inst|cpu:the_cpu|cpu_test_bench:the_cpu_test_bench|Add0~597COUT1_1871 at LC_X35_Y15_N7

--operation mode is arithmetic

XC1L54 = AMPP_FUNCTION(S1L866, S1L967, XC1L57);

--XC1L56 is std_1c20:inst|cpu:the_cpu|cpu_test_bench:the_cpu_test_bench|Add0~599 at LC_X35_Y15_N6

--operation mode is arithmetic

XC1L56 = AMPP_FUNCTION(S1L865, S1L966, XC1L59);

--XC1L57 is std_1c20:inst|cpu:the_cpu|cpu_test_bench:the_cpu_test_bench|Add0~599COUT1_1869 at LC_X35_Y15_N6

--operation mode is arithmetic

XC1L57 = AMPP_FUNCTION(S1L865, S1L966, XC1L60);

--XC1L59 is std_1c20:inst|cpu:the_cpu|cpu_test_bench:the_cpu_test_bench|Add0~601 at LC_X35_Y15_N5

--operation mode is arithmetic

XC1L59 = AMPP_FUNCTION(S1L965, S1L864);

--XC1L60 is std_1c20:inst|cpu:the_cpu|cpu_test_bench:the_cpu_test_bench|Add0~601COUT1_1867 at LC_X35_Y15_N5

--operation mode is arithmetic

XC1L60 = AMPP_FUNCTION(S1L965, S1L864);

--XC1L62 is std_1c20:inst|cpu:the_cpu|cpu_test_bench:the_cpu_test_bench|Add0~603 at LC_X35_Y15_N4

--operation mode is arithmetic

XC1L62 = AMPP_FUNCTION(S1L964, S1L863, XC1L76, XC1L64, XC1L65);

--XC1L64 is std_1c20:inst|cpu:the_cpu|cpu_test_bench:the_cpu_test_bench|Add0~605 at LC_X35_Y15_N3

--operation mode is arithmetic

XC1L64 = AMPP_FUNCTION(S1L963, S1L862, XC1L67);

--XC1L65 is std_1c20:inst|cpu:the_cpu|cpu_test_bench:the_cpu_test_bench|Add0~605COUT1_1865 at LC_X35_Y15_N3

--operation mode is arithmetic

XC1L65 = AMPP_FUNCTION(S1L963, S1L862, XC1L68);

--XC1L67 is std_1c20:inst|cpu:the_cpu|cpu_test_bench:the_cpu_test_bench|Add0~607 at LC_X35_Y15_N2

--operation mode is arithmetic

XC1L67 = AMPP_FUNCTION(S1L861, S1L962, XC1L70);

--XC1L68 is std_1c20:inst|cpu:the_cpu|cpu_test_bench:the_cpu_test_bench|Add0~607COUT1_1863 at LC_X35_Y15_N2

--operation mode is arithmetic

XC1L68 = AMPP_FUNCTION(S1L861, S1L962, XC1L71);

--XC1L70 is std_1c20:inst|cpu:the_cpu|cpu_test_bench:the_cpu_test_bench|Add0~609 at LC_X35_Y15_N1

--operation mode is arithmetic

XC1L70 = AMPP_FUNCTION(S1L860, S1L957, XC1L73);

--XC1L71 is std_1c20:inst|cpu:the_cpu|cpu_test_bench:the_cpu_test_bench|Add0~609COUT1_1861 at LC_X35_Y15_N1

--operation mode is arithmetic

XC1L71 = AMPP_FUNCTION(S1L860, S1L957, XC1L74);

--XC1L73 is std_1c20:inst|cpu:the_cpu|cpu_test_bench:the_cpu_test_bench|Add0~611 at LC_X35_Y15_N0

--operation mode is arithmetic

XC1L73 = AMPP_FUNCTION(S1L859, S1L952);

--XC1L74 is std_1c20:inst|cpu:the_cpu|cpu_test_bench:the_cpu_test_bench|Add0~611COUT1_1859 at LC_X35_Y15_N0

--operation mode is arithmetic

XC1L74 = AMPP_FUNCTION(S1L859, S1L952);

--XC1L76 is std_1c20:inst|cpu:the_cpu|cpu_test_bench:the_cpu_test_bench|Add0~613 at LC_X35_Y16_N9

--operation mode is arithmetic

XC1L76 = AMPP_FUNCTION(S1L947, S1L858, XC1L90, XC1L78, XC1L79);

--XC1L78 is std_1c20:inst|cpu:the_cpu|cpu_test_bench:the_cpu_test_bench|Add0~615 at LC_X35_Y16_N8

--operation mode is arithmetic

XC1L78 = AMPP_FUNCTION(S1L855, S1L942, XC1L81);

--XC1L79 is std_1c20:inst|cpu:the_cpu|cpu_test_bench:the_cpu_test_bench|Add0~615COUT1_1857 at LC_X35_Y16_N8

--operation mode is arithmetic

XC1L79 = AMPP_FUNCTION(S1L855, S1L942, XC1L82);

--XC1L81 is std_1c20:inst|cpu:the_cpu|cpu_test_bench:the_cpu_test_bench|Add0~617 at LC_X35_Y16_N7

--operation mode is arithmetic

XC1L81 = AMPP_FUNCTION(S1L937, S1L854, XC1L84);

--XC1L82 is std_1c20:inst|cpu:the_cpu|cpu_test_bench:the_cpu_test_bench|Add0~617COUT1_1855 at LC_X35_Y16_N7

--operation mode is arithmetic

XC1L82 = AMPP_FUNCTION(S1L937, S1L854, XC1L85);

--XC1L84 is std_1c20:inst|cpu:the_cpu|cpu_test_bench:the_cpu_test_bench|Add0~619 at LC_X35_Y16_N6

--operation mode is arithmetic

XC1L84 = AMPP_FUNCTION(S1L932, S1L853, XC1L87);

--XC1L85 is std_1c20:inst|cpu:the_cpu|cpu_test_bench:the_cpu_test_bench|Add0~619COUT1_1853 at LC_X35_Y16_N6

--operation mode is arithmetic

XC1L85 = AMPP_FUNCTION(S1L932, S1L853, XC1L88);

--XC1L87 is std_1c20:inst|cpu:the_cpu|cpu_test_bench:the_cpu_test_bench|Add0~621 at LC_X35_Y16_N5

--operation mode is arithmetic

XC1L87 = AMPP_FUNCTION(S1L927, S1L852);

--XC1L88 is std_1c20:inst|cpu:the_cpu|cpu_test_bench:the_cpu_test_bench|Add0~621COUT1_1851 at LC_X35_Y16_N5

--operation mode is arithmetic

XC1L88 = AMPP_FUNCTION(S1L927, S1L852);

--XC1L90 is std_1c20:inst|cpu:the_cpu|cpu_test_bench:the_cpu_test_bench|Add0~623 at LC_X35_Y16_N4

--operation mode is arithmetic

XC1L90 = AMPP_FUNCTION(S1L851, S1L922);

--EB1L38 is std_1c20:inst|lcd_display_control_slave_arbitrator:the_lcd_display_control_slave|LessThan0~94 at LC_X35_Y22_N1

--operation mode is normal

EB1L38 = !EB1_lcd_display_control_slave_wait_counter[4] & !EB1_lcd_display_control_slave_wait_counter[5] & EB1L36;

--DB1L5 is std_1c20:inst|lcd_display:the_lcd_display|LCD_E~451 at LC_X35_Y22_N3

--operation mode is normal

DB1L5 = EB1_lcd_display_control_slave_wait_counter[4] & EB1_lcd_display_control_slave_wait_counter[3] & (DB1L2) # !EB1_lcd_display_control_slave_wait_counter[4] & !EB1_lcd_display_control_slave_wait_counter[5] & (!DB1L2 # !EB1_lcd_display_control_slave_wait_counter[3]);

--Y1L913Q is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|last_cycle_cpu_data_master_granted_slave_ext_ram_s1~7 at LC_X34_Y22_N1

--operation mode is normal

Y1L913Q_lut_out = !T1L448Q & !S1L1866Q & (S1_internal_d_write # S1_internal_d_read);

Y1L913Q = DFFEAS(Y1L913Q_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--KB1L246 is std_1c20:inst|sdram:the_sdram|m_cmd~58 at LC_X17_Y22_N9

--operation mode is normal

KB1L246 = KB1_f_pop & (KB1L987 # KB1L988 # !KB1L248);

--KB1L506 is std_1c20:inst|sdram:the_sdram|Mux19~1741 at LC_X12_Y21_N2

--operation mode is normal

KB1L506 = !KB1_m_state[3] & !KB1_m_state[4] & !KB1_init_done & KB1_i_cmd[1];

--S1_W_stall is std_1c20:inst|cpu:the_cpu|W_stall at LC_X34_Y18_N3

--operation mode is normal

S1_W_stall = AMPP_FUNCTION(S1_internal_d_write, S1L2514, T1_internal_cpu_data_master_waitrequest);

--S1L2014Q is std_1c20:inst|cpu:the_cpu|M_alu_result[31]~304 at LC_X34_Y18_N3

--operation mode is normal

S1L2014Q = AMPP_FUNCTION(QC2__clk0, S1_internal_d_write, S1L2514, T1_internal_cpu_data_master_waitrequest, F1_data_out);

--KB1_f_select is std_1c20:inst|sdram:the_sdram|f_select at LC_X17_Y22_N6

--operation mode is normal

KB1_f_select = !KB1L987 & KB1L131 & !KB1L989 & !KB1L988;

--KB1L948 is std_1c20:inst|sdram:the_sdram|Mux118~1221 at LC_X14_Y22_N5

--operation mode is normal

KB1L948 = !KB1_m_state[8] & !KB1_m_state[6] & KB1L518 & !KB1_m_state[5];

--K1L7 is std_1c20:inst|clock_0_in_arbitrator:the_clock_0_in|cpu_data_master_requests_clock_0_in~538 at LC_X34_Y23_N1

--operation mode is normal

K1L7 = !S1_M_alu_result[11] & (S1_internal_d_write # S1_internal_d_read);

--S1L1693Q is std_1c20:inst|cpu:the_cpu|internal_d_write~71 at LC_X31_Y21_N0

--operation mode is normal

S1L1693Q = AMPP_FUNCTION(QC2__clk0, S1L1685, S1L1682, S1L208, S1L1867, F1_data_out);

--S1_D_ic_fill_starting is std_1c20:inst|cpu:the_cpu|D_ic_fill_starting at LC_X24_Y20_N3

--operation mode is normal

S1_D_ic_fill_starting = AMPP_FUNCTION(S1_M_pipe_flush, S1_ic_fill_active, S1L322);

--S1_D_ic_fill_starting_d1 is std_1c20:inst|cpu:the_cpu|D_ic_fill_starting_d1 at LC_X24_Y20_N3

--operation mode is normal

S1_D_ic_fill_starting_d1 = AMPP_FUNCTION(QC2__clk0, S1_M_pipe_flush, S1_ic_fill_active, S1L322, F1_data_out);

--Y1L203Q is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_ext_ram_bus_avalon_slave_end_xfer~6 at LC_X29_Y25_N9

--operation mode is normal

Y1L203Q_lut_out = Y1L122 # U1L223 & (Y1L43 # Y1L40);

Y1L203Q = DFFEAS(Y1L203Q_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--WE1L65 is std_1c20:inst|sdram_s1_arbitrator:the_sdram_s1|rdv_fifo_for_cpu_instruction_master_to_sdram_s1_module:rdv_fifo_for_cpu_instruction_master_to_sdram_s1|updated_one_count~71 at LC_X24_Y23_N7

--operation mode is normal

WE1L65 = !WE1L69 & NB1L25 & (NB1_sdram_s1_arb_addend[1] # !WE1L67);

--WE1L5 is std_1c20:inst|sdram_s1_arbitrator:the_sdram_s1|rdv_fifo_for_cpu_instruction_master_to_sdram_s1_module:rdv_fifo_for_cpu_instruction_master_to_sdram_s1|A_WE_StdLogicVector~1217 at LC_X25_Y24_N1

--operation mode is normal

WE1L5 = WE1_how_many_ones[0] & WE1_how_many_ones[1] & (!WE1L37Q # !KB1_za_valid) # !WE1_how_many_ones[0] & KB1_za_valid & WE1L37Q & !WE1_how_many_ones[1];

--WE1L6 is std_1c20:inst|sdram_s1_arbitrator:the_sdram_s1|rdv_fifo_for_cpu_instruction_master_to_sdram_s1_module:rdv_fifo_for_cpu_instruction_master_to_sdram_s1|A_WE_StdLogicVector~1218 at LC_X25_Y24_N3

--operation mode is normal

WE1_how_many_ones[0]_qfbk = WE1_how_many_ones[0];

WE1L6 = WE1_how_many_ones[0]_qfbk $ WE1L65 $ (KB1_za_valid & WE1L37Q);

--WE1_how_many_ones[0] is std_1c20:inst|sdram_s1_arbitrator:the_sdram_s1|rdv_fifo_for_cpu_instruction_master_to_sdram_s1_module:rdv_fifo_for_cpu_instruction_master_to_sdram_s1|how_many_ones[0] at LC_X25_Y24_N3

--operation mode is normal

WE1_how_many_ones[0] = DFFEAS(WE1L6, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , WE1L33, , , , );

--Y1L879Q is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|lan91c111_s1_wait_counter[0]~114 at LC_X32_Y26_N5

--operation mode is normal

Y1L879Q_lut_out = !Y1L653Q & S1_internal_d_write & Y1L739 & !Y1L718;

Y1L879Q = DFFEAS(Y1L879Q_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--KB1L523 is std_1c20:inst|sdram:the_sdram|Mux24~1470 at LC_X14_Y23_N3

--operation mode is normal

KB1L523 = !KB1_m_count[2] & KB1L521 & !KB1_m_count[1] & KB1L522;

--KB1L515 is std_1c20:inst|sdram:the_sdram|Mux22~1326 at LC_X15_Y22_N0

--operation mode is normal

KB1L515 = KB1_m_state[0] & (!KB1L1011 & !KB1_m_state[2] # !KB1_m_state[8]);

--KB1L516 is std_1c20:inst|sdram:the_sdram|Mux22~1327 at LC_X14_Y23_N4

--operation mode is normal

KB1L516 = KB1_m_next[1] & KB1_m_state[2] & !KB1_m_count[1] & !KB1_m_count[2];

--KB1L549 is std_1c20:inst|sdram:the_sdram|Mux28~1636 at LC_X14_Y23_N8

--operation mode is normal

KB1L549 = KB1_m_count[2] # KB1_m_count[1] # KB1_m_next[1] # !KB1L660;

--KB1L534 is std_1c20:inst|sdram:the_sdram|Mux26~1237 at LC_X17_Y23_N6

--operation mode is normal

KB1L534 = !KB1_refresh_request & !KB1L991 & (TE1_entries[1] # TE1_entries[0]);

--KB1L538 is std_1c20:inst|sdram:the_sdram|Mux27~1234 at LC_X14_Y22_N8

--operation mode is normal

KB1L538 = !KB1_m_state[8] & !KB1_m_state[2] & KB1_m_state[0] & KB1L984;

--TE1L84 is std_1c20:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_0[56]~56 at LC_X23_Y23_N0

--operation mode is normal

TE1L84 = KB1L477 & !TE1_wr_address & (TE1_entries[0] # !TE1_entries[1]);

--TE1L148 is std_1c20:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_1[56]~56 at LC_X23_Y23_N7

--operation mode is normal

TE1L148 = KB1L477 & TE1_wr_address & (TE1_entries[0] # !TE1_entries[1]);

--KB1L461 is std_1c20:inst|sdram:the_sdram|m_next~848 at LC_X17_Y23_N7

--operation mode is normal

KB1L461 = KB1_refresh_request & !KB1L991 & (TE1_entries[1] # TE1_entries[0]);

--KB1L462 is std_1c20:inst|sdram:the_sdram|m_next~849 at LC_X17_Y23_N8

--operation mode is normal

KB1L462 = KB1_refresh_request # KB1L991 & (TE1_entries[1] # TE1_entries[0]);

--XE1L14 is std_1c20:inst|uart1:the_uart1|uart1_regs:the_uart1_regs|control_wr_strobe~27 at LC_X48_Y22_N1

--operation mode is normal

XE1L14 = S1_M_alu_result[3] & !S1L1738Q & S1L1726Q & XE1L13;

--S1L2398 is std_1c20:inst|cpu:the_cpu|M_wr_data_unfiltered[2]~3709 at LC_X39_Y15_N4

--operation mode is normal

S1L2398 = AMPP_FUNCTION(S1_M_shift_rot_result[2], S1L2056Q, S1L2397);

--S1_W_wr_data[2] is std_1c20:inst|cpu:the_cpu|W_wr_data[2] at LC_X39_Y15_N4

--operation mode is normal

S1_W_wr_data[2] = AMPP_FUNCTION(QC2__clk0, S1_M_shift_rot_result[2], S1L2056Q, S1L2397, F1_data_out, S1_W_stall);

--S1L306 is std_1c20:inst|cpu:the_cpu|D_ctrl_jmp_indirect~46 at LC_X32_Y14_N3

--operation mode is normal

S1L306 = AMPP_FUNCTION(S1_D_iw[5], S1_D_iw[4], S1_D_iw[12], S1L1168);

--S1L2401 is std_1c20:inst|cpu:the_cpu|M_wr_data_unfiltered[3]~3710 at LC_X39_Y16_N6

--operation mode is normal

S1L2401 = AMPP_FUNCTION(S1L2056Q, S1L2400, S1_M_shift_rot_result[3]);

--S1_W_wr_data[3] is std_1c20:inst|cpu:the_cpu|W_wr_data[3] at LC_X39_Y16_N6

--operation mode is normal

S1_W_wr_data[3] = AMPP_FUNCTION(QC2__clk0, S1L2056Q, S1L2400, S1_M_shift_rot_result[3], F1_data_out, S1_W_stall);

--S1_E_hbreak_req is std_1c20:inst|cpu:the_cpu|E_hbreak_req at LC_X30_Y15_N5

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

S1_E_hbreak_req = AMPP_FUNCTION(S1_E_iw[13], S1L761, S1L1356);

--S1_E_iw[14] is std_1c20:inst|cpu:the_cpu|E_iw[14] at LC_X30_Y15_N5

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

S1_E_iw[14] = AMPP_FUNCTION(QC2__clk0, S1_D_iw[14], F1_data_out, GND, S1_W_stall);

--S1L83 is std_1c20:inst|cpu:the_cpu|A_WE_StdLogic~280 at LC_X34_Y18_N6

--operation mode is normal

S1L83 = AMPP_FUNCTION(S1L1159, S1_internal_d_write, S1L2514, T1_internal_cpu_data_master_waitrequest);

--S1L2458 is std_1c20:inst|cpu:the_cpu|M_wr_data_unfiltered[22]~3711 at LC_X42_Y16_N6

--operation mode is normal

S1L2458 = AMPP_FUNCTION(S1L2062Q, S1L195Q, S1_M_shift_rot_result[22]);

--S1_W_wr_data[22] is std_1c20:inst|cpu:the_cpu|W_wr_data[22] at LC_X42_Y16_N6

--operation mode is normal

S1_W_wr_data[22] = AMPP_FUNCTION(QC2__clk0, S1L2062Q, S1L195Q, S1_M_shift_rot_result[22], F1_data_out, S1_W_stall);

--S1L2455 is std_1c20:inst|cpu:the_cpu|M_wr_data_unfiltered[21]~3712 at LC_X42_Y14_N2

--operation mode is normal

S1L2455 = AMPP_FUNCTION(S1_M_shift_rot_result[21], S1L192Q, S1L2062Q);

--S1_W_wr_data[21] is std_1c20:inst|cpu:the_cpu|W_wr_data[21] at LC_X42_Y14_N2

--operation mode is normal

S1_W_wr_data[21] = AMPP_FUNCTION(QC2__clk0, S1_M_shift_rot_result[21], S1L192Q, S1L2062Q, F1_data_out, S1_W_stall);

--S1L2449 is std_1c20:inst|cpu:the_cpu|M_wr_data_unfiltered[19]~3713 at LC_X40_Y15_N0

--operation mode is normal

S1L2449 = AMPP_FUNCTION(S1L2448, S1L2062Q, S1_M_shift_rot_result[19]);

--S1_W_wr_data[19] is std_1c20:inst|cpu:the_cpu|W_wr_data[19] at LC_X40_Y15_N0

--operation mode is normal

S1_W_wr_data[19] = AMPP_FUNCTION(QC2__clk0, S1L2448, S1L2062Q, S1_M_shift_rot_result[19], F1_data_out, S1_W_stall);

--S1L2446 is std_1c20:inst|cpu:the_cpu|M_wr_data_unfiltered[18]~3714 at LC_X41_Y15_N7

--operation mode is normal

S1L2446 = AMPP_FUNCTION(S1_M_shift_rot_result[18], S1L2445, S1L2062Q);

--S1_W_wr_data[18] is std_1c20:inst|cpu:the_cpu|W_wr_data[18] at LC_X41_Y15_N7

--operation mode is normal

S1_W_wr_data[18] = AMPP_FUNCTION(QC2__clk0, S1_M_shift_rot_result[18], S1L2445, S1L2062Q, F1_data_out, S1_W_stall);

--S1L2464 is std_1c20:inst|cpu:the_cpu|M_wr_data_unfiltered[24]~3715 at LC_X43_Y17_N7

--operation mode is normal

S1L2464 = AMPP_FUNCTION(S1_M_shift_rot_result[24], S1L2062Q, S1L203Q);

--S1_W_wr_data[24] is std_1c20:inst|cpu:the_cpu|W_wr_data[24] at LC_X43_Y17_N7

--operation mode is normal

S1_W_wr_data[24] = AMPP_FUNCTION(QC2__clk0, S1_M_shift_rot_result[24], S1L2062Q, S1L203Q, F1_data_out, S1_W_stall);

--S1L2440 is std_1c20:inst|cpu:the_cpu|M_wr_data_unfiltered[16]~3716 at LC_X43_Y16_N8

--operation mode is normal

S1L2440 = AMPP_FUNCTION(S1L2062Q, S1L2439, S1_M_shift_rot_result[16]);

--S1_W_wr_data[16] is std_1c20:inst|cpu:the_cpu|W_wr_data[16] at LC_X43_Y16_N8

--operation mode is normal

S1_W_wr_data[16] = AMPP_FUNCTION(QC2__clk0, S1L2062Q, S1L2439, S1_M_shift_rot_result[16], F1_data_out, S1_W_stall);

--S1L2437 is std_1c20:inst|cpu:the_cpu|M_wr_data_unfiltered[15]~3717 at LC_X38_Y17_N0

--operation mode is normal

S1L2437 = AMPP_FUNCTION(S1L2056Q, S1_M_shift_rot_result[15], S1L2436);

--S1_W_wr_data[15] is std_1c20:inst|cpu:the_cpu|W_wr_data[15] at LC_X38_Y17_N0

--operation mode is normal

S1_W_wr_data[15] = AMPP_FUNCTION(QC2__clk0, S1L2056Q, S1_M_shift_rot_result[15], S1L2436, F1_data_out, S1_W_stall);

--S1L2434 is std_1c20:inst|cpu:the_cpu|M_wr_data_unfiltered[14]~3718 at LC_X43_Y17_N8

--operation mode is normal

S1L2434 = AMPP_FUNCTION(S1L2062Q, S1_M_shift_rot_result[14], S1L2433);

--S1_W_wr_data[14] is std_1c20:inst|cpu:the_cpu|W_wr_data[14] at LC_X43_Y17_N8

--operation mode is normal

S1_W_wr_data[14] = AMPP_FUNCTION(QC2__clk0, S1L2062Q, S1_M_shift_rot_result[14], S1L2433, F1_data_out, S1_W_stall);

--S1L2431 is std_1c20:inst|cpu:the_cpu|M_wr_data_unfiltered[13]~3719 at LC_X37_Y19_N8

--operation mode is normal

S1L2431 = AMPP_FUNCTION(S1L2430, S1L2056Q, S1_M_shift_rot_result[13]);

--S1_W_wr_data[13] is std_1c20:inst|cpu:the_cpu|W_wr_data[13] at LC_X37_Y19_N8

--operation mode is normal

S1_W_wr_data[13] = AMPP_FUNCTION(QC2__clk0, S1L2430, S1L2056Q, S1_M_shift_rot_result[13], F1_data_out, S1_W_stall);

--S1L2428 is std_1c20:inst|cpu:the_cpu|M_wr_data_unfiltered[12]~3720 at LC_X42_Y17_N8

--operation mode is normal

S1L2428 = AMPP_FUNCTION(S1_M_shift_rot_result[12], S1L2427, S1L2062Q);

--S1_W_wr_data[12] is std_1c20:inst|cpu:the_cpu|W_wr_data[12] at LC_X42_Y17_N8

--operation mode is normal

S1_W_wr_data[12] = AMPP_FUNCTION(QC2__clk0, S1_M_shift_rot_result[12], S1L2427, S1L2062Q, F1_data_out, S1_W_stall);

--S1L2443 is std_1c20:inst|cpu:the_cpu|M_wr_data_unfiltered[17]~3721 at LC_X42_Y14_N6

--operation mode is normal

S1L2443 = AMPP_FUNCTION(S1L2062Q, S1_M_shift_rot_result[17], S1L2442);

--S1_W_wr_data[17] is std_1c20:inst|cpu:the_cpu|W_wr_data[17] at LC_X42_Y14_N6

--operation mode is normal

S1_W_wr_data[17] = AMPP_FUNCTION(QC2__clk0, S1L2062Q, S1_M_shift_rot_result[17], S1L2442, F1_data_out, S1_W_stall);

--S1L2467 is std_1c20:inst|cpu:the_cpu|M_wr_data_unfiltered[25]~3722 at LC_X39_Y13_N3

--operation mode is normal

S1L2467 = AMPP_FUNCTION(S1L2056Q, S1L211Q, S1_M_shift_rot_result[25]);

--S1_W_wr_data[25] is std_1c20:inst|cpu:the_cpu|W_wr_data[25] at LC_X39_Y13_N3

--operation mode is normal

S1_W_wr_data[25] = AMPP_FUNCTION(QC2__clk0, S1L2056Q, S1L211Q, S1_M_shift_rot_result[25], F1_data_out, S1_W_stall);

--S1L2452 is std_1c20:inst|cpu:the_cpu|M_wr_data_unfiltered[20]~3723 at LC_X40_Y17_N6

--operation mode is normal

S1L2452 = AMPP_FUNCTION(S1_M_shift_rot_result[20], S1L188Q, S1L2062Q);

--S1_W_wr_data[20] is std_1c20:inst|cpu:the_cpu|W_wr_data[20] at LC_X40_Y17_N6

--operation mode is normal

S1_W_wr_data[20] = AMPP_FUNCTION(QC2__clk0, S1_M_shift_rot_result[20], S1L188Q, S1L2062Q, F1_data_out, S1_W_stall);

--S1L2461 is std_1c20:inst|cpu:the_cpu|M_wr_data_unfiltered[23]~3724 at LC_X41_Y13_N1

--operation mode is normal

S1L2461 = AMPP_FUNCTION(S1L2062Q, S1L199Q, S1_M_shift_rot_result[23]);

--S1_W_wr_data[23] is std_1c20:inst|cpu:the_cpu|W_wr_data[23] at LC_X41_Y13_N1

--operation mode is normal

S1_W_wr_data[23] = AMPP_FUNCTION(QC2__clk0, S1L2062Q, S1L199Q, S1_M_shift_rot_result[23], F1_data_out, S1_W_stall);

--S1L2425 is std_1c20:inst|cpu:the_cpu|M_wr_data_unfiltered[11]~3725 at LC_X38_Y15_N7

--operation mode is normal

S1L2425 = AMPP_FUNCTION(S1_M_shift_rot_result[11], S1L2424, S1L2056Q);

--S1_W_wr_data[11] is std_1c20:inst|cpu:the_cpu|W_wr_data[11] at LC_X38_Y15_N7

--operation mode is normal

S1_W_wr_data[11] = AMPP_FUNCTION(QC2__clk0, S1_M_shift_rot_result[11], S1L2424, S1L2056Q, F1_data_out, S1_W_stall);

--S1L2422 is std_1c20:inst|cpu:the_cpu|M_wr_data_unfiltered[10]~3726 at LC_X38_Y18_N9

--operation mode is normal

S1L2422 = AMPP_FUNCTION(S1L2421, S1_M_shift_rot_result[10], S1L2056Q);

--S1_W_wr_data[10] is std_1c20:inst|cpu:the_cpu|W_wr_data[10] at LC_X38_Y18_N9

--operation mode is normal

S1_W_wr_data[10] = AMPP_FUNCTION(QC2__clk0, S1L2421, S1_M_shift_rot_result[10], S1L2056Q, F1_data_out, S1_W_stall);

--S1L2419 is std_1c20:inst|cpu:the_cpu|M_wr_data_unfiltered[9]~3727 at LC_X36_Y18_N9

--operation mode is normal

S1L2419 = AMPP_FUNCTION(S1L2056Q, S1_M_shift_rot_result[9], S1L2418);

--S1_W_wr_data[9] is std_1c20:inst|cpu:the_cpu|W_wr_data[9] at LC_X36_Y18_N9

--operation mode is normal

S1_W_wr_data[9] = AMPP_FUNCTION(QC2__clk0, S1L2056Q, S1_M_shift_rot_result[9], S1L2418, F1_data_out, S1_W_stall);

--S1L2416 is std_1c20:inst|cpu:the_cpu|M_wr_data_unfiltered[8]~3728 at LC_X37_Y18_N8

--operation mode is normal

S1L2416 = AMPP_FUNCTION(S1L2056Q, S1L2415, S1_M_shift_rot_result[8]);

--S1_W_wr_data[8] is std_1c20:inst|cpu:the_cpu|W_wr_data[8] at LC_X37_Y18_N8

--operation mode is normal

S1_W_wr_data[8] = AMPP_FUNCTION(QC2__clk0, S1L2056Q, S1L2415, S1_M_shift_rot_result[8], F1_data_out, S1_W_stall);

--S1L2413 is std_1c20:inst|cpu:the_cpu|M_wr_data_unfiltered[7]~3729 at LC_X42_Y19_N9

--operation mode is normal

S1L2413 = AMPP_FUNCTION(S1L2412, S1L2062Q, S1_M_shift_rot_result[7]);

--S1_W_wr_data[7] is std_1c20:inst|cpu:the_cpu|W_wr_data[7] at LC_X42_Y19_N9

--operation mode is normal

S1_W_wr_data[7] = AMPP_FUNCTION(QC2__clk0, S1L2412, S1L2062Q, S1_M_shift_rot_result[7], F1_data_out, S1_W_stall);

--S1L2410 is std_1c20:inst|cpu:the_cpu|M_wr_data_unfiltered[6]~3730 at LC_X36_Y17_N7

--operation mode is normal

S1L2410 = AMPP_FUNCTION(S1_M_shift_rot_result[6], S1L2056Q, S1L2409);

--S1_W_wr_data[6] is std_1c20:inst|cpu:the_cpu|W_wr_data[6] at LC_X36_Y17_N7

--operation mode is normal

S1_W_wr_data[6] = AMPP_FUNCTION(QC2__clk0, S1_M_shift_rot_result[6], S1L2056Q, S1L2409, F1_data_out, S1_W_stall);

--S1L2404 is std_1c20:inst|cpu:the_cpu|M_wr_data_unfiltered[4]~3731 at LC_X41_Y16_N9

--operation mode is normal

S1L2404 = AMPP_FUNCTION(S1L2062Q, S1_M_shift_rot_result[4], S1L2403);

--S1_W_wr_data[4] is std_1c20:inst|cpu:the_cpu|W_wr_data[4] at LC_X41_Y16_N9

--operation mode is normal

S1_W_wr_data[4] = AMPP_FUNCTION(QC2__clk0, S1L2062Q, S1_M_shift_rot_result[4], S1L2403, F1_data_out, S1_W_stall);

--S1L2407 is std_1c20:inst|cpu:the_cpu|M_wr_data_unfiltered[5]~3732 at LC_X39_Y18_N7

--operation mode is normal

S1L2407 = AMPP_FUNCTION(S1L2061Q, S1_M_shift_rot_result[5], S1L2406);

--S1_W_wr_data[5] is std_1c20:inst|cpu:the_cpu|W_wr_data[5] at LC_X39_Y18_N7

--operation mode is normal

S1_W_wr_data[5] = AMPP_FUNCTION(QC2__clk0, S1L2061Q, S1_M_shift_rot_result[5], S1L2406, F1_data_out, S1_W_stall);

--S1L2395 is std_1c20:inst|cpu:the_cpu|M_wr_data_unfiltered[1]~3733 at LC_X40_Y16_N2

--operation mode is normal

S1L2395 = AMPP_FUNCTION(S1_M_shift_rot_result[1], S1L2062Q, S1L1718);

--S1_W_wr_data[1] is std_1c20:inst|cpu:the_cpu|W_wr_data[1] at LC_X40_Y16_N2

--operation mode is normal

S1_W_wr_data[1] = AMPP_FUNCTION(QC2__clk0, S1_M_shift_rot_result[1], S1L2062Q, S1L1718, F1_data_out, S1_W_stall);

--S1L2392 is std_1c20:inst|cpu:the_cpu|M_wr_data_unfiltered[0]~3734 at LC_X37_Y16_N2

--operation mode is normal

S1L2392 = AMPP_FUNCTION(S1_M_shift_rot_result[0], S1L2056Q, S1L231);

--S1_W_wr_data[0] is std_1c20:inst|cpu:the_cpu|W_wr_data[0] at LC_X37_Y16_N2

--operation mode is normal

S1_W_wr_data[0] = AMPP_FUNCTION(QC2__clk0, S1_M_shift_rot_result[0], S1L2056Q, S1L231, F1_data_out, S1_W_stall);

--V1L43Q is std_1c20:inst|cpu_jtag_debug_module_arbitrator:the_cpu_jtag_debug_module|cpu_jtag_debug_module_arb_addend[1]~763 at LC_X35_Y24_N8

--operation mode is normal

V1L43Q_lut_out = V1L39 & !S1L1451 & (!V1L8 # !K1L3);

V1L43Q = DFFEAS(V1L43Q_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--V1L30 is std_1c20:inst|cpu_jtag_debug_module_arbitrator:the_cpu_jtag_debug_module|cpu_jtag_debug_module_arb_addend[0]~750 at LC_X35_Y24_N2

--operation mode is normal

V1L30 = !V1L34Q & !S1L1451 & (!V1L8 # !K1L3);

--V1L32Q is std_1c20:inst|cpu_jtag_debug_module_arbitrator:the_cpu_jtag_debug_module|cpu_jtag_debug_module_arb_addend[0]~756 at LC_X35_Y24_N2

--operation mode is normal

V1L32Q = DFFEAS(V1L30, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--X1L13 is std_1c20:inst|epcs_controller_epcs_control_port_arbitrator:the_epcs_controller_epcs_control_port|cpu_instruction_master_read_data_valid_epcs_controller_epcs_control_port~18 at LC_X33_Y24_N9

--operation mode is normal

X1L13 = X1L16 & !V1L58 & !S1L1593Q & X1_cpu_instruction_master_granted_epcs_controller_epcs_control_port;

--VE1L5 is std_1c20:inst|sdram_s1_arbitrator:the_sdram_s1|rdv_fifo_for_cpu_data_master_to_sdram_s1_module:rdv_fifo_for_cpu_data_master_to_sdram_s1|A_WE_StdLogicVector~1210 at LC_X23_Y24_N1

--operation mode is normal

VE1L5 = VE1_how_many_ones[0] & VE1_how_many_ones[1] & (!VE1L24Q # !KB1_za_valid) # !VE1_how_many_ones[0] & KB1_za_valid & VE1L24Q & !VE1_how_many_ones[1];

--VE1L6 is std_1c20:inst|sdram_s1_arbitrator:the_sdram_s1|rdv_fifo_for_cpu_data_master_to_sdram_s1_module:rdv_fifo_for_cpu_data_master_to_sdram_s1|A_WE_StdLogicVector~1211 at LC_X23_Y24_N4

--operation mode is normal

VE1_how_many_ones[0]_qfbk = VE1_how_many_ones[0];

VE1L6 = VE1_how_many_ones[0]_qfbk $ VE1L49 $ (KB1_za_valid & VE1L24Q);

--VE1_how_many_ones[0] is std_1c20:inst|sdram_s1_arbitrator:the_sdram_s1|rdv_fifo_for_cpu_data_master_to_sdram_s1_module:rdv_fifo_for_cpu_data_master_to_sdram_s1|how_many_ones[0] at LC_X23_Y24_N4

--operation mode is normal

VE1_how_many_ones[0] = DFFEAS(VE1L6, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , WE1L33, , , , );

--NB1L84 is std_1c20:inst|sdram_s1_arbitrator:the_sdram_s1|sdram_s1_end_xfer~20 at LC_X23_Y23_N2

--operation mode is normal

NB1L84 = !TE1_entries[0] & (TE1_entries[1] & KB1L477);

--NB1_d1_reasons_to_wait is std_1c20:inst|sdram_s1_arbitrator:the_sdram_s1|d1_reasons_to_wait at LC_X23_Y23_N2

--operation mode is normal

NB1_d1_reasons_to_wait = DFFEAS(NB1L84, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--N1L1 is std_1c20:inst|clock_1_in_arbitrator:the_clock_1_in|clock_1_in_read~33 at LC_X47_Y27_N9

--operation mode is normal

N1L1 = !T1_internal_cpu_data_master_waitrequest & S1_internal_d_read & N1_cpu_data_master_requests_clock_1_in;

--K1L1 is std_1c20:inst|clock_0_in_arbitrator:the_clock_0_in|clock_0_in_read~33 at LC_X42_Y27_N2

--operation mode is normal

K1L1 = !T1_internal_cpu_data_master_waitrequest & S1_internal_d_read & (K1_cpu_data_master_requests_clock_0_in);

--KB1L630 is std_1c20:inst|sdram:the_sdram|Mux40~1482 at LC_X12_Y24_N1

--operation mode is normal

KB1L630 = !KB1_m_state[4] & !KB1_m_state[3] & KB1L616;

--KB1L658 is std_1c20:inst|sdram:the_sdram|Mux41~1479 at LC_X12_Y24_N9

--operation mode is normal

KB1L658 = KB1_m_state[0] & !KB1_m_state[3] & KB1L616;

--KB1L659 is std_1c20:inst|sdram:the_sdram|Mux41~1480 at LC_X11_Y24_N1

--operation mode is normal

KB1L659 = KB1_m_count[1] & (!KB1_refresh_request # !KB1L616 # !KB1_init_done);

--H1_cpu_data_master_requests_button_pio_s1 is std_1c20:inst|button_pio_s1_arbitrator:the_button_pio_s1|cpu_data_master_requests_button_pio_s1 at LC_X44_Y23_N1

--operation mode is normal

H1_cpu_data_master_requests_button_pio_s1 = S1L1743Q & S1_M_alu_result[6] & !S1L1738Q & SB1L2;

--UB1_cpu_data_master_granted_sysid_control_slave is std_1c20:inst|sysid_control_slave_arbitrator:the_sysid_control_slave|cpu_data_master_granted_sysid_control_slave at LC_X44_Y25_N1

--operation mode is normal

UB1_cpu_data_master_granted_sysid_control_slave = S1_M_alu_result[3] & S1_internal_d_read & S1L1738Q & UB1L9;

--T1L162 is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[10]~5336 at LC_X44_Y23_N4

--operation mode is normal

T1L162 = T1L150 & (S1L1743Q # !SB1L2 # !S1_M_alu_result[6]);

--T1L99 is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[5]~5337 at LC_X43_Y23_N7

--operation mode is normal

T1L99 = T1L81 & (S1L1726Q # !UB1L10 # !UB1L9);

--CF1L25 is sld_hub:sld_hub_inst|sld_rom_sr:HUB_INFO_REG|word_counter[0]~1282 at LC_X57_Y17_N6

--operation mode is normal

CF1L25 = AMPP_FUNCTION(C1_jtag_debug_mode_usr0, FF1L18, C1_jtag_debug_mode_usr1, FF1_state[8]);

--C1L5 is sld_hub:sld_hub_inst|comb~99 at LC_X58_Y17_N8

--operation mode is normal

C1L5 = AMPP_FUNCTION(A1L7, BF3_Q[6], C1L4, altera_internal_jtag);

--SD1L141 is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|process2~2 at LC_X52_Y14_N4

--operation mode is normal

SD1L141 = AMPP_FUNCTION(SD1L144, A1L4, SD1_in_between_shiftdr_and_updatedr);

--GE1L62 is std_1c20:inst|jtag_uart:the_jtag_uart|alt_jtag_atlantic:jtag_uart_alt_jtag_atlantic|td_shift[9]~3577 at LC_X52_Y19_N1

--operation mode is normal

GE1L62 = AMPP_FUNCTION(GE1_state, GE1_count[1], GE1_user_saw_rvalid, GE1_td_shift[9]);

--HB1L3 is std_1c20:inst|reconfig_request_pio:the_reconfig_request_pio|process2~28 at LC_X36_Y21_N1

--operation mode is normal

HB1L3 = S1_internal_d_write & S1_M_alu_result[5] & !T1_internal_cpu_data_master_waitrequest & JB1L3;

--NB1L82 is std_1c20:inst|sdram_s1_arbitrator:the_sdram_s1|sdram_s1_arb_winner~0 at LC_X23_Y22_N3

--operation mode is normal

NB1L82 = NB1_WideOr1 & (!NB1L19 & !NB1L79 # !NB1_sdram_s1_slavearbiterlockenable);

--NB1L67 is std_1c20:inst|sdram_s1_arbitrator:the_sdram_s1|sdram_s1_arb_counter_enable~45 at LC_X21_Y22_N9

--operation mode is normal

NB1L67 = NB1L66 & (TE1_entries[0] # !KB1L477 # !TE1_entries[1]);

--S1L1234 is std_1c20:inst|cpu:the_cpu|F_ic_tag_rd_addr_nxt[0]~4256 at LC_X27_Y19_N0

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

S1L1234 = AMPP_FUNCTION(S1_D_kill, S1L331, S1L1232);

--S1_D_pc[3] is std_1c20:inst|cpu:the_cpu|D_pc[3] at LC_X27_Y19_N0

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

S1_D_pc[3] = AMPP_FUNCTION(QC2__clk0, S1_F_pc[3], F1_data_out, GND, S1_W_stall);

--S1L1237 is std_1c20:inst|cpu:the_cpu|F_ic_tag_rd_addr_nxt[1]~4257 at LC_X27_Y19_N1

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

S1L1237 = AMPP_FUNCTION(S1_D_kill, S1L331, S1L1235);

--S1_D_pc[4] is std_1c20:inst|cpu:the_cpu|D_pc[4] at LC_X27_Y19_N1

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

S1_D_pc[4] = AMPP_FUNCTION(QC2__clk0, S1_F_pc[4], F1_data_out, GND, S1_W_stall);

--S1L1240 is std_1c20:inst|cpu:the_cpu|F_ic_tag_rd_addr_nxt[2]~4258 at LC_X26_Y18_N8

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

S1L1240 = AMPP_FUNCTION(S1L331, S1_D_kill, S1L1238);

--S1_D_pc[5] is std_1c20:inst|cpu:the_cpu|D_pc[5] at LC_X26_Y18_N8

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

S1_D_pc[5] = AMPP_FUNCTION(QC2__clk0, S1_F_pc[5], F1_data_out, GND, S1_W_stall);

--S1L1243 is std_1c20:inst|cpu:the_cpu|F_ic_tag_rd_addr_nxt[3]~4259 at LC_X26_Y17_N5

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

S1L1243 = AMPP_FUNCTION(S1_D_kill, S1L331, S1L1241);

--S1_D_pc[6] is std_1c20:inst|cpu:the_cpu|D_pc[6] at LC_X26_Y17_N5

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

S1_D_pc[6] = AMPP_FUNCTION(QC2__clk0, S1_F_pc[6], F1_data_out, GND, S1_W_stall);

--S1L1246 is std_1c20:inst|cpu:the_cpu|F_ic_tag_rd_addr_nxt[4]~4260 at LC_X26_Y17_N1

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

S1L1246 = AMPP_FUNCTION(S1_D_kill, S1L331, S1L1244);

--S1_D_pc[7] is std_1c20:inst|cpu:the_cpu|D_pc[7] at LC_X26_Y17_N1

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

S1_D_pc[7] = AMPP_FUNCTION(QC2__clk0, S1_F_pc[7], F1_data_out, GND, S1_W_stall);

--S1L1249 is std_1c20:inst|cpu:the_cpu|F_ic_tag_rd_addr_nxt[5]~4261 at LC_X25_Y20_N4

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

S1L1249 = AMPP_FUNCTION(S1L331, S1_D_kill, S1L1247);

--S1_D_pc[8] is std_1c20:inst|cpu:the_cpu|D_pc[8] at LC_X25_Y20_N4

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

S1_D_pc[8] = AMPP_FUNCTION(QC2__clk0, S1_F_pc[8], F1_data_out, GND, S1_W_stall);

--S1L1252 is std_1c20:inst|cpu:the_cpu|F_ic_tag_rd_addr_nxt[6]~4262 at LC_X26_Y17_N7

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

S1L1252 = AMPP_FUNCTION(S1_D_kill, S1L331, S1L1250);

--S1_D_pc[9] is std_1c20:inst|cpu:the_cpu|D_pc[9] at LC_X26_Y17_N7

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

S1_D_pc[9] = AMPP_FUNCTION(QC2__clk0, S1_F_pc[9], F1_data_out, GND, S1_W_stall);

--S1L1204 is std_1c20:inst|cpu:the_cpu|F_ic_data_rd_addr_nxt[2]~1824 at LC_X23_Y19_N7

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

S1L1204 = AMPP_FUNCTION(S1_D_kill, S1L1202, S1L331);

--S1_D_pc[2] is std_1c20:inst|cpu:the_cpu|D_pc[2] at LC_X23_Y19_N7

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

S1_D_pc[2] = AMPP_FUNCTION(QC2__clk0, S1_F_pc[2], F1_data_out, GND, S1_W_stall);

--S1L1201 is std_1c20:inst|cpu:the_cpu|F_ic_data_rd_addr_nxt[1]~1825 at LC_X23_Y19_N2

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

S1L1201 = AMPP_FUNCTION(S1_D_kill, S1L1199, S1L331);

--S1_D_pc[1] is std_1c20:inst|cpu:the_cpu|D_pc[1] at LC_X23_Y19_N2

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

S1_D_pc[1] = AMPP_FUNCTION(QC2__clk0, S1_F_pc[1], F1_data_out, GND, S1_W_stall);

--S1_D_pc[0] is std_1c20:inst|cpu:the_cpu|D_pc[0] at LC_X25_Y20_N3

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

S1_D_pc[0] = AMPP_FUNCTION(QC2__clk0, S1_F_pc[0], F1_data_out, GND, S1_W_stall);

--XE1L64 is std_1c20:inst|uart1:the_uart1|uart1_regs:the_uart1_regs|tx_wr_strobe~14 at LC_X47_Y22_N9

--operation mode is normal

XE1L64 = !S1_M_alu_result[3] & !S1L1738Q & S1L1726Q & XE1L13;

--S1L2378 is std_1c20:inst|cpu:the_cpu|M_status_reg_pie~161 at LC_X32_Y15_N8

--operation mode is normal

S1L2378 = AMPP_FUNCTION(S1_E_ctrl_exception, S1_E_wrctl_status, S1L825, S1_E_ctrl_break);

--S1L2385Q is std_1c20:inst|cpu:the_cpu|M_status_reg_pie~168 at LC_X32_Y16_N4

--operation mode is normal

S1L2385Q = AMPP_FUNCTION(QC2__clk0, S1_W_stall, S1_E_ctrl_exception, S1_E_ctrl_break, S1L1160, F1_data_out);

--T1L355Q is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|dbs_8_reg_segment_0[7]~753 at LC_X34_Y27_N2

--operation mode is normal

T1L355Q_lut_out = !T1_internal_cpu_data_master_dbs_address[0] & !T1_internal_cpu_data_master_dbs_address[1] & T1L524;

T1L355Q = DFFEAS(T1L355Q_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--DE1L278 is std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|p1_data_to_cpu[2]~877 at LC_X36_Y26_N6

--operation mode is normal

DE1L278 = !X1L33 & (X1L4 & S1_M_alu_result[3] # !X1L4 & (S1_ic_fill_ap_offset[1]));

--DE1L72Q is std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|data_to_cpu[5]~36 at LC_X36_Y26_N6

--operation mode is normal

DE1L72Q = DFFEAS(DE1L278, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--RD1L71 is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|module_input6~27 at LC_X43_Y19_N7

--operation mode is normal

RD1L71 = AMPP_FUNCTION(S1_hbreak_enabled, S1L1756Q, V1L6, S1_internal_d_write);

--Z1_control_wr_strobe is std_1c20:inst|high_res_timer:the_high_res_timer|control_wr_strobe at LC_X47_Y23_N7

--operation mode is normal

Z1_control_wr_strobe = !T1_internal_cpu_data_master_waitrequest & XE1L18 & S1_internal_d_write & AB1_cpu_data_master_requests_high_res_timer_s1;

--S1L2470 is std_1c20:inst|cpu:the_cpu|M_wr_data_unfiltered[26]~3735 at LC_X44_Y13_N9

--operation mode is normal

S1L2470 = AMPP_FUNCTION(S1L214Q, S1L2062Q, S1_M_shift_rot_result[26]);

--S1_W_wr_data[26] is std_1c20:inst|cpu:the_cpu|W_wr_data[26] at LC_X44_Y13_N9

--operation mode is normal

S1_W_wr_data[26] = AMPP_FUNCTION(QC2__clk0, S1L214Q, S1L2062Q, S1_M_shift_rot_result[26], F1_data_out, S1_W_stall);

--T1L508 is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|p1_registered_cpu_data_master_readdata~58 at LC_X45_Y24_N0

--operation mode is normal

T1L508 = BB1_ien_AE & BB1_fifo_AE # !UB1L9 # !CB1L2;

--T1L47 is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[1]~5338 at LC_X47_Y24_N8

--operation mode is normal

T1L47 = JB1L3 & (S1L1743Q # !A1L140);

--S1L2038Q is std_1c20:inst|cpu:the_cpu|M_bstatus_reg~7 at LC_X34_Y18_N9

--operation mode is normal

S1L2038Q = AMPP_FUNCTION(QC2__clk0, S1L2514, S1L1160, S1_internal_d_write, T1_internal_cpu_data_master_waitrequest, F1_data_out);

--RB1_control_wr_strobe is std_1c20:inst|sys_clk_timer:the_sys_clk_timer|control_wr_strobe at LC_X47_Y25_N8

--operation mode is normal

RB1_control_wr_strobe = RB1L9 & !S1_M_alu_result[6] & !S1L1743Q & SB1L2;

--YE1L40 is std_1c20:inst|uart1:the_uart1|uart1_rx:the_uart1_rx|break_detect~48 at LC_X52_Y22_N5

--operation mode is normal

YE1L40 = YE1_break_detect # !YE1L81 & !YE1_unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[0] & YE1_delayed_unxrx_in_processxx3;

--RB1_period_h_wr_strobe is std_1c20:inst|sys_clk_timer:the_sys_clk_timer|period_h_wr_strobe at LC_X47_Y25_N2

--operation mode is normal

RB1_period_h_wr_strobe = S1_internal_d_write & SB1_cpu_data_master_requests_sys_clk_timer_s1 & XE1L15 & !T1_internal_cpu_data_master_waitrequest;

--RB1_period_l_wr_strobe is std_1c20:inst|sys_clk_timer:the_sys_clk_timer|period_l_wr_strobe at LC_X51_Y27_N8

--operation mode is normal

RB1_period_l_wr_strobe = !T1_internal_cpu_data_master_waitrequest & S1_internal_d_write & SB1_cpu_data_master_requests_sys_clk_timer_s1 & XE1L20;

--Z1_period_h_wr_strobe is std_1c20:inst|high_res_timer:the_high_res_timer|period_h_wr_strobe at LC_X54_Y25_N1

--operation mode is normal

Z1_period_h_wr_strobe = !T1_internal_cpu_data_master_waitrequest & S1_internal_d_write & AB1_cpu_data_master_requests_high_res_timer_s1 & XE1L15;

--Z1_period_l_wr_strobe is std_1c20:inst|high_res_timer:the_high_res_timer|period_l_wr_strobe at LC_X54_Y25_N4

--operation mode is normal

Z1_period_l_wr_strobe = !T1_internal_cpu_data_master_waitrequest & S1_internal_d_write & AB1_cpu_data_master_requests_high_res_timer_s1 & XE1L20;

--NE2L1 is std_1c20:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_r:the_jtag_uart_scfifo_r|scfifo:rfifo|scfifo_jf21:auto_generated|a_dpfifo_ml21:dpfifo|a_fefifo_7cf:fifo_state|_~28 at LC_X45_Y21_N5

--operation mode is normal

NE2L1 = NE2_b_non_empty & (BB1L58 $ (!NE2_b_full & GE1L37Q)) # !NE2_b_non_empty & !NE2_b_full & GE1L37Q;

--S1L2495 is std_1c20:inst|cpu:the_cpu|M_wr_data_unfiltered[31]~3736 at LC_X39_Y13_N4

--operation mode is normal

S1L2495 = AMPP_FUNCTION(S1L2056Q, S1L229Q, S1_M_shift_rot_result[31]);

--S1_W_wr_data[31] is std_1c20:inst|cpu:the_cpu|W_wr_data[31] at LC_X39_Y13_N4

--operation mode is normal

S1_W_wr_data[31] = AMPP_FUNCTION(QC2__clk0, S1L2056Q, S1L229Q, S1_M_shift_rot_result[31], F1_data_out, S1_W_stall);

--S1L278 is std_1c20:inst|cpu:the_cpu|D_ctrl_alu_signed_cmp~296 at LC_X30_Y13_N6

--operation mode is normal

S1L278 = AMPP_FUNCTION(S1_D_iw[11], S1_D_iw[5], S1_D_iw[4], S1L279);

--SD1L70 is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|DRsize[0]~20068 at LC_X52_Y14_N8

--operation mode is normal

SD1L70 = AMPP_FUNCTION(SD1_ir[0], SD1L144, A1L4, SD1_in_between_shiftdr_and_updatedr);

--S1L2473 is std_1c20:inst|cpu:the_cpu|M_wr_data_unfiltered[27]~3737 at LC_X43_Y13_N9

--operation mode is normal

S1L2473 = AMPP_FUNCTION(S1_M_shift_rot_result[27], S1L2062Q, S1L217Q);

--S1_W_wr_data[27] is std_1c20:inst|cpu:the_cpu|W_wr_data[27] at LC_X43_Y13_N9

--operation mode is normal

S1_W_wr_data[27] = AMPP_FUNCTION(QC2__clk0, S1_M_shift_rot_result[27], S1L2062Q, S1L217Q, F1_data_out, S1_W_stall);

--DE1L285 is std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|p1_wr_strobe~42 at LC_X35_Y27_N4

--operation mode is normal

DE1_wr_strobe_qfbk = DE1_wr_strobe;

DE1L285 = S1_internal_d_write & X1L4 & !DE1_wr_strobe_qfbk & W1L1;

--DE1_wr_strobe is std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|wr_strobe at LC_X35_Y27_N4

--operation mode is normal

DE1_wr_strobe = DFFEAS(DE1L285, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--S1L2482 is std_1c20:inst|cpu:the_cpu|M_wr_data_unfiltered[30]~3738 at LC_X43_Y15_N5

--operation mode is normal

S1L2482 = AMPP_FUNCTION(S1L2062Q, S1L226Q, S1_M_shift_rot_result[30]);

--S1_W_wr_data[30] is std_1c20:inst|cpu:the_cpu|W_wr_data[30] at LC_X43_Y15_N5

--operation mode is normal

S1_W_wr_data[30] = AMPP_FUNCTION(QC2__clk0, S1L2062Q, S1L226Q, S1_M_shift_rot_result[30], F1_data_out, S1_W_stall);

--S1L2479 is std_1c20:inst|cpu:the_cpu|M_wr_data_unfiltered[29]~3739 at LC_X44_Y14_N1

--operation mode is normal

S1L2479 = AMPP_FUNCTION(S1L223Q, S1_M_shift_rot_result[29], S1L2062Q);

--S1_W_wr_data[29] is std_1c20:inst|cpu:the_cpu|W_wr_data[29] at LC_X44_Y14_N1

--operation mode is normal

S1_W_wr_data[29] = AMPP_FUNCTION(QC2__clk0, S1L223Q, S1_M_shift_rot_result[29], S1L2062Q, F1_data_out, S1_W_stall);

--S1L2476 is std_1c20:inst|cpu:the_cpu|M_wr_data_unfiltered[28]~3740 at LC_X43_Y13_N1

--operation mode is normal

S1L2476 = AMPP_FUNCTION(S1L2062Q, S1L220Q, S1_M_shift_rot_result[28]);

--S1_W_wr_data[28] is std_1c20:inst|cpu:the_cpu|W_wr_data[28] at LC_X43_Y13_N1

--operation mode is normal

S1_W_wr_data[28] = AMPP_FUNCTION(QC2__clk0, S1L2062Q, S1L220Q, S1_M_shift_rot_result[28], F1_data_out, S1_W_stall);

--DE1L315 is std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|shift_reg~616 at LC_X40_Y28_N2

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

DE1_tx_holding_reg[2]_qfbk = DE1_tx_holding_reg[2];

DE1L315 = DE1_tx_holding_primed & (DE1_transmitting & DE1_shift_reg[2] # !DE1_transmitting & (DE1_tx_holding_reg[2]_qfbk)) # !DE1_tx_holding_primed & DE1_shift_reg[2];

--DE1_tx_holding_reg[2] is std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|tx_holding_reg[2] at LC_X40_Y28_N2

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

DE1_tx_holding_reg[2] = DFFEAS(DE1L315, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , DE1_write_tx_holding, S1_M_st_data[2], , , VCC);

--DE1L316 is std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|shift_reg~617 at LC_X40_Y28_N8

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

DE1_tx_holding_reg[3]_qfbk = DE1_tx_holding_reg[3];

DE1L316 = DE1_tx_holding_primed & (DE1_transmitting & (DE1_shift_reg[3]) # !DE1_transmitting & DE1_tx_holding_reg[3]_qfbk) # !DE1_tx_holding_primed & (DE1_shift_reg[3]);

--DE1_tx_holding_reg[3] is std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|tx_holding_reg[3] at LC_X40_Y28_N8

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

DE1_tx_holding_reg[3] = DFFEAS(DE1L316, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , DE1_write_tx_holding, S1_M_st_data[3], , , VCC);

--DE1L317 is std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|shift_reg~618 at LC_X40_Y28_N6

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

DE1_tx_holding_reg[7]_qfbk = DE1_tx_holding_reg[7];

DE1L317 = DE1_tx_holding_primed & (DE1_transmitting & (DE1_shift_reg[7]) # !DE1_transmitting & DE1_tx_holding_reg[7]_qfbk) # !DE1_tx_holding_primed & (DE1_shift_reg[7]);

--DE1_tx_holding_reg[7] is std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|tx_holding_reg[7] at LC_X40_Y28_N6

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

DE1_tx_holding_reg[7] = DFFEAS(DE1L317, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , DE1_write_tx_holding, S1_M_st_data[7], , , VCC);

--DE1L318 is std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|shift_reg~619 at LC_X40_Y28_N1

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

DE1_tx_holding_reg[6]_qfbk = DE1_tx_holding_reg[6];

DE1L318 = DE1_tx_holding_primed & (DE1_transmitting & (DE1_shift_reg[6]) # !DE1_transmitting & DE1_tx_holding_reg[6]_qfbk) # !DE1_tx_holding_primed & (DE1_shift_reg[6]);

--DE1_tx_holding_reg[6] is std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|tx_holding_reg[6] at LC_X40_Y28_N1

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

DE1_tx_holding_reg[6] = DFFEAS(DE1L318, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , DE1_write_tx_holding, S1_M_st_data[6], , , VCC);

--DE1L319 is std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|shift_reg~620 at LC_X40_Y28_N7

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

DE1_tx_holding_reg[4]_qfbk = DE1_tx_holding_reg[4];

DE1L319 = DE1_tx_holding_primed & (DE1_transmitting & (DE1_shift_reg[4]) # !DE1_transmitting & DE1_tx_holding_reg[4]_qfbk) # !DE1_tx_holding_primed & (DE1_shift_reg[4]);

--DE1_tx_holding_reg[4] is std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|tx_holding_reg[4] at LC_X40_Y28_N7

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

DE1_tx_holding_reg[4] = DFFEAS(DE1L319, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , DE1_write_tx_holding, S1_M_st_data[4], , , VCC);

--DE1L320 is std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|shift_reg~621 at LC_X40_Y28_N4

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

DE1_tx_holding_reg[5]_qfbk = DE1_tx_holding_reg[5];

DE1L320 = DE1_tx_holding_primed & (DE1_transmitting & (DE1_shift_reg[5]) # !DE1_transmitting & DE1_tx_holding_reg[5]_qfbk) # !DE1_tx_holding_primed & (DE1_shift_reg[5]);

--DE1_tx_holding_reg[5] is std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|tx_holding_reg[5] at LC_X40_Y28_N4

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

DE1_tx_holding_reg[5] = DFFEAS(DE1L320, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , DE1_write_tx_holding, S1_M_st_data[5], , , VCC);

--DE1L321 is std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|shift_reg~622 at LC_X40_Y28_N3

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

DE1_tx_holding_reg[1]_qfbk = DE1_tx_holding_reg[1];

DE1L321 = DE1_tx_holding_primed & (DE1_transmitting & (DE1_shift_reg[1]) # !DE1_transmitting & DE1_tx_holding_reg[1]_qfbk) # !DE1_tx_holding_primed & (DE1_shift_reg[1]);

--DE1_tx_holding_reg[1] is std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|tx_holding_reg[1] at LC_X40_Y28_N3

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

DE1_tx_holding_reg[1] = DFFEAS(DE1L321, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , DE1_write_tx_holding, S1_M_st_data[1], , , VCC);

--DE1L305 is std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|SCLK_reg~291 at LC_X41_Y28_N8

--operation mode is normal

DE1L305 = DE1_state[4] & (DE1_transmitting # DE1_state[0] & DE1L261) # !DE1_state[4] & DE1_transmitting & (DE1_state[0] # !DE1L261);

--SD1L71 is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|DRsize[0]~20069 at LC_X51_Y14_N8

--operation mode is normal

SD1L71 = AMPP_FUNCTION(SD1L134, SD1L55, SD1L143, SD1L135);

--DE1L322 is std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|shift_reg~623 at LC_X40_Y28_N5

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

DE1_tx_holding_reg[0]_qfbk = DE1_tx_holding_reg[0];

DE1L322 = DE1_tx_holding_primed & (DE1_transmitting & DE1_shift_reg[0] # !DE1_transmitting & (DE1_tx_holding_reg[0]_qfbk)) # !DE1_tx_holding_primed & DE1_shift_reg[0];

--DE1_tx_holding_reg[0] is std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|tx_holding_reg[0] at LC_X40_Y28_N5

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

DE1_tx_holding_reg[0] = DFFEAS(DE1L322, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , DE1_write_tx_holding, S1_M_st_data[0], , , VCC);

--S1L293 is std_1c20:inst|cpu:the_cpu|D_ctrl_flush_pipe_always~577 at LC_X28_Y14_N0

--operation mode is normal

S1L293 = AMPP_FUNCTION(S1_D_iw[0], S1_D_iw[2], S1_D_iw[5]);

--S1L299 is std_1c20:inst|cpu:the_cpu|D_ctrl_flush_pipe_always~588 at LC_X28_Y14_N1

--operation mode is normal

S1L299 = AMPP_FUNCTION(S1_D_iw[1], S1_D_iw[3], S1_D_iw[4], S1L293);

--GE1L63 is std_1c20:inst|jtag_uart:the_jtag_uart|alt_jtag_atlantic:jtag_uart_alt_jtag_atlantic|td_shift[9]~3578 at LC_X53_Y19_N5

--operation mode is normal

GE1L63 = AMPP_FUNCTION(FF1_state[4], GE1L51, GE1_state, BF4_Q[0]);

--GE1L51 is std_1c20:inst|jtag_uart:the_jtag_uart|alt_jtag_atlantic:jtag_uart_alt_jtag_atlantic|td_shift[9]~3539 at LC_X52_Y19_N4

--operation mode is normal

GE1L51 = AMPP_FUNCTION(GE1_count[1], GE1_user_saw_rvalid, GE1_td_shift[9]);

--S1L670 is std_1c20:inst|cpu:the_cpu|D_wr_dst_reg~94 at LC_X28_Y14_N6

--operation mode is normal

S1L670 = AMPP_FUNCTION(S1_D_iw[2], S1_D_iw[1], S1_D_iw[0]);

--S1L671 is std_1c20:inst|cpu:the_cpu|D_wr_dst_reg~95 at LC_X28_Y14_N7

--operation mode is normal

S1L671 = AMPP_FUNCTION(S1_D_iw[2], S1_D_iw[1], S1_D_iw[0]);

--S1L288 is std_1c20:inst|cpu:the_cpu|D_ctrl_br~23 at LC_X27_Y15_N0

--operation mode is normal

S1L288 = AMPP_FUNCTION(S1_D_iw[0], S1_D_iw[1], S1_D_iw[2]);

--S1L669 is std_1c20:inst|cpu:the_cpu|D_wr_dst_reg~91 at LC_X30_Y14_N5

--operation mode is normal

S1L669 = AMPP_FUNCTION(S1_D_iw[0], S1_D_iw[1], S1_D_iw[2]);

--S1L672 is std_1c20:inst|cpu:the_cpu|D_wr_dst_reg~96 at LC_X30_Y14_N1

--operation mode is normal

S1L672 = AMPP_FUNCTION(S1_M_pipe_flush, S1L669, S1L343);

--KB1L670 is std_1c20:inst|sdram:the_sdram|Mux42~1491 at LC_X13_Y23_N6

--operation mode is normal

KB1L670 = KB1_m_state[4] & (KB1_m_count[0] # !KB1_m_state[3] & KB1L664) # !KB1_m_state[4] & (!KB1L664 & KB1_m_count[0] # !KB1_m_state[3]);

--KB1L671 is std_1c20:inst|sdram:the_sdram|Mux42~1492 at LC_X13_Y23_N9

--operation mode is normal

KB1L671 = KB1L670 & (KB1_m_state[4] # KB1_m_state[3] # KB1L668);

--A1L277 is ~GND at LC_X29_Y20_N5

--operation mode is normal

A1L277 = GND;

--PLD_CLKFB is PLD_CLKFB at PIN_L14

--operation mode is input

PLD_CLKFB = INPUT();

--PLD_CLOCKINPUT[1] is PLD_CLOCKINPUT[1] at PIN_K5

--operation mode is input

PLD_CLOCKINPUT[1] = INPUT();

--PLD_CLEAR_N is PLD_CLEAR_N at PIN_C4

--operation mode is input

PLD_CLEAR_N = INPUT();

--in_port_to_the_button_pio[2] is in_port_to_the_button_pio[2] at PIN_V4

--operation mode is input

in_port_to_the_button_pio[2] = INPUT();

--in_port_to_the_button_pio[3] is in_port_to_the_button_pio[3] at PIN_W4

--operation mode is input

in_port_to_the_button_pio[3] = INPUT();

--irq_from_the_lan91c111 is irq_from_the_lan91c111 at PIN_D15

--operation mode is input

irq_from_the_lan91c111 = INPUT();

--in_port_to_the_button_pio[1] is in_port_to_the_button_pio[1] at PIN_Y4

--operation mode is input

in_port_to_the_button_pio[1] = INPUT();

--in_port_to_the_button_pio[0] is in_port_to_the_button_pio[0] at PIN_W3

--operation mode is input

in_port_to_the_button_pio[0] = INPUT();

--rxd_to_the_uart1 is rxd_to_the_uart1 at PIN_K16

--operation mode is input

rxd_to_the_uart1 = INPUT();

--SDRAM_CLK is SDRAM_CLK at PIN_L13

--operation mode is output

SDRAM_CLK = OUTPUT(QC2__extclk0);

--PLD_CLKOUT is PLD_CLKOUT at PIN_L8

--operation mode is output

PLD_CLKOUT = OUTPUT(QC1__extclk0);

--ENET_ADS_N is ENET_ADS_N at PIN_A14

--operation mode is output

ENET_ADS_N = OUTPUT(GND);

--ENET_AEN is ENET_AEN at PIN_B15

--operation mode is output

ENET_AEN = OUTPUT(GND);

--ior_n_to_the_lan91c111 is ior_n_to_the_lan91c111 at PIN_A15

--operation mode is output --output register power-up is high

ior_n_to_the_lan91c111 = OUTPUT(Y1_ior_n_to_the_lan91c111);

--Y1_ior_n_to_the_lan91c111 is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ior_n_to_the_lan91c111 at PIN_A15

--operation mode is output --output register power-up is high

Y1_ior_n_to_the_lan91c111 = DFFE(!Y1L862, GLOBAL(QC2__clk0), , GLOBAL(F1_data_out), );

--write_n_to_the_ext_flash is write_n_to_the_ext_flash at PIN_D12

--operation mode is output --output register power-up is high

write_n_to_the_ext_flash = OUTPUT(Y1_write_n_to_the_ext_flash);

--Y1_write_n_to_the_ext_flash is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|write_n_to_the_ext_flash at PIN_D12

--operation mode is output --output register power-up is high

Y1_write_n_to_the_ext_flash = DFFE(!Y1L1033, GLOBAL(QC2__clk0), , GLOBAL(F1_data_out), );

--iow_n_to_the_lan91c111 is iow_n_to_the_lan91c111 at PIN_E15

--operation mode is output --output register power-up is high

iow_n_to_the_lan91c111 = OUTPUT(Y1_iow_n_to_the_lan91c111);

--Y1_iow_n_to_the_lan91c111 is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|iow_n_to_the_lan91c111 at PIN_E15

--operation mode is output --output register power-up is high

Y1_iow_n_to_the_lan91c111 = DFFE(!Y1L867, GLOBAL(QC2__clk0), , GLOBAL(F1_data_out), );

--read_n_to_the_ext_flash is read_n_to_the_ext_flash at PIN_B12

--operation mode is output --output register power-up is high

read_n_to_the_ext_flash = OUTPUT(Y1_read_n_to_the_ext_flash);

--Y1_read_n_to_the_ext_flash is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|read_n_to_the_ext_flash at PIN_B12

--operation mode is output --output register power-up is high

Y1_read_n_to_the_ext_flash = DFFE(!Y1L1017, GLOBAL(QC2__clk0), , GLOBAL(F1_data_out), );

--read_n_to_the_ext_ram is read_n_to_the_ext_ram at PIN_Y17

--operation mode is output --output register power-up is high

read_n_to_the_ext_ram = OUTPUT(Y1_read_n_to_the_ext_ram);

--Y1_read_n_to_the_ext_ram is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|read_n_to_the_ext_ram at PIN_Y17

--operation mode is output --output register power-up is high

Y1_read_n_to_the_ext_ram = DFFE(!Y1L1022, GLOBAL(QC2__clk0), , GLOBAL(F1_data_out), );

--select_n_to_the_ext_flash is select_n_to_the_ext_flash at PIN_A12

--operation mode is output --output register power-up is high

select_n_to_the_ext_flash = OUTPUT(Y1_select_n_to_the_ext_flash);

--Y1_select_n_to_the_ext_flash is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|select_n_to_the_ext_flash at PIN_A12

--operation mode is output --output register power-up is high

Y1_select_n_to_the_ext_flash = DFFE(Y1L998, GLOBAL(QC2__clk0), , GLOBAL(F1_data_out), );

--select_n_to_the_ext_ram is select_n_to_the_ext_ram at PIN_W17

--operation mode is output --output register power-up is high

select_n_to_the_ext_ram = OUTPUT(Y1_select_n_to_the_ext_ram);

--Y1_select_n_to_the_ext_ram is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|select_n_to_the_ext_ram at PIN_W17

--operation mode is output --output register power-up is high

Y1_select_n_to_the_ext_ram = DFFE(!Y1L1026, GLOBAL(QC2__clk0), , GLOBAL(F1_data_out), );

--write_n_to_the_ext_ram is write_n_to_the_ext_ram at PIN_U16

--operation mode is output

write_n_to_the_ext_ram = OUTPUT(!Y1L1040);

--zs_cas_n_from_the_sdram is zs_cas_n_from_the_sdram at PIN_G3

--operation mode is output --output register power-up is high

zs_cas_n_from_the_sdram = OUTPUT(KB1_m_cmd[1]);

--KB1_m_cmd[1] is std_1c20:inst|sdram:the_sdram|m_cmd[1] at PIN_G3

--operation mode is output --output register power-up is high

KB1_m_cmd[1] = DFFE(!KB1L237, GLOBAL(QC2__clk0), , GLOBAL(F1_data_out), );

--zs_cke_from_the_sdram is zs_cke_from_the_sdram at PIN_G7

--operation mode is output

zs_cke_from_the_sdram = OUTPUT(VCC);

--zs_cs_n_from_the_sdram is zs_cs_n_from_the_sdram at PIN_G6

--operation mode is output --output register power-up is high

zs_cs_n_from_the_sdram = OUTPUT(KB1_m_cmd[3]);

--KB1_m_cmd[3] is std_1c20:inst|sdram:the_sdram|m_cmd[3] at PIN_G6

--operation mode is output --output register power-up is high

KB1_m_cmd[3] = DFFE(!KB1L245, GLOBAL(QC2__clk0), , GLOBAL(F1_data_out), );

--zs_ras_n_from_the_sdram is zs_ras_n_from_the_sdram at PIN_H2

--operation mode is output --output register power-up is high

zs_ras_n_from_the_sdram = OUTPUT(KB1_m_cmd[2]);

--KB1_m_cmd[2] is std_1c20:inst|sdram:the_sdram|m_cmd[2] at PIN_H2

--operation mode is output --output register power-up is high

KB1_m_cmd[2] = DFFE(!KB1L241, GLOBAL(QC2__clk0), , GLOBAL(F1_data_out), );

--zs_we_n_from_the_sdram is zs_we_n_from_the_sdram at PIN_G4

--operation mode is output --output register power-up is high

zs_we_n_from_the_sdram = OUTPUT(KB1_m_cmd[0]);

--KB1_m_cmd[0] is std_1c20:inst|sdram:the_sdram|m_cmd[0] at PIN_G4

--operation mode is output --output register power-up is high

KB1_m_cmd[0] = DFFE(!KB1L232, GLOBAL(QC2__clk0), , GLOBAL(F1_data_out), );

--txd_from_the_uart1 is txd_from_the_uart1 at PIN_M14

--operation mode is output

txd_from_the_uart1 = OUTPUT(!ZE1_txd);

--LCD_RW_from_the_lcd_display is LCD_RW_from_the_lcd_display at PIN_J19

--operation mode is output

LCD_RW_from_the_lcd_display = OUTPUT(S1L1726Q);

--LCD_RS_from_the_lcd_display is LCD_RS_from_the_lcd_display at PIN_J15

--operation mode is output

LCD_RS_from_the_lcd_display = OUTPUT(S1_M_alu_result[3]);

--LCD_E_from_the_lcd_display is LCD_E_from_the_lcd_display at PIN_J20

--operation mode is output

LCD_E_from_the_lcd_display = OUTPUT(DB1L4);

--be_n_to_the_ext_ram[3] is be_n_to_the_ext_ram[3] at PIN_T16

--operation mode is output --output register power-up is high

be_n_to_the_ext_ram[3] = OUTPUT(Y1_be_n_to_the_ext_ram[3]);

--Y1_be_n_to_the_ext_ram[3] is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|be_n_to_the_ext_ram[3] at PIN_T16

--operation mode is output --output register power-up is high

Y1_be_n_to_the_ext_ram[3] = DFFE(!Y1L69, GLOBAL(QC2__clk0), , GLOBAL(F1_data_out), );

--be_n_to_the_ext_ram[2] is be_n_to_the_ext_ram[2] at PIN_W16

--operation mode is output --output register power-up is high

be_n_to_the_ext_ram[2] = OUTPUT(Y1_be_n_to_the_ext_ram[2]);

--Y1_be_n_to_the_ext_ram[2] is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|be_n_to_the_ext_ram[2] at PIN_W16

--operation mode is output --output register power-up is high

Y1_be_n_to_the_ext_ram[2] = DFFE(!Y1L66, GLOBAL(QC2__clk0), , GLOBAL(F1_data_out), );

--be_n_to_the_ext_ram[1] is be_n_to_the_ext_ram[1] at PIN_V16

--operation mode is output --output register power-up is high

be_n_to_the_ext_ram[1] = OUTPUT(Y1_be_n_to_the_ext_ram[1]);

--Y1_be_n_to_the_ext_ram[1] is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|be_n_to_the_ext_ram[1] at PIN_V16

--operation mode is output --output register power-up is high

Y1_be_n_to_the_ext_ram[1] = DFFE(!Y1L63, GLOBAL(QC2__clk0), , GLOBAL(F1_data_out), );

--be_n_to_the_ext_ram[0] is be_n_to_the_ext_ram[0] at PIN_V17

--operation mode is output --output register power-up is high

be_n_to_the_ext_ram[0] = OUTPUT(Y1_be_n_to_the_ext_ram[0]);

--Y1_be_n_to_the_ext_ram[0] is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|be_n_to_the_ext_ram[0] at PIN_V17

--operation mode is output --output register power-up is high

Y1_be_n_to_the_ext_ram[0] = DFFE(!Y1L60, GLOBAL(QC2__clk0), , GLOBAL(F1_data_out), );

--byteenablen_to_the_lan91c111[3] is byteenablen_to_the_lan91c111[3] at PIN_E16

--operation mode is output --output register power-up is high

byteenablen_to_the_lan91c111[3] = OUTPUT(Y1_byteenablen_to_the_lan91c111[3]);

--Y1_byteenablen_to_the_lan91c111[3] is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|byteenablen_to_the_lan91c111[3] at PIN_E16

--operation mode is output --output register power-up is high

Y1_byteenablen_to_the_lan91c111[3] = DFFE(!Y1L82, GLOBAL(QC2__clk0), , GLOBAL(F1_data_out), );

--byteenablen_to_the_lan91c111[2] is byteenablen_to_the_lan91c111[2] at PIN_D16

--operation mode is output --output register power-up is high

byteenablen_to_the_lan91c111[2] = OUTPUT(Y1_byteenablen_to_the_lan91c111[2]);

--Y1_byteenablen_to_the_lan91c111[2] is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|byteenablen_to_the_lan91c111[2] at PIN_D16

--operation mode is output --output register power-up is high

Y1_byteenablen_to_the_lan91c111[2] = DFFE(!Y1L79, GLOBAL(QC2__clk0), , GLOBAL(F1_data_out), );

--byteenablen_to_the_lan91c111[1] is byteenablen_to_the_lan91c111[1] at PIN_B16

--operation mode is output --output register power-up is high

byteenablen_to_the_lan91c111[1] = OUTPUT(Y1_byteenablen_to_the_lan91c111[1]);

--Y1_byteenablen_to_the_lan91c111[1] is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|byteenablen_to_the_lan91c111[1] at PIN_B16

--operation mode is output --output register power-up is high

Y1_byteenablen_to_the_lan91c111[1] = DFFE(!Y1L76, GLOBAL(QC2__clk0), , GLOBAL(F1_data_out), );

--byteenablen_to_the_lan91c111[0] is byteenablen_to_the_lan91c111[0] at PIN_C16

--operation mode is output --output register power-up is high

byteenablen_to_the_lan91c111[0] = OUTPUT(Y1_byteenablen_to_the_lan91c111[0]);

--Y1_byteenablen_to_the_lan91c111[0] is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|byteenablen_to_the_lan91c111[0] at PIN_C16

--operation mode is output --output register power-up is high

Y1_byteenablen_to_the_lan91c111[0] = DFFE(!Y1L73, GLOBAL(QC2__clk0), , GLOBAL(F1_data_out), );

--ext_ram_bus_address[22] is ext_ram_bus_address[22] at PIN_G2

--operation mode is output --output register power-up is low

ext_ram_bus_address[22] = OUTPUT(Y1_ext_ram_bus_address[22]);

--Y1_ext_ram_bus_address[22] is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_address[22] at PIN_G2

--operation mode is output --output register power-up is low

Y1_ext_ram_bus_address[22] = DFFE(Y1L498, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , );

--ext_ram_bus_address[21] is ext_ram_bus_address[21] at PIN_G1

--operation mode is output --output register power-up is low

ext_ram_bus_address[21] = OUTPUT(Y1_ext_ram_bus_address[21]);

--Y1_ext_ram_bus_address[21] is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_address[21] at PIN_G1

--operation mode is output --output register power-up is low

Y1_ext_ram_bus_address[21] = DFFE(Y1L489, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , );

--ext_ram_bus_address[20] is ext_ram_bus_address[20] at PIN_G5

--operation mode is output --output register power-up is low

ext_ram_bus_address[20] = OUTPUT(Y1_ext_ram_bus_address[20]);

--Y1_ext_ram_bus_address[20] is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_address[20] at PIN_G5

--operation mode is output --output register power-up is low

Y1_ext_ram_bus_address[20] = DFFE(Y1L480, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , );

--ext_ram_bus_address[19] is ext_ram_bus_address[19] at PIN_F6

--operation mode is output --output register power-up is low

ext_ram_bus_address[19] = OUTPUT(Y1_ext_ram_bus_address[19]);

--Y1_ext_ram_bus_address[19] is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_address[19] at PIN_F6

--operation mode is output --output register power-up is low

Y1_ext_ram_bus_address[19] = DFFE(S1L1606, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , );

--ext_ram_bus_address[18] is ext_ram_bus_address[18] at PIN_F1

--operation mode is output --output register power-up is low

ext_ram_bus_address[18] = OUTPUT(Y1_ext_ram_bus_address[18]);

--Y1_ext_ram_bus_address[18] is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_address[18] at PIN_F1

--operation mode is output --output register power-up is low

Y1_ext_ram_bus_address[18] = DFFE(S1L1603, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , );

--ext_ram_bus_address[17] is ext_ram_bus_address[17] at PIN_F2

--operation mode is output --output register power-up is low

ext_ram_bus_address[17] = OUTPUT(Y1_ext_ram_bus_address[17]);

--Y1_ext_ram_bus_address[17] is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_address[17] at PIN_F2

--operation mode is output --output register power-up is low

Y1_ext_ram_bus_address[17] = DFFE(Y1L471, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , );

--ext_ram_bus_address[16] is ext_ram_bus_address[16] at PIN_F5

--operation mode is output --output register power-up is low

ext_ram_bus_address[16] = OUTPUT(Y1_ext_ram_bus_address[16]);

--Y1_ext_ram_bus_address[16] is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_address[16] at PIN_F5

--operation mode is output --output register power-up is low

Y1_ext_ram_bus_address[16] = DFFE(Y1L458, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , );

--ext_ram_bus_address[15] is ext_ram_bus_address[15] at PIN_F4

--operation mode is output --output register power-up is low

ext_ram_bus_address[15] = OUTPUT(Y1_ext_ram_bus_address[15]);

--Y1_ext_ram_bus_address[15] is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_address[15] at PIN_F4

--operation mode is output --output register power-up is low

Y1_ext_ram_bus_address[15] = DFFE(Y1L455, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , );

--ext_ram_bus_address[14] is ext_ram_bus_address[14] at PIN_E2

--operation mode is output --output register power-up is low

ext_ram_bus_address[14] = OUTPUT(Y1_ext_ram_bus_address[14]);

--Y1_ext_ram_bus_address[14] is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_address[14] at PIN_E2

--operation mode is output --output register power-up is low

Y1_ext_ram_bus_address[14] = DFFE(Y1L452, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , );

--ext_ram_bus_address[13] is ext_ram_bus_address[13] at PIN_E3

--operation mode is output --output register power-up is low

ext_ram_bus_address[13] = OUTPUT(Y1_ext_ram_bus_address[13]);

--Y1_ext_ram_bus_address[13] is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_address[13] at PIN_E3

--operation mode is output --output register power-up is low

Y1_ext_ram_bus_address[13] = DFFE(Y1L449, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , );

--ext_ram_bus_address[12] is ext_ram_bus_address[12] at PIN_F3

--operation mode is output --output register power-up is low

ext_ram_bus_address[12] = OUTPUT(Y1_ext_ram_bus_address[12]);

--Y1_ext_ram_bus_address[12] is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_address[12] at PIN_F3

--operation mode is output --output register power-up is low

Y1_ext_ram_bus_address[12] = DFFE(Y1L445, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , );

--ext_ram_bus_address[11] is ext_ram_bus_address[11] at PIN_E5

--operation mode is output --output register power-up is low

ext_ram_bus_address[11] = OUTPUT(Y1_ext_ram_bus_address[11]);

--Y1_ext_ram_bus_address[11] is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_address[11] at PIN_E5

--operation mode is output --output register power-up is low

Y1_ext_ram_bus_address[11] = DFFE(S1L1556, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , );

--ext_ram_bus_address[10] is ext_ram_bus_address[10] at PIN_E4

--operation mode is output --output register power-up is low

ext_ram_bus_address[10] = OUTPUT(Y1_ext_ram_bus_address[10]);

--Y1_ext_ram_bus_address[10] is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_address[10] at PIN_E4

--operation mode is output --output register power-up is low

Y1_ext_ram_bus_address[10] = DFFE(Y1L440, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , );

--ext_ram_bus_address[9] is ext_ram_bus_address[9] at PIN_D1

--operation mode is output --output register power-up is low

ext_ram_bus_address[9] = OUTPUT(Y1_ext_ram_bus_address[9]);

--Y1_ext_ram_bus_address[9] is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_address[9] at PIN_D1

--operation mode is output --output register power-up is low

Y1_ext_ram_bus_address[9] = DFFE(Y1L437, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , );

--ext_ram_bus_address[8] is ext_ram_bus_address[8] at PIN_D4

--operation mode is output --output register power-up is low

ext_ram_bus_address[8] = OUTPUT(Y1_ext_ram_bus_address[8]);

--Y1_ext_ram_bus_address[8] is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_address[8] at PIN_D4

--operation mode is output --output register power-up is low

Y1_ext_ram_bus_address[8] = DFFE(Y1L433, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , );

--ext_ram_bus_address[7] is ext_ram_bus_address[7] at PIN_D2

--operation mode is output --output register power-up is low

ext_ram_bus_address[7] = OUTPUT(Y1_ext_ram_bus_address[7]);

--Y1_ext_ram_bus_address[7] is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_address[7] at PIN_D2

--operation mode is output --output register power-up is low

Y1_ext_ram_bus_address[7] = DFFE(Y1L430, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , );

--ext_ram_bus_address[6] is ext_ram_bus_address[6] at PIN_C2

--operation mode is output --output register power-up is low

ext_ram_bus_address[6] = OUTPUT(Y1_ext_ram_bus_address[6]);

--Y1_ext_ram_bus_address[6] is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_address[6] at PIN_C2

--operation mode is output --output register power-up is low

Y1_ext_ram_bus_address[6] = DFFE(Y1L427, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , );

--ext_ram_bus_address[5] is ext_ram_bus_address[5] at PIN_B5

--operation mode is output --output register power-up is low

ext_ram_bus_address[5] = OUTPUT(Y1_ext_ram_bus_address[5]);

--Y1_ext_ram_bus_address[5] is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_address[5] at PIN_B5

--operation mode is output --output register power-up is low

Y1_ext_ram_bus_address[5] = DFFE(Y1L424, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , );

--ext_ram_bus_address[4] is ext_ram_bus_address[4] at PIN_C5

--operation mode is output --output register power-up is low

ext_ram_bus_address[4] = OUTPUT(Y1_ext_ram_bus_address[4]);

--Y1_ext_ram_bus_address[4] is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_address[4] at PIN_C5

--operation mode is output --output register power-up is low

Y1_ext_ram_bus_address[4] = DFFE(Y1L421, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , );

--ext_ram_bus_address[3] is ext_ram_bus_address[3] at PIN_D6

--operation mode is output --output register power-up is low

ext_ram_bus_address[3] = OUTPUT(Y1_ext_ram_bus_address[3]);

--Y1_ext_ram_bus_address[3] is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_address[3] at PIN_D6

--operation mode is output --output register power-up is low

Y1_ext_ram_bus_address[3] = DFFE(Y1L418, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , );

--ext_ram_bus_address[2] is ext_ram_bus_address[2] at PIN_D5

--operation mode is output --output register power-up is low

ext_ram_bus_address[2] = OUTPUT(Y1_ext_ram_bus_address[2]);

--Y1_ext_ram_bus_address[2] is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_address[2] at PIN_D5

--operation mode is output --output register power-up is low

Y1_ext_ram_bus_address[2] = DFFE(Y1L415, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , );

--ext_ram_bus_address[1] is ext_ram_bus_address[1] at PIN_A4

--operation mode is output --output register power-up is low

ext_ram_bus_address[1] = OUTPUT(Y1_ext_ram_bus_address[1]);

--Y1_ext_ram_bus_address[1] is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_address[1] at PIN_A4

--operation mode is output --output register power-up is low

Y1_ext_ram_bus_address[1] = DFFE(Y1L412, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , );

--ext_ram_bus_address[0] is ext_ram_bus_address[0] at PIN_B4

--operation mode is output --output register power-up is low

ext_ram_bus_address[0] = OUTPUT(Y1_ext_ram_bus_address[0]);

--Y1_ext_ram_bus_address[0] is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_address[0] at PIN_B4

--operation mode is output --output register power-up is low

Y1_ext_ram_bus_address[0] = DFFE(Y1L409, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , );

--out_port_from_the_led_pio[7] is out_port_from_the_led_pio[7] at PIN_B14

--operation mode is output

out_port_from_the_led_pio[7] = OUTPUT(FB1_data_out[7]);

--out_port_from_the_led_pio[6] is out_port_from_the_led_pio[6] at PIN_B3

--operation mode is output

out_port_from_the_led_pio[6] = OUTPUT(FB1_data_out[6]);

--out_port_from_the_led_pio[5] is out_port_from_the_led_pio[5] at PIN_F12

--operation mode is output

out_port_from_the_led_pio[5] = OUTPUT(FB1_data_out[5]);

--out_port_from_the_led_pio[4] is out_port_from_the_led_pio[4] at PIN_E12

--operation mode is output

out_port_from_the_led_pio[4] = OUTPUT(FB1_data_out[4]);

--out_port_from_the_led_pio[3] is out_port_from_the_led_pio[3] at PIN_D14

--operation mode is output

out_port_from_the_led_pio[3] = OUTPUT(FB1_data_out[3]);

--out_port_from_the_led_pio[2] is out_port_from_the_led_pio[2] at PIN_C14

--operation mode is output

out_port_from_the_led_pio[2] = OUTPUT(FB1_data_out[2]);

--out_port_from_the_led_pio[1] is out_port_from_the_led_pio[1] at PIN_E13

--operation mode is output

out_port_from_the_led_pio[1] = OUTPUT(FB1_data_out[1]);

--out_port_from_the_led_pio[0] is out_port_from_the_led_pio[0] at PIN_E14

--operation mode is output

out_port_from_the_led_pio[0] = OUTPUT(FB1_data_out[0]);

--out_port_from_the_seven_seg_pio[15] is out_port_from_the_seven_seg_pio[15] at PIN_Y6

--operation mode is output

out_port_from_the_seven_seg_pio[15] = OUTPUT(PB1_data_out[15]);

--out_port_from_the_seven_seg_pio[14] is out_port_from_the_seven_seg_pio[14] at PIN_T5

--operation mode is output

out_port_from_the_seven_seg_pio[14] = OUTPUT(PB1_data_out[14]);

--out_port_from_the_seven_seg_pio[13] is out_port_from_the_seven_seg_pio[13] at PIN_U5

--operation mode is output

out_port_from_the_seven_seg_pio[13] = OUTPUT(PB1_data_out[13]);

--out_port_from_the_seven_seg_pio[12] is out_port_from_the_seven_seg_pio[12] at PIN_V5

--operation mode is output

out_port_from_the_seven_seg_pio[12] = OUTPUT(PB1_data_out[12]);

--out_port_from_the_seven_seg_pio[11] is out_port_from_the_seven_seg_pio[11] at PIN_W5

--operation mode is output

out_port_from_the_seven_seg_pio[11] = OUTPUT(PB1_data_out[11]);

--out_port_from_the_seven_seg_pio[10] is out_port_from_the_seven_seg_pio[10] at PIN_T6

--operation mode is output

out_port_from_the_seven_seg_pio[10] = OUTPUT(PB1_data_out[10]);

--out_port_from_the_seven_seg_pio[9] is out_port_from_the_seven_seg_pio[9] at PIN_T7

--operation mode is output

out_port_from_the_seven_seg_pio[9] = OUTPUT(PB1_data_out[9]);

--out_port_from_the_seven_seg_pio[8] is out_port_from_the_seven_seg_pio[8] at PIN_W6

--operation mode is output

out_port_from_the_seven_seg_pio[8] = OUTPUT(PB1_data_out[8]);

--out_port_from_the_seven_seg_pio[7] is out_port_from_the_seven_seg_pio[7] at PIN_U7

--operation mode is output

out_port_from_the_seven_seg_pio[7] = OUTPUT(PB1_data_out[7]);

--out_port_from_the_seven_seg_pio[6] is out_port_from_the_seven_seg_pio[6] at PIN_U6

--operation mode is output

out_port_from_the_seven_seg_pio[6] = OUTPUT(PB1_data_out[6]);

--out_port_from_the_seven_seg_pio[5] is out_port_from_the_seven_seg_pio[5] at PIN_V6

--operation mode is output

out_port_from_the_seven_seg_pio[5] = OUTPUT(PB1_data_out[5]);

--out_port_from_the_seven_seg_pio[4] is out_port_from_the_seven_seg_pio[4] at PIN_W7

--operation mode is output

out_port_from_the_seven_seg_pio[4] = OUTPUT(PB1_data_out[4]);

--out_port_from_the_seven_seg_pio[3] is out_port_from_the_seven_seg_pio[3] at PIN_Y7

--operation mode is output

out_port_from_the_seven_seg_pio[3] = OUTPUT(PB1_data_out[3]);

--out_port_from_the_seven_seg_pio[2] is out_port_from_the_seven_seg_pio[2] at PIN_R7

--operation mode is output

out_port_from_the_seven_seg_pio[2] = OUTPUT(PB1_data_out[2]);

--out_port_from_the_seven_seg_pio[1] is out_port_from_the_seven_seg_pio[1] at PIN_T8

--operation mode is output

out_port_from_the_seven_seg_pio[1] = OUTPUT(PB1_data_out[1]);

--out_port_from_the_seven_seg_pio[0] is out_port_from_the_seven_seg_pio[0] at PIN_V7

--operation mode is output

out_port_from_the_seven_seg_pio[0] = OUTPUT(PB1_data_out[0]);

--zs_addr_from_the_sdram[11] is zs_addr_from_the_sdram[11] at PIN_H5

--operation mode is output --output register power-up is low

zs_addr_from_the_sdram[11] = OUTPUT(KB1_m_addr[11]);

--KB1_m_addr[11] is std_1c20:inst|sdram:the_sdram|m_addr[11] at PIN_H5

--operation mode is output --output register power-up is low

KB1_m_addr[11] = DFFE(KB1L218, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , );

--zs_addr_from_the_sdram[10] is zs_addr_from_the_sdram[10] at PIN_H6

--operation mode is output --output register power-up is low

zs_addr_from_the_sdram[10] = OUTPUT(KB1_m_addr[10]);

--KB1_m_addr[10] is std_1c20:inst|sdram:the_sdram|m_addr[10] at PIN_H6

--operation mode is output --output register power-up is low

KB1_m_addr[10] = DFFE(KB1L214, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , );

--zs_addr_from_the_sdram[9] is zs_addr_from_the_sdram[9] at PIN_J3

--operation mode is output --output register power-up is low

zs_addr_from_the_sdram[9] = OUTPUT(KB1_m_addr[9]);

--KB1_m_addr[9] is std_1c20:inst|sdram:the_sdram|m_addr[9] at PIN_J3

--operation mode is output --output register power-up is low

KB1_m_addr[9] = DFFE(KB1L210, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , );

--zs_addr_from_the_sdram[8] is zs_addr_from_the_sdram[8] at PIN_J4

--operation mode is output --output register power-up is low

zs_addr_from_the_sdram[8] = OUTPUT(KB1_m_addr[8]);

--KB1_m_addr[8] is std_1c20:inst|sdram:the_sdram|m_addr[8] at PIN_J4

--operation mode is output --output register power-up is low

KB1_m_addr[8] = DFFE(KB1L206, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , );

--zs_addr_from_the_sdram[7] is zs_addr_from_the_sdram[7] at PIN_J5

--operation mode is output --output register power-up is low

zs_addr_from_the_sdram[7] = OUTPUT(KB1_m_addr[7]);

--KB1_m_addr[7] is std_1c20:inst|sdram:the_sdram|m_addr[7] at PIN_J5

--operation mode is output --output register power-up is low

KB1_m_addr[7] = DFFE(KB1L202, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , );

--zs_addr_from_the_sdram[6] is zs_addr_from_the_sdram[6] at PIN_J6

--operation mode is output --output register power-up is low

zs_addr_from_the_sdram[6] = OUTPUT(KB1_m_addr[6]);

--KB1_m_addr[6] is std_1c20:inst|sdram:the_sdram|m_addr[6] at PIN_J6

--operation mode is output --output register power-up is low

KB1_m_addr[6] = DFFE(KB1L197, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , );

--zs_addr_from_the_sdram[5] is zs_addr_from_the_sdram[5] at PIN_J7

--operation mode is output --output register power-up is low

zs_addr_from_the_sdram[5] = OUTPUT(KB1_m_addr[5]);

--KB1_m_addr[5] is std_1c20:inst|sdram:the_sdram|m_addr[5] at PIN_J7

--operation mode is output --output register power-up is low

KB1_m_addr[5] = DFFE(KB1L192, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , );

--zs_addr_from_the_sdram[4] is zs_addr_from_the_sdram[4] at PIN_J8

--operation mode is output --output register power-up is low

zs_addr_from_the_sdram[4] = OUTPUT(KB1_m_addr[4]);

--KB1_m_addr[4] is std_1c20:inst|sdram:the_sdram|m_addr[4] at PIN_J8

--operation mode is output --output register power-up is low

KB1_m_addr[4] = DFFE(KB1L187, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , );

--zs_addr_from_the_sdram[3] is zs_addr_from_the_sdram[3] at PIN_M4

--operation mode is output --output register power-up is low

zs_addr_from_the_sdram[3] = OUTPUT(KB1_m_addr[3]);

--KB1_m_addr[3] is std_1c20:inst|sdram:the_sdram|m_addr[3] at PIN_M4

--operation mode is output --output register power-up is low

KB1_m_addr[3] = DFFE(KB1L182, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , );

--zs_addr_from_the_sdram[2] is zs_addr_from_the_sdram[2] at PIN_M6

--operation mode is output --output register power-up is low

zs_addr_from_the_sdram[2] = OUTPUT(KB1_m_addr[2]);

--KB1_m_addr[2] is std_1c20:inst|sdram:the_sdram|m_addr[2] at PIN_M6

--operation mode is output --output register power-up is low

KB1_m_addr[2] = DFFE(KB1L177, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , );

--zs_addr_from_the_sdram[1] is zs_addr_from_the_sdram[1] at PIN_M1

--operation mode is output --output register power-up is low

zs_addr_from_the_sdram[1] = OUTPUT(KB1_m_addr[1]);

--KB1_m_addr[1] is std_1c20:inst|sdram:the_sdram|m_addr[1] at PIN_M1

--operation mode is output --output register power-up is low

KB1_m_addr[1] = DFFE(KB1L172, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , );

--zs_addr_from_the_sdram[0] is zs_addr_from_the_sdram[0] at PIN_M2

--operation mode is output --output register power-up is low

zs_addr_from_the_sdram[0] = OUTPUT(KB1_m_addr[0]);

--KB1_m_addr[0] is std_1c20:inst|sdram:the_sdram|m_addr[0] at PIN_M2

--operation mode is output --output register power-up is low

KB1_m_addr[0] = DFFE(KB1L167, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , );

--zs_ba_from_the_sdram[1] is zs_ba_from_the_sdram[1] at PIN_H1

--operation mode is output --output register power-up is low

zs_ba_from_the_sdram[1] = OUTPUT(KB1_m_bank[1]);

--KB1_m_bank[1] is std_1c20:inst|sdram:the_sdram|m_bank[1] at PIN_H1

--operation mode is output --output register power-up is low

KB1_m_bank[1] = DFFE(KB1L227, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , );

--zs_ba_from_the_sdram[0] is zs_ba_from_the_sdram[0] at PIN_H7

--operation mode is output --output register power-up is low

zs_ba_from_the_sdram[0] = OUTPUT(KB1_m_bank[0]);

--KB1_m_bank[0] is std_1c20:inst|sdram:the_sdram|m_bank[0] at PIN_H7

--operation mode is output --output register power-up is low

KB1_m_bank[0] = DFFE(KB1L223, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , );

--zs_dqm_from_the_sdram[3] is zs_dqm_from_the_sdram[3] at PIN_H3

--operation mode is output --output register power-up is low

zs_dqm_from_the_sdram[3] = OUTPUT(KB1_m_dqm[3]);

--KB1_m_dqm[3] is std_1c20:inst|sdram:the_sdram|m_dqm[3] at PIN_H3

--operation mode is output --output register power-up is low

KB1_m_dqm[3] = DFFE(KB1L428, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , );

--zs_dqm_from_the_sdram[2] is zs_dqm_from_the_sdram[2] at PIN_H4

--operation mode is output --output register power-up is low

zs_dqm_from_the_sdram[2] = OUTPUT(KB1_m_dqm[2]);

--KB1_m_dqm[2] is std_1c20:inst|sdram:the_sdram|m_dqm[2] at PIN_H4

--operation mode is output --output register power-up is low

KB1_m_dqm[2] = DFFE(KB1L424, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , );

--zs_dqm_from_the_sdram[1] is zs_dqm_from_the_sdram[1] at PIN_J1

--operation mode is output --output register power-up is low

zs_dqm_from_the_sdram[1] = OUTPUT(KB1_m_dqm[1]);

--KB1_m_dqm[1] is std_1c20:inst|sdram:the_sdram|m_dqm[1] at PIN_J1

--operation mode is output --output register power-up is low

KB1_m_dqm[1] = DFFE(KB1L420, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , );

--zs_dqm_from_the_sdram[0] is zs_dqm_from_the_sdram[0] at PIN_J2

--operation mode is output --output register power-up is low

zs_dqm_from_the_sdram[0] = OUTPUT(KB1_m_dqm[0]);

--KB1_m_dqm[0] is std_1c20:inst|sdram:the_sdram|m_dqm[0] at PIN_J2

--operation mode is output --output register power-up is low

KB1_m_dqm[0] = DFFE(KB1L416, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , );

--A1L20 is bidir_port_to_and_from_the_reconfig_request_pio~0 at PIN_V8

--operation mode is bidir

A1L20 = bidir_port_to_and_from_the_reconfig_request_pio;

--bidir_port_to_and_from_the_reconfig_request_pio is bidir_port_to_and_from_the_reconfig_request_pio at PIN_V8

--operation mode is bidir

bidir_port_to_and_from_the_reconfig_request_pio_tri_out = TRI(HB1_data_out, HB1_data_dir);

bidir_port_to_and_from_the_reconfig_request_pio = BIDIR(bidir_port_to_and_from_the_reconfig_request_pio_tri_out);

--Y1_internal_incoming_ext_ram_bus_data[31] is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|internal_incoming_ext_ram_bus_data[31] at PIN_E11

--operation mode is bidir --input register power-up is low --output register power-up is low --oe register power-up is low

Y1_internal_incoming_ext_ram_bus_data[31] = DFFE(ext_ram_bus_data[31], GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , );

--ext_ram_bus_data[31] is ext_ram_bus_data[31] at PIN_E11

--operation mode is bidir --input register power-up is low --output register power-up is low --oe register power-up is low

ext_ram_bus_data[31]_tri_out = TRI(Y1_d1_outgoing_ext_ram_bus_data[31], Y1L246Q);

ext_ram_bus_data[31] = BIDIR(ext_ram_bus_data[31]_tri_out);

--Y1_d1_outgoing_ext_ram_bus_data[31] is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_outgoing_ext_ram_bus_data[31] at PIN_E11

--operation mode is bidir --input register power-up is low --output register power-up is low --oe register power-up is low

Y1_d1_outgoing_ext_ram_bus_data[31] = DFFE(Y1L366, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , );

--Y1L246Q is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_in_a_write_cycle~_Duplicate_31 at PIN_E11

--operation mode is bidir --input register power-up is low --output register power-up is low --oe register power-up is low

Y1L246Q = DFFE(Y1L247, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , );

--Y1_internal_incoming_ext_ram_bus_data[30] is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|internal_incoming_ext_ram_bus_data[30] at PIN_A11

--operation mode is bidir --input register power-up is low --output register power-up is low --oe register power-up is low

Y1_internal_incoming_ext_ram_bus_data[30] = DFFE(ext_ram_bus_data[30], GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , );

--ext_ram_bus_data[30] is ext_ram_bus_data[30] at PIN_A11

--operation mode is bidir --input register power-up is low --output register power-up is low --oe register power-up is low

ext_ram_bus_data[30]_tri_out = TRI(Y1_d1_outgoing_ext_ram_bus_data[30], Y1L245Q);

ext_ram_bus_data[30] = BIDIR(ext_ram_bus_data[30]_tri_out);

--Y1_d1_outgoing_ext_ram_bus_data[30] is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_outgoing_ext_ram_bus_data[30] at PIN_A11

--operation mode is bidir --input register power-up is low --output register power-up is low --oe register power-up is low

Y1_d1_outgoing_ext_ram_bus_data[30] = DFFE(Y1L363, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , );

--Y1L245Q is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_in_a_write_cycle~_Duplicate_30 at PIN_A11

--operation mode is bidir --input register power-up is low --output register power-up is low --oe register power-up is low

Y1L245Q = DFFE(Y1L247, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , );

--Y1_internal_incoming_ext_ram_bus_data[29] is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|internal_incoming_ext_ram_bus_data[29] at PIN_B11

--operation mode is bidir --input register power-up is low --output register power-up is low --oe register power-up is low

Y1_internal_incoming_ext_ram_bus_data[29] = DFFE(ext_ram_bus_data[29], GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , );

--ext_ram_bus_data[29] is ext_ram_bus_data[29] at PIN_B11

--operation mode is bidir --input register power-up is low --output register power-up is low --oe register power-up is low

ext_ram_bus_data[29]_tri_out = TRI(Y1_d1_outgoing_ext_ram_bus_data[29], Y1L244Q);

ext_ram_bus_data[29] = BIDIR(ext_ram_bus_data[29]_tri_out);

--Y1_d1_outgoing_ext_ram_bus_data[29] is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_outgoing_ext_ram_bus_data[29] at PIN_B11

--operation mode is bidir --input register power-up is low --output register power-up is low --oe register power-up is low

Y1_d1_outgoing_ext_ram_bus_data[29] = DFFE(Y1L360, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , );

--Y1L244Q is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_in_a_write_cycle~_Duplicate_29 at PIN_B11

--operation mode is bidir --input register power-up is low --output register power-up is low --oe register power-up is low

Y1L244Q = DFFE(Y1L247, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , );

--Y1_internal_incoming_ext_ram_bus_data[28] is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|internal_incoming_ext_ram_bus_data[28] at PIN_D11

--operation mode is bidir --input register power-up is low --output register power-up is low --oe register power-up is low

Y1_internal_incoming_ext_ram_bus_data[28] = DFFE(ext_ram_bus_data[28], GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , );

--ext_ram_bus_data[28] is ext_ram_bus_data[28] at PIN_D11

--operation mode is bidir --input register power-up is low --output register power-up is low --oe register power-up is low

ext_ram_bus_data[28]_tri_out = TRI(Y1_d1_outgoing_ext_ram_bus_data[28], Y1L243Q);

ext_ram_bus_data[28] = BIDIR(ext_ram_bus_data[28]_tri_out);

--Y1_d1_outgoing_ext_ram_bus_data[28] is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_outgoing_ext_ram_bus_data[28] at PIN_D11

--operation mode is bidir --input register power-up is low --output register power-up is low --oe register power-up is low

Y1_d1_outgoing_ext_ram_bus_data[28] = DFFE(Y1L357, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , );

--Y1L243Q is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_in_a_write_cycle~_Duplicate_28 at PIN_D11

--operation mode is bidir --input register power-up is low --output register power-up is low --oe register power-up is low

Y1L243Q = DFFE(Y1L247, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , );

--Y1_internal_incoming_ext_ram_bus_data[27] is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|internal_incoming_ext_ram_bus_data[27] at PIN_C11

--operation mode is bidir --input register power-up is low --output register power-up is low --oe register power-up is low

Y1_internal_incoming_ext_ram_bus_data[27] = DFFE(ext_ram_bus_data[27], GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , );

--ext_ram_bus_data[27] is ext_ram_bus_data[27] at PIN_C11

--operation mode is bidir --input register power-up is low --output register power-up is low --oe register power-up is low

ext_ram_bus_data[27]_tri_out = TRI(Y1_d1_outgoing_ext_ram_bus_data[27], Y1L242Q);

ext_ram_bus_data[27] = BIDIR(ext_ram_bus_data[27]_tri_out);

--Y1_d1_outgoing_ext_ram_bus_data[27] is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_outgoing_ext_ram_bus_data[27] at PIN_C11

--operation mode is bidir --input register power-up is low --output register power-up is low --oe register power-up is low

Y1_d1_outgoing_ext_ram_bus_data[27] = DFFE(Y1L354, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , );

--Y1L242Q is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_in_a_write_cycle~_Duplicate_27 at PIN_C11

--operation mode is bidir --input register power-up is low --output register power-up is low --oe register power-up is low

Y1L242Q = DFFE(Y1L247, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , );

--Y1_internal_incoming_ext_ram_bus_data[26] is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|internal_incoming_ext_ram_bus_data[26] at PIN_D10

--operation mode is bidir --input register power-up is low --output register power-up is low --oe register power-up is low

Y1_internal_incoming_ext_ram_bus_data[26] = DFFE(ext_ram_bus_data[26], GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , );

--ext_ram_bus_data[26] is ext_ram_bus_data[26] at PIN_D10

--operation mode is bidir --input register power-up is low --output register power-up is low --oe register power-up is low

ext_ram_bus_data[26]_tri_out = TRI(Y1_d1_outgoing_ext_ram_bus_data[26], Y1L241Q);

ext_ram_bus_data[26] = BIDIR(ext_ram_bus_data[26]_tri_out);

--Y1_d1_outgoing_ext_ram_bus_data[26] is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_outgoing_ext_ram_bus_data[26] at PIN_D10

--operation mode is bidir --input register power-up is low --output register power-up is low --oe register power-up is low

Y1_d1_outgoing_ext_ram_bus_data[26] = DFFE(Y1L351, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , );

--Y1L241Q is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_in_a_write_cycle~_Duplicate_26 at PIN_D10

--operation mode is bidir --input register power-up is low --output register power-up is low --oe register power-up is low

Y1L241Q = DFFE(Y1L247, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , );

--Y1_internal_incoming_ext_ram_bus_data[25] is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|internal_incoming_ext_ram_bus_data[25] at PIN_C10

--operation mode is bidir --input register power-up is low --output register power-up is low --oe register power-up is low

Y1_internal_incoming_ext_ram_bus_data[25] = DFFE(ext_ram_bus_data[25], GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , );

--ext_ram_bus_data[25] is ext_ram_bus_data[25] at PIN_C10

--operation mode is bidir --input register power-up is low --output register power-up is low --oe register power-up is low

ext_ram_bus_data[25]_tri_out = TRI(Y1_d1_outgoing_ext_ram_bus_data[25], Y1L240Q);

ext_ram_bus_data[25] = BIDIR(ext_ram_bus_data[25]_tri_out);

--Y1_d1_outgoing_ext_ram_bus_data[25] is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_outgoing_ext_ram_bus_data[25] at PIN_C10

--operation mode is bidir --input register power-up is low --output register power-up is low --oe register power-up is low

Y1_d1_outgoing_ext_ram_bus_data[25] = DFFE(Y1L348, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , );

--Y1L240Q is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_in_a_write_cycle~_Duplicate_25 at PIN_C10

--operation mode is bidir --input register power-up is low --output register power-up is low --oe register power-up is low

Y1L240Q = DFFE(Y1L247, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , );

--Y1_internal_incoming_ext_ram_bus_data[24] is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|internal_incoming_ext_ram_bus_data[24] at PIN_F10

--operation mode is bidir --input register power-up is low --output register power-up is low --oe register power-up is low

Y1_internal_incoming_ext_ram_bus_data[24] = DFFE(ext_ram_bus_data[24], GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , );

--ext_ram_bus_data[24] is ext_ram_bus_data[24] at PIN_F10

--operation mode is bidir --input register power-up is low --output register power-up is low --oe register power-up is low

ext_ram_bus_data[24]_tri_out = TRI(Y1_d1_outgoing_ext_ram_bus_data[24], Y1L239Q);

ext_ram_bus_data[24] = BIDIR(ext_ram_bus_data[24]_tri_out);

--Y1_d1_outgoing_ext_ram_bus_data[24] is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_outgoing_ext_ram_bus_data[24] at PIN_F10

--operation mode is bidir --input register power-up is low --output register power-up is low --oe register power-up is low

Y1_d1_outgoing_ext_ram_bus_data[24] = DFFE(Y1L345, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , );

--Y1L239Q is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_in_a_write_cycle~_Duplicate_24 at PIN_F10

--operation mode is bidir --input register power-up is low --output register power-up is low --oe register power-up is low

Y1L239Q = DFFE(Y1L247, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , );

--Y1_internal_incoming_ext_ram_bus_data[23] is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|internal_incoming_ext_ram_bus_data[23] at PIN_A10

--operation mode is bidir --input register power-up is low --output register power-up is low --oe register power-up is low

Y1_internal_incoming_ext_ram_bus_data[23] = DFFE(ext_ram_bus_data[23], GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , );

--ext_ram_bus_data[23] is ext_ram_bus_data[23] at PIN_A10

--operation mode is bidir --input register power-up is low --output register power-up is low --oe register power-up is low

ext_ram_bus_data[23]_tri_out = TRI(Y1_d1_outgoing_ext_ram_bus_data[23], Y1L238Q);

ext_ram_bus_data[23] = BIDIR(ext_ram_bus_data[23]_tri_out);

--Y1_d1_outgoing_ext_ram_bus_data[23] is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_outgoing_ext_ram_bus_data[23] at PIN_A10

--operation mode is bidir --input register power-up is low --output register power-up is low --oe register power-up is low

Y1_d1_outgoing_ext_ram_bus_data[23] = DFFE(Y1L342, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , );

--Y1L238Q is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_in_a_write_cycle~_Duplicate_23 at PIN_A10

--operation mode is bidir --input register power-up is low --output register power-up is low --oe register power-up is low

Y1L238Q = DFFE(Y1L247, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , );

--Y1_internal_incoming_ext_ram_bus_data[22] is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|internal_incoming_ext_ram_bus_data[22] at PIN_B10

--operation mode is bidir --input register power-up is low --output register power-up is low --oe register power-up is low

Y1_internal_incoming_ext_ram_bus_data[22] = DFFE(ext_ram_bus_data[22], GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , );

--ext_ram_bus_data[22] is ext_ram_bus_data[22] at PIN_B10

--operation mode is bidir --input register power-up is low --output register power-up is low --oe register power-up is low

ext_ram_bus_data[22]_tri_out = TRI(Y1_d1_outgoing_ext_ram_bus_data[22], Y1L237Q);

ext_ram_bus_data[22] = BIDIR(ext_ram_bus_data[22]_tri_out);

--Y1_d1_outgoing_ext_ram_bus_data[22] is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_outgoing_ext_ram_bus_data[22] at PIN_B10

--operation mode is bidir --input register power-up is low --output register power-up is low --oe register power-up is low

Y1_d1_outgoing_ext_ram_bus_data[22] = DFFE(Y1L339, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , );

--Y1L237Q is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_in_a_write_cycle~_Duplicate_22 at PIN_B10

--operation mode is bidir --input register power-up is low --output register power-up is low --oe register power-up is low

Y1L237Q = DFFE(Y1L247, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , );

--Y1_internal_incoming_ext_ram_bus_data[21] is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|internal_incoming_ext_ram_bus_data[21] at PIN_E10

--operation mode is bidir --input register power-up is low --output register power-up is low --oe register power-up is low

Y1_internal_incoming_ext_ram_bus_data[21] = DFFE(ext_ram_bus_data[21], GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , );

--ext_ram_bus_data[21] is ext_ram_bus_data[21] at PIN_E10

--operation mode is bidir --input register power-up is low --output register power-up is low --oe register power-up is low

ext_ram_bus_data[21]_tri_out = TRI(Y1_d1_outgoing_ext_ram_bus_data[21], Y1L236Q);

ext_ram_bus_data[21] = BIDIR(ext_ram_bus_data[21]_tri_out);

--Y1_d1_outgoing_ext_ram_bus_data[21] is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_outgoing_ext_ram_bus_data[21] at PIN_E10

--operation mode is bidir --input register power-up is low --output register power-up is low --oe register power-up is low

Y1_d1_outgoing_ext_ram_bus_data[21] = DFFE(Y1L336, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , );

--Y1L236Q is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_in_a_write_cycle~_Duplicate_21 at PIN_E10

--operation mode is bidir --input register power-up is low --output register power-up is low --oe register power-up is low

Y1L236Q = DFFE(Y1L247, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , );

--Y1_internal_incoming_ext_ram_bus_data[20] is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|internal_incoming_ext_ram_bus_data[20] at PIN_E9

--operation mode is bidir --input register power-up is low --output register power-up is low --oe register power-up is low

Y1_internal_incoming_ext_ram_bus_data[20] = DFFE(ext_ram_bus_data[20], GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , );

--ext_ram_bus_data[20] is ext_ram_bus_data[20] at PIN_E9

--operation mode is bidir --input register power-up is low --output register power-up is low --oe register power-up is low

ext_ram_bus_data[20]_tri_out = TRI(Y1_d1_outgoing_ext_ram_bus_data[20], Y1L235Q);

ext_ram_bus_data[20] = BIDIR(ext_ram_bus_data[20]_tri_out);

--Y1_d1_outgoing_ext_ram_bus_data[20] is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_outgoing_ext_ram_bus_data[20] at PIN_E9

--operation mode is bidir --input register power-up is low --output register power-up is low --oe register power-up is low

Y1_d1_outgoing_ext_ram_bus_data[20] = DFFE(Y1L333, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , );

--Y1L235Q is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_in_a_write_cycle~_Duplicate_20 at PIN_E9

--operation mode is bidir --input register power-up is low --output register power-up is low --oe register power-up is low

Y1L235Q = DFFE(Y1L247, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , );

--Y1_internal_incoming_ext_ram_bus_data[19] is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|internal_incoming_ext_ram_bus_data[19] at PIN_C9

--operation mode is bidir --input register power-up is low --output register power-up is low --oe register power-up is low

Y1_internal_incoming_ext_ram_bus_data[19] = DFFE(ext_ram_bus_data[19], GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , );

--ext_ram_bus_data[19] is ext_ram_bus_data[19] at PIN_C9

--operation mode is bidir --input register power-up is low --output register power-up is low --oe register power-up is low

ext_ram_bus_data[19]_tri_out = TRI(Y1_d1_outgoing_ext_ram_bus_data[19], Y1L234Q);

ext_ram_bus_data[19] = BIDIR(ext_ram_bus_data[19]_tri_out);

--Y1_d1_outgoing_ext_ram_bus_data[19] is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_outgoing_ext_ram_bus_data[19] at PIN_C9

--operation mode is bidir --input register power-up is low --output register power-up is low --oe register power-up is low

Y1_d1_outgoing_ext_ram_bus_data[19] = DFFE(Y1L330, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , );

--Y1L234Q is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_in_a_write_cycle~_Duplicate_19 at PIN_C9

--operation mode is bidir --input register power-up is low --output register power-up is low --oe register power-up is low

Y1L234Q = DFFE(Y1L247, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , );

--Y1_internal_incoming_ext_ram_bus_data[18] is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|internal_incoming_ext_ram_bus_data[18] at PIN_D9

--operation mode is bidir --input register power-up is low --output register power-up is low --oe register power-up is low

Y1_internal_incoming_ext_ram_bus_data[18] = DFFE(ext_ram_bus_data[18], GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , );

--ext_ram_bus_data[18] is ext_ram_bus_data[18] at PIN_D9

--operation mode is bidir --input register power-up is low --output register power-up is low --oe register power-up is low

ext_ram_bus_data[18]_tri_out = TRI(Y1_d1_outgoing_ext_ram_bus_data[18], Y1L233Q);

ext_ram_bus_data[18] = BIDIR(ext_ram_bus_data[18]_tri_out);

--Y1_d1_outgoing_ext_ram_bus_data[18] is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_outgoing_ext_ram_bus_data[18] at PIN_D9

--operation mode is bidir --input register power-up is low --output register power-up is low --oe register power-up is low

Y1_d1_outgoing_ext_ram_bus_data[18] = DFFE(Y1L327, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , );

--Y1L233Q is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_in_a_write_cycle~_Duplicate_18 at PIN_D9

--operation mode is bidir --input register power-up is low --output register power-up is low --oe register power-up is low

Y1L233Q = DFFE(Y1L247, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , );

--Y1_internal_incoming_ext_ram_bus_data[17] is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|internal_incoming_ext_ram_bus_data[17] at PIN_A9

--operation mode is bidir --input register power-up is low --output register power-up is low --oe register power-up is low

Y1_internal_incoming_ext_ram_bus_data[17] = DFFE(ext_ram_bus_data[17], GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , );

--ext_ram_bus_data[17] is ext_ram_bus_data[17] at PIN_A9

--operation mode is bidir --input register power-up is low --output register power-up is low --oe register power-up is low

ext_ram_bus_data[17]_tri_out = TRI(Y1_d1_outgoing_ext_ram_bus_data[17], Y1L232Q);

ext_ram_bus_data[17] = BIDIR(ext_ram_bus_data[17]_tri_out);

--Y1_d1_outgoing_ext_ram_bus_data[17] is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_outgoing_ext_ram_bus_data[17] at PIN_A9

--operation mode is bidir --input register power-up is low --output register power-up is low --oe register power-up is low

Y1_d1_outgoing_ext_ram_bus_data[17] = DFFE(Y1L324, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , );

--Y1L232Q is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_in_a_write_cycle~_Duplicate_17 at PIN_A9

--operation mode is bidir --input register power-up is low --output register power-up is low --oe register power-up is low

Y1L232Q = DFFE(Y1L247, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , );

--Y1_internal_incoming_ext_ram_bus_data[16] is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|internal_incoming_ext_ram_bus_data[16] at PIN_B9

--operation mode is bidir --input register power-up is low --output register power-up is low --oe register power-up is low

Y1_internal_incoming_ext_ram_bus_data[16] = DFFE(ext_ram_bus_data[16], GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , );

--ext_ram_bus_data[16] is ext_ram_bus_data[16] at PIN_B9

--operation mode is bidir --input register power-up is low --output register power-up is low --oe register power-up is low

ext_ram_bus_data[16]_tri_out = TRI(Y1_d1_outgoing_ext_ram_bus_data[16], Y1L231Q);

ext_ram_bus_data[16] = BIDIR(ext_ram_bus_data[16]_tri_out);

--Y1_d1_outgoing_ext_ram_bus_data[16] is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_outgoing_ext_ram_bus_data[16] at PIN_B9

--operation mode is bidir --input register power-up is low --output register power-up is low --oe register power-up is low

Y1_d1_outgoing_ext_ram_bus_data[16] = DFFE(Y1L321, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , );

--Y1L231Q is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_in_a_write_cycle~_Duplicate_16 at PIN_B9

--operation mode is bidir --input register power-up is low --output register power-up is low --oe register power-up is low

Y1L231Q = DFFE(Y1L247, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , );

--Y1_internal_incoming_ext_ram_bus_data[15] is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|internal_incoming_ext_ram_bus_data[15] at PIN_C8

--operation mode is bidir --input register power-up is low --output register power-up is low --oe register power-up is low

Y1_internal_incoming_ext_ram_bus_data[15] = DFFE(ext_ram_bus_data[15], GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , );

--ext_ram_bus_data[15] is ext_ram_bus_data[15] at PIN_C8

--operation mode is bidir --input register power-up is low --output register power-up is low --oe register power-up is low

ext_ram_bus_data[15]_tri_out = TRI(Y1_d1_outgoing_ext_ram_bus_data[15], Y1L230Q);

ext_ram_bus_data[15] = BIDIR(ext_ram_bus_data[15]_tri_out);

--Y1_d1_outgoing_ext_ram_bus_data[15] is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_outgoing_ext_ram_bus_data[15] at PIN_C8

--operation mode is bidir --input register power-up is low --output register power-up is low --oe register power-up is low

Y1_d1_outgoing_ext_ram_bus_data[15] = DFFE(Y1L318, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , );

--Y1L230Q is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_in_a_write_cycle~_Duplicate_15 at PIN_C8

--operation mode is bidir --input register power-up is low --output register power-up is low --oe register power-up is low

Y1L230Q = DFFE(Y1L247, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , );

--Y1_internal_incoming_ext_ram_bus_data[14] is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|internal_incoming_ext_ram_bus_data[14] at PIN_D8

--operation mode is bidir --input register power-up is low --output register power-up is low --oe register power-up is low

Y1_internal_incoming_ext_ram_bus_data[14] = DFFE(ext_ram_bus_data[14], GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , );

--ext_ram_bus_data[14] is ext_ram_bus_data[14] at PIN_D8

--operation mode is bidir --input register power-up is low --output register power-up is low --oe register power-up is low

ext_ram_bus_data[14]_tri_out = TRI(Y1_d1_outgoing_ext_ram_bus_data[14], Y1L229Q);

ext_ram_bus_data[14] = BIDIR(ext_ram_bus_data[14]_tri_out);

--Y1_d1_outgoing_ext_ram_bus_data[14] is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_outgoing_ext_ram_bus_data[14] at PIN_D8

--operation mode is bidir --input register power-up is low --output register power-up is low --oe register power-up is low

Y1_d1_outgoing_ext_ram_bus_data[14] = DFFE(Y1L315, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , );

--Y1L229Q is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_in_a_write_cycle~_Duplicate_14 at PIN_D8

--operation mode is bidir --input register power-up is low --output register power-up is low --oe register power-up is low

Y1L229Q = DFFE(Y1L247, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , );

--Y1_internal_incoming_ext_ram_bus_data[13] is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|internal_incoming_ext_ram_bus_data[13] at PIN_A8

--operation mode is bidir --input register power-up is low --output register power-up is low --oe register power-up is low

Y1_internal_incoming_ext_ram_bus_data[13] = DFFE(ext_ram_bus_data[13], GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , );

--ext_ram_bus_data[13] is ext_ram_bus_data[13] at PIN_A8

--operation mode is bidir --input register power-up is low --output register power-up is low --oe register power-up is low

ext_ram_bus_data[13]_tri_out = TRI(Y1_d1_outgoing_ext_ram_bus_data[13], Y1L228Q);

ext_ram_bus_data[13] = BIDIR(ext_ram_bus_data[13]_tri_out);

--Y1_d1_outgoing_ext_ram_bus_data[13] is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_outgoing_ext_ram_bus_data[13] at PIN_A8

--operation mode is bidir --input register power-up is low --output register power-up is low --oe register power-up is low

Y1_d1_outgoing_ext_ram_bus_data[13] = DFFE(Y1L312, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , );

--Y1L228Q is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_in_a_write_cycle~_Duplicate_13 at PIN_A8

--operation mode is bidir --input register power-up is low --output register power-up is low --oe register power-up is low

Y1L228Q = DFFE(Y1L247, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , );

--Y1_internal_incoming_ext_ram_bus_data[12] is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|internal_incoming_ext_ram_bus_data[12] at PIN_B8

--operation mode is bidir --input register power-up is low --output register power-up is low --oe register power-up is low

Y1_internal_incoming_ext_ram_bus_data[12] = DFFE(ext_ram_bus_data[12], GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , );

--ext_ram_bus_data[12] is ext_ram_bus_data[12] at PIN_B8

--operation mode is bidir --input register power-up is low --output register power-up is low --oe register power-up is low

ext_ram_bus_data[12]_tri_out = TRI(Y1_d1_outgoing_ext_ram_bus_data[12], Y1L227Q);

ext_ram_bus_data[12] = BIDIR(ext_ram_bus_data[12]_tri_out);

--Y1_d1_outgoing_ext_ram_bus_data[12] is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_outgoing_ext_ram_bus_data[12] at PIN_B8

--operation mode is bidir --input register power-up is low --output register power-up is low --oe register power-up is low

Y1_d1_outgoing_ext_ram_bus_data[12] = DFFE(Y1L309, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , );

--Y1L227Q is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_in_a_write_cycle~_Duplicate_12 at PIN_B8

--operation mode is bidir --input register power-up is low --output register power-up is low --oe register power-up is low

Y1L227Q = DFFE(Y1L247, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , );

--Y1_internal_incoming_ext_ram_bus_data[11] is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|internal_incoming_ext_ram_bus_data[11] at PIN_E8

--operation mode is bidir --input register power-up is low --output register power-up is low --oe register power-up is low

Y1_internal_incoming_ext_ram_bus_data[11] = DFFE(ext_ram_bus_data[11], GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , );

--ext_ram_bus_data[11] is ext_ram_bus_data[11] at PIN_E8

--operation mode is bidir --input register power-up is low --output register power-up is low --oe register power-up is low

ext_ram_bus_data[11]_tri_out = TRI(Y1_d1_outgoing_ext_ram_bus_data[11], Y1L226Q);

ext_ram_bus_data[11] = BIDIR(ext_ram_bus_data[11]_tri_out);

--Y1_d1_outgoing_ext_ram_bus_data[11] is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_outgoing_ext_ram_bus_data[11] at PIN_E8

--operation mode is bidir --input register power-up is low --output register power-up is low --oe register power-up is low

Y1_d1_outgoing_ext_ram_bus_data[11] = DFFE(Y1L306, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , );

--Y1L226Q is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_in_a_write_cycle~_Duplicate_11 at PIN_E8

--operation mode is bidir --input register power-up is low --output register power-up is low --oe register power-up is low

Y1L226Q = DFFE(Y1L247, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , );

--Y1_internal_incoming_ext_ram_bus_data[10] is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|internal_incoming_ext_ram_bus_data[10] at PIN_F8

--operation mode is bidir --input register power-up is low --output register power-up is low --oe register power-up is low

Y1_internal_incoming_ext_ram_bus_data[10] = DFFE(ext_ram_bus_data[10], GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , );

--ext_ram_bus_data[10] is ext_ram_bus_data[10] at PIN_F8

--operation mode is bidir --input register power-up is low --output register power-up is low --oe register power-up is low

ext_ram_bus_data[10]_tri_out = TRI(Y1_d1_outgoing_ext_ram_bus_data[10], Y1L225Q);

ext_ram_bus_data[10] = BIDIR(ext_ram_bus_data[10]_tri_out);

--Y1_d1_outgoing_ext_ram_bus_data[10] is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_outgoing_ext_ram_bus_data[10] at PIN_F8

--operation mode is bidir --input register power-up is low --output register power-up is low --oe register power-up is low

Y1_d1_outgoing_ext_ram_bus_data[10] = DFFE(Y1L303, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , );

--Y1L225Q is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_in_a_write_cycle~_Duplicate_10 at PIN_F8

--operation mode is bidir --input register power-up is low --output register power-up is low --oe register power-up is low

Y1L225Q = DFFE(Y1L247, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , );

--Y1_internal_incoming_ext_ram_bus_data[9] is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|internal_incoming_ext_ram_bus_data[9] at PIN_C7

--operation mode is bidir --input register power-up is low --output register power-up is low --oe register power-up is low

Y1_internal_incoming_ext_ram_bus_data[9] = DFFE(ext_ram_bus_data[9], GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , );

--ext_ram_bus_data[9] is ext_ram_bus_data[9] at PIN_C7

--operation mode is bidir --input register power-up is low --output register power-up is low --oe register power-up is low

ext_ram_bus_data[9]_tri_out = TRI(Y1_d1_outgoing_ext_ram_bus_data[9], Y1L224Q);

ext_ram_bus_data[9] = BIDIR(ext_ram_bus_data[9]_tri_out);

--Y1_d1_outgoing_ext_ram_bus_data[9] is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_outgoing_ext_ram_bus_data[9] at PIN_C7

--operation mode is bidir --input register power-up is low --output register power-up is low --oe register power-up is low

Y1_d1_outgoing_ext_ram_bus_data[9] = DFFE(Y1L300, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , );

--Y1L224Q is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_in_a_write_cycle~_Duplicate_9 at PIN_C7

--operation mode is bidir --input register power-up is low --output register power-up is low --oe register power-up is low

Y1L224Q = DFFE(Y1L247, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , );

--Y1_internal_incoming_ext_ram_bus_data[8] is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|internal_incoming_ext_ram_bus_data[8] at PIN_D7

--operation mode is bidir --input register power-up is low --output register power-up is low --oe register power-up is low

Y1_internal_incoming_ext_ram_bus_data[8] = DFFE(ext_ram_bus_data[8], GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , );

--ext_ram_bus_data[8] is ext_ram_bus_data[8] at PIN_D7

--operation mode is bidir --input register power-up is low --output register power-up is low --oe register power-up is low

ext_ram_bus_data[8]_tri_out = TRI(Y1_d1_outgoing_ext_ram_bus_data[8], Y1L223Q);

ext_ram_bus_data[8] = BIDIR(ext_ram_bus_data[8]_tri_out);

--Y1_d1_outgoing_ext_ram_bus_data[8] is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_outgoing_ext_ram_bus_data[8] at PIN_D7

--operation mode is bidir --input register power-up is low --output register power-up is low --oe register power-up is low

Y1_d1_outgoing_ext_ram_bus_data[8] = DFFE(Y1L297, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , );

--Y1L223Q is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_in_a_write_cycle~_Duplicate_8 at PIN_D7

--operation mode is bidir --input register power-up is low --output register power-up is low --oe register power-up is low

Y1L223Q = DFFE(Y1L247, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , );

--Y1_internal_incoming_ext_ram_bus_data[7] is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|internal_incoming_ext_ram_bus_data[7] at PIN_A7

--operation mode is bidir --input register power-up is low --output register power-up is low --oe register power-up is low

Y1_internal_incoming_ext_ram_bus_data[7] = DFFE(ext_ram_bus_data[7], GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , );

--ext_ram_bus_data[7] is ext_ram_bus_data[7] at PIN_A7

--operation mode is bidir --input register power-up is low --output register power-up is low --oe register power-up is low

ext_ram_bus_data[7]_tri_out = TRI(Y1_d1_outgoing_ext_ram_bus_data[7], Y1L222Q);

ext_ram_bus_data[7] = BIDIR(ext_ram_bus_data[7]_tri_out);

--Y1_d1_outgoing_ext_ram_bus_data[7] is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_outgoing_ext_ram_bus_data[7] at PIN_A7

--operation mode is bidir --input register power-up is low --output register power-up is low --oe register power-up is low

Y1_d1_outgoing_ext_ram_bus_data[7] = DFFE(Y1L294, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , );

--Y1L222Q is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_in_a_write_cycle~_Duplicate_7 at PIN_A7

--operation mode is bidir --input register power-up is low --output register power-up is low --oe register power-up is low

Y1L222Q = DFFE(Y1L247, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , );

--Y1_internal_incoming_ext_ram_bus_data[6] is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|internal_incoming_ext_ram_bus_data[6] at PIN_B7

--operation mode is bidir --input register power-up is low --output register power-up is low --oe register power-up is low

Y1_internal_incoming_ext_ram_bus_data[6] = DFFE(ext_ram_bus_data[6], GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , );

--ext_ram_bus_data[6] is ext_ram_bus_data[6] at PIN_B7

--operation mode is bidir --input register power-up is low --output register power-up is low --oe register power-up is low

ext_ram_bus_data[6]_tri_out = TRI(Y1_d1_outgoing_ext_ram_bus_data[6], Y1L221Q);

ext_ram_bus_data[6] = BIDIR(ext_ram_bus_data[6]_tri_out);

--Y1_d1_outgoing_ext_ram_bus_data[6] is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_outgoing_ext_ram_bus_data[6] at PIN_B7

--operation mode is bidir --input register power-up is low --output register power-up is low --oe register power-up is low

Y1_d1_outgoing_ext_ram_bus_data[6] = DFFE(Y1L283, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , );

--Y1L221Q is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_in_a_write_cycle~_Duplicate_6 at PIN_B7

--operation mode is bidir --input register power-up is low --output register power-up is low --oe register power-up is low

Y1L221Q = DFFE(Y1L247, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , );

--Y1_internal_incoming_ext_ram_bus_data[5] is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|internal_incoming_ext_ram_bus_data[5] at PIN_E7

--operation mode is bidir --input register power-up is low --output register power-up is low --oe register power-up is low

Y1_internal_incoming_ext_ram_bus_data[5] = DFFE(ext_ram_bus_data[5], GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , );

--ext_ram_bus_data[5] is ext_ram_bus_data[5] at PIN_E7

--operation mode is bidir --input register power-up is low --output register power-up is low --oe register power-up is low

ext_ram_bus_data[5]_tri_out = TRI(Y1_d1_outgoing_ext_ram_bus_data[5], Y1L220Q);

ext_ram_bus_data[5] = BIDIR(ext_ram_bus_data[5]_tri_out);

--Y1_d1_outgoing_ext_ram_bus_data[5] is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_outgoing_ext_ram_bus_data[5] at PIN_E7

--operation mode is bidir --input register power-up is low --output register power-up is low --oe register power-up is low

Y1_d1_outgoing_ext_ram_bus_data[5] = DFFE(Y1L272, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , );

--Y1L220Q is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_in_a_write_cycle~_Duplicate_5 at PIN_E7

--operation mode is bidir --input register power-up is low --output register power-up is low --oe register power-up is low

Y1L220Q = DFFE(Y1L247, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , );

--Y1_internal_incoming_ext_ram_bus_data[4] is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|internal_incoming_ext_ram_bus_data[4] at PIN_F7

--operation mode is bidir --input register power-up is low --output register power-up is low --oe register power-up is low

Y1_internal_incoming_ext_ram_bus_data[4] = DFFE(ext_ram_bus_data[4], GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , );

--ext_ram_bus_data[4] is ext_ram_bus_data[4] at PIN_F7

--operation mode is bidir --input register power-up is low --output register power-up is low --oe register power-up is low

ext_ram_bus_data[4]_tri_out = TRI(Y1_d1_outgoing_ext_ram_bus_data[4], Y1L219Q);

ext_ram_bus_data[4] = BIDIR(ext_ram_bus_data[4]_tri_out);

--Y1_d1_outgoing_ext_ram_bus_data[4] is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_outgoing_ext_ram_bus_data[4] at PIN_F7

--operation mode is bidir --input register power-up is low --output register power-up is low --oe register power-up is low

Y1_d1_outgoing_ext_ram_bus_data[4] = DFFE(Y1L261, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , );

--Y1L219Q is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_in_a_write_cycle~_Duplicate_4 at PIN_F7

--operation mode is bidir --input register power-up is low --output register power-up is low --oe register power-up is low

Y1L219Q = DFFE(Y1L247, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , );

--Y1_internal_incoming_ext_ram_bus_data[3] is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|internal_incoming_ext_ram_bus_data[3] at PIN_A6

--operation mode is bidir --input register power-up is low --output register power-up is low --oe register power-up is low

Y1_internal_incoming_ext_ram_bus_data[3] = DFFE(ext_ram_bus_data[3], GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , );

--ext_ram_bus_data[3] is ext_ram_bus_data[3] at PIN_A6

--operation mode is bidir --input register power-up is low --output register power-up is low --oe register power-up is low

ext_ram_bus_data[3]_tri_out = TRI(Y1_d1_outgoing_ext_ram_bus_data[3], Y1L218Q);

ext_ram_bus_data[3] = BIDIR(ext_ram_bus_data[3]_tri_out);

--Y1_d1_outgoing_ext_ram_bus_data[3] is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_outgoing_ext_ram_bus_data[3] at PIN_A6

--operation mode is bidir --input register power-up is low --output register power-up is low --oe register power-up is low

Y1_d1_outgoing_ext_ram_bus_data[3] = DFFE(S1L2268, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , );

--Y1L218Q is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_in_a_write_cycle~_Duplicate_3 at PIN_A6

--operation mode is bidir --input register power-up is low --output register power-up is low --oe register power-up is low

Y1L218Q = DFFE(Y1L247, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , );

--Y1_internal_incoming_ext_ram_bus_data[2] is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|internal_incoming_ext_ram_bus_data[2] at PIN_B6

--operation mode is bidir --input register power-up is low --output register power-up is low --oe register power-up is low

Y1_internal_incoming_ext_ram_bus_data[2] = DFFE(ext_ram_bus_data[2], GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , );

--ext_ram_bus_data[2] is ext_ram_bus_data[2] at PIN_B6

--operation mode is bidir --input register power-up is low --output register power-up is low --oe register power-up is low

ext_ram_bus_data[2]_tri_out = TRI(Y1_d1_outgoing_ext_ram_bus_data[2], Y1L217Q);

ext_ram_bus_data[2] = BIDIR(ext_ram_bus_data[2]_tri_out);

--Y1_d1_outgoing_ext_ram_bus_data[2] is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_outgoing_ext_ram_bus_data[2] at PIN_B6

--operation mode is bidir --input register power-up is low --output register power-up is low --oe register power-up is low

Y1_d1_outgoing_ext_ram_bus_data[2] = DFFE(S1L2265, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , );

--Y1L217Q is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_in_a_write_cycle~_Duplicate_2 at PIN_B6

--operation mode is bidir --input register power-up is low --output register power-up is low --oe register power-up is low

Y1L217Q = DFFE(Y1L247, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , );

--Y1_internal_incoming_ext_ram_bus_data[1] is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|internal_incoming_ext_ram_bus_data[1] at PIN_E6

--operation mode is bidir --input register power-up is low --output register power-up is low --oe register power-up is low

Y1_internal_incoming_ext_ram_bus_data[1] = DFFE(ext_ram_bus_data[1], GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , );

--ext_ram_bus_data[1] is ext_ram_bus_data[1] at PIN_E6

--operation mode is bidir --input register power-up is low --output register power-up is low --oe register power-up is low

ext_ram_bus_data[1]_tri_out = TRI(Y1_d1_outgoing_ext_ram_bus_data[1], Y1L216Q);

ext_ram_bus_data[1] = BIDIR(ext_ram_bus_data[1]_tri_out);

--Y1_d1_outgoing_ext_ram_bus_data[1] is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_outgoing_ext_ram_bus_data[1] at PIN_E6

--operation mode is bidir --input register power-up is low --output register power-up is low --oe register power-up is low

Y1_d1_outgoing_ext_ram_bus_data[1] = DFFE(S1L2262, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , );

--Y1L216Q is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_in_a_write_cycle~_Duplicate_1 at PIN_E6

--operation mode is bidir --input register power-up is low --output register power-up is low --oe register power-up is low

Y1L216Q = DFFE(Y1L247, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , );

--Y1_internal_incoming_ext_ram_bus_data[0] is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|internal_incoming_ext_ram_bus_data[0] at PIN_C6

--operation mode is bidir --input register power-up is low --output register power-up is low --oe register power-up is low

Y1_internal_incoming_ext_ram_bus_data[0] = DFFE(ext_ram_bus_data[0], GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , );

--ext_ram_bus_data[0] is ext_ram_bus_data[0] at PIN_C6

--operation mode is bidir --input register power-up is low --output register power-up is low --oe register power-up is low

ext_ram_bus_data[0]_tri_out = TRI(Y1_d1_outgoing_ext_ram_bus_data[0], Y1_d1_in_a_write_cycle);

ext_ram_bus_data[0] = BIDIR(ext_ram_bus_data[0]_tri_out);

--Y1_d1_outgoing_ext_ram_bus_data[0] is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_outgoing_ext_ram_bus_data[0] at PIN_C6

--operation mode is bidir --input register power-up is low --output register power-up is low --oe register power-up is low

Y1_d1_outgoing_ext_ram_bus_data[0] = DFFE(S1L2259, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , );

--Y1_d1_in_a_write_cycle is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_in_a_write_cycle at PIN_C6

--operation mode is bidir --input register power-up is low --output register power-up is low --oe register power-up is low

Y1_d1_in_a_write_cycle = DFFE(Y1L247, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , );

--A1L134 is LCD_data_to_and_from_the_lcd_display~0 at PIN_V19

--operation mode is bidir

A1L134 = LCD_data_to_and_from_the_lcd_display[7];

--LCD_data_to_and_from_the_lcd_display[7] is LCD_data_to_and_from_the_lcd_display[7] at PIN_V19

--operation mode is bidir

LCD_data_to_and_from_the_lcd_display[7]_tri_out = TRI(S1_M_st_data[7], !S1L1726Q);

LCD_data_to_and_from_the_lcd_display[7] = BIDIR(LCD_data_to_and_from_the_lcd_display[7]_tri_out);

--A1L135 is LCD_data_to_and_from_the_lcd_display~1 at PIN_V18

--operation mode is bidir

A1L135 = LCD_data_to_and_from_the_lcd_display[6];

--LCD_data_to_and_from_the_lcd_display[6] is LCD_data_to_and_from_the_lcd_display[6] at PIN_V18

--operation mode is bidir

LCD_data_to_and_from_the_lcd_display[6]_tri_out = TRI(S1_M_st_data[6], !S1L1726Q);

LCD_data_to_and_from_the_lcd_display[6] = BIDIR(LCD_data_to_and_from_the_lcd_display[6]_tri_out);

--A1L136 is LCD_data_to_and_from_the_lcd_display~2 at PIN_W18

--operation mode is bidir

A1L136 = LCD_data_to_and_from_the_lcd_display[5];

--LCD_data_to_and_from_the_lcd_display[5] is LCD_data_to_and_from_the_lcd_display[5] at PIN_W18

--operation mode is bidir

LCD_data_to_and_from_the_lcd_display[5]_tri_out = TRI(S1_M_st_data[5], !S1L1726Q);

LCD_data_to_and_from_the_lcd_display[5] = BIDIR(LCD_data_to_and_from_the_lcd_display[5]_tri_out);

--A1L137 is LCD_data_to_and_from_the_lcd_display~3 at PIN_K15

--operation mode is bidir

A1L137 = LCD_data_to_and_from_the_lcd_display[4];

--LCD_data_to_and_from_the_lcd_display[4] is LCD_data_to_and_from_the_lcd_display[4] at PIN_K15

--operation mode is bidir

LCD_data_to_and_from_the_lcd_display[4]_tri_out = TRI(S1_M_st_data[4], !S1L1726Q);

LCD_data_to_and_from_the_lcd_display[4] = BIDIR(LCD_data_to_and_from_the_lcd_display[4]_tri_out);

--A1L138 is LCD_data_to_and_from_the_lcd_display~4 at PIN_J18

--operation mode is bidir

A1L138 = LCD_data_to_and_from_the_lcd_display[3];

--LCD_data_to_and_from_the_lcd_display[3] is LCD_data_to_and_from_the_lcd_display[3] at PIN_J18

--operation mode is bidir

LCD_data_to_and_from_the_lcd_display[3]_tri_out = TRI(S1_M_st_data[3], !S1L1726Q);

LCD_data_to_and_from_the_lcd_display[3] = BIDIR(LCD_data_to_and_from_the_lcd_display[3]_tri_out);

--A1L139 is LCD_data_to_and_from_the_lcd_display~5 at PIN_J17

--operation mode is bidir

A1L139 = LCD_data_to_and_from_the_lcd_display[2];

--LCD_data_to_and_from_the_lcd_display[2] is LCD_data_to_and_from_the_lcd_display[2] at PIN_J17

--operation mode is bidir

LCD_data_to_and_from_the_lcd_display[2]_tri_out = TRI(S1_M_st_data[2], !S1L1726Q);

LCD_data_to_and_from_the_lcd_display[2] = BIDIR(LCD_data_to_and_from_the_lcd_display[2]_tri_out);

--A1L140 is LCD_data_to_and_from_the_lcd_display~6 at PIN_J14

--operation mode is bidir

A1L140 = LCD_data_to_and_from_the_lcd_display[1];

--LCD_data_to_and_from_the_lcd_display[1] is LCD_data_to_and_from_the_lcd_display[1] at PIN_J14

--operation mode is bidir

LCD_data_to_and_from_the_lcd_display[1]_tri_out = TRI(S1_M_st_data[1], !S1L1726Q);

LCD_data_to_and_from_the_lcd_display[1] = BIDIR(LCD_data_to_and_from_the_lcd_display[1]_tri_out);

--A1L141 is LCD_data_to_and_from_the_lcd_display~7 at PIN_H14

--operation mode is bidir

A1L141 = LCD_data_to_and_from_the_lcd_display[0];

--LCD_data_to_and_from_the_lcd_display[0] is LCD_data_to_and_from_the_lcd_display[0] at PIN_H14

--operation mode is bidir

LCD_data_to_and_from_the_lcd_display[0]_tri_out = TRI(S1_M_st_data[0], !S1L1726Q);

LCD_data_to_and_from_the_lcd_display[0] = BIDIR(LCD_data_to_and_from_the_lcd_display[0]_tri_out);

--KB1_za_data[31] is std_1c20:inst|sdram:the_sdram|za_data[31] at PIN_V2

--operation mode is bidir --input register power-up is low --output register power-up is low

KB1_za_data[31] = DFFE(zs_dq_to_and_from_the_sdram[31], GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , );

--zs_dq_to_and_from_the_sdram[31] is zs_dq_to_and_from_the_sdram[31] at PIN_V2

--operation mode is bidir --input register power-up is low --output register power-up is low

zs_dq_to_and_from_the_sdram[31]_tri_out = TRI(KB1_m_data[31], KB1_oe);

zs_dq_to_and_from_the_sdram[31] = BIDIR(zs_dq_to_and_from_the_sdram[31]_tri_out);

--KB1_m_data[31] is std_1c20:inst|sdram:the_sdram|m_data[31] at PIN_V2

--operation mode is bidir --input register power-up is low --output register power-up is low

KB1_m_data[31] = DFFE(KB1L411, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , );

--KB1_za_data[30] is std_1c20:inst|sdram:the_sdram|za_data[30] at PIN_V3

--operation mode is bidir --input register power-up is low --output register power-up is low

KB1_za_data[30] = DFFE(zs_dq_to_and_from_the_sdram[30], GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , );

--zs_dq_to_and_from_the_sdram[30] is zs_dq_to_and_from_the_sdram[30] at PIN_V3

--operation mode is bidir --input register power-up is low --output register power-up is low

zs_dq_to_and_from_the_sdram[30]_tri_out = TRI(KB1_m_data[30], KB1_oe);

zs_dq_to_and_from_the_sdram[30] = BIDIR(zs_dq_to_and_from_the_sdram[30]_tri_out);

--KB1_m_data[30] is std_1c20:inst|sdram:the_sdram|m_data[30] at PIN_V3

--operation mode is bidir --input register power-up is low --output register power-up is low

KB1_m_data[30] = DFFE(KB1L406, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , );

--KB1_za_data[29] is std_1c20:inst|sdram:the_sdram|za_data[29] at PIN_U3

--operation mode is bidir --input register power-up is low --output register power-up is low

KB1_za_data[29] = DFFE(zs_dq_to_and_from_the_sdram[29], GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , );

--zs_dq_to_and_from_the_sdram[29] is zs_dq_to_and_from_the_sdram[29] at PIN_U3

--operation mode is bidir --input register power-up is low --output register power-up is low

zs_dq_to_and_from_the_sdram[29]_tri_out = TRI(KB1_m_data[29], KB1_oe);

zs_dq_to_and_from_the_sdram[29] = BIDIR(zs_dq_to_and_from_the_sdram[29]_tri_out);

--KB1_m_data[29] is std_1c20:inst|sdram:the_sdram|m_data[29] at PIN_U3

--operation mode is bidir --input register power-up is low --output register power-up is low

KB1_m_data[29] = DFFE(KB1L401, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , );

--KB1_za_data[28] is std_1c20:inst|sdram:the_sdram|za_data[28] at PIN_U2

--operation mode is bidir --input register power-up is low --output register power-up is low

KB1_za_data[28] = DFFE(zs_dq_to_and_from_the_sdram[28], GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , );

--zs_dq_to_and_from_the_sdram[28] is zs_dq_to_and_from_the_sdram[28] at PIN_U2

--operation mode is bidir --input register power-up is low --output register power-up is low

zs_dq_to_and_from_the_sdram[28]_tri_out = TRI(KB1_m_data[28], KB1_oe);

zs_dq_to_and_from_the_sdram[28] = BIDIR(zs_dq_to_and_from_the_sdram[28]_tri_out);

--KB1_m_data[28] is std_1c20:inst|sdram:the_sdram|m_data[28] at PIN_U2

--operation mode is bidir --input register power-up is low --output register power-up is low

KB1_m_data[28] = DFFE(KB1L396, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , );

--KB1_za_data[27] is std_1c20:inst|sdram:the_sdram|za_data[27] at PIN_U4

--operation mode is bidir --input register power-up is low --output register power-up is low

KB1_za_data[27] = DFFE(zs_dq_to_and_from_the_sdram[27], GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , );

--zs_dq_to_and_from_the_sdram[27] is zs_dq_to_and_from_the_sdram[27] at PIN_U4

--operation mode is bidir --input register power-up is low --output register power-up is low

zs_dq_to_and_from_the_sdram[27]_tri_out = TRI(KB1_m_data[27], KB1_oe);

zs_dq_to_and_from_the_sdram[27] = BIDIR(zs_dq_to_and_from_the_sdram[27]_tri_out);

--KB1_m_data[27] is std_1c20:inst|sdram:the_sdram|m_data[27] at PIN_U4

--operation mode is bidir --input register power-up is low --output register power-up is low

KB1_m_data[27] = DFFE(KB1L391, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , );

--KB1_za_data[26] is std_1c20:inst|sdram:the_sdram|za_data[26] at PIN_U1

--operation mode is bidir --input register power-up is low --output register power-up is low

KB1_za_data[26] = DFFE(zs_dq_to_and_from_the_sdram[26], GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , );

--zs_dq_to_and_from_the_sdram[26] is zs_dq_to_and_from_the_sdram[26] at PIN_U1

--operation mode is bidir --input register power-up is low --output register power-up is low

zs_dq_to_and_from_the_sdram[26]_tri_out = TRI(KB1_m_data[26], KB1_oe);

zs_dq_to_and_from_the_sdram[26] = BIDIR(zs_dq_to_and_from_the_sdram[26]_tri_out);

--KB1_m_data[26] is std_1c20:inst|sdram:the_sdram|m_data[26] at PIN_U1

--operation mode is bidir --input register power-up is low --output register power-up is low

KB1_m_data[26] = DFFE(KB1L386, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , );

--KB1_za_data[25] is std_1c20:inst|sdram:the_sdram|za_data[25] at PIN_T3

--operation mode is bidir --input register power-up is low --output register power-up is low

KB1_za_data[25] = DFFE(zs_dq_to_and_from_the_sdram[25], GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , );

--zs_dq_to_and_from_the_sdram[25] is zs_dq_to_and_from_the_sdram[25] at PIN_T3

--operation mode is bidir --input register power-up is low --output register power-up is low

zs_dq_to_and_from_the_sdram[25]_tri_out = TRI(KB1_m_data[25], KB1_oe);

zs_dq_to_and_from_the_sdram[25] = BIDIR(zs_dq_to_and_from_the_sdram[25]_tri_out);

--KB1_m_data[25] is std_1c20:inst|sdram:the_sdram|m_data[25] at PIN_T3

--operation mode is bidir --input register power-up is low --output register power-up is low

KB1_m_data[25] = DFFE(KB1L381, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , );

--KB1_za_data[24] is std_1c20:inst|sdram:the_sdram|za_data[24] at PIN_T2

--operation mode is bidir --input register power-up is low --output register power-up is low

KB1_za_data[24] = DFFE(zs_dq_to_and_from_the_sdram[24], GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , );

--zs_dq_to_and_from_the_sdram[24] is zs_dq_to_and_from_the_sdram[24] at PIN_T2

--operation mode is bidir --input register power-up is low --output register power-up is low

zs_dq_to_and_from_the_sdram[24]_tri_out = TRI(KB1_m_data[24], KB1_oe);

zs_dq_to_and_from_the_sdram[24] = BIDIR(zs_dq_to_and_from_the_sdram[24]_tri_out);

--KB1_m_data[24] is std_1c20:inst|sdram:the_sdram|m_data[24] at PIN_T2

--operation mode is bidir --input register power-up is low --output register power-up is low

KB1_m_data[24] = DFFE(KB1L376, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , );

--KB1_za_data[23] is std_1c20:inst|sdram:the_sdram|za_data[23] at PIN_T4

--operation mode is bidir --input register power-up is low --output register power-up is low

KB1_za_data[23] = DFFE(zs_dq_to_and_from_the_sdram[23], GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , );

--zs_dq_to_and_from_the_sdram[23] is zs_dq_to_and_from_the_sdram[23] at PIN_T4

--operation mode is bidir --input register power-up is low --output register power-up is low

zs_dq_to_and_from_the_sdram[23]_tri_out = TRI(KB1_m_data[23], KB1_oe);

zs_dq_to_and_from_the_sdram[23] = BIDIR(zs_dq_to_and_from_the_sdram[23]_tri_out);

--KB1_m_data[23] is std_1c20:inst|sdram:the_sdram|m_data[23] at PIN_T4

--operation mode is bidir --input register power-up is low --output register power-up is low

KB1_m_data[23] = DFFE(KB1L371, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , );

--KB1_za_data[22] is std_1c20:inst|sdram:the_sdram|za_data[22] at PIN_R4

--operation mode is bidir --input register power-up is low --output register power-up is low

KB1_za_data[22] = DFFE(zs_dq_to_and_from_the_sdram[22], GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , );

--zs_dq_to_and_from_the_sdram[22] is zs_dq_to_and_from_the_sdram[22] at PIN_R4

--operation mode is bidir --input register power-up is low --output register power-up is low

zs_dq_to_and_from_the_sdram[22]_tri_out = TRI(KB1_m_data[22], KB1_oe);

zs_dq_to_and_from_the_sdram[22] = BIDIR(zs_dq_to_and_from_the_sdram[22]_tri_out);

--KB1_m_data[22] is std_1c20:inst|sdram:the_sdram|m_data[22] at PIN_R4

--operation mode is bidir --input register power-up is low --output register power-up is low

KB1_m_data[22] = DFFE(KB1L366, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , );

--KB1_za_data[21] is std_1c20:inst|sdram:the_sdram|za_data[21] at PIN_R3

--operation mode is bidir --input register power-up is low --output register power-up is low

KB1_za_data[21] = DFFE(zs_dq_to_and_from_the_sdram[21], GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , );

--zs_dq_to_and_from_the_sdram[21] is zs_dq_to_and_from_the_sdram[21] at PIN_R3

--operation mode is bidir --input register power-up is low --output register power-up is low

zs_dq_to_and_from_the_sdram[21]_tri_out = TRI(KB1_m_data[21], KB1_oe);

zs_dq_to_and_from_the_sdram[21] = BIDIR(zs_dq_to_and_from_the_sdram[21]_tri_out);

--KB1_m_data[21] is std_1c20:inst|sdram:the_sdram|m_data[21] at PIN_R3

--operation mode is bidir --input register power-up is low --output register power-up is low

KB1_m_data[21] = DFFE(KB1L361, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , );

--KB1_za_data[20] is std_1c20:inst|sdram:the_sdram|za_data[20] at PIN_R5

--operation mode is bidir --input register power-up is low --output register power-up is low

KB1_za_data[20] = DFFE(zs_dq_to_and_from_the_sdram[20], GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , );

--zs_dq_to_and_from_the_sdram[20] is zs_dq_to_and_from_the_sdram[20] at PIN_R5

--operation mode is bidir --input register power-up is low --output register power-up is low

zs_dq_to_and_from_the_sdram[20]_tri_out = TRI(KB1_m_data[20], KB1_oe);

zs_dq_to_and_from_the_sdram[20] = BIDIR(zs_dq_to_and_from_the_sdram[20]_tri_out);

--KB1_m_data[20] is std_1c20:inst|sdram:the_sdram|m_data[20] at PIN_R5

--operation mode is bidir --input register power-up is low --output register power-up is low

KB1_m_data[20] = DFFE(KB1L356, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , );

--KB1_za_data[19] is std_1c20:inst|sdram:the_sdram|za_data[19] at PIN_R6

--operation mode is bidir --input register power-up is low --output register power-up is low

KB1_za_data[19] = DFFE(zs_dq_to_and_from_the_sdram[19], GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , );

--zs_dq_to_and_from_the_sdram[19] is zs_dq_to_and_from_the_sdram[19] at PIN_R6

--operation mode is bidir --input register power-up is low --output register power-up is low

zs_dq_to_and_from_the_sdram[19]_tri_out = TRI(KB1_m_data[19], KB1_oe);

zs_dq_to_and_from_the_sdram[19] = BIDIR(zs_dq_to_and_from_the_sdram[19]_tri_out);

--KB1_m_data[19] is std_1c20:inst|sdram:the_sdram|m_data[19] at PIN_R6

--operation mode is bidir --input register power-up is low --output register power-up is low

KB1_m_data[19] = DFFE(KB1L351, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , );

--KB1_za_data[18] is std_1c20:inst|sdram:the_sdram|za_data[18] at PIN_R2

--operation mode is bidir --input register power-up is low --output register power-up is low

KB1_za_data[18] = DFFE(zs_dq_to_and_from_the_sdram[18], GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , );

--zs_dq_to_and_from_the_sdram[18] is zs_dq_to_and_from_the_sdram[18] at PIN_R2

--operation mode is bidir --input register power-up is low --output register power-up is low

zs_dq_to_and_from_the_sdram[18]_tri_out = TRI(KB1_m_data[18], KB1_oe);

zs_dq_to_and_from_the_sdram[18] = BIDIR(zs_dq_to_and_from_the_sdram[18]_tri_out);

--KB1_m_data[18] is std_1c20:inst|sdram:the_sdram|m_data[18] at PIN_R2

--operation mode is bidir --input register power-up is low --output register power-up is low

KB1_m_data[18] = DFFE(KB1L344, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , );

--KB1_za_data[17] is std_1c20:inst|sdram:the_sdram|za_data[17] at PIN_R1

--operation mode is bidir --input register power-up is low --output register power-up is low

KB1_za_data[17] = DFFE(zs_dq_to_and_from_the_sdram[17], GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , );

--zs_dq_to_and_from_the_sdram[17] is zs_dq_to_and_from_the_sdram[17] at PIN_R1

--operation mode is bidir --input register power-up is low --output register power-up is low

zs_dq_to_and_from_the_sdram[17]_tri_out = TRI(KB1_m_data[17], KB1_oe);

zs_dq_to_and_from_the_sdram[17] = BIDIR(zs_dq_to_and_from_the_sdram[17]_tri_out);

--KB1_m_data[17] is std_1c20:inst|sdram:the_sdram|m_data[17] at PIN_R1

--operation mode is bidir --input register power-up is low --output register power-up is low

KB1_m_data[17] = DFFE(KB1L340, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , );

--KB1_za_data[16] is std_1c20:inst|sdram:the_sdram|za_data[16] at PIN_P4

--operation mode is bidir --input register power-up is low --output register power-up is low

KB1_za_data[16] = DFFE(zs_dq_to_and_from_the_sdram[16], GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , );

--zs_dq_to_and_from_the_sdram[16] is zs_dq_to_and_from_the_sdram[16] at PIN_P4

--operation mode is bidir --input register power-up is low --output register power-up is low

zs_dq_to_and_from_the_sdram[16]_tri_out = TRI(KB1_m_data[16], KB1_oe);

zs_dq_to_and_from_the_sdram[16] = BIDIR(zs_dq_to_and_from_the_sdram[16]_tri_out);

--KB1_m_data[16] is std_1c20:inst|sdram:the_sdram|m_data[16] at PIN_P4

--operation mode is bidir --input register power-up is low --output register power-up is low

KB1_m_data[16] = DFFE(KB1L335, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , );

--KB1_za_data[15] is std_1c20:inst|sdram:the_sdram|za_data[15] at PIN_P3

--operation mode is bidir --input register power-up is low --output register power-up is low

KB1_za_data[15] = DFFE(zs_dq_to_and_from_the_sdram[15], GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , );

--zs_dq_to_and_from_the_sdram[15] is zs_dq_to_and_from_the_sdram[15] at PIN_P3

--operation mode is bidir --input register power-up is low --output register power-up is low

zs_dq_to_and_from_the_sdram[15]_tri_out = TRI(KB1_m_data[15], KB1_oe);

zs_dq_to_and_from_the_sdram[15] = BIDIR(zs_dq_to_and_from_the_sdram[15]_tri_out);

--KB1_m_data[15] is std_1c20:inst|sdram:the_sdram|m_data[15] at PIN_P3

--operation mode is bidir --input register power-up is low --output register power-up is low

KB1_m_data[15] = DFFE(KB1L330, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , );

--KB1_za_data[14] is std_1c20:inst|sdram:the_sdram|za_data[14] at PIN_P5

--operation mode is bidir --input register power-up is low --output register power-up is low

KB1_za_data[14] = DFFE(zs_dq_to_and_from_the_sdram[14], GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , );

--zs_dq_to_and_from_the_sdram[14] is zs_dq_to_and_from_the_sdram[14] at PIN_P5

--operation mode is bidir --input register power-up is low --output register power-up is low

zs_dq_to_and_from_the_sdram[14]_tri_out = TRI(KB1_m_data[14], KB1_oe);

zs_dq_to_and_from_the_sdram[14] = BIDIR(zs_dq_to_and_from_the_sdram[14]_tri_out);

--KB1_m_data[14] is std_1c20:inst|sdram:the_sdram|m_data[14] at PIN_P5

--operation mode is bidir --input register power-up is low --output register power-up is low

KB1_m_data[14] = DFFE(KB1L325, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , );

--KB1_za_data[13] is std_1c20:inst|sdram:the_sdram|za_data[13] at PIN_P6

--operation mode is bidir --input register power-up is low --output register power-up is low

KB1_za_data[13] = DFFE(zs_dq_to_and_from_the_sdram[13], GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , );

--zs_dq_to_and_from_the_sdram[13] is zs_dq_to_and_from_the_sdram[13] at PIN_P6

--operation mode is bidir --input register power-up is low --output register power-up is low

zs_dq_to_and_from_the_sdram[13]_tri_out = TRI(KB1_m_data[13], KB1_oe);

zs_dq_to_and_from_the_sdram[13] = BIDIR(zs_dq_to_and_from_the_sdram[13]_tri_out);

--KB1_m_data[13] is std_1c20:inst|sdram:the_sdram|m_data[13] at PIN_P6

--operation mode is bidir --input register power-up is low --output register power-up is low

KB1_m_data[13] = DFFE(KB1L320, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , );

--KB1_za_data[12] is std_1c20:inst|sdram:the_sdram|za_data[12] at PIN_P1

--operation mode is bidir --input register power-up is low --output register power-up is low

KB1_za_data[12] = DFFE(zs_dq_to_and_from_the_sdram[12], GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , );

--zs_dq_to_and_from_the_sdram[12] is zs_dq_to_and_from_the_sdram[12] at PIN_P1

--operation mode is bidir --input register power-up is low --output register power-up is low

zs_dq_to_and_from_the_sdram[12]_tri_out = TRI(KB1_m_data[12], KB1_oe);

zs_dq_to_and_from_the_sdram[12] = BIDIR(zs_dq_to_and_from_the_sdram[12]_tri_out);

--KB1_m_data[12] is std_1c20:inst|sdram:the_sdram|m_data[12] at PIN_P1

--operation mode is bidir --input register power-up is low --output register power-up is low

KB1_m_data[12] = DFFE(KB1L315, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , );

--KB1_za_data[11] is std_1c20:inst|sdram:the_sdram|za_data[11] at PIN_P2

--operation mode is bidir --input register power-up is low --output register power-up is low

KB1_za_data[11] = DFFE(zs_dq_to_and_from_the_sdram[11], GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , );

--zs_dq_to_and_from_the_sdram[11] is zs_dq_to_and_from_the_sdram[11] at PIN_P2

--operation mode is bidir --input register power-up is low --output register power-up is low

zs_dq_to_and_from_the_sdram[11]_tri_out = TRI(KB1_m_data[11], KB1_oe);

zs_dq_to_and_from_the_sdram[11] = BIDIR(zs_dq_to_and_from_the_sdram[11]_tri_out);

--KB1_m_data[11] is std_1c20:inst|sdram:the_sdram|m_data[11] at PIN_P2

--operation mode is bidir --input register power-up is low --output register power-up is low

KB1_m_data[11] = DFFE(KB1L310, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , );

--KB1_za_data[10] is std_1c20:inst|sdram:the_sdram|za_data[10] at PIN_P7

--operation mode is bidir --input register power-up is low --output register power-up is low

KB1_za_data[10] = DFFE(zs_dq_to_and_from_the_sdram[10], GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , );

--zs_dq_to_and_from_the_sdram[10] is zs_dq_to_and_from_the_sdram[10] at PIN_P7

--operation mode is bidir --input register power-up is low --output register power-up is low

zs_dq_to_and_from_the_sdram[10]_tri_out = TRI(KB1_m_data[10], KB1_oe);

zs_dq_to_and_from_the_sdram[10] = BIDIR(zs_dq_to_and_from_the_sdram[10]_tri_out);

--KB1_m_data[10] is std_1c20:inst|sdram:the_sdram|m_data[10] at PIN_P7

--operation mode is bidir --input register power-up is low --output register power-up is low

KB1_m_data[10] = DFFE(KB1L305, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , );

--KB1_za_data[9] is std_1c20:inst|sdram:the_sdram|za_data[9] at PIN_N7

--operation mode is bidir --input register power-up is low --output register power-up is low

KB1_za_data[9] = DFFE(zs_dq_to_and_from_the_sdram[9], GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , );

--zs_dq_to_and_from_the_sdram[9] is zs_dq_to_and_from_the_sdram[9] at PIN_N7

--operation mode is bidir --input register power-up is low --output register power-up is low

zs_dq_to_and_from_the_sdram[9]_tri_out = TRI(KB1_m_data[9], KB1_oe);

zs_dq_to_and_from_the_sdram[9] = BIDIR(zs_dq_to_and_from_the_sdram[9]_tri_out);

--KB1_m_data[9] is std_1c20:inst|sdram:the_sdram|m_data[9] at PIN_N7

--operation mode is bidir --input register power-up is low --output register power-up is low

KB1_m_data[9] = DFFE(KB1L300, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , );

--KB1_za_data[8] is std_1c20:inst|sdram:the_sdram|za_data[8] at PIN_N5

--operation mode is bidir --input register power-up is low --output register power-up is low

KB1_za_data[8] = DFFE(zs_dq_to_and_from_the_sdram[8], GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , );

--zs_dq_to_and_from_the_sdram[8] is zs_dq_to_and_from_the_sdram[8] at PIN_N5

--operation mode is bidir --input register power-up is low --output register power-up is low

zs_dq_to_and_from_the_sdram[8]_tri_out = TRI(KB1_m_data[8], KB1_oe);

zs_dq_to_and_from_the_sdram[8] = BIDIR(zs_dq_to_and_from_the_sdram[8]_tri_out);

--KB1_m_data[8] is std_1c20:inst|sdram:the_sdram|m_data[8] at PIN_N5

--operation mode is bidir --input register power-up is low --output register power-up is low

KB1_m_data[8] = DFFE(KB1L295, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , );

--KB1_za_data[7] is std_1c20:inst|sdram:the_sdram|za_data[7] at PIN_N3

--operation mode is bidir --input register power-up is low --output register power-up is low

KB1_za_data[7] = DFFE(zs_dq_to_and_from_the_sdram[7], GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , );

--zs_dq_to_and_from_the_sdram[7] is zs_dq_to_and_from_the_sdram[7] at PIN_N3

--operation mode is bidir --input register power-up is low --output register power-up is low

zs_dq_to_and_from_the_sdram[7]_tri_out = TRI(KB1_m_data[7], KB1_oe);

zs_dq_to_and_from_the_sdram[7] = BIDIR(zs_dq_to_and_from_the_sdram[7]_tri_out);

--KB1_m_data[7] is std_1c20:inst|sdram:the_sdram|m_data[7] at PIN_N3

--operation mode is bidir --input register power-up is low --output register power-up is low

KB1_m_data[7] = DFFE(KB1L290, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , );

--KB1_za_data[6] is std_1c20:inst|sdram:the_sdram|za_data[6] at PIN_N4

--operation mode is bidir --input register power-up is low --output register power-up is low

KB1_za_data[6] = DFFE(zs_dq_to_and_from_the_sdram[6], GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , );

--zs_dq_to_and_from_the_sdram[6] is zs_dq_to_and_from_the_sdram[6] at PIN_N4

--operation mode is bidir --input register power-up is low --output register power-up is low

zs_dq_to_and_from_the_sdram[6]_tri_out = TRI(KB1_m_data[6], KB1_oe);

zs_dq_to_and_from_the_sdram[6] = BIDIR(zs_dq_to_and_from_the_sdram[6]_tri_out);

--KB1_m_data[6] is std_1c20:inst|sdram:the_sdram|m_data[6] at PIN_N4

--operation mode is bidir --input register power-up is low --output register power-up is low

KB1_m_data[6] = DFFE(KB1L285, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , );

--KB1_za_data[5] is std_1c20:inst|sdram:the_sdram|za_data[5] at PIN_N2

--operation mode is bidir --input register power-up is low --output register power-up is low

KB1_za_data[5] = DFFE(zs_dq_to_and_from_the_sdram[5], GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , );

--zs_dq_to_and_from_the_sdram[5] is zs_dq_to_and_from_the_sdram[5] at PIN_N2

--operation mode is bidir --input register power-up is low --output register power-up is low

zs_dq_to_and_from_the_sdram[5]_tri_out = TRI(KB1_m_data[5], KB1_oe);

zs_dq_to_and_from_the_sdram[5] = BIDIR(zs_dq_to_and_from_the_sdram[5]_tri_out);

--KB1_m_data[5] is std_1c20:inst|sdram:the_sdram|m_data[5] at PIN_N2

--operation mode is bidir --input register power-up is low --output register power-up is low

KB1_m_data[5] = DFFE(KB1L280, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , );

--KB1_za_data[4] is std_1c20:inst|sdram:the_sdram|za_data[4] at PIN_N1

--operation mode is bidir --input register power-up is low --output register power-up is low

KB1_za_data[4] = DFFE(zs_dq_to_and_from_the_sdram[4], GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , );

--zs_dq_to_and_from_the_sdram[4] is zs_dq_to_and_from_the_sdram[4] at PIN_N1

--operation mode is bidir --input register power-up is low --output register power-up is low

zs_dq_to_and_from_the_sdram[4]_tri_out = TRI(KB1_m_data[4], KB1_oe);

zs_dq_to_and_from_the_sdram[4] = BIDIR(zs_dq_to_and_from_the_sdram[4]_tri_out);

--KB1_m_data[4] is std_1c20:inst|sdram:the_sdram|m_data[4] at PIN_N1

--operation mode is bidir --input register power-up is low --output register power-up is low

KB1_m_data[4] = DFFE(KB1L275, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , );

--KB1_za_data[3] is std_1c20:inst|sdram:the_sdram|za_data[3] at PIN_N6

--operation mode is bidir --input register power-up is low --output register power-up is low

KB1_za_data[3] = DFFE(zs_dq_to_and_from_the_sdram[3], GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , );

--zs_dq_to_and_from_the_sdram[3] is zs_dq_to_and_from_the_sdram[3] at PIN_N6

--operation mode is bidir --input register power-up is low --output register power-up is low

zs_dq_to_and_from_the_sdram[3]_tri_out = TRI(KB1_m_data[3], KB1_oe);

zs_dq_to_and_from_the_sdram[3] = BIDIR(zs_dq_to_and_from_the_sdram[3]_tri_out);

--KB1_m_data[3] is std_1c20:inst|sdram:the_sdram|m_data[3] at PIN_N6

--operation mode is bidir --input register power-up is low --output register power-up is low

KB1_m_data[3] = DFFE(KB1L271, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , );

--KB1_za_data[2] is std_1c20:inst|sdram:the_sdram|za_data[2] at PIN_M7

--operation mode is bidir --input register power-up is low --output register power-up is low

KB1_za_data[2] = DFFE(zs_dq_to_and_from_the_sdram[2], GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , );

--zs_dq_to_and_from_the_sdram[2] is zs_dq_to_and_from_the_sdram[2] at PIN_M7

--operation mode is bidir --input register power-up is low --output register power-up is low

zs_dq_to_and_from_the_sdram[2]_tri_out = TRI(KB1_m_data[2], KB1_oe);

zs_dq_to_and_from_the_sdram[2] = BIDIR(zs_dq_to_and_from_the_sdram[2]_tri_out);

--KB1_m_data[2] is std_1c20:inst|sdram:the_sdram|m_data[2] at PIN_M7

--operation mode is bidir --input register power-up is low --output register power-up is low

KB1_m_data[2] = DFFE(KB1L267, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , );

--KB1_za_data[1] is std_1c20:inst|sdram:the_sdram|za_data[1] at PIN_M3

--operation mode is bidir --input register power-up is low --output register power-up is low

KB1_za_data[1] = DFFE(zs_dq_to_and_from_the_sdram[1], GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , );

--zs_dq_to_and_from_the_sdram[1] is zs_dq_to_and_from_the_sdram[1] at PIN_M3

--operation mode is bidir --input register power-up is low --output register power-up is low

zs_dq_to_and_from_the_sdram[1]_tri_out = TRI(KB1_m_data[1], KB1_oe);

zs_dq_to_and_from_the_sdram[1] = BIDIR(zs_dq_to_and_from_the_sdram[1]_tri_out);

--KB1_m_data[1] is std_1c20:inst|sdram:the_sdram|m_data[1] at PIN_M3

--operation mode is bidir --input register power-up is low --output register power-up is low

KB1_m_data[1] = DFFE(KB1L262, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , );

--KB1_za_data[0] is std_1c20:inst|sdram:the_sdram|za_data[0] at PIN_M5

--operation mode is bidir --input register power-up is low --output register power-up is low

KB1_za_data[0] = DFFE(zs_dq_to_and_from_the_sdram[0], GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , );

--zs_dq_to_and_from_the_sdram[0] is zs_dq_to_and_from_the_sdram[0] at PIN_M5

--operation mode is bidir --input register power-up is low --output register power-up is low

zs_dq_to_and_from_the_sdram[0]_tri_out = TRI(KB1_m_data[0], KB1_oe);

zs_dq_to_and_from_the_sdram[0] = BIDIR(zs_dq_to_and_from_the_sdram[0]_tri_out);

--KB1_m_data[0] is std_1c20:inst|sdram:the_sdram|m_data[0] at PIN_M5

--operation mode is bidir --input register power-up is low --output register power-up is low

KB1_m_data[0] = DFFE(KB1L257, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , );

--S1L1531 is std_1c20:inst|cpu:the_cpu|ic_fill_ap_offset[0]~$wirecell at LC_X26_Y21_N2

--operation mode is normal

S1L1531 = AMPP_FUNCTION(S1_ic_fill_ap_offset[0]);

--S1L2117Q is std_1c20:inst|cpu:the_cpu|M_ienable_reg[6]~679 at LC_X35_Y19_N6

--operation mode is normal

S1L2117Q = AMPP_FUNCTION(QC2__clk0, S1L2121, S1L26, S1L27, S1L2119, F1_data_out, S1L2099);

--S1L2110Q is std_1c20:inst|cpu:the_cpu|M_ienable_reg[5]~681 at LC_X34_Y19_N4

--operation mode is normal

S1L2110Q = AMPP_FUNCTION(QC2__clk0, S1L2112, S1L2114, S1L32, S1L33, F1_data_out, S1L2099);

--S1L2107Q is std_1c20:inst|cpu:the_cpu|M_ienable_reg[4]~683 at LC_X36_Y20_N6

--operation mode is normal

S1L2107Q = AMPP_FUNCTION(QC2__clk0, S1_E_ctrl_dst_data_sel_cmp, S1_E_control_rd_data_without_mmu_regs[4], S1_E_ctrl_rdctl_inst, S1L31, F1_data_out, S1L2099);

--S1L2104Q is std_1c20:inst|cpu:the_cpu|M_ienable_reg[3]~685 at LC_X36_Y19_N3

--operation mode is normal

S1L2104Q = AMPP_FUNCTION(QC2__clk0, S1_E_control_rd_data_without_mmu_regs[3], S1_E_ctrl_rdctl_inst, S1_E_ctrl_dst_data_sel_cmp, S1L6, F1_data_out, S1L2099);

--S1L2101Q is std_1c20:inst|cpu:the_cpu|M_ienable_reg[2]~687 at LC_X36_Y19_N1

--operation mode is normal

S1L2101Q = AMPP_FUNCTION(QC2__clk0, S1_E_ctrl_dst_data_sel_cmp, S1_E_control_rd_data_without_mmu_regs[2], S1_E_ctrl_rdctl_inst, S1L3, F1_data_out, S1L2099);

--DE1L160Q is std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|EOP~172 at LC_X36_Y28_N7

--operation mode is normal

DE1L160Q_lut_out = !DE1L138Q & DE1L155 & DE1L154 & !DE1L135Q;

DE1L160Q = DFFEAS(DE1L160Q_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--S1L1368Q is std_1c20:inst|cpu:the_cpu|i_readdata_d1[1]~128 at LC_X42_Y19_N5

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

S1L1368Q = AMPP_FUNCTION(QC2__clk0, FD1L19Q, F1_data_out, GND);

--S1L1361Q is std_1c20:inst|cpu:the_cpu|i_readdata_d1[0]~131 at LC_X44_Y19_N2

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

S1L1361Q = AMPP_FUNCTION(QC2__clk0, FD1L14Q, F1_data_out, GND);

--S1L1389Q is std_1c20:inst|cpu:the_cpu|i_readdata_d1[3]~134 at LC_X44_Y19_N9

--operation mode is normal

S1L1389Q = AMPP_FUNCTION(QC2__clk0, FD1L25Q, F1_data_out);

--S1L1375Q is std_1c20:inst|cpu:the_cpu|i_readdata_d1[2]~137 at LC_X44_Y19_N0

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

S1L1375Q = AMPP_FUNCTION(QC2__clk0, FD1L22Q, F1_data_out, GND);

--S1L1501 is std_1c20:inst|cpu:the_cpu|ic_fill_ap_cnt[0]~44 at LC_X26_Y24_N5

--operation mode is normal

S1L1501 = AMPP_FUNCTION(S1L1498Q, U1L14Q, S1L1701Q, S1_D_ic_fill_starting_d1);

--S1L1497Q is std_1c20:inst|cpu:the_cpu|ic_fill_ap_cnt[0]~23 at LC_X26_Y24_N5

--operation mode is normal

S1L1497Q = AMPP_FUNCTION(QC2__clk0, S1L1498Q, U1L14Q, S1L1701Q, S1_D_ic_fill_starting_d1, F1_data_out);

--S1L1701Q is std_1c20:inst|cpu:the_cpu|internal_i_read~3 at LC_X26_Y24_N4

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

S1L1701Q = AMPP_FUNCTION(QC2__clk0, S1L1526, F1_data_out, GND);

--Y1L910Q is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|last_cycle_cpu_data_master_granted_slave_ext_ram_s1~4 at LC_X34_Y21_N1

--operation mode is normal

Y1L910Q_lut_out = S1L1782Q;

Y1L910Q = DFFEAS(Y1L910Q_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--Y1L512 is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_avalon_slave_arb_addend[0]~727 at LC_X31_Y21_N1

--operation mode is normal

Y1L512 = Y1L721 # !Y1L181 & (Y1L372 # Y1L204);

--Y1L205Q is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_ext_ram_bus_avalon_slave_end_xfer~7 at LC_X31_Y21_N1

--operation mode is normal

Y1L205Q = DFFEAS(Y1L512, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--Y1L510 is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_avalon_slave_arb_addend[0]~725 at LC_X30_Y25_N4

--operation mode is normal

Y1L510 = Y1L711 & Y1L799 # !Y1L711 & (Y1L792);

--Y1L590Q is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_avalon_slave_arb_addend[0]~871 at LC_X30_Y25_N4

--operation mode is normal

Y1L590Q = DFFEAS(Y1L510, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--S1L1713 is std_1c20:inst|cpu:the_cpu|M_alu_result[0]~_DUP_COMB at LC_X33_Y14_N7

--operation mode is normal

S1L1713 = AMPP_FUNCTION(S1L2013Q, S1L2043Q, S1L2044Q);

--S1L2282 is std_1c20:inst|cpu:the_cpu|M_st_data[9]~_DUP_COMB at LC_X44_Y16_N3

--operation mode is normal

S1L2282 = AMPP_FUNCTION(S1_E_src2_hazard_M, S1_E_src2_prelim[1], S1L2395);

--S1L2295 is std_1c20:inst|cpu:the_cpu|M_st_data[11]~_DUP_COMB at LC_X42_Y17_N5

--operation mode is normal

S1L2295 = AMPP_FUNCTION(S1_E_src2_hazard_M, S1_E_src2_prelim[3], S1L2401);

--S1L2314 is std_1c20:inst|cpu:the_cpu|M_st_data[14]~_DUP_COMB at LC_X42_Y17_N1

--operation mode is normal

S1L2314 = AMPP_FUNCTION(S1_E_src2_hazard_M, S1L2410, S1_E_src2_prelim[6]);

--Y1L742 is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_avalon_slave_saved_chosen_master_vector[0]~_DUP_COMB at LC_X30_Y22_N7

--operation mode is normal

Y1L742 = Y1L874 & (Y1L25 # !Y1L5);

--Y1L974Q is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|last_cycle_cpu_instruction_master_granted_slave_lan91c111_s1~10 at LC_X30_Y22_N7

--operation mode is normal

Y1L974Q = DFFEAS(Y1L742, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--Y1L755 is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_avalon_slave_saved_chosen_master_vector[1]~_DUP_COMB at LC_X29_Y22_N5

--operation mode is normal

Y1L755 = Y1L112 & (Y1L28 # Y1L31);

--Y1L735Q is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_avalon_slave_saved_chosen_master_vector[0]~707 at LC_X29_Y22_N5

--operation mode is normal

Y1L735Q = DFFEAS(Y1L755, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--DE1L163Q is std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|EOP~175 at LC_X37_Y28_N7

--operation mode is normal

DE1L163Q_lut_out = DE1L285 & X1L28 & !X1L33 & !DE1L21;

DE1L163Q = DFFEAS(DE1L163Q_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--DE1L164Q is std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|EOP~176 at LC_X35_Y27_N7

--operation mode is normal

DE1L164Q_lut_out = !DE1L21 & !X1L33 & !X1L28 & DE1_p1_rd_strobe;

DE1L164Q = DFFEAS(DE1L164Q_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--V1L13 is std_1c20:inst|cpu_jtag_debug_module_arbitrator:the_cpu_jtag_debug_module|cpu_instruction_master_qualified_request_cpu_jtag_debug_module~_DUP_COMB at LC_X34_Y24_N4

--operation mode is normal

V1L13 = !V1L58 & S1L1593Q & X1L16;

--S1L1450Q is std_1c20:inst|cpu:the_cpu|i_readdata_d1[10]~142 at LC_X34_Y24_N4

--operation mode is normal

S1L1450Q = AMPP_FUNCTION(QC2__clk0, V1L58, S1L1593Q, X1L16, F1_data_out);

--Y1L799 is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_avalon_slave_saved_chosen_master_vector[4]~_DUP_COMB at LC_X31_Y23_N0

--operation mode is normal

Y1L799 = Y1L1007 & (Y1L46 # Y1L49);

--Y1L656Q is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_avalon_slave_arb_addend[4]~862 at LC_X31_Y23_N0

--operation mode is normal

Y1L656Q = DFFEAS(Y1L799, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--Y1L770 is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_avalon_slave_saved_chosen_master_vector[2]~_DUP_COMB at LC_X29_Y23_N5

--operation mode is normal

Y1L770 = U1L223 & (Y1L43 # Y1L40);

--Y1L751Q is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_avalon_slave_saved_chosen_master_vector[1]~705 at LC_X29_Y23_N5

--operation mode is normal

Y1L751Q = DFFEAS(Y1L770, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--Y1L787 is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_avalon_slave_saved_chosen_master_vector[3]~_DUP_COMB at LC_X29_Y25_N3

--operation mode is normal

Y1L787 = Y1L100 & (Y1L37 # Y1L34);

--Y1L631Q is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_avalon_slave_arb_addend[3]~867 at LC_X29_Y25_N3

--operation mode is normal

Y1L631Q = DFFEAS(Y1L787, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--Y1L679Q is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_avalon_slave_arb_addend[5]~865 at LC_X32_Y22_N1

--operation mode is normal

Y1L679Q_lut_out = Y1L104 & (Y1L51 # Y1L53);

Y1L679Q = DFFEAS(Y1L679Q_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--Y1L208 is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_ext_ram_bus_avalon_slave_end_xfer~_DUP_COMB at LC_X30_Y24_N2

--operation mode is normal

Y1L208 = Y1L721 # !Y1L181 & (Y1L372 # Y1L204);

--Y1L653Q is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_avalon_slave_arb_addend[4]~844 at LC_X30_Y24_N2

--operation mode is normal

Y1L653Q = DFFEAS(Y1L208, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--Y1L602 is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_avalon_slave_arb_addend[1]~_DUP_COMB at LC_X32_Y25_N1

--operation mode is normal

Y1L602 = Y1L557 & Y1L533 # !Y1L557 & (Y1L529);

--Y1L563Q is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_avalon_slave_arb_addend[0]~800 at LC_X32_Y25_N1

--operation mode is normal

Y1L563Q = DFFEAS(Y1L602, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--Y1L633 is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_avalon_slave_arb_addend[3]~_DUP_COMB at LC_X32_Y25_N7

--operation mode is normal

Y1L633 = Y1L557 & Y1L540 # !Y1L557 & (Y1L565);

--Y1L566Q is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_avalon_slave_arb_addend[0]~803 at LC_X32_Y25_N7

--operation mode is normal

Y1L566Q = DFFEAS(Y1L633, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--Y1L613 is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_avalon_slave_arb_addend[2]~_DUP_COMB at LC_X32_Y25_N0

--operation mode is normal

Y1L613 = Y1L557 & (Y1L547) # !Y1L557 & Y1L568;

--Y1L569Q is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_avalon_slave_arb_addend[0]~806 at LC_X32_Y25_N0

--operation mode is normal

Y1L569Q = DFFEAS(Y1L613, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--Y1L662 is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_avalon_slave_arb_addend[4]~_DUP_COMB at LC_X32_Y25_N8

--operation mode is normal

Y1L662 = Y1L557 & Y1L570 # !Y1L557 & (Y1L571);

--Y1L572Q is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_avalon_slave_arb_addend[0]~809 at LC_X32_Y25_N8

--operation mode is normal

Y1L572Q = DFFEAS(Y1L662, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--S1L2356 is std_1c20:inst|cpu:the_cpu|M_st_data[22]~_DUP_COMB_113 at LC_X43_Y14_N2

--operation mode is normal

S1L2356 = AMPP_FUNCTION(S1_E_src2_prelim[22], S1L2458, S1_E_src2_hazard_M);

--S1L2355Q is std_1c20:inst|cpu:the_cpu|M_st_data[22]~113 at LC_X42_Y17_N7

--operation mode is normal

S1L2355Q = AMPP_FUNCTION(QC2__clk0, S1_W_stall, S1L2355Q, S1L2358, F1_data_out);

--S1L2277 is std_1c20:inst|cpu:the_cpu|M_st_data[8]~_DUP_COMB_116 at LC_X37_Y16_N1

--operation mode is normal

S1L2277 = AMPP_FUNCTION(S1_E_src2_hazard_M, S1L2392, S1_E_src2_prelim[0]);

--S1L2275Q is std_1c20:inst|cpu:the_cpu|M_st_data[8]~116 at LC_X42_Y19_N7

--operation mode is normal

S1L2275Q = AMPP_FUNCTION(QC2__clk0, S1L2275Q, S1L2279, S1_W_stall, F1_data_out);

--S1L2283 is std_1c20:inst|cpu:the_cpu|M_st_data[9]~_DUP_COMB_119 at LC_X40_Y16_N1

--operation mode is normal

S1L2283 = AMPP_FUNCTION(S1_E_src2_hazard_M, S1_E_src2_prelim[1], S1L2395);

--S1L2281Q is std_1c20:inst|cpu:the_cpu|M_st_data[9]~119 at LC_X42_Y18_N8

--operation mode is normal

S1L2281Q = AMPP_FUNCTION(QC2__clk0, S1_W_stall, S1L2281Q, S1L2286, F1_data_out);

--S1L2321 is std_1c20:inst|cpu:the_cpu|M_st_data[15]~_DUP_COMB_122 at LC_X42_Y18_N5

--operation mode is normal

S1L2321 = AMPP_FUNCTION(S1_E_src2_prelim[7], S1_E_src2_hazard_M, S1L2413);

--S1L2319Q is std_1c20:inst|cpu:the_cpu|M_st_data[15]~122 at LC_X42_Y19_N1

--operation mode is normal

S1L2319Q = AMPP_FUNCTION(QC2__clk0, S1L2319Q, S1L2323, S1_W_stall, F1_data_out);

--S1L2361 is std_1c20:inst|cpu:the_cpu|M_st_data[23]~_DUP_COMB_125 at LC_X43_Y14_N9

--operation mode is normal

S1L2361 = AMPP_FUNCTION(S1_E_src2_prelim[23], S1L2461, S1_E_src2_hazard_M);

--S1L2360Q is std_1c20:inst|cpu:the_cpu|M_st_data[23]~125 at LC_X42_Y18_N9

--operation mode is normal

S1L2360Q = AMPP_FUNCTION(QC2__clk0, S1_W_stall, S1L2360Q, S1L2363, F1_data_out);

--S1L2346 is std_1c20:inst|cpu:the_cpu|M_st_data[20]~_DUP_COMB_128 at LC_X39_Y14_N7

--operation mode is normal

S1L2346 = AMPP_FUNCTION(S1L2452, S1_E_src2_hazard_M, S1_E_src2_prelim[20]);

--S1L2345Q is std_1c20:inst|cpu:the_cpu|M_st_data[20]~128 at LC_X39_Y14_N6

--operation mode is normal

S1L2345Q = AMPP_FUNCTION(QC2__clk0, S1L2345Q, S1_W_stall, S1L2348, F1_data_out);

--S1L2331 is std_1c20:inst|cpu:the_cpu|M_st_data[17]~_DUP_COMB_131 at LC_X42_Y14_N7

--operation mode is normal

S1L2331 = AMPP_FUNCTION(S1_E_src2_prelim[17], S1_E_src2_hazard_M, S1L2443);

--S1L2330Q is std_1c20:inst|cpu:the_cpu|M_st_data[17]~131 at LC_X43_Y18_N5

--operation mode is normal

S1L2330Q = AMPP_FUNCTION(QC2__clk0, S1L2330Q, S1_W_stall, S1L2333, F1_data_out);

--S1L2326 is std_1c20:inst|cpu:the_cpu|M_st_data[16]~_DUP_COMB_134 at LC_X43_Y16_N3

--operation mode is normal

S1L2326 = AMPP_FUNCTION(S1_E_src2_hazard_M, S1_E_src2_prelim[16], S1L2440);

--S1L2325Q is std_1c20:inst|cpu:the_cpu|M_st_data[16]~134 at LC_X43_Y16_N2

--operation mode is normal

S1L2325Q = AMPP_FUNCTION(QC2__clk0, S1_W_stall, S1L2328, S1L2325Q, F1_data_out);

--S1L2336 is std_1c20:inst|cpu:the_cpu|M_st_data[18]~_DUP_COMB_137 at LC_X41_Y15_N1

--operation mode is normal

S1L2336 = AMPP_FUNCTION(S1L2446, S1_E_src2_hazard_M, S1_E_src2_prelim[18]);

--S1L2335Q is std_1c20:inst|cpu:the_cpu|M_st_data[18]~137 at LC_X42_Y14_N3

--operation mode is normal

S1L2335Q = AMPP_FUNCTION(QC2__clk0, S1L2335Q, S1_W_stall, S1L2338, F1_data_out);

--S1L2341 is std_1c20:inst|cpu:the_cpu|M_st_data[19]~_DUP_COMB_140 at LC_X43_Y16_N0

--operation mode is normal

S1L2341 = AMPP_FUNCTION(S1_E_src2_hazard_M, S1L2449, S1_E_src2_prelim[19]);

--S1L2340Q is std_1c20:inst|cpu:the_cpu|M_st_data[19]~140 at LC_X43_Y18_N8

--operation mode is normal

S1L2340Q = AMPP_FUNCTION(QC2__clk0, S1_W_stall, S1L2340Q, S1L2343, F1_data_out);

--S1L2351 is std_1c20:inst|cpu:the_cpu|M_st_data[21]~_DUP_COMB_143 at LC_X43_Y14_N4

--operation mode is normal

S1L2351 = AMPP_FUNCTION(S1_E_src2_hazard_M, S1L2455, S1_E_src2_prelim[21]);

--S1L2350Q is std_1c20:inst|cpu:the_cpu|M_st_data[21]~143 at LC_X43_Y18_N4

--operation mode is normal

S1L2350Q = AMPP_FUNCTION(QC2__clk0, S1_W_stall, S1L2350Q, S1L2353, F1_data_out);

--S1L2296 is std_1c20:inst|cpu:the_cpu|M_st_data[11]~_DUP_COMB_146 at LC_X39_Y12_N2

--operation mode is normal

S1L2296 = AMPP_FUNCTION(S1_E_src2_hazard_M, S1_E_src2_prelim[3], S1L2401);

--S1L2294Q is std_1c20:inst|cpu:the_cpu|M_st_data[11]~146 at LC_X42_Y15_N7

--operation mode is normal

S1L2294Q = AMPP_FUNCTION(QC2__clk0, S1_W_stall, S1L2294Q, S1L2299, F1_data_out);

--S1L2313Q is std_1c20:inst|cpu:the_cpu|M_st_data[14]~149 at LC_X37_Y19_N5

--operation mode is normal

S1L2313Q = AMPP_FUNCTION(QC2__clk0, S1L2313Q, S1_W_stall, S1L2317, F1_data_out);

--S1L2309 is std_1c20:inst|cpu:the_cpu|M_st_data[13]~_DUP_COMB_152 at LC_X40_Y18_N2

--operation mode is normal

S1L2309 = AMPP_FUNCTION(S1_E_src2_hazard_M, S1_E_src2_prelim[5], S1L2407);

--S1L2307Q is std_1c20:inst|cpu:the_cpu|M_st_data[13]~152 at LC_X40_Y18_N5

--operation mode is normal

S1L2307Q = AMPP_FUNCTION(QC2__clk0, S1_W_stall, S1L2307Q, S1L2311, F1_data_out);

--S1L2303 is std_1c20:inst|cpu:the_cpu|M_st_data[12]~_DUP_COMB_155 at LC_X42_Y15_N5

--operation mode is normal

S1L2303 = AMPP_FUNCTION(S1_E_src2_prelim[4], S1_E_src2_hazard_M, S1L2404);

--S1L2301Q is std_1c20:inst|cpu:the_cpu|M_st_data[12]~155 at LC_X42_Y16_N1

--operation mode is normal

S1L2301Q = AMPP_FUNCTION(QC2__clk0, S1L2301Q, S1_W_stall, S1L2305, F1_data_out);

--S1L2290 is std_1c20:inst|cpu:the_cpu|M_st_data[10]~_DUP_COMB_158 at LC_X40_Y18_N6

--operation mode is normal

S1L2290 = AMPP_FUNCTION(S1_E_src2_prelim[2], S1L2398, S1_E_src2_hazard_M);

--S1L2288Q is std_1c20:inst|cpu:the_cpu|M_st_data[10]~158 at LC_X38_Y14_N7

--operation mode is normal

S1L2288Q = AMPP_FUNCTION(QC2__clk0, S1L2288Q, S1L2292, S1_W_stall, F1_data_out);

--S1L2077 is std_1c20:inst|cpu:the_cpu|M_estatus_reg~_DUP_COMB at LC_X32_Y15_N5

--operation mode is normal

S1L2077 = AMPP_FUNCTION(S1L2076Q, S1L2074Q, S1L1713);

--S1L2073 is std_1c20:inst|cpu:the_cpu|M_estatus_reg~5 at LC_X32_Y15_N4

--operation mode is normal

S1L2073 = AMPP_FUNCTION(S1L2038Q, S1L2074Q, S1L2071);

--S1L2074Q is std_1c20:inst|cpu:the_cpu|M_estatus_reg~7 at LC_X32_Y15_N4

--operation mode is normal

S1L2074Q = AMPP_FUNCTION(QC2__clk0, S1L2038Q, S1L2074Q, S1L2071, F1_data_out);

--S1L2045 is std_1c20:inst|cpu:the_cpu|M_bstatus_reg~_DUP_COMB at LC_X32_Y15_N1

--operation mode is normal

S1L2045 = AMPP_FUNCTION(S1L2042Q, S1L2039Q, S1L1713);

--S1L2037 is std_1c20:inst|cpu:the_cpu|M_bstatus_reg~5 at LC_X32_Y15_N9

--operation mode is normal

S1L2037 = AMPP_FUNCTION(S1L2035, S1L2038Q, S1L2039Q);

--S1L2039Q is std_1c20:inst|cpu:the_cpu|M_bstatus_reg~8 at LC_X32_Y15_N9

--operation mode is normal

S1L2039Q = AMPP_FUNCTION(QC2__clk0, S1L2035, S1L2038Q, S1L2039Q, F1_data_out);

--S1L2018Q is std_1c20:inst|cpu:the_cpu|M_alu_result[31]~310 at LC_X35_Y13_N7

--operation mode is normal

S1L2018Q = AMPP_FUNCTION(QC2__clk0, YC1_result[31], S1_E_ctrl_dst_data_sel_logic_result, S1L821, S1_E_ctrl_dst_data_sel_pc_plus_one, F1_data_out);

--S1L2012 is std_1c20:inst|cpu:the_cpu|M_alu_result[31]~301 at LC_X34_Y13_N6

--operation mode is normal

S1L2012 = AMPP_FUNCTION(S1L2014Q, S1L2015Q, S1L2013Q, S1L2020Q);

--S1L2015Q is std_1c20:inst|cpu:the_cpu|M_alu_result[31]~305 at LC_X34_Y13_N6

--operation mode is normal

S1L2015Q = AMPP_FUNCTION(QC2__clk0, S1L2014Q, S1L2015Q, S1L2013Q, S1L2020Q, F1_data_out);

--S1L1994Q is std_1c20:inst|cpu:the_cpu|M_alu_result[30]~311 at LC_X34_Y14_N0

--operation mode is normal

S1L1994Q = AMPP_FUNCTION(QC2__clk0, S1_E_ctrl_dst_data_sel_pc_plus_one, S1_E_ctrl_dst_data_sel_logic_result, YC1_result[30], S1L820, F1_data_out);

--S1L1991 is std_1c20:inst|cpu:the_cpu|M_alu_result[30]~306 at LC_X34_Y14_N7

--operation mode is normal

S1L1991 = AMPP_FUNCTION(S1L2013Q, S1L1995Q, S1L1992Q, S1L2014Q);

--S1L1992Q is std_1c20:inst|cpu:the_cpu|M_alu_result[30]~308 at LC_X34_Y14_N7

--operation mode is normal

S1L1992Q = AMPP_FUNCTION(QC2__clk0, S1L2013Q, S1L1995Q, S1L1992Q, S1L2014Q, F1_data_out);

--FD1L14Q is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_avalon_reg:the_cpu_nios2_avalon_reg|internal_oci_ienable1[0]~656 at LC_X45_Y19_N7

--operation mode is normal

FD1L14Q = AMPP_FUNCTION(QC2__clk0, FD1L14Q, S1_M_st_data[0], FD1L1, FD1L17, F1_data_out);

--FD1L19Q is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_avalon_reg:the_cpu_nios2_avalon_reg|internal_oci_ienable1[1]~658 at LC_X41_Y19_N0

--operation mode is normal

FD1L19Q = AMPP_FUNCTION(QC2__clk0, FD1L19Q, S1_M_st_data[1], FD1L37, F1_data_out);

--FD1L28Q is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_avalon_reg:the_cpu_nios2_avalon_reg|internal_oci_ienable1[4]~660 at LC_X41_Y19_N6

--operation mode is normal

FD1L28Q = AMPP_FUNCTION(QC2__clk0, FD1L28Q, S1_M_st_data[4], FD1L37, F1_data_out);

--FD1L34Q is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_avalon_reg:the_cpu_nios2_avalon_reg|internal_oci_ienable1[6]~662 at LC_X41_Y19_N7

--operation mode is normal

FD1L34Q = AMPP_FUNCTION(QC2__clk0, S1_M_st_data[6], FD1L34Q, FD1L37, F1_data_out);

--FD1L31Q is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_avalon_reg:the_cpu_nios2_avalon_reg|internal_oci_ienable1[5]~664 at LC_X41_Y19_N3

--operation mode is normal

FD1L31Q = AMPP_FUNCTION(QC2__clk0, S1_M_st_data[5], FD1L31Q, FD1L37, F1_data_out);

--FD1L25Q is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_avalon_reg:the_cpu_nios2_avalon_reg|internal_oci_ienable1[3]~666 at LC_X44_Y19_N3

--operation mode is normal

FD1L25Q = AMPP_FUNCTION(QC2__clk0, FD1L25Q, S1_M_st_data[3], FD1L37, F1_data_out);

--FD1L22Q is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_avalon_reg:the_cpu_nios2_avalon_reg|internal_oci_ienable1[2]~668 at LC_X45_Y20_N9

--operation mode is normal

FD1L22Q = AMPP_FUNCTION(QC2__clk0, S1_M_st_data[2], FD1L22Q, FD1L37, F1_data_out);

--T1L330 is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|dbs_8_reg_segment_0[1]~767 at LC_X41_Y27_N3

--operation mode is normal

T1L330 = T1L355Q & T1L366Q # !T1L355Q & (T1L331Q);

--T1L331Q is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|dbs_8_reg_segment_0[1]~768 at LC_X41_Y27_N3

--operation mode is normal

T1L331Q = DFFEAS(T1L330, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--T1L342 is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|dbs_8_reg_segment_0[4]~765 at LC_X43_Y25_N9

--operation mode is normal

T1L342 = T1L355Q & (T1L381Q) # !T1L355Q & T1L343Q;

--T1L343Q is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|dbs_8_reg_segment_0[4]~766 at LC_X43_Y25_N9

--operation mode is normal

T1L343Q = DFFEAS(T1L342, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--T1L326 is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|dbs_8_reg_segment_0[0]~763 at LC_X41_Y27_N0

--operation mode is normal

T1L326 = T1L355Q & T1L361Q # !T1L355Q & (T1L327Q);

--T1L327Q is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|dbs_8_reg_segment_0[0]~764 at LC_X41_Y27_N0

--operation mode is normal

T1L327Q = DFFEAS(T1L326, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--T1L347Q is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|dbs_8_reg_segment_0[5]~762 at LC_X43_Y25_N0

--operation mode is normal

T1L347Q_lut_out = T1L355Q & T1L386Q # !T1L355Q & (T1L347Q);

T1L347Q = DFFEAS(T1L347Q_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--T1L351Q is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|dbs_8_reg_segment_0[6]~760 at LC_X43_Y26_N6

--operation mode is normal

T1L351Q_lut_out = T1L355Q & T1L391Q # !T1L355Q & (T1L351Q);

T1L351Q = DFFEAS(T1L351Q_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--T1L339Q is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|dbs_8_reg_segment_0[3]~758 at LC_X39_Y26_N3

--operation mode is normal

T1L339Q_lut_out = T1L355Q & T1L376Q # !T1L355Q & (T1L339Q);

T1L339Q = DFFEAS(T1L339Q_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--T1L335Q is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|dbs_8_reg_segment_0[2]~756 at LC_X43_Y25_N6

--operation mode is normal

T1L335Q_lut_out = T1L355Q & T1L371Q # !T1L355Q & (T1L335Q);

T1L335Q = DFFEAS(T1L335Q_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--T1L356Q is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|dbs_8_reg_segment_0[7]~754 at LC_X43_Y26_N3

--operation mode is normal

T1L356Q_lut_out = T1L355Q & T1L397Q # !T1L355Q & (T1L356Q);

T1L356Q = DFFEAS(T1L356Q_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--T1L370 is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|dbs_8_reg_segment_1[2]~774 at LC_X43_Y25_N7

--operation mode is normal

T1L370 = T1L392Q & (T1L371Q) # !T1L392Q & T1L372Q;

--T1L372Q is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|dbs_8_reg_segment_1[2]~776 at LC_X43_Y25_N7

--operation mode is normal

T1L372Q = DFFEAS(T1L370, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--T1L365 is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|dbs_8_reg_segment_1[1]~771 at LC_X40_Y25_N5

--operation mode is normal

T1L365 = T1L392Q & (T1L366Q) # !T1L392Q & (T1L367Q);

--T1L367Q is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|dbs_8_reg_segment_1[1]~773 at LC_X40_Y25_N5

--operation mode is normal

T1L367Q = DFFEAS(T1L365, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--T1L396 is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|dbs_8_reg_segment_1[7]~768 at LC_X41_Y26_N3

--operation mode is normal

T1L396 = T1L392Q & T1L397Q # !T1L392Q & (T1L398Q);

--T1L398Q is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|dbs_8_reg_segment_1[7]~770 at LC_X41_Y26_N3

--operation mode is normal

T1L398Q = DFFEAS(T1L396, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--T1L360 is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|dbs_8_reg_segment_1[0]~765 at LC_X43_Y25_N4

--operation mode is normal

T1L360 = T1L392Q & T1L361Q # !T1L392Q & (T1L362Q);

--T1L362Q is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|dbs_8_reg_segment_1[0]~767 at LC_X43_Y25_N4

--operation mode is normal

T1L362Q = DFFEAS(T1L360, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--T1L377Q is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|dbs_8_reg_segment_1[3]~764 at LC_X39_Y26_N8

--operation mode is normal

T1L377Q_lut_out = T1L392Q & T1L376Q # !T1L392Q & (T1L377Q);

T1L377Q = DFFEAS(T1L377Q_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--T1L382Q is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|dbs_8_reg_segment_1[4]~761 at LC_X39_Y26_N1

--operation mode is normal

T1L382Q_lut_out = T1L392Q & (T1L381Q) # !T1L392Q & T1L382Q;

T1L382Q = DFFEAS(T1L382Q_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--T1L387Q is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|dbs_8_reg_segment_1[5]~758 at LC_X41_Y26_N9

--operation mode is normal

T1L387Q_lut_out = T1L392Q & T1L386Q # !T1L392Q & (T1L387Q);

T1L387Q = DFFEAS(T1L387Q_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--T1L393Q is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|dbs_8_reg_segment_1[6]~755 at LC_X41_Y26_N2

--operation mode is normal

T1L393Q_lut_out = T1L392Q & (T1L391Q) # !T1L392Q & T1L393Q;

T1L393Q = DFFEAS(T1L393Q_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--T1L420Q is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|dbs_8_reg_segment_2[4]~768 at LC_X42_Y22_N6

--operation mode is normal

T1L420Q_lut_out = T1L411Q & (T1L381Q) # !T1L411Q & T1L420Q;

T1L420Q = DFFEAS(T1L420Q_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--T1L407Q is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|dbs_8_reg_segment_2[1]~766 at LC_X41_Y27_N1

--operation mode is normal

T1L407Q_lut_out = T1L411Q & (T1L366Q) # !T1L411Q & T1L407Q;

T1L407Q = DFFEAS(T1L407Q_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--T1L403Q is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|dbs_8_reg_segment_2[0]~764 at LC_X41_Y27_N9

--operation mode is normal

T1L403Q_lut_out = T1L411Q & (T1L361Q) # !T1L411Q & T1L403Q;

T1L403Q = DFFEAS(T1L403Q_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--T1L424Q is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|dbs_8_reg_segment_2[5]~762 at LC_X40_Y23_N7

--operation mode is normal

T1L424Q_lut_out = T1L411Q & (T1L386Q) # !T1L411Q & T1L424Q;

T1L424Q = DFFEAS(T1L424Q_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--T1L432Q is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|dbs_8_reg_segment_2[7]~760 at LC_X40_Y23_N3

--operation mode is normal

T1L432Q_lut_out = T1L411Q & T1L397Q # !T1L411Q & (T1L432Q);

T1L432Q = DFFEAS(T1L432Q_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--T1L428Q is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|dbs_8_reg_segment_2[6]~758 at LC_X41_Y27_N5

--operation mode is normal

T1L428Q_lut_out = T1L411Q & T1L391Q # !T1L411Q & (T1L428Q);

T1L428Q = DFFEAS(T1L428Q_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--T1L416Q is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|dbs_8_reg_segment_2[3]~756 at LC_X40_Y24_N9

--operation mode is normal

T1L416Q_lut_out = T1L411Q & (T1L376Q) # !T1L411Q & T1L416Q;

T1L416Q = DFFEAS(T1L416Q_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--T1L412Q is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|dbs_8_reg_segment_2[2]~754 at LC_X40_Y24_N3

--operation mode is normal

T1L412Q_lut_out = T1L411Q & T1L371Q # !T1L411Q & (T1L412Q);

T1L412Q = DFFEAS(T1L412Q_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--S1L1511 is std_1c20:inst|cpu:the_cpu|ic_fill_ap_cnt[1]~32 at LC_X26_Y25_N8

--operation mode is normal

S1L1511 = AMPP_FUNCTION(S1L1512Q, S1L1510, S1L1545);

--S1L1512Q is std_1c20:inst|cpu:the_cpu|ic_fill_ap_cnt[1]~35 at LC_X26_Y25_N8

--operation mode is normal

S1L1512Q = AMPP_FUNCTION(QC2__clk0, S1L1512Q, S1L1510, S1L1545, F1_data_out);

--S1L1518 is std_1c20:inst|cpu:the_cpu|ic_fill_ap_cnt[2]~36 at LC_X26_Y25_N2

--operation mode is normal

S1L1518 = AMPP_FUNCTION(S1L1517, S1L1519Q, S1L1545);

--S1L1519Q is std_1c20:inst|cpu:the_cpu|ic_fill_ap_cnt[2]~38 at LC_X26_Y25_N2

--operation mode is normal

S1L1519Q = AMPP_FUNCTION(QC2__clk0, S1L1517, S1L1519Q, S1L1545, F1_data_out);

--S1L1526 is std_1c20:inst|cpu:the_cpu|ic_fill_ap_cnt[3]~39 at LC_X26_Y24_N2

--operation mode is normal

S1L1526 = AMPP_FUNCTION(S1L1701Q, S1L1545, S1L1525);

--Y1L589Q is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_avalon_slave_arb_addend[0]~870 at LC_X30_Y25_N3

--operation mode is normal

Y1L589Q_lut_out = Y1L645 & (Y1L507) # !Y1L645 & Y1L589Q;

Y1L589Q = DFFEAS(Y1L589Q_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--Y1L705 is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_avalon_slave_arb_share_counter[1]~600 at LC_X27_Y25_N4

--operation mode is normal

Y1L705 = Y1L685 & Y1L706Q # !Y1L685 & (Y1L707Q);

--Y1L707Q is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_avalon_slave_arb_share_counter[1]~602 at LC_X27_Y25_N4

--operation mode is normal

Y1L707Q = DFFEAS(Y1L705, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--Y1L690 is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_avalon_slave_arb_share_counter[0]~596 at LC_X27_Y25_N9

--operation mode is normal

Y1L690 = Y1L685 & Y1L691Q # !Y1L685 & (Y1L692Q);

--Y1L692Q is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_avalon_slave_arb_share_counter[0]~599 at LC_X27_Y25_N9

--operation mode is normal

Y1L692Q = DFFEAS(Y1L690, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--Y1L603 is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_avalon_slave_arb_addend[1]~_DUP_COMB_688 at LC_X31_Y19_N7

--operation mode is normal

Y1L603 = Y1L711 & (Y1L742) # !Y1L711 & Y1L730;

--Y1L733Q is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_avalon_slave_saved_chosen_master_vector[0]~673 at LC_X31_Y19_N7

--operation mode is normal

Y1L733Q = DFFEAS(Y1L603, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--Y1L599 is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_avalon_slave_arb_addend[1]~718 at LC_X30_Y21_N8

--operation mode is normal

Y1L599 = Y1L643Q & (Y1L741Q) # !Y1L643Q & Y1L600Q;

--Y1L600Q is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_avalon_slave_arb_addend[1]~720 at LC_X30_Y21_N8

--operation mode is normal

Y1L600Q = DFFEAS(Y1L599, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--Y1L634 is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_avalon_slave_arb_addend[3]~_DUP_COMB_691 at LC_X28_Y24_N9

--operation mode is normal

Y1L634 = Y1L711 & (Y1L770) # !Y1L711 & Y1L762;

--Y1L766Q is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_avalon_slave_saved_chosen_master_vector[2]~680 at LC_X28_Y24_N9

--operation mode is normal

Y1L766Q = DFFEAS(Y1L634, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--Y1L623 is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_avalon_slave_arb_addend[3]~715 at LC_X30_Y24_N9

--operation mode is normal

Y1L623 = Y1L653Q & (Y1L660Q) # !Y1L653Q & (Y1L643Q & Y1L630Q # !Y1L643Q & (Y1L660Q));

--Y1L632Q is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_avalon_slave_arb_addend[3]~868 at LC_X30_Y24_N9

--operation mode is normal

Y1L632Q = DFFEAS(Y1L623, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--Y1L681 is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_avalon_slave_arb_addend[5]~_DUP_COMB_694 at LC_X27_Y21_N3

--operation mode is normal

Y1L681 = Y1L711 & Y1L176 # !Y1L711 & (Y1L792);

--Y1L795Q is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_avalon_slave_saved_chosen_master_vector[4]~672 at LC_X27_Y21_N3

--operation mode is normal

Y1L795Q = DFFEAS(Y1L681, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--Y1L671 is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_avalon_slave_arb_addend[5]~712 at LC_X31_Y24_N6

--operation mode is normal

Y1L671 = Y1L643Q & (Y1L653Q & Y1L661Q # !Y1L653Q & (Y1L678Q)) # !Y1L643Q & Y1L661Q;

--Y1L680Q is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_avalon_slave_arb_addend[5]~866 at LC_X31_Y24_N6

--operation mode is normal

Y1L680Q = DFFEAS(Y1L671, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--Y1L749Q is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_avalon_slave_saved_chosen_master_vector[1]~671 at LC_X31_Y19_N9

--operation mode is normal

Y1L749Q_lut_out = Y1L711 & (Y1L755) # !Y1L711 & Y1L746;

Y1L749Q = DFFEAS(Y1L749Q_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--Y1L610 is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_avalon_slave_arb_addend[2]~709 at LC_X31_Y24_N8

--operation mode is normal

Y1L610 = Y1L643Q & (Y1L753Q) # !Y1L643Q & Y1L611Q;

--Y1L611Q is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_avalon_slave_arb_addend[2]~711 at LC_X31_Y24_N8

--operation mode is normal

Y1L611Q = DFFEAS(Y1L610, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--Y1L663 is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_avalon_slave_arb_addend[4]~_DUP_COMB_700 at LC_X32_Y23_N2

--operation mode is normal

Y1L663 = Y1L711 & (Y1L905) # !Y1L711 & Y1L774;

--Y1L778Q is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_avalon_slave_saved_chosen_master_vector[3]~681 at LC_X32_Y23_N2

--operation mode is normal

Y1L778Q = DFFEAS(Y1L663, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--Y1L642 is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_avalon_slave_arb_addend[4]~705 at LC_X30_Y24_N7

--operation mode is normal

Y1L642 = Y1L653Q & (Y1L659Q) # !Y1L653Q & (Y1L643Q & Y1L655Q # !Y1L643Q & (Y1L659Q));

--Y1L657Q is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_avalon_slave_arb_addend[4]~863 at LC_X30_Y24_N7

--operation mode is normal

Y1L657Q = DFFEAS(Y1L642, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--S1L2013Q is std_1c20:inst|cpu:the_cpu|M_alu_result[31]~302 at LC_X33_Y14_N3

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

S1L2013Q = AMPP_FUNCTION(QC2__clk0, S1_E_ctrl_dst_data_sel_cmp, F1_data_out, GND);

--Y1L883Q is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|lan91c111_s1_wait_counter[1]~101 at LC_X32_Y27_N6

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

Y1L883Q_lut_out = GND;

Y1L883Q = DFFEAS(Y1L883Q_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , Y1L978, , , VCC);

--Y1L893Q is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|lan91c111_s1_wait_counter[2]~111 at LC_X32_Y27_N8

--operation mode is normal

Y1L893Q_lut_out = Y1_ext_ram_bus_avalon_slave_begins_xfer & (Y1L177 # S1L1686Q & Y1L739);

Y1L893Q = DFFEAS(Y1L893Q_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--Y1L398Q is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_flash_s1_wait_counter[3]~88 at LC_X30_Y27_N6

--operation mode is normal

Y1L398Q_lut_out = Y1L380;

Y1L398Q = DFFEAS(Y1L398Q_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--U1L14Q is std_1c20:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_read_but_no_slave_selected~62 at LC_X26_Y24_N8

--operation mode is normal

U1L14Q_lut_out = S1_D_ic_fill_starting_d1 # U1L14Q & (!S1L1701Q # !S1L1498Q);

U1L14Q = DFFEAS(U1L14Q_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--S1L209Q is std_1c20:inst|cpu:the_cpu|av_ld_data_aligned_or_div[25]~125 at LC_X31_Y20_N3

--operation mode is normal

S1L209Q = AMPP_FUNCTION(QC2__clk0, S1L1817, S1L1871, S1L1803, F1_data_out);

--S1L1688Q is std_1c20:inst|cpu:the_cpu|internal_d_write~68 at LC_X31_Y20_N4

--operation mode is normal

S1L1688Q = AMPP_FUNCTION(QC2__clk0, S1L1682, S1L1685, S1L1867, T1L449, F1_data_out);

--Y1L900 is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|last_cycle_cpu_data_master_granted_slave_ext_flash_s1~5_DUP_COMB at LC_X32_Y21_N4

--operation mode is normal

Y1L900 = !S1L1855 & S1L1687 & !T1L449 & !S1L208;

--S1L1689Q is std_1c20:inst|cpu:the_cpu|internal_d_write~69 at LC_X32_Y21_N4

--operation mode is normal

S1L1689Q = AMPP_FUNCTION(QC2__clk0, S1L1855, S1L1687, T1L449, S1L208, F1_data_out);

--Y1L967 is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|last_cycle_cpu_instruction_master_granted_slave_lan91c111_s1~4_DUP_COMB at LC_X30_Y20_N2

--operation mode is normal

Y1L967 = S1L1620 & S1L1591 & !S1L1599 & S1L1504;

--S1L1601Q is std_1c20:inst|cpu:the_cpu|ic_fill_tag[6]~156 at LC_X30_Y20_N2

--operation mode is normal

S1L1601Q = AMPP_FUNCTION(QC2__clk0, S1L1620, S1L1591, S1L1599, S1L1504, F1_data_out);

--S1L1507Q is std_1c20:inst|cpu:the_cpu|ic_fill_ap_cnt[0]~65 at LC_X29_Y22_N4

--operation mode is normal

S1L1507Q = AMPP_FUNCTION(QC2__clk0, S1L1639, S1L1634, S1L1643, U1L15, F1_data_out);

--S1L1640Q is std_1c20:inst|cpu:the_cpu|ic_fill_tag[12]~158 at LC_X31_Y23_N5

--operation mode is normal

S1L1640Q = AMPP_FUNCTION(QC2__clk0, S1L1639, S1L1504, Y1L1009, S1L1634, F1_data_out);

--Y1L903 is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|last_cycle_cpu_data_master_granted_slave_ext_flash_s1~8_DUP_COMB at LC_X29_Y25_N2

--operation mode is normal

Y1L903 = Y1L711 & (Y1L787) # !Y1L711 & Y1L774;

--Y1L777Q is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_avalon_slave_saved_chosen_master_vector[3]~678 at LC_X29_Y25_N2

--operation mode is normal

Y1L777Q = DFFEAS(Y1L903, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--Y1L782Q is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_avalon_slave_saved_chosen_master_vector[3]~684 at LC_X32_Y23_N0

--operation mode is normal

Y1L782Q_lut_out = Y1_cpu_data_master_requests_ext_flash_s1 & (Y1L663 # Y1L896 & !Y1_ext_ram_bus_avalon_slave_arbitration_holdoff_internal);

Y1L782Q = DFFEAS(Y1L782Q_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--Y1L942 is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|last_cycle_cpu_data_master_granted_slave_lan91c111_s1~8_DUP_COMB at LC_X31_Y24_N7

--operation mode is normal

Y1L942 = Y1L711 & Y1L736 # !Y1L711 & (Y1L746);

--Y1L752Q is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_avalon_slave_saved_chosen_master_vector[1]~706 at LC_X31_Y24_N7

--operation mode is normal

Y1L752Q = DFFEAS(Y1L942, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--Y1L796Q is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_avalon_slave_saved_chosen_master_vector[4]~679 at LC_X27_Y21_N0

--operation mode is normal

Y1L796Q_lut_out = Y1L711 & Y1L176 # !Y1L711 & (Y1L792);

Y1L796Q = DFFEAS(Y1L796Q_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--Y1L797Q is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_avalon_slave_saved_chosen_master_vector[4]~687 at LC_X28_Y21_N3

--operation mode is normal

Y1L797Q_lut_out = Y1L1005 & (Y1L681 # Y1L955 & !Y1_ext_ram_bus_avalon_slave_arbitration_holdoff_internal);

Y1L797Q = DFFEAS(Y1L797Q_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--Y1L765Q is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_avalon_slave_saved_chosen_master_vector[2]~677 at LC_X28_Y24_N2

--operation mode is normal

Y1L765Q_lut_out = Y1L711 & Y1L770 # !Y1L711 & (Y1L762);

Y1L765Q = DFFEAS(Y1L765Q_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--Y1L767Q is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_avalon_slave_saved_chosen_master_vector[2]~688 at LC_X28_Y24_N3

--operation mode is normal

Y1L767Q_lut_out = Y1L194 & (Y1L634 # !Y1_ext_ram_bus_avalon_slave_arbitration_holdoff_internal & Y1L945);

Y1L767Q = DFFEAS(Y1L767Q_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--Y1L973 is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|last_cycle_cpu_instruction_master_granted_slave_lan91c111_s1~9_DUP_COMB at LC_X30_Y21_N2

--operation mode is normal

Y1L973 = Y1L711 & Y1L742 # !Y1L711 & (Y1L730);

--Y1L740Q is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_avalon_slave_saved_chosen_master_vector[0]~708 at LC_X30_Y21_N2

--operation mode is normal

Y1L740Q = DFFEAS(Y1L973, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--DE1L216Q is std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|epcs_slave_select_reg[0]~2505 at LC_X37_Y27_N3

--operation mode is normal

DE1L216Q_lut_out = DE1L286 & DE1L167Q # !DE1L286 & (DE1L216Q);

DE1L216Q = DFFEAS(DE1L216Q_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--DE1L232Q is std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|epcs_slave_select_reg[8]~2506 at LC_X38_Y27_N4

--operation mode is normal

DE1L232Q_lut_out = DE1L286 & DE1L191Q # !DE1L286 & (DE1L232Q);

DE1L232Q = DFFEAS(DE1L232Q_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--DE1L234Q is std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|epcs_slave_select_reg[9]~2507 at LC_X37_Y27_N7

--operation mode is normal

DE1L234Q_lut_out = DE1L286 & (DE1L194Q) # !DE1L286 & (DE1L234Q);

DE1L234Q = DFFEAS(DE1L234Q_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--DE1L236Q is std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|epcs_slave_select_reg[10]~2508 at LC_X36_Y27_N3

--operation mode is normal

DE1L236Q_lut_out = DE1L286 & DE1L197Q # !DE1L286 & (DE1L236Q);

DE1L236Q = DFFEAS(DE1L236Q_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--DE1L218Q is std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|epcs_slave_select_reg[1]~2509 at LC_X38_Y29_N0

--operation mode is normal

DE1L218Q_lut_out = DE1L286 & DE1L170Q # !DE1L286 & (DE1L218Q);

DE1L218Q = DFFEAS(DE1L218Q_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--DE1L220Q is std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|epcs_slave_select_reg[2]~2510 at LC_X38_Y29_N7

--operation mode is normal

DE1L220Q_lut_out = DE1L286 & (DE1L173Q) # !DE1L286 & DE1L220Q;

DE1L220Q = DFFEAS(DE1L220Q_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--DE1L224Q is std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|epcs_slave_select_reg[4]~2511 at LC_X37_Y27_N9

--operation mode is normal

DE1L224Q_lut_out = DE1L286 & (DE1L179Q) # !DE1L286 & DE1L224Q;

DE1L224Q = DFFEAS(DE1L224Q_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--DE1L228Q is std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|epcs_slave_select_reg[6]~2512 at LC_X36_Y28_N2

--operation mode is normal

DE1L228Q_lut_out = DE1L286 & DE1L185Q # !DE1L286 & (DE1L228Q);

DE1L228Q = DFFEAS(DE1L228Q_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--DE1L230Q is std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|epcs_slave_select_reg[7]~2513 at LC_X35_Y29_N4

--operation mode is normal

DE1L230Q_lut_out = DE1L286 & DE1L188Q # !DE1L286 & (DE1L230Q);

DE1L230Q = DFFEAS(DE1L230Q_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--DE1L222Q is std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|epcs_slave_select_reg[3]~2514 at LC_X35_Y29_N2

--operation mode is normal

DE1L222Q_lut_out = DE1L286 & DE1L176Q # !DE1L286 & (DE1L222Q);

DE1L222Q = DFFEAS(DE1L222Q_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--DE1L226Q is std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|epcs_slave_select_reg[5]~2515 at LC_X36_Y27_N1

--operation mode is normal

DE1L226Q_lut_out = DE1L286 & (DE1L182Q) # !DE1L286 & DE1L226Q;

DE1L226Q = DFFEAS(DE1L226Q_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--DE1L238Q is std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|epcs_slave_select_reg[11]~2516 at LC_X36_Y29_N3

--operation mode is normal

DE1L238Q_lut_out = DE1L286 & DE1L200Q # !DE1L286 & (DE1L238Q);

DE1L238Q = DFFEAS(DE1L238Q_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--DE1L241Q is std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|epcs_slave_select_reg[12]~2518 at LC_X38_Y27_N3

--operation mode is normal

DE1L241Q_lut_out = DE1L286 & DE1L203Q # !DE1L286 & (DE1L241Q);

DE1L241Q = DFFEAS(DE1L241Q_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--DE1L244Q is std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|epcs_slave_select_reg[13]~2520 at LC_X36_Y28_N3

--operation mode is normal

DE1L244Q_lut_out = DE1L286 & DE1L206Q # !DE1L286 & (DE1L244Q);

DE1L244Q = DFFEAS(DE1L244Q_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--DE1L247Q is std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|epcs_slave_select_reg[14]~2522 at LC_X36_Y28_N4

--operation mode is normal

DE1L247Q_lut_out = DE1L286 & (DE1L209Q) # !DE1L286 & DE1L247Q;

DE1L247Q = DFFEAS(DE1L247Q_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--DE1L250Q is std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|epcs_slave_select_reg[15]~2524 at LC_X36_Y29_N6

--operation mode is normal

DE1L250Q_lut_out = DE1L286 & DE1L212Q # !DE1L286 & (DE1L250Q);

DE1L250Q = DFFEAS(DE1L250Q_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--Y1L591Q is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_avalon_slave_arb_addend[0]~872 at LC_X30_Y25_N5

--operation mode is normal

Y1L591Q_lut_out = Y1L645 & (Y1L510) # !Y1L645 & Y1L591Q;

Y1L591Q = DFFEAS(Y1L591Q_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--Y1L524Q is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_avalon_slave_arb_addend[0]~742 at LC_X30_Y25_N6

--operation mode is normal

Y1L524Q_lut_out = Y1L645 & (Y1L200 # Y1L580) # !Y1L645 & Y1L524Q;

Y1L524Q = DFFEAS(Y1L524Q_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--Y1L730 is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_avalon_slave_saved_chosen_master_vector[0]~668 at LC_X31_Y26_N6

--operation mode is normal

Y1L730 = Y1L805Q & (Y1L731Q) # !Y1L805Q & Y1L732Q;

--Y1L732Q is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_avalon_slave_saved_chosen_master_vector[0]~670 at LC_X31_Y26_N6

--operation mode is normal

Y1L732Q = DFFEAS(Y1L730, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--Y1L762 is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_avalon_slave_saved_chosen_master_vector[2]~665 at LC_X26_Y25_N4

--operation mode is normal

Y1L762 = Y1L805Q & Y1L763Q # !Y1L805Q & (Y1L764Q);

--Y1L764Q is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_avalon_slave_saved_chosen_master_vector[2]~667 at LC_X26_Y25_N4

--operation mode is normal

Y1L764Q = DFFEAS(Y1L762, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--Y1L792 is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_avalon_slave_saved_chosen_master_vector[4]~662 at LC_X27_Y24_N8

--operation mode is normal

Y1L792 = Y1L805Q & (Y1L793Q) # !Y1L805Q & Y1L794Q;

--Y1L794Q is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_avalon_slave_saved_chosen_master_vector[4]~664 at LC_X27_Y24_N8

--operation mode is normal

Y1L794Q = DFFEAS(Y1L792, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--Y1L746 is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_avalon_slave_saved_chosen_master_vector[1]~659 at LC_X35_Y25_N4

--operation mode is normal

Y1L746 = Y1L805Q & (Y1L747Q) # !Y1L805Q & Y1L748Q;

--Y1L748Q is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_avalon_slave_saved_chosen_master_vector[1]~661 at LC_X35_Y25_N4

--operation mode is normal

Y1L748Q = DFFEAS(Y1L746, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--Y1L774 is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_avalon_slave_saved_chosen_master_vector[3]~656 at LC_X31_Y26_N5

--operation mode is normal

Y1L774 = Y1L805Q & (Y1L775Q) # !Y1L805Q & Y1L776Q;

--Y1L776Q is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_avalon_slave_saved_chosen_master_vector[3]~658 at LC_X31_Y26_N5

--operation mode is normal

Y1L776Q = DFFEAS(Y1L774, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--Y1L803 is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_avalon_slave_saved_chosen_master_vector[5]~652 at LC_X32_Y22_N7

--operation mode is normal

Y1L803 = Y1L805Q & (Y1L804Q) # !Y1L805Q & Y1L807Q;

--Y1L807Q is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_avalon_slave_saved_chosen_master_vector[5]~655 at LC_X32_Y22_N7

--operation mode is normal

Y1L807Q = DFFEAS(Y1L803, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--S1L2041Q is std_1c20:inst|cpu:the_cpu|M_bstatus_reg~10 at LC_X32_Y14_N5

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

S1L2041Q = AMPP_FUNCTION(QC2__clk0, S1_E_ctrl_break, F1_data_out, GND);

--S1L2075Q is std_1c20:inst|cpu:the_cpu|M_estatus_reg~8 at LC_X32_Y15_N0

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

S1L2075Q = AMPP_FUNCTION(QC2__clk0, S1_E_ctrl_exception, F1_data_out, GND);

--Y1L118 is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|cpu_data_master_read_data_valid_ext_flash_s1_shift_register[0]~23 at LC_X30_Y27_N4

--operation mode is normal

Y1L118 = !Y1_ext_flash_s1_wait_counter[1] & !Y1L396Q & !Y1L387Q & !Y1L380;

--T1L391Q is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|dbs_8_reg_segment_1[6]~753 at LC_X41_Y27_N7

--operation mode is normal

T1L391Q_lut_out = Y1_internal_incoming_ext_ram_bus_data[6];

T1L391Q = DFFEAS(T1L391Q_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--T1L386Q is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|dbs_8_reg_segment_1[5]~757 at LC_X40_Y23_N4

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

T1L386Q_lut_out = GND;

T1L386Q = DFFEAS(T1L386Q_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , Y1_internal_incoming_ext_ram_bus_data[5], , , VCC);

--T1L381Q is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|dbs_8_reg_segment_1[4]~760 at LC_X39_Y26_N4

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

T1L381Q_lut_out = GND;

T1L381Q = DFFEAS(T1L381Q_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , Y1_internal_incoming_ext_ram_bus_data[4], , , VCC);

--T1L376Q is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|dbs_8_reg_segment_1[3]~763 at LC_X39_Y25_N9

--operation mode is normal

T1L376Q_lut_out = Y1_internal_incoming_ext_ram_bus_data[3];

T1L376Q = DFFEAS(T1L376Q_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--T1L361Q is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|dbs_8_reg_segment_1[0]~766 at LC_X40_Y25_N1

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

T1L361Q_lut_out = GND;

T1L361Q = DFFEAS(T1L361Q_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , Y1_internal_incoming_ext_ram_bus_data[0], , , VCC);

--T1L397Q is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|dbs_8_reg_segment_1[7]~769 at LC_X40_Y23_N5

--operation mode is normal

T1L397Q_lut_out = Y1_internal_incoming_ext_ram_bus_data[7];

T1L397Q = DFFEAS(T1L397Q_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--T1L366Q is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|dbs_8_reg_segment_1[1]~772 at LC_X39_Y24_N9

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

T1L366Q_lut_out = GND;

T1L366Q = DFFEAS(T1L366Q_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , Y1_internal_incoming_ext_ram_bus_data[1], , , VCC);

--T1L371Q is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|dbs_8_reg_segment_1[2]~775 at LC_X41_Y25_N9

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

T1L371Q_lut_out = GND;

T1L371Q = DFFEAS(T1L371Q_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , Y1_internal_incoming_ext_ram_bus_data[2], , , VCC);

--S1L1369Q is std_1c20:inst|cpu:the_cpu|i_readdata_d1[1]~161 at LC_X46_Y19_N3

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

S1L1369Q = AMPP_FUNCTION(QC2__clk0, V1L26, F1_data_out, GND);

--S1L1370Q is std_1c20:inst|cpu:the_cpu|i_readdata_d1[1]~162 at LC_X46_Y19_N7

--operation mode is normal

S1L1370Q = AMPP_FUNCTION(QC2__clk0, CE1_q_a[1], F1_data_out);

--S1L1371Q is std_1c20:inst|cpu:the_cpu|i_readdata_d1[1]~163 at LC_X46_Y19_N4

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

S1L1371Q = AMPP_FUNCTION(QC2__clk0, JD1_internal_monitor_ready, F1_data_out, GND);

--S1L1362Q is std_1c20:inst|cpu:the_cpu|i_readdata_d1[0]~164 at LC_X46_Y19_N6

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

S1L1362Q = AMPP_FUNCTION(QC2__clk0, CE1_q_a[0], F1_data_out, GND);

--S1L1363Q is std_1c20:inst|cpu:the_cpu|i_readdata_d1[0]~165 at LC_X46_Y18_N8

--operation mode is normal

S1L1363Q = AMPP_FUNCTION(QC2__clk0, JD1_internal_monitor_error, F1_data_out);

--S1L1376Q is std_1c20:inst|cpu:the_cpu|i_readdata_d1[2]~166 at LC_X46_Y19_N9

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

S1L1376Q = AMPP_FUNCTION(QC2__clk0, JD1_internal_monitor_go, F1_data_out, GND);

--S1L1377Q is std_1c20:inst|cpu:the_cpu|i_readdata_d1[2]~167 at LC_X46_Y19_N5

--operation mode is normal

S1L1377Q = AMPP_FUNCTION(QC2__clk0, CE1_q_a[2], F1_data_out);

--DE1L70Q is std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|data_to_cpu[5]~34 at LC_X37_Y26_N8

--operation mode is normal

DE1L70Q_lut_out = DE1L47 & (DE1L76) # !DE1L47 & (DE1L74 & DE1L226Q # !DE1L74 & (DE1L76));

DE1L70Q = DFFEAS(DE1L70Q_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--DE1L48Q is std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|data_to_cpu[0]~39 at LC_X38_Y28_N5

--operation mode is normal

DE1L48Q_lut_out = DE1L103Q;

DE1L48Q = DFFEAS(DE1L48Q_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--DE1L51 is std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|data_to_cpu[0]~48 at LC_X37_Y28_N9

--operation mode is normal

DE1L51 = DE1L52Q & (!DE1L54Q) # !DE1L52Q & DE1L53Q;

--Y1L699 is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_avalon_slave_arb_share_counter[0]~607 at LC_X28_Y26_N9

--operation mode is normal

Y1L699 = Y1L700Q & (Y1L201Q # !Y1L197Q & !Y1L203Q);

--S1L1996Q is std_1c20:inst|cpu:the_cpu|M_alu_result[30]~316 at LC_X35_Y18_N0

--operation mode is normal

S1L1996Q = AMPP_FUNCTION(QC2__clk0, S1_W_stall, S1L1988, S1_E_ctrl_dst_data_sel_cmp, S1L1991, F1_data_out);

--S1L2022Q is std_1c20:inst|cpu:the_cpu|M_alu_result[31]~317 at LC_X34_Y13_N8

--operation mode is normal

S1L2022Q = AMPP_FUNCTION(QC2__clk0, S1L2012, S1_E_ctrl_dst_data_sel_cmp, S1_W_stall, S1L2009, F1_data_out);

--WE1L62 is std_1c20:inst|sdram_s1_arbitrator:the_sdram_s1|rdv_fifo_for_cpu_instruction_master_to_sdram_s1_module:rdv_fifo_for_cpu_instruction_master_to_sdram_s1|stage_6~_DUP_COMB at LC_X23_Y22_N8

--operation mode is normal

WE1L62 = NB1L25 & (!NB1L22 & NB1_sdram_s1_arb_addend[1] # !NB1_sdram_s1_arb_addend[0]);

--S1L523 is std_1c20:inst|cpu:the_cpu|d_readdata_d1[8]~107_DUP_COMB at LC_X37_Y21_N0

--operation mode is normal

S1L523 = AMPP_FUNCTION(K1L3, V1L8);

--Y1L381Q is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_flash_s1_wait_counter[0]~96 at LC_X30_Y27_N7

--operation mode is normal

Y1L381Q_lut_out = Y1_ext_ram_bus_avalon_slave_begins_xfer & (Y1L372 # Y1L770 # Y1L122);

Y1L381Q = DFFEAS(Y1L381Q_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--S1L1451 is std_1c20:inst|cpu:the_cpu|i_readdata_d1[10]~142_DUP_COMB at LC_X34_Y24_N2

--operation mode is normal

S1L1451 = AMPP_FUNCTION(V1L58, S1L1593Q, X1L16);

--V1L40 is std_1c20:inst|cpu_jtag_debug_module_arbitrator:the_cpu_jtag_debug_module|cpu_jtag_debug_module_arb_addend[1]~752_DUP_COMB at LC_X34_Y24_N5

--operation mode is normal

V1L40 = V1L13 & (V1L2 # !V1L34Q);

--Y1L644 is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_avalon_slave_arb_addend[4]~707_DUP_COMB at LC_X31_Y23_N8

--operation mode is normal

Y1L644 = Y1L905 # Y1L96 # Y1L736 # !Y1L696;

--VE1L48Q is std_1c20:inst|sdram_s1_arbitrator:the_sdram_s1|rdv_fifo_for_cpu_data_master_to_sdram_s1_module:rdv_fifo_for_cpu_data_master_to_sdram_s1|stage_6~7021 at LC_X22_Y25_N6

--operation mode is normal

VE1L48Q_lut_out = WE1L26 & (NB1L20) # !WE1L26 & VE1L48Q;

VE1L48Q = DFFEAS(VE1L48Q_lut_out, GLOBAL(QC2__clk0), VCC, , , , , , );

--VE1L44Q is std_1c20:inst|sdram_s1_arbitrator:the_sdram_s1|rdv_fifo_for_cpu_data_master_to_sdram_s1_module:rdv_fifo_for_cpu_data_master_to_sdram_s1|stage_5~7020 at LC_X22_Y25_N8

--operation mode is normal

VE1L44Q_lut_out = WE1L27 & (VE1L45) # !WE1L27 & VE1L44Q;

VE1L44Q = DFFEAS(VE1L44Q_lut_out, GLOBAL(QC2__clk0), VCC, , , , , , );

--WE1L57Q is std_1c20:inst|sdram_s1_arbitrator:the_sdram_s1|rdv_fifo_for_cpu_instruction_master_to_sdram_s1_module:rdv_fifo_for_cpu_instruction_master_to_sdram_s1|stage_5~4 at LC_X22_Y25_N2

--operation mode is normal

WE1L57Q_lut_out = WE1L27 & (WE1L58) # !WE1L27 & WE1L57Q;

WE1L57Q = DFFEAS(WE1L57Q_lut_out, GLOBAL(QC2__clk0), VCC, , , , , , );

--VE1L40Q is std_1c20:inst|sdram_s1_arbitrator:the_sdram_s1|rdv_fifo_for_cpu_data_master_to_sdram_s1_module:rdv_fifo_for_cpu_data_master_to_sdram_s1|stage_4~7020 at LC_X23_Y25_N3

--operation mode is normal

VE1L40Q_lut_out = WE1L28 & (VE1L41) # !WE1L28 & VE1L40Q;

VE1L40Q = DFFEAS(VE1L40Q_lut_out, GLOBAL(QC2__clk0), VCC, , , , , , );

--WE1L53Q is std_1c20:inst|sdram_s1_arbitrator:the_sdram_s1|rdv_fifo_for_cpu_instruction_master_to_sdram_s1_module:rdv_fifo_for_cpu_instruction_master_to_sdram_s1|stage_4~4 at LC_X23_Y25_N6

--operation mode is normal

WE1L53Q_lut_out = WE1L28 & (WE1L54) # !WE1L28 & WE1L53Q;

WE1L53Q = DFFEAS(WE1L53Q_lut_out, GLOBAL(QC2__clk0), VCC, , , , , , );

--VE1L36Q is std_1c20:inst|sdram_s1_arbitrator:the_sdram_s1|rdv_fifo_for_cpu_data_master_to_sdram_s1_module:rdv_fifo_for_cpu_data_master_to_sdram_s1|stage_3~7020 at LC_X23_Y25_N8

--operation mode is normal

VE1L36Q_lut_out = WE1L29 & (VE1L37) # !WE1L29 & VE1L36Q;

VE1L36Q = DFFEAS(VE1L36Q_lut_out, GLOBAL(QC2__clk0), VCC, , , , , , );

--WE1L49Q is std_1c20:inst|sdram_s1_arbitrator:the_sdram_s1|rdv_fifo_for_cpu_instruction_master_to_sdram_s1_module:rdv_fifo_for_cpu_instruction_master_to_sdram_s1|stage_3~4 at LC_X23_Y25_N2

--operation mode is normal

WE1L49Q_lut_out = WE1L29 & (WE1L50) # !WE1L29 & WE1L49Q;

WE1L49Q = DFFEAS(WE1L49Q_lut_out, GLOBAL(QC2__clk0), VCC, , , , , , );

--VE1L32Q is std_1c20:inst|sdram_s1_arbitrator:the_sdram_s1|rdv_fifo_for_cpu_data_master_to_sdram_s1_module:rdv_fifo_for_cpu_data_master_to_sdram_s1|stage_2~980 at LC_X24_Y25_N3

--operation mode is normal

VE1L32Q_lut_out = WE1L30 & (VE1L33) # !WE1L30 & VE1L32Q;

VE1L32Q = DFFEAS(VE1L32Q_lut_out, GLOBAL(QC2__clk0), VCC, , , , , , );

--WE1L45Q is std_1c20:inst|sdram_s1_arbitrator:the_sdram_s1|rdv_fifo_for_cpu_instruction_master_to_sdram_s1_module:rdv_fifo_for_cpu_instruction_master_to_sdram_s1|stage_2~4 at LC_X24_Y25_N8

--operation mode is normal

WE1L45Q_lut_out = WE1L30 & (WE1L46) # !WE1L30 & WE1L45Q;

WE1L45Q = DFFEAS(WE1L45Q_lut_out, GLOBAL(QC2__clk0), VCC, , , , , , );

--VE1L28Q is std_1c20:inst|sdram_s1_arbitrator:the_sdram_s1|rdv_fifo_for_cpu_data_master_to_sdram_s1_module:rdv_fifo_for_cpu_data_master_to_sdram_s1|stage_1~572 at LC_X24_Y25_N6

--operation mode is normal

VE1L28Q_lut_out = WE1L31 & (VE1L29) # !WE1L31 & VE1L28Q;

VE1L28Q = DFFEAS(VE1L28Q_lut_out, GLOBAL(QC2__clk0), VCC, , , , , , );

--WE1L41Q is std_1c20:inst|sdram_s1_arbitrator:the_sdram_s1|rdv_fifo_for_cpu_instruction_master_to_sdram_s1_module:rdv_fifo_for_cpu_instruction_master_to_sdram_s1|stage_1~4 at LC_X24_Y25_N4

--operation mode is normal

WE1L41Q_lut_out = WE1L31 & (WE1L42) # !WE1L31 & WE1L41Q;

WE1L41Q = DFFEAS(WE1L41Q_lut_out, GLOBAL(QC2__clk0), VCC, , , , , , );

--VE1L24Q is std_1c20:inst|sdram_s1_arbitrator:the_sdram_s1|rdv_fifo_for_cpu_data_master_to_sdram_s1_module:rdv_fifo_for_cpu_data_master_to_sdram_s1|stage_0~578 at LC_X24_Y24_N9

--operation mode is normal

VE1L24Q_lut_out = WE1L32 & (VE1L25) # !WE1L32 & VE1L24Q;

VE1L24Q = DFFEAS(VE1L24Q_lut_out, GLOBAL(QC2__clk0), VCC, , , , , , );

--WE1L37Q is std_1c20:inst|sdram_s1_arbitrator:the_sdram_s1|rdv_fifo_for_cpu_instruction_master_to_sdram_s1_module:rdv_fifo_for_cpu_instruction_master_to_sdram_s1|stage_0~4 at LC_X24_Y24_N4

--operation mode is normal

WE1L37Q_lut_out = WE1L32 & WE1L38 # !WE1L32 & (WE1L37Q);

WE1L37Q = DFFEAS(WE1L37Q_lut_out, GLOBAL(QC2__clk0), VCC, , , , , , );

--VE1L11 is std_1c20:inst|sdram_s1_arbitrator:the_sdram_s1|rdv_fifo_for_cpu_data_master_to_sdram_s1_module:rdv_fifo_for_cpu_data_master_to_sdram_s1|fifo_contains_ones_n~20 at LC_X23_Y24_N9

--operation mode is normal

VE1L11 = VE1L16 & (VE1L2 # VE1L4) # !VE1L16 & (VE1L14);

--VE1L8Q is std_1c20:inst|sdram_s1_arbitrator:the_sdram_s1|rdv_fifo_for_cpu_data_master_to_sdram_s1_module:rdv_fifo_for_cpu_data_master_to_sdram_s1|fifo_contains_ones_n~18 at LC_X23_Y24_N9

--operation mode is normal

VE1L8Q = DFFEAS(VE1L11, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--WE1L11 is std_1c20:inst|sdram_s1_arbitrator:the_sdram_s1|rdv_fifo_for_cpu_instruction_master_to_sdram_s1_module:rdv_fifo_for_cpu_instruction_master_to_sdram_s1|fifo_contains_ones_n~19 at LC_X25_Y24_N9

--operation mode is normal

WE1L11 = WE1L33 & (WE1L2 # !WE1L13) # !WE1L33 & WE1L8Q;

--WE1L8Q is std_1c20:inst|sdram_s1_arbitrator:the_sdram_s1|rdv_fifo_for_cpu_instruction_master_to_sdram_s1_module:rdv_fifo_for_cpu_instruction_master_to_sdram_s1|fifo_contains_ones_n~17 at LC_X25_Y24_N9

--operation mode is normal

WE1L8Q = DFFEAS(WE1L11, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--DE1L63Q is std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|data_to_cpu[4]~45 at LC_X38_Y28_N2

--operation mode is normal

DE1L63Q_lut_out = DE1L255 & DE1_iTOE_reg # !DE1L255 & (DE1L15);

DE1L63Q = DFFEAS(DE1L63Q_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--DE1L84Q is std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|data_to_cpu[6]~47 at LC_X38_Y28_N0

--operation mode is normal

DE1L84Q_lut_out = DE1L255 & (DE1_iTRDY_reg) # !DE1L255 & DE1L12;

DE1L84Q = DFFEAS(DE1L84Q_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--S1L2017Q is std_1c20:inst|cpu:the_cpu|M_alu_result[31]~309 at LC_X33_Y13_N0

--operation mode is normal

S1L2017Q = AMPP_FUNCTION(QC2__clk0, S1_E_ctrl_rdctl_inst, F1_data_out);

--DE1L62Q is std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|data_to_cpu[4]~44 at LC_X38_Y28_N1

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

DE1L62Q_lut_out = GND;

DE1L62Q = DFFEAS(DE1L62Q_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , DE1_TOE, , , VCC);

--DE1L294Q is std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|rx_holding_reg[0]~2396 at LC_X40_Y29_N3

--operation mode is normal

DE1L294Q_lut_out = DE1_shift_reg[0];

DE1L294Q = DFFEAS(DE1L294Q_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , DE1L302, , , , );

--DE1L53Q is std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|data_to_cpu[0]~50 at LC_X39_Y28_N2

--operation mode is normal

DE1L53Q_lut_out = DE1L294Q;

DE1L53Q = DFFEAS(DE1L53Q_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--DE1L54Q is std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|data_to_cpu[0]~51 at LC_X37_Y28_N5

--operation mode is normal

DE1L54Q_lut_out = DE1L216Q;

DE1L54Q = DFFEAS(DE1L54Q_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--T1L531 is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|r_1~241 at LC_X31_Y27_N9

--operation mode is normal

T1L531 = !Y1_ext_flash_s1_wait_counter[1] & !Y1L396Q & (!Y1L387Q);

--Y1L978 is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|LessThan1~92 at LC_X32_Y26_N9

--operation mode is normal

Y1L978 = Y1L879Q # !Y1L885Q & Y1L880Q & !Y1L878Q;

--Y1L700Q is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_avalon_slave_arb_share_counter[0]~608 at LC_X32_Y26_N0

--operation mode is normal

Y1L700Q_lut_out = Y1L188 # !Y1L177 & (!Y1L739 # !S1L1686Q);

Y1L700Q = DFFEAS(Y1L700Q_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--Y1L559 is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_avalon_slave_arb_addend[0]~796 at LC_X31_Y23_N4

--operation mode is normal

Y1L559 = !Y1L726 & (Y1L736 # Y1L96 # !Y1L578);

--U1L15 is std_1c20:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_read_but_no_slave_selected~62_DUP_COMB at LC_X29_Y22_N3

--operation mode is normal

U1L15 = S1_D_ic_fill_starting # S1L1501 & (!S1L1499 # !S1L1526);

--S1L1502Q is std_1c20:inst|cpu:the_cpu|ic_fill_ap_cnt[0]~45 at LC_X29_Y22_N3

--operation mode is normal

S1L1502Q = AMPP_FUNCTION(QC2__clk0, S1L1526, S1_D_ic_fill_starting, S1L1501, S1L1499, F1_data_out);

--DE1L47 is std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|data_to_cpu[0]~38_DUP_COMB at LC_X37_Y26_N5

--operation mode is normal

DE1L47 = X1L33 & DE1L21 & !X1L28;

--Y1L754Q is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_avalon_slave_saved_chosen_master_vector[1]~748 at LC_X31_Y20_N5

--operation mode is normal

Y1L754Q_lut_out = Y1L146 & (Y1L750 # !Y1_ext_ram_bus_avalon_slave_arbitration_holdoff_internal & Y1L932);

Y1L754Q = DFFEAS(Y1L754Q_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--Y1L969 is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|last_cycle_cpu_instruction_master_granted_slave_lan91c111_s1~5_DUP_COMB at LC_X31_Y19_N8

--operation mode is normal

Y1L969 = Y1L870 & (Y1L603 # Y1L965 & !Y1_ext_ram_bus_avalon_slave_arbitration_holdoff_internal);

--S1L1626Q is std_1c20:inst|cpu:the_cpu|ic_fill_tag[9]~108 at LC_X31_Y19_N8

--operation mode is normal

S1L1626Q = AMPP_FUNCTION(QC2__clk0, Y1L965, Y1L870, Y1_ext_ram_bus_avalon_slave_arbitration_holdoff_internal, Y1L603, F1_data_out);

--Y1L200 is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_ext_ram_bus_avalon_slave_end_xfer~4_DUP_COMB at LC_X31_Y25_N2

--operation mode is normal

Y1L200 = !Y1L188 & (Y1L177 # S1L1686Q & Y1L737);

--Y1L819Q is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_avalon_slave_slavearbiterlockenable~202 at LC_X31_Y21_N8

--operation mode is normal

Y1L819Q_lut_out = Y1L1014 & (Y1L512 & Y1L813 # !Y1L512 & (Y1L812)) # !Y1L1014 & Y1L813;

Y1L819Q = DFFEAS(Y1L819Q_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--Y1L905 is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|last_cycle_cpu_data_master_granted_slave_ext_flash_s1~9_DUP_COMB at LC_X29_Y23_N7

--operation mode is normal

Y1L905 = Y1L100 & (Y1L34 # Y1L37);

--Y1L916 is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|last_cycle_cpu_data_master_granted_slave_ext_ram_s1~9_DUP_COMB at LC_X29_Y23_N3

--operation mode is normal

Y1L916 = Y1L104 & (Y1L51 # Y1L53);

--WE1L61Q is std_1c20:inst|sdram_s1_arbitrator:the_sdram_s1|rdv_fifo_for_cpu_instruction_master_to_sdram_s1_module:rdv_fifo_for_cpu_instruction_master_to_sdram_s1|stage_6~5 at LC_X22_Y25_N4

--operation mode is normal

WE1L61Q_lut_out = WE1L26 & (NB1L24) # !WE1L26 & WE1L61Q;

WE1L61Q = DFFEAS(WE1L61Q_lut_out, GLOBAL(QC2__clk0), VCC, , , , , , );

--Y1L528Q is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_avalon_slave_arb_addend[0]~751 at LC_X31_Y26_N4

--operation mode is normal

Y1L528Q_lut_out = Y1L645 & (Y1L730) # !Y1L645 & Y1L528Q;

Y1L528Q = DFFEAS(Y1L528Q_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--Y1L532Q is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_avalon_slave_arb_addend[0]~753 at LC_X31_Y26_N7

--operation mode is normal

Y1L532Q_lut_out = Y1L645 & (Y1L177) # !Y1L645 & Y1L532Q;

Y1L532Q = DFFEAS(Y1L532Q_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--Y1L565 is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_avalon_slave_arb_addend[0]~802 at LC_X32_Y25_N2

--operation mode is normal

Y1L565 = Y1L696 & (Y1L582 & (Y1L536Q) # !Y1L582 & Y1L762) # !Y1L696 & Y1L762;

--Y1L536Q is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_avalon_slave_arb_addend[0]~755 at LC_X32_Y25_N2

--operation mode is normal

Y1L536Q = DFFEAS(Y1L565, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--Y1L539Q is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_avalon_slave_arb_addend[0]~757 at LC_X31_Y23_N2

--operation mode is normal

Y1L539Q_lut_out = Y1L644 & (Y1L770) # !Y1L644 & Y1L539Q;

Y1L539Q = DFFEAS(Y1L539Q_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--Y1L568 is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_avalon_slave_arb_addend[0]~805 at LC_X32_Y25_N6

--operation mode is normal

Y1L568 = Y1L696 & (Y1L582 & Y1L543Q # !Y1L582 & (Y1L746)) # !Y1L696 & (Y1L746);

--Y1L543Q is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_avalon_slave_arb_addend[0]~759 at LC_X32_Y25_N6

--operation mode is normal

Y1L543Q = DFFEAS(Y1L568, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--Y1L546Q is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_avalon_slave_arb_addend[0]~761 at LC_X31_Y19_N2

--operation mode is normal

Y1L546Q_lut_out = Y1L645 & (Y1L739) # !Y1L645 & Y1L546Q;

Y1L546Q = DFFEAS(Y1L546Q_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--Y1L571 is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_avalon_slave_arb_addend[0]~808 at LC_X31_Y25_N8

--operation mode is normal

Y1L571 = Y1L645 & Y1L774 # !Y1L645 & (Y1L550Q);

--Y1L550Q is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_avalon_slave_arb_addend[0]~763 at LC_X31_Y25_N8

--operation mode is normal

Y1L550Q = DFFEAS(Y1L571, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--Y1L570 is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_avalon_slave_arb_addend[0]~807 at LC_X30_Y25_N1

--operation mode is normal

Y1L570 = Y1L585 & (Y1L696 & Y1L553Q # !Y1L696 & (Y1L587)) # !Y1L585 & (Y1L587);

--Y1L553Q is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_avalon_slave_arb_addend[0]~765 at LC_X30_Y25_N1

--operation mode is normal

Y1L553Q = DFFEAS(Y1L570, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--S1L1617 is std_1c20:inst|cpu:the_cpu|ic_fill_tag[9]~82 at LC_X27_Y22_N0

--operation mode is normal

S1L1617 = AMPP_FUNCTION(S1_D_pc[19], S1_D_pc[23], S1_D_pc[18], S1_D_pc[20]);

--S1L1598 is std_1c20:inst|cpu:the_cpu|ic_fill_tag[6]~80 at LC_X26_Y21_N5

--operation mode is normal

S1L1598 = AMPP_FUNCTION(S1_D_pc[22], S1_D_pc[21], S1_D_pc[17], S1_D_pc[16]);

--S1L1619 is std_1c20:inst|cpu:the_cpu|ic_fill_tag[9]~86 at LC_X27_Y22_N2

--operation mode is normal

S1L1619 = AMPP_FUNCTION(S1_D_pc[19], S1_D_pc[20], S1_D_pc[23]);

--Y1L126Q is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|cpu_data_master_read_data_valid_ext_ram_s1_shift_register[0]~22 at LC_X33_Y25_N0

--operation mode is normal

Y1L126Q_lut_out = S1L1682 & (Y1L125 # Y1_cpu_data_master_read_data_valid_ext_ram_s1_shift_register[0]);

Y1L126Q = DFFEAS(Y1L126Q_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--Y1L562 is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_avalon_slave_arb_addend[0]~799 at LC_X31_Y23_N9

--operation mode is normal

Y1L562 = Y1L644 & (Y1L559) # !Y1L644 & Y1L556Q;

--Y1L556Q is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_avalon_slave_arb_addend[0]~795 at LC_X31_Y23_N9

--operation mode is normal

Y1L556Q = DFFEAS(Y1L562, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--S1L1639 is std_1c20:inst|cpu:the_cpu|ic_fill_tag[12]~72 at LC_X27_Y22_N5

--operation mode is normal

S1L1639 = AMPP_FUNCTION(S1_D_pc[22], S1L1636Q, S1_D_ic_fill_starting);

--S1L1636Q is std_1c20:inst|cpu:the_cpu|ic_fill_tag[12]~65 at LC_X27_Y22_N5

--operation mode is normal

S1L1636Q = AMPP_FUNCTION(QC2__clk0, S1_D_pc[22], S1L1636Q, S1_D_ic_fill_starting, F1_data_out);

--S1L1634 is std_1c20:inst|cpu:the_cpu|ic_fill_tag[11]~71 at LC_X27_Y21_N5

--operation mode is normal

S1L1634 = AMPP_FUNCTION(S1_D_ic_fill_starting, S1L1633Q, S1_D_pc[21]);

--S1L1633Q is std_1c20:inst|cpu:the_cpu|ic_fill_tag[11]~66 at LC_X27_Y21_N5

--operation mode is normal

S1L1633Q = AMPP_FUNCTION(QC2__clk0, S1_D_ic_fill_starting, S1L1633Q, S1_D_pc[21], F1_data_out);

--S1L1642Q is std_1c20:inst|cpu:the_cpu|ic_fill_tag[13]~67 at LC_X27_Y22_N4

--operation mode is normal

S1L1642Q = AMPP_FUNCTION(QC2__clk0, S1L1642Q, S1_D_pc[23], S1_D_ic_fill_starting, F1_data_out);

--S1L2180 is std_1c20:inst|cpu:the_cpu|M_mem_byte_en[3]~129 at LC_X34_Y20_N8

--operation mode is normal

S1L2180 = AMPP_FUNCTION(S1L2175, S1L2182, YC1_result[0], YC1_result[1]);

--S1L2177Q is std_1c20:inst|cpu:the_cpu|M_mem_byte_en[3]~120 at LC_X34_Y20_N8

--operation mode is normal

S1L2177Q = AMPP_FUNCTION(QC2__clk0, S1L2175, S1L2182, YC1_result[0], YC1_result[1], F1_data_out);

--S1L2171 is std_1c20:inst|cpu:the_cpu|M_mem_byte_en[2]~128 at LC_X34_Y20_N3

--operation mode is normal

S1L2171 = AMPP_FUNCTION(S1L2173, YC1_result[0], S1L2175, YC1_result[1]);

--S1L2168Q is std_1c20:inst|cpu:the_cpu|M_mem_byte_en[2]~122 at LC_X34_Y20_N3

--operation mode is normal

S1L2168Q = AMPP_FUNCTION(QC2__clk0, S1L2173, YC1_result[0], S1L2175, YC1_result[1], F1_data_out);

--S1L2161 is std_1c20:inst|cpu:the_cpu|M_mem_byte_en[1]~131 at LC_X28_Y20_N1

--operation mode is normal

S1L2161 = AMPP_FUNCTION(YC1_result[1], S1L2156, YC1_result[0], S1L2165);

--S1L2158Q is std_1c20:inst|cpu:the_cpu|M_mem_byte_en[1]~124 at LC_X28_Y20_N1

--operation mode is normal

S1L2158Q = AMPP_FUNCTION(QC2__clk0, YC1_result[1], S1L2156, YC1_result[0], S1L2165, F1_data_out);

--S1L2152 is std_1c20:inst|cpu:the_cpu|M_mem_byte_en[0]~130 at LC_X28_Y20_N3

--operation mode is normal

S1L2152 = AMPP_FUNCTION(YC1_result[1], S1L2156, YC1_result[0], S1L2154);

--S1L2149Q is std_1c20:inst|cpu:the_cpu|M_mem_byte_en[0]~126 at LC_X28_Y20_N3

--operation mode is normal

S1L2149Q = AMPP_FUNCTION(QC2__clk0, YC1_result[1], S1L2156, YC1_result[0], S1L2154, F1_data_out);

--S1L1588 is std_1c20:inst|cpu:the_cpu|ic_fill_tag[4]~76 at LC_X28_Y21_N9

--operation mode is normal

S1L1588 = AMPP_FUNCTION(S1L1587Q, S1_D_pc[14], S1_D_ic_fill_starting);

--S1L1587Q is std_1c20:inst|cpu:the_cpu|ic_fill_tag[4]~68 at LC_X28_Y21_N9

--operation mode is normal

S1L1587Q = AMPP_FUNCTION(QC2__clk0, S1L1587Q, S1_D_pc[14], S1_D_ic_fill_starting, F1_data_out);

--S1L1584 is std_1c20:inst|cpu:the_cpu|ic_fill_tag[3]~75 at LC_X29_Y20_N8

--operation mode is normal

S1L1584 = AMPP_FUNCTION(S1L1583Q, S1_D_ic_fill_starting, S1_D_pc[13]);

--S1L1583Q is std_1c20:inst|cpu:the_cpu|ic_fill_tag[3]~69 at LC_X29_Y20_N8

--operation mode is normal

S1L1583Q = AMPP_FUNCTION(QC2__clk0, S1L1583Q, S1_D_ic_fill_starting, S1_D_pc[13], F1_data_out);

--S1L1581 is std_1c20:inst|cpu:the_cpu|ic_fill_tag[2]~74 at LC_X27_Y20_N7

--operation mode is normal

S1L1581 = AMPP_FUNCTION(S1L1580Q, S1_D_pc[12], S1_D_ic_fill_starting);

--S1L1580Q is std_1c20:inst|cpu:the_cpu|ic_fill_tag[2]~70 at LC_X27_Y20_N7

--operation mode is normal

S1L1580Q = AMPP_FUNCTION(QC2__clk0, S1L1580Q, S1_D_pc[12], S1_D_ic_fill_starting, F1_data_out);

--S1L1785 is std_1c20:inst|cpu:the_cpu|M_alu_result[20]~344 at LC_X31_Y20_N8

--operation mode is normal

S1L1785 = AMPP_FUNCTION(S1_E_ctrl_dst_data_sel_logic_result, S1L1789, S1L1791, S1L1795);

--S1L1782Q is std_1c20:inst|cpu:the_cpu|M_alu_result[20]~319 at LC_X31_Y20_N8

--operation mode is normal

S1L1782Q = AMPP_FUNCTION(QC2__clk0, S1_E_ctrl_dst_data_sel_logic_result, S1L1789, S1L1791, S1L1795, F1_data_out);

--S1L1803 is std_1c20:inst|cpu:the_cpu|M_alu_result[21]~340 at LC_X31_Y18_N8

--operation mode is normal

S1L1803 = AMPP_FUNCTION(S1L1789, S1_E_ctrl_dst_data_sel_logic_result, S1L1812, S1L1808);

--S1L1800Q is std_1c20:inst|cpu:the_cpu|M_alu_result[21]~321 at LC_X31_Y18_N8

--operation mode is normal

S1L1800Q = AMPP_FUNCTION(QC2__clk0, S1L1789, S1_E_ctrl_dst_data_sel_logic_result, S1L1812, S1L1808, F1_data_out);

--S1L1855 is std_1c20:inst|cpu:the_cpu|M_alu_result[24]~339 at LC_X32_Y21_N7

--operation mode is normal

S1L1855 = AMPP_FUNCTION(S1L1789, S1_E_ctrl_dst_data_sel_logic_result, S1L1864, S1L1860);

--S1L1850Q is std_1c20:inst|cpu:the_cpu|M_alu_result[24]~323 at LC_X32_Y21_N7

--operation mode is normal

S1L1850Q = AMPP_FUNCTION(QC2__clk0, S1L1789, S1_E_ctrl_dst_data_sel_logic_result, S1L1864, S1L1860, F1_data_out);

--S1L1870Q is std_1c20:inst|cpu:the_cpu|M_alu_result[25]~325 at LC_X32_Y18_N0

--operation mode is normal

S1L1870Q = AMPP_FUNCTION(QC2__clk0, S1_E_ctrl_dst_data_sel_logic_result, S1L1879, S1L1789, S1L1883, F1_data_out);

--S1L1892 is std_1c20:inst|cpu:the_cpu|M_alu_result[26]~345 at LC_X36_Y12_N3

--operation mode is normal

S1L1892 = AMPP_FUNCTION(S1L1907, S1L1911, S1L1913, YC1_result[26]);

--S1L1891Q is std_1c20:inst|cpu:the_cpu|M_alu_result[26]~327 at LC_X36_Y12_N3

--operation mode is normal

S1L1891Q = AMPP_FUNCTION(QC2__clk0, S1L1907, S1L1911, S1L1913, YC1_result[26], F1_data_out);

--S1L1917 is std_1c20:inst|cpu:the_cpu|M_alu_result[27]~346 at LC_X37_Y12_N2

--operation mode is normal

S1L1917 = AMPP_FUNCTION(S1L1936, S1L1938, YC1_result[27], S1L1932);

--S1L1916Q is std_1c20:inst|cpu:the_cpu|M_alu_result[27]~329 at LC_X37_Y12_N2

--operation mode is normal

S1L1916Q = AMPP_FUNCTION(QC2__clk0, S1L1936, S1L1938, YC1_result[27], S1L1932, F1_data_out);

--S1L1942 is std_1c20:inst|cpu:the_cpu|M_alu_result[28]~347 at LC_X35_Y12_N3

--operation mode is normal

S1L1942 = AMPP_FUNCTION(S1L1960, S1L1962, S1L1956, YC1_result[28]);

--S1L1941Q is std_1c20:inst|cpu:the_cpu|M_alu_result[28]~331 at LC_X35_Y12_N3

--operation mode is normal

S1L1941Q = AMPP_FUNCTION(QC2__clk0, S1L1960, S1L1962, S1L1956, YC1_result[28], F1_data_out);

--S1L1966 is std_1c20:inst|cpu:the_cpu|M_alu_result[29]~348 at LC_X34_Y12_N4

--operation mode is normal

S1L1966 = AMPP_FUNCTION(S1L1986, YC1_result[29], S1L1984, S1L1980);

--S1L1965Q is std_1c20:inst|cpu:the_cpu|M_alu_result[29]~333 at LC_X34_Y12_N4

--operation mode is normal

S1L1965Q = AMPP_FUNCTION(QC2__clk0, S1L1986, YC1_result[29], S1L1984, S1L1980, F1_data_out);

--S1L1833Q is std_1c20:inst|cpu:the_cpu|M_alu_result[23]~335 at LC_X34_Y21_N8

--operation mode is normal

S1L1833Q = AMPP_FUNCTION(QC2__clk0, S1L1789, S1L1842, S1_E_ctrl_dst_data_sel_logic_result, S1L1846, F1_data_out);

--S1L1819 is std_1c20:inst|cpu:the_cpu|M_alu_result[22]~341 at LC_X32_Y16_N2

--operation mode is normal

S1L1819 = AMPP_FUNCTION(S1_E_ctrl_dst_data_sel_logic_result, S1L1829, S1L1823, S1L1825);

--S1L1816Q is std_1c20:inst|cpu:the_cpu|M_alu_result[22]~337 at LC_X32_Y16_N2

--operation mode is normal

S1L1816Q = AMPP_FUNCTION(QC2__clk0, S1_E_ctrl_dst_data_sel_logic_result, S1L1829, S1L1823, S1L1825, F1_data_out);

--S1L1569 is std_1c20:inst|cpu:the_cpu|ic_fill_tag[0]~89 at LC_X26_Y21_N8

--operation mode is normal

S1L1569 = AMPP_FUNCTION(S1L1568Q, S1_D_pc[10], S1_D_ic_fill_starting);

--S1L1568Q is std_1c20:inst|cpu:the_cpu|ic_fill_tag[0]~77 at LC_X26_Y21_N8

--operation mode is normal

S1L1568Q = AMPP_FUNCTION(QC2__clk0, S1L1568Q, S1_D_pc[10], S1_D_ic_fill_starting, F1_data_out);

--S1L1578 is std_1c20:inst|cpu:the_cpu|ic_fill_tag[1]~88 at LC_X25_Y19_N5

--operation mode is normal

S1L1578 = AMPP_FUNCTION(S1_D_pc[11], S1_D_ic_fill_starting, S1L1577Q);

--S1L1577Q is std_1c20:inst|cpu:the_cpu|ic_fill_tag[1]~78 at LC_X25_Y19_N5

--operation mode is normal

S1L1577Q = AMPP_FUNCTION(QC2__clk0, S1_D_pc[11], S1_D_ic_fill_starting, S1L1577Q, F1_data_out);

--S1L1599 is std_1c20:inst|cpu:the_cpu|ic_fill_tag[6]~93 at LC_X28_Y21_N4

--operation mode is normal

S1L1599 = AMPP_FUNCTION(S1L1598, S1L1597Q, S1_D_ic_fill_starting);

--S1L1597Q is std_1c20:inst|cpu:the_cpu|ic_fill_tag[6]~79 at LC_X28_Y21_N4

--operation mode is normal

S1L1597Q = AMPP_FUNCTION(QC2__clk0, S1L1598, S1L1597Q, S1_D_ic_fill_starting, F1_data_out);

--S1L1620 is std_1c20:inst|cpu:the_cpu|ic_fill_tag[9]~92 at LC_X28_Y22_N2

--operation mode is normal

S1L1620 = AMPP_FUNCTION(S1L1616Q, S1L1617, S1_D_ic_fill_starting);

--S1L1616Q is std_1c20:inst|cpu:the_cpu|ic_fill_tag[9]~81 at LC_X28_Y22_N2

--operation mode is normal

S1L1616Q = AMPP_FUNCTION(QC2__clk0, S1L1616Q, S1L1617, S1_D_ic_fill_starting, F1_data_out);

--S1L1591 is std_1c20:inst|cpu:the_cpu|ic_fill_tag[4]~91 at LC_X29_Y20_N0

--operation mode is normal

S1L1591 = AMPP_FUNCTION(S1L1589Q, S1_D_pc[14], S1_D_ic_fill_starting, S1_D_pc[15]);

--S1L1589Q is std_1c20:inst|cpu:the_cpu|ic_fill_tag[4]~83 at LC_X29_Y20_N0

--operation mode is normal

S1L1589Q = AMPP_FUNCTION(QC2__clk0, S1L1589Q, S1_D_pc[14], S1_D_ic_fill_starting, S1_D_pc[15], F1_data_out);

--S1L1621 is std_1c20:inst|cpu:the_cpu|ic_fill_tag[9]~96 at LC_X28_Y21_N1

--operation mode is normal

S1L1621 = AMPP_FUNCTION(S1L1618Q, S1L1619, S1_D_ic_fill_starting);

--S1L1618Q is std_1c20:inst|cpu:the_cpu|ic_fill_tag[9]~85 at LC_X28_Y21_N1

--operation mode is normal

S1L1618Q = AMPP_FUNCTION(QC2__clk0, S1L1618Q, S1L1619, S1_D_ic_fill_starting, F1_data_out);

--S1L1610 is std_1c20:inst|cpu:the_cpu|ic_fill_tag[8]~95 at LC_X24_Y20_N7

--operation mode is normal

S1L1610 = AMPP_FUNCTION(S1L1609Q, S1_D_pc[18], S1_D_ic_fill_starting);

--S1L1609Q is std_1c20:inst|cpu:the_cpu|ic_fill_tag[8]~87 at LC_X24_Y20_N7

--operation mode is normal

S1L1609Q = AMPP_FUNCTION(QC2__clk0, S1L1609Q, S1_D_pc[18], S1_D_ic_fill_starting, F1_data_out);

--S1L210Q is std_1c20:inst|cpu:the_cpu|av_ld_data_aligned_or_div[25]~126 at LC_X29_Y21_N2

--operation mode is normal

S1L210Q = AMPP_FUNCTION(QC2__clk0, S1L1867, S1L208, S1L1696, T1L449, F1_data_out);

--S1L2063 is std_1c20:inst|cpu:the_cpu|M_ctrl_shift_rot~5 at LC_X38_Y16_N2

--operation mode is normal

S1L2063 = AMPP_FUNCTION(S1_E_ctrl_shift_rot, S1L2056Q, S1_W_stall);

--S1L2056Q is std_1c20:inst|cpu:the_cpu|M_ctrl_shift_rot~4 at LC_X38_Y16_N2

--operation mode is normal

S1L2056Q = AMPP_FUNCTION(QC2__clk0, S1_E_ctrl_shift_rot, S1L2056Q, S1_W_stall, F1_data_out);

--S1L1593Q is std_1c20:inst|cpu:the_cpu|ic_fill_tag[5]~101 at LC_X28_Y21_N5

--operation mode is normal

S1L1593Q = AMPP_FUNCTION(QC2__clk0, S1_D_ic_fill_starting, S1_D_pc[15], S1L1593Q, F1_data_out);

--S1L1895 is std_1c20:inst|cpu:the_cpu|M_alu_result[26]~354_BDD1 at LC_X36_Y12_N9

--operation mode is normal

S1L1895 = AMPP_FUNCTION(S1_E_ctrl_dst_data_sel_logic_result, S1_E_ctrl_rdctl_inst);

--S1L1920 is std_1c20:inst|cpu:the_cpu|M_alu_result[27]~358_BDD5 at LC_X37_Y12_N5

--operation mode is normal

S1L1920 = AMPP_FUNCTION(S1_E_ctrl_rdctl_inst, S1_E_ctrl_dst_data_sel_logic_result);

--S1L1876 is std_1c20:inst|cpu:the_cpu|M_alu_result[25]~369_BDD19 at LC_X32_Y18_N1

--operation mode is normal

S1L1876 = AMPP_FUNCTION(S1L1870Q, S1_W_stall);

--S1L1879 is std_1c20:inst|cpu:the_cpu|M_alu_result[25]~371_BDD21 at LC_X32_Y18_N8

--operation mode is normal

S1L1879 = AMPP_FUNCTION(S1_E_ctrl_dst_data_sel_pc_plus_one, S1_E_extra_pc[23], YC1_result[25]);

--S1L1881 is std_1c20:inst|cpu:the_cpu|M_alu_result[25]~372_BDD22 at LC_X34_Y14_N9

--operation mode is normal

S1L1881 = AMPP_FUNCTION(S1_E_logic_op[1], S1_E_logic_op[0], S1L878, S1L1040);

--S1L1883 is std_1c20:inst|cpu:the_cpu|M_alu_result[25]~373_BDD23 at LC_X32_Y18_N5

--operation mode is normal

S1L1883 = AMPP_FUNCTION(S1L1876, S1_E_ctrl_dst_data_sel_logic_result, S1L1789, S1L1881);

--S1L1857 is std_1c20:inst|cpu:the_cpu|M_alu_result[24]~375_BDD25 at LC_X33_Y20_N3

--operation mode is normal

S1L1857 = AMPP_FUNCTION(S1L1866Q, S1_W_stall);

--S1L1860 is std_1c20:inst|cpu:the_cpu|M_alu_result[24]~377_BDD27 at LC_X32_Y17_N2

--operation mode is normal

S1L1860 = AMPP_FUNCTION(S1_E_ctrl_dst_data_sel_pc_plus_one, S1_E_extra_pc[22], YC1_result[24]);

--S1L1862 is std_1c20:inst|cpu:the_cpu|M_alu_result[24]~378_BDD28 at LC_X34_Y17_N0

--operation mode is normal

S1L1862 = AMPP_FUNCTION(S1_E_logic_op[1], S1L877, S1L1035, S1_E_logic_op[0]);

--S1L1864 is std_1c20:inst|cpu:the_cpu|M_alu_result[24]~379_BDD29 at LC_X33_Y20_N1

--operation mode is normal

S1L1864 = AMPP_FUNCTION(S1_E_ctrl_dst_data_sel_logic_result, S1L1862, S1L1789, S1L1857);

--KB1L738 is std_1c20:inst|sdram:the_sdram|Mux108~1500_BDD31 at LC_X14_Y21_N3

--operation mode is normal

KB1L738 = KB1_m_state[6] & (!KB1L729) # !KB1_m_state[6] & KB1_m_state[1] & (!KB1L730);

--KB1L740 is std_1c20:inst|sdram:the_sdram|Mux108~1501_BDD32 at LC_X14_Y21_N0

--operation mode is normal

KB1L740 = KB1_m_state[6] & (!KB1L729) # !KB1_m_state[6] & KB1_m_state[1] & (KB1L730);

--KB1L742 is std_1c20:inst|sdram:the_sdram|Mux108~1502_BDD33 at LC_X14_Y22_N3

--operation mode is normal

KB1L742 = KB1_m_state[6] & (KB1L729);

--KB1L744 is std_1c20:inst|sdram:the_sdram|Mux108~1503_BDD34 at LC_X15_Y21_N0

--operation mode is normal

KB1L744 = KB1_m_state[4] $ KB1_m_state[3];

--KB1L747 is std_1c20:inst|sdram:the_sdram|Mux108~1505_BDD36 at LC_X14_Y21_N1

--operation mode is normal

KB1L747 = !KB1L738 & (KB1_m_state[0] # KB1L731 & !KB1L740);

--S1L1839 is std_1c20:inst|cpu:the_cpu|M_alu_result[23]~381_BDD40 at LC_X34_Y21_N0

--operation mode is normal

S1L1839 = AMPP_FUNCTION(T1L448Q, S1_W_stall);

--S1L1842 is std_1c20:inst|cpu:the_cpu|M_alu_result[23]~383_BDD42 at LC_X32_Y17_N4

--operation mode is normal

S1L1842 = AMPP_FUNCTION(S1_E_ctrl_dst_data_sel_pc_plus_one, S1_E_extra_pc[21], YC1_result[23]);

--S1L1844 is std_1c20:inst|cpu:the_cpu|M_alu_result[23]~384_BDD43 at LC_X34_Y16_N5

--operation mode is normal

S1L1844 = AMPP_FUNCTION(S1L1030, S1_E_logic_op[0], S1_E_logic_op[1], S1L876);

--S1L1846 is std_1c20:inst|cpu:the_cpu|M_alu_result[23]~385_BDD44 at LC_X34_Y21_N6

--operation mode is normal

S1L1846 = AMPP_FUNCTION(S1_E_ctrl_dst_data_sel_logic_result, S1L1839, S1L1789, S1L1844);

--S1L2024 is std_1c20:inst|cpu:the_cpu|M_alu_result[31]~387_BDD46 at LC_X35_Y12_N6

--operation mode is normal

S1L2024 = AMPP_FUNCTION(S1_E_ctrl_rdctl_inst, S1_E_ctrl_dst_data_sel_pc_plus_one, S1L884, S1_E_ctrl_dst_data_sel_logic_result);

--S1L2026 is std_1c20:inst|cpu:the_cpu|M_alu_result[31]~388_BDD47 at LC_X33_Y12_N2

--operation mode is normal

S1L2026 = AMPP_FUNCTION(S1_E_ctrl_dst_data_sel_logic_result, S1_E_ctrl_rdctl_inst);

--S1L2028 is std_1c20:inst|cpu:the_cpu|M_alu_result[31]~389_BDD48 at LC_X34_Y13_N9

--operation mode is normal

S1L2028 = AMPP_FUNCTION(S1L2000, S1L2024, S1_E_logic_op[0], S1L1070);

--S1L2030 is std_1c20:inst|cpu:the_cpu|M_alu_result[31]~390_BDD49 at LC_X34_Y13_N0

--operation mode is normal

S1L2030 = AMPP_FUNCTION(S1L2000, S1L2024, S1_E_logic_op[0], S1L1070);

--S1L1998 is std_1c20:inst|cpu:the_cpu|M_alu_result[30]~391_BDD50 at LC_X34_Y14_N1

--operation mode is normal

S1L1998 = AMPP_FUNCTION(S1L883, S1_E_ctrl_dst_data_sel_logic_result, S1_E_ctrl_rdctl_inst, S1_E_ctrl_dst_data_sel_pc_plus_one);

--S1L2000 is std_1c20:inst|cpu:the_cpu|M_alu_result[30]~392_BDD51 at LC_X34_Y14_N2

--operation mode is normal

S1L2000 = AMPP_FUNCTION(S1_E_ctrl_rdctl_inst, S1_E_ctrl_dst_data_sel_logic_result);

--S1L2002 is std_1c20:inst|cpu:the_cpu|M_alu_result[30]~393_BDD52 at LC_X34_Y14_N5

--operation mode is normal

S1L2002 = AMPP_FUNCTION(S1L2000, S1_E_logic_op[0], S1L1065, S1L1998);

--S1L2004 is std_1c20:inst|cpu:the_cpu|M_alu_result[30]~394_BDD53 at LC_X34_Y14_N8

--operation mode is normal

S1L2004 = AMPP_FUNCTION(S1L2000, S1_E_logic_op[0], S1L1065, S1L1998);

--S1L1821 is std_1c20:inst|cpu:the_cpu|M_alu_result[22]~395_BDD54 at LC_X32_Y16_N1

--operation mode is normal

S1L1821 = AMPP_FUNCTION(S1L1816Q, S1_W_stall);

--S1L1823 is std_1c20:inst|cpu:the_cpu|M_alu_result[22]~396_BDD55 at LC_X32_Y16_N8

--operation mode is normal

S1L1823 = AMPP_FUNCTION(S1_E_ctrl_rdctl_inst, S1_E_ctrl_dst_data_sel_cmp, S1_W_stall);

--S1L1825 is std_1c20:inst|cpu:the_cpu|M_alu_result[22]~397_BDD56 at LC_X31_Y16_N6

--operation mode is normal

S1L1825 = AMPP_FUNCTION(S1_E_ctrl_dst_data_sel_pc_plus_one, YC1_result[22], S1_E_extra_pc[20]);

--S1L1827 is std_1c20:inst|cpu:the_cpu|M_alu_result[22]~398_BDD57 at LC_X34_Y16_N1

--operation mode is normal

S1L1827 = AMPP_FUNCTION(S1L875, S1_E_logic_op[0], S1_E_logic_op[1], S1L1025);

--S1L1829 is std_1c20:inst|cpu:the_cpu|M_alu_result[22]~399_BDD58 at LC_X32_Y16_N5

--operation mode is normal

S1L1829 = AMPP_FUNCTION(S1_E_ctrl_dst_data_sel_logic_result, S1L1827, S1L1823, S1L1821);

--S1L1805 is std_1c20:inst|cpu:the_cpu|M_alu_result[21]~401_BDD60 at LC_X31_Y18_N9

--operation mode is normal

S1L1805 = AMPP_FUNCTION(S1_W_stall, S1L1800Q);

--S1L1808 is std_1c20:inst|cpu:the_cpu|M_alu_result[21]~403_BDD62 at LC_X31_Y18_N3

--operation mode is normal

S1L1808 = AMPP_FUNCTION(S1_E_ctrl_dst_data_sel_pc_plus_one, S1_E_extra_pc[19], YC1_result[21]);

--S1L1810 is std_1c20:inst|cpu:the_cpu|M_alu_result[21]~404_BDD63 at LC_X34_Y14_N6

--operation mode is normal

S1L1810 = AMPP_FUNCTION(S1_E_logic_op[1], S1_E_logic_op[0], S1L874, S1L1020);

--S1L1812 is std_1c20:inst|cpu:the_cpu|M_alu_result[21]~405_BDD64 at LC_X31_Y18_N7

--operation mode is normal

S1L1812 = AMPP_FUNCTION(S1L1805, S1_E_ctrl_dst_data_sel_logic_result, S1L1810, S1L1789);

--S1L1696 is std_1c20:inst|cpu:the_cpu|internal_d_write~77_BDD66 at LC_X32_Y21_N1

--operation mode is normal

S1L1696 = AMPP_FUNCTION(S1L1682, Y1_cpu_data_master_read_data_valid_ext_flash_s1_shift_register[0], Y1L119, S1L1687);

--T1L447Q is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|internal_cpu_data_master_dbs_address[1]~65 at LC_X32_Y21_N1

--operation mode is normal

T1L447Q = DFFEAS(S1L1696, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--S1L1787 is std_1c20:inst|cpu:the_cpu|M_alu_result[20]~407_BDD67 at LC_X34_Y21_N3

--operation mode is normal

S1L1787 = AMPP_FUNCTION(S1L1782Q, S1_W_stall);

--S1L1789 is std_1c20:inst|cpu:the_cpu|M_alu_result[20]~408_BDD68 at LC_X33_Y19_N8

--operation mode is normal

S1L1789 = AMPP_FUNCTION(S1_E_ctrl_rdctl_inst, S1_E_ctrl_dst_data_sel_cmp, S1_W_stall);

--S1L1791 is std_1c20:inst|cpu:the_cpu|M_alu_result[20]~409_BDD69 at LC_X32_Y17_N5

--operation mode is normal

S1L1791 = AMPP_FUNCTION(S1_E_ctrl_dst_data_sel_pc_plus_one, YC1_result[20], S1_E_extra_pc[18]);

--S1L1793 is std_1c20:inst|cpu:the_cpu|M_alu_result[20]~410_BDD70 at LC_X34_Y17_N4

--operation mode is normal

S1L1793 = AMPP_FUNCTION(S1_E_logic_op[0], S1L873, S1L1015, S1_E_logic_op[1]);

--S1L1795 is std_1c20:inst|cpu:the_cpu|M_alu_result[20]~411_BDD71 at LC_X32_Y17_N9

--operation mode is normal

S1L1795 = AMPP_FUNCTION(S1L1793, S1_E_ctrl_dst_data_sel_logic_result, S1L1787, S1L1823);

--S1L924 is std_1c20:inst|cpu:the_cpu|E_src2[0]~1535_BDD73 at LC_X37_Y16_N3

--operation mode is normal

S1L924 = AMPP_FUNCTION(S1_E_src2_prelim[0], S1_E_src2_imm[0], S1_E_src2_hazard_M, S1_E_ctrl_src2_is_imm);

--S1L926 is std_1c20:inst|cpu:the_cpu|E_src2[0]~1536_BDD74 at LC_X37_Y16_N7

--operation mode is normal

S1L926 = AMPP_FUNCTION(S1_E_src2_prelim[0], S1_E_src2_imm[0], S1_E_src2_hazard_M, S1_E_ctrl_src2_is_imm);

--S1L929 is std_1c20:inst|cpu:the_cpu|E_src2[1]~1537_BDD75 at LC_X40_Y16_N8

--operation mode is normal

S1L929 = AMPP_FUNCTION(S1_E_ctrl_src2_is_imm, S1_E_src2_hazard_M, S1_E_src2_prelim[1], S1_E_src2_imm[1]);

--S1L931 is std_1c20:inst|cpu:the_cpu|E_src2[1]~1538_BDD76 at LC_X40_Y16_N4

--operation mode is normal

S1L931 = AMPP_FUNCTION(S1_E_ctrl_src2_is_imm, S1_E_src2_hazard_M, S1_E_src2_prelim[1], S1_E_src2_imm[1]);

--S1L949 is std_1c20:inst|cpu:the_cpu|E_src2[5]~1539_BDD77 at LC_X39_Y18_N0

--operation mode is normal

S1L949 = AMPP_FUNCTION(S1_E_ctrl_src2_is_imm, S1_E_src2_prelim[5], S1_E_src2_hazard_M, S1_E_src2_imm[5]);

--S1L951 is std_1c20:inst|cpu:the_cpu|E_src2[5]~1540_BDD78 at LC_X39_Y18_N9

--operation mode is normal

S1L951 = AMPP_FUNCTION(S1_E_ctrl_src2_is_imm, S1_E_src2_prelim[5], S1_E_src2_hazard_M, S1_E_src2_imm[5]);

--S1L934 is std_1c20:inst|cpu:the_cpu|E_src2[2]~1541_BDD79 at LC_X39_Y15_N7

--operation mode is normal

S1L934 = AMPP_FUNCTION(S1_E_src2_prelim[2], S1_E_src2_hazard_M, S1_E_ctrl_src2_is_imm, S1_E_src2_imm[2]);

--S1L936 is std_1c20:inst|cpu:the_cpu|E_src2[2]~1542_BDD80 at LC_X39_Y15_N2

--operation mode is normal

S1L936 = AMPP_FUNCTION(S1_E_src2_prelim[2], S1_E_src2_hazard_M, S1_E_ctrl_src2_is_imm, S1_E_src2_imm[2]);

--S1L954 is std_1c20:inst|cpu:the_cpu|E_src2[6]~1543_BDD81 at LC_X36_Y17_N8

--operation mode is normal

S1L954 = AMPP_FUNCTION(S1_E_src2_imm[6], S1_E_src2_prelim[6], S1_E_ctrl_src2_is_imm, S1_E_src2_hazard_M);

--S1L956 is std_1c20:inst|cpu:the_cpu|E_src2[6]~1544_BDD82 at LC_X36_Y17_N0

--operation mode is normal

S1L956 = AMPP_FUNCTION(S1_E_src2_imm[6], S1_E_src2_prelim[6], S1_E_ctrl_src2_is_imm, S1_E_src2_hazard_M);

--S1L944 is std_1c20:inst|cpu:the_cpu|E_src2[4]~1545_BDD83 at LC_X41_Y16_N3

--operation mode is normal

S1L944 = AMPP_FUNCTION(S1_E_src2_prelim[4], S1_E_src2_hazard_M, S1_E_src2_imm[4], S1_E_ctrl_src2_is_imm);

--S1L946 is std_1c20:inst|cpu:the_cpu|E_src2[4]~1546_BDD84 at LC_X41_Y16_N7

--operation mode is normal

S1L946 = AMPP_FUNCTION(S1_E_src2_prelim[4], S1_E_src2_hazard_M, S1_E_src2_imm[4], S1_E_ctrl_src2_is_imm);

--S1L939 is std_1c20:inst|cpu:the_cpu|E_src2[3]~1547_BDD85 at LC_X39_Y16_N5

--operation mode is normal

S1L939 = AMPP_FUNCTION(S1_E_src2_imm[3], S1_E_ctrl_src2_is_imm, S1_E_src2_hazard_M, S1_E_src2_prelim[3]);

--S1L941 is std_1c20:inst|cpu:the_cpu|E_src2[3]~1548_BDD86 at LC_X39_Y16_N2

--operation mode is normal

S1L941 = AMPP_FUNCTION(S1_E_src2_imm[3], S1_E_ctrl_src2_is_imm, S1_E_src2_hazard_M, S1_E_src2_prelim[3]);

--S1L959 is std_1c20:inst|cpu:the_cpu|E_src2[7]~1549_BDD87 at LC_X41_Y17_N9

--operation mode is normal

S1L959 = AMPP_FUNCTION(S1_E_src2_hazard_M, S1_E_src2_prelim[7], S1_E_ctrl_src2_is_imm, S1_E_src2_imm[7]);

--S1L961 is std_1c20:inst|cpu:the_cpu|E_src2[7]~1550_BDD88 at LC_X41_Y17_N6

--operation mode is normal

S1L961 = AMPP_FUNCTION(S1_E_src2_hazard_M, S1_E_src2_prelim[7], S1_E_ctrl_src2_is_imm, S1_E_src2_imm[7]);

--S1L2182 is std_1c20:inst|cpu:the_cpu|M_mem_byte_en[3]~133_BDD91 at LC_X34_Y20_N0

--operation mode is normal

S1L2182 = AMPP_FUNCTION(S1_W_stall, S1L2177Q, S1_E_iw[4], S1_E_iw[3]);

--Y1L578 is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_avalon_slave_arb_addend[0]~828_BDD93 at LC_X31_Y23_N3

--operation mode is normal

Y1L578 = !Y1L905 & !Y1L742 & !Y1L770 & !Y1L799;

--S1L2173 is std_1c20:inst|cpu:the_cpu|M_mem_byte_en[2]~135_BDD102 at LC_X34_Y20_N6

--operation mode is normal

S1L2173 = AMPP_FUNCTION(S1_W_stall, S1L2168Q, S1_E_iw[4], S1_E_iw[3]);

--S1L2175 is std_1c20:inst|cpu:the_cpu|M_mem_byte_en[2]~136_BDD103 at LC_X34_Y20_N7

--operation mode is normal

S1L2175 = AMPP_FUNCTION(S1_W_stall, S1_E_iw[4]);

--Y1L660Q is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_avalon_slave_arb_addend[4]~960 at LC_X30_Y24_N3

--operation mode is normal

Y1L660Q_lut_out = Y1_WideOr6 & (Y1L587 & Y1L208) # !Y1_WideOr6 & Y1L623;

Y1L660Q = DFFEAS(Y1L660Q_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--Y1L629 is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_avalon_slave_arb_addend[3]~831_BDD106 at LC_X30_Y24_N1

--operation mode is normal

Y1L629 = Y1L711 & (Y1L770) # !Y1L711 & Y1L762;

--Y1L630Q is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_avalon_slave_arb_addend[3]~850 at LC_X30_Y24_N1

--operation mode is normal

Y1L630Q = DFFEAS(Y1L629, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--Y1L661Q is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_avalon_slave_arb_addend[4]~961 at LC_X31_Y24_N2

--operation mode is normal

Y1L661Q_lut_out = Y1L644 & (Y1L96 & Y1L654) # !Y1L644 & Y1L671;

Y1L661Q = DFFEAS(Y1L661Q_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--Y1L678Q is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_avalon_slave_arb_addend[5]~848 at LC_X31_Y24_N4

--operation mode is normal

Y1L678Q_lut_out = Y1L711 & (Y1L799) # !Y1L711 & Y1L792;

Y1L678Q = DFFEAS(Y1L678Q_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--Y1L659Q is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_avalon_slave_arb_addend[4]~957 at LC_X30_Y24_N5

--operation mode is normal

Y1L659Q_lut_out = Y1_WideOr6 & (Y1L799 & Y1L208) # !Y1_WideOr6 & Y1L642;

Y1L659Q = DFFEAS(Y1L659Q_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--Y1L655Q is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_avalon_slave_arb_addend[4]~846 at LC_X30_Y24_N6

--operation mode is normal

Y1L655Q_lut_out = Y1L711 & (Y1L587) # !Y1L711 & Y1L774;

Y1L655Q = DFFEAS(Y1L655Q_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--S1L2497 is std_1c20:inst|cpu:the_cpu|M_wr_data_unfiltered[31]~3741_BDD113 at LC_X34_Y13_N7

--operation mode is normal

S1L2497 = AMPP_FUNCTION(S1L2012, S1_W_stall, S1_av_ld_aligning_data, S1L2057);

--S1L2499 is std_1c20:inst|cpu:the_cpu|M_wr_data_unfiltered[31]~3742_BDD114 at LC_X34_Y13_N4

--operation mode is normal

S1L2499 = AMPP_FUNCTION(S1L2012, S1_W_stall, S1_av_ld_aligning_data, S1L2057);

--S1L2502 is std_1c20:inst|cpu:the_cpu|M_wr_data_unfiltered[31]~3744_BDD116 at LC_X34_Y13_N5

--operation mode is normal

S1L2502 = AMPP_FUNCTION(S1_E_ctrl_dst_data_sel_cmp, S1L228, S1L2499);

--S1L2504 is std_1c20:inst|cpu:the_cpu|M_wr_data_unfiltered[31]~3745_BDD117 at LC_X34_Y13_N1

--operation mode is normal

S1L2504 = AMPP_FUNCTION(S1L2499, S1_E_ctrl_dst_data_sel_cmp);

--S1L2484 is std_1c20:inst|cpu:the_cpu|M_wr_data_unfiltered[30]~3746_BDD118 at LC_X35_Y18_N3

--operation mode is normal

S1L2484 = AMPP_FUNCTION(S1_av_ld_aligning_data, S1L1991, S1L2063, S1_W_stall);

--S1L2486 is std_1c20:inst|cpu:the_cpu|M_wr_data_unfiltered[30]~3747_BDD119 at LC_X35_Y18_N7

--operation mode is normal

S1L2486 = AMPP_FUNCTION(S1_av_ld_aligning_data, S1L1991, S1L2063, S1_W_stall);

--S1L2488 is std_1c20:inst|cpu:the_cpu|M_wr_data_unfiltered[30]~3748_BDD120 at LC_X41_Y19_N4

--operation mode is normal

S1L2488 = AMPP_FUNCTION(S1_M_iw[4], S1L637, S1_M_ctrl_ld_signed, S1L239);

--S1L2490 is std_1c20:inst|cpu:the_cpu|M_wr_data_unfiltered[30]~3749_BDD121 at LC_X35_Y18_N9

--operation mode is normal

S1L2490 = AMPP_FUNCTION(S1L2486, S1_E_ctrl_dst_data_sel_cmp, S1L2488);

--S1L2492 is std_1c20:inst|cpu:the_cpu|M_wr_data_unfiltered[30]~3750_BDD122 at LC_X35_Y18_N5

--operation mode is normal

S1L2492 = AMPP_FUNCTION(S1L2486, S1_E_ctrl_dst_data_sel_cmp);

--U1L251 is std_1c20:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|r_0~69_BDD123 at LC_X33_Y24_N7

--operation mode is normal

U1L251 = !V1L39 & !V1L58 & U1L256 & X1L16;

--U1L253 is std_1c20:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|r_0~70_BDD124 at LC_X33_Y24_N2

--operation mode is normal

U1L253 = V1L39 & !V1L58 & U1L256 & X1L16;

--S1L2165 is std_1c20:inst|cpu:the_cpu|M_mem_byte_en[1]~137_BDD125 at LC_X28_Y20_N5

--operation mode is normal

S1L2165 = AMPP_FUNCTION(S1L2158Q, S1_E_iw[4], S1_E_iw[3], S1_W_stall);

--EB1L27 is std_1c20:inst|lcd_display_control_slave_arbitrator:the_lcd_display_control_slave|lcd_display_control_slave_in_a_write_cycle~50_BDD127 at LC_X36_Y25_N1

--operation mode is normal

EB1L27 = S1_internal_d_write & UB1L6 & (!S1_M_alu_result[5]);

--S1L2154 is std_1c20:inst|cpu:the_cpu|M_mem_byte_en[0]~139_BDD128 at LC_X28_Y20_N2

--operation mode is normal

S1L2154 = AMPP_FUNCTION(S1_W_stall, S1_E_iw[4], S1_E_iw[3], S1L2149Q);

--S1L2156 is std_1c20:inst|cpu:the_cpu|M_mem_byte_en[0]~140_BDD129 at LC_X28_Y20_N8

--operation mode is normal

S1L2156 = AMPP_FUNCTION(S1_E_iw[4], S1_W_stall);

--Y1L1009 is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|p1_read_n_to_the_ext_ram~63_BDD130 at LC_X27_Y21_N1

--operation mode is normal

Y1L1009 = S1L1621 & !S1L1610;

--S1L1628Q is std_1c20:inst|cpu:the_cpu|ic_fill_tag[9]~113 at LC_X27_Y21_N1

--operation mode is normal

S1L1628Q = AMPP_FUNCTION(QC2__clk0, S1L1621, S1L1610, F1_data_out);

--S1L1017 is std_1c20:inst|cpu:the_cpu|E_src2[20]~1559_BDD131 at LC_X39_Y14_N4

--operation mode is normal

S1L1017 = AMPP_FUNCTION(S1_E_src2_hazard_M, S1_E_src2_prelim[20], S1_E_ctrl_src2_is_imm, S1_E_src2_imm[20]);

--S1L1019 is std_1c20:inst|cpu:the_cpu|E_src2[20]~1560_BDD132 at LC_X39_Y14_N1

--operation mode is normal

S1L1019 = AMPP_FUNCTION(S1_E_src2_hazard_M, S1_E_src2_prelim[20], S1_E_ctrl_src2_is_imm, S1_E_src2_imm[20]);

--S1L1022 is std_1c20:inst|cpu:the_cpu|E_src2[21]~1561_BDD133 at LC_X41_Y14_N8

--operation mode is normal

S1L1022 = AMPP_FUNCTION(S1_E_ctrl_src2_is_imm, S1_E_src2_prelim[21], S1_E_src2_hazard_M, S1_E_src2_imm[21]);

--S1L1024 is std_1c20:inst|cpu:the_cpu|E_src2[21]~1562_BDD134 at LC_X41_Y14_N6

--operation mode is normal

S1L1024 = AMPP_FUNCTION(S1_E_ctrl_src2_is_imm, S1_E_src2_prelim[21], S1_E_src2_hazard_M, S1_E_src2_imm[21]);

--T1L438 is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|internal_cpu_data_master_dbs_address[0]~61_BDD135 at LC_X29_Y26_N5

--operation mode is normal

T1L438 = S1L1689Q & (Y1_cpu_data_master_read_data_valid_ext_flash_s1_shift_register[1] # T1L522 & S1_internal_d_write);

--T1L440 is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|internal_cpu_data_master_dbs_address[0]~62_BDD136 at LC_X29_Y26_N1

--operation mode is normal

T1L440 = !Y1_cpu_data_master_read_data_valid_ext_flash_s1_shift_register[1] & !T1L522 & S1_internal_d_write & S1L1689Q;

--S1L1027 is std_1c20:inst|cpu:the_cpu|E_src2[22]~1563_BDD137 at LC_X43_Y14_N8

--operation mode is normal

S1L1027 = AMPP_FUNCTION(S1_E_src2_imm[22], S1_E_src2_prelim[22], S1_E_ctrl_src2_is_imm, S1_E_src2_hazard_M);

--S1L1029 is std_1c20:inst|cpu:the_cpu|E_src2[22]~1564_BDD138 at LC_X43_Y14_N0

--operation mode is normal

S1L1029 = AMPP_FUNCTION(S1_E_src2_imm[22], S1_E_src2_prelim[22], S1_E_ctrl_src2_is_imm, S1_E_src2_hazard_M);

--S1L1032 is std_1c20:inst|cpu:the_cpu|E_src2[23]~1565_BDD139 at LC_X41_Y13_N0

--operation mode is normal

S1L1032 = AMPP_FUNCTION(S1_E_src2_imm[23], S1_E_ctrl_src2_is_imm, S1_E_src2_hazard_M, S1_E_src2_prelim[23]);

--S1L1034 is std_1c20:inst|cpu:the_cpu|E_src2[23]~1566_BDD140 at LC_X41_Y13_N8

--operation mode is normal

S1L1034 = AMPP_FUNCTION(S1_E_src2_imm[23], S1_E_ctrl_src2_is_imm, S1_E_src2_hazard_M, S1_E_src2_prelim[23]);

--S1L976 is std_1c20:inst|cpu:the_cpu|E_src2[14]~1567_BDD141 at LC_X39_Y17_N7

--operation mode is normal

S1L976 = AMPP_FUNCTION(S1_E_src2_prelim[14], S1_E_ctrl_src2_is_imm, S1_E_src2_hazard_M, S1L2433);

--S1L978 is std_1c20:inst|cpu:the_cpu|E_src2[14]~1568_BDD142 at LC_X39_Y17_N6

--operation mode is normal

S1L978 = AMPP_FUNCTION(S1_E_src2_prelim[14], S1_E_ctrl_src2_is_imm, S1_E_src2_hazard_M);

--Y1L580 is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_avalon_slave_arb_addend[0]~838_BDD145 at LC_X31_Y24_N0

--operation mode is normal

Y1L580 = !Y1L181 & (Y1L204 # Y1L372);

--Y1L159 is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|cpu_instruction_master_continuerequest~62_BDD147 at LC_X31_Y21_N5

--operation mode is normal

Y1L159 = Y1L955 & (Y1L726 # Y1L206Q # Y1L718);

--S1L1037 is std_1c20:inst|cpu:the_cpu|E_src2[24]~1571_BDD148 at LC_X43_Y17_N5

--operation mode is normal

S1L1037 = AMPP_FUNCTION(S1L203Q, S1_E_src2_prelim[24], S1_E_ctrl_src2_is_imm, S1_E_src2_hazard_M);

--S1L1039 is std_1c20:inst|cpu:the_cpu|E_src2[24]~1572_BDD149 at LC_X43_Y17_N9

--operation mode is normal

S1L1039 = AMPP_FUNCTION(S1_E_src2_prelim[24], S1_E_ctrl_src2_is_imm, S1_E_src2_hazard_M);

--DE1L74 is std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|data_to_cpu[5]~52_BDD150 at LC_X37_Y26_N9

--operation mode is normal

DE1L74 = X1L33 & !DE1L21 & X1L28;

--DE1L76 is std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|data_to_cpu[5]~53_BDD151 at LC_X37_Y26_N7

--operation mode is normal

DE1L76 = DE1L79 & (DE1L21 & DE1L115Q # !DE1L21 & (DE1_rx_holding_reg[5])) # !DE1L79 & (DE1_rx_holding_reg[5]);

--U1L176 is std_1c20:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_run~175_BDD153 at LC_X27_Y24_N2

--operation mode is normal

U1L176 = Y1L874 & (Y1L976 # !Y1L653Q);

--U1L178 is std_1c20:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_run~176_BDD154 at LC_X27_Y24_N4

--operation mode is normal

U1L178 = Y1L5 & Y1L653Q & Y1L874 & !Y1L976;

--K1L9 is std_1c20:inst|clock_0_in_arbitrator:the_clock_0_in|cpu_data_master_requests_clock_0_in~539_BDD155 at LC_X34_Y23_N3

--operation mode is normal

K1L9 = !S1L1756Q & K1L4 & !S1_M_alu_result[6] & !S1L1773Q;

--K1L11 is std_1c20:inst|clock_0_in_arbitrator:the_clock_0_in|cpu_data_master_requests_clock_0_in~540_BDD156 at LC_X34_Y23_N2

--operation mode is normal

K1L11 = UB1L8 & (UB1L4 & K1L7);

--KB1L794 is std_1c20:inst|sdram:the_sdram|Mux110~1396_BDD157 at LC_X15_Y19_N7

--operation mode is normal

KB1L794 = KB1L190Q & (KB1_m_state[3] $ !KB1_m_state[4]);

--KB1L796 is std_1c20:inst|sdram:the_sdram|Mux110~1397_BDD158 at LC_X15_Y19_N2

--operation mode is normal

KB1L796 = !KB1L190Q & (KB1_m_state[3] # KB1_init_done # KB1_m_state[4]);

--KB1L800 is std_1c20:inst|sdram:the_sdram|Mux110~1400_BDD161 at LC_X15_Y19_N6

--operation mode is normal

KB1L800 = KB1_m_state[0] & (KB1_m_state[1]) # !KB1_m_state[0] & KB1L796 & !KB1_m_state[1];

--KB1L822 is std_1c20:inst|sdram:the_sdram|Mux111~1323_BDD162 at LC_X14_Y20_N3

--operation mode is normal

KB1L822 = KB1L185Q & (KB1_m_state[3] $ !KB1_m_state[4]);

--KB1L824 is std_1c20:inst|sdram:the_sdram|Mux111~1324_BDD163 at LC_X14_Y20_N7

--operation mode is normal

KB1L824 = !KB1L185Q & (KB1_m_state[3] # KB1_init_done # KB1_m_state[4]);

--KB1L828 is std_1c20:inst|sdram:the_sdram|Mux111~1327_BDD166 at LC_X14_Y20_N8

--operation mode is normal

KB1L828 = KB1_m_state[1] & (KB1_m_state[0]) # !KB1_m_state[1] & KB1L824 & !KB1_m_state[0];

--T1L22 is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|A_WE_StdLogicVector~1448_BDD167 at LC_X34_Y25_N3

--operation mode is normal

T1L22 = !Y1_cpu_data_master_read_data_valid_ext_ram_s1_shift_register[0] & (!Y1L104 & Y1_cpu_data_master_requests_ext_ram_s1);

--T1L24 is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|A_WE_StdLogicVector~1449_BDD168 at LC_X47_Y28_N7

--operation mode is normal

T1L24 = NC1_slave_state[2] & (T1L10) # !NC1_slave_state[2] & NC1L10 & !NC1L7;

--T1L26 is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|A_WE_StdLogicVector~1450_BDD169 at LC_X43_Y27_N3

--operation mode is normal

T1L26 = EC1_slave_state[2] & (T1L12) # !EC1_slave_state[2] & !EC1L7 & (EC1L10);

--T1L28 is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|A_WE_StdLogicVector~1451_BDD170 at LC_X43_Y27_N4

--operation mode is normal

T1L28 = S1L1743Q & (T1L24) # !S1L1743Q & T1L26;

--S1L1565 is std_1c20:inst|cpu:the_cpu|ic_fill_req_accepted~19_BDD171 at LC_X26_Y22_N4

--operation mode is normal

S1L1565 = AMPP_FUNCTION(S1L1574Q, U1L259, U1L164);

--Y1L190 is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|cpu_instruction_master_read_data_valid_lan91c111_s1_shift_register_in~17_BDD172 at LC_X30_Y26_N7

--operation mode is normal

Y1L190 = Y1L653Q & (!Y1L976);

--Y1L192 is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|cpu_instruction_master_read_data_valid_lan91c111_s1_shift_register_in~18_BDD173 at LC_X30_Y26_N2

--operation mode is normal

Y1L192 = !Y1L653Q & !U1L223 & !Y1L1007 & !Y1L976;

--KB1L767 is std_1c20:inst|sdram:the_sdram|Mux109~1372_BDD174 at LC_X15_Y21_N7

--operation mode is normal

KB1L767 = KB1L195Q & (KB1_m_state[3] $ !KB1_m_state[4]);

--KB1L769 is std_1c20:inst|sdram:the_sdram|Mux109~1373_BDD175 at LC_X16_Y21_N5

--operation mode is normal

KB1L769 = !KB1L767 & (TE1L196 # !KB1L771);

--KB1L771 is std_1c20:inst|sdram:the_sdram|Mux109~1374_BDD176 at LC_X16_Y21_N4

--operation mode is normal

KB1L771 = KB1_m_state[4] $ KB1_m_state[3];

--KB1L851 is std_1c20:inst|sdram:the_sdram|Mux112~1355_BDD177 at LC_X13_Y19_N0

--operation mode is normal

KB1L851 = KB1L180Q & (KB1_m_state[3] $ (!KB1_m_state[4]));

--KB1L853 is std_1c20:inst|sdram:the_sdram|Mux112~1356_BDD178 at LC_X13_Y19_N2

--operation mode is normal

KB1L853 = !KB1L851 & (TE1L193 # !KB1L504);

--KB1L855 is std_1c20:inst|sdram:the_sdram|Mux112~1357_BDD179 at LC_X13_Y19_N1

--operation mode is normal

KB1L855 = KB1L504 & (KB1_m_state[3] $ KB1_m_state[4] # !KB1L180Q);

--KB1L876 is std_1c20:inst|sdram:the_sdram|Mux113~1355_BDD180 at LC_X12_Y18_N6

--operation mode is normal

KB1L876 = KB1L175Q & (KB1_m_state[3] $ !KB1_m_state[4]);

--KB1L878 is std_1c20:inst|sdram:the_sdram|Mux113~1356_BDD181 at LC_X12_Y18_N8

--operation mode is normal

KB1L878 = !KB1L876 & (TE1L192 # !KB1L504);

--KB1L880 is std_1c20:inst|sdram:the_sdram|Mux113~1357_BDD182 at LC_X12_Y18_N0

--operation mode is normal

KB1L880 = KB1L504 & (KB1_m_state[3] $ KB1_m_state[4] # !KB1L175Q);

--KB1L900 is std_1c20:inst|sdram:the_sdram|Mux114~1355_BDD183 at LC_X14_Y19_N9

--operation mode is normal

KB1L900 = KB1L170Q & (KB1_m_state[3] $ !KB1_m_state[4]);

--KB1L902 is std_1c20:inst|sdram:the_sdram|Mux114~1356_BDD184 at LC_X14_Y19_N0

--operation mode is normal

KB1L902 = !KB1L900 & (TE1L191 # !KB1L744);

--KB1L904 is std_1c20:inst|sdram:the_sdram|Mux114~1357_BDD185 at LC_X14_Y19_N8

--operation mode is normal

KB1L904 = KB1L744 & (KB1_m_state[4] $ KB1_m_state[3] # !KB1L170Q);

--KB1L926 is std_1c20:inst|sdram:the_sdram|Mux115~1355_BDD186 at LC_X13_Y18_N1

--operation mode is normal

KB1L926 = KB1L165Q & (KB1_m_state[4] $ !KB1_m_state[3]);

--KB1L928 is std_1c20:inst|sdram:the_sdram|Mux115~1356_BDD187 at LC_X13_Y18_N3

--operation mode is normal

KB1L928 = !KB1L926 & (TE1L190 # !KB1L504);

--KB1L930 is std_1c20:inst|sdram:the_sdram|Mux115~1357_BDD188 at LC_X13_Y18_N9

--operation mode is normal

KB1L930 = KB1L504 & (KB1_m_state[3] $ KB1_m_state[4] # !KB1L165Q);

--Y1L130 is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|cpu_data_master_read_data_valid_ext_ram_s1_shift_register[0]~25_BDD189 at LC_X33_Y25_N5

--operation mode is normal

Y1L130 = !Y1_cpu_data_master_read_data_valid_ext_ram_s1_shift_register[1] & !Y1_cpu_data_master_read_data_valid_ext_ram_s1_shift_register[0] & S1_internal_d_read;

--S1L678 is std_1c20:inst|cpu:the_cpu|E_alu_result[0]~2404_BDD190 at LC_X34_Y19_N6

--operation mode is normal

S1L678 = AMPP_FUNCTION(S1_E_ctrl_rdctl_inst, S1_E_ctrl_dst_data_sel_logic_result, S1_E_ctrl_dst_data_sel_pc_plus_one, S1_E_control_rd_data_without_mmu_regs[0]);

--S1L680 is std_1c20:inst|cpu:the_cpu|E_alu_result[0]~2405_BDD191 at LC_X34_Y12_N8

--operation mode is normal

S1L680 = AMPP_FUNCTION(S1_E_ctrl_rdctl_inst, S1_E_ctrl_dst_data_sel_logic_result, S1_E_ctrl_dst_data_sel_pc_plus_one);

--S1L682 is std_1c20:inst|cpu:the_cpu|E_alu_result[0]~2406_BDD192 at LC_X34_Y16_N0

--operation mode is normal

S1L682 = AMPP_FUNCTION(S1_E_logic_op[1], S1L851, S1_E_logic_op[0], S1L922);

--S1L1572Q is std_1c20:inst|cpu:the_cpu|ic_fill_tag[0]~110 at LC_X28_Y22_N0

--operation mode is normal

S1L1572Q = AMPP_FUNCTION(QC2__clk0, S1L1584, S1L1599, S1L1588, S1L1620, F1_data_out);

--S1L1573Q is std_1c20:inst|cpu:the_cpu|ic_fill_tag[0]~111 at LC_X28_Y22_N3

--operation mode is normal

S1L1573Q = AMPP_FUNCTION(QC2__clk0, S1L1578, S1L1581, S1L1569, F1_data_out);

--Y1L921 is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|last_cycle_cpu_data_master_granted_slave_ext_ram_s1~13_BDD196 at LC_X34_Y22_N5

--operation mode is normal

Y1L921 = !T1L448Q & !S1L1782Q & Y1L143 & !S1L1866Q;

--Y1L923 is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|last_cycle_cpu_data_master_granted_slave_ext_ram_s1~14_BDD197 at LC_X32_Y20_N1

--operation mode is normal

Y1L923 = Y1L919Q & (Y1L206Q # Y1L726 # Y1L718);

--Y1L925 is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|last_cycle_cpu_data_master_granted_slave_ext_ram_s1~15_BDD198 at LC_X34_Y22_N4

--operation mode is normal

Y1L925 = Y1L921 & (S1_internal_d_read # S1_internal_d_write);

--Y1L927 is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|last_cycle_cpu_data_master_granted_slave_ext_ram_s1~16_BDD199 at LC_X32_Y20_N8

--operation mode is normal

Y1L927 = Y1L925 & (Y1L3 # Y1L96);

--Y1L929 is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|last_cycle_cpu_data_master_granted_slave_ext_ram_s1~17_BDD200 at LC_X32_Y20_N2

--operation mode is normal

Y1L929 = Y1L925 & !Y1L923;

--KB1L131 is std_1c20:inst|sdram:the_sdram|f_select~12_BDD201 at LC_X17_Y22_N8

--operation mode is normal

KB1L131 = !TE1L78 & KB1_f_pop & KB1L133 & !KB1L125;

--FD1L17 is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_avalon_reg:the_cpu_nios2_avalon_reg|internal_oci_ienable1[0]~670_BDD202 at LC_X45_Y19_N6

--operation mode is normal

FD1L17 = AMPP_FUNCTION(RD1L70, FD1L2, V1L16);

--T1L519 is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|p1_registered_cpu_data_master_readdata~2092_BDD203 at LC_X44_Y21_N8

--operation mode is normal

T1L519 = CB1L2 & (UB1L9);

--T1L521 is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|p1_registered_cpu_data_master_readdata~2093_BDD204 at LC_X46_Y24_N0

--operation mode is normal

T1L521 = UB1L9 & CB1L2;

--T1L60 is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[2]~5339_BDD205 at LC_X43_Y25_N8

--operation mode is normal

T1L60 = S1L1689Q & (T1L355Q & (!T1L371Q) # !T1L355Q & !T1L335Q);

--S1L1042 is std_1c20:inst|cpu:the_cpu|E_src2[25]~1573_BDD206 at LC_X39_Y13_N8

--operation mode is normal

S1L1042 = AMPP_FUNCTION(S1_E_src2_imm[25], S1_E_src2_prelim[25], S1_E_ctrl_src2_is_imm, S1_E_src2_hazard_M);

--S1L1044 is std_1c20:inst|cpu:the_cpu|E_src2[25]~1574_BDD207 at LC_X39_Y13_N2

--operation mode is normal

S1L1044 = AMPP_FUNCTION(S1_E_src2_imm[25], S1_E_src2_prelim[25], S1_E_ctrl_src2_is_imm, S1_E_src2_hazard_M);

--S1L1746 is std_1c20:inst|cpu:the_cpu|M_alu_result[6]~413_BDD208 at LC_X35_Y17_N1

--operation mode is normal

S1L1746 = AMPP_FUNCTION(S1_E_ctrl_dst_data_sel_cmp, S1_E_ctrl_dst_data_sel_logic_result, S1_E_ctrl_rdctl_inst, S1_E_control_rd_data_without_mmu_regs[6]);

--S1L1748 is std_1c20:inst|cpu:the_cpu|M_alu_result[6]~414_BDD209 at LC_X35_Y17_N8

--operation mode is normal

S1L1748 = AMPP_FUNCTION(S1_E_ctrl_dst_data_sel_cmp, S1_E_ctrl_dst_data_sel_logic_result, S1_E_ctrl_rdctl_inst, S1_E_control_rd_data_without_mmu_regs[6]);

--S1L1047 is std_1c20:inst|cpu:the_cpu|E_src2[26]~1575_BDD212 at LC_X44_Y13_N7

--operation mode is normal

S1L1047 = AMPP_FUNCTION(S1_E_src2_imm[26], S1_E_ctrl_src2_is_imm, S1_E_src2_prelim[26], S1_E_src2_hazard_M);

--S1L1049 is std_1c20:inst|cpu:the_cpu|E_src2[26]~1576_BDD213 at LC_X44_Y13_N0

--operation mode is normal

S1L1049 = AMPP_FUNCTION(S1_E_src2_imm[26], S1_E_ctrl_src2_is_imm, S1_E_src2_prelim[26], S1_E_src2_hazard_M);

--S1L464 is std_1c20:inst|cpu:the_cpu|d_readdata_d1[2]~180_BDD215 at LC_X44_Y25_N3

--operation mode is normal

S1L464 = AMPP_FUNCTION(Y1_cpu_data_master_requests_ext_ram_s1, Y1L146, Y1_internal_incoming_ext_ram_bus_data[2], UB1_cpu_data_master_granted_sysid_control_slave);

--S1L466 is std_1c20:inst|cpu:the_cpu|d_readdata_d1[2]~181_BDD216 at LC_X44_Y25_N0

--operation mode is normal

S1L466 = AMPP_FUNCTION(RB1_readdata[2], JB1_cpu_data_master_requests_reconfig_request_pio_s1, SB1_cpu_data_master_requests_sys_clk_timer_s1, S1L464);

--S1L468 is std_1c20:inst|cpu:the_cpu|d_readdata_d1[2]~182_BDD217 at LC_X46_Y25_N5

--operation mode is normal

S1L468 = AMPP_FUNCTION(XE1_readdata[2], WB1_cpu_data_master_granted_uart1_s1, T1L54, T1L56);

--S1L470 is std_1c20:inst|cpu:the_cpu|d_readdata_d1[2]~183_BDD218 at LC_X43_Y25_N1

--operation mode is normal

S1L470 = AMPP_FUNCTION(H1_cpu_data_master_requests_button_pio_s1, S1L466, G1_readdata[2]);

--S1L474 is std_1c20:inst|cpu:the_cpu|d_readdata_d1[3]~184_BDD219 at LC_X44_Y25_N6

--operation mode is normal

S1L474 = AMPP_FUNCTION(Y1_cpu_data_master_requests_ext_ram_s1, Y1L146, Y1_internal_incoming_ext_ram_bus_data[3], UB1_cpu_data_master_granted_sysid_control_slave);

--S1L476 is std_1c20:inst|cpu:the_cpu|d_readdata_d1[3]~185_BDD220 at LC_X44_Y25_N7

--operation mode is normal

S1L476 = AMPP_FUNCTION(G1_readdata[3], JB1_cpu_data_master_requests_reconfig_request_pio_s1, H1_cpu_data_master_requests_button_pio_s1, S1L474);

--S1L483Q is std_1c20:inst|cpu:the_cpu|d_readdata_d1[3]~222 at LC_X44_Y25_N8

--operation mode is normal

S1L483Q = AMPP_FUNCTION(QC2__clk0, T1L71, T1L73, S1L476, F1_data_out);

--S1L484Q is std_1c20:inst|cpu:the_cpu|d_readdata_d1[3]~223 at LC_X44_Y24_N5

--operation mode is normal

S1L484Q = AMPP_FUNCTION(QC2__clk0, S1_M_alu_result[6], RB1_readdata[3], XE1_readdata[3], SB1L3, F1_data_out);

--S1L508 is std_1c20:inst|cpu:the_cpu|d_readdata_d1[6]~188_BDD223 at LC_X45_Y26_N9

--operation mode is normal

S1L508 = AMPP_FUNCTION(T1L107, Y1_cpu_data_master_requests_ext_ram_s1, Y1_internal_incoming_ext_ram_bus_data[6], Y1L146);

--S1L510 is std_1c20:inst|cpu:the_cpu|d_readdata_d1[6]~189_BDD224 at LC_X46_Y26_N9

--operation mode is normal

S1L510 = AMPP_FUNCTION(SB1_cpu_data_master_requests_sys_clk_timer_s1, RB1_readdata[6], T1L81, T1L109);

--S1L512 is std_1c20:inst|cpu:the_cpu|d_readdata_d1[6]~190_BDD225 at LC_X47_Y25_N4

--operation mode is normal

S1L512 = AMPP_FUNCTION(XE1_readdata[6], Z1_readdata[6], WB1_cpu_data_master_granted_uart1_s1, AB1_cpu_data_master_requests_high_res_timer_s1);

--S1L514 is std_1c20:inst|cpu:the_cpu|d_readdata_d1[6]~191_BDD226 at LC_X46_Y26_N2

--operation mode is normal

S1L514 = AMPP_FUNCTION(S1L512, S1L508);

--S1L498 is std_1c20:inst|cpu:the_cpu|d_readdata_d1[5]~192_BDD227 at LC_X45_Y25_N0

--operation mode is normal

S1L498 = AMPP_FUNCTION(Y1_cpu_data_master_requests_ext_ram_s1, Y1L146, Y1_internal_incoming_ext_ram_bus_data[5], T1L93);

--S1L500 is std_1c20:inst|cpu:the_cpu|d_readdata_d1[5]~193_BDD228 at LC_X46_Y25_N4

--operation mode is normal

S1L500 = AMPP_FUNCTION(RB1_readdata[5], SB1_cpu_data_master_requests_sys_clk_timer_s1, S1L498, T1L96);

--S1L502 is std_1c20:inst|cpu:the_cpu|d_readdata_d1[5]~194_BDD229 at LC_X46_Y23_N7

--operation mode is normal

S1L502 = AMPP_FUNCTION(Z1_readdata[5], XE1_readdata[5], WB1_cpu_data_master_granted_uart1_s1, AB1_cpu_data_master_requests_high_res_timer_s1);

--S1L504 is std_1c20:inst|cpu:the_cpu|d_readdata_d1[5]~195_BDD230 at LC_X46_Y23_N8

--operation mode is normal

S1L504 = AMPP_FUNCTION(T1L99, S1L502);

--T1L125 is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[7]~5340_BDD231 at LC_X42_Y26_N7

--operation mode is normal

T1L125 = T1L118 & (Y1_internal_incoming_ext_ram_bus_data[7] # !Y1_cpu_data_master_requests_ext_ram_s1 & !Y1L146);

--T1L127 is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[7]~5341_BDD232 at LC_X43_Y26_N1

--operation mode is normal

T1L127 = T1L81 & !T1L120 & (RB1_readdata[7] # !SB1_cpu_data_master_requests_sys_clk_timer_s1);

--T1L129 is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[7]~5342_BDD233 at LC_X47_Y25_N1

--operation mode is normal

T1L129 = XE1_readdata[7] & (Z1_readdata[7] # !AB1_cpu_data_master_requests_high_res_timer_s1) # !XE1_readdata[7] & !WB1_cpu_data_master_granted_uart1_s1 & (Z1_readdata[7] # !AB1_cpu_data_master_requests_high_res_timer_s1);

--T1L131 is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[7]~5343_BDD234 at LC_X43_Y26_N5

--operation mode is normal

T1L131 = T1L129 & T1L125;

--S1L1229 is std_1c20:inst|cpu:the_cpu|F_ic_hit~128_BDD235 at LC_X25_Y19_N6

--operation mode is normal

S1L1229 = AMPP_FUNCTION(S1_F_pc[15], BD1_q_b[9], BD1_q_b[13], S1_F_pc[11]);

--S1L1231 is std_1c20:inst|cpu:the_cpu|F_ic_hit~129_BDD236 at LC_X25_Y19_N8

--operation mode is normal

S1L1231 = AMPP_FUNCTION(BD1_q_b[21], S1_F_pc[23]);

--S1L1052 is std_1c20:inst|cpu:the_cpu|E_src2[27]~1577_BDD237 at LC_X43_Y13_N3

--operation mode is normal

S1L1052 = AMPP_FUNCTION(S1_E_src2_prelim[27], S1_E_src2_hazard_M, S1_E_src2_imm[27], S1_E_ctrl_src2_is_imm);

--S1L1054 is std_1c20:inst|cpu:the_cpu|E_src2[27]~1578_BDD238 at LC_X43_Y13_N5

--operation mode is normal

S1L1054 = AMPP_FUNCTION(S1_E_src2_prelim[27], S1_E_src2_hazard_M, S1_E_src2_imm[27], S1_E_ctrl_src2_is_imm);

--S1L2212 is std_1c20:inst|cpu:the_cpu|M_pipe_flush~40_BDD239 at LC_X30_Y18_N3

--operation mode is normal

S1L2212 = AMPP_FUNCTION(S1L1159, S1_E_ctrl_flush_pipe_always, S1_E_hbreak_req, S1_E_ctrl_br_cond);

--S1L2214 is std_1c20:inst|cpu:the_cpu|M_pipe_flush~41_BDD240 at LC_X30_Y18_N7

--operation mode is normal

S1L2214 = AMPP_FUNCTION(S1L1159, S1_E_ctrl_flush_pipe_always, S1_E_hbreak_req);

--JD1L8 is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_debug:the_cpu_nios2_oci_debug|internal_monitor_ready~123_BDD241 at LC_X45_Y19_N3

--operation mode is normal

JD1L8 = AMPP_FUNCTION(SD1L190, S1_M_st_data[0], RD1L70, V1L16);

--JD1L10 is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_debug:the_cpu_nios2_oci_debug|internal_monitor_ready~124_BDD242 at LC_X46_Y18_N1

--operation mode is normal

JD1L10 = AMPP_FUNCTION(SD1_internal_jdo1[25], JD1_internal_monitor_ready, SD1L189, SD1_internal_jdo1[34]);

--S1L1057 is std_1c20:inst|cpu:the_cpu|E_src2[28]~1579_BDD243 at LC_X42_Y13_N9

--operation mode is normal

S1L1057 = AMPP_FUNCTION(S1_E_src2_prelim[28], S1_E_ctrl_src2_is_imm, S1_E_src2_hazard_M, S1_E_src2_imm[28]);

--S1L1059 is std_1c20:inst|cpu:the_cpu|E_src2[28]~1580_BDD244 at LC_X42_Y13_N4

--operation mode is normal

S1L1059 = AMPP_FUNCTION(S1_E_src2_prelim[28], S1_E_ctrl_src2_is_imm, S1_E_src2_hazard_M, S1_E_src2_imm[28]);

--U1L180 is std_1c20:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_run~177_BDD245 at LC_X27_Y23_N0

--operation mode is normal

U1L180 = X1L10 & (X1_epcs_controller_epcs_control_port_arb_addend[0] & !X1_epcs_controller_epcs_control_port_arb_addend[1] # !X1_d1_reasons_to_wait);

--U1L182 is std_1c20:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_run~178_BDD246 at LC_X27_Y23_N5

--operation mode is normal

U1L182 = X1_epcs_controller_epcs_control_port_arb_addend[0] & X1_epcs_controller_epcs_control_port_arb_addend[1] & X1_d1_reasons_to_wait & X1L10;

--U1L186 is std_1c20:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_run~181_BDD249 at LC_X24_Y22_N1

--operation mode is normal

U1L186 = !U1L192 & !U1L190 & (!U1L188 # !NB1L25);

--V1L19 is std_1c20:inst|cpu_jtag_debug_module_arbitrator:the_cpu_jtag_debug_module|cpu_jtag_debug_module_address[1]~99_BDD250 at LC_X38_Y21_N2

--operation mode is normal

V1L19 = !V1L39 & (V1L34Q # S1L1451);

--Y1L461 is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_address[17]~46_BDD251 at LC_X29_Y23_N4

--operation mode is normal

Y1L461 = !Y1L905 & !Y1L770 & (S1L1593Q $ S1_M_alu_result[17]);

--Y1L463 is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_address[17]~47_BDD252 at LC_X29_Y24_N2

--operation mode is normal

Y1L463 = Y1L467 $ (!Y1L34 & Y1L469 & !Y1L37);

--Y1L465 is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_address[17]~48_BDD253 at LC_X29_Y24_N3

--operation mode is normal

Y1L465 = Y1L742 # Y1L112 & (Y1L28 # Y1L31);

--S1L1062 is std_1c20:inst|cpu:the_cpu|E_src2[29]~1581_BDD254 at LC_X44_Y14_N9

--operation mode is normal

S1L1062 = AMPP_FUNCTION(S1_E_src2_hazard_M, S1_E_src2_prelim[29], S1_E_ctrl_src2_is_imm, S1_E_src2_imm[29]);

--S1L1064 is std_1c20:inst|cpu:the_cpu|E_src2[29]~1582_BDD255 at LC_X44_Y14_N3

--operation mode is normal

S1L1064 = AMPP_FUNCTION(S1_E_src2_hazard_M, S1_E_src2_prelim[29], S1_E_ctrl_src2_is_imm, S1_E_src2_imm[29]);

--KB1L632 is std_1c20:inst|sdram:the_sdram|Mux40~1483_BDD256 at LC_X12_Y23_N8

--operation mode is normal

KB1L632 = !KB1_m_count[0] & KB1L619 & !KB1_m_count[1];

--KB1L634 is std_1c20:inst|sdram:the_sdram|Mux40~1484_BDD257 at LC_X13_Y22_N8

--operation mode is normal

KB1L634 = KB1_refresh_request & KB1L539 & !KB1L991 & TE1L152;

--KB1L637 is std_1c20:inst|sdram:the_sdram|Mux40~1486_BDD259 at LC_X12_Y23_N0

--operation mode is normal

KB1L637 = KB1_m_state[2] & (KB1L623 # KB1_m_state[3]) # !KB1_m_state[2] & (!KB1_m_state[3] & KB1L624);

--KB1L639 is std_1c20:inst|sdram:the_sdram|Mux40~1487_BDD260 at LC_X12_Y23_N9

--operation mode is normal

KB1L639 = KB1_m_state[4] & KB1_m_state[5] # !KB1_m_state[4] & KB1_m_count[2] & (!KB1L632 # !KB1_m_state[5]);

--KB1L641 is std_1c20:inst|sdram:the_sdram|Mux40~1488_BDD261 at LC_X12_Y22_N6

--operation mode is normal

KB1L641 = KB1_m_state[4] # KB1_m_state[5];

--KB1L643 is std_1c20:inst|sdram:the_sdram|Mux40~1489_BDD262 at LC_X12_Y23_N3

--operation mode is normal

KB1L643 = KB1_m_state[3] & !KB1L637 & KB1L639 & !KB1L641;

--KB1L645 is std_1c20:inst|sdram:the_sdram|Mux40~1490_BDD263 at LC_X12_Y23_N5

--operation mode is normal

KB1L645 = KB1L641 & (KB1L639) # !KB1L641 & KB1L637 & (KB1L639 # !KB1_m_state[3]);

--S1L488 is std_1c20:inst|cpu:the_cpu|d_readdata_d1[4]~196_BDD264 at LC_X43_Y23_N1

--operation mode is normal

S1L488 = AMPP_FUNCTION(Z1_readdata[4], AB1_cpu_data_master_requests_high_res_timer_s1, T1L85, T1L84);

--S1L490 is std_1c20:inst|cpu:the_cpu|d_readdata_d1[4]~197_BDD265 at LC_X43_Y23_N3

--operation mode is normal

S1L490 = AMPP_FUNCTION(S1L1689Q, T1L81, T1L342, T1L87);

--S1L492 is std_1c20:inst|cpu:the_cpu|d_readdata_d1[4]~198_BDD266 at LC_X44_Y24_N1

--operation mode is normal

S1L492 = AMPP_FUNCTION(S1_M_alu_result[6], RB1_readdata[4], XE1_readdata[4], SB1L3);

--S1L494 is std_1c20:inst|cpu:the_cpu|d_readdata_d1[4]~199_BDD267 at LC_X43_Y23_N5

--operation mode is normal

S1L494 = AMPP_FUNCTION(S1L492, S1L488);

--S1L1734 is std_1c20:inst|cpu:the_cpu|M_alu_result[4]~417_BDD269 at LC_X36_Y20_N7

--operation mode is normal

S1L1734 = AMPP_FUNCTION(S1_E_ctrl_dst_data_sel_cmp, S1_E_ctrl_rdctl_inst, S1_E_ctrl_dst_data_sel_logic_result, S1_E_control_rd_data_without_mmu_regs[4]);

--S1L1736 is std_1c20:inst|cpu:the_cpu|M_alu_result[4]~418_BDD270 at LC_X36_Y20_N3

--operation mode is normal

S1L1736 = AMPP_FUNCTION(S1_E_ctrl_dst_data_sel_cmp, S1_E_ctrl_rdctl_inst, S1_E_ctrl_dst_data_sel_logic_result, S1_E_control_rd_data_without_mmu_regs[4]);

--SB1L5 is std_1c20:inst|sys_clk_timer_s1_arbitrator:the_sys_clk_timer_s1|cpu_data_master_requests_sys_clk_timer_s1~182_BDD271 at LC_X42_Y25_N0

--operation mode is normal

SB1L5 = !S1L1743Q & UB1L6;

--S1L1729 is std_1c20:inst|cpu:the_cpu|M_alu_result[3]~419_BDD272 at LC_X36_Y19_N0

--operation mode is normal

S1L1729 = AMPP_FUNCTION(S1_E_ctrl_dst_data_sel_logic_result, S1_E_ctrl_rdctl_inst, S1_E_ctrl_dst_data_sel_cmp, S1_E_control_rd_data_without_mmu_regs[3]);

--S1L1731 is std_1c20:inst|cpu:the_cpu|M_alu_result[3]~420_BDD273 at LC_X36_Y20_N8

--operation mode is normal

S1L1731 = AMPP_FUNCTION(S1_E_ctrl_dst_data_sel_cmp, S1_E_ctrl_rdctl_inst, S1_E_ctrl_dst_data_sel_logic_result, S1_E_control_rd_data_without_mmu_regs[3]);

--Y1L492 is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_address[22]~49_BDD274 at LC_X26_Y23_N5

--operation mode is normal

Y1L492 = Y1L496 & (!Y1L34 & !Y1L37 # !Y1L100);

--Y1L494 is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_address[22]~50_BDD275 at LC_X25_Y23_N8

--operation mode is normal

Y1L494 = Y1L905 & S1L1816Q # !Y1L905 & (S1_ic_fill_tag[10] & Y1L14);

--Y1L483 is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_address[21]~51_BDD276 at LC_X27_Y23_N3

--operation mode is normal

Y1L483 = Y1L487 & (!Y1L37 & !Y1L34 # !Y1L100);

--Y1L485 is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_address[21]~52_BDD277 at LC_X28_Y23_N3

--operation mode is normal

Y1L485 = Y1L905 & (S1L1800Q) # !Y1L905 & S1_ic_fill_tag[9] & (Y1L770);

--S1L1067 is std_1c20:inst|cpu:the_cpu|E_src2[30]~1583_BDD278 at LC_X40_Y13_N2

--operation mode is normal

S1L1067 = AMPP_FUNCTION(S1_E_src2_prelim[30], S1_E_ctrl_src2_is_imm, S1_E_src2_hazard_M, S1_E_src2_imm[30]);

--S1L1069 is std_1c20:inst|cpu:the_cpu|E_src2[30]~1584_BDD279 at LC_X40_Y13_N7

--operation mode is normal

S1L1069 = AMPP_FUNCTION(S1_E_src2_prelim[30], S1_E_ctrl_src2_is_imm, S1_E_src2_hazard_M, S1_E_src2_imm[30]);

--S1L1722 is std_1c20:inst|cpu:the_cpu|M_alu_result[2]~421_BDD280 at LC_X33_Y19_N7

--operation mode is normal

S1L1722 = AMPP_FUNCTION(S1_E_ctrl_dst_data_sel_logic_result, S1_E_control_rd_data_without_mmu_regs[2], S1_E_ctrl_dst_data_sel_cmp, S1_E_ctrl_rdctl_inst);

--S1L1724 is std_1c20:inst|cpu:the_cpu|M_alu_result[2]~422_BDD281 at LC_X33_Y19_N4

--operation mode is normal

S1L1724 = AMPP_FUNCTION(S1_E_ctrl_dst_data_sel_logic_result, S1_E_control_rd_data_without_mmu_regs[2], S1_E_ctrl_dst_data_sel_cmp, S1_E_ctrl_rdctl_inst);

--BB1L73 is std_1c20:inst|jtag_uart:the_jtag_uart|process2~49_BDD282 at LC_X36_Y25_N8

--operation mode is normal

BB1L73 = S1_M_alu_result[5] & BB1L69 & (UB1L6);

--Y1L286 is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_outgoing_ext_ram_bus_data[7]~64_BDD283 at LC_X26_Y26_N3

--operation mode is normal

Y1L286 = Y1L100 & T1L433 & (Y1L34 # Y1L37);

--Y1L288 is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_outgoing_ext_ram_bus_data[7]~65_BDD284 at LC_X33_Y26_N7

--operation mode is normal

Y1L288 = T1_internal_cpu_data_master_dbs_address[1] & !S1_M_st_data[31] & (T1_internal_cpu_data_master_dbs_address[0]) # !T1_internal_cpu_data_master_dbs_address[1] & (T1_internal_cpu_data_master_dbs_address[0] & (!S1L2319Q) # !T1_internal_cpu_data_master_dbs_address[0] & !S1_M_st_data[31]);

--Y1L290 is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_outgoing_ext_ram_bus_data[7]~66_BDD285 at LC_X33_Y26_N5

--operation mode is normal

Y1L290 = T1_internal_cpu_data_master_dbs_address[1] & S1_M_st_data[31] & (T1_internal_cpu_data_master_dbs_address[0]) # !T1_internal_cpu_data_master_dbs_address[1] & (T1_internal_cpu_data_master_dbs_address[0] & (S1L2319Q) # !T1_internal_cpu_data_master_dbs_address[0] & S1_M_st_data[31]);

--Y1L292 is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_outgoing_ext_ram_bus_data[7]~67_BDD286 at LC_X33_Y26_N6

--operation mode is normal

Y1L292 = Y1L290 # S1L2360Q & !Y1L288;

--T1L133 is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[7]~5344_BDD287 at LC_X42_Y26_N9

--operation mode is normal

T1L133 = !T1_registered_cpu_data_master_readdata[7] & (S1L1693Q # N1_cpu_data_master_requests_clock_1_in);

--T1L135 is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[7]~5345_BDD288 at LC_X43_Y26_N4

--operation mode is normal

T1L135 = S1L1689Q & (T1L355Q & !T1L397Q # !T1L355Q & (!T1L356Q));

--T1L113 is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[6]~5346_BDD289 at LC_X46_Y25_N6

--operation mode is normal

T1L113 = !T1_registered_cpu_data_master_readdata[6] & (S1L1693Q # N1_cpu_data_master_requests_clock_1_in);

--T1L115 is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[6]~5347_BDD290 at LC_X43_Y26_N7

--operation mode is normal

T1L115 = S1L1689Q & (T1L355Q & !T1L391Q # !T1L355Q & (!T1L351Q));

--T1L101 is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[5]~5348_BDD291 at LC_X46_Y25_N2

--operation mode is normal

T1L101 = !T1_registered_cpu_data_master_readdata[5] & (S1L1693Q # N1_cpu_data_master_requests_clock_1_in);

--T1L103 is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[5]~5349_BDD292 at LC_X43_Y25_N3

--operation mode is normal

T1L103 = S1L1689Q & (T1L355Q & !T1L386Q # !T1L355Q & (!T1L347Q));

--WC1L6 is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|readdata[3]~1373_BDD293 at LC_X45_Y19_N8

--operation mode is normal

WC1L6 = AMPP_FUNCTION(FD1_internal_oci_single_step_mode1, FD1L2, V1L16);

--Y1L596Q is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_avalon_slave_arb_addend[0]~956 at LC_X30_Y25_N7

--operation mode is normal

Y1L596Q_lut_out = Y1L562 & Y1L18 & (!Y1L540) # !Y1L562 & (Y1L22);

Y1L596Q = DFFEAS(Y1L596Q_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--T1L77 is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[3]~5350_BDD297 at LC_X44_Y26_N3

--operation mode is normal

T1L77 = !T1_registered_cpu_data_master_readdata[3] & (S1L1693Q # K1_cpu_data_master_requests_clock_0_in);

--T1L79 is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[3]~5351_BDD298 at LC_X39_Y26_N5

--operation mode is normal

T1L79 = S1L1689Q & (T1L355Q & (!T1L376Q) # !T1L355Q & !T1L339Q);

--BB1L80 is std_1c20:inst|jtag_uart:the_jtag_uart|rvalid~28_BDD299 at LC_X44_Y21_N3

--operation mode is normal

BB1L80 = NE2_b_non_empty & CB1L2;

--Y1L14 is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|A_WE_StdLogicVector~4296_BDD300 at LC_X26_Y23_N9

--operation mode is normal

Y1L14 = U1L223 & (Y1L40 # Y1L43);

--Y1L16 is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|A_WE_StdLogicVector~4297_BDD301 at LC_X26_Y23_N2

--operation mode is normal

Y1L16 = Y1L100 & (S1_internal_d_read # S1_internal_d_write);

--WE1L35 is std_1c20:inst|sdram_s1_arbitrator:the_sdram_s1|rdv_fifo_for_cpu_instruction_master_to_sdram_s1_module:rdv_fifo_for_cpu_instruction_master_to_sdram_s1|process15~1_BDD302 at LC_X24_Y24_N5

--operation mode is normal

WE1L35 = S1_internal_d_read & NB1L20;

--T1L460 is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|internal_cpu_data_master_waitrequest~26_BDD303 at LC_X35_Y25_N2

--operation mode is normal

T1L460 = !V1L3 & !BB1L70 & !T1L18 & !T1L532;

--S1L455 is std_1c20:inst|cpu:the_cpu|d_readdata_d1[1]~200_BDD306 at LC_X44_Y24_N4

--operation mode is normal

S1L455 = AMPP_FUNCTION(T1L45, T1L42, T1L43, T1L41);

--S1L457 is std_1c20:inst|cpu:the_cpu|d_readdata_d1[1]~201_BDD307 at LC_X43_Y24_N9

--operation mode is normal

S1L457 = AMPP_FUNCTION(DE1_data_to_cpu[1], X1_cpu_data_master_requests_epcs_controller_epcs_control_port, FE1_q_a[1], W1L1);

--S1L459 is std_1c20:inst|cpu:the_cpu|d_readdata_d1[1]~202_BDD308 at LC_X43_Y24_N5

--operation mode is normal

S1L459 = AMPP_FUNCTION(S1L1689Q, T1L330, G1_readdata[1], H1_cpu_data_master_requests_button_pio_s1);

--S1L461 is std_1c20:inst|cpu:the_cpu|d_readdata_d1[1]~203_BDD309 at LC_X46_Y24_N7

--operation mode is normal

S1L461 = AMPP_FUNCTION(Z1_readdata[1], AB1_cpu_data_master_requests_high_res_timer_s1);

--KB1L437 is std_1c20:inst|sdram:the_sdram|m_next[3]~852_BDD312 at LC_X16_Y24_N2

--operation mode is normal

KB1L437 = KB1_m_state[0] $ (KB1_m_state[1]);

--KB1L439 is std_1c20:inst|sdram:the_sdram|m_next[3]~853_BDD313 at LC_X16_Y24_N6

--operation mode is normal

KB1L439 = KB1_m_state[0] & (KB1L586 # !KB1_m_state[1]) # !KB1_m_state[0] & (!KB1_m_state[1] & KB1L587);

--KB1L442 is std_1c20:inst|sdram:the_sdram|m_next[3]~855_BDD315 at LC_X16_Y24_N7

--operation mode is normal

KB1L442 = !KB1L447 & (KB1L439 & KB1L437 & KB1L455 # !KB1L439 & !KB1L437);

--KB1L444 is std_1c20:inst|sdram:the_sdram|m_next[3]~856_BDD316 at LC_X16_Y24_N1

--operation mode is normal

KB1L444 = !KB1L447 & !KB1L437 & KB1L439;

--KB1L447 is std_1c20:inst|sdram:the_sdram|m_next[4]~857_BDD317 at LC_X16_Y23_N6

--operation mode is normal

KB1L447 = KB1_m_state[7] & (KB1_m_state[8] # !KB1L729) # !KB1_m_state[7] & KB1_m_state[8] & (!KB1L462 # !KB1L729);

--KB1L449 is std_1c20:inst|sdram:the_sdram|m_next[4]~858_BDD318 at LC_X16_Y23_N2

--operation mode is normal

KB1L449 = KB1L729 & (KB1_m_state[7] & !KB1_m_state[8] # !KB1_m_state[7] & KB1_m_state[8] & KB1L462);

--KB1L451 is std_1c20:inst|sdram:the_sdram|m_next[4]~859_BDD319 at LC_X16_Y23_N5

--operation mode is normal

KB1L451 = KB1_m_state[0] $ KB1_m_state[1];

--KB1L453 is std_1c20:inst|sdram:the_sdram|m_next[4]~860_BDD320 at LC_X16_Y24_N9

--operation mode is normal

KB1L453 = KB1_m_state[0] & (KB1L579 # !KB1_m_state[1]) # !KB1_m_state[0] & (!KB1_m_state[1] & KB1L580);

--KB1L455 is std_1c20:inst|sdram:the_sdram|m_next[4]~861_BDD321 at LC_X16_Y23_N4

--operation mode is normal

KB1L455 = KB1L461 & (KB1_m_state[4] $ KB1_m_state[3]);

--KB1L457 is std_1c20:inst|sdram:the_sdram|m_next[4]~862_BDD322 at LC_X16_Y23_N7

--operation mode is normal

KB1L457 = !KB1L447 & (KB1L453 & KB1L451 & KB1L455 # !KB1L453 & !KB1L451);

--KB1L459 is std_1c20:inst|sdram:the_sdram|m_next[4]~863_BDD323 at LC_X16_Y23_N9

--operation mode is normal

KB1L459 = !KB1L451 & KB1L453 & !KB1L447;

--S1L693 is std_1c20:inst|cpu:the_cpu|E_arith_src1~65_BDD329 at LC_X37_Y13_N4

--operation mode is normal

S1L693 = AMPP_FUNCTION(S1L886Q, S1L229Q, S1_E_src1_prelim[31]);

--S1L695 is std_1c20:inst|cpu:the_cpu|E_arith_src1~66_BDD330 at LC_X37_Y13_N8

--operation mode is normal

S1L695 = AMPP_FUNCTION(S1L886Q, S1L229Q);

--S1L1422 is std_1c20:inst|cpu:the_cpu|i_readdata_d1[6]~168_BDD331 at LC_X38_Y21_N8

--operation mode is normal

S1L1422 = AMPP_FUNCTION(V1L26, FD1L2, FD1L34Q, V1L16);

--S1L1424 is std_1c20:inst|cpu:the_cpu|i_readdata_d1[6]~169_BDD332 at LC_X38_Y19_N4

--operation mode is normal

S1L1424 = AMPP_FUNCTION(V1L6, S1_ic_fill_line[5], CE1_q_a[6], S1L1756Q);

--S1L1072 is std_1c20:inst|cpu:the_cpu|E_src2[31]~1585_BDD333 at LC_X37_Y13_N6

--operation mode is normal

S1L1072 = AMPP_FUNCTION(S1_E_src2_hazard_M, S1_E_src2_imm[31], S1_E_ctrl_src2_is_imm, S1_E_src2_prelim[31]);

--S1L1074 is std_1c20:inst|cpu:the_cpu|E_src2[31]~1586_BDD334 at LC_X37_Y13_N2

--operation mode is normal

S1L1074 = AMPP_FUNCTION(S1_E_src2_hazard_M, S1_E_src2_imm[31], S1_E_ctrl_src2_is_imm, S1_E_src2_prelim[31]);

--U1L83 is std_1c20:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_readdata[15]~2535_BDD335 at LC_X44_Y27_N0

--operation mode is normal

U1L83 = NB1_cpu_instruction_master_read_data_valid_sdram_s1 & !KB1_za_data[15];

--U1L85 is std_1c20:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_readdata[15]~2536_BDD336 at LC_X40_Y26_N5

--operation mode is normal

U1L85 = U1L83 # !DE1_data_to_cpu[15] & X1L10 & W1L1;

--U1L87 is std_1c20:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_readdata[15]~2537_BDD337 at LC_X40_Y26_N7

--operation mode is normal

U1L87 = !W1L1 & (X1L10 & !U1L83);

--U1L89 is std_1c20:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_readdata[15]~2538_BDD338 at LC_X37_Y25_N2

--operation mode is normal

U1L89 = !Y1_internal_incoming_ext_ram_bus_data[15] & (Y1_cpu_instruction_master_read_data_valid_ext_ram_s1_shift_register[1] # Y1_cpu_instruction_master_read_data_valid_lan91c111_s1_shift_register[1]);

--U1L91 is std_1c20:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_readdata[15]~2539_BDD339 at LC_X37_Y25_N7

--operation mode is normal

U1L91 = U1L89 # Y1_cpu_instruction_master_read_data_valid_ext_flash_s1_shift_register[1] & !U1_dbs_latent_8_reg_segment_1[7];

--U1L47 is std_1c20:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_readdata[9]~2540_BDD340 at LC_X44_Y27_N9

--operation mode is normal

U1L47 = NB1_cpu_instruction_master_read_data_valid_sdram_s1 & !KB1_za_data[9];

--U1L49 is std_1c20:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_readdata[9]~2541_BDD341 at LC_X40_Y26_N3

--operation mode is normal

U1L49 = U1L47 # !DE1_data_to_cpu[9] & X1L10 & W1L1;

--U1L51 is std_1c20:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_readdata[9]~2542_BDD342 at LC_X40_Y26_N2

--operation mode is normal

U1L51 = X1L10 & !U1L47 & !W1L1;

--U1L53 is std_1c20:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_readdata[9]~2543_BDD343 at LC_X39_Y25_N8

--operation mode is normal

U1L53 = !Y1_internal_incoming_ext_ram_bus_data[9] & (Y1_cpu_instruction_master_read_data_valid_lan91c111_s1_shift_register[1] # Y1_cpu_instruction_master_read_data_valid_ext_ram_s1_shift_register[1]);

--U1L55 is std_1c20:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_readdata[9]~2544_BDD344 at LC_X39_Y25_N5

--operation mode is normal

U1L55 = U1L53 # Y1_cpu_instruction_master_read_data_valid_ext_flash_s1_shift_register[1] & !U1_dbs_latent_8_reg_segment_1[1];

--U1L59 is std_1c20:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_readdata[10]~2545_BDD345 at LC_X44_Y22_N9

--operation mode is normal

U1L59 = !KB1_za_data[10] & NB1_cpu_instruction_master_read_data_valid_sdram_s1;

--U1L61 is std_1c20:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_readdata[10]~2546_BDD346 at LC_X45_Y23_N9

--operation mode is normal

U1L61 = U1L59 # X1L10 & !DE1_data_to_cpu[10] & W1L1;

--U1L63 is std_1c20:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_readdata[10]~2547_BDD347 at LC_X45_Y23_N5

--operation mode is normal

U1L63 = X1L10 & !W1L1 & (!U1L59);

--U1L65 is std_1c20:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_readdata[10]~2548_BDD348 at LC_X41_Y24_N6

--operation mode is normal

U1L65 = !Y1_internal_incoming_ext_ram_bus_data[10] & (Y1_cpu_instruction_master_read_data_valid_lan91c111_s1_shift_register[1] # Y1_cpu_instruction_master_read_data_valid_ext_ram_s1_shift_register[1]);

--U1L67 is std_1c20:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_readdata[10]~2549_BDD349 at LC_X41_Y25_N7

--operation mode is normal

U1L67 = U1L65 # Y1_cpu_instruction_master_read_data_valid_ext_flash_s1_shift_register[1] & !U1_dbs_latent_8_reg_segment_1[2];

--S1L440 is std_1c20:inst|cpu:the_cpu|d_readdata_d1[0]~204_BDD350 at LC_X41_Y23_N5

--operation mode is normal

S1L440 = AMPP_FUNCTION(T1_registered_cpu_data_master_readdata[0], S1L450, S1L448, S1L452);

--S1L442 is std_1c20:inst|cpu:the_cpu|d_readdata_d1[0]~205_BDD351 at LC_X38_Y24_N6

--operation mode is normal

S1L442 = AMPP_FUNCTION(DE1L45, X1_cpu_data_master_requests_epcs_controller_epcs_control_port, FE1_q_a[0], W1L1);

--S1L444 is std_1c20:inst|cpu:the_cpu|d_readdata_d1[0]~206_BDD352 at LC_X47_Y25_N3

--operation mode is normal

S1L444 = AMPP_FUNCTION(Z1_readdata[0], AB1_cpu_data_master_requests_high_res_timer_s1, RB1_readdata[0], SB1_cpu_data_master_requests_sys_clk_timer_s1);

--S1L446 is std_1c20:inst|cpu:the_cpu|d_readdata_d1[0]~207_BDD353 at LC_X45_Y22_N2

--operation mode is normal

S1L446 = AMPP_FUNCTION(XE1_readdata[0], H1_cpu_data_master_requests_button_pio_s1, G1_readdata[0], WB1_cpu_data_master_granted_uart1_s1);

--S1L1426 is std_1c20:inst|cpu:the_cpu|i_readdata_d1[6]~170_BDD354 at LC_X46_Y27_N2

--operation mode is normal

S1L1426 = AMPP_FUNCTION(X1L10, W1L1);

--S1L1428 is std_1c20:inst|cpu:the_cpu|i_readdata_d1[6]~171_BDD355 at LC_X46_Y27_N6

--operation mode is normal

S1L1428 = AMPP_FUNCTION(X1L10, DE1L82, W1L1);

--S1L1430 is std_1c20:inst|cpu:the_cpu|i_readdata_d1[6]~172_BDD356 at LC_X45_Y26_N7

--operation mode is normal

S1L1430 = AMPP_FUNCTION(U1_dbs_latent_8_reg_segment_0[6], KB1_za_data[6], Y1_cpu_instruction_master_read_data_valid_ext_flash_s1_shift_register[1], NB1_cpu_instruction_master_read_data_valid_sdram_s1);

--S1L1432 is std_1c20:inst|cpu:the_cpu|i_readdata_d1[6]~173_BDD357 at LC_X45_Y26_N8

--operation mode is normal

S1L1432 = AMPP_FUNCTION(Y1_cpu_instruction_master_read_data_valid_lan91c111_s1_shift_register[1], Y1_cpu_instruction_master_read_data_valid_ext_ram_s1_shift_register[1], Y1_internal_incoming_ext_ram_bus_data[6], S1L1430);

--S1L1402 is std_1c20:inst|cpu:the_cpu|i_readdata_d1[4]~174_BDD358 at LC_X38_Y23_N2

--operation mode is normal

S1L1402 = AMPP_FUNCTION(W1L1, X1L10);

--S1L1404 is std_1c20:inst|cpu:the_cpu|i_readdata_d1[4]~175_BDD359 at LC_X38_Y23_N6

--operation mode is normal

S1L1404 = AMPP_FUNCTION(X1L10, W1L1, DE1L60);

--S1L1406 is std_1c20:inst|cpu:the_cpu|i_readdata_d1[4]~176_BDD360 at LC_X38_Y23_N0

--operation mode is normal

S1L1406 = AMPP_FUNCTION(Y1_cpu_instruction_master_read_data_valid_ext_flash_s1_shift_register[1], U1_dbs_latent_8_reg_segment_0[4], NB1_cpu_instruction_master_read_data_valid_sdram_s1, KB1_za_data[4]);

--S1L1408 is std_1c20:inst|cpu:the_cpu|i_readdata_d1[4]~177_BDD361 at LC_X38_Y23_N1

--operation mode is normal

S1L1408 = AMPP_FUNCTION(Y1_cpu_instruction_master_read_data_valid_lan91c111_s1_shift_register[1], Y1_internal_incoming_ext_ram_bus_data[4], Y1_cpu_instruction_master_read_data_valid_ext_ram_s1_shift_register[1], S1L1406);

--S1L1380 is std_1c20:inst|cpu:the_cpu|i_readdata_d1[2]~179_BDD363 at LC_X38_Y24_N2

--operation mode is normal

S1L1380 = AMPP_FUNCTION(X1L10, DE1_data_to_cpu[2], W1L1);

--S1L1382 is std_1c20:inst|cpu:the_cpu|i_readdata_d1[2]~180_BDD364 at LC_X37_Y24_N6

--operation mode is normal

S1L1382 = AMPP_FUNCTION(NB1_cpu_instruction_master_read_data_valid_sdram_s1, U1_dbs_latent_8_reg_segment_0[2], Y1_cpu_instruction_master_read_data_valid_ext_flash_s1_shift_register[1], KB1_za_data[2]);

--S1L1384 is std_1c20:inst|cpu:the_cpu|i_readdata_d1[2]~181_BDD365 at LC_X37_Y24_N7

--operation mode is normal

S1L1384 = AMPP_FUNCTION(Y1_cpu_instruction_master_read_data_valid_ext_ram_s1_shift_register[1], Y1_cpu_instruction_master_read_data_valid_lan91c111_s1_shift_register[1], Y1_internal_incoming_ext_ram_bus_data[2], S1L1382);

--S1L1392 is std_1c20:inst|cpu:the_cpu|i_readdata_d1[3]~182_BDD366 at LC_X44_Y24_N7

--operation mode is normal

S1L1392 = AMPP_FUNCTION(X1L10, W1L1);

--S1L1394 is std_1c20:inst|cpu:the_cpu|i_readdata_d1[3]~183_BDD367 at LC_X44_Y24_N8

--operation mode is normal

S1L1394 = AMPP_FUNCTION(DE1_data_to_cpu[3], X1L10, W1L1);

--S1L1396 is std_1c20:inst|cpu:the_cpu|i_readdata_d1[3]~184_BDD368 at LC_X38_Y25_N6

--operation mode is normal

S1L1396 = AMPP_FUNCTION(Y1_cpu_instruction_master_read_data_valid_ext_flash_s1_shift_register[1], U1_dbs_latent_8_reg_segment_0[3], KB1_za_data[3], NB1_cpu_instruction_master_read_data_valid_sdram_s1);

--S1L1398 is std_1c20:inst|cpu:the_cpu|i_readdata_d1[3]~185_BDD369 at LC_X38_Y25_N7

--operation mode is normal

S1L1398 = AMPP_FUNCTION(Y1_cpu_instruction_master_read_data_valid_ext_ram_s1_shift_register[1], Y1_cpu_instruction_master_read_data_valid_lan91c111_s1_shift_register[1], Y1_internal_incoming_ext_ram_bus_data[3], S1L1396);

--S1L1412 is std_1c20:inst|cpu:the_cpu|i_readdata_d1[5]~186_BDD370 at LC_X46_Y23_N5

--operation mode is normal

S1L1412 = AMPP_FUNCTION(W1L1, X1L10);

--S1L1414 is std_1c20:inst|cpu:the_cpu|i_readdata_d1[5]~187_BDD371 at LC_X46_Y23_N3

--operation mode is normal

S1L1414 = AMPP_FUNCTION(X1L10, W1L1, DE1L68);

--S1L1416 is std_1c20:inst|cpu:the_cpu|i_readdata_d1[5]~188_BDD372 at LC_X45_Y25_N3

--operation mode is normal

S1L1416 = AMPP_FUNCTION(Y1_cpu_instruction_master_read_data_valid_ext_flash_s1_shift_register[1], NB1_cpu_instruction_master_read_data_valid_sdram_s1, U1_dbs_latent_8_reg_segment_0[5], KB1_za_data[5]);

--S1L1418 is std_1c20:inst|cpu:the_cpu|i_readdata_d1[5]~189_BDD373 at LC_X45_Y25_N2

--operation mode is normal

S1L1418 = AMPP_FUNCTION(Y1_cpu_instruction_master_read_data_valid_lan91c111_s1_shift_register[1], Y1_cpu_instruction_master_read_data_valid_ext_ram_s1_shift_register[1], Y1_internal_incoming_ext_ram_bus_data[5], S1L1416);

--T1L145 is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[8]~5352_BDD374 at LC_X45_Y23_N2

--operation mode is normal

T1L145 = X1_cpu_data_master_requests_epcs_controller_epcs_control_port & (W1L1 & !DE1_data_to_cpu[8] # !W1L1 & (!FE1_q_a[8]));

--T1L147 is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[8]~5353_BDD375 at LC_X46_Y26_N5

--operation mode is normal

T1L147 = T1L141 & T1L137 & (RB1_readdata[8] # !SB1_cpu_data_master_requests_sys_clk_timer_s1);

--T1L149 is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[8]~5354_BDD376 at LC_X46_Y23_N1

--operation mode is normal

T1L149 = Z1_readdata[8] & (XE1_readdata[8] # !WB1_cpu_data_master_granted_uart1_s1) # !Z1_readdata[8] & !AB1_cpu_data_master_requests_high_res_timer_s1 & (XE1_readdata[8] # !WB1_cpu_data_master_granted_uart1_s1);

--Y1L403 is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_flash_s1_wait_counter[3]~102_BDD377 at LC_X31_Y27_N3

--operation mode is normal

Y1L403 = Y1L396Q & (Y1L380 # !Y1L1010);

--Y1L405 is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_flash_s1_wait_counter[3]~103_BDD378 at LC_X31_Y27_N6

--operation mode is normal

Y1L405 = !Y1L770 & !Y1L122;

--G1L28 is std_1c20:inst|button_pio:the_button_pio|process1~15_BDD379 at LC_X45_Y22_N8

--operation mode is normal

G1L28 = S1_M_alu_result[6] & !S1L1726Q & G1L16;

--KB1L563 is std_1c20:inst|sdram:the_sdram|Mux32~1288_BDD380 at LC_X15_Y24_N6

--operation mode is normal

KB1L563 = !KB1_m_state[3] & (KB1_m_state[7] $ (KB1L558));

--KB1L565 is std_1c20:inst|sdram:the_sdram|Mux32~1289_BDD381 at LC_X15_Y24_N8

--operation mode is normal

KB1L565 = !KB1_m_state[4] & !KB1_m_state[7] & KB1_m_state[3];

--KB1L568 is std_1c20:inst|sdram:the_sdram|Mux32~1291_BDD383 at LC_X15_Y24_N1

--operation mode is normal

KB1L568 = KB1_m_state[0] # KB1L546 & KB1_init_done & KB1_refresh_request;

--KB1L570 is std_1c20:inst|sdram:the_sdram|Mux32~1292_BDD384 at LC_X15_Y24_N9

--operation mode is normal

KB1L570 = !KB1_m_state[0] & KB1L546 & (KB1_refresh_request # !KB1_init_done);

--KB1L572 is std_1c20:inst|sdram:the_sdram|Mux32~1293_BDD385 at LC_X15_Y24_N3

--operation mode is normal

KB1L572 = KB1L568 & KB1L570 # !KB1L568 & (KB1_m_state[8] # !KB1L570 & KB1_m_next[7]);

--KB1L574 is std_1c20:inst|sdram:the_sdram|Mux32~1294_BDD386 at LC_X15_Y24_N2

--operation mode is normal

KB1L574 = !KB1L570 & !KB1_m_state[8] & KB1_m_next[7] & KB1L568;

--KB1L576 is std_1c20:inst|sdram:the_sdram|Mux32~1295_BDD387 at LC_X15_Y24_N7

--operation mode is normal

KB1L576 = KB1L574 & !KB1_m_state[1] & (KB1L461) # !KB1L574 & (KB1L572);

--KB1L598 is std_1c20:inst|sdram:the_sdram|Mux38~1217_BDD389 at LC_X15_Y23_N7

--operation mode is normal

KB1L598 = KB1_m_next[1] & !KB1_m_state[8] & (KB1_m_state[0] # KB1L546);

--KB1L600 is std_1c20:inst|sdram:the_sdram|Mux38~1218_BDD390 at LC_X15_Y23_N6

--operation mode is normal

KB1L600 = !KB1_m_state[0] & (KB1_m_state[8] # KB1_m_next[1]);

--KB1L602 is std_1c20:inst|sdram:the_sdram|Mux38~1219_BDD391 at LC_X15_Y23_N0

--operation mode is normal

KB1L602 = !KB1_m_state[1] & (!KB1_m_state[4] & KB1L461);

--KB1L604 is std_1c20:inst|sdram:the_sdram|Mux38~1220_BDD392 at LC_X15_Y23_N5

--operation mode is normal

KB1L604 = KB1_m_state[3] & !KB1_m_state[7] & (KB1L602) # !KB1_m_state[3] & (KB1_m_state[7] $ KB1L558);

--KB1L606 is std_1c20:inst|sdram:the_sdram|Mux38~1221_BDD393 at LC_X15_Y24_N4

--operation mode is normal

KB1L606 = KB1_init_done & !KB1_refresh_request;

--DE1L17 is std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|A_WE_StdLogicVector~1136_BDD394 at LC_X36_Y26_N8

--operation mode is normal

DE1L17 = DE1L21 & (X1L4 & S1_M_alu_result[4] # !X1L4 & (S1_ic_fill_ap_offset[2]));

--DE1L19 is std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|A_WE_StdLogicVector~1137_BDD395 at LC_X37_Y26_N1

--operation mode is normal

DE1L19 = DE1L234Q & (!DE1L21 & X1L33);

--WE1L13 is std_1c20:inst|sdram_s1_arbitrator:the_sdram_s1|rdv_fifo_for_cpu_instruction_master_to_sdram_s1_module:rdv_fifo_for_cpu_instruction_master_to_sdram_s1|fifo_contains_ones_n~20_BDD396 at LC_X25_Y24_N8

--operation mode is normal

WE1L13 = !WE1L6 & !WE1L4 & !WE1L3;

--T1L217 is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[18]~5356_BDD398 at LC_X37_Y23_N8

--operation mode is normal

T1L217 = !Y1_internal_incoming_ext_ram_bus_data[18] & (Y1L146 # Y1_cpu_data_master_requests_ext_ram_s1);

--T1L219 is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[18]~5357_BDD399 at LC_X40_Y24_N0

--operation mode is normal

T1L219 = S1L1689Q & (T1L411Q & !T1L371Q # !T1L411Q & (!T1L412Q));

--T1L224 is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[19]~5358_BDD400 at LC_X40_Y24_N7

--operation mode is normal

T1L224 = !Y1_internal_incoming_ext_ram_bus_data[19] & (Y1_cpu_data_master_requests_ext_ram_s1 # Y1L146);

--T1L226 is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[19]~5359_BDD401 at LC_X40_Y24_N2

--operation mode is normal

T1L226 = S1L1689Q & (T1L411Q & !T1L376Q # !T1L411Q & (!T1L416Q));

--T1L246 is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[22]~5360_BDD402 at LC_X37_Y23_N3

--operation mode is normal

T1L246 = !Y1_internal_incoming_ext_ram_bus_data[22] & (Y1L146 # Y1_cpu_data_master_requests_ext_ram_s1);

--T1L248 is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[22]~5361_BDD403 at LC_X41_Y27_N8

--operation mode is normal

T1L248 = S1L1689Q & (T1L411Q & !T1L391Q # !T1L411Q & (!T1L428Q));

--T1L254 is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[23]~5362_BDD404 at LC_X36_Y22_N6

--operation mode is normal

T1L254 = !Y1_internal_incoming_ext_ram_bus_data[23] & (Y1_cpu_data_master_requests_ext_ram_s1 # Y1L146);

--T1L256 is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[23]~5363_BDD405 at LC_X40_Y23_N1

--operation mode is normal

T1L256 = S1L1689Q & (T1L411Q & (!T1L397Q) # !T1L411Q & !T1L432Q);

--T1L309 is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[31]~5364_BDD406 at LC_X37_Y23_N5

--operation mode is normal

T1L309 = !Y1_internal_incoming_ext_ram_bus_data[31] & (Y1_cpu_data_master_requests_ext_ram_s1 # Y1L146);

--T1L311 is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[31]~5365_BDD407 at LC_X40_Y23_N9

--operation mode is normal

T1L311 = S1L1689Q & !Y1_internal_incoming_ext_ram_bus_data[7];

--T1L238 is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[21]~5366_BDD408 at LC_X36_Y23_N5

--operation mode is normal

T1L238 = !Y1_internal_incoming_ext_ram_bus_data[21] & (Y1L146 # Y1_cpu_data_master_requests_ext_ram_s1);

--T1L240 is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[21]~5367_BDD409 at LC_X40_Y23_N0

--operation mode is normal

T1L240 = S1L1689Q & (T1L411Q & (!T1L386Q) # !T1L411Q & !T1L424Q);

--T1L261 is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[24]~5368_BDD410 at LC_X39_Y22_N7

--operation mode is normal

T1L261 = !Y1_internal_incoming_ext_ram_bus_data[24] & (Y1_cpu_data_master_requests_ext_ram_s1 # Y1L146);

--T1L263 is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[24]~5369_BDD411 at LC_X40_Y25_N9

--operation mode is normal

T1L263 = !Y1_internal_incoming_ext_ram_bus_data[0] & S1L1689Q;

--T1L201 is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[16]~5370_BDD412 at LC_X39_Y22_N6

--operation mode is normal

T1L201 = !Y1_internal_incoming_ext_ram_bus_data[16] & (Y1L146 # Y1_cpu_data_master_requests_ext_ram_s1);

--T1L203 is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[16]~5371_BDD413 at LC_X41_Y27_N6

--operation mode is normal

T1L203 = S1L1689Q & (T1L411Q & (!T1L361Q) # !T1L411Q & !T1L403Q);

--T1L297 is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[29]~5372_BDD414 at LC_X36_Y23_N4

--operation mode is normal

T1L297 = !Y1_internal_incoming_ext_ram_bus_data[29] & (Y1L146 # Y1_cpu_data_master_requests_ext_ram_s1);

--T1L299 is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[29]~5373_BDD415 at LC_X40_Y23_N8

--operation mode is normal

T1L299 = S1L1689Q & !Y1_internal_incoming_ext_ram_bus_data[5];

--T1L290 is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[28]~5374_BDD416 at LC_X37_Y23_N4

--operation mode is normal

T1L290 = !Y1_internal_incoming_ext_ram_bus_data[28] & (Y1_cpu_data_master_requests_ext_ram_s1 # Y1L146);

--T1L292 is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[28]~5375_BDD417 at LC_X38_Y23_N9

--operation mode is normal

T1L292 = !Y1_internal_incoming_ext_ram_bus_data[4] & S1L1689Q;

--T1L208 is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[17]~5376_BDD418 at LC_X41_Y24_N8

--operation mode is normal

T1L208 = !Y1_internal_incoming_ext_ram_bus_data[17] & (Y1_cpu_data_master_requests_ext_ram_s1 # Y1L146);

--T1L210 is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[17]~5377_BDD419 at LC_X41_Y27_N4

--operation mode is normal

T1L210 = S1L1689Q & (T1L411Q & (!T1L366Q) # !T1L411Q & !T1L407Q);

--T1L268 is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[25]~5378_BDD420 at LC_X39_Y24_N0

--operation mode is normal

T1L268 = !Y1_internal_incoming_ext_ram_bus_data[25] & (Y1L146 # Y1_cpu_data_master_requests_ext_ram_s1);

--T1L270 is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[25]~5379_BDD421 at LC_X39_Y24_N2

--operation mode is normal

T1L270 = !Y1_internal_incoming_ext_ram_bus_data[1] & S1L1689Q;

--T1L231 is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[20]~5380_BDD422 at LC_X40_Y24_N4

--operation mode is normal

T1L231 = !Y1_internal_incoming_ext_ram_bus_data[20] & (Y1L146 # Y1_cpu_data_master_requests_ext_ram_s1);

--T1L233 is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[20]~5381_BDD423 at LC_X42_Y22_N1

--operation mode is normal

T1L233 = S1L1689Q & (T1L411Q & (!T1L381Q) # !T1L411Q & !T1L420Q);

--T1L283 is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[27]~5382_BDD424 at LC_X39_Y25_N6

--operation mode is normal

T1L283 = !Y1_internal_incoming_ext_ram_bus_data[27] & (Y1_cpu_data_master_requests_ext_ram_s1 # Y1L146);

--T1L285 is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[27]~5383_BDD425 at LC_X39_Y25_N7

--operation mode is normal

T1L285 = S1L1689Q & !Y1_internal_incoming_ext_ram_bus_data[3];

--T1L276 is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[26]~5384_BDD426 at LC_X41_Y24_N2

--operation mode is normal

T1L276 = !Y1_internal_incoming_ext_ram_bus_data[26] & (Y1L146 # Y1_cpu_data_master_requests_ext_ram_s1);

--T1L278 is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[26]~5385_BDD427 at LC_X41_Y25_N8

--operation mode is normal

T1L278 = !Y1_internal_incoming_ext_ram_bus_data[2] & (S1L1689Q);

--T1L49 is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[1]~5386_BDD428 at LC_X39_Y24_N4

--operation mode is normal

T1L49 = !Y1_internal_incoming_ext_ram_bus_data[1] & (Y1L146 # Y1_cpu_data_master_requests_ext_ram_s1);

--T1L90 is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[4]~5387_BDD429 at LC_X38_Y23_N5

--operation mode is normal

T1L90 = !Y1_internal_incoming_ext_ram_bus_data[4] & (Y1L146 # Y1_cpu_data_master_requests_ext_ram_s1);

--V1L5 is std_1c20:inst|cpu_jtag_debug_module_arbitrator:the_cpu_jtag_debug_module|Add2~348_BDD430 at LC_X36_Y24_N8

--operation mode is normal

V1L5 = !S1L1451 & !V1L34Q;

--WE1L67 is std_1c20:inst|sdram_s1_arbitrator:the_sdram_s1|rdv_fifo_for_cpu_instruction_master_to_sdram_s1_module:rdv_fifo_for_cpu_instruction_master_to_sdram_s1|updated_one_count~72_BDD431 at LC_X24_Y23_N6

--operation mode is normal

WE1L67 = !NB1L22 & NB1_sdram_s1_arb_addend[0] & (TE1_entries[0] # !TE1_entries[1]);

--WE1L69 is std_1c20:inst|sdram_s1_arbitrator:the_sdram_s1|rdv_fifo_for_cpu_instruction_master_to_sdram_s1_module:rdv_fifo_for_cpu_instruction_master_to_sdram_s1|updated_one_count~73_BDD432 at LC_X24_Y23_N2

--operation mode is normal

WE1L69 = TE1_entries[1] & (NB1L22 & NB1_sdram_s1_arb_addend[0] # !TE1_entries[0]) # !TE1_entries[1] & NB1L22 & (NB1_sdram_s1_arb_addend[0]);

--RB1L9 is std_1c20:inst|sys_clk_timer:the_sys_clk_timer|control_wr_strobe~43_BDD433 at LC_X47_Y23_N0

--operation mode is normal

RB1L9 = XE1L18 & S1_internal_d_write & !T1_internal_cpu_data_master_waitrequest;

--T1L62 is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[2]~5388_BDD434 at LC_X46_Y25_N8

--operation mode is normal

T1L62 = !T1_registered_cpu_data_master_readdata[2] & N1_cpu_data_master_requests_clock_1_in;

--T1L64 is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[2]~5389_BDD435 at LC_X46_Y25_N0

--operation mode is normal

T1L64 = !T1_registered_cpu_data_master_readdata[2] & (CB1L2 & !N1_cpu_data_master_requests_clock_1_in);

--T1L66 is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[2]~5390_BDD436 at LC_X47_Y25_N7

--operation mode is normal

T1L66 = !Z1_readdata[2] & !S1_M_alu_result[6] & S1L1743Q & SB1L2;

--Y1L865 is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|iow_n_to_the_lan91c111~2_BDD437 at LC_X30_Y26_N4

--operation mode is normal

Y1L865 = Y1L976 & S1_internal_d_write & (Y1L653Q # Y1L718);

--DE1L258 is std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|Equal0~144_BDD438 at LC_X36_Y26_N2

--operation mode is normal

DE1L258 = S1_M_alu_result[3] & !S1_M_alu_result[4];

--DE1L260 is std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|Equal0~145_BDD439 at LC_X36_Y26_N9

--operation mode is normal

DE1L260 = !S1_ic_fill_ap_offset[2] & (S1_ic_fill_ap_offset[1]);

--Y1L106 is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|cpu_data_master_qualified_request_ext_ram_s1~145_BDD440 at LC_X32_Y21_N9

--operation mode is normal

Y1L106 = !S1L1855 & Y1L108 & !S1L1785 & !T1L449;

--Y1L1037Q is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|write_n_to_the_ext_ram_local~14 at LC_X32_Y21_N9

--operation mode is normal

Y1L1037Q = DFFEAS(Y1L106, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--Y1L108 is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|cpu_data_master_qualified_request_ext_ram_s1~146_BDD441 at LC_X33_Y25_N8

--operation mode is normal

Y1L108 = S1L1682 & !Y1_cpu_data_master_read_data_valid_ext_ram_s1_shift_register[0] & (!Y1L131) # !S1L1682 & (S1L1685);

--Y1L1038Q is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|write_n_to_the_ext_ram_local~15 at LC_X33_Y25_N8

--operation mode is normal

Y1L1038Q = DFFEAS(Y1L108, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--S1L346Q is std_1c20:inst|cpu:the_cpu|D_issue~8 at LC_X25_Y18_N6

--operation mode is normal

S1L346Q = AMPP_FUNCTION(QC2__clk0, S1_F_kill, S1L1225, S1L1220, S1L1221, F1_data_out, S1_W_stall);

--S1L342 is std_1c20:inst|cpu:the_cpu|D_issue~4_BDD443 at LC_X24_Y19_N1

--operation mode is normal

S1L342 = AMPP_FUNCTION(S1_D_pc[0], S1L347Q, S1L336Q, S1L335Q);

--S1L2389 is std_1c20:inst|cpu:the_cpu|M_valid_from_E~8_BDD444 at LC_X30_Y15_N2

--operation mode is normal

S1L2389 = AMPP_FUNCTION(S1_E_iw[11], S1L822, S1L760, S1L762);

--FD1L5 is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_avalon_reg:the_cpu_nios2_avalon_reg|Equal0~74_BDD445 at LC_X37_Y20_N1

--operation mode is normal

FD1L5 = AMPP_FUNCTION(S1_M_alu_result[9], S1L1756Q, S1_M_alu_result[7]);

--FD1L7 is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_avalon_reg:the_cpu_nios2_avalon_reg|Equal0~75_BDD446 at LC_X35_Y23_N2

--operation mode is normal

FD1L7 = AMPP_FUNCTION(S1_ic_fill_line[2], S1_ic_fill_line[4], S1_ic_fill_line[5]);

--FD1L9 is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_avalon_reg:the_cpu_nios2_avalon_reg|Equal0~76_BDD447 at LC_X35_Y23_N1

--operation mode is normal

FD1L9 = AMPP_FUNCTION(S1_M_alu_result[4], S1_M_alu_result[8], S1_M_alu_result[6], S1_M_alu_result[5]);

--FD1L11 is std_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_avalon_reg:the_cpu_nios2_avalon_reg|Equal0~77_BDD448 at LC_X35_Y23_N7

--operation mode is normal

FD1L11 = AMPP_FUNCTION(S1_ic_fill_line[3], S1_ic_fill_line[0], S1_ic_fill_line[1]);

--X1L23 is std_1c20:inst|epcs_controller_epcs_control_port_arbitrator:the_epcs_controller_epcs_control_port|d1_reasons_to_wait~12_BDD449 at LC_X34_Y23_N7

--operation mode is normal

X1L23 = !S1_internal_d_write & !S1_internal_d_read;

--X1L25 is std_1c20:inst|epcs_controller_epcs_control_port_arbitrator:the_epcs_controller_epcs_control_port|d1_reasons_to_wait~13_BDD450 at LC_X33_Y23_N3

--operation mode is normal

X1L25 = X1_cpu_instruction_master_granted_epcs_controller_epcs_control_port & X1L16 & !V1L58 & !S1L1593Q;

--X1L27 is std_1c20:inst|epcs_controller_epcs_control_port_arbitrator:the_epcs_controller_epcs_control_port|d1_reasons_to_wait~14_BDD451 at LC_X33_Y23_N0

--operation mode is normal

X1L27 = !X1_d1_reasons_to_wait & (X1_cpu_data_master_requests_epcs_controller_epcs_control_port # X1L10);

--Y1L582 is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_avalon_slave_arb_addend[0]~839_BDD453 at LC_X32_Y25_N5

--operation mode is normal

Y1L582 = !Y1L96 & !Y1L587 & !Y1L737;

--KB1L803 is std_1c20:inst|sdram:the_sdram|Mux110~1402_BDD456 at LC_X15_Y20_N7

--operation mode is normal

KB1L803 = KB1L744 & (KB1_f_select & (TE1L195) # !KB1_f_select & KB1_active_addr[5]);

--KB1L805 is std_1c20:inst|sdram:the_sdram|Mux110~1403_BDD457 at LC_X15_Y19_N3

--operation mode is normal

KB1L805 = KB1_m_state[0] & (KB1L796 # !KB1L794);

--KB1L807 is std_1c20:inst|sdram:the_sdram|Mux110~1404_BDD458 at LC_X15_Y19_N8

--operation mode is normal

KB1L807 = KB1_m_state[1] & (KB1L800 & KB1L906 # !KB1L190Q) # !KB1_m_state[1] & KB1L800;

--KB1L809 is std_1c20:inst|sdram:the_sdram|Mux110~1405_BDD459 at LC_X15_Y19_N4

--operation mode is normal

KB1L809 = KB1_m_state[1] & (KB1L190Q # KB1L800 & KB1L906);

--KB1L811 is std_1c20:inst|sdram:the_sdram|Mux110~1406_BDD460 at LC_X15_Y20_N6

--operation mode is normal

KB1L811 = KB1L809 & (KB1_active_addr[14] # !KB1L807);

--KB1L813 is std_1c20:inst|sdram:the_sdram|Mux110~1407_BDD461 at LC_X15_Y20_N9

--operation mode is normal

KB1L813 = KB1L807 & (!KB1L809 # !KB1_active_addr[14]);

--KB1L830 is std_1c20:inst|sdram:the_sdram|Mux111~1328_BDD462 at LC_X14_Y20_N0

--operation mode is normal

KB1L830 = !KB1_m_state[4] & !KB1_m_state[3];

--KB1L832 is std_1c20:inst|sdram:the_sdram|Mux111~1329_BDD463 at LC_X15_Y20_N1

--operation mode is normal

KB1L832 = KB1L744 & (KB1_f_select & (TE1L194) # !KB1_f_select & KB1_active_addr[4]);

--KB1L834 is std_1c20:inst|sdram:the_sdram|Mux111~1330_BDD464 at LC_X14_Y20_N4

--operation mode is normal

KB1L834 = KB1_m_state[0] & (KB1L824 # !KB1L822);

--KB1L836 is std_1c20:inst|sdram:the_sdram|Mux111~1331_BDD465 at LC_X14_Y20_N9

--operation mode is normal

KB1L836 = KB1_m_state[1] & (KB1L830 & KB1L828 # !KB1L185Q) # !KB1_m_state[1] & (KB1L828);

--KB1L838 is std_1c20:inst|sdram:the_sdram|Mux111~1332_BDD466 at LC_X14_Y20_N1

--operation mode is normal

KB1L838 = KB1_m_state[1] & (KB1L185Q # KB1L830 & KB1L828);

--KB1L840 is std_1c20:inst|sdram:the_sdram|Mux111~1333_BDD467 at LC_X14_Y20_N2

--operation mode is normal

KB1L840 = KB1L838 & (KB1_active_addr[13] # !KB1L836);

--KB1L842 is std_1c20:inst|sdram:the_sdram|Mux111~1334_BDD468 at LC_X14_Y20_N5

--operation mode is normal

KB1L842 = KB1L836 & (!KB1L838 # !KB1_active_addr[13]);

--Y1L713 is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_avalon_slave_arb_winner~40_BDD469 at LC_X28_Y23_N5

--operation mode is normal

Y1L713 = !Y1L742 & !Y1L770 & !Y1L905 & !Y1L176;

--S1L1899 is std_1c20:inst|cpu:the_cpu|M_alu_result[26]~423_BDD470 at LC_X36_Y12_N6

--operation mode is normal

S1L1899 = AMPP_FUNCTION(S1_E_ctrl_dst_data_sel_cmp, S1L1891Q, S1L1895, S1_W_stall);

--S1L1901 is std_1c20:inst|cpu:the_cpu|M_alu_result[26]~424_BDD471 at LC_X36_Y12_N1

--operation mode is normal

S1L1901 = AMPP_FUNCTION(S1_E_ctrl_dst_data_sel_cmp, S1_W_stall);

--S1L1903 is std_1c20:inst|cpu:the_cpu|M_alu_result[26]~425_BDD472 at LC_X36_Y12_N5

--operation mode is normal

S1L1903 = AMPP_FUNCTION(S1_E_logic_op[1], S1_E_logic_op[0], S1L1045, S1L1899);

--S1L1905 is std_1c20:inst|cpu:the_cpu|M_alu_result[26]~426_BDD473 at LC_X36_Y12_N4

--operation mode is normal

S1L1905 = AMPP_FUNCTION(S1_E_logic_op[1], S1_E_logic_op[0], S1L1045, S1L1899);

--S1L1907 is std_1c20:inst|cpu:the_cpu|M_alu_result[26]~427_BDD474 at LC_X36_Y12_N7

--operation mode is normal

S1L1907 = AMPP_FUNCTION(S1_E_logic_op[1], S1_E_logic_op[0], S1L1045, S1L1899);

--S1L1909 is std_1c20:inst|cpu:the_cpu|M_alu_result[26]~428_BDD475 at LC_X36_Y12_N2

--operation mode is normal

S1L1909 = AMPP_FUNCTION(S1L879, S1_E_ctrl_dst_data_sel_logic_result, S1_E_ctrl_dst_data_sel_pc_plus_one, S1_E_ctrl_rdctl_inst);

--S1L1911 is std_1c20:inst|cpu:the_cpu|M_alu_result[26]~429_BDD476 at LC_X36_Y12_N0

--operation mode is normal

S1L1911 = AMPP_FUNCTION(S1L1909, S1L1903, S1L1905, S1L1901);

--S1L1913 is std_1c20:inst|cpu:the_cpu|M_alu_result[26]~430_BDD477 at LC_X36_Y12_N8

--operation mode is normal

S1L1913 = AMPP_FUNCTION(S1L1909, S1L1903, S1L1905, S1L1901);

--S1L1924 is std_1c20:inst|cpu:the_cpu|M_alu_result[27]~431_BDD478 at LC_X37_Y12_N6

--operation mode is normal

S1L1924 = AMPP_FUNCTION(S1L1916Q, S1_W_stall, S1_E_ctrl_dst_data_sel_cmp, S1L1920);

--S1L1926 is std_1c20:inst|cpu:the_cpu|M_alu_result[27]~432_BDD479 at LC_X37_Y12_N3

--operation mode is normal

S1L1926 = AMPP_FUNCTION(S1_E_ctrl_dst_data_sel_cmp, S1_W_stall);

--S1L1928 is std_1c20:inst|cpu:the_cpu|M_alu_result[27]~433_BDD480 at LC_X37_Y12_N4

--operation mode is normal

S1L1928 = AMPP_FUNCTION(S1L1050, S1_E_logic_op[0], S1_E_logic_op[1], S1L1924);

--S1L1930 is std_1c20:inst|cpu:the_cpu|M_alu_result[27]~434_BDD481 at LC_X37_Y12_N7

--operation mode is normal

S1L1930 = AMPP_FUNCTION(S1L1050, S1_E_logic_op[0], S1_E_logic_op[1], S1L1924);

--S1L1932 is std_1c20:inst|cpu:the_cpu|M_alu_result[27]~435_BDD482 at LC_X37_Y12_N1

--operation mode is normal

S1L1932 = AMPP_FUNCTION(S1L1050, S1_E_logic_op[0], S1_E_logic_op[1], S1L1924);

--S1L1934 is std_1c20:inst|cpu:the_cpu|M_alu_result[27]~436_BDD483 at LC_X37_Y12_N0

--operation mode is normal

S1L1934 = AMPP_FUNCTION(S1L880, S1_E_ctrl_rdctl_inst, S1_E_ctrl_dst_data_sel_pc_plus_one, S1_E_ctrl_dst_data_sel_logic_result);

--S1L1936 is std_1c20:inst|cpu:the_cpu|M_alu_result[27]~437_BDD484 at LC_X37_Y12_N9

--operation mode is normal

S1L1936 = AMPP_FUNCTION(S1L1930, S1L1926, S1L1928, S1L1934);

--S1L1938 is std_1c20:inst|cpu:the_cpu|M_alu_result[27]~438_BDD485 at LC_X37_Y12_N8

--operation mode is normal

S1L1938 = AMPP_FUNCTION(S1L1930, S1L1926, S1L1928, S1L1934);

--S1L1948 is std_1c20:inst|cpu:the_cpu|M_alu_result[28]~439_BDD486 at LC_X35_Y12_N7

--operation mode is normal

S1L1948 = AMPP_FUNCTION(S1_E_ctrl_dst_data_sel_cmp, S1L1941Q, S1L1895, S1_W_stall);

--S1L1950 is std_1c20:inst|cpu:the_cpu|M_alu_result[28]~440_BDD487 at LC_X35_Y12_N0

--operation mode is normal

S1L1950 = AMPP_FUNCTION(S1_E_ctrl_dst_data_sel_cmp, S1_W_stall);

--S1L1952 is std_1c20:inst|cpu:the_cpu|M_alu_result[28]~441_BDD488 at LC_X35_Y12_N1

--operation mode is normal

S1L1952 = AMPP_FUNCTION(S1_E_logic_op[1], S1_E_logic_op[0], S1L1948, S1L1055);

--S1L1954 is std_1c20:inst|cpu:the_cpu|M_alu_result[28]~442_BDD489 at LC_X35_Y12_N8

--operation mode is normal

S1L1954 = AMPP_FUNCTION(S1_E_logic_op[1], S1L1055, S1_E_logic_op[0], S1L1948);

--S1L1956 is std_1c20:inst|cpu:the_cpu|M_alu_result[28]~443_BDD490 at LC_X35_Y12_N9

--operation mode is normal

S1L1956 = AMPP_FUNCTION(S1_E_logic_op[1], S1_E_logic_op[0], S1L1948, S1L1055);

--S1L1958 is std_1c20:inst|cpu:the_cpu|M_alu_result[28]~444_BDD491 at LC_X35_Y12_N4

--operation mode is normal

S1L1958 = AMPP_FUNCTION(S1_E_ctrl_rdctl_inst, S1_E_ctrl_dst_data_sel_pc_plus_one, S1L881, S1_E_ctrl_dst_data_sel_logic_result);

--S1L1960 is std_1c20:inst|cpu:the_cpu|M_alu_result[28]~445_BDD492 at LC_X35_Y12_N2

--operation mode is normal

S1L1960 = AMPP_FUNCTION(S1L1952, S1L1954, S1L1958, S1L1950);

--S1L1962 is std_1c20:inst|cpu:the_cpu|M_alu_result[28]~446_BDD493 at LC_X35_Y12_N5

--operation mode is normal

S1L1962 = AMPP_FUNCTION(S1L1952, S1L1954, S1L1958, S1L1950);

--S1L1972 is std_1c20:inst|cpu:the_cpu|M_alu_result[29]~447_BDD494 at LC_X34_Y12_N0

--operation mode is normal

S1L1972 = AMPP_FUNCTION(S1_W_stall, S1L2026, S1L1965Q, S1_E_ctrl_dst_data_sel_cmp);

--S1L1974 is std_1c20:inst|cpu:the_cpu|M_alu_result[29]~448_BDD495 at LC_X34_Y12_N7

--operation mode is normal

S1L1974 = AMPP_FUNCTION(S1_E_ctrl_dst_data_sel_cmp, S1_W_stall);

--S1L1976 is std_1c20:inst|cpu:the_cpu|M_alu_result[29]~449_BDD496 at LC_X34_Y12_N6

--operation mode is normal

S1L1976 = AMPP_FUNCTION(S1L1060, S1_E_logic_op[0], S1_E_logic_op[1], S1L1972);

--S1L1978 is std_1c20:inst|cpu:the_cpu|M_alu_result[29]~450_BDD497 at LC_X34_Y12_N1

--operation mode is normal

S1L1978 = AMPP_FUNCTION(S1L1060, S1_E_logic_op[0], S1_E_logic_op[1], S1L1972);

--S1L1980 is std_1c20:inst|cpu:the_cpu|M_alu_result[29]~451_BDD498 at LC_X34_Y12_N3

--operation mode is normal

S1L1980 = AMPP_FUNCTION(S1L1060, S1_E_logic_op[0], S1_E_logic_op[1], S1L1972);

--S1L1982 is std_1c20:inst|cpu:the_cpu|M_alu_result[29]~452_BDD499 at LC_X34_Y12_N5

--operation mode is normal

S1L1982 = AMPP_FUNCTION(S1_E_ctrl_rdctl_inst, S1_E_ctrl_dst_data_sel_logic_result, S1_E_ctrl_dst_data_sel_pc_plus_one, S1L882);

--S1L1984 is std_1c20:inst|cpu:the_cpu|M_alu_result[29]~453_BDD500 at LC_X34_Y12_N2

--operation mode is normal

S1L1984 = AMPP_FUNCTION(S1L1976, S1L1982, S1L1974, S1L1978);

--S1L1986 is std_1c20:inst|cpu:the_cpu|M_alu_result[29]~454_BDD501 at LC_X34_Y12_N9

--operation mode is normal

S1L1986 = AMPP_FUNCTION(S1L1976, S1L1982, S1L1974, S1L1978);

--Y1L496 is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_address[22]~53_BDD502 at LC_X26_Y23_N4

--operation mode is normal

Y1L496 = S1_ic_fill_tag[10] & (!Y1L43 & !Y1L40 # !U1L223);

--Y1L720 is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_avalon_slave_begins_xfer~62_BDD503 at LC_X30_Y26_N8

--operation mode is normal

Y1L720 = !Y1L1007 & !U1L223;

--S1L2119 is std_1c20:inst|cpu:the_cpu|M_ienable_reg[6]~693_BDD504 at LC_X35_Y19_N0

--operation mode is normal

S1L2119 = AMPP_FUNCTION(S1_E_ctrl_dst_data_sel_logic_result, S1_E_ctrl_rdctl_inst, S1_E_ctrl_dst_data_sel_cmp, S1_E_control_rd_data_without_mmu_regs[6]);

--S1L2121 is std_1c20:inst|cpu:the_cpu|M_ienable_reg[6]~694_BDD505 at LC_X35_Y19_N2

--operation mode is normal

S1L2121 = AMPP_FUNCTION(S1_E_ctrl_dst_data_sel_logic_result, S1_E_ctrl_rdctl_inst, S1_E_ctrl_dst_data_sel_cmp, S1_E_control_rd_data_without_mmu_regs[6]);

--S1L2112 is std_1c20:inst|cpu:the_cpu|M_ienable_reg[5]~695_BDD506 at LC_X34_Y19_N1

--operation mode is normal

S1L2112 = AMPP_FUNCTION(S1_E_ctrl_rdctl_inst, S1_E_ctrl_dst_data_sel_cmp, S1_E_ctrl_dst_data_sel_logic_result, S1_E_control_rd_data_without_mmu_regs[5]);

--S1L2114 is std_1c20:inst|cpu:the_cpu|M_ienable_reg[5]~696_BDD507 at LC_X34_Y19_N5

--operation mode is normal

S1L2114 = AMPP_FUNCTION(S1_E_ctrl_rdctl_inst, S1_E_ctrl_dst_data_sel_cmp, S1_E_ctrl_dst_data_sel_logic_result, S1_E_control_rd_data_without_mmu_regs[5]);

--Y1L18 is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|A_WE_StdLogicVector~4298_BDD508 at LC_X31_Y25_N7

--operation mode is normal

Y1L18 = !Y1L570 & (!Y1L547 & !Y1L533);

--Y1L592Q is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_avalon_slave_arb_addend[0]~873 at LC_X31_Y25_N7

--operation mode is normal

Y1L592Q = DFFEAS(Y1L18, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--Y1L593Q is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_avalon_slave_arb_addend[0]~874 at LC_X31_Y23_N6

--operation mode is normal

Y1L593Q_lut_out = Y1L644 & (Y1L559) # !Y1L644 & Y1L556Q;

Y1L593Q = DFFEAS(Y1L593Q_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--Y1L22 is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|A_WE_StdLogicVector~4300_BDD510 at LC_X31_Y25_N5

--operation mode is normal

Y1L22 = !Y1L568 & !Y1L571 & !Y1L565 & !Y1L529;

--Y1L594Q is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_avalon_slave_arb_addend[0]~875 at LC_X31_Y25_N5

--operation mode is normal

Y1L594Q = DFFEAS(Y1L22, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--DE1L79 is std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|data_to_cpu[5]~55_BDD511 at LC_X37_Y26_N2

--operation mode is normal

DE1L79 = X1L33 & (!X1L28);

--S1L984 is std_1c20:inst|cpu:the_cpu|E_src2[16]~1587_BDD512 at LC_X43_Y15_N6

--operation mode is normal

S1L984 = AMPP_FUNCTION(S1L2062Q, S1_M_shift_rot_result[16]);

--S1L986 is std_1c20:inst|cpu:the_cpu|E_src2[16]~1588_BDD513 at LC_X43_Y15_N2

--operation mode is normal

S1L986 = AMPP_FUNCTION(S1_E_src2_hazard_M, S1_E_src2_prelim[16], S1_E_ctrl_src2_is_imm, S1_E_src2_imm[16]);

--S1L988 is std_1c20:inst|cpu:the_cpu|E_src2[16]~1589_BDD514 at LC_X43_Y15_N0

--operation mode is normal

S1L988 = AMPP_FUNCTION(S1_E_src2_hazard_M, S1_E_src2_prelim[16], S1_E_ctrl_src2_is_imm, S1_E_src2_imm[16]);

--KB1L773 is std_1c20:inst|sdram:the_sdram|Mux109~1375_BDD515 at LC_X15_Y21_N9

--operation mode is normal

KB1L773 = !KB1_m_state[4] & !KB1_m_state[3];

--KB1L775 is std_1c20:inst|sdram:the_sdram|Mux109~1376_BDD516 at LC_X16_Y21_N6

--operation mode is normal

KB1L775 = KB1L771 & (KB1_f_select & (!KB1L769) # !KB1_f_select & !KB1_active_addr[6]) # !KB1L771 & (KB1L769);

--KB1L777 is std_1c20:inst|sdram:the_sdram|Mux109~1377_BDD517 at LC_X15_Y21_N1

--operation mode is normal

KB1L777 = !KB1_m_state[4] & !KB1_init_done & !KB1_m_state[3];

--KB1L779 is std_1c20:inst|sdram:the_sdram|Mux109~1378_BDD518 at LC_X15_Y21_N2

--operation mode is normal

KB1L779 = KB1_m_state[1] # !KB1_m_state[0] & !KB1L777;

--KB1L781 is std_1c20:inst|sdram:the_sdram|Mux109~1379_BDD519 at LC_X15_Y21_N4

--operation mode is normal

KB1L781 = KB1_m_state[1] & KB1_m_state[0] & KB1L773 # !KB1_m_state[1] & !KB1_m_state[0] & (KB1L777);

--KB1L783 is std_1c20:inst|sdram:the_sdram|Mux109~1380_BDD520 at LC_X15_Y21_N3

--operation mode is normal

KB1L783 = KB1L779 & (KB1L781 # KB1L195Q) # !KB1L779 & !KB1_i_addr[0] & KB1L781;

--KB1L785 is std_1c20:inst|sdram:the_sdram|Mux109~1381_BDD521 at LC_X15_Y21_N8

--operation mode is normal

KB1L785 = KB1L781 & (KB1L779 # KB1_i_addr[0]) # !KB1L781 & !KB1L195Q & KB1L779;

--KB1L857 is std_1c20:inst|sdram:the_sdram|Mux112~1358_BDD522 at LC_X12_Y21_N8

--operation mode is normal

KB1L857 = !KB1_m_state[3] & !KB1_m_state[4];

--KB1L859 is std_1c20:inst|sdram:the_sdram|Mux112~1359_BDD523 at LC_X13_Y19_N4

--operation mode is normal

KB1L859 = KB1L855 & (KB1_f_select & (!KB1L853) # !KB1_f_select & !KB1_active_addr[3]) # !KB1L855 & (KB1L853);

--KB1L863 is std_1c20:inst|sdram:the_sdram|Mux112~1362_BDD526 at LC_X12_Y21_N9

--operation mode is normal

KB1L863 = KB1L857 & (KB1_m_state[0] & (KB1_m_state[1]) # !KB1_m_state[0] & !KB1_init_done & !KB1_m_state[1]);

--KB1L865 is std_1c20:inst|sdram:the_sdram|Mux112~1363_BDD527 at LC_X13_Y19_N9

--operation mode is normal

KB1L865 = KB1L911 & (KB1L180Q # KB1L863) # !KB1L911 & (!KB1_i_addr[0] & KB1L863);

--KB1L867 is std_1c20:inst|sdram:the_sdram|Mux112~1364_BDD528 at LC_X13_Y19_N7

--operation mode is normal

KB1L867 = KB1L911 & (KB1L863 # !KB1L180Q) # !KB1L911 & (KB1_i_addr[0] & KB1L863);

--KB1L883 is std_1c20:inst|sdram:the_sdram|Mux113~1359_BDD530 at LC_X12_Y18_N1

--operation mode is normal

KB1L883 = KB1L880 & (KB1_f_select & (!KB1L878) # !KB1_f_select & !KB1_active_addr[2]) # !KB1L880 & (KB1L878);

--KB1L887 is std_1c20:inst|sdram:the_sdram|Mux113~1362_BDD533 at LC_X12_Y19_N4

--operation mode is normal

KB1L887 = KB1L932 & (KB1_m_state[0] & (KB1_m_state[1]) # !KB1_m_state[0] & !KB1_init_done & !KB1_m_state[1]);

--KB1L889 is std_1c20:inst|sdram:the_sdram|Mux113~1363_BDD534 at LC_X12_Y18_N5

--operation mode is normal

KB1L889 = KB1L911 & (KB1L175Q # KB1L887) # !KB1L911 & !KB1_i_addr[0] & (KB1L887);

--KB1L891 is std_1c20:inst|sdram:the_sdram|Mux113~1364_BDD535 at LC_X12_Y18_N9

--operation mode is normal

KB1L891 = KB1L911 & (KB1L887 # !KB1L175Q) # !KB1L911 & KB1_i_addr[0] & (KB1L887);

--KB1L906 is std_1c20:inst|sdram:the_sdram|Mux114~1358_BDD536 at LC_X15_Y19_N9

--operation mode is normal

KB1L906 = !KB1_m_state[3] & !KB1_m_state[4];

--KB1L908 is std_1c20:inst|sdram:the_sdram|Mux114~1359_BDD537 at LC_X14_Y19_N1

--operation mode is normal

KB1L908 = KB1L904 & (KB1_f_select & (!KB1L902) # !KB1_f_select & !KB1_active_addr[1]) # !KB1L904 & (KB1L902);

--KB1L911 is std_1c20:inst|sdram:the_sdram|Mux114~1361_BDD539 at LC_X12_Y19_N5

--operation mode is normal

KB1L911 = KB1_m_state[1] # !KB1_m_state[0] & (KB1_init_done # !KB1L932);

--KB1L913 is std_1c20:inst|sdram:the_sdram|Mux114~1362_BDD540 at LC_X15_Y19_N5

--operation mode is normal

KB1L913 = KB1L906 & (KB1_m_state[1] & (KB1_m_state[0]) # !KB1_m_state[1] & !KB1_init_done & !KB1_m_state[0]);

--KB1L915 is std_1c20:inst|sdram:the_sdram|Mux114~1363_BDD541 at LC_X14_Y19_N7

--operation mode is normal

KB1L915 = KB1L913 & (KB1L911 # !KB1_i_addr[0]) # !KB1L913 & (KB1L170Q & KB1L911);

--KB1L917 is std_1c20:inst|sdram:the_sdram|Mux114~1364_BDD542 at LC_X14_Y19_N5

--operation mode is normal

KB1L917 = KB1L913 & (KB1_i_addr[0] # KB1L911) # !KB1L913 & (!KB1L170Q & KB1L911);

--KB1L932 is std_1c20:inst|sdram:the_sdram|Mux115~1358_BDD543 at LC_X12_Y19_N2

--operation mode is normal

KB1L932 = !KB1_m_state[3] & !KB1_m_state[4];

--KB1L934 is std_1c20:inst|sdram:the_sdram|Mux115~1359_BDD544 at LC_X13_Y18_N4

--operation mode is normal

KB1L934 = KB1L930 & (KB1_f_select & (!KB1L928) # !KB1_f_select & !KB1_active_addr[0]) # !KB1L930 & (KB1L928);

--KB1L939 is std_1c20:inst|sdram:the_sdram|Mux115~1363_BDD548 at LC_X13_Y18_N0

--operation mode is normal

KB1L939 = KB1L911 & (KB1L165Q # KB1L887) # !KB1L911 & (KB1L887 & !KB1_i_addr[0]);

--KB1L941 is std_1c20:inst|sdram:the_sdram|Mux115~1364_BDD549 at LC_X13_Y18_N2

--operation mode is normal

KB1L941 = KB1L911 & (KB1L887 # !KB1L165Q) # !KB1L911 & (KB1L887 & KB1_i_addr[0]);

--S1L993 is std_1c20:inst|cpu:the_cpu|E_src2[17]~1590_BDD550 at LC_X41_Y14_N2

--operation mode is normal

S1L993 = AMPP_FUNCTION(S1_M_shift_rot_result[17], S1L2062Q);

--S1L995 is std_1c20:inst|cpu:the_cpu|E_src2[17]~1591_BDD551 at LC_X41_Y14_N9

--operation mode is normal

S1L995 = AMPP_FUNCTION(S1_E_ctrl_src2_is_imm, S1_E_src2_prelim[17], S1_E_src2_hazard_M, S1_E_src2_imm[17]);

--S1L997 is std_1c20:inst|cpu:the_cpu|E_src2[17]~1592_BDD552 at LC_X41_Y14_N4

--operation mode is normal

S1L997 = AMPP_FUNCTION(S1_E_ctrl_src2_is_imm, S1_E_src2_prelim[17], S1_E_src2_hazard_M, S1_E_src2_imm[17]);

--S1L1012 is std_1c20:inst|cpu:the_cpu|E_src2[19]~1594_BDD554 at LC_X40_Y15_N3

--operation mode is normal

S1L1012 = AMPP_FUNCTION(S1_E_src2_hazard_M, S1_E_src2_prelim[19], S1_E_ctrl_src2_is_imm, S1_E_src2_imm[19]);

--S1L1014 is std_1c20:inst|cpu:the_cpu|E_src2[19]~1595_BDD555 at LC_X40_Y15_N1

--operation mode is normal

S1L1014 = AMPP_FUNCTION(S1_E_src2_hazard_M, S1_E_src2_prelim[19], S1_E_ctrl_src2_is_imm, S1_E_src2_imm[19]);

--S1L1002 is std_1c20:inst|cpu:the_cpu|E_src2[18]~1596_BDD556 at LC_X41_Y15_N3

--operation mode is normal

S1L1002 = AMPP_FUNCTION(S1_M_shift_rot_result[18], S1L2062Q);

--S1L1004 is std_1c20:inst|cpu:the_cpu|E_src2[18]~1597_BDD557 at LC_X41_Y15_N8

--operation mode is normal

S1L1004 = AMPP_FUNCTION(S1_E_src2_hazard_M, S1_E_src2_imm[18], S1_E_ctrl_src2_is_imm, S1_E_src2_prelim[18]);

--S1L1006 is std_1c20:inst|cpu:the_cpu|E_src2[18]~1598_BDD558 at LC_X41_Y15_N9

--operation mode is normal

S1L1006 = AMPP_FUNCTION(S1_E_src2_hazard_M, S1_E_src2_imm[18], S1_E_ctrl_src2_is_imm, S1_E_src2_prelim[18]);

--Y1L1020 is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|read_n_to_the_ext_ram~2_BDD559 at LC_X31_Y22_N1

--operation mode is normal

Y1L1020 = S1_internal_d_read & Y1L104 & (Y1L51 # Y1L53);

--S1L448 is std_1c20:inst|cpu:the_cpu|d_readdata_d1[0]~208_BDD560 at LC_X41_Y23_N4

--operation mode is normal

S1L448 = AMPP_FUNCTION(N1_cpu_data_master_requests_clock_1_in, S1L1693Q, CB1_cpu_data_master_requests_jtag_uart_avalon_jtag_slave, K1_cpu_data_master_requests_clock_0_in);

--S1L450 is std_1c20:inst|cpu:the_cpu|d_readdata_d1[0]~209_BDD561 at LC_X40_Y25_N2

--operation mode is normal

S1L450 = AMPP_FUNCTION(S1L1689Q, T1L326, T1L35, T1L321);

--S1L452 is std_1c20:inst|cpu:the_cpu|d_readdata_d1[0]~210_BDD562 at LC_X47_Y22_N5

--operation mode is normal

S1L452 = AMPP_FUNCTION(A1L141, S1L1743Q, HB1_readdata, JB1L3);

--X1L32 is std_1c20:inst|epcs_controller_epcs_control_port_arbitrator:the_epcs_controller_epcs_control_port|epcs_controller_epcs_control_port_address[1]~75_BDD563 at LC_X33_Y23_N6

--operation mode is normal

X1L32 = !X1_epcs_controller_epcs_control_port_arb_addend[1] & (X1_epcs_controller_epcs_control_port_arb_addend[0] # X1L10);

--Y1L275 is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_outgoing_ext_ram_bus_data[6]~68_BDD564 at LC_X26_Y29_N1

--operation mode is normal

Y1L275 = T1L433 & Y1L100 & (Y1L37 # Y1L34);

--Y1L277 is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_outgoing_ext_ram_bus_data[6]~69_BDD565 at LC_X25_Y29_N7

--operation mode is normal

Y1L277 = T1_internal_cpu_data_master_dbs_address[1] & T1_internal_cpu_data_master_dbs_address[0] & !S1_M_st_data[30] # !T1_internal_cpu_data_master_dbs_address[1] & (T1_internal_cpu_data_master_dbs_address[0] & (!S1L2313Q) # !T1_internal_cpu_data_master_dbs_address[0] & !S1_M_st_data[30]);

--Y1L279 is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_outgoing_ext_ram_bus_data[6]~70_BDD566 at LC_X25_Y29_N2

--operation mode is normal

Y1L279 = T1_internal_cpu_data_master_dbs_address[1] & T1_internal_cpu_data_master_dbs_address[0] & S1_M_st_data[30] # !T1_internal_cpu_data_master_dbs_address[1] & (T1_internal_cpu_data_master_dbs_address[0] & (S1L2313Q) # !T1_internal_cpu_data_master_dbs_address[0] & S1_M_st_data[30]);

--Y1L281 is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_outgoing_ext_ram_bus_data[6]~71_BDD567 at LC_X25_Y29_N3

--operation mode is normal

Y1L281 = Y1L279 # S1L2355Q & !Y1L277;

--Y1L161 is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|cpu_instruction_master_continuerequest~63_BDD568 at LC_X27_Y21_N7

--operation mode is normal

Y1L161 = !S1L1610 & !S1L1634 & S1L1621 & !S1L1637;

--Y1L163 is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|cpu_instruction_master_continuerequest~64_BDD569 at LC_X27_Y21_N8

--operation mode is normal

Y1L163 = !Y1L159 & (Y1L711 & (!Y1L176) # !Y1L711 & !Y1L792);

--U1L188 is std_1c20:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_run~182_BDD570 at LC_X24_Y22_N4

--operation mode is normal

U1L188 = NB1_sdram_s1_arb_addend[0] & (NB1L22 # !NB1_sdram_s1_arb_addend[1]);

--U1L190 is std_1c20:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_run~183_BDD571 at LC_X24_Y22_N0

--operation mode is normal

U1L190 = NB1L27 & (NB1L30 # !TE1_entries[0] & TE1_entries[1]);

--U1L192 is std_1c20:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_run~184_BDD572 at LC_X28_Y22_N5

--operation mode is normal

U1L192 = X1L16 & (V1L58 # !V1_d1_reasons_to_wait & S1L1593Q);

--U1L230 is std_1c20:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|internal_cpu_instruction_master_latency_counter[0]~27_BDD573 at LC_X26_Y22_N5

--operation mode is normal

U1L230 = S1L1574Q & U1L258 & U1L259 & U1L164;

--U1L232 is std_1c20:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|internal_cpu_instruction_master_latency_counter[0]~28_BDD574 at LC_X26_Y22_N7

--operation mode is normal

U1L232 = U1L238Q & !U1_internal_cpu_instruction_master_latency_counter[0];

--KB1L752 is std_1c20:inst|sdram:the_sdram|Mux108~1509_BDD575 at LC_X14_Y21_N9

--operation mode is normal

KB1L752 = !KB1L742 & (KB1L744 & KB1L747 # !KB1L200Q);

--KB1L754 is std_1c20:inst|sdram:the_sdram|Mux108~1510_BDD576 at LC_X14_Y21_N7

--operation mode is normal

KB1L754 = !KB1L742 & (KB1L200Q & (KB1L744 # !KB1L747) # !KB1L200Q & (KB1L747));

--KB1L756 is std_1c20:inst|sdram:the_sdram|Mux108~1511_BDD577 at LC_X15_Y20_N2

--operation mode is normal

KB1L756 = KB1L744 & (KB1_f_select & (TE1L197) # !KB1_f_select & KB1_active_addr[7]);

--KB1L758 is std_1c20:inst|sdram:the_sdram|Mux108~1512_BDD578 at LC_X14_Y21_N4

--operation mode is normal

KB1L758 = KB1L740 & (!KB1L738) # !KB1L740 & !KB1_m_state[0] & (KB1L738 # KB1L731);

--T1L171 is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[11]~5391_BDD579 at LC_X44_Y23_N7

--operation mode is normal

T1L171 = S1L1743Q & H1L2 # !S1L1743Q & (S1_M_alu_result[6]);

--KB1L248 is std_1c20:inst|sdram:the_sdram|m_cmd~59_BDD580 at LC_X17_Y22_N2

--operation mode is normal

KB1L248 = !KB1L989 & !KB1L990 & (TE1_entries[0] # TE1_entries[1]);

--S1L2089 is std_1c20:inst|cpu:the_cpu|M_ienable_reg[1]~697_BDD581 at LC_X35_Y16_N0

--operation mode is normal

S1L2089 = AMPP_FUNCTION(S1L927, S1L852, S1_E_logic_op[1], S1_E_logic_op[0]);

--S1L2091 is std_1c20:inst|cpu:the_cpu|M_ienable_reg[1]~698_BDD582 at LC_X35_Y19_N7

--operation mode is normal

S1L2091 = AMPP_FUNCTION(S1_E_ctrl_dst_data_sel_cmp, S1_E_ctrl_rdctl_inst, S1_E_ctrl_dst_data_sel_logic_result, S1_E_control_rd_data_without_mmu_regs[1]);

--S1L2093 is std_1c20:inst|cpu:the_cpu|M_ienable_reg[1]~699_BDD583 at LC_X35_Y19_N4

--operation mode is normal

S1L2093 = AMPP_FUNCTION(S1_E_ctrl_dst_data_sel_logic_result, S1_E_ctrl_rdctl_inst, S1_E_ctrl_dst_data_sel_cmp, S1_E_control_rd_data_without_mmu_regs[1]);

--S1L2095 is std_1c20:inst|cpu:the_cpu|M_ienable_reg[1]~700_BDD584 at LC_X35_Y19_N1

--operation mode is normal

S1L2095 = AMPP_FUNCTION(S1_E_ctrl_dst_data_sel_pc_plus_one, S1L2091, S1L2089);

--S1L2097 is std_1c20:inst|cpu:the_cpu|M_ienable_reg[1]~701_BDD585 at LC_X35_Y19_N3

--operation mode is normal

S1L2097 = AMPP_FUNCTION(S1L2091, S1_E_ctrl_dst_data_sel_pc_plus_one);

--KB1L133 is std_1c20:inst|sdram:the_sdram|f_select~13_BDD586 at LC_X21_Y22_N1

--operation mode is normal

KB1L133 = !KB1_active_cs_n & !TE1L81 & (TE1_entries[1] # TE1_entries[0]);

--X1L3 is std_1c20:inst|epcs_controller_epcs_control_port_arbitrator:the_epcs_controller_epcs_control_port|Add2~345_BDD587 at LC_X33_Y23_N4

--operation mode is normal

X1L3 = !X1_epcs_controller_epcs_control_port_arb_addend[1] & !S1L1773Q & (X1_epcs_controller_epcs_control_port_arb_addend[0] # X1L10);

--VE1L14 is std_1c20:inst|sdram_s1_arbitrator:the_sdram_s1|rdv_fifo_for_cpu_data_master_to_sdram_s1_module:rdv_fifo_for_cpu_data_master_to_sdram_s1|fifo_contains_ones_n~22_BDD588 at LC_X23_Y24_N5

--operation mode is normal

VE1L14 = WE1L33 & (VE1L3 # VE1L6) # !WE1L33 & VE1L8Q;

--VE1L16 is std_1c20:inst|sdram_s1_arbitrator:the_sdram_s1|rdv_fifo_for_cpu_data_master_to_sdram_s1_module:rdv_fifo_for_cpu_data_master_to_sdram_s1|fifo_contains_ones_n~23_BDD589 at LC_X23_Y24_N8

--operation mode is normal

VE1L16 = !VE1L6 & WE1L33 & !VE1L3;

--T1L534 is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|r_2~103_BDD590 at LC_X36_Y25_N3

--operation mode is normal

T1L534 = !S1_M_alu_result[5] & JB1L2 & UB1L7 & S1_internal_d_read;

--SB1L7 is std_1c20:inst|sys_clk_timer_s1_arbitrator:the_sys_clk_timer_s1|cpu_data_master_requests_sys_clk_timer_s1~183_BDD591 at LC_X37_Y25_N8

--operation mode is normal

SB1L7 = S1L1686Q & !S1_M_alu_result[7] & V1L8 & UB1L4;

--S1L332Q is std_1c20:inst|cpu:the_cpu|D_inst_ram_hit~16 at LC_X25_Y18_N5

--operation mode is normal

S1L332Q = AMPP_FUNCTION(QC2__clk0, S1L1220, S1L1219, S1L1225, S1L1221, F1_data_out, S1_W_stall);

--S1L328 is std_1c20:inst|cpu:the_cpu|D_inst_ram_hit~13_BDD594 at LC_X24_Y19_N5

--operation mode is normal

S1L328 = AMPP_FUNCTION(S1_D_pc[0], S1L334Q, S1L336Q, S1L335Q);

--S1L333Q is std_1c20:inst|cpu:the_cpu|D_inst_ram_hit~18 at LC_X25_Y19_N7

--operation mode is normal

S1L333Q = AMPP_FUNCTION(QC2__clk0, S1_F_pc[22], BD1_q_b[9], BD1_q_b[20], S1_F_pc[11], F1_data_out, S1_W_stall);

--VE1L52 is std_1c20:inst|sdram_s1_arbitrator:the_sdram_s1|rdv_fifo_for_cpu_data_master_to_sdram_s1_module:rdv_fifo_for_cpu_data_master_to_sdram_s1|updated_one_count~72_BDD596 at LC_X24_Y23_N3

--operation mode is normal

VE1L52 = NB1L22 & !NB1_sdram_s1_arb_addend[0] & (NB1_sdram_s1_arb_addend[1] $ S1_internal_d_read);

--VE1L54 is std_1c20:inst|sdram_s1_arbitrator:the_sdram_s1|rdv_fifo_for_cpu_data_master_to_sdram_s1_module:rdv_fifo_for_cpu_data_master_to_sdram_s1|updated_one_count~73_BDD597 at LC_X24_Y23_N8

--operation mode is normal

VE1L54 = NB1_sdram_s1_arb_addend[1] & NB1L22 & (S1_internal_d_read # !NB1_sdram_s1_arb_addend[0]);

--K1L13 is std_1c20:inst|clock_0_in_arbitrator:the_clock_0_in|cpu_data_master_requests_clock_0_in~541_BDD598 at LC_X33_Y17_N7

--operation mode is normal

K1L13 = !S1L1762Q & !S1_M_alu_result[13] & !S1_M_alu_result[11] & !S1_M_alu_result[12];

--K1L15 is std_1c20:inst|clock_0_in_arbitrator:the_clock_0_in|cpu_data_master_requests_clock_0_in~542_BDD599 at LC_X33_Y21_N7

--operation mode is normal

K1L15 = !S1L1866Q & !S1L1776Q & !S1_M_alu_result[16] & !S1_M_alu_result[15];

--K1L17 is std_1c20:inst|clock_0_in_arbitrator:the_clock_0_in|cpu_data_master_requests_clock_0_in~543_BDD600 at LC_X33_Y21_N5

--operation mode is normal

K1L17 = !S1L1779Q & !S1L1800Q & (S1_internal_d_read # S1_internal_d_write);

--Y1L585 is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_avalon_slave_arb_addend[0]~841_BDD601 at LC_X30_Y25_N0

--operation mode is normal

Y1L585 = !Y1L587 & !Y1L737 & !Y1L916;

--Y1L587 is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_avalon_slave_arb_addend[0]~842_BDD602 at LC_X29_Y25_N0

--operation mode is normal

Y1L587 = Y1L100 & (Y1L37 # Y1L34);

--Y1L487 is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_address[21]~54_BDD603 at LC_X27_Y23_N2

--operation mode is normal

Y1L487 = S1_ic_fill_tag[9] & (!Y1L40 & !Y1L43 # !U1L223);

--Y1L213 is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_in_a_write_cycle~2_BDD604 at LC_X29_Y26_N3

--operation mode is normal

Y1L213 = !Y1L215 & (!Y1L51 & !Y1L53 # !Y1L104);

--Y1L716 is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_avalon_slave_arbitration_holdoff_internal~10_BDD605 at LC_X28_Y24_N6

--operation mode is normal

Y1L716 = !Y1L874 & !Y1L1007 & !U1L223;

--Y1L264 is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_outgoing_ext_ram_bus_data[5]~72_BDD606 at LC_X25_Y22_N3

--operation mode is normal

Y1L264 = T1L433 & Y1L100 & (Y1L34 # Y1L37);

--Y1L266 is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_outgoing_ext_ram_bus_data[5]~73_BDD607 at LC_X25_Y22_N7

--operation mode is normal

Y1L266 = T1_internal_cpu_data_master_dbs_address[0] & (T1_internal_cpu_data_master_dbs_address[1] & (!S1_M_st_data[29]) # !T1_internal_cpu_data_master_dbs_address[1] & !S1L2307Q) # !T1_internal_cpu_data_master_dbs_address[0] & (!S1_M_st_data[29] & !T1_internal_cpu_data_master_dbs_address[1]);

--Y1L268 is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_outgoing_ext_ram_bus_data[5]~74_BDD608 at LC_X25_Y22_N2

--operation mode is normal

Y1L268 = T1_internal_cpu_data_master_dbs_address[0] & (T1_internal_cpu_data_master_dbs_address[1] & (S1_M_st_data[29]) # !T1_internal_cpu_data_master_dbs_address[1] & S1L2307Q) # !T1_internal_cpu_data_master_dbs_address[0] & (S1_M_st_data[29] & !T1_internal_cpu_data_master_dbs_address[1]);

--Y1L270 is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_outgoing_ext_ram_bus_data[5]~75_BDD609 at LC_X25_Y22_N8

--operation mode is normal

Y1L270 = Y1L268 # !Y1L266 & S1L2350Q;

--Y1L92 is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|cpu_data_master_continuerequest~105_BDD610 at LC_X33_Y20_N9

--operation mode is normal

Y1L92 = Y1_cpu_data_master_requests_ext_flash_s1 & QB1L1 & (Y1L94 # Y1L663);

--Y1L784Q is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_avalon_slave_saved_chosen_master_vector[3]~702 at LC_X33_Y20_N9

--operation mode is normal

Y1L784Q = DFFEAS(Y1L92, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--Y1L94 is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|cpu_data_master_continuerequest~106_BDD611 at LC_X32_Y23_N5

--operation mode is normal

Y1L94 = Y1L896 & (!Y1_ext_ram_bus_avalon_slave_arbitration_holdoff_internal);

--Y1L785Q is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_avalon_slave_saved_chosen_master_vector[3]~703 at LC_X32_Y23_N5

--operation mode is normal

Y1L785Q = DFFEAS(Y1L94, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--Y1L165 is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|cpu_instruction_master_continuerequest~65_BDD612 at LC_X27_Y21_N4

--operation mode is normal

Y1L165 = Y1L194 & !S1L1634 & !S1L1643 & !S1L1637;

--Y1L167 is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|cpu_instruction_master_continuerequest~66_BDD613 at LC_X28_Y24_N1

--operation mode is normal

Y1L167 = Y1L713 & (Y1L171 & Y1L762 # !Y1L171 & (Y1L174)) # !Y1L713 & (Y1L174);

--Y1L169 is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|cpu_instruction_master_continuerequest~67_BDD614 at LC_X28_Y24_N8

--operation mode is normal

Y1L169 = Y1L945 & (!Y1_ext_ram_bus_avalon_slave_arbitration_holdoff_internal);

--T1L464 is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|internal_cpu_data_master_waitrequest~29_BDD615 at LC_X33_Y22_N2

--operation mode is normal

T1L464 = !X1L1 & !T1L15 & !T1L9 & !T1L3;

--T1L466 is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|internal_cpu_data_master_waitrequest~30_BDD616 at LC_X32_Y22_N6

--operation mode is normal

T1L466 = T1L6 # !Y1L53 & Y1L104 & !Y1L51;

--T1L468 is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|internal_cpu_data_master_waitrequest~31_BDD617 at LC_X32_Y22_N0

--operation mode is normal

T1L468 = T1L460 & (Y1L100 # T1L529 # !S1L1689Q);

--S1L1871 is std_1c20:inst|cpu:the_cpu|M_alu_result[25]~325_DUP_COMB_457 at LC_X32_Y20_N6

--operation mode is normal

S1L1871 = AMPP_FUNCTION(S1_E_ctrl_dst_data_sel_logic_result, S1L1883, S1L1789, S1L1879);

--S1L207Q is std_1c20:inst|cpu:the_cpu|av_ld_data_aligned_or_div[25]~105 at LC_X32_Y20_N6

--operation mode is normal

S1L207Q = AMPP_FUNCTION(QC2__clk0, S1_E_ctrl_dst_data_sel_logic_result, S1L1883, S1L1789, S1L1879, F1_data_out);

--S1L1851 is std_1c20:inst|cpu:the_cpu|M_alu_result[24]~323_DUP_COMB_459 at LC_X33_Y20_N5

--operation mode is normal

S1L1851 = AMPP_FUNCTION(S1L1789, S1L1860, S1_E_ctrl_dst_data_sel_logic_result, S1L1864);

--S1L1866Q is std_1c20:inst|cpu:the_cpu|M_alu_result[24]~467 at LC_X33_Y20_N5

--operation mode is normal

S1L1866Q = AMPP_FUNCTION(QC2__clk0, S1L1789, S1L1860, S1_E_ctrl_dst_data_sel_logic_result, S1L1864, F1_data_out);

--T1L448Q is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|internal_cpu_data_master_dbs_address[1]~66 at LC_X34_Y21_N4

--operation mode is normal

T1L448Q_lut_out = S1_E_ctrl_dst_data_sel_logic_result & (S1L1846) # !S1_E_ctrl_dst_data_sel_logic_result & (S1L1789 & S1L1842 # !S1L1789 & (S1L1846));

T1L448Q = DFFEAS(T1L448Q_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--S1L1817 is std_1c20:inst|cpu:the_cpu|M_alu_result[22]~337_DUP_COMB_463 at LC_X31_Y16_N7

--operation mode is normal

S1L1817 = AMPP_FUNCTION(S1L1823, S1_E_ctrl_dst_data_sel_logic_result, S1L1829, S1L1825);

--S1L1885Q is std_1c20:inst|cpu:the_cpu|M_alu_result[25]~465 at LC_X31_Y16_N7

--operation mode is normal

S1L1885Q = AMPP_FUNCTION(QC2__clk0, S1L1823, S1_E_ctrl_dst_data_sel_logic_result, S1L1829, S1L1825, F1_data_out);

--S1L1888Q is std_1c20:inst|cpu:the_cpu|M_alu_result[25]~466 at LC_X31_Y18_N0

--operation mode is normal

S1L1888Q = AMPP_FUNCTION(QC2__clk0, S1L1789, S1L1808, S1L1812, S1_E_ctrl_dst_data_sel_logic_result, F1_data_out);

--T1L441 is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|internal_cpu_data_master_dbs_address[0]~_DUP_COMB at LC_X29_Y26_N7

--operation mode is normal

T1L441 = T1_internal_cpu_data_master_dbs_address[0] $ (T1L440 & (T1L523) # !T1L440 & T1L438);

--T1L453 is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|internal_cpu_data_master_dbs_address[1]~_DUP_COMB at LC_X29_Y21_N3

--operation mode is normal

T1L453 = T1_internal_cpu_data_master_dbs_address[1] $ (S1L1689Q & T1_internal_cpu_data_master_dbs_address[0] & T1L524);

--T1L450Q is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|internal_cpu_data_master_dbs_address[1]~67 at LC_X29_Y21_N0

--operation mode is normal

T1L450Q_lut_out = !T1L453 & (T1L441 & (S1L2161) # !T1L441 & S1L2152);

T1L450Q = DFFEAS(T1L450Q_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--T1L451Q is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|internal_cpu_data_master_dbs_address[1]~68 at LC_X29_Y21_N1

--operation mode is normal

T1L451Q_lut_out = T1L453 & (T1L441 & S1L2180 # !T1L441 & (S1L2171));

T1L451Q = DFFEAS(T1L451Q_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--Y1L204 is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_ext_ram_bus_avalon_slave_end_xfer~6_DUP_COMB at LC_X30_Y24_N0

--operation mode is normal

Y1L204 = Y1L122 # U1L223 & (Y1L40 # Y1L43);

--Y1L696 is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_avalon_slave_arb_share_counter[0]~605_DUP_COMB_612 at LC_X31_Y23_N7

--operation mode is normal

Y1L696 = !Y1L799 & !Y1L770 & !Y1L742;

--S1L1499 is std_1c20:inst|cpu:the_cpu|ic_fill_ap_cnt[0]~24_DUP_COMB_56 at LC_X26_Y22_N2

--operation mode is normal

S1L1499 = AMPP_FUNCTION(U1L170, U1L258, U1L257, U1L165);

--S1L1503 is std_1c20:inst|cpu:the_cpu|ic_fill_ap_cnt[0]~45_DUP_COMB_57 at LC_X28_Y22_N8

--operation mode is normal

S1L1503 = AMPP_FUNCTION(S1L1501, S1L1526, S1L1499, S1_D_ic_fill_starting);

--S1L1574Q is std_1c20:inst|cpu:the_cpu|ic_fill_tag[0]~112 at LC_X28_Y22_N8

--operation mode is normal

S1L1574Q = AMPP_FUNCTION(QC2__clk0, S1L1501, S1L1526, S1L1499, S1_D_ic_fill_starting, F1_data_out);

--S1L1627Q is std_1c20:inst|cpu:the_cpu|ic_fill_tag[9]~109 at LC_X30_Y20_N0

--operation mode is normal

S1L1627Q = AMPP_FUNCTION(QC2__clk0, S1L1599, S1L1591, S1L1620, S1L1504, F1_data_out);

--Y1L533 is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_avalon_slave_arb_addend[0]~753_DUP_COMB at LC_X31_Y25_N6

--operation mode is normal

Y1L533 = Y1L645 & Y1L177 # !Y1L645 & (Y1L532Q);

--Y1L540 is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_avalon_slave_arb_addend[0]~757_DUP_COMB at LC_X31_Y25_N4

--operation mode is normal

Y1L540 = Y1L645 & (Y1L770) # !Y1L645 & Y1L539Q;

--Y1L595Q is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_avalon_slave_arb_addend[0]~876 at LC_X31_Y25_N4

--operation mode is normal

Y1L595Q = DFFEAS(Y1L540, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--Y1L547 is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_avalon_slave_arb_addend[0]~761_DUP_COMB at LC_X31_Y25_N9

--operation mode is normal

Y1L547 = Y1L645 & (Y1L737) # !Y1L645 & Y1L546Q;

--Y1L529 is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_avalon_slave_arb_addend[0]~751_DUP_COMB at LC_X31_Y25_N1

--operation mode is normal

Y1L529 = Y1L645 & (Y1L730) # !Y1L645 & Y1L528Q;

--Y1L645 is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_avalon_slave_arb_addend[4]~707_DUP_COMB_862 at LC_X30_Y25_N2

--operation mode is normal

Y1L645 = Y1L916 # Y1L737 # Y1L587 # !Y1L696;

--Y1L658Q is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_avalon_slave_arb_addend[4]~864 at LC_X30_Y25_N2

--operation mode is normal

Y1L658Q = DFFEAS(Y1L645, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--Y1L818Q is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_avalon_slave_slavearbiterlockenable~199 at LC_X31_Y21_N2

--operation mode is normal

Y1L818Q_lut_out = Y1L721 # !Y1L181 & (Y1L372 # Y1L204);

Y1L818Q = DFFEAS(Y1L818Q_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--Y1L557 is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_avalon_slave_arb_addend[0]~795_DUP_COMB_879 at LC_X32_Y23_N4

--operation mode is normal

Y1L557 = Y1L644 & Y1L559 # !Y1L644 & (Y1L556Q);

--DE1L170Q is std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|epcs_slave_select_holding_reg[1]~7248 at LC_X37_Y29_N3

--operation mode is normal

DE1L170Q_lut_out = DE1_slaveselect_wr_strobe & (S1_M_st_data[1]) # !DE1_slaveselect_wr_strobe & DE1L170Q;

DE1L170Q = DFFEAS(DE1L170Q_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--DE1L167Q is std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|epcs_slave_select_holding_reg[0]~7250 at LC_X37_Y29_N9

--operation mode is normal

DE1L167Q_lut_out = DE1_slaveselect_wr_strobe & !S1_M_st_data[0] # !DE1_slaveselect_wr_strobe & (DE1L167Q);

DE1L167Q = DFFEAS(DE1L167Q_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--DE1L179Q is std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|epcs_slave_select_holding_reg[4]~7252 at LC_X35_Y29_N8

--operation mode is normal

DE1L179Q_lut_out = DE1_slaveselect_wr_strobe & S1_M_st_data[4] # !DE1_slaveselect_wr_strobe & (DE1L179Q);

DE1L179Q = DFFEAS(DE1L179Q_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--DE1L185Q is std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|epcs_slave_select_holding_reg[6]~7254 at LC_X35_Y28_N6

--operation mode is normal

DE1L185Q_lut_out = DE1_slaveselect_wr_strobe & S1_M_st_data[6] # !DE1_slaveselect_wr_strobe & (DE1L185Q);

DE1L185Q = DFFEAS(DE1L185Q_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--DE1L191Q is std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|epcs_slave_select_holding_reg[8]~7256 at LC_X38_Y27_N1

--operation mode is normal

DE1L191Q_lut_out = DE1_slaveselect_wr_strobe & S1L2275Q # !DE1_slaveselect_wr_strobe & (DE1L191Q);

DE1L191Q = DFFEAS(DE1L191Q_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--DE1L194Q is std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|epcs_slave_select_holding_reg[9]~7258 at LC_X35_Y28_N2

--operation mode is normal

DE1L194Q_lut_out = DE1_slaveselect_wr_strobe & (S1L2281Q) # !DE1_slaveselect_wr_strobe & DE1L194Q;

DE1L194Q = DFFEAS(DE1L194Q_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--DE1L197Q is std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|epcs_slave_select_holding_reg[10]~7260 at LC_X36_Y27_N2

--operation mode is normal

DE1L197Q_lut_out = DE1_slaveselect_wr_strobe & S1L2288Q # !DE1_slaveselect_wr_strobe & (DE1L197Q);

DE1L197Q = DFFEAS(DE1L197Q_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--DE1L200Q is std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|epcs_slave_select_holding_reg[11]~7262 at LC_X36_Y29_N8

--operation mode is normal

DE1L200Q_lut_out = DE1_slaveselect_wr_strobe & (S1L2294Q) # !DE1_slaveselect_wr_strobe & DE1L200Q;

DE1L200Q = DFFEAS(DE1L200Q_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--DE1L203Q is std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|epcs_slave_select_holding_reg[12]~7264 at LC_X35_Y28_N4

--operation mode is normal

DE1L203Q_lut_out = DE1_slaveselect_wr_strobe & (S1L2301Q) # !DE1_slaveselect_wr_strobe & DE1L203Q;

DE1L203Q = DFFEAS(DE1L203Q_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--DE1L206Q is std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|epcs_slave_select_holding_reg[13]~7266 at LC_X36_Y28_N9

--operation mode is normal

DE1L206Q_lut_out = DE1_slaveselect_wr_strobe & (S1L2307Q) # !DE1_slaveselect_wr_strobe & DE1L206Q;

DE1L206Q = DFFEAS(DE1L206Q_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--DE1L209Q is std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|epcs_slave_select_holding_reg[14]~7268 at LC_X36_Y28_N5

--operation mode is normal

DE1L209Q_lut_out = DE1_slaveselect_wr_strobe & (S1L2313Q) # !DE1_slaveselect_wr_strobe & DE1L209Q;

DE1L209Q = DFFEAS(DE1L209Q_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--DE1L188Q is std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|epcs_slave_select_holding_reg[7]~7270 at LC_X35_Y29_N6

--operation mode is normal

DE1L188Q_lut_out = DE1_slaveselect_wr_strobe & (S1_M_st_data[7]) # !DE1_slaveselect_wr_strobe & DE1L188Q;

DE1L188Q = DFFEAS(DE1L188Q_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--DE1L212Q is std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|epcs_slave_select_holding_reg[15]~7272 at LC_X36_Y29_N2

--operation mode is normal

DE1L212Q_lut_out = DE1_slaveselect_wr_strobe & S1L2319Q # !DE1_slaveselect_wr_strobe & (DE1L212Q);

DE1L212Q = DFFEAS(DE1L212Q_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--DE1L182Q is std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|epcs_slave_select_holding_reg[5]~7274 at LC_X36_Y27_N7

--operation mode is normal

DE1L182Q_lut_out = DE1_slaveselect_wr_strobe & (S1_M_st_data[5]) # !DE1_slaveselect_wr_strobe & DE1L182Q;

DE1L182Q = DFFEAS(DE1L182Q_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--DE1L176Q is std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|epcs_slave_select_holding_reg[3]~7276 at LC_X35_Y29_N5

--operation mode is normal

DE1L176Q_lut_out = DE1_slaveselect_wr_strobe & S1_M_st_data[3] # !DE1_slaveselect_wr_strobe & (DE1L176Q);

DE1L176Q = DFFEAS(DE1L176Q_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--DE1L173Q is std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|epcs_slave_select_holding_reg[2]~7278 at LC_X37_Y29_N7

--operation mode is normal

DE1L173Q_lut_out = DE1_slaveselect_wr_strobe & S1_M_st_data[2] # !DE1_slaveselect_wr_strobe & (DE1L173Q);

DE1L173Q = DFFEAS(DE1L173Q_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--DE1L138Q is std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|endofpacketvalue_reg[14]~2496 at LC_X36_Y28_N6

--operation mode is normal

DE1L138Q_lut_out = DE1_endofpacketvalue_wr_strobe & (S1L2313Q) # !DE1_endofpacketvalue_wr_strobe & DE1L138Q;

DE1L138Q = DFFEAS(DE1L138Q_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--DE1L113Q is std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|endofpacketvalue_reg[4]~2497 at LC_X37_Y29_N8

--operation mode is normal

DE1L113Q_lut_out = DE1_endofpacketvalue_wr_strobe & S1_M_st_data[4] # !DE1_endofpacketvalue_wr_strobe & (DE1L113Q);

DE1L113Q = DFFEAS(DE1L113Q_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--DE1L117Q is std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|endofpacketvalue_reg[6]~2498 at LC_X39_Y29_N5

--operation mode is normal

DE1L117Q_lut_out = DE1_endofpacketvalue_wr_strobe & (S1_M_st_data[6]) # !DE1_endofpacketvalue_wr_strobe & DE1L117Q;

DE1L117Q = DFFEAS(DE1L117Q_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--DE1L115Q is std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|endofpacketvalue_reg[5]~2499 at LC_X39_Y29_N1

--operation mode is normal

DE1L115Q_lut_out = DE1_endofpacketvalue_wr_strobe & (S1_M_st_data[5]) # !DE1_endofpacketvalue_wr_strobe & DE1L115Q;

DE1L115Q = DFFEAS(DE1L115Q_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--DE1L140Q is std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|endofpacketvalue_reg[15]~2500 at LC_X36_Y29_N5

--operation mode is normal

DE1L140Q_lut_out = DE1_endofpacketvalue_wr_strobe & S1L2319Q # !DE1_endofpacketvalue_wr_strobe & (DE1L140Q);

DE1L140Q = DFFEAS(DE1L140Q_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--DE1L133Q is std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|endofpacketvalue_reg[12]~2501 at LC_X35_Y28_N5

--operation mode is normal

DE1L133Q_lut_out = DE1_endofpacketvalue_wr_strobe & S1L2301Q # !DE1_endofpacketvalue_wr_strobe & (DE1L133Q);

DE1L133Q = DFFEAS(DE1L133Q_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--DE1L111Q is std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|endofpacketvalue_reg[3]~2502 at LC_X39_Y29_N2

--operation mode is normal

DE1L111Q_lut_out = DE1_endofpacketvalue_wr_strobe & (S1_M_st_data[3]) # !DE1_endofpacketvalue_wr_strobe & DE1L111Q;

DE1L111Q = DFFEAS(DE1L111Q_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--DE1L119Q is std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|endofpacketvalue_reg[7]~2503 at LC_X39_Y29_N4

--operation mode is normal

DE1L119Q_lut_out = DE1_endofpacketvalue_wr_strobe & S1_M_st_data[7] # !DE1_endofpacketvalue_wr_strobe & (DE1L119Q);

DE1L119Q = DFFEAS(DE1L119Q_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--DE1L109Q is std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|endofpacketvalue_reg[2]~2504 at LC_X37_Y29_N5

--operation mode is normal

DE1L109Q_lut_out = DE1_endofpacketvalue_wr_strobe & S1_M_st_data[2] # !DE1_endofpacketvalue_wr_strobe & (DE1L109Q);

DE1L109Q = DFFEAS(DE1L109Q_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--DE1L106Q is std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|endofpacketvalue_reg[1]~2505 at LC_X37_Y29_N4

--operation mode is normal

DE1L106Q_lut_out = DE1_endofpacketvalue_wr_strobe & (S1_M_st_data[1]) # !DE1_endofpacketvalue_wr_strobe & DE1L106Q;

DE1L106Q = DFFEAS(DE1L106Q_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--DE1L103Q is std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|endofpacketvalue_reg[0]~2507 at LC_X39_Y29_N0

--operation mode is normal

DE1L103Q_lut_out = DE1_endofpacketvalue_wr_strobe & (S1_M_st_data[0]) # !DE1_endofpacketvalue_wr_strobe & DE1L103Q;

DE1L103Q = DFFEAS(DE1L103Q_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--DE1L121Q is std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|endofpacketvalue_reg[8]~2509 at LC_X38_Y27_N7

--operation mode is normal

DE1L121Q_lut_out = DE1_endofpacketvalue_wr_strobe & (S1L2275Q) # !DE1_endofpacketvalue_wr_strobe & DE1L121Q;

DE1L121Q = DFFEAS(DE1L121Q_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--DE1L124Q is std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|endofpacketvalue_reg[9]~2511 at LC_X35_Y27_N9

--operation mode is normal

DE1L124Q_lut_out = DE1_endofpacketvalue_wr_strobe & (S1L2281Q) # !DE1_endofpacketvalue_wr_strobe & DE1L124Q;

DE1L124Q = DFFEAS(DE1L124Q_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--DE1L127Q is std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|endofpacketvalue_reg[10]~2513 at LC_X36_Y27_N9

--operation mode is normal

DE1L127Q_lut_out = DE1_endofpacketvalue_wr_strobe & S1L2288Q # !DE1_endofpacketvalue_wr_strobe & (DE1L127Q);

DE1L127Q = DFFEAS(DE1L127Q_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--DE1L130Q is std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|endofpacketvalue_reg[11]~2515 at LC_X36_Y29_N0

--operation mode is normal

DE1L130Q_lut_out = DE1_endofpacketvalue_wr_strobe & (S1L2294Q) # !DE1_endofpacketvalue_wr_strobe & DE1L130Q;

DE1L130Q = DFFEAS(DE1L130Q_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--DE1L135Q is std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|endofpacketvalue_reg[13]~2517 at LC_X36_Y28_N1

--operation mode is normal

DE1L135Q_lut_out = DE1_endofpacketvalue_wr_strobe & (S1L2307Q) # !DE1_endofpacketvalue_wr_strobe & DE1L135Q;

DE1L135Q = DFFEAS(DE1L135Q_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--Y1L215 is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_in_a_write_cycle~3_BDD618 at LC_X29_Y26_N0

--operation mode is normal

Y1L215 = Y1L100 & (Y1L34 # Y1L37);

--DE1L21 is std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|A_WE_StdLogicVector~1138_BDD619 at LC_X36_Y26_N7

--operation mode is normal

DE1L21 = X1_cpu_data_master_requests_epcs_controller_epcs_control_port & (X1L32 & S1_ic_fill_ap_offset[1] # !X1L32 & (S1_M_alu_result[3])) # !X1_cpu_data_master_requests_epcs_controller_epcs_control_port & S1_ic_fill_ap_offset[1];

--Y1L391 is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_flash_s1_wait_counter[2]~104_BDD620 at LC_X30_Y27_N8

--operation mode is normal

Y1L391 = !Y1L770 & !Y1L122;

--Y1L393 is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_flash_s1_wait_counter[2]~105_BDD621 at LC_X30_Y27_N2

--operation mode is normal

Y1L393 = Y1_ext_flash_s1_wait_counter[1] & (Y1L387Q) # !Y1_ext_flash_s1_wait_counter[1] & (Y1L387Q & (Y1L380) # !Y1L387Q & Y1L396Q & !Y1L380);

--DE1L23 is std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|A_WE_StdLogicVector~1139_BDD622 at LC_X39_Y28_N9

--operation mode is normal

DE1L23 = X1L28 & (!DE1L222Q & !DE1L21) # !X1L28 & !DE1L111Q & (DE1L21);

--DE1L25 is std_1c20:inst|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|A_WE_StdLogicVector~1140_BDD623 at LC_X39_Y28_N6

--operation mode is normal

DE1L25 = X1L28 & (DE1L222Q & !DE1L21) # !X1L28 & DE1L111Q & (DE1L21);

--U1L256 is std_1c20:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|r_0~72_BDD624 at LC_X33_Y24_N4

--operation mode is normal

U1L256 = V1L34Q & S1L1593Q;

--Y1L467 is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_address[17]~55_BDD625 at LC_X29_Y24_N9

--operation mode is normal

Y1L467 = Y1L100 & S1_M_alu_result[17] # !Y1L100 & (S1L1593Q);

--Y1L469 is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_address[17]~56_BDD626 at LC_X29_Y24_N5

--operation mode is normal

Y1L469 = Y1L100 & (S1_M_alu_result[17] $ S1L1593Q);

--Y1L171 is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|cpu_instruction_master_continuerequest~70_BDD627 at LC_X28_Y24_N0

--operation mode is normal

Y1L171 = !Y1L736 & !Y1L916;

--Y1L174 is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|cpu_instruction_master_continuerequest~72_BDD629 at LC_X28_Y24_N4

--operation mode is normal

Y1L174 = Y1L726 & Y1L762 # !Y1L726 & (Y1L770);

--Y1L826 is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|internal_cpu_instruction_master_qualified_request_ext_ram_s1~97_BDD630 at LC_X30_Y20_N1

--operation mode is normal

Y1L826 = Y1L786Q # Y1L937 & Y1L754Q & Y1L145;

--S1L886Q is std_1c20:inst|cpu:the_cpu|E_src1_hazard_M~10 at LC_X37_Y14_N2

--operation mode is normal

S1L886Q = AMPP_FUNCTION(QC2__clk0, S1L886Q, S1_W_stall, S1L887, F1_data_out);

--Y1L937 is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|last_cycle_cpu_data_master_granted_slave_lan91c111_s1~5_DUP_COMB_DUP_COMB at LC_X31_Y20_N9

--operation mode is normal

Y1L937 = S1L1688Q & S1L1782Q & S1L209Q;

--Y1L938 is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|last_cycle_cpu_data_master_granted_slave_lan91c111_s1~5_DUP_COMB_DUP_COMB_11 at LC_X31_Y20_N7

--operation mode is normal

Y1L938 = !Y1_cpu_data_master_read_data_valid_lan91c111_s1_shift_register[1] & S1L1688Q & S1L1782Q & S1L209Q;

--Y1L939 is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|last_cycle_cpu_data_master_granted_slave_lan91c111_s1~5_DUP_COMB_DUP_COMB_12 at LC_X31_Y20_N0

--operation mode is normal

Y1L939 = Y1L754Q & S1L1688Q & S1L1782Q & S1L209Q;

--Y1L111 is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|cpu_data_master_qualified_request_lan91c111_s1~128_DUP_COMB at LC_X30_Y20_N4

--operation mode is normal

Y1L111 = Y1L938 & Y1L145 & (!Y1L820Q # !S1L1630Q);

--S1L1726Q is std_1c20:inst|cpu:the_cpu|M_alu_result[2]~_DUP_REG at LC_X38_Y15_N9

--operation mode is normal

S1L1726Q = AMPP_FUNCTION(QC2__clk0, S1L1722, S1L1724, S1L1, S1L2, F1_data_out, S1_W_stall);

--S1L1772Q is std_1c20:inst|cpu:the_cpu|M_alu_result[17]~_DUP_REG at LC_X29_Y20_N3

--operation mode is normal

S1L1772Q = AMPP_FUNCTION(QC2__clk0, S1L807, S1_E_ctrl_dst_data_sel_logic_result, A1L277, S1L17, F1_data_out, S1_E_ctrl_dst_data_sel_cmp, S1_E_ctrl_rdctl_inst, S1_W_stall);

--S1L1779Q is std_1c20:inst|cpu:the_cpu|M_alu_result[19]~_DUP_REG at LC_X33_Y18_N2

--operation mode is normal

S1L1779Q = AMPP_FUNCTION(QC2__clk0, S1_E_ctrl_dst_data_sel_logic_result, S1L809, A1L277, S1L9, F1_data_out, S1_E_ctrl_dst_data_sel_cmp, S1_E_ctrl_rdctl_inst, S1_W_stall);

--Y1L820Q is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_avalon_slave_slavearbiterlockenable~202_DUP_REG at LC_X30_Y20_N8

--operation mode is normal

Y1L820Q_lut_out = Y1L512 & Y1L813 # !Y1L512 & (Y1L1014 & (Y1L812) # !Y1L1014 & Y1L813);

Y1L820Q = DFFEAS(Y1L820Q_lut_out, GLOBAL(QC2__clk0), GLOBAL(F1_data_out), , , , , , );

--S1L1630Q is std_1c20:inst|cpu:the_cpu|ic_fill_tag[9]~157_DUP_REG at LC_X30_Y20_N9

--operation mode is normal

S1L1630Q = AMPP_FUNCTION(QC2__clk0, Y1L969, Y1L151, Y1L967, Y1L150, F1_data_out);

--S1L1602Q is std_1c20:inst|cpu:the_cpu|ic_fill_tag[6]~156_DUP_REG at LC_X30_Y20_N5

--operation mode is normal

S1L1602Q = AMPP_FUNCTION(QC2__clk0, S1L1620, S1L1591, S1L1599, S1L1504, F1_data_out);

--Y1L736 is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_avalon_slave_saved_chosen_master_vector[0]~707_DUP_COMB_758 at LC_X29_Y24_N0

--operation mode is normal

Y1L736 = Y1L112 & (Y1L28 # Y1L31);

--Y1L737 is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_avalon_slave_saved_chosen_master_vector[0]~707_DUP_COMB_760 at LC_X29_Y25_N5

--operation mode is normal

Y1L737 = Y1L112 & (Y1L28 # Y1L31);

--Y1L449 is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_address[13]~COMB_OUT_DUP_COMB at LC_X29_Y25_N7

--operation mode is normal

Y1L449 = Y1L737 & S1_M_alu_result[13] # !Y1L737 & (Y1L2 & S1_M_alu_result[13] # !Y1L2 & (S1L1577Q));

--Y1L437 is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_address[9]~COMB_OUT_DUP_COMB at LC_X25_Y26_N2

--operation mode is normal

Y1L437 = Y1L739 & (S1_M_alu_result[9]) # !Y1L739 & (Y1L2 & (S1_M_alu_result[9]) # !Y1L2 & S1_ic_fill_line[4]);

--S1L1768Q is std_1c20:inst|cpu:the_cpu|M_alu_result[16]~_DUP_REG at LC_X35_Y17_N9

--operation mode is normal

S1L1768Q = AMPP_FUNCTION(QC2__clk0, S1L806, S1_E_ctrl_dst_data_sel_logic_result, A1L277, S1L12, F1_data_out, S1_E_ctrl_dst_data_sel_cmp, S1_E_ctrl_rdctl_inst, S1_W_stall);

--S1L1765Q is std_1c20:inst|cpu:the_cpu|M_alu_result[15]~_DUP_REG at LC_X35_Y17_N3

--operation mode is normal

S1L1765Q = AMPP_FUNCTION(QC2__clk0, S1L13, S1_E_ctrl_dst_data_sel_logic_result, A1L277, S1L805, F1_data_out, S1_E_ctrl_dst_data_sel_cmp, S1_E_ctrl_rdctl_inst, S1_W_stall);

--S1L1773Q is std_1c20:inst|cpu:the_cpu|M_alu_result[17]~_DUP_REG_DUP_REG at LC_X33_Y18_N1

--operation mode is normal

S1L1773Q = AMPP_FUNCTION(QC2__clk0, S1_E_ctrl_dst_data_sel_logic_result, S1L17, A1L277, S1L807, F1_data_out, S1_E_ctrl_dst_data_sel_cmp, S1_E_ctrl_rdctl_inst, S1_W_stall);

--S1L1776Q is std_1c20:inst|cpu:the_cpu|M_alu_result[18]~_DUP_REG at LC_X33_Y18_N9

--operation mode is normal

S1L1776Q = AMPP_FUNCTION(QC2__clk0, S1_E_ctrl_dst_data_sel_logic_result, S1L808, A1L277, S1L10, F1_data_out, S1_E_ctrl_dst_data_sel_cmp, S1_E_ctrl_rdctl_inst, S1_W_stall);

--S1L1716Q is std_1c20:inst|cpu:the_cpu|M_alu_result[0]~_DUP_REG at LC_X38_Y16_N4

--operation mode is normal

S1L1716Q = AMPP_FUNCTION(QC2__clk0, S1_E_ctrl_dst_data_sel_cmp, S1L675, S1L697, F1_data_out, S1_W_stall);

--S1L1738Q is std_1c20:inst|cpu:the_cpu|M_alu_result[4]~_DUP_REG at LC_X41_Y16_N5

--operation mode is normal

S1L1738Q = AMPP_FUNCTION(QC2__clk0, S1L1734, S1L1736, S1L29, S1L30, F1_data_out, S1_W_stall);

--S1L1743Q is std_1c20:inst|cpu:the_cpu|M_alu_result[5]~_DUP_REG at LC_X39_Y18_N1

--operation mode is normal

S1L1743Q = AMPP_FUNCTION(QC2__clk0, S1L2112, S1L2114, S1L32, S1L33, F1_data_out, S1_W_stall);

--S1L235Q is std_1c20:inst|cpu:the_cpu|av_ld_or_div_done~_DUP_REG at LC_X38_Y18_N7

--operation mode is normal

S1L235Q = AMPP_FUNCTION(QC2__clk0, S1_av_ld_aligning_data, F1_data_out);

--S1L2061Q is std_1c20:inst|cpu:the_cpu|M_ctrl_shift_rot~4_DUP_REG at LC_X39_Y18_N5

--operation mode is normal

S1L2061Q = AMPP_FUNCTION(QC2__clk0, S1_W_stall, S1_E_ctrl_shift_rot, S1L2061Q, F1_data_out);

--S1L236Q is std_1c20:inst|cpu:the_cpu|av_ld_or_div_done~_DUP_REG_5 at LC_X41_Y17_N5

--operation mode is normal

S1L236Q = AMPP_FUNCTION(QC2__clk0, S1_av_ld_aligning_data, F1_data_out);

--S1L2062Q is std_1c20:inst|cpu:the_cpu|M_ctrl_shift_rot~4_DUP_REG_8 at LC_X41_Y17_N1

--operation mode is normal

S1L2062Q = AMPP_FUNCTION(QC2__clk0, S1L2062Q, S1_W_stall, S1_E_ctrl_shift_rot, F1_data_out);

--S1L1756Q is std_1c20:inst|cpu:the_cpu|M_alu_result[10]~_DUP_REG at LC_X37_Y20_N5

--operation mode is normal

S1L1756Q = AMPP_FUNCTION(QC2__clk0, S1_E_ctrl_dst_data_sel_logic_result, S1L22, A1L277, S1L800, F1_data_out, S1_E_ctrl_dst_data_sel_cmp, S1_E_ctrl_rdctl_inst, S1_W_stall);

--S1L1762Q is std_1c20:inst|cpu:the_cpu|M_alu_result[14]~_DUP_REG at LC_X33_Y17_N1

--operation mode is normal

S1L1762Q = AMPP_FUNCTION(QC2__clk0, S1L804, S1_E_ctrl_dst_data_sel_logic_result, A1L277, S1L14, F1_data_out, S1_E_ctrl_dst_data_sel_cmp, S1_E_ctrl_rdctl_inst, S1_W_stall);

--S1L1559Q is std_1c20:inst|cpu:the_cpu|ic_fill_line[6]~_DUP_REG at LC_X28_Y22_N6

--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

S1L1559Q = AMPP_FUNCTION(QC2__clk0, S1L1679, F1_data_out, GND);

--X1L10 is std_1c20:inst|epcs_controller_epcs_control_port_arbitrator:the_epcs_controller_epcs_control_port|cpu_instruction_master_qualified_request_epcs_controller_epcs_control_port~_DUP_COMB at LC_X29_Y22_N7

--operation mode is normal

X1L10 = !V1L58 & (!S1L1593Q & X1L16);

--Y1L739 is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_avalon_slave_saved_chosen_master_vector[0]~707_DUP_COMB_764 at LC_X29_Y26_N8

--operation mode is normal

Y1L739 = Y1L112 & (Y1L28 # Y1L31);

--Y1L112 is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|cpu_data_master_qualified_request_lan91c111_s1~128_DUP_COMB_133 at LC_X30_Y22_N8

--operation mode is normal

Y1L112 = Y1L145 & Y1L938 & (!Y1L820Q # !S1L1629Q);

--Y1L480 is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_address[20]~COMB_OUT_DUP_COMB_DUP_COMB at LC_X28_Y27_N4

--operation mode is normal

Y1L480 = Y1L739 # Y1L1 # S1L1609Q & !Y1L2;

--S1L1751Q is std_1c20:inst|cpu:the_cpu|M_alu_result[7]~_DUP_REG at LC_X35_Y17_N4

--operation mode is normal

S1L1751Q = AMPP_FUNCTION(QC2__clk0, S1_E_ctrl_dst_data_sel_logic_result, S1L25, A1L277, S1L797, F1_data_out, S1_E_ctrl_dst_data_sel_cmp, S1_E_ctrl_rdctl_inst, S1_W_stall);

--S1L1606 is std_1c20:inst|cpu:the_cpu|ic_fill_tag[7]~_DUP_COMB at LC_X25_Y23_N2

--operation mode is normal

S1L1606 = AMPP_FUNCTION(S1_ic_fill_tag[7], S1_M_alu_result[19], Y1L1001, Y1L1003);

--S1L1603 is std_1c20:inst|cpu:the_cpu|ic_fill_tag[6]~_DUP_COMB at LC_X25_Y23_N6

--operation mode is normal

S1L1603 = AMPP_FUNCTION(S1_M_alu_result[18], S1_ic_fill_tag[6], Y1L1001, Y1L1003);

--S1L1556 is std_1c20:inst|cpu:the_cpu|ic_fill_line[6]~_DUP_COMB at LC_X29_Y26_N2

--operation mode is normal

S1L1556 = AMPP_FUNCTION(S1_M_alu_result[11], Y1L739, Y1L2, S1L1559Q);

--S1L1687 is std_1c20:inst|cpu:the_cpu|internal_d_write~67_DUP_COMB at LC_X32_Y21_N0

--operation mode is normal

S1L1687 = AMPP_FUNCTION(S1L1685, S1L1682);

--Y1L131 is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|cpu_data_master_read_data_valid_ext_ram_s1_shift_register[0]~_DUP_COMB at LC_X33_Y25_N7

--operation mode is normal

Y1L131 = Y1L130 & Y1L104 & (Y1L51 # Y1L53);

--TE1L53 is std_1c20:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_0[45]~_DUP_COMB at LC_X18_Y23_N7

--operation mode is normal

TE1L53 = KB1_active_addr[9] $ (TE1_rd_address & (TE1_entry_1[45]) # !TE1_rd_address & TE1_entry_0[45]);

--TE1L50 is std_1c20:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_0[44]~_DUP_COMB at LC_X17_Y23_N4

--operation mode is normal

TE1L50 = KB1_active_addr[8] $ (TE1_rd_address & (TE1_entry_1[44]) # !TE1_rd_address & TE1_entry_0[44]);

--TE1L66 is std_1c20:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_0[50]~_DUP_COMB at LC_X18_Y23_N2

--operation mode is normal

TE1L66 = KB1_active_addr[14] $ (TE1_rd_address & TE1_entry_1[50] # !TE1_rd_address & (TE1_entry_0[50]));

--TE1L63 is std_1c20:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_0[49]~_DUP_COMB at LC_X17_Y23_N5

--operation mode is normal

TE1L63 = KB1_active_addr[13] $ (TE1_rd_address & TE1_entry_1[49] # !TE1_rd_address & (TE1_entry_0[49]));

--TE1L59 is std_1c20:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_0[47]~_DUP_COMB at LC_X21_Y21_N0

--operation mode is normal

TE1L59 = KB1_active_addr[11] $ (TE1_rd_address & TE1_entry_1[47] # !TE1_rd_address & (TE1_entry_0[47]));

--TE1L72 is std_1c20:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_0[52]~_DUP_COMB at LC_X17_Y21_N8

--operation mode is normal

TE1L72 = KB1_active_addr[16] $ (TE1_rd_address & TE1_entry_1[52] # !TE1_rd_address & (TE1_entry_0[52]));

--TE1L69 is std_1c20:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_0[51]~_DUP_COMB at LC_X18_Y20_N0

--operation mode is normal

TE1L69 = KB1_active_addr[15] $ (TE1_rd_address & TE1_entry_1[51] # !TE1_rd_address & (TE1_entry_0[51]));

--TE1L75 is std_1c20:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_0[53]~_DUP_COMB at LC_X17_Y20_N8

--operation mode is normal

TE1L75 = KB1_active_addr[17] $ (TE1_rd_address & TE1_entry_1[53] # !TE1_rd_address & (TE1_entry_0[53]));

--TE1L56 is std_1c20:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_0[46]~_DUP_COMB at LC_X17_Y20_N3

--operation mode is normal

TE1L56 = KB1_active_addr[10] $ (TE1_rd_address & TE1_entry_1[46] # !TE1_rd_address & (TE1_entry_0[46]));

--TE1L85 is std_1c20:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_0[56]~_DUP_COMB at LC_X17_Y20_N7

--operation mode is normal

TE1L85 = KB1_active_addr[20] $ (TE1_rd_address & (TE1_entry_1[56]) # !TE1_rd_address & TE1_entry_0[56]);

--TE1L78 is std_1c20:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_0[54]~_DUP_COMB at LC_X18_Y20_N2

--operation mode is normal

TE1L78 = KB1_active_addr[18] $ (TE1_rd_address & TE1_entry_1[54] # !TE1_rd_address & (TE1_entry_0[54]));

--TE1L81 is std_1c20:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_0[55]~_DUP_COMB at LC_X21_Y22_N0

--operation mode is normal

TE1L81 = KB1_active_addr[19] $ (TE1_rd_address & TE1_entry_1[55] # !TE1_rd_address & (TE1_entry_0[55]));

--S1L178 is std_1c20:inst|cpu:the_cpu|av_ld_data_aligned_or_div[15]~_DUP_COMB at LC_X40_Y20_N2

--operation mode is normal

S1L178 = AMPP_FUNCTION(S1L563, S1L642, S1_M_ld_align_sh16);

--S1L174 is std_1c20:inst|cpu:the_cpu|av_ld_data_aligned_or_div[14]~_DUP_COMB at LC_X40_Y20_N8

--operation mode is normal

S1L174 = AMPP_FUNCTION(S1_M_ld_align_sh16, S1L637, S1L557);

--S1L164 is std_1c20:inst|cpu:the_cpu|av_ld_data_aligned_or_div[11]~_DUP_COMB at LC_X40_Y20_N9

--operation mode is normal

S1L164 = AMPP_FUNCTION(S1L622, S1L537, S1_M_ld_align_sh16);

--S1L231 is std_1c20:inst|cpu:the_cpu|av_ld_or_div_done~_DUP_COMB at LC_X38_Y16_N8

--operation mode is normal

S1L231 = AMPP_FUNCTION(S1_av_ld_or_div_done, S1L1716Q, S1L2056Q, S1_av_ld_data_aligned_or_div[0]);

--S1L1718 is std_1c20:inst|cpu:the_cpu|M_alu_result[1]~_DUP_COMB at LC_X38_Y16_N6

--operation mode is normal

S1L1718 = AMPP_FUNCTION(S1_av_ld_or_div_done, S1_av_ld_data_aligned_or_div[1], S1L2056Q, S1_M_alu_result[1]);

--S1L2268 is std_1c20:inst|cpu:the_cpu|M_st_data[3]~_DUP_COMB at LC_X23_Y29_N2

--operation mode is normal

S1L2268 = AMPP_FUNCTION(S1_M_st_data[3], T1L433, Y1L986, Y1L995);

--S1L2265 is std_1c20:inst|cpu:the_cpu|M_st_data[2]~_DUP_COMB at LC_X23_Y29_N6

--operation mode is normal

S1L2265 = AMPP_FUNCTION(Y1L984, T1L433, S1_M_st_data[2], Y1L995);

--S1L2262 is std_1c20:inst|cpu:the_cpu|M_st_data[1]~_DUP_COMB at LC_X23_Y29_N9

--operation mode is normal

S1L2262 = AMPP_FUNCTION(S1_M_st_data[1], Y1L982, T1L433, Y1L995);

--S1L2259 is std_1c20:inst|cpu:the_cpu|M_st_data[0]~_DUP_COMB at LC_X23_Y29_N4

--operation mode is normal

S1L2259 = AMPP_FUNCTION(Y1L980, S1_M_st_data[0], T1L433, Y1L995);

--KB1L344 is std_1c20:inst|sdram:the_sdram|m_data[18]~_Duplicate_1_DUP_COMB at LC_X17_Y16_N6

--operation mode is normal

KB1L344 = KB1L948 & (KB1L947 & (KB1L961) # !KB1L947 & KB1L343Q) # !KB1L948 & KB1L343Q;

--S1L2522 is std_1c20:inst|cpu:the_cpu|W_wr_data[2]~_DUP_COMB at LC_X39_Y15_N6

--operation mode is normal

S1L2522 = AMPP_FUNCTION(S1_M_shift_rot_result[2], S1L2056Q, S1L2397);

--S1L2525 is std_1c20:inst|cpu:the_cpu|W_wr_data[3]~_DUP_COMB at LC_X39_Y16_N0

--operation mode is normal

S1L2525 = AMPP_FUNCTION(S1L2056Q, S1L2400, S1_M_shift_rot_result[3]);

--S1L2558 is std_1c20:inst|cpu:the_cpu|W_wr_data[23]~_DUP_COMB at LC_X41_Y13_N4

--operation mode is normal

S1L2558 = AMPP_FUNCTION(S1L2062Q, S1L199Q, S1_M_shift_rot_result[23]);

--S1L2537 is std_1c20:inst|cpu:the_cpu|W_wr_data[7]~_DUP_COMB at LC_X41_Y17_N4

--operation mode is normal

S1L2537 = AMPP_FUNCTION(S1L2062Q, S1_M_shift_rot_result[7], S1L2412);

--S1L2534 is std_1c20:inst|cpu:the_cpu|W_wr_data[6]~_DUP_COMB at LC_X36_Y17_N2

--operation mode is normal

S1L2534 = AMPP_FUNCTION(S1_M_shift_rot_result[6], S1L2056Q, S1L2409);

--S1L2528 is std_1c20:inst|cpu:the_cpu|W_wr_data[4]~_DUP_COMB at LC_X41_Y16_N0

--operation mode is normal

S1L2528 = AMPP_FUNCTION(S1L2062Q, S1_M_shift_rot_result[4], S1L2403);

--S1L2531 is std_1c20:inst|cpu:the_cpu|W_wr_data[5]~_DUP_COMB at LC_X39_Y18_N3

--operation mode is normal

S1L2531 = AMPP_FUNCTION(S1_M_shift_rot_result[5], S1L2406, S1L2061Q);

--S1L2517 is std_1c20:inst|cpu:the_cpu|W_wr_data[0]~_DUP_COMB at LC_X38_Y16_N5

--operation mode is normal

S1L2517 = AMPP_FUNCTION(S1_M_shift_rot_result[0], S1L2056Q, S1L231);

--S1L385 is std_1c20:inst|cpu:the_cpu|D_pc[0]~_DUP_COMB at LC_X25_Y20_N2

--operation mode is normal

S1L385 = AMPP_FUNCTION(S1L331, S1_D_pc[0], S1_D_kill, S1L1196);

--Y1L654 is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_avalon_slave_arb_addend[4]~844_DUP_COMB at LC_X31_Y24_N1

--operation mode is normal

Y1L654 = Y1L721 # !Y1L181 & (Y1L204 # Y1L372);

--Y1L750 is std_1c20:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_avalon_slave_saved_chosen_master_vector[1]~671_DUP_COMB at LC_X31_Y20_N1

--operation mode is normal

Y1L750 = Y1L711 & (Y1L755) # !Y1L711 & (Y1L746);

--S1L1504 is std_1c20:inst|cpu:the_cpu|ic_fill_ap_cnt[0]~45_DUP_COMB_69 at LC_X29_Y22_N9

--operation mode is normal

S1L1504 = AMPP_FUNCTION(S1L1526, S1_D_ic_fill_starting, S1L1501, S1L1499);

--S1L1637 is std_1c20:inst|cpu:the_cpu|ic_fill_tag[12]~65_DUP_COMB at LC_X27_Y21_N6

--operation mode is normal

S1L1637 = AMPP_FUNCTION(S1L1636Q, S1_D_ic_fill_starting, S1_D_pc[22]);

--S1L1643 is std_1c20:inst|cpu:the_cpu|ic_fill_tag[13]~67_DUP_COMB at LC_X28_Y21_N7

--operation mode is normal

S1L1643 = AMPP_FUNCTION(S1_D_pc[23], S1_D_ic_fill_starting, S1L1642Q);

--S1L1783 is std_1c20:inst|cpu:the_cpu|M_alu_result[20]~319_DUP_COMB_481 at LC_X32_Y17_N8

--operation mode is normal

S1L1783 = AMPP_FUNCTION(S1L1823, S1_E_ctrl_dst_data_sel_logic_result, S1L1795, S1L1791);

--S1L2057 is std_1c20:inst|cpu:the_cpu|M_ctrl_shift_rot~4_DUP_COMB at LC_X38_Y13_N6

--operation mode is normal

S1L2057 = AMPP_FUNCTION(S1_E_ctrl_shift_rot, S1L2056Q, S1_W_stall);

--S1L208 is std_1c20:inst|cpu:the_cpu|av_ld_data_aligned_or_div[25]~105_DUP_COMB_143 at LC_X32_Y21_N5

--operation mode is normal

S1L208 = AMPP_FUNCTION(S1L1789, S1_E_ctrl_dst_data_sel_logic_result, S1L1883, S1L1879);

--S1L1867 is std_1c20:inst|cpu:the_cpu|M_alu_result[24]~467_DUP_COMB at LC_X32_Y21_N6

--operation mode is normal

S1L1867 = AMPP_FUNCTION(S1L1789, S1_E_ctrl_dst_data_sel_logic_result, S1L1864, S1L1860);

--T1L449 is std_1c20:inst|cpu_data_master_arbitrator:the_cpu_data_master|internal_cpu_data_master_dbs_address[1]~66_DUP_COMB at LC_X32_Y21_N8

--operation mode is normal

T1L449 = S1L1789 & (S1_E_ctrl_dst_data_sel_logic_result & S1L1846 # !S1_E_ctrl_dst_data_sel_logic_result & (S1L1842)) # !S1L1789 & (S1L1846);

--S1L1575 is std_1c20:inst|cpu:the_cpu|ic_fill_tag[0]~112_DUP_COMB_164 at LC_X26_Y22_N3

--operation mode is normal

S1L1575 = AMPP_FUNCTION(S1L1526, S1_D_ic_fill_starting, S1L1501, S1L1499);

--S1L857 is std_1c20:inst|cpu:the_cpu|E_src1[4]~2047_BDD631 at LC_X40_Y16_N6

--operation mode is normal

S1L857 = AMPP_FUNCTION(S1L2062Q, S1_M_shift_rot_result[4]);

--S1L971 is std_1c20:inst|cpu:the_cpu|E_src2[13]~1599_BDD632 at LC_X37_Y19_N0

--operation mode is normal

S1L971 = AMPP_FUNCTION(S1_E_src2_imm[13], S1_E_src2_hazard_M, S1_E_ctrl_src2_is_imm, S1_E_src2_prelim[13]);

--S1L973 is std_1c20:inst|cpu:the_cpu|E_src2[13]~1600_BDD633 at LC_X37_Y19_N2

--operation mode is normal

S1L973 = AMPP_FUNCTION(S1_E_src2_imm[13], S1_E_src2_hazard_M, S1_E_ctrl_src2_is_imm, S1_E_src2_prelim[13]);

--NB1L32 is std_1c20:inst|sdram_s1_arbitrator:the_sdram_s1|internal_cpu_instruction_master_qualified_request_sdram_s1~61_BDD634 at LC_X24_Y22_N7

--operation mode is normal

NB1L32 = NB1_sdram_s1_slavearbiterlockenable & S1L1850Q & S1L1686Q;