I'm a PhD student in Alchemy Group (Architectures, Languages and Compilers to Harness the End of Moore Years) at INRIA Futurs (Saclay) (Computer Sciences Research Laboratory) under the direction of Olivier Temam.

I'm working on how to exploit available space (i.e. transistors) in future processors to get performance improvments.

Because clock speed increase seems to be really technically hard now, future processors got on chip parallelism to exploit available space (i.e. transistors) (scalability problem). Processors are going to evolve to SMT processors (Simultaneous Multi-Threading, known as HyperThreading in Intel marketing's terms) and, in a not-so-faraway future to CMP (Chip Multi Processor; typically, a chip is made of a grid of processing units).
On chip parallelism lacks of programming methods to avoid "by-hand" programming. Our group have a symbiotic approach : we add dynamic parallelism support mechanisms on chip to make compiler work easier and we express programs in a spatial way which facilitate processor decisions and compiler analyses. Currently, I conceive a programming paradigm (including languages extensions, approaches, memory and execution models) which exploits ours processor features (division threading).