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Contrat de l'équipe Architectures parallèles


HIPEAC 2

Contrat europeen
Févr. 2008 - Janv. 2012

Equipe : Architectures parallèles
Responsable : 

Gestionnaire : 
Organisme gérant : INRIA

European Network of Excellence on High Performance and Embedded Architecture and Compilation

Due to technology limitations, the domain of high-performance processors is experiencing a radical shift towards parallelism through on-chip multi-cores and chip customization, leading to heterogeneous multi-core systems. Furthermore, the commodity market, the supercomputing market and the embedded market are increasingly sharing the same challenges, leading to convergence of the three markets.

Core objectives of HiPEAC

Research coordination Research coordination in HiPEAC is done in 9 clusters, each dealing with a specific part of the HiPEAC research agenda. Clusters are formed by researchers from industry and academia interested in the topic of the cluster. Clusters continuously update their research agenda, and steer the European research by deciding on which challenges to tackle and by coordinating the research efforts of the cluster members.

Collaboration and networking Stimulate joint research between member institutions, across the different disciplines: computer architects, design tool builders, compiler builders, system designers, between researchers from academia and industry, between European and non-European institutions. This collaboration between best of breed must lead to more European excellence in the HiPEAC domain.

Valorisation Stimulate valorisation of research results in the form of highly visible publications and commercialization of research results by existing companies or by newly created companies. The goal is to further increase Europe’s worldwide visibility in the HiPEAC domain and to help companies to achieve world-leading positions in the computing systems and computing products.

Activités de recherche
  Architecture
  Compilation

Membres LRI


Pour en savoir plus : http://www.hipeac.net
Contrats
° IUF
FABIO MARTIGNON
SUBVENTION

° DIGISCOPE UPS
INFRASTRUCTURE HAUTE PERFORMANCE POUR LA VISUALISATION INTERACTIVE ET COLLABORATIVE
ANR

° DIGISCOPE CNRS
INFRASTRUCTURE HAUTE PERFORMANCE POUR LA VISUALISATION INTERACTIVE ET COLLABORATIVE
ANR

° ATOS/BULL
CONTRAT ATOS/BULL
INDUSTRIEL

° LCHIP
LCHIP