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Improving Cache and Memory Performance in Multicore Architectures.
Govindarajan Ramaswamy

20 June 2013, 10h00 - 20 June 2013, 11h30
Salle/Bat : 445/PCRI-N
Contact : govind@serc.iisc.in

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Résumé :
Title: Improving Cache and Memory Performance in Multicore Architectures.

Abstract: In this talk we will present our recent work on improving the memory subsystem performance in a multi-core architecture. In particular, we will talk about techniques for improving the last-level cache performance and Memory (DRAM) performance, especially for multiprogrammed environment. First, we discuss PriSM, our Probabilistic Shared cache Management framework which provides an efficient mechanism for fine-grain management of Last-Level Cache to achieve various performance objectives such as hit-maximization, fairness or quality of service. Next we present a simple analytical model for estimating memory system performance. We validate the analytical model and discuss how it could be used for memory system design space exploration.

Biography: Govindarajan Ramaswamy received his B.Sc. degree in Mathematics from Madras University in 1981 and B.E. (Electronics and Communication) and Ph.D. (Computer Science) degrees from the Indian Institute of Science, Bangalore in 1984 and 1989 respectively. He has held postdoctoral research positions and visiting faculty positions at Universities in USA and Canada. Since 1995, he has been with the Supercomputer Education and Research Centre and the Department of Computer Science and Automation, Indian Institute of Science, Bangalore. Currently he is a professor and the chairman of the Supercomputer Education and Research Centre. His research interests are in the areas of High Performance Computing, Compilation Techniques, and Computer Architecture.

Pour en savoir plus : http://www.serc.iisc.ernet.in/~govind/
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