Involution Delay Model: Faithful Delay Prediction in Digital Circuits
Jürgen Maier

25 July 2017, 14:00 Salle/Bat : 465/PCRI-N
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Résumé :

Rapid developements in circuit design over the last decades have not only led to an increased performance at lower area requirements but also increased the complexity to accurately model the signal traces, such that analog simulation tools like SPICE nowadays quickly reach their limit with increasing size. Therefore high level approaches, which abstract certain parts of the circuit, are required to achieve a reasonable computational effort while still maintaining an adequate accuracy.

In this talk I will present our digital involution delay model that faithfully predicts signal delays in electronic circuits. Faithful in this sense means that a circuit can only be modelled if it can be implemented in actual hardware and vice versa. The delay of a single transition is determined as a function f(T) with T being the previous-output-to-input transition time difference and f(.) an involution, i.e., fulfilling -f(-f(T)) = T. Compared to the established pure and inertial delay our approach allows accurate modeling of pulse degradation effects, which become very important for example for power estimations.

Despite the good results we already achieved the model is far from being finished. I will therefore also present some extensions we are currently investigating such as introducing non-determinism, reducing the characterization effort or increasing the accuracy.