Publications (2000-2017)

Refereed international journals

  1. A. Tran Tan, J. Falcou,  D. Etiemble,  H. Kayser, "Automatic  Task-based Code Generation  for High Performance Domain  Specific Embedded  Language",  International Journal of Parallel  Programming", 44(3), 449-465, 2016.

  2. F Laguzet, A Romero, M Gouiffès, L Lacassagne, D Etiemble, “Color tracking with contextual switching: real-time implementation on CPU”, Journal of Real-Time Image Processing 10 (2), 403-422, 2015

  3. L. Cabaret, L. Lacassagne, D. Etiemble, Parallel Light Speed Labeling: an efficient connected component algorithm for labeling and analysis on multi-core processors”, Journal of Real-Time Image Processing, (Springer Verlag) (2016)

  4. K. Hamidouche, F. M. Mendonca, J. Falcou, A. C. M. Alves de Melo & D. Etiemble, "Parallel Smith-Waterman Comparison on Multicore and Manycore Computing Platforms with BSP++", International Journal of Parallel Computing, 2012, 10.1007/s10766-012-0209-6
  5. D. Etiemble, “Why M-Valued Circuits are restricted to a Small Niche”, in Journal of Multiple Valued Logic and Soft Computing, Volume 9, N°1, 2003. 

  6. D. Etiemble, "Computer Arithmetic and hardware: "off the shelves" microprocessors versus custom hardware", Theorical Computer Science, Volume 279, 1-2, May 2002

  7. F. Cappello, O. Richard , D. Etiemble, "Understanding performance of SMP clusters running MPI programs" in Future Generation Computer Systems, 17 (6) (2001) pp. 711-720

Refereed international conferences.

  1. L. Cabaret, L. Lacassagne, D. Etiemble : “Distanceless Label Propagation: an Efficient Direct Connected Component Labeling Algorithm for GPUs”, International Conference on Image Processing Theory, Tools and Application (IPTA), Montreal, Canada (2017).
  2. L. Lacassagne, L. Cabaret, D. Etiemble, F. Hebbache, A. Petreto: “A new SIMD iterative connected component labeling algorithm”, Principles and Practice of Parallel Programming / WVMVP, Barcelone, Spain (2016)
  3. L. Cabaret, L. Lacassagne, D. Etiemble, « Parallel Light Speed Labeling: an Efficient Connected Component Labeling Algorithm for Multi-Core Processors”, in IEEE International Conference on Image Processing (ICIP 2015), Quebec, Canada. 
  4. A. Tran Tan, J. Falcou, D. Etiemble and H. Kaiser, “Automatic Task-based Code Generation for High Performance Domain Specific Embedded Language”, International Symposium on High-level Parallel Programming and Applications (HLPP), July 2014, Amsterdam, Netherlands.
  5. H Ye, Lionel Lacassagne, Daniel Etiemble, L Cabaret, Joel Falcou, Andrés Romero, O Florent, “ Impact of high level transforms on high level synthesis for motion detection algorithm”, Conference on Design and Architectures for Signal and Image Processing (DASIP), 2012, pp 1-8.
  6. C. Bechara, A. Berhault, N. Ventroux, C. Chevobbe, Y. Thuillier, R. David and D. Etiemble, “A Small Footprint Interleaved Processor for Embedded Systems”, in Proc. International Conference on Electronics, Circuits and Systems (ICECS), December 2011, Beirut, Lebanon.
  7. F. Laguzet, M. Gouiffes, L.Lacassagne and D. Etiemble, “'Automatic Color Space Switching for Robust Tracking'”, in Proc. International Conference on Signal and Image Processing Applications (ICSIPA 2011), November 2011, Kuala Lampur, Malaysia.
  8. W. S. Zhao, Y. Zhang, Y. Lakys, J-O. Klein, D. Etiemble, D. Revelosona , C. Chappert, L. Torres, L. V. Cargnini, R. M. Brum, Y. Guillemenet and G. Sassatelli, « Embedded MRAM for High-speed Computing” in Proc. VLSI-SOC, October 2011, Hong Kong, China  
  9. K. Hamidouche, F.M. Mendonca, J. Falcou and D. Etiemble, « Parallel biological sequence comparison on heterogeneous high performance platforms with BSP++ », Proc. SBAC-PAD, October 2011, Vitoria, Brazil. 
  10. C. Bechara, N. Ventroux and D. Etiemble, “Comparison of different thread scheduling strategies for Asymmetric Chip MultiThreading architectures in embedded systems”, Proc. Euromicro Conference on DIGITAL SYSTEM DESIGN DSD 2011), August – September 2011, Oulu, Finland
  11. K. Hamidouche, J. Falcou, D. Etiemble, “A Framework for an Automatic Hybrid MPI+OpenMP code generation”, HPC 2011,  19th High Performance Computing Symposium, April 2011, Boston 
  12. C. Bechara, N. Ventroux and D. Etiemble, “Towards a parameterizable cycle-accurate ISS in ArchC”, AICCSA 2010, ACS/IEEE International Conference on Computer Systems and Applications; May 2010, Hammamet, Tunisia.
  13. T. Saidani, J. Falcou, C. Tadonki, L. Lacassagne and D. Etiemble, "Algorithmic Skeletons within an Embedded Domain Specific Language for the CELL Processor", Proc. PACT 2009, Raleigh, September 2009
  14. L. Duflot, D. Etiemble and O. Grumelard, "Using CPU Management Mode to Circumvent Operating System Security Functions", in Proc. CanSecWest 2006, Vancouver, Canada 
  15. S. Piskorski, L. Lacassagne, M. Kieffer and D. Etiemble, "Efficient 16-bit floating point interval processor for embedded system and applications", Proc. SCAN 2006, Duisburg, Germany
  16. L. Lacassagne, D. Etiemble and S.A. Ould Kablia, "16-bit floating point instructions for embedded multimedia applications", in Proc. CAMP2005, Palermo, Italy, July 2005
  17. D. Etiemble and L. Lacassagne, “16-bit FP sub-word parallelism to facilitate compiler vectorization and improve performance of image and media processing", Proc. ICPP-2004, Montreal, Canada, August 2004
  18. D. Etiemble, "Optimizing DSP and media benchmarks for Pentium 4: hardware and software issues" in IEEE International Conference on Multimedia and Expo (ICME2002), Lausanne, Switzerland, August 26-29 2002
  19. D. Etiemble, “Numerical applications and sub-word parallelism: The NAS benchmarks on a Pentium 4”, in 16th Annual International Symposium on High Performance Computing Systems and Applications (HPCS’2002),” Moncton, NB, Canada, June 17-19, 2002
  20. F. Cappello and D. Etiemble, "MPI versus MPI+OpenMP on IBM SP for the NAS Benchmarks", in Proc. Supercomputing 2000 (SC2000), Dallas, November 2000.