From 1969 to 1983, as assistant professor, I worked successively
From 1983 to 1985, member of CAD and VLSI research group within MASI laboratory in Paris 6. VLSI design and CAD tools (electrical simulation). Beginning of comparative study of performance of integrated technologies (speed, power dissipation, chip area).
From 1986 to 1988, chairman of the research group on "Architecture and Circuits for Artificial Intelligence" within MASI laboratories. This group had two projects that were sponsored by the Silicon Integrated Circuit consortium of CNRS (French national research institute)
a) Models of performance and comparison of integrated high speed technologies.
Comparison of integrated high speed technologies examines the impact of physical features, geometrical features (design rules), circuit styles and design methodologies on the overall performance of benchmark circuits (speed, power dissipation, chip area). Silicon (MOS and BJT) and GaAs (MESFET and HBT) were considered. Several contracts were signed with LETI-CEA, THOMSON DCI et SDC, CNET Bagneux, SGS-Thomson Grenoble, and collaborations were developed with IBM Corbeil Essonnes. Five Ph. D. thesis corresponded to these works between 1987 and 1990. The results are summarized in a chapter of a book " High Speed Digital Integrated Circuits " edited (ARTECH) by Marc Rocchi, from LEP(Philips).
b) Design of a VLSI Data Base Processor (RAPID)
During this joined project with the Data Base group of MASI, a VLSI Data Base processor was designed and implemented. The project was sponsored by CNRS. It was based on a highly parallel coprocessor, which instruction set included a relational algebra extended to sorts and aggregates.
Since 1988, I have been chairman of the "Computer Architecture" group (called Parallel Architecture" group since 1994) within LRI laboratory.
From 1988 to 1994, my research interests have been focused on two aspects:
a) Massively parallel architecture
From 1988 to 1990, I was leader with J-P Sansonnet for the MEGA project (massively parallel architecture for AI applications). This project included the feasibility of an asynchronous message passing MIMD architecture with up to 1-million CPUs. It was based on an original framework of single chip CPUs on a 3-D grid and used "forced" routing (C. Germain’s thesis). The single chip CPU was carefully designed and evaluated. Poor performance of the used execution model (asynchronous fine grain MIMD) experimented by implementing an actor language and a functional language were the reasons to stop the project.
From 1990 to 1994, I have been responsible for the PTAH project on a parallel machine based on a statically controlled communication network. The corresponding applications were high-end numerical computing. The following aspects have been extensively examined:
b) Technology impact on architectures and performance.
The goal of this work is modeling the CPUs (computation), memory hierarchies and interconnection networks (bandwidth and latency) performance according to fundamental physical and technological parameters (such as channel length of MOS transistors). The objective is understanding the trends in the performance of each component to define new "balanced" architectures according to fundamental parameters. One objective is to forecast the long term evolution faced to the announced limits of CMOS technologies. In the context of high speed technologies, we have compared performance of CMOS and BiCMOS technologies within an European project called CANDI in cooperation with SGS-Thomson (now called ST). CMOS and BiCMOS cells of the 2901 slice processor have been designed, fabricated and tested. We also considered some design alternatives, such as multivalued current mode circuits. These experiments have led to interesting results with arithmetic circuits, that have been published in the IEEE Symposium on Computer Arithmetic.
MEGA and PTAH projects have been supported by the National Coordinate Program in Computer Architecture (PRC-GDR ANM) and the French army (DRET). Microelectronics activities have been supported by CNRS (GDR GCIS).
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From 1994 to 1998, I have been working on performance evaluation of desktop PCs in the framework of a contract with a Hewlett Packard division in Grenoble in charge of designing desktop PCs for HP. We have developed techniques for evaluating the impact of the basic components (CPU, caches and MM, video, disks, networks) on the overall performance and for detecting the bottlenecks on desktop PC benchmarks. The results include
In the last part of the cooperation, during my 3-month stay in HP Labs in Palo Alto, I have developed a technique to detect graphics bottlenecks by using Perftool package, which is an improved version of Windows NT Perfmon developed by HP-Grenoble and EPFL in Lausanne.
I have had a sabbatical year from October 1998 to September 1999. I have spent 3 months in HP Labs and one month in South America (1 week in Porto Alegre university, Brazil and 3 weeks in Buenos Aires University, Argentina).
Due to financial cutoffs in HP, the division with which I was working in Grenoble has been disbanded. In 1999-2000, I worked with F. Cappello on performance evaluation of clusters of multiprocessor PCs for numerical applications and specially on comparing performance of the different programming models on these architectures that combine message passing and shared memory.