--****-- --======================================================-- -- LIBRARIES -- --======================================================-- -- IEEE Libraries -- library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_arith.all; use IEEE.std_logic_unsigned.all; --use IEEE.std_logic_signed.all; library work; --use work.float_pkg.all; entity mixcolumn is port ( dataa : in std_logic_vector(31 downto 0); result : out std_logic_vector(31 downto 0) ); end mixcolumn; ---------------------------------------------------------- -- AES Mixcolumn -- ---------------------------------------------------------- architecture comp of mixcolumn is signal a,b,c,d,e, ab,bc,cd, da, aa, bb, cc, dd, t0,t1,t2,t3 : std_logic_vector(7 downto 0); begin a<= dataa(7 downto 0); b<=dataa(15 downto 8); c<= dataa(23 downto 16); d<= dataa(31 downto 24); e<= a xor b xor c xor d; ab <= a xor b; bc <= b xor c; cd <= c xor d; da <= d xor a; t0<= ab(6 downto 0)&'0';--aa(0)<='0'; aa <= t0 xor "00011011" when (ab(7)='1') else t0; t1<= bc(6 downto 0)&'0';--aa(0)<='0'; bb <= t1 xor "00011011" when (bc(7)='1') else t1; t2<= cd(6 downto 0)&'0';--aa(0)<='0'; cc <= t2 xor "00011011" when (cd(7)='1') else t2; t3<= da(6 downto 0)&'0';--aa(0)<='0'; dd <= t3 xor "00011011" when (da(7)='1') else t3; result (7 downto 0)<= a xor e xor aa; result (15 downto 8)<= b xor e xor bb; result (23 downto 16)<= c xor e xor cc; result (31 downto 24)<= d xor e xor dd; end comp; -- end of architecture --======================================================-- --** ARCHITECTURE ENDS **-- --======================================================--